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Posted to commits@mynewt.apache.org by je...@apache.org on 2023/04/03 06:45:15 UTC
[mynewt-core] 02/03: bsp/nucleo-l073rz: Change PLL settings
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 2889699304ce6605a63a7972d306c128bae2f539
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Fri Mar 31 19:56:16 2023 +0200
bsp/nucleo-l073rz: Change PLL settings
PLL settings are now changed to generate 48MHz clock
usable for USB without need for HSI48.
---
hw/bsp/nucleo-l073rz/syscfg.yml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/bsp/nucleo-l073rz/syscfg.yml b/hw/bsp/nucleo-l073rz/syscfg.yml
index 1512e892c..01cabc90c 100644
--- a/hw/bsp/nucleo-l073rz/syscfg.yml
+++ b/hw/bsp/nucleo-l073rz/syscfg.yml
@@ -47,8 +47,9 @@ syscfg.vals:
STM32_CLOCK_HSI48: 0
STM32_CLOCK_HSE: 0
STM32_CLOCK_HSE_BYPASS: 0
- STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL4' # 16 * 4 = 64MHz
- STM32_CLOCK_PLL_DIV: 'RCC_PLL_DIV2' # 64 / 2 = 32MHz
+ STM32_CLOCK_HSI_DIV4: 1 # HSI/4 = 4MHz
+ STM32_CLOCK_PLL_MUL: RCC_PLL_MUL24 # 4 * 24 = 96MHz
+ STM32_CLOCK_PLL_DIV: RCC_PLL_DIV3 # 96 / 3 = 32MHz
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'