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Posted to commits@harmony.apache.org by "Naumova Natalya (JIRA)" <ji...@apache.org> on 2007/08/12 15:13:43 UTC
[jira] Created: (HARMONY-4621) Stack misalignment when using SSE
instructions
Stack misalignment when using SSE instructions
----------------------------------------------
Key: HARMONY-4621
URL: https://issues.apache.org/jira/browse/HARMONY-4621
Project: Harmony
Issue Type: Improvement
Components: DRLVM
Reporter: Naumova Natalya
This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
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[jira] Commented: (HARMONY-4621) [drlvm][jit] Stack misalignment
when using SSE instructions
Posted by "Evgueni Brevnov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#action_12541033 ]
Evgueni Brevnov commented on HARMONY-4621:
------------------------------------------
Thanks, Alexey. Yes, you are right, it makes sense to think about more convinient way of setting required alignment. At least we definitly should specify it in one place for JIT and OPT.
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Commented: (HARMONY-4621) [drlvm][jit] Stack misalignment
when using SSE instructions
Posted by "Evgueni Brevnov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#action_12536661 ]
Evgueni Brevnov commented on HARMONY-4621:
------------------------------------------
As you pointed out there are three different areas where we may want to allign on 16-byte boundary.
1) Local values.
2) Spilled values.
3) Input values.
In spite of common part each area reqires its own implementation. Could you answer to the following questions...
Do you have any ideas which area is worth to start with?
Do we need to support all three cases? (I personally think that the last one is not strongly required).
Is it possible to provide a test case we want to optimize?
Thanks
Evgueni
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Commented: (HARMONY-4621) [drlvm][jit] Stack misalignment
when using SSE instructions
Posted by "Evgueni Brevnov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#action_12542717 ]
Evgueni Brevnov commented on HARMONY-4621:
------------------------------------------
I just noticed the following lines in stackalignment_part2.patch
+ // TODO: remove before commit
+ assert((stackSizeAlignment & 15) == 0);
Plz, remove this code before commit.
Thanks
Evgueni
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch, stackalign_part2.patch, stackalign_part2.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Updated: (HARMONY-4621) [drlvm][jit] Stack misalignment when
using SSE instructions
Posted by "Gregory Shimansky (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Gregory Shimansky updated HARMONY-4621:
---------------------------------------
Summary: [drlvm][jit] Stack misalignment when using SSE instructions (was: Stack misalignment when using SSE instructions)
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Updated: (HARMONY-4621) [drlvm][jit] Stack misalignment when
using SSE instructions
Posted by "Evgueni Brevnov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Evgueni Brevnov updated HARMONY-4621:
-------------------------------------
Attachment: stackalign_part2.patch
I've updated stackalign_part2.patch. It fixes regression introduced by stackalign_part1.patch on Windows EM64T. Actually the same problem existed for Linux EM64T as well.
Thanks
Evgueni
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch, stackalign_part2.patch, stackalign_part2.patch, stackalign_part2.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Assigned: (HARMONY-4621) [drlvm][jit] Stack misalignment
when using SSE instructions
Posted by "Alexey Varlamov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Alexey Varlamov reassigned HARMONY-4621:
----------------------------------------
Assignee: Alexey Varlamov
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Updated: (HARMONY-4621) [drlvm][jit] Stack misalignment when
using SSE instructions
Posted by "Evgueni Brevnov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Evgueni Brevnov updated HARMONY-4621:
-------------------------------------
Attachment: stackalign_part2.patch
Update stackalign_part.patch. Resolved performance problems with the spec.
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch, stackalign_part2.patch, stackalign_part2.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Resolved: (HARMONY-4621) [drlvm][jit] Stack misalignment
when using SSE instructions
Posted by "Alexey Varlamov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Alexey Varlamov resolved HARMONY-4621.
--------------------------------------
Resolution: Fixed
Applied at revision: 595300.
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch, stackalign_part2.patch, stackalign_part2.patch, stackalign_part2.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Updated: (HARMONY-4621) [drlvm][jit] Stack misalignment when
using SSE instructions
Posted by "Evgueni Brevnov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Evgueni Brevnov updated HARMONY-4621:
-------------------------------------
Attachment: stackalign_part1.patch
This is the first step to have aligned local values. In particular attached patch aligns stack pointer on 16byte boundary on ia32 platfrom. It also fixes number of misconfigurations in helper calling conventions. The patch was tested on Lin/Win x86 and Lin x86_64 by 'build test'. I managed to build and partially test it on Win x86_64 due to problems with environment.
Thanks
Evgueni
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Attachments: stackalign_part1.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Commented: (HARMONY-4621) [drlvm][jit] Stack misalignment
when using SSE instructions
Posted by "Alexey Varlamov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#action_12541026 ]
Alexey Varlamov commented on HARMONY-4621:
------------------------------------------
Oh, another king-size patch. Generally looks good, I only spotted mistyped define in jit_runtime_support_common.h:
#define STACK_ALIGN4 (0x00000008)
BTW, related defines are duplicated thrice, in both JITs and in VM stubs. Moreover, seems there appears conceptual binding, i.e. alignment should be coherent in VM and JIT. Indeed this may worth explicit and more articulated interface, need to think about this?
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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[jira] Updated: (HARMONY-4621) [drlvm][jit] Stack misalignment when
using SSE instructions
Posted by "Evgueni Brevnov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Evgueni Brevnov updated HARMONY-4621:
-------------------------------------
Attachment: stackalign_part2.patch
Here is the second patch which alignes local memory operands on 16-bytes if they are used in SSE instruction. This patch is under performance testing now...so we need to know the results before commit.
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch, stackalign_part2.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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-
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[jira] Commented: (HARMONY-4621) [drlvm][jit] Stack misalignment
when using SSE instructions
Posted by "Alexey Varlamov (JIRA)" <ji...@apache.org>.
[ https://issues.apache.org/jira/browse/HARMONY-4621?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel#action_12541029 ]
Alexey Varlamov commented on HARMONY-4621:
------------------------------------------
Applied the patch at revision: 593136.
> [drlvm][jit] Stack misalignment when using SSE instructions
> -----------------------------------------------------------
>
> Key: HARMONY-4621
> URL: https://issues.apache.org/jira/browse/HARMONY-4621
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Naumova Natalya
> Assignee: Alexey Varlamov
> Attachments: stackalign_part1.patch
>
>
> This issue is related with stack misalignment: data must be 16-bytes aligned when loading and storing on 128bit xmm registers, it increases the performance of SSE usage. Now we have misalign local variables, and stack register (esp). Then we have a penalty from using xmm registers. Can we do some optimization for better SSE using, e.g. 16-bytes allignment of esp and all local variables?
--
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