[incubator-nuttx] branch master updated (370152f3ba -> f5cf35784e)

[xi...@apache.org]

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xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git


    from 370152f3ba RISC-V: Move mhartid to own assembly macro+function
     new 898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register
     new f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler

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Summary of changes:
 arch/risc-v/src/common/riscv_misaligned.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

[incubator-nuttx] 02/02: arch/risc-v: Correct format of 32-bit insn in misaligned handler

[xi...@apache.org]

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git

commit f5cf35784e5a13ea66376deffcffa9cd9a388c86
Author: Huang Qi <hu...@xiaomi.com>
AuthorDate: Wed Apr 13 16:25:18 2022 +0800

    arch/risc-v: Correct format of 32-bit insn in misaligned handler
    
    FIx:
    Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')
    
    Signed-off-by: Huang Qi <hu...@xiaomi.com>
---
 arch/risc-v/src/common/riscv_misaligned.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/risc-v/src/common/riscv_misaligned.c b/arch/risc-v/src/common/riscv_misaligned.c
index 4358dfe64f..3c3f8431eb 100644
--- a/arch/risc-v/src/common/riscv_misaligned.c
+++ b/arch/risc-v/src/common/riscv_misaligned.c
@@ -447,7 +447,7 @@ static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx)
       case INSN_FSD:
         _alert("Misaligned float instruction not support yet\n");
       default:
-        _alert("Uncompressed: %lx\n", insn.insn);
+        _alert("Uncompressed: %x\n", insn.insn);
         return false;
     }
 

[incubator-nuttx] 01/02: arch/risc-v/riscv_misaligned: Correct sw source register

[xi...@apache.org]

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git

commit 898d789a5fd604550178c36cc7061cab3e0da9c6
Author: Huang Qi <hu...@xiaomi.com>
AuthorDate: Wed Apr 13 16:22:54 2022 +0800

    arch/risc-v/riscv_misaligned: Correct sw source register
    
    If source register of sw instruction is x0, we must point it to a constant zero
    since in NuttX's context,
    value of index 0 is EPC.
    
    Signed-off-by: Huang Qi <hu...@xiaomi.com>
---
 arch/risc-v/src/common/riscv_misaligned.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/risc-v/src/common/riscv_misaligned.c b/arch/risc-v/src/common/riscv_misaligned.c
index 54148f0f4b..4358dfe64f 100644
--- a/arch/risc-v/src/common/riscv_misaligned.c
+++ b/arch/risc-v/src/common/riscv_misaligned.c
@@ -363,6 +363,7 @@ static bool decode_insn_compressed(uintptr_t *regs, riscv_insn_ctx_t *ctx)
 
 static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx)
 {
+  static const uintptr_t x0;
   uint32_t in;
   int32_t imm;
   riscv_insn_t insn;
@@ -418,7 +419,17 @@ static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx)
         imm = sext(insn.s.imm2 | insn.s.imm1 << 5, 12);
 
         ctx->dest = (uint8_t *)regs[insn.s.rs1] + imm;
-        ctx->src = (uint8_t *)&regs[insn.s.rs2];
+
+        /* If source register is x0, target it to constant register */
+
+        if (insn.s.rs2 == 0)
+          {
+            ctx->src = (uint8_t *)&x0;
+          }
+        else
+          {
+            ctx->src = (uint8_t *)&regs[insn.s.rs2];
+          }
 
         /* Get data wide bit */