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Posted to commits@mynewt.apache.org by ma...@apache.org on 2017/04/03 17:55:12 UTC
[1/3] incubator-mynewt-core git commit: pic32 port,
soft floating point only, kernel mode only
Repository: incubator-mynewt-core
Updated Branches:
refs/heads/develop a73a65bfc -> ab16b5db1
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/mips/danube/include/mcu/mips_bsp.h
----------------------------------------------------------------------
diff --git a/hw/mcu/mips/danube/include/mcu/mips_bsp.h b/hw/mcu/mips/danube/include/mcu/mips_bsp.h
index 01d75f4..67c16e8 100644
--- a/hw/mcu/mips/danube/include/mcu/mips_bsp.h
+++ b/hw/mcu/mips/danube/include/mcu/mips_bsp.h
@@ -21,4 +21,4 @@
extern const struct hal_flash native_flash_dev;
-#endif /* H_NATIVE_BSP_ */
+#endif /* H_MIPS_BSP_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/mips/danube/include/mcu/mips_hal.h
----------------------------------------------------------------------
diff --git a/hw/mcu/mips/danube/include/mcu/mips_hal.h b/hw/mcu/mips/danube/include/mcu/mips_hal.h
index f407e0c..74426cf 100644
--- a/hw/mcu/mips/danube/include/mcu/mips_hal.h
+++ b/hw/mcu/mips/danube/include/mcu/mips_hal.h
@@ -35,4 +35,4 @@ extern "C" {
}
#endif
-#endif /* MCU_HAL_H */
+#endif /* MIPS_HAL_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/mips/danube/src/hal_uart.c
----------------------------------------------------------------------
diff --git a/hw/mcu/mips/danube/src/hal_uart.c b/hw/mcu/mips/danube/src/hal_uart.c
index 7509fed..9729f0c 100644
--- a/hw/mcu/mips/danube/src/hal_uart.c
+++ b/hw/mcu/mips/danube/src/hal_uart.c
@@ -118,7 +118,7 @@ hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
static void
uart_irq_handler(int port)
{
- uint8_t lsr = uart_reg_read(1, CR_UART_LSR);
+ uint8_t lsr = uart_reg_read(port, CR_UART_LSR);
if (lsr & CR_UART_LSR_RXFER) {
/* receive error */
if (lsr & CR_UART_LSR_BI) {
@@ -201,6 +201,9 @@ hal_uart_start_tx(int port)
void
hal_uart_blocking_tx(int port, uint8_t data)
{
+ /* wait for transmit holding register to be empty */
+ while(!(uart_reg_read(port, CR_UART_LSR) & CR_UART_LSR_THRE)) {
+ }
/* write to transmit holding register */
uart_reg_write(port, CR_UART_RBR_THR_DLL, data);
/* wait for transmit holding register to be empty */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/include/os/arch/mips/os/os_arch.h
----------------------------------------------------------------------
diff --git a/kernel/os/include/os/arch/mips/os/os_arch.h b/kernel/os/include/os/arch/mips/os/os_arch.h
index 33afcee..91cd40e 100644
--- a/kernel/os/include/os/arch/mips/os/os_arch.h
+++ b/kernel/os/include/os/arch/mips/os/os_arch.h
@@ -77,4 +77,4 @@ void os_default_irq_asm(void);
void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio);
void os_bsp_ctx_sw(void);
-#endif /* _OS_ARCH_ARM_H */
+#endif /* _OS_ARCH_MIPS_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/include/os/arch/pic32mx/os/os_arch.h
----------------------------------------------------------------------
diff --git a/kernel/os/include/os/arch/pic32mx/os/os_arch.h b/kernel/os/include/os/arch/pic32mx/os/os_arch.h
new file mode 100644
index 0000000..5cd30ff
--- /dev/null
+++ b/kernel/os/include/os/arch/pic32mx/os/os_arch.h
@@ -0,0 +1,84 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _OS_ARCH_PIC32MX_H
+#define _OS_ARCH_PIC32MX_H
+
+#include <stdint.h>
+#include <xc.h>
+
+// is this req'd? It seems a little odd to include up the tree
+#include "mcu/pic32mx470.h"
+
+struct os_task;
+
+/* Run in priviliged or unprivileged Thread mode */
+/* only priv currently supported */
+#define OS_RUN_PRIV (0)
+#define OS_RUN_UNPRIV (1)
+
+/* CPU status register */
+typedef uint32_t os_sr_t;
+/* Stack type, aligned to a 32-bit word. */
+#define OS_STACK_PATTERN (0xdeadbeef)
+
+typedef uint32_t os_stack_t;
+#define OS_ALIGNMENT (4)
+#define OS_STACK_ALIGNMENT (8)
+
+#define OS_SR_IPL_BITS (0xE0)
+
+/*
+ * Stack sizes for common OS tasks
+ */
+#define OS_SANITY_STACK_SIZE (64)
+#define OS_IDLE_STACK_SIZE (64)
+
+#define OS_STACK_ALIGN(__nmemb) \
+ (OS_ALIGN((__nmemb), OS_STACK_ALIGNMENT))
+
+/* Enter a critical section, save processor state, and block interrupts */
+#define OS_ENTER_CRITICAL(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+/* Exit a critical section, restore processor state and unblock interrupts */
+#define OS_EXIT_CRITICAL(__os_sr) __builtin_set_isr_state(__os_sr)
+/* This is not the only way interrupts can be disabled */
+#define OS_IS_CRITICAL() ((__builtin_get_isr_state() & 1) == 0)
+#define OS_ASSERT_CRITICAL() assert(OS_IS_CRITICAL())
+
+os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int);
+void timer_handler(void);
+void os_arch_ctx_sw(struct os_task *);
+os_sr_t os_arch_save_sr(void);
+void os_arch_restore_sr(os_sr_t);
+int os_arch_in_critical(void);
+void os_arch_init(void);
+uint32_t os_arch_start(void);
+os_error_t os_arch_os_init(void);
+os_error_t os_arch_os_start(void);
+void os_set_env(os_stack_t *);
+void os_arch_init_task_stack(os_stack_t *sf);
+void os_default_irq_asm(void);
+
+/* External function prototypes supplied by BSP */
+void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio);
+void os_bsp_ctx_sw(void);
+
+#endif /* _OS_ARCH_PIC32MX_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/include/os/arch/pic32mz/os/os_arch.h
----------------------------------------------------------------------
diff --git a/kernel/os/include/os/arch/pic32mz/os/os_arch.h b/kernel/os/include/os/arch/pic32mz/os/os_arch.h
new file mode 100644
index 0000000..bf3017f
--- /dev/null
+++ b/kernel/os/include/os/arch/pic32mz/os/os_arch.h
@@ -0,0 +1,84 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef _OS_ARCH_PIC32MZ_H
+#define _OS_ARCH_PIC32MZ_H
+
+#include <stdint.h>
+#include <xc.h>
+
+// is this req'd? It seems a little odd to include up the tree
+#include "mcu/pic32mz2048.h"
+
+struct os_task;
+
+/* Run in priviliged or unprivileged Thread mode */
+/* only priv currently supported */
+#define OS_RUN_PRIV (0)
+#define OS_RUN_UNPRIV (1)
+
+/* CPU status register */
+typedef uint32_t os_sr_t;
+/* Stack type, aligned to a 32-bit word. */
+#define OS_STACK_PATTERN (0xdeadbeef)
+
+typedef uint32_t os_stack_t;
+#define OS_ALIGNMENT (4)
+#define OS_STACK_ALIGNMENT (8)
+
+#define OS_SR_IPL_BITS (0xE0)
+
+/*
+ * Stack sizes for common OS tasks
+ */
+#define OS_SANITY_STACK_SIZE (64)
+#define OS_IDLE_STACK_SIZE (64)
+
+#define OS_STACK_ALIGN(__nmemb) \
+ (OS_ALIGN((__nmemb), OS_STACK_ALIGNMENT))
+
+/* Enter a critical section, save processor state, and block interrupts */
+#define OS_ENTER_CRITICAL(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+/* Exit a critical section, restore processor state and unblock interrupts */
+#define OS_EXIT_CRITICAL(__os_sr) __builtin_set_isr_state(__os_sr)
+/* This is not the only way interrupts can be disabled */
+#define OS_IS_CRITICAL() ((__builtin_get_isr_state() & 1) == 0)
+#define OS_ASSERT_CRITICAL() assert(OS_IS_CRITICAL())
+
+os_stack_t *os_arch_task_stack_init(struct os_task *, os_stack_t *, int);
+void timer_handler(void);
+void os_arch_ctx_sw(struct os_task *);
+os_sr_t os_arch_save_sr(void);
+void os_arch_restore_sr(os_sr_t);
+int os_arch_in_critical(void);
+void os_arch_init(void);
+uint32_t os_arch_start(void);
+os_error_t os_arch_os_init(void);
+os_error_t os_arch_os_start(void);
+void os_set_env(os_stack_t *);
+void os_arch_init_task_stack(os_stack_t *sf);
+void os_default_irq_asm(void);
+
+/* External function prototypes supplied by BSP */
+void os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio);
+void os_bsp_ctx_sw(void);
+
+#endif /* _OS_ARCH_PIC32MZ_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/src/arch/mips/asm/excpt_isr.S
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/mips/asm/excpt_isr.S b/kernel/os/src/arch/mips/asm/excpt_isr.S
index dded29c..ee8e4e7 100644
--- a/kernel/os/src/arch/mips/asm/excpt_isr.S
+++ b/kernel/os/src/arch/mips/asm/excpt_isr.S
@@ -70,9 +70,6 @@ AENT(__isr_vec_fallback)
.set pop
END(__isr_vec)
-/* XXX: these are all pointelss, if there was a way to detect if a symbol is
- defined elsewhere it could be fixed .ifdef does not seem to work for this */
-
.text
.weak _mips_isr_sw1
_mips_isr_sw1:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/src/arch/mips/os_arch_mips.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/mips/os_arch_mips.c b/kernel/os/src/arch/mips/os_arch_mips.c
index d1d7401..bdc9e5e 100644
--- a/kernel/os/src/arch/mips/os_arch_mips.c
+++ b/kernel/os/src/arch/mips/os_arch_mips.c
@@ -44,7 +44,8 @@ extern struct os_task g_idle_task;
void __attribute__((interrupt, keep_interrupts_masked))
_mips_isr_hw5(void)
{
- mips_setcompare(mips_getcompare() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
+ mips_setcompare(mips_getcompare() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) /
+ OS_TICKS_PER_SEC));
timer_handler();
}
@@ -150,9 +151,6 @@ os_arch_start(void)
t = os_sched_next_task();
/* set the core timer compare register */
- /* XXX: take this magic number (for a 1ms tick from a 546MHz clock) and put
- ** it in bsp or mcu somewhere
- */
mips_setcompare(mips_getcount() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
/* global interrupt enable */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/src/arch/pic32mx/asm/ctx.S
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mx/asm/ctx.S b/kernel/os/src/arch/pic32mx/asm/ctx.S
new file mode 100644
index 0000000..e14c131
--- /dev/null
+++ b/kernel/os/src/arch/pic32mx/asm/ctx.S
@@ -0,0 +1,163 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <xc.h>
+
+#define CTX_SIZE (35*4)
+#define CTX_EPC (31*4)
+#define CTX_BADVADDR (32*4)
+#define CTX_STATUS (33*4)
+#define CTX_CAUSE (34*4)
+
+# note that k0 is not saved when using these macros.
+# The cause register is saved but not resored.
+
+# saves to location k0
+.macro _gpctx_save
+ sw $1, 0(k0)
+ sw $2, 4(k0)
+ sw $3, 8(k0)
+ sw $4, 12(k0)
+ sw $5, 16(k0)
+ sw $6, 20(k0)
+ sw $7, 24(k0)
+ sw $8, 28(k0)
+ sw $9, 32(k0)
+ sw $10, 36(k0)
+ sw $11, 40(k0)
+ sw $12, 44(k0)
+ sw $13, 48(k0)
+ sw $14, 52(k0)
+ sw $15, 56(k0)
+ sw $16, 60(k0)
+ sw $17, 64(k0)
+ sw $18, 68(k0)
+ sw $19, 72(k0)
+ sw $20, 76(k0)
+ sw $21, 80(k0)
+ sw $22, 84(k0)
+ sw $23, 88(k0)
+ sw $24, 92(k0)
+ sw $25, 96(k0)
+ # k0 not saved
+ sw $27, 104(k0)
+ sw $28, 108(k0)
+ sw $29, 112(k0)
+ sw $30, 116(k0)
+ sw $31, 120(k0)
+
+ # cp0
+ sw ra, CTX_EPC(k0)
+ mfc0 $9, _CP0_BADVADDR /* PTR_MFC0? */
+ sw $9, CTX_BADVADDR(k0)
+ mfc0 $9, _CP0_STATUS
+ sw $9, CTX_STATUS(k0)
+ mfc0 $9, _CP0_CAUSE
+ sw $9, CTX_CAUSE(k0)
+
+.endm
+
+# restores from location a0
+
+.macro _gpctx_load
+ lw $1, 0(a0)
+ lw $2, 4(a0)
+ lw $3, 8(a0)
+ # a0 is loaded last
+ lw $5, 16(a0)
+ lw $6, 20(a0)
+ lw $7, 24(a0)
+ lw $8, 28(a0)
+ lw $9, 32(a0)
+ lw $10, 36(a0)
+ lw $11, 40(a0)
+ lw $12, 44(a0)
+ lw $13, 48(a0)
+ lw $14, 52(a0)
+ lw $15, 56(a0)
+ lw $16, 60(a0)
+ lw $17, 64(a0)
+ lw $18, 68(a0)
+ lw $19, 72(a0)
+ lw $20, 76(a0)
+ lw $21, 80(a0)
+ lw $22, 84(a0)
+ lw $23, 88(a0)
+ lw $24, 92(a0)
+ lw $25, 96(a0)
+ # restore k0 after interrupts have been disabled
+ lw $27, 104(a0)
+ lw $28, 108(a0)
+ # restore sp after interrupts have been disabled
+ lw $30, 116(a0)
+ lw $31, 120(a0)
+
+ di
+ lw k0, CTX_EPC(a0)
+ mtc0 k0, _CP0_EPC
+ lw k0, CTX_STATUS(a0)
+ # STATUS here will have EXL set
+ mtc0 k0, _CP0_STATUS
+ ehb
+
+ # restore k0 and sp as these may be overwritten by nested interrupts
+ lw $26, 100(a0)
+ lw $29, 112(a0)
+ # restore a0 last
+ lw $4, 12(a0)
+.endm
+
+.text
+.global get_global_pointer
+.ent get_global_pointer
+get_global_pointer:
+ .set noat
+ move v0, gp
+ jr ra
+.end
+
+.text
+.global isr_sw0
+.ent isr_sw0
+isr_sw0:
+ # context switch
+ .set noat
+ rdpgpr sp, sp
+ # save k0 as its not saved in ctx_switch, hardcode values for now
+ sw $26, ((25 * 4) - ((((CTX_SIZE - 1) / 8) + 1) * 8))(sp)
+ addi k0, sp, -((((CTX_SIZE - 1) / 8) + 1) * 8)
+ _gpctx_save # save the context
+ .set at
+ lw t0, g_current_task # get current task
+ beqz t0, 1f
+ sw k0, 0(t0) # update stored sp
+1:
+ lw t1, g_os_run_list # get new task
+ sw t1, g_current_task # g_current_task = g_os_run_list
+
+ li k0, _IFS0_CS0IF_MASK
+ sw k0, IFS0CLR
+
+ lw a0, 0(t1)
+ .set noat
+ _gpctx_load # updates actual sp
+ wrpgpr sp, sp
+
+ eret
+.end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/src/arch/pic32mx/os_arch_pic32mx.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mx/os_arch_pic32mx.c b/kernel/os/src/arch/pic32mx/os_arch_pic32mx.c
new file mode 100644
index 0000000..0dbddcc
--- /dev/null
+++ b/kernel/os/src/arch/pic32mx/os_arch_pic32mx.c
@@ -0,0 +1,213 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "os/os.h"
+#include "os/os_arch.h"
+#include "syscfg/syscfg.h"
+#include <hal/hal_bsp.h>
+#include <hal/hal_os_tick.h>
+
+#include "os_priv.h"
+
+#include <string.h>
+
+extern void SVC_Handler(void);
+extern void PendSV_Handler(void);
+extern void SysTick_Handler(void);
+
+struct ctx {
+ uint32_t regs[31];
+ uint32_t epc;
+ uint32_t badvaddr;
+ uint32_t status;
+ uint32_t cause;
+};
+
+/* XXX: determine how to deal with running un-privileged */
+/* only priv currently supported */
+uint32_t os_flags = OS_RUN_PRIV;
+
+extern struct os_task g_idle_task;
+
+/* core timer interrupt */
+void __attribute__((interrupt(IPL1AUTO),
+vector(_CORE_TIMER_VECTOR))) isr_core_timer(void)
+{
+ timer_handler();
+ _CP0_SET_COMPARE(_CP0_GET_COMPARE() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
+ IFS0CLR = _IFS0_CTIF_MASK;
+}
+
+/* context switch interrupt, in ctx.S */
+void __attribute__((interrupt(IPL1AUTO),
+vector(_CORE_SOFTWARE_0_VECTOR))) isr_sw0(void);
+
+static int
+os_in_isr(void)
+{
+ /* check the EXL bit */
+ return (_CP0_GET_STATUS() & _CP0_STATUS_EXL_MASK) ? 1 : 0;
+}
+
+void
+timer_handler(void)
+{
+ os_time_advance(1);
+}
+
+void
+os_arch_ctx_sw(struct os_task *t)
+{
+ if ((os_sched_get_current_task() != 0) && (t != 0)) {
+ os_sched_ctx_sw_hook(t);
+ }
+
+ IFS0SET = _IFS0_CS0IF_MASK;
+}
+
+os_sr_t
+os_arch_save_sr(void)
+{
+ os_sr_t sr;
+ OS_ENTER_CRITICAL(sr);
+ return sr;
+}
+
+void
+os_arch_restore_sr(os_sr_t isr_ctx)
+{
+ OS_EXIT_CRITICAL(isr_ctx);
+}
+
+int
+os_arch_in_critical(void)
+{
+ return OS_IS_CRITICAL();
+}
+
+uint32_t get_global_pointer(void);
+
+/* assumes stack_top will be 8 aligned */
+
+os_stack_t *
+os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
+{
+ os_stack_t *s = stack_top - ((((sizeof(struct ctx) - 1) /
+ OS_STACK_ALIGNMENT) + 1) * 2);
+
+ struct ctx ctx;
+
+ ctx.regs[3] = (uint32_t)t->t_arg;
+ ctx.regs[27] = get_global_pointer();
+ ctx.regs[28] = (uint32_t)(stack_top - 4);
+ ctx.status = _CP0_GET_STATUS() | _CP0_STATUS_IE_MASK;
+ ctx.cause = _CP0_GET_CAUSE();
+ ctx.epc = (uint32_t)t->t_func;
+ /* copy struct onto the stack */
+ memcpy(s, &ctx, sizeof(ctx));
+
+ return (s);
+}
+
+void
+os_arch_init(void)
+{
+ os_init_idle_task();
+}
+
+os_error_t
+os_arch_os_init(void)
+{
+ os_error_t err;
+
+ err = OS_ERR_IN_ISR;
+ if (os_in_isr() == 0) {
+ err = OS_OK;
+ os_sr_t sr;
+ OS_ENTER_CRITICAL(sr);
+
+ _CP0_BIC_STATUS(_CP0_STATUS_IPL_MASK);
+ /* multi vector mode */
+ INTCONSET = _INTCON_MVEC_MASK;
+ /* vector spacing 0x20 */
+ _CP0_SET_INTCTL(_CP0_GET_INTCTL() | (1 << _CP0_INTCTL_VS_POSITION));
+
+ /* enable core timer interrupt */
+ IEC0SET = _IEC0_CTIE_MASK;
+ /* set interrupt priority */
+ IPC0CLR = _IPC0_CTIP_MASK;
+ IPC0SET = (1 << _IPC0_CTIP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC0CLR = _IPC0_CTIS_MASK;
+ IPC0SET = (0 << _IPC0_CTIS_POSITION); // subpriority 0
+
+ /* enable software interrupt 0 */
+ IEC0SET = _IEC0_CS0IE_MASK;
+ /* set interrupt priority */
+ IPC0CLR = _IPC0_CS0IP_MASK;
+ IPC0SET = (1 << _IPC0_CS0IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC0CLR = _IPC0_CS0IS_MASK;
+ IPC0SET = (0 << _IPC0_CS0IS_POSITION); // subpriority 0
+
+ OS_EXIT_CRITICAL(sr);
+
+ /* should be in kernel mode here */
+ os_arch_init();
+ }
+ return err;
+}
+
+uint32_t
+os_arch_start(void)
+{
+ struct os_task *t;
+
+ /* Get the highest priority ready to run to set the current task */
+ t = os_sched_next_task();
+
+ /* set the core timer compare register */
+ _CP0_SET_COMPARE(_CP0_GET_COUNT() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
+
+ /* global interrupt enable */
+ __builtin_enable_interrupts();
+
+ /* Mark the OS as started, right before we run our first task */
+ g_os_started = 1;
+
+ /* Perform context switch to first task */
+ os_arch_ctx_sw(t);
+
+ return (uint32_t)(t->t_arg);
+}
+
+os_error_t
+os_arch_os_start(void)
+{
+ os_error_t err;
+
+ err = OS_OK; // OS_ERR_IN_ISR
+ if (os_in_isr() == 0) {
+ err = OS_OK;
+ /* should be in kernel mode here */
+ os_arch_start();
+ }
+
+ return err;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/src/arch/pic32mx/os_fault.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mx/os_fault.c b/kernel/os/src/arch/pic32mx/os_fault.c
new file mode 100644
index 0000000..5dc952a
--- /dev/null
+++ b/kernel/os/src/arch/pic32mx/os_fault.c
@@ -0,0 +1,122 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <console/console.h>
+#include <hal/hal_system.h>
+#ifdef COREDUMP_PRESENT
+#include <coredump/coredump.h>
+#endif
+#include "os/os.h"
+
+#include <stdint.h>
+#include <unistd.h>
+
+struct exception_frame {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+struct trap_frame {
+ struct exception_frame *ef;
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t lr; /* this LR holds EXC_RETURN */
+};
+
+struct coredump_regs {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t r12;
+ uint32_t sp;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+#ifdef COREDUMP_PRESENT
+static void
+trap_to_coredump(struct trap_frame *tf, struct coredump_regs *regs)
+{
+}
+#endif
+
+void
+__assert_func(const char *file, int line, const char *func, const char *e)
+{
+ int sr;
+
+ OS_ENTER_CRITICAL(sr);
+ (void)sr;
+ console_blocking_mode();
+ console_printf("Assert @ 0x%x\n",
+ (unsigned int)__builtin_return_address(0));
+ if (hal_debugger_connected()) {
+ /*
+ * If debugger is attached, breakpoint before the trap.
+ */
+ }
+ hal_system_reset();
+}
+
+void
+os_default_irq(struct trap_frame *tf)
+{
+#ifdef COREDUMP_PRESENT
+ struct coredump_regs regs;
+#endif
+
+ console_blocking_mode();
+ console_printf("Unhandled interrupt, exception sp 0x%08lx\n",
+ (uint32_t)tf->ef);
+ console_printf(" r0:0x%08lx r1:0x%08lx r2:0x%08lx r3:0x%08lx\n",
+ tf->ef->r0, tf->ef->r1, tf->ef->r2, tf->ef->r3);
+ console_printf(" r4:0x%08lx r5:0x%08lx r6:0x%08lx r7:0x%08lx\n",
+ tf->r4, tf->r5, tf->r6, tf->r7);
+ console_printf(" r8:0x%08lx r9:0x%08lx r10:0x%08lx r11:0x%08lx\n",
+ tf->r8, tf->r9, tf->r10, tf->r11);
+ console_printf("r12:0x%08lx lr:0x%08lx pc:0x%08lx psr:0x%08lx\n",
+ tf->ef->r12, tf->ef->lr, tf->ef->pc, tf->ef->psr);
+#ifdef COREDUMP_PRESENT
+ trap_to_coredump(tf, ®s);
+ coredump_dump(®s, sizeof(regs));
+#endif
+ hal_system_reset();
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/src/arch/pic32mz/asm/ctx.S
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mz/asm/ctx.S b/kernel/os/src/arch/pic32mz/asm/ctx.S
new file mode 100644
index 0000000..0793952
--- /dev/null
+++ b/kernel/os/src/arch/pic32mz/asm/ctx.S
@@ -0,0 +1,163 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <xc.h>
+
+#define CTX_SIZE (35*4)
+#define CTX_EPC (31*4)
+#define CTX_BADVADDR (32*4)
+#define CTX_STATUS (33*4)
+#define CTX_CAUSE (34*4)
+
+# note that k0 is not saved when using these macros.
+# The cause register is saved but not resored.
+
+# saves to location k0
+.macro _gpctx_save
+ sw $1, 0(k0)
+ sw $2, 4(k0)
+ sw $3, 8(k0)
+ sw $4, 12(k0)
+ sw $5, 16(k0)
+ sw $6, 20(k0)
+ sw $7, 24(k0)
+ sw $8, 28(k0)
+ sw $9, 32(k0)
+ sw $10, 36(k0)
+ sw $11, 40(k0)
+ sw $12, 44(k0)
+ sw $13, 48(k0)
+ sw $14, 52(k0)
+ sw $15, 56(k0)
+ sw $16, 60(k0)
+ sw $17, 64(k0)
+ sw $18, 68(k0)
+ sw $19, 72(k0)
+ sw $20, 76(k0)
+ sw $21, 80(k0)
+ sw $22, 84(k0)
+ sw $23, 88(k0)
+ sw $24, 92(k0)
+ sw $25, 96(k0)
+ # k0 not saved
+ sw $27, 104(k0)
+ sw $28, 108(k0)
+ sw $29, 112(k0)
+ sw $30, 116(k0)
+ sw $31, 120(k0)
+
+ # cp0
+ sw ra, CTX_EPC(k0)
+ mfc0 $9, _CP0_BADVADDR /* PTR_MFC0? */
+ sw $9, CTX_BADVADDR(k0)
+ mfc0 $9, _CP0_STATUS
+ sw $9, CTX_STATUS(k0)
+ mfc0 $9, _CP0_CAUSE
+ sw $9, CTX_CAUSE(k0)
+
+.endm
+
+# restores from location a0
+
+.macro _gpctx_load
+ lw $1, 0(a0)
+ lw $2, 4(a0)
+ lw $3, 8(a0)
+ # a0 is loaded last
+ lw $5, 16(a0)
+ lw $6, 20(a0)
+ lw $7, 24(a0)
+ lw $8, 28(a0)
+ lw $9, 32(a0)
+ lw $10, 36(a0)
+ lw $11, 40(a0)
+ lw $12, 44(a0)
+ lw $13, 48(a0)
+ lw $14, 52(a0)
+ lw $15, 56(a0)
+ lw $16, 60(a0)
+ lw $17, 64(a0)
+ lw $18, 68(a0)
+ lw $19, 72(a0)
+ lw $20, 76(a0)
+ lw $21, 80(a0)
+ lw $22, 84(a0)
+ lw $23, 88(a0)
+ lw $24, 92(a0)
+ lw $25, 96(a0)
+ # restore k0 after interrupts have been disabled
+ lw $27, 104(a0)
+ lw $28, 108(a0)
+ # restore sp after interrupts have been disabled
+ lw $30, 116(a0)
+ lw $31, 120(a0)
+
+ di
+ lw k0, CTX_EPC(a0)
+ mtc0 k0, _CP0_EPC
+ lw k0, CTX_STATUS(a0)
+ # STATUS here will have EXL set
+ mtc0 k0, _CP0_STATUS
+ ehb
+
+ # restore k0 and sp as these may be overwritten by nested interrupts
+ lw $26, 100(a0)
+ lw $29, 112(a0)
+ # restore a0 last
+ lw $4, 12(a0)
+.endm
+
+.text
+.global get_global_pointer
+.ent get_global_pointer
+get_global_pointer:
+ .set noat
+ move v0, gp
+ jr ra
+.end
+
+.text
+.global isr_sw0
+.ent isr_sw0
+isr_sw0:
+ # context switch
+ .set noat
+ rdpgpr sp, sp
+ # save k0 as its not saved in ctx_switch, hardcode values for now
+ sw $26, ((25 * 4) - ((((CTX_SIZE - 1) / 8) + 1) * 8))(sp)
+ addi k0, sp, -((((CTX_SIZE - 1) / 8) + 1) * 8)
+ _gpctx_save # save the context
+ .set at
+ lw t0, g_current_task # get current task
+ beqz t0, 1f
+ sw k0, 0(t0) # update stored sp
+1:
+ lw t1, g_os_run_list # get new task
+ sw t1, g_current_task # g_current_task = g_os_run_list
+
+ li k0, _IFS0_CS0IF_MASK
+ sw k0, IFS0CLR
+
+ lw a0, 0(t1)
+ .set noat
+ _gpctx_load # updates actual sp
+ wrpgpr sp, sp
+
+ eret
+.end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/src/arch/pic32mz/os_arch_pic32mz.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mz/os_arch_pic32mz.c b/kernel/os/src/arch/pic32mz/os_arch_pic32mz.c
new file mode 100644
index 0000000..0dbddcc
--- /dev/null
+++ b/kernel/os/src/arch/pic32mz/os_arch_pic32mz.c
@@ -0,0 +1,213 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "os/os.h"
+#include "os/os_arch.h"
+#include "syscfg/syscfg.h"
+#include <hal/hal_bsp.h>
+#include <hal/hal_os_tick.h>
+
+#include "os_priv.h"
+
+#include <string.h>
+
+extern void SVC_Handler(void);
+extern void PendSV_Handler(void);
+extern void SysTick_Handler(void);
+
+struct ctx {
+ uint32_t regs[31];
+ uint32_t epc;
+ uint32_t badvaddr;
+ uint32_t status;
+ uint32_t cause;
+};
+
+/* XXX: determine how to deal with running un-privileged */
+/* only priv currently supported */
+uint32_t os_flags = OS_RUN_PRIV;
+
+extern struct os_task g_idle_task;
+
+/* core timer interrupt */
+void __attribute__((interrupt(IPL1AUTO),
+vector(_CORE_TIMER_VECTOR))) isr_core_timer(void)
+{
+ timer_handler();
+ _CP0_SET_COMPARE(_CP0_GET_COMPARE() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
+ IFS0CLR = _IFS0_CTIF_MASK;
+}
+
+/* context switch interrupt, in ctx.S */
+void __attribute__((interrupt(IPL1AUTO),
+vector(_CORE_SOFTWARE_0_VECTOR))) isr_sw0(void);
+
+static int
+os_in_isr(void)
+{
+ /* check the EXL bit */
+ return (_CP0_GET_STATUS() & _CP0_STATUS_EXL_MASK) ? 1 : 0;
+}
+
+void
+timer_handler(void)
+{
+ os_time_advance(1);
+}
+
+void
+os_arch_ctx_sw(struct os_task *t)
+{
+ if ((os_sched_get_current_task() != 0) && (t != 0)) {
+ os_sched_ctx_sw_hook(t);
+ }
+
+ IFS0SET = _IFS0_CS0IF_MASK;
+}
+
+os_sr_t
+os_arch_save_sr(void)
+{
+ os_sr_t sr;
+ OS_ENTER_CRITICAL(sr);
+ return sr;
+}
+
+void
+os_arch_restore_sr(os_sr_t isr_ctx)
+{
+ OS_EXIT_CRITICAL(isr_ctx);
+}
+
+int
+os_arch_in_critical(void)
+{
+ return OS_IS_CRITICAL();
+}
+
+uint32_t get_global_pointer(void);
+
+/* assumes stack_top will be 8 aligned */
+
+os_stack_t *
+os_arch_task_stack_init(struct os_task *t, os_stack_t *stack_top, int size)
+{
+ os_stack_t *s = stack_top - ((((sizeof(struct ctx) - 1) /
+ OS_STACK_ALIGNMENT) + 1) * 2);
+
+ struct ctx ctx;
+
+ ctx.regs[3] = (uint32_t)t->t_arg;
+ ctx.regs[27] = get_global_pointer();
+ ctx.regs[28] = (uint32_t)(stack_top - 4);
+ ctx.status = _CP0_GET_STATUS() | _CP0_STATUS_IE_MASK;
+ ctx.cause = _CP0_GET_CAUSE();
+ ctx.epc = (uint32_t)t->t_func;
+ /* copy struct onto the stack */
+ memcpy(s, &ctx, sizeof(ctx));
+
+ return (s);
+}
+
+void
+os_arch_init(void)
+{
+ os_init_idle_task();
+}
+
+os_error_t
+os_arch_os_init(void)
+{
+ os_error_t err;
+
+ err = OS_ERR_IN_ISR;
+ if (os_in_isr() == 0) {
+ err = OS_OK;
+ os_sr_t sr;
+ OS_ENTER_CRITICAL(sr);
+
+ _CP0_BIC_STATUS(_CP0_STATUS_IPL_MASK);
+ /* multi vector mode */
+ INTCONSET = _INTCON_MVEC_MASK;
+ /* vector spacing 0x20 */
+ _CP0_SET_INTCTL(_CP0_GET_INTCTL() | (1 << _CP0_INTCTL_VS_POSITION));
+
+ /* enable core timer interrupt */
+ IEC0SET = _IEC0_CTIE_MASK;
+ /* set interrupt priority */
+ IPC0CLR = _IPC0_CTIP_MASK;
+ IPC0SET = (1 << _IPC0_CTIP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC0CLR = _IPC0_CTIS_MASK;
+ IPC0SET = (0 << _IPC0_CTIS_POSITION); // subpriority 0
+
+ /* enable software interrupt 0 */
+ IEC0SET = _IEC0_CS0IE_MASK;
+ /* set interrupt priority */
+ IPC0CLR = _IPC0_CS0IP_MASK;
+ IPC0SET = (1 << _IPC0_CS0IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC0CLR = _IPC0_CS0IS_MASK;
+ IPC0SET = (0 << _IPC0_CS0IS_POSITION); // subpriority 0
+
+ OS_EXIT_CRITICAL(sr);
+
+ /* should be in kernel mode here */
+ os_arch_init();
+ }
+ return err;
+}
+
+uint32_t
+os_arch_start(void)
+{
+ struct os_task *t;
+
+ /* Get the highest priority ready to run to set the current task */
+ t = os_sched_next_task();
+
+ /* set the core timer compare register */
+ _CP0_SET_COMPARE(_CP0_GET_COUNT() + ((MYNEWT_VAL(CLOCK_FREQ) / 2) / 1000));
+
+ /* global interrupt enable */
+ __builtin_enable_interrupts();
+
+ /* Mark the OS as started, right before we run our first task */
+ g_os_started = 1;
+
+ /* Perform context switch to first task */
+ os_arch_ctx_sw(t);
+
+ return (uint32_t)(t->t_arg);
+}
+
+os_error_t
+os_arch_os_start(void)
+{
+ os_error_t err;
+
+ err = OS_OK; // OS_ERR_IN_ISR
+ if (os_in_isr() == 0) {
+ err = OS_OK;
+ /* should be in kernel mode here */
+ os_arch_start();
+ }
+
+ return err;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/kernel/os/src/arch/pic32mz/os_fault.c
----------------------------------------------------------------------
diff --git a/kernel/os/src/arch/pic32mz/os_fault.c b/kernel/os/src/arch/pic32mz/os_fault.c
new file mode 100644
index 0000000..5dc952a
--- /dev/null
+++ b/kernel/os/src/arch/pic32mz/os_fault.c
@@ -0,0 +1,122 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <console/console.h>
+#include <hal/hal_system.h>
+#ifdef COREDUMP_PRESENT
+#include <coredump/coredump.h>
+#endif
+#include "os/os.h"
+
+#include <stdint.h>
+#include <unistd.h>
+
+struct exception_frame {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+struct trap_frame {
+ struct exception_frame *ef;
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t lr; /* this LR holds EXC_RETURN */
+};
+
+struct coredump_regs {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t r12;
+ uint32_t sp;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+#ifdef COREDUMP_PRESENT
+static void
+trap_to_coredump(struct trap_frame *tf, struct coredump_regs *regs)
+{
+}
+#endif
+
+void
+__assert_func(const char *file, int line, const char *func, const char *e)
+{
+ int sr;
+
+ OS_ENTER_CRITICAL(sr);
+ (void)sr;
+ console_blocking_mode();
+ console_printf("Assert @ 0x%x\n",
+ (unsigned int)__builtin_return_address(0));
+ if (hal_debugger_connected()) {
+ /*
+ * If debugger is attached, breakpoint before the trap.
+ */
+ }
+ hal_system_reset();
+}
+
+void
+os_default_irq(struct trap_frame *tf)
+{
+#ifdef COREDUMP_PRESENT
+ struct coredump_regs regs;
+#endif
+
+ console_blocking_mode();
+ console_printf("Unhandled interrupt, exception sp 0x%08lx\n",
+ (uint32_t)tf->ef);
+ console_printf(" r0:0x%08lx r1:0x%08lx r2:0x%08lx r3:0x%08lx\n",
+ tf->ef->r0, tf->ef->r1, tf->ef->r2, tf->ef->r3);
+ console_printf(" r4:0x%08lx r5:0x%08lx r6:0x%08lx r7:0x%08lx\n",
+ tf->r4, tf->r5, tf->r6, tf->r7);
+ console_printf(" r8:0x%08lx r9:0x%08lx r10:0x%08lx r11:0x%08lx\n",
+ tf->r8, tf->r9, tf->r10, tf->r11);
+ console_printf("r12:0x%08lx lr:0x%08lx pc:0x%08lx psr:0x%08lx\n",
+ tf->ef->r12, tf->ef->lr, tf->ef->pc, tf->ef->psr);
+#ifdef COREDUMP_PRESENT
+ trap_to_coredump(tf, ®s);
+ coredump_dump(®s, sizeof(regs));
+#endif
+ hal_system_reset();
+}
[3/3] incubator-mynewt-core git commit: This closes #218.
Posted by ma...@apache.org.
This closes #218.
Merge branch 'pic32' of https://github.com/IMGJulian/incubator-mynewt-core into develop
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/ab16b5db
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/ab16b5db
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/ab16b5db
Branch: refs/heads/develop
Commit: ab16b5db18fa81e749c33a12cfe79265e873df8e
Parents: a73a65b 70bf4a8
Author: Marko Kiiskila <ma...@runtime.io>
Authored: Mon Apr 3 10:51:42 2017 -0700
Committer: Marko Kiiskila <ma...@runtime.io>
Committed: Mon Apr 3 10:51:42 2017 -0700
----------------------------------------------------------------------
compiler/xc32/compiler.yml | 36 ++
compiler/xc32/pkg.yml | 27 +
hw/bsp/pic32mx470_6LP_clicker/bsp.yml | 53 ++
hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h | 52 ++
.../include/bsp/bsp_sysid.h | 36 ++
hw/bsp/pic32mx470_6LP_clicker/pkg.yml | 46 ++
hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c | 27 +
hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c | 85 +++
hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c | 51 ++
hw/bsp/pic32mx470_6LP_clicker/syscfg.yml | 41 ++
hw/bsp/pic32mz2048_wi-fire/bsp.yml | 53 ++
hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp.h | 52 ++
.../pic32mz2048_wi-fire/include/bsp/bsp_sysid.h | 36 ++
hw/bsp/pic32mz2048_wi-fire/pkg.yml | 52 ++
hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c | 27 +
hw/bsp/pic32mz2048_wi-fire/src/os_bsp.c | 109 ++++
hw/bsp/pic32mz2048_wi-fire/src/sbrk.c | 51 ++
hw/bsp/pic32mz2048_wi-fire/syscfg.yml | 49 ++
.../pic32mx470F512H/include/mcu/mips_bsp.h | 24 +
.../pic32mx470F512H/include/mcu/mips_hal.h | 39 ++
.../pic32mx470F512H/include/mcu/pic32mx470.h | 25 +
hw/mcu/microchip/pic32mx470F512H/pkg.yml | 31 +
.../microchip/pic32mx470F512H/src/hal_os_tick.c | 36 ++
.../microchip/pic32mx470F512H/src/hal_system.c | 35 +
hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c | 463 +++++++++++++
.../pic32mx470F512H/src/hal_watchdog.c | 39 ++
.../pic32mz2048efg100/include/mcu/mips_bsp.h | 24 +
.../pic32mz2048efg100/include/mcu/mips_hal.h | 39 ++
.../pic32mz2048efg100/include/mcu/pic32mz2048.h | 25 +
hw/mcu/microchip/pic32mz2048efg100/pkg.yml | 31 +
.../pic32mz2048efg100/src/hal_os_tick.c | 36 ++
.../pic32mz2048efg100/src/hal_system.c | 35 +
.../microchip/pic32mz2048efg100/src/hal_uart.c | 645 +++++++++++++++++++
.../pic32mz2048efg100/src/hal_watchdog.c | 39 ++
hw/mcu/mips/danube/include/mcu/mips.h | 2 +-
hw/mcu/mips/danube/include/mcu/mips_bsp.h | 2 +-
hw/mcu/mips/danube/include/mcu/mips_hal.h | 2 +-
hw/mcu/mips/danube/src/hal_uart.c | 5 +-
kernel/os/include/os/arch/mips/os/os_arch.h | 2 +-
kernel/os/include/os/arch/pic32mx/os/os_arch.h | 84 +++
kernel/os/include/os/arch/pic32mz/os/os_arch.h | 84 +++
kernel/os/src/arch/mips/asm/excpt_isr.S | 3 -
kernel/os/src/arch/mips/os_arch_mips.c | 6 +-
kernel/os/src/arch/pic32mx/asm/ctx.S | 163 +++++
kernel/os/src/arch/pic32mx/os_arch_pic32mx.c | 213 ++++++
kernel/os/src/arch/pic32mx/os_fault.c | 122 ++++
kernel/os/src/arch/pic32mz/asm/ctx.S | 163 +++++
kernel/os/src/arch/pic32mz/os_arch_pic32mz.c | 213 ++++++
kernel/os/src/arch/pic32mz/os_fault.c | 122 ++++
49 files changed, 3623 insertions(+), 12 deletions(-)
----------------------------------------------------------------------
[2/3] incubator-mynewt-core git commit: pic32 port,
soft floating point only, kernel mode only
Posted by ma...@apache.org.
pic32 port, soft floating point only, kernel mode only
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/70bf4a85
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/70bf4a85
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/70bf4a85
Branch: refs/heads/develop
Commit: 70bf4a85791417a041ed79ab909fed8ed064a753
Parents: 612f8ef
Author: julian <ju...@imgtec.com>
Authored: Wed Mar 29 17:18:04 2017 +0100
Committer: julian <ju...@imgtec.com>
Committed: Thu Mar 30 10:52:13 2017 +0100
----------------------------------------------------------------------
compiler/xc32/compiler.yml | 36 ++
compiler/xc32/pkg.yml | 27 +
hw/bsp/pic32mx470_6LP_clicker/bsp.yml | 53 ++
hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h | 52 ++
.../include/bsp/bsp_sysid.h | 36 ++
hw/bsp/pic32mx470_6LP_clicker/pkg.yml | 46 ++
hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c | 27 +
hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c | 85 +++
hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c | 51 ++
hw/bsp/pic32mx470_6LP_clicker/syscfg.yml | 41 ++
hw/bsp/pic32mz2048_wi-fire/bsp.yml | 53 ++
hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp.h | 52 ++
.../pic32mz2048_wi-fire/include/bsp/bsp_sysid.h | 36 ++
hw/bsp/pic32mz2048_wi-fire/pkg.yml | 52 ++
hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c | 27 +
hw/bsp/pic32mz2048_wi-fire/src/os_bsp.c | 109 ++++
hw/bsp/pic32mz2048_wi-fire/src/sbrk.c | 51 ++
hw/bsp/pic32mz2048_wi-fire/syscfg.yml | 49 ++
.../pic32mx470F512H/include/mcu/mips_bsp.h | 24 +
.../pic32mx470F512H/include/mcu/mips_hal.h | 39 ++
.../pic32mx470F512H/include/mcu/pic32mx470.h | 25 +
hw/mcu/microchip/pic32mx470F512H/pkg.yml | 31 +
.../microchip/pic32mx470F512H/src/hal_os_tick.c | 36 ++
.../microchip/pic32mx470F512H/src/hal_system.c | 35 +
hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c | 463 +++++++++++++
.../pic32mx470F512H/src/hal_watchdog.c | 39 ++
.../pic32mz2048efg100/include/mcu/mips_bsp.h | 24 +
.../pic32mz2048efg100/include/mcu/mips_hal.h | 39 ++
.../pic32mz2048efg100/include/mcu/pic32mz2048.h | 25 +
hw/mcu/microchip/pic32mz2048efg100/pkg.yml | 31 +
.../pic32mz2048efg100/src/hal_os_tick.c | 36 ++
.../pic32mz2048efg100/src/hal_system.c | 35 +
.../microchip/pic32mz2048efg100/src/hal_uart.c | 645 +++++++++++++++++++
.../pic32mz2048efg100/src/hal_watchdog.c | 39 ++
hw/mcu/mips/danube/include/mcu/mips.h | 2 +-
hw/mcu/mips/danube/include/mcu/mips_bsp.h | 2 +-
hw/mcu/mips/danube/include/mcu/mips_hal.h | 2 +-
hw/mcu/mips/danube/src/hal_uart.c | 5 +-
kernel/os/include/os/arch/mips/os/os_arch.h | 2 +-
kernel/os/include/os/arch/pic32mx/os/os_arch.h | 84 +++
kernel/os/include/os/arch/pic32mz/os/os_arch.h | 84 +++
kernel/os/src/arch/mips/asm/excpt_isr.S | 3 -
kernel/os/src/arch/mips/os_arch_mips.c | 6 +-
kernel/os/src/arch/pic32mx/asm/ctx.S | 163 +++++
kernel/os/src/arch/pic32mx/os_arch_pic32mx.c | 213 ++++++
kernel/os/src/arch/pic32mx/os_fault.c | 122 ++++
kernel/os/src/arch/pic32mz/asm/ctx.S | 163 +++++
kernel/os/src/arch/pic32mz/os_arch_pic32mz.c | 213 ++++++
kernel/os/src/arch/pic32mz/os_fault.c | 122 ++++
49 files changed, 3623 insertions(+), 12 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/compiler/xc32/compiler.yml
----------------------------------------------------------------------
diff --git a/compiler/xc32/compiler.yml b/compiler/xc32/compiler.yml
new file mode 100644
index 0000000..8bf1567
--- /dev/null
+++ b/compiler/xc32/compiler.yml
@@ -0,0 +1,36 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+compiler.path.cc: "xc32-gcc"
+compiler.path.as: "xc32-gcc"
+compiler.path.archive: "xc32-ar"
+compiler.path.objdump: "xc32-objdump"
+compiler.path.objsize: "xc32-size"
+compiler.path.objcopy: "xc32-objcopy"
+
+compiler.flags.base: -I/opt/microchip/xc32/v1.42/pic32mx/include -std=gnu11
+compiler.flags.default: [compiler.flags.base, -O2, -g3]
+compiler.flags.optimized: [compiler.flags.base, -Os -g3]
+compiler.flags.debug: [compiler.flags.base, -g3]
+
+compiler.as.flags: [-x, assembler-with-cpp]
+
+compiler.ld.flags:
+compiler.ld.resolve_circular_deps: true
+compiler.ld.mapfile: true
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/compiler/xc32/pkg.yml
----------------------------------------------------------------------
diff --git a/compiler/xc32/pkg.yml b/compiler/xc32/pkg.yml
new file mode 100644
index 0000000..94b8c44
--- /dev/null
+++ b/compiler/xc32/pkg.yml
@@ -0,0 +1,27 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: compiler/xc32
+pkg.type: compiler
+pkg.description: Compiler definition for the Microchip XC32 compiler.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - compiler
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/bsp.yml b/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
new file mode 100644
index 0000000..a898cd0
--- /dev/null
+++ b/hw/bsp/pic32mx470_6LP_clicker/bsp.yml
@@ -0,0 +1,53 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.arch: pic32mx
+bsp.compiler: compiler/xc32
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x00000000
+ size: 0kB
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h b/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h
new file mode 100644
index 0000000..b3c219e
--- /dev/null
+++ b/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp.h
@@ -0,0 +1,52 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+extern uint8_t _ccram_start;
+
+#define RAM_SIZE (128 * 1024)
+#define CCRAM_SIZE (64 * 1024)
+
+/* UART */
+#define UART_CNT 4
+#define CONSOLE_UART "uart2"
+
+#define NFFS_AREA_MAX (8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp_sysid.h
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp_sysid.h b/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp_sysid.h
new file mode 100644
index 0000000..7b0a24b
--- /dev/null
+++ b/hw/bsp/pic32mx470_6LP_clicker/include/bsp/bsp_sysid.h
@@ -0,0 +1,36 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef BSP_SYSID_H
+#define BSP_SYSID_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* stub until this BSP gets new HAL */
+enum system_device_id
+{
+ RESERVED,
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_SYSID_H */
\ No newline at end of file
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mx470_6LP_clicker/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/pkg.yml b/hw/bsp/pic32mx470_6LP_clicker/pkg.yml
new file mode 100644
index 0000000..bf2a1ed
--- /dev/null
+++ b/hw/bsp/pic32mx470_6LP_clicker/pkg.yml
@@ -0,0 +1,46 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/pic32mx470_6LP_clicker
+pkg.type: bsp
+pkg.description: BSP definition for the 6LoWPAN Clicker board.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+ - clicker
+
+pkg.lflags:
+ - -Wl,--defsym=_min_heap_size=0x400
+
+pkg.deps:
+ - hw/mcu/microchip/pic32mx470f512h
+
+pkg.deps.UART_0:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_1:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_2:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_3:
+ - hw/drivers/uart/uart_hal
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c b/hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c
new file mode 100644
index 0000000..c1187c6
--- /dev/null
+++ b/hw/bsp/pic32mx470_6LP_clicker/src/hal_bsp.c
@@ -0,0 +1,27 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include "hal/hal_bsp.h"
+#include "bsp/bsp.h"
+#include <assert.h>
+
+const struct hal_flash *
+bsp_flash_dev(uint8_t id)
+{
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c b/hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c
new file mode 100644
index 0000000..8add7e2
--- /dev/null
+++ b/hw/bsp/pic32mx470_6LP_clicker/src/os_bsp.c
@@ -0,0 +1,85 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_bsp.h"
+#include "syscfg/syscfg.h"
+#include "uart/uart.h"
+#if MYNEWT_VAL(UART_0) || MYNEWT_VAL(UART_1)
+#include "uart_hal/uart_hal.h"
+#endif
+
+#include <xc.h>
+
+#include <assert.h>
+
+#pragma config CP=1, FWDTEN=0, FCKSM=1, FPBDIV=1, OSCIOFNC=1, POSCMOD=1
+/* PLL conf div in: 2, mul: 20, div out: 1 8->4->80->80 */
+#pragma config FNOSC=3, FPLLODIV=0, UPLLEN=1, FPLLMUL=5, FPLLIDIV=1, FSRSSEL=7
+/* PGEC2/PGED2 pair is used */
+#pragma config ICESEL=2
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_uart1;
+#endif
+
+#if MYNEWT_VAL(UART_2)
+static struct uart_dev os_bsp_uart2;
+#endif
+
+#if MYNEWT_VAL(UART_3)
+static struct uart_dev os_bsp_uart3;
+#endif
+
+void _close(int fd);
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_2)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart2, "uart2",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_3)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart3, "uart3",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+#endif
+
+ (void)rc;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c b/hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c
new file mode 100644
index 0000000..d3f99d6
--- /dev/null
+++ b/hw/bsp/pic32mx470_6LP_clicker/src/sbrk.c
@@ -0,0 +1,51 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#define HEAPSIZE (1024)
+
+static char __Heap[HEAPSIZE];
+
+void *
+_sbrk(int incr)
+{
+ static char *brk = __Heap;
+
+ void *prev_brk;
+
+ if (incr < 0) {
+ /* Returning memory to the heap. */
+ incr = -incr;
+ if (brk - incr < __Heap) {
+ prev_brk = (void *)-1;
+ } else {
+ prev_brk = brk;
+ brk -= incr;
+ }
+ } else {
+ /* Allocating memory from the heap. */
+ if ((__Heap + HEAPSIZE) - brk >= incr) {
+ prev_brk = brk;
+ brk += incr;
+ } else {
+ prev_brk = (void *)-1;
+ }
+ }
+
+ return prev_brk;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mx470_6LP_clicker/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mx470_6LP_clicker/syscfg.yml b/hw/bsp/pic32mx470_6LP_clicker/syscfg.yml
new file mode 100644
index 0000000..87c4e47
--- /dev/null
+++ b/hw/bsp/pic32mx470_6LP_clicker/syscfg.yml
@@ -0,0 +1,41 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Package: hw/bsp/pic32mx470_6LP_clicker
+
+syscfg.defs:
+ CLOCK_FREQ:
+ description: 'TBD'
+ value: 80000000ul
+
+ UART_0:
+ description: 'TBD'
+ value: 1
+
+ UART_1:
+ description: 'TBD'
+ value: 1
+
+ UART_2:
+ description: 'TBD'
+ value: 1
+
+ UART_3:
+ description: 'TBD'
+ value: 1
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mz2048_wi-fire/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/bsp.yml b/hw/bsp/pic32mz2048_wi-fire/bsp.yml
new file mode 100644
index 0000000..742b89d
--- /dev/null
+++ b/hw/bsp/pic32mz2048_wi-fire/bsp.yml
@@ -0,0 +1,53 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.arch: pic32mz
+bsp.compiler: compiler/xc32
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x00000000
+ size: 0kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x00000000
+ size: 0kB
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp.h b/hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp.h
new file mode 100644
index 0000000..1a8a40c
--- /dev/null
+++ b/hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp.h
@@ -0,0 +1,52 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+extern uint8_t _ccram_start;
+
+#define RAM_SIZE (128 * 1024)
+#define CCRAM_SIZE (64 * 1024)
+
+/* UART */
+#define UART_CNT 6
+#define CONSOLE_UART "uart3"
+
+#define NFFS_AREA_MAX (8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp_sysid.h
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp_sysid.h b/hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp_sysid.h
new file mode 100644
index 0000000..7b0a24b
--- /dev/null
+++ b/hw/bsp/pic32mz2048_wi-fire/include/bsp/bsp_sysid.h
@@ -0,0 +1,36 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef BSP_SYSID_H
+#define BSP_SYSID_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* stub until this BSP gets new HAL */
+enum system_device_id
+{
+ RESERVED,
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_SYSID_H */
\ No newline at end of file
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mz2048_wi-fire/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/pkg.yml b/hw/bsp/pic32mz2048_wi-fire/pkg.yml
new file mode 100644
index 0000000..ebd831b
--- /dev/null
+++ b/hw/bsp/pic32mz2048_wi-fire/pkg.yml
@@ -0,0 +1,52 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/pic32mz2048_wi-fire
+pkg.type: bsp
+pkg.description: BSP definition for the 6LoWPAN Clicker board.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+ - clicker
+
+pkg.lflags:
+ - -Wl,--defsym=_min_heap_size=0x400
+
+pkg.deps:
+ - hw/mcu/microchip/pic32mz2048efg100
+
+pkg.deps.UART_0:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_1:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_2:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_3:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_4:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_5:
+ - hw/drivers/uart/uart_hal
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c b/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c
new file mode 100644
index 0000000..c1187c6
--- /dev/null
+++ b/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c
@@ -0,0 +1,27 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include "hal/hal_bsp.h"
+#include "bsp/bsp.h"
+#include <assert.h>
+
+const struct hal_flash *
+bsp_flash_dev(uint8_t id)
+{
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mz2048_wi-fire/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/src/os_bsp.c b/hw/bsp/pic32mz2048_wi-fire/src/os_bsp.c
new file mode 100644
index 0000000..4b9c0a6
--- /dev/null
+++ b/hw/bsp/pic32mz2048_wi-fire/src/os_bsp.c
@@ -0,0 +1,109 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_bsp.h"
+#include "syscfg/syscfg.h"
+#include "uart/uart.h"
+#if MYNEWT_VAL(UART_0) || MYNEWT_VAL(UART_1)
+#include "uart_hal/uart_hal.h"
+#endif
+
+#include <xc.h>
+
+#include <assert.h>
+
+/* JTAG on, WDT off */
+#pragma config JTAGEN=1, FWDTEN=0
+/* DMT off, primary oscilator EC mode, PLL */
+#pragma config FDMTEN=0, POSCMOD=0, FNOSC=1
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLODIV=1, FPLLMULT=49, FPLLICLK=0, FPLLRNG=1, FPLLIDIV=2
+/* USB off */
+#pragma config FUSBIDIO=0
+
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_uart1;
+#endif
+
+#if MYNEWT_VAL(UART_2)
+static struct uart_dev os_bsp_uart2;
+#endif
+
+#if MYNEWT_VAL(UART_3)
+static struct uart_dev os_bsp_uart3;
+#endif
+
+#if MYNEWT_VAL(UART_4)
+static struct uart_dev os_bsp_uart4;
+#endif
+
+#if MYNEWT_VAL(UART_5)
+static struct uart_dev os_bsp_uart5;
+#endif
+
+void _close(int fd);
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+ #if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+ #endif
+
+ #if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+ #endif
+
+ #if MYNEWT_VAL(UART_2)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart2, "uart2",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+ #endif
+
+ #if MYNEWT_VAL(UART_3)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart3, "uart3",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+ #endif
+
+ #if MYNEWT_VAL(UART_4)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart4, "uart4",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+ #endif
+
+ #if MYNEWT_VAL(UART_5)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart5, "uart5",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, 0);
+ assert(rc == 0);
+ #endif
+
+ (void)rc;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mz2048_wi-fire/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/src/sbrk.c b/hw/bsp/pic32mz2048_wi-fire/src/sbrk.c
new file mode 100644
index 0000000..d3f99d6
--- /dev/null
+++ b/hw/bsp/pic32mz2048_wi-fire/src/sbrk.c
@@ -0,0 +1,51 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#define HEAPSIZE (1024)
+
+static char __Heap[HEAPSIZE];
+
+void *
+_sbrk(int incr)
+{
+ static char *brk = __Heap;
+
+ void *prev_brk;
+
+ if (incr < 0) {
+ /* Returning memory to the heap. */
+ incr = -incr;
+ if (brk - incr < __Heap) {
+ prev_brk = (void *)-1;
+ } else {
+ prev_brk = brk;
+ brk -= incr;
+ }
+ } else {
+ /* Allocating memory from the heap. */
+ if ((__Heap + HEAPSIZE) - brk >= incr) {
+ prev_brk = brk;
+ brk += incr;
+ } else {
+ prev_brk = (void *)-1;
+ }
+ }
+
+ return prev_brk;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/bsp/pic32mz2048_wi-fire/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/pic32mz2048_wi-fire/syscfg.yml b/hw/bsp/pic32mz2048_wi-fire/syscfg.yml
new file mode 100644
index 0000000..5c082e4
--- /dev/null
+++ b/hw/bsp/pic32mz2048_wi-fire/syscfg.yml
@@ -0,0 +1,49 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Package: hw/bsp/pic32mx470_6LP_clicker
+
+syscfg.defs:
+ CLOCK_FREQ:
+ description: 'TBD'
+ value: 200000000ul
+
+ UART_0:
+ description: 'TBD'
+ value: 1
+
+ UART_1:
+ description: 'TBD'
+ value: 1
+
+ UART_2:
+ description: 'TBD'
+ value: 1
+
+ UART_3:
+ description: 'TBD'
+ value: 1
+
+ UART_4:
+ description: 'TBD'
+ value: 1
+
+ UART_5:
+ description: 'TBD'
+ value: 1
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_bsp.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_bsp.h b/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_bsp.h
new file mode 100644
index 0000000..01d75f4
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_bsp.h
@@ -0,0 +1,24 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_MIPS_BSP_
+#define H_MIPS_BSP_
+
+extern const struct hal_flash native_flash_dev;
+
+#endif /* H_NATIVE_BSP_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_hal.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_hal.h b/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_hal.h
new file mode 100644
index 0000000..f29bd2a
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/include/mcu/mips_hal.h
@@ -0,0 +1,39 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the HAL implementations within this MCU */
+
+#ifndef MIPS_HAL_H
+#define MIPS_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+#define __HAL_ENABLE_INTERRUPTS(__os_sr) __builtin_set_isr_state(__os_sr)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MCU_HAL_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32mx470.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32mx470.h b/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32mx470.h
new file mode 100644
index 0000000..6dccd82
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/include/mcu/pic32mx470.h
@@ -0,0 +1,25 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_PIC32_H__
+#define __MCU_PIC32_H__
+
+#define OS_TICKS_PER_SEC (1000)
+
+#endif /* __MCU_PIC32_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mx470F512H/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/pkg.yml b/hw/mcu/microchip/pic32mx470F512H/pkg.yml
new file mode 100644
index 0000000..824984e
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/pkg.yml
@@ -0,0 +1,31 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/mcu/microchip/pic32mx470f512h
+pkg.description: MCU definition for the Microchip PIC32MX470F512H microcontroller.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+
+pkg.cflags:
+ - -mprocessor=32MX470F512H
+pkg.deps:
+ - hw/hal
+ - compiler/xc32
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mx470F512H/src/hal_os_tick.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/src/hal_os_tick.c b/hw/mcu/microchip/pic32mx470F512H/src/hal_os_tick.c
new file mode 100644
index 0000000..8fc68d6
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/src/hal_os_tick.c
@@ -0,0 +1,36 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/os.h>
+#include <hal/hal_os_tick.h>
+
+/*
+ * XXX implement tickless mode.
+ */
+void
+os_tick_idle(os_time_t ticks)
+{
+ OS_ASSERT_CRITICAL();
+}
+
+void
+os_tick_init(uint32_t os_ticks_per_sec, int prio)
+{
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mx470F512H/src/hal_system.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/src/hal_system.c b/hw/mcu/microchip/pic32mx470F512H/src/hal_system.c
new file mode 100644
index 0000000..ed6e6a3
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/src/hal_system.c
@@ -0,0 +1,35 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_system.h"
+
+#include <stdint.h>
+
+void
+hal_system_reset(void)
+{
+ while (1) {
+ }
+}
+
+int
+hal_debugger_connected(void)
+{
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c b/hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c
new file mode 100644
index 0000000..93eff5b
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/src/hal_uart.c
@@ -0,0 +1,463 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_uart.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/mips_hal.h"
+#include <assert.h>
+#include <stdlib.h>
+
+#include <xc.h>
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC1CLR = _IEC1_U1TXIE_MASK;
+ break;
+ case 1:
+ IEC1CLR = _IEC1_U2TXIE_MASK;
+ break;
+ case 2:
+ IEC2CLR = _IEC2_U3TXIE_MASK;
+ break;
+ case 3:
+ IEC2CLR = _IEC2_U4TXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC1SET = _IEC1_U1TXIE_MASK;
+ break;
+ case 1:
+ IEC1SET = _IEC1_U2TXIE_MASK;
+ break;
+ case 2:
+ IEC2SET = _IEC2_U3TXIE_MASK;
+ break;
+ case 3:
+ IEC2SET = _IEC2_U4TXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC1CLR = _IEC1_U1RXIE_MASK;
+ break;
+ case 1:
+ IEC1CLR = _IEC1_U2RXIE_MASK;
+ break;
+ case 2:
+ IEC1CLR = _IEC1_U3RXIE_MASK;
+ break;
+ case 3:
+ IEC2CLR = _IEC2_U4RXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC1SET = _IEC1_U1RXIE_MASK;
+ break;
+ case 1:
+ IEC1SET = _IEC1_U2RXIE_MASK;
+ break;
+ case 2:
+ IEC1SET = _IEC1_U3RXIE_MASK;
+ break;
+ case 3:
+ IEC2SET = _IEC2_U4RXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_receive_ready(int port)
+{
+ switch (port) {
+ case 0:
+ uarts[port].u_rx_data = U1RXREG;
+ break;
+ case 1:
+ uarts[port].u_rx_data = U2RXREG;
+ break;
+ case 2:
+ uarts[port].u_rx_data = U3RXREG;
+ break;
+ case 3:
+ uarts[port].u_rx_data = U4RXREG;
+ break;
+ }
+
+ int c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ } else {
+ /* write char out */
+ switch (port) {
+ case 0:
+ U1TXREG = (uint32_t)c & 0xff;
+ break;
+ case 1:
+ U2TXREG = (uint32_t)c & 0xff;
+ break;
+ case 2:
+ U3TXREG = (uint32_t)c & 0xff;
+ break;
+ case 3:
+ U4TXREG = (uint32_t)c & 0xff;
+ break;
+ }
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART_1_VECTOR))) uart_1_isr(void)
+{
+ uint32_t sta = U1STA;
+ if (sta & _U1STA_URXDA_MASK) {
+ uart_receive_ready(0);
+ IFS1CLR = _IFS1_U1RXIF_MASK;
+ }
+ if (sta & _U1STA_TRMT_MASK) {
+ uart_transmit_ready(0);
+ IFS1CLR = _IFS1_U1TXIF_MASK;
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART_2_VECTOR))) uart_2_isr(void)
+{
+ uint32_t sta = U2STA;
+ if (sta & _U2STA_URXDA_MASK) {
+ uart_receive_ready(1);
+ IFS1CLR = _IFS1_U2RXIF_MASK;
+ }
+ if (sta & _U2STA_TRMT_MASK) {
+ uart_transmit_ready(1);
+ IFS1CLR = _IFS1_U2TXIF_MASK;
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART_3_VECTOR))) uart_3_isr(void)
+{
+ uint32_t sta = U3STA;
+ if (sta & _U3STA_URXDA_MASK) {
+ uart_receive_ready(2);
+ IFS1CLR = _IFS1_U3RXIF_MASK;
+ }
+ if (sta & _U3STA_TRMT_MASK) {
+ uart_transmit_ready(2);
+ IFS2CLR = _IFS2_U3TXIF_MASK;
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART_4_VECTOR))) uart_4_isr(void)
+{
+ uint32_t sta = U4STA;
+ if (sta & _U4STA_URXDA_MASK) {
+ uart_receive_ready(3);
+ IFS2CLR = _IFS2_U4RXIF_MASK;
+ }
+ if (sta & _U4STA_TRMT_MASK) {
+ uart_transmit_ready(3);
+ IFS2CLR = _IFS2_U4TXIF_MASK;
+ }
+}
+
+void
+hal_uart_start_rx(int port)
+{
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ uint32_t sr;
+ __HAL_DISABLE_INTERRUPTS(sr);
+ int c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ /* enable RX interrupt */
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ switch (port){
+ case 0:
+ /* wait for transmit holding register to be empty */
+ while(!(U1STA & _U1STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U1TXREG = data;
+ break;
+ case 1:
+ /* wait for transmit holding register to be empty */
+ while(!(U2STA & _U2STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U2TXREG = data;
+ break;
+ case 2:
+ /* wait for transmit holding register to be empty */
+ while(!(U3STA & _U3STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U3TXREG = data;
+ break;
+ case 3:
+ /* wait for transmit holding register to be empty */
+ while(!(U4STA & _U4STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U4TXREG = data;
+ break;
+ }
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint32_t peripheral_clk = MYNEWT_VAL(CLOCK_FREQ) / 2;
+
+ // check input
+ if ((databits < 8) || (databits > 9) || (stopbits < 1) || (stopbits > 2)) {
+ return -1;
+ }
+
+ /* XXX: flow control currently unsupported */
+ (void) flow_ctl;
+ uarts[port].u_rx_stall = 0;
+
+ uint16_t mode = _U1MODE_BRGH_MASK | (stopbits >> 1);
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ if (databits == 9) {
+ mode |= _U1MODE_PDSEL_MASK;
+ }
+ break;
+ case HAL_UART_PARITY_ODD:
+ if (databits == 9) { // PIC does not do 9 bit data + parity.
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL1_MASK;
+ break;
+ case HAL_UART_PARITY_EVEN:
+ if (databits == 9) {
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL0_MASK;
+ break;
+ default:
+ return -1;
+ }
+
+ uint16_t divisor = peripheral_clk / (4 * baudrate) - 1;
+
+ switch (port) {
+ case 0:
+ /* disable */
+ U1MODE = 0;
+ __asm__("nop");
+ U1BRG = divisor;
+ U1MODE = mode;
+ U1STA = _U1STA_URXEN_MASK | _U1STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS1CLR = _IFS1_U1RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC1SET = _IEC1_U1RXIE_MASK;
+
+ /* set interrupt priority */
+ IPC7CLR = _IPC7_U1IP_MASK;
+ IPC7SET = (1 << _IPC7_U1IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC7CLR = _IPC7_U1IS_MASK;
+ IPC7SET = (0 << _IPC7_U1IS_POSITION); // subpriority 0
+ U1MODESET = _U1MODE_ON_MASK;
+ break;
+ case 1:
+ /* disable */
+ U2MODE = 0;
+ __asm__("nop");
+ U2BRG = divisor;
+ U2MODE = mode;
+ U2STA = _U2STA_URXEN_MASK | _U2STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS1CLR = _IFS1_U2RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC1SET = _IEC1_U2RXIE_MASK;
+
+ /* set interrupt priority */
+ IPC9CLR = _IPC9_U2IP_MASK;
+ IPC9SET = (1 << _IPC9_U2IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC9CLR = _IPC9_U2IS_MASK;
+ IPC9SET = (0 << _IPC9_U2IS_POSITION); // subpriority 0
+ U2MODESET = _U2MODE_ON_MASK;
+ break;
+ case 2:
+ /* disable */
+ U3MODE = 0;
+ __asm__("nop");
+ U3BRG = divisor;
+ U3MODE = mode;
+ U3STA = _U3STA_URXEN_MASK | _U3STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS1CLR = _IFS1_U3RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC1SET = _IEC1_U3RXIE_MASK;
+
+ /* set interrupt priority */
+ IPC9CLR = _IPC9_U3IP_MASK;
+ IPC9SET = (1 << _IPC9_U3IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC9CLR = _IPC9_U3IS_MASK;
+ IPC9SET = (0 << _IPC9_U3IS_POSITION); // subpriority 0
+ U3MODESET = _U3MODE_ON_MASK;
+ break;
+ case 3:
+ /* disable */
+ U4MODE = 0;
+ __asm__("nop");
+ U4BRG = divisor;
+ U4MODE = mode;
+ U4STA = _U4STA_URXEN_MASK | _U4STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS2CLR = _IFS2_U4RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC2SET = _IEC2_U4RXIE_MASK;
+
+ /* set interrupt priority */
+ IPC9CLR = _IPC9_U4IP_MASK;
+ IPC9SET = (1 << _IPC9_U4IP_POSITION); // priority 1
+ /* set interrupt subpriority */
+ IPC9CLR = _IPC9_U4IS_MASK;
+ IPC9SET = (0 << _IPC9_U4IS_POSITION); // subpriority 0
+ U4MODESET = _U4MODE_ON_MASK;
+ break;
+ }
+ return 0;
+}
+
+int
+hal_uart_close(int port)
+{
+ switch(port) {
+ case 0:
+ /* disable */
+ U1MODE = 0;
+ /* disable RX interrupt */
+ IEC1CLR = _IEC1_U1RXIE_MASK;
+ break;
+ case 1:
+ /* disable */
+ U2MODE = 0;
+ /* disable RX interrupt */
+ IEC1CLR = _IEC1_U2RXIE_MASK;
+ break;
+ case 2:
+ U3MODE = 0;
+ /* disable RX interrupt */
+ IEC1CLR = _IEC1_U3RXIE_MASK;
+ break;
+ case 3:
+ /* disable */
+ U4MODE = 0;
+ /* disable RX interrupt */
+ IEC2CLR = _IEC2_U4RXIE_MASK;
+ break;
+ default:
+ return -1;
+ }
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mx470F512H/src/hal_watchdog.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mx470F512H/src/hal_watchdog.c b/hw/mcu/microchip/pic32mx470F512H/src/hal_watchdog.c
new file mode 100644
index 0000000..392b967
--- /dev/null
+++ b/hw/mcu/microchip/pic32mx470F512H/src/hal_watchdog.c
@@ -0,0 +1,39 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_watchdog.h"
+
+#include <assert.h>
+
+int
+hal_watchdog_init(uint32_t expire_msecs)
+{
+ return (0);
+}
+
+void
+hal_watchdog_enable(void)
+{
+}
+
+void
+hal_watchdog_tickle(void)
+{
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mips_bsp.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mips_bsp.h b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mips_bsp.h
new file mode 100644
index 0000000..01d75f4
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mips_bsp.h
@@ -0,0 +1,24 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_MIPS_BSP_
+#define H_MIPS_BSP_
+
+extern const struct hal_flash native_flash_dev;
+
+#endif /* H_NATIVE_BSP_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mips_hal.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mips_hal.h b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mips_hal.h
new file mode 100644
index 0000000..f29bd2a
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/mips_hal.h
@@ -0,0 +1,39 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the HAL implementations within this MCU */
+
+#ifndef MIPS_HAL_H
+#define MIPS_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+#define __HAL_ENABLE_INTERRUPTS(__os_sr) __builtin_set_isr_state(__os_sr)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MCU_HAL_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32mz2048.h
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32mz2048.h b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32mz2048.h
new file mode 100644
index 0000000..6dccd82
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/include/mcu/pic32mz2048.h
@@ -0,0 +1,25 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_PIC32_H__
+#define __MCU_PIC32_H__
+
+#define OS_TICKS_PER_SEC (1000)
+
+#endif /* __MCU_PIC32_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mz2048efg100/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/pkg.yml b/hw/mcu/microchip/pic32mz2048efg100/pkg.yml
new file mode 100644
index 0000000..a3ad428
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/pkg.yml
@@ -0,0 +1,31 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/mcu/microchip/pic32mz2048efg100
+pkg.description: MCU definition for Microchip PIC32 microcontrollers.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+
+pkg.cflags:
+ - -mprocessor=32MZ2048EFG100
+pkg.deps:
+ - hw/hal
+ - compiler/xc32
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mz2048efg100/src/hal_os_tick.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/src/hal_os_tick.c b/hw/mcu/microchip/pic32mz2048efg100/src/hal_os_tick.c
new file mode 100644
index 0000000..8fc68d6
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/src/hal_os_tick.c
@@ -0,0 +1,36 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <os/os.h>
+#include <hal/hal_os_tick.h>
+
+/*
+ * XXX implement tickless mode.
+ */
+void
+os_tick_idle(os_time_t ticks)
+{
+ OS_ASSERT_CRITICAL();
+}
+
+void
+os_tick_init(uint32_t os_ticks_per_sec, int prio)
+{
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mz2048efg100/src/hal_system.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/src/hal_system.c b/hw/mcu/microchip/pic32mz2048efg100/src/hal_system.c
new file mode 100644
index 0000000..ed6e6a3
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/src/hal_system.c
@@ -0,0 +1,35 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_system.h"
+
+#include <stdint.h>
+
+void
+hal_system_reset(void)
+{
+ while (1) {
+ }
+}
+
+int
+hal_debugger_connected(void)
+{
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mz2048efg100/src/hal_uart.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/src/hal_uart.c b/hw/mcu/microchip/pic32mz2048efg100/src/hal_uart.c
new file mode 100644
index 0000000..5131f57
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/src/hal_uart.c
@@ -0,0 +1,645 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_uart.h"
+#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "mcu/mips_hal.h"
+#include <assert.h>
+#include <stdlib.h>
+
+#include <xc.h>
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK;
+ break;
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK;
+ break;
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK;
+ break;
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK;
+ break;
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK;
+ break;
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK;
+ break;
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK;
+ break;
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK;
+ break;
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK;
+ break;
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK;
+ break;
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK;
+ break;
+ }
+}
+
+static void
+uart_receive_ready(int port)
+{
+ switch (port) {
+ case 0:
+ uarts[port].u_rx_data = U1RXREG;
+ break;
+ case 1:
+ uarts[port].u_rx_data = U2RXREG;
+ break;
+ case 2:
+ uarts[port].u_rx_data = U3RXREG;
+ break;
+ case 3:
+ uarts[port].u_rx_data = U4RXREG;
+ break;
+ case 4:
+ uarts[port].u_rx_data = U5RXREG;
+ break;
+ case 5:
+ uarts[port].u_rx_data = U6RXREG;
+ break;
+ }
+
+ int c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ } else {
+ /* write char out */
+ switch (port) {
+ case 0:
+ U1TXREG = (uint32_t)c & 0xff;
+ break;
+ case 1:
+ U2TXREG = (uint32_t)c & 0xff;
+ break;
+ case 2:
+ U3TXREG = (uint32_t)c & 0xff;
+ break;
+ case 3:
+ U4TXREG = (uint32_t)c & 0xff;
+ break;
+ case 4:
+ U5TXREG = (uint32_t)c & 0xff;
+ break;
+ case 5:
+ U6TXREG = (uint32_t)c & 0xff;
+ break;
+ }
+ }
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_RX_VECTOR))) uart_1_rx_isr(void)
+{
+ uart_receive_ready(0);
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_TX_VECTOR))) uart_1_tx_isr(void)
+{
+ uart_transmit_ready(0);
+ IFS3CLR = _IFS3_U1TXIF_MASK;
+}
+
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_RX_VECTOR))) uart_2_rx_isr(void)
+{
+ uart_receive_ready(1);
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_TX_VECTOR))) uart_2_tx_isr(void)
+{
+ uart_transmit_ready(1);
+ IFS4CLR = _IFS4_U2TXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_RX_VECTOR))) uart_3_tx_rx_isr(void)
+{
+ uart_receive_ready(2);
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_TX_VECTOR))) uart_3_tx_isr(void)
+{
+ uart_transmit_ready(2);
+ IFS4CLR = _IFS4_U3TXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_RX_VECTOR))) uart_4_rx_isr(void)
+{
+ uart_receive_ready(3);
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_TX_VECTOR))) uart_4_tx_isr(void)
+{
+ uart_transmit_ready(3);
+ IFS5CLR = _IFS5_U4TXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_RX_VECTOR))) uart_5_rx_isr(void)
+{
+ uart_receive_ready(4);
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_TX_VECTOR))) uart_5_tx_isr(void)
+{
+ uart_transmit_ready(4);
+ IFS5CLR = _IFS5_U5TXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_RX_VECTOR))) uart_6_rx_isr(void)
+{
+ uart_receive_ready(5);
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_TX_VECTOR))) uart_6_tx_isr(void)
+{
+ uart_transmit_ready(5);
+ IFS5CLR = _IFS5_U6TXIF_MASK;
+}
+
+void
+hal_uart_start_rx(int port)
+{
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ uint32_t sr;
+ __HAL_DISABLE_INTERRUPTS(sr);
+ int c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ /* enable RX interrupt */
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ switch (port){
+ case 0:
+ /* wait for transmit holding register to be empty */
+ while(!(U1STA & _U1STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U1TXREG = data;
+ break;
+ case 1:
+ /* wait for transmit holding register to be empty */
+ while(!(U2STA & _U2STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U2TXREG = data;
+ break;
+ case 2:
+ /* wait for transmit holding register to be empty */
+ while(!(U3STA & _U3STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U3TXREG = data;
+ break;
+ case 3:
+ /* wait for transmit holding register to be empty */
+ while(!(U4STA & _U4STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U4TXREG = data;
+ break;
+ case 4:
+ /* wait for transmit holding register to be empty */
+ while(!(U5STA & _U5STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U5TXREG = data;
+ break;
+ case 5:
+ /* wait for transmit holding register to be empty */
+ while(!(U6STA & _U6STA_TRMT_MASK)) {
+ }
+ /* write to transmit register */
+ U6TXREG = data;
+ break;
+ }
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint32_t peripheral_clk = MYNEWT_VAL(CLOCK_FREQ) / 2;
+
+ // check input
+ if ((databits < 8) || (databits > 9) || (stopbits < 1) || (stopbits > 2)) {
+ return -1;
+ }
+
+ /* XXX: flow control currently unsupported */
+ (void) flow_ctl;
+ uarts[port].u_rx_stall = 0;
+
+ uint16_t mode = _U1MODE_BRGH_MASK | (stopbits >> 1);
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ if (databits == 9) {
+ mode |= _U1MODE_PDSEL_MASK;
+ }
+ break;
+ case HAL_UART_PARITY_ODD:
+ if (databits == 9) { // PIC does not do 9 bit data + parity.
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL1_MASK;
+ break;
+ case HAL_UART_PARITY_EVEN:
+ if (databits == 9) {
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL0_MASK;
+ break;
+ default:
+ return -1;
+ }
+
+ uint16_t divisor = peripheral_clk / (4 * baudrate) - 1;
+
+ switch (port) {
+ case 0:
+ /* disable */
+ U1MODE = 0;
+ __asm__("nop");
+ U1BRG = divisor;
+ U1MODE = mode;
+ U1STA = _U1STA_URXEN_MASK | _U1STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC3SET = _IEC3_U1RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC28CLR = _IPC28_U1RXIP_MASK;
+ IPC28SET = (1 << _IPC28_U1RXIP_POSITION); // priority 1
+ /* set rx interrupt subpriority */
+ IPC28CLR = _IPC28_U1RXIS_MASK;
+ IPC28SET = (0 << _IPC28_U1RXIS_POSITION); // subpriority 0
+
+ /* set tx interrupt priority */
+ IPC28CLR = _IPC28_U1TXIP_MASK;
+ IPC28SET = (1 << _IPC28_U1TXIP_POSITION); // priority 1
+ /* set tx interrupt subpriority */
+ IPC28CLR = _IPC28_U1TXIS_MASK;
+ IPC28SET = (0 << _IPC28_U1TXIS_POSITION); // subpriority 0
+
+ U1MODESET = _U1MODE_ON_MASK;
+ break;
+ case 1:
+ /* disable */
+ U2MODE = 0;
+ __asm__("nop");
+ U2BRG = divisor;
+ U2MODE = mode;
+ U2STA = _U2STA_URXEN_MASK | _U2STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC4SET = _IEC4_U2RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC36CLR = _IPC36_U2RXIP_MASK;
+ IPC36SET = (1 << _IPC36_U2RXIP_POSITION); // priority 1
+ /* set rx interrupt subpriority */
+ IPC36CLR = _IPC36_U2RXIS_MASK;
+ IPC36SET = (0 << _IPC36_U2RXIS_POSITION); // subpriority 0
+
+ /* set tx interrupt priority */
+ IPC36CLR = _IPC36_U2TXIP_MASK;
+ IPC36SET = (1 << _IPC36_U2TXIP_POSITION); // priority 1
+ /* set tx interrupt subpriority */
+ IPC36CLR = _IPC36_U2TXIS_MASK;
+ IPC36SET = (0 << _IPC36_U2TXIS_POSITION); // subpriority 0
+
+ U2MODESET = _U2MODE_ON_MASK;
+ break;
+ case 2:
+ /* disable */
+ U3MODE = 0;
+ __asm__("nop");
+ U3BRG = divisor;
+ U3MODE = mode;
+ U3STA = _U3STA_URXEN_MASK | _U3STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC4SET = _IEC4_U3RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC39CLR = _IPC39_U3RXIP_MASK;
+ IPC39SET = (1 << _IPC39_U3RXIP_POSITION); // priority 1
+ /* set rx interrupt subpriority */
+ IPC39CLR = _IPC39_U3RXIS_MASK;
+ IPC39SET = (0 << _IPC39_U3RXIS_POSITION); // subpriority 0
+
+ /* set tx interrupt priority */
+ IPC39CLR = _IPC39_U3TXIP_MASK;
+ IPC39SET = (1 << _IPC39_U3TXIP_POSITION); // priority 1
+ /* set tx interrupt subpriority */
+ IPC39CLR = _IPC39_U3TXIS_MASK;
+ IPC39SET = (0 << _IPC39_U3TXIS_POSITION); // subpriority 0
+
+ U3MODESET = _U3MODE_ON_MASK;
+ break;
+ case 3:
+ /* disable */
+ U4MODE = 0;
+ __asm__("nop");
+ U4BRG = divisor;
+ U4MODE = mode;
+ U4STA = _U4STA_URXEN_MASK | _U4STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC5SET = _IEC5_U4RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC42CLR = _IPC42_U4RXIP_MASK;
+ IPC42SET = (1 << _IPC42_U4RXIP_POSITION); // priority 1
+ /* set rx interrupt subpriority */
+ IPC42CLR = _IPC42_U4RXIS_MASK;
+ IPC42SET = (0 << _IPC42_U4RXIS_POSITION); // subpriority 0
+
+ /* set tx interrupt priority */
+ IPC43CLR = _IPC43_U4TXIP_MASK;
+ IPC43SET = (1 << _IPC43_U4TXIP_POSITION); // priority 1
+ /* set tx interrupt subpriority */
+ IPC43CLR = _IPC43_U4TXIS_MASK;
+ IPC43SET = (0 << _IPC43_U4TXIS_POSITION); // subpriority 0
+
+ U4MODESET = _U4MODE_ON_MASK;
+ break;
+ case 4:
+ /* disable */
+ U5MODE = 0;
+ __asm__("nop");
+ U5BRG = divisor;
+ U5MODE = mode;
+ U5STA = _U5STA_URXEN_MASK | _U5STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC5SET = _IEC5_U5RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC45CLR = _IPC45_U5RXIP_MASK;
+ IPC45SET = (1 << _IPC45_U5RXIP_POSITION); // priority 1
+ /* set rx interrupt subpriority */
+ IPC45CLR = _IPC45_U5RXIS_MASK;
+ IPC45SET = (0 << _IPC45_U5RXIS_POSITION); // subpriority 0
+
+ /* set tx interrupt priority */
+ IPC45CLR = _IPC45_U5TXIP_MASK;
+ IPC45SET = (1 << _IPC45_U5TXIP_POSITION); // priority 1
+ /* set tx interrupt subpriority */
+ IPC45CLR = _IPC45_U5TXIS_MASK;
+ IPC45SET = (0 << _IPC45_U5TXIS_POSITION); // subpriority 0
+
+ U5MODESET = _U5MODE_ON_MASK;
+ break;
+ case 5:
+ /* disable */
+ U6MODE = 0;
+ __asm__("nop");
+ U6BRG = divisor;
+ U6MODE = mode;
+ U6STA = _U6STA_URXEN_MASK | _U6STA_UTXEN_MASK;
+ /* clear RX interrupt flag */
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC5SET = _IEC5_U6RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC47CLR = _IPC47_U6RXIP_MASK;
+ IPC47SET = (1 << _IPC47_U6RXIP_POSITION); // priority 1
+ /* set rx interrupt subpriority */
+ IPC47CLR = _IPC47_U6RXIS_MASK;
+ IPC47SET = (0 << _IPC47_U6RXIS_POSITION); // subpriority 0
+
+ /* set tx interrupt priority */
+ IPC47CLR = _IPC47_U6TXIP_MASK;
+ IPC47SET = (1 << _IPC47_U6TXIP_POSITION); // priority 1
+ /* set tx interrupt subpriority */
+ IPC47CLR = _IPC47_U6TXIS_MASK;
+ IPC47SET = (0 << _IPC47_U6TXIS_POSITION); // subpriority 0
+
+ U6MODESET = _U6MODE_ON_MASK;
+ break;
+ }
+ return 0;
+}
+
+int
+hal_uart_close(int port)
+{
+ switch(port) {
+ case 0:
+ /* disable */
+ U1MODE = 0;
+ /* disable RX interrupt */
+ IEC3CLR = _IEC3_U1RXIE_MASK;
+ break;
+ case 1:
+ /* disable */
+ U2MODE = 0;
+ /* disable RX interrupt */
+ IEC4CLR = _IEC4_U2RXIE_MASK;
+ break;
+ case 2:
+ /* disable */
+ U3MODE = 0;
+ /* disable RX interrupt */
+ IEC4CLR = _IEC4_U3RXIE_MASK;
+ break;
+ case 3:
+ /* disable */
+ U4MODE = 0;
+ /* disable RX interrupt */
+ IEC5CLR = _IEC5_U4RXIE_MASK;
+ break;
+ case 5:
+ /* disable */
+ U5MODE = 0;
+ /* disable RX interrupt */
+ IEC5CLR = _IEC5_U5RXIE_MASK;
+ break;
+ case 6:
+ /* disable */
+ U6MODE = 0;
+ /* disable RX interrupt */
+ IEC5CLR = _IEC5_U6RXIE_MASK;
+ break;
+ default:
+ return -1;
+ }
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/microchip/pic32mz2048efg100/src/hal_watchdog.c
----------------------------------------------------------------------
diff --git a/hw/mcu/microchip/pic32mz2048efg100/src/hal_watchdog.c b/hw/mcu/microchip/pic32mz2048efg100/src/hal_watchdog.c
new file mode 100644
index 0000000..392b967
--- /dev/null
+++ b/hw/mcu/microchip/pic32mz2048efg100/src/hal_watchdog.c
@@ -0,0 +1,39 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "hal/hal_watchdog.h"
+
+#include <assert.h>
+
+int
+hal_watchdog_init(uint32_t expire_msecs)
+{
+ return (0);
+}
+
+void
+hal_watchdog_enable(void)
+{
+}
+
+void
+hal_watchdog_tickle(void)
+{
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/70bf4a85/hw/mcu/mips/danube/include/mcu/mips.h
----------------------------------------------------------------------
diff --git a/hw/mcu/mips/danube/include/mcu/mips.h b/hw/mcu/mips/danube/include/mcu/mips.h
index d1d9824..5cf1b74 100644
--- a/hw/mcu/mips/danube/include/mcu/mips.h
+++ b/hw/mcu/mips/danube/include/mcu/mips.h
@@ -22,4 +22,4 @@
#define OS_TICKS_PER_SEC (1000)
-#endif /* __MCU_CORTEX_M4_H__ */
+#endif /* __MCU_MIPS_H__ */