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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/03/28 14:52:36 UTC
[incubator-nuttx] branch master updated (b03f2e3 -> 0f02791)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from b03f2e3 lseek: use type:off_t for return value
new 60fc933 armv8-m: make the securefault handled by non-securefult
new 0f02791 armv8-m: add wake_func arm_should_generate_nonsecure_busfault
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repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
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Summary of changes:
arch/arm/src/armv8-m/arm_securefault.c | 54 ++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
[incubator-nuttx] 02/02: armv8-m: add wake_func arm_should_generate_nonsecure_busfault
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 0f02791ae68318127877a9db78d03ceb35a92a99
Author: ligd <li...@xiaomi.com>
AuthorDate: Thu Mar 24 21:21:34 2022 +0800
armv8-m: add wake_func arm_should_generate_nonsecure_busfault
Signed-off-by: ligd <li...@xiaomi.com>
---
arch/arm/src/armv8-m/arm_securefault.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/armv8-m/arm_securefault.c b/arch/arm/src/armv8-m/arm_securefault.c
index 5183ff9..a06a72b 100644
--- a/arch/arm/src/armv8-m/arm_securefault.c
+++ b/arch/arm/src/armv8-m/arm_securefault.c
@@ -82,6 +82,19 @@ static void generate_nonsecure_busfault(void)
****************************************************************************/
/****************************************************************************
+ * Name: arm_securefault_should_generate
+ *
+ * Description:
+ * Check whether should generate non-secure IRQ from securefault
+ *
+ ****************************************************************************/
+
+bool weak_function arm_should_generate_nonsecure_busfault(void)
+{
+ return true;
+}
+
+/****************************************************************************
* Name: arm_securefault
*
* Description:
@@ -145,11 +158,15 @@ int arm_securefault(int irq, FAR void *context, FAR void *arg)
putreg32(0xff, SAU_SFSR);
#ifdef CONFIG_DEBUG_SECUREFAULT
- generate_nonsecure_busfault();
-#else
+ if (arm_should_generate_nonsecure_busfault())
+ {
+ generate_nonsecure_busfault();
+ return OK;
+ }
+#endif
+
up_irq_save();
PANIC();
-#endif
return OK;
}
[incubator-nuttx] 01/02: armv8-m: make the securefault handled by non-securefult
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 60fc9332613dc84ff3d45a2d9308515a0d709487
Author: ligd <li...@xiaomi.com>
AuthorDate: Tue Mar 15 21:54:39 2022 +0800
armv8-m: make the securefault handled by non-securefult
tee is secure cpu and ap is non-secure cpu.
The crash PC can get by IP (R12).
[ EMERG] [tee] arm_hardfault: Hard Fault escalation:
[ EMERG] [tee] arm_securefault: PANIC!!! Secure Fault:
[ EMERG] [tee] arm_securefault: IRQ: 3 regs: 0x2400ff00
[ EMERG] [tee] arm_securefault: BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 0000000c
[ EMERG] [tee] arm_securefault: CFSR: 00000000 HFSR: 40000000 DFSR: 00000000
[ EMERG] [tee] arm_securefault: BFAR: 08006008 AFSR: 00000000 SFAR: 3c049ea0
[ EMERG] [tee] arm_securefault: Secure Fault Reason:
[ EMERG] [tee] arm_securefault: Attribution unit violation
[ EMERG] [tee] arm_securefault_handled_by_ns: Non-sec sp 3c475678
[ EMERG] [ap] arm_busfault: PANIC!!! Bus Fault:
[ EMERG] [ap] arm_busfault: IRQ: 5 regs: 0x3c475608
[ EMERG] [ap] arm_busfault: BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000005 CONTROL: 00000004
[ EMERG] [ap] arm_busfault: CFSR: 00000100 HFSR: 40000000 DFSR: 00000000 BFAR: 08006008 AFSR: 20000000
[ EMERG] [ap] arm_busfault: Bus Fault Reason:
[ EMERG] [ap] arm_busfault: Instruction bus error
[ EMERG] [ap] up_assert: Assertion failed at file:armv8-m/arm_busfault.c line: 105 task: nsh_main
[ EMERG] [ap] backtrace:
[ EMERG] [ap] [ 9] [<0x2c565246>] up_backtrace+0xa/0x168
[ EMERG] [ap] [ 9] [<0x2c550118>] sched_dumpstack+0x1c/0x60
[ EMERG] [ap] [ 9] [<0x2c5645d6>] up_assert+0x4e/0x324
[ EMERG] [ap] [ 9] [<0x2c54a98e>] _assert+0x2/0x10
[ EMERG] [ap] [ 9] [<0x2c5636d4>] arm_busfault+0xc8/0x15c
[ EMERG] [ap] [ 9] [<0x2c523070>] irq_dispatch+0x40/0x11c
[ EMERG] [ap] [ 9] [<0x2c563424>] arm_doirq+0x28/0x3c
[ EMERG] [ap] [ 9] [<0x2c55c892>] exception_common+0x4a/0xac
[ EMERG] [ap] [ 9] [<0x2c58668e>] nsh_parse_command+0x976/0x12b4
[ EMERG] [ap] [ 9] [<0x2c849cee>] write+0x52/0x74
[ EMERG] [ap] [ 9] [<0x2c58c0ac>] nsh_session+0x2c/0x1c8
[ EMERG] [ap] [ 9] [<0x2c58d82c>] nsh_consolemain+0x28/0x54
[ EMERG] [ap] [ 9] [<0x2c590352>] nsh_main+0x2a/0x48
[ EMERG] [ap] [ 9] [<0x2c5500da>] cxx_initialize+0x2a/0x4c
[ EMERG] [ap] [ 9] [<0x2c550090>] nxtask_startup+0x14/0x34
[ EMERG] [ap] [ 9] [<0x2c52966a>] nxtask_start+0x92/0xb8
[ EMERG] [ap] arm_registerdump: R0: 3c049ea0 R1: 00000004 R2: 3c448f98 R3: 00000000
[ EMERG] [ap] arm_registerdump: R4: 3c476a98 R5: 3c049ea0 R6: 00000000 FP: 3c476aac
[ EMERG] [ap] arm_registerdump: R8: 2c5873c9 SB: 3c049ea0 SL: 3c2e98fc R11: 3c284c2c
[ EMERG] [ap] arm_registerdump: IP: 2c58ba4a SP: 3c4756e0 LR: 3c049ea4 PC: 00000000
[ EMERG] [ap] arm_registerdump: xPSR: 610f0000 BASEPRI: 000000e0 CONTROL: 00000004
[ EMERG] [ap] arm_registerdump: EXC_RETURN: ffffffa8
[ EMERG] [ap] arm_dump_stack: IRQ Stack:
[ EMERG] [ap] arm_dump_stack: sp: 3c41c900
Signed-off-by: ligd <li...@xiaomi.com>
---
arch/arm/src/armv8-m/arm_securefault.c | 37 ++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/src/armv8-m/arm_securefault.c b/arch/arm/src/armv8-m/arm_securefault.c
index 84fba7f..5183ff9 100644
--- a/arch/arm/src/armv8-m/arm_securefault.c
+++ b/arch/arm/src/armv8-m/arm_securefault.c
@@ -41,6 +41,38 @@
#ifdef CONFIG_DEBUG_SECUREFAULT
# define sfalert(format, ...) _alert(format, ##__VA_ARGS__)
+
+# define OFFSET_R0 (0 * 4) /* R0 */
+# define OFFSET_R1 (1 * 4) /* R1 */
+# define OFFSET_R2 (2 * 4) /* R2 */
+# define OFFSET_R3 (3 * 4) /* R3 */
+# define OFFSET_R12 (4 * 4) /* R12 */
+# define OFFSET_R14 (5 * 4) /* R14 = LR */
+# define OFFSET_R15 (6 * 4) /* R15 = PC */
+# define OFFSET_XPSR (7 * 4) /* xPSR */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void generate_nonsecure_busfault(void)
+{
+ uint32_t nsp;
+
+ /* Get non-secure SP */
+
+ __asm__ __volatile__ ("mrs %0, msp_ns" : "=r" (nsp));
+
+ sfalert("Non-sec sp %08" PRIx32 "\n", nsp);
+ syslog_flush();
+
+ /* Force set return ReturnAddress to 0, then non-secure cpu will crash.
+ * Also, the ReturnAddress is very important, so move it to R12.
+ */
+
+ putreg32(getreg32(nsp + OFFSET_R15), nsp + OFFSET_R12);
+ putreg32(0, nsp + OFFSET_R15);
+}
#else
# define sfalert(...)
#endif
@@ -112,7 +144,12 @@ int arm_securefault(int irq, FAR void *context, FAR void *arg)
putreg32(0xff, SAU_SFSR);
+#ifdef CONFIG_DEBUG_SECUREFAULT
+ generate_nonsecure_busfault();
+#else
up_irq_save();
PANIC();
+#endif
+
return OK;
}