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Posted to commits@nuttx.apache.org by ac...@apache.org on 2026/10/08 18:53:29 UTC
(nuttx) 01/03: arch/arm/stm32h5: Use common Cortex-M33 core support
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 15c02fde299aabe437b5138143b17b33035205e3
Author: raiden00pl <ra...@railab.me>
AuthorDate: Wed Aug 26 10:23:03 2026 +0200
arch/arm/stm32h5: Use common Cortex-M33 core support
Enable STM32_COMMON_M33 for STM32H5 and drop the family reset, NVIC,
SysTick, and idle sources in favor of the common Cortex-M33 v1
implementation. The common heap allocator replaces the generic ARM one
through a STM32_PRIMARY_SRAM_SIZE spanning the contiguous SRAM banks
and skips the SRAM2 region when the primary heap already covers it.
Rename the family RCC header to stm32_rcc_m33.h for the common RCC
dispatch.
Add the SRAM3 parity initialization block and the CONFIG_STM32_ICACHE
enable call to the common reset handler, taken from the STM32H5 start
logic. Without CONFIG_STM32_ICACHE the reset handler disables an
ICACHE left enabled by a bootloader on STM32_HAVE_ICACHE families.
Move the flat-build MPU initialization to stm32_mpuinit_m33_v1.c in
common/stm32, built for every Cortex-M33 family with ARM_MPU, and
declare stm32_mpuinitialize for ARM_MPU as well as protected builds.
Declare stm32_board_initialize in the common start header.
Signed-off-by: raiden00pl <ra...@railab.me>
Assisted-by: Claude Code
---
arch/arm/include/stm32h5/chip.h | 4 +
arch/arm/src/common/stm32/CMakeLists.txt | 4 +
arch/arm/src/common/stm32/Kconfig | 1 +
arch/arm/src/common/stm32/Make.defs | 5 +
.../src/common/stm32/stm32_allocateheap_m33_v1.c | 5 +-
arch/arm/src/common/stm32/stm32_mpuinit.h | 2 +-
.../stm32/stm32_mpuinit_m33_v1.c} | 2 +-
arch/arm/src/common/stm32/stm32_start.h | 11 +
arch/arm/src/common/stm32/stm32_start_m33_v1.c | 41 +-
arch/arm/src/stm32h5/CMakeLists.txt | 11 -
arch/arm/src/stm32h5/Make.defs | 12 +-
arch/arm/src/stm32h5/stm32_idle.c | 102 -----
arch/arm/src/stm32h5/stm32_irq.c | 479 ---------------------
arch/arm/src/stm32h5/stm32_mpuinit.h | 53 ---
.../src/stm32h5/{stm32_rcc.h => stm32_rcc_m33.h} | 8 +-
arch/arm/src/stm32h5/stm32_start.c | 270 ------------
arch/arm/src/stm32h5/stm32_start.h | 47 --
arch/arm/src/stm32h5/stm32_timerisr.c | 150 -------
18 files changed, 76 insertions(+), 1131 deletions(-)
diff --git a/arch/arm/include/stm32h5/chip.h b/arch/arm/include/stm32h5/chip.h
index a3f2aa69072..4b51c0b4aa5 100644
--- a/arch/arm/include/stm32h5/chip.h
+++ b/arch/arm/include/stm32h5/chip.h
@@ -142,6 +142,10 @@
#define STM32_NCOMP (0) /* Comparators */
#define STM32_NOPAMP (0) /* Operational Amplifiers */
+/* Keep the primary heap within the configured SRAM range. */
+
+#define STM32_PRIMARY_SRAM_SIZE (CONFIG_RAM_END - STM32_SRAM1_BASE)
+
/* NVIC priority levels *****************************************************/
/* 16 Programmable interrupt levels */
diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt
index ac5c2c39ab2..85070c8f51a 100644
--- a/arch/arm/src/common/stm32/CMakeLists.txt
+++ b/arch/arm/src/common/stm32/CMakeLists.txt
@@ -58,6 +58,10 @@ if(CONFIG_STM32_COMMON_M33)
if(NOT CONFIG_ARCH_IDLE_CUSTOM)
list(APPEND SRCS stm32_idle_m33_v1.c)
endif()
+
+ if(CONFIG_ARM_MPU AND NOT CONFIG_BUILD_PROTECTED)
+ list(APPEND SRCS stm32_mpuinit_m33_v1.c)
+ endif()
endif()
if(CONFIG_STM32_PULSECOUNT)
diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig
index 562196ab357..044fc5cb7c8 100644
--- a/arch/arm/src/common/stm32/Kconfig
+++ b/arch/arm/src/common/stm32/Kconfig
@@ -56,6 +56,7 @@ config STM32_COMMON_L4_H5_L5_U5
config STM32_COMMON_M33
bool
default y if ARCH_CHIP_STM32C5
+ default y if ARCH_CHIP_STM32H5
default y if ARCH_CHIP_STM32L5
default y if ARCH_CHIP_STM32U3
default y if ARCH_CHIP_STM32U5
diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs
index 15aa2f05d9b..d9125f49357 100644
--- a/arch/arm/src/common/stm32/Make.defs
+++ b/arch/arm/src/common/stm32/Make.defs
@@ -70,6 +70,11 @@ CHIP_CSRCS += stm32_timerisr_m33_v1.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32_idle_m33_v1.c
endif
+ifeq ($(CONFIG_ARM_MPU),y)
+ifneq ($(CONFIG_BUILD_PROTECTED),y)
+CHIP_CSRCS += stm32_mpuinit_m33_v1.c
+endif
+endif
endif
ifeq ($(CONFIG_STM32_PULSECOUNT),y)
diff --git a/arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c b/arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c
index 6e683fd2c3d..4bf1e9bc9eb 100644
--- a/arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c
+++ b/arch/arm/src/common/stm32/stm32_allocateheap_m33_v1.c
@@ -57,7 +57,8 @@
*
* STM32_PRIMARY_SRAM_SIZE may span multiple contiguous SRAM banks. SRAM3
* and SRAM5 may be added as separate regions when their corresponding heap
- * options are selected.
+ * options are selected. Do not add SRAM2 again if it is already covered
+ * by the primary heap.
*
* In addition to internal SRAM, memory may also be available through the
* FSMC. In order to use FSMC SRAM, the following additional things need to
@@ -303,7 +304,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
-#ifdef CONFIG_STM32_SRAM2_HEAP
+#if defined(CONFIG_STM32_SRAM2_HEAP) && SRAM2_START >= SRAM1_END
# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
diff --git a/arch/arm/src/common/stm32/stm32_mpuinit.h b/arch/arm/src/common/stm32/stm32_mpuinit.h
index 606d589ef28..cb6043ca6ce 100644
--- a/arch/arm/src/common/stm32/stm32_mpuinit.h
+++ b/arch/arm/src/common/stm32/stm32_mpuinit.h
@@ -42,7 +42,7 @@
*
****************************************************************************/
-#ifdef CONFIG_BUILD_PROTECTED
+#if defined(CONFIG_BUILD_PROTECTED) || defined(CONFIG_ARM_MPU)
void stm32_mpuinitialize(void);
#else
# define stm32_mpuinitialize()
diff --git a/arch/arm/src/stm32h5/stm32_mpuinit.c b/arch/arm/src/common/stm32/stm32_mpuinit_m33_v1.c
similarity index 97%
rename from arch/arm/src/stm32h5/stm32_mpuinit.c
rename to arch/arm/src/common/stm32/stm32_mpuinit_m33_v1.c
index ba98332269c..360bf8b2df4 100644
--- a/arch/arm/src/stm32h5/stm32_mpuinit.c
+++ b/arch/arm/src/common/stm32/stm32_mpuinit_m33_v1.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32h5/stm32_mpuinit.c
+ * arch/arm/src/common/stm32/stm32_mpuinit_m33_v1.c
*
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/arch/arm/src/common/stm32/stm32_start.h b/arch/arm/src/common/stm32/stm32_start.h
index ad9bbda5e31..14343e4eb75 100644
--- a/arch/arm/src/common/stm32/stm32_start.h
+++ b/arch/arm/src/common/stm32/stm32_start.h
@@ -56,6 +56,17 @@ extern "C"
void stm32_boardinitialize(void);
+/****************************************************************************
+ * Name: stm32_board_initialize
+ *
+ * Description:
+ * Board-specific initialization called by the common Cortex-M33 start
+ * logic after the chip and early serial have been set up.
+ *
+ ****************************************************************************/
+
+void stm32_board_initialize(void);
+
#ifdef __cplusplus
}
#endif
diff --git a/arch/arm/src/common/stm32/stm32_start_m33_v1.c b/arch/arm/src/common/stm32/stm32_start_m33_v1.c
index 26e0a8d43ec..9583d3a03f8 100644
--- a/arch/arm/src/common/stm32/stm32_start_m33_v1.c
+++ b/arch/arm/src/common/stm32/stm32_start_m33_v1.c
@@ -37,13 +37,14 @@
#include "nvic.h"
#include "stm32.h"
-#include "stm32_gpio.h"
#include "stm32_start.h"
#ifdef CONFIG_BUILD_PROTECTED
# include "stm32_userspace.h"
#endif
+#include "stm32_mpuinit.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -60,6 +61,11 @@
# define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE)
#endif
+#ifdef CONFIG_STM32_SRAM3_INIT
+# define SRAM3_START STM32_SRAM3_BASE
+# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE)
+#endif
+
#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
@@ -162,6 +168,13 @@ void __start(void)
}
#endif
+#ifdef CONFIG_STM32_SRAM3_INIT
+ for (dest = (uint32_t *)SRAM3_START; dest < (uint32_t *)SRAM3_END; )
+ {
+ *dest++ = 0;
+ }
+#endif
+
/* Configure clocks, the FPU, GPIO and the debug UART only after .data and
* .bss are valid. GPIO configuration uses a spinlock stored in .bss.
*/
@@ -187,6 +200,14 @@ void __start(void)
#endif
showprogress('B');
+ /* Configure the MPU in a flat build. Protected builds do this from
+ * stm32_userspace().
+ */
+
+#if defined(CONFIG_ARM_MPU) && !defined(CONFIG_BUILD_PROTECTED)
+ stm32_mpuinitialize();
+#endif
+
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
@@ -201,6 +222,24 @@ void __start(void)
/* Initialize onboard resources */
stm32_board_initialize();
+
+#ifdef CONFIG_STM32_ICACHE
+ stm32_enable_icache();
+#elif defined(CONFIG_STM32_HAVE_ICACHE)
+ /* Disable an ICACHE left enabled by a bootloader: the OTP and RO flash
+ * areas cannot be read through it (RM0481 7.3.2).
+ */
+
+ if ((getreg32(STM32_ICACHE_CR) & ICACHE_CR_EN) != 0)
+ {
+ uint32_t regval;
+
+ regval = getreg32(STM32_ICACHE_CR);
+ regval &= ~(ICACHE_CR_EN);
+ putreg32(regval, STM32_ICACHE_CR);
+ }
+
+#endif
showprogress('D');
/* Then start NuttX */
diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt
index 2ba3d3f6e8d..6598f35ea90 100644
--- a/arch/arm/src/stm32h5/CMakeLists.txt
+++ b/arch/arm/src/stm32h5/CMakeLists.txt
@@ -38,12 +38,9 @@ list(
APPEND
SRCS
stm32_gpio.c
- stm32_irq.c
stm32_lowputc.c
stm32_rcc.c
- stm32_start.c
stm32_pwr.c
- stm32_timerisr.c
stm32_lse.c
stm32_lsi.c
stm32_exti_gpio.c
@@ -53,10 +50,6 @@ if(CONFIG_STM32_USART)
list(APPEND SRCS stm32_serial.c)
endif()
-if(NOT CONFIG_ARCH_IDLE_CUSTOM)
- list(APPEND SRCS stm32_idle.c)
-endif()
-
if(CONFIG_TIMER)
list(APPEND SRCS stm32_tim_lowerhalf.c)
endif()
@@ -137,10 +130,6 @@ if(CONFIG_STM32_IWDG)
list(APPEND SRCS stm32_iwdg.c)
endif()
-if(CONFIG_ARM_MPU)
- list(APPEND SRCS stm32_mpuinit.c)
-endif()
-
# Required chip type specific files
if(CONFIG_STM32_STM32H5XXXX)
diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs
index 2488ff9f82a..ad800675824 100644
--- a/arch/arm/src/stm32h5/Make.defs
+++ b/arch/arm/src/stm32h5/Make.defs
@@ -40,14 +40,10 @@ endif
# Required STM32H5 files
-CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c
-CHIP_CSRCS += stm32_start.c stm32_pwr.c stm32_timerisr.c
+CHIP_CSRCS += stm32_gpio.c stm32_lowputc.c stm32_rcc.c
+CHIP_CSRCS += stm32_pwr.c
CHIP_CSRCS += stm32_lse.c stm32_lsi.c stm32_exti_gpio.c stm32_sdmmc.c
-ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
-CHIP_CSRCS += stm32_idle.c
-endif
-
ifeq ($(CONFIG_STM32_USART),y)
CHIP_CSRCS += stm32_serial.c
endif
@@ -139,10 +135,6 @@ ifeq ($(CONFIG_STM32_IWDG),y)
CHIP_CSRCS += stm32_iwdg.c
endif
-ifeq ($(CONFIG_ARM_MPU),y)
-CHIP_CSRCS += stm32_mpuinit.c
-endif
-
ifeq ($(CONFIG_STM32_WWDG),y)
CHIP_CSRCS += stm32_wwdg.c
endif
diff --git a/arch/arm/src/stm32h5/stm32_idle.c b/arch/arm/src/stm32h5/stm32_idle.c
deleted file mode 100644
index 5cc08c4759b..00000000000
--- a/arch/arm/src/stm32h5/stm32_idle.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/****************************************************************************
- * arch/arm/src/stm32h5/stm32_idle.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <arch/board/board.h>
-#include <nuttx/config.h>
-#include <nuttx/debug.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/irq.h>
-#include <nuttx/board.h>
-#include <nuttx/power/pm.h>
-
-#include "chip.h"
-#include "stm32_rcc.h"
-#include "arm_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Does the board support an IDLE LED to indicate that the board is in the
- * IDLE state?
- */
-
-#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
-# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
-# define END_IDLE() board_autoled_off(LED_IDLE)
-#else
-# define BEGIN_IDLE()
-# define END_IDLE()
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-#define up_idlepm()
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_idle
- *
- * Description:
- * up_idle() is the logic that will be executed when their is no other
- * ready-to-run task. This is processor idle time and will continue until
- * some interrupt occurs to cause a context switch from the idle task.
- *
- * Processing in this state may be processor-specific. e.g., this is where
- * power management operations might be performed.
- *
- ****************************************************************************/
-
-void up_idle(void)
-{
-#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
- /* If the system is idle and there are no timer interrupts, then process
- * "fake" timer interrupts. Hopefully, something will wake up.
- */
-
- nxsched_process_timer();
-#else
-
- /* Perform IDLE mode power management */
-
- up_idlepm();
-
- /* Sleep until an interrupt occurs to save power. */
-
-#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
- BEGIN_IDLE();
- asm("WFI");
- END_IDLE();
-#endif
-
-#endif
-}
diff --git a/arch/arm/src/stm32h5/stm32_irq.c b/arch/arm/src/stm32h5/stm32_irq.c
deleted file mode 100644
index 41bcdec41a0..00000000000
--- a/arch/arm/src/stm32h5/stm32_irq.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/****************************************************************************
- * arch/arm/src/stm32h5/stm32_irq.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <assert.h>
-
-#include <nuttx/debug.h>
-#include <nuttx/irq.h>
-#include <nuttx/arch.h>
-#include <arch/irq.h>
-#include <arch/armv8-m/nvicpri.h>
-
-#include "nvic.h"
-#include "ram_vectors.h"
-#include "arm_internal.h"
-#include "stm32.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Get a 32-bit version of the default priority */
-
-#define DEFPRIORITY32 \
- (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
- NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
- NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
- NVIC_SYSH_PRIORITY_DEFAULT)
-
-/* Given the address of a NVIC ENABLE register, this is the offset to
- * the corresponding CLEAR ENABLE register.
- */
-
-#define NVIC_ENA_OFFSET (0)
-#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: stm32_dumpnvic
- *
- * Description:
- * Dump some interesting NVIC registers
- *
- ****************************************************************************/
-
-#if defined(CONFIG_DEBUG_IRQ_INFO)
-static void stm32_dumpnvic(const char *msg, int irq)
-{
- irqstate_t flags;
-
- flags = enter_critical_section();
-
- irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
- irqinfo(" INTCTRL: %08" PRIx32 " VECTAB: %08" PRIx32 "\n",
- getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
- irqinfo(" IRQ ENABLE: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n",
- getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
- getreg32(NVIC_IRQ64_95_ENABLE));
- irqinfo(" SYSH_PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n",
- getreg32(NVIC_SYSH4_7_PRIORITY),
- getreg32(NVIC_SYSH8_11_PRIORITY),
- getreg32(NVIC_SYSH12_15_PRIORITY));
- irqinfo(" IRQ PRIO: %08" PRIx32 " %08" PRIx32
- " %08" PRIx32 " %08" PRIx32 "\n",
- getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
- getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
- irqinfo(" %08" PRIx32 " %08" PRIx32
- " %08" PRIx32 " %08" PRIx32 "\n",
- getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
- getreg32(NVIC_IRQ24_27_PRIORITY),
- getreg32(NVIC_IRQ28_31_PRIORITY));
- irqinfo(" %08" PRIx32 " %08" PRIx32
- " %08" PRIx32 " %08" PRIx32 "\n",
- getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
- getreg32(NVIC_IRQ40_43_PRIORITY),
- getreg32(NVIC_IRQ44_47_PRIORITY));
- irqinfo(" %08" PRIx32 " %08" PRIx32
- " %08" PRIx32 " %08" PRIx32 "\n",
- getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
- getreg32(NVIC_IRQ56_59_PRIORITY),
- getreg32(NVIC_IRQ60_63_PRIORITY));
- irqinfo(" %08" PRIx32 "\n",
- getreg32(NVIC_IRQ64_67_PRIORITY));
-
- leave_critical_section(flags);
-}
-#else
-# define stm32_dumpnvic(msg, irq)
-#endif
-
-/****************************************************************************
- * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved
- *
- * Description:
- * Handlers for various exceptions. None are handled and all are fatal
- * error conditions. The only advantage these provide over the default
- * unexpected interrupt handler is that they provide a diagnostic output.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_FEATURES
-static int stm32_nmi(int irq, void *context, void *arg)
-{
- up_irq_save();
- _err("PANIC!!! NMI received\n");
- PANIC();
- return 0;
-}
-
-static int stm32_pendsv(int irq, void *context, void *arg)
-{
- up_irq_save();
- _err("PANIC!!! PendSV received\n");
- PANIC();
- return 0;
-}
-
-static int stm32_reserved(int irq, void *context, void *arg)
-{
- up_irq_save();
- _err("PANIC!!! Reserved interrupt\n");
- PANIC();
- return 0;
-}
-#endif
-
-/****************************************************************************
- * Name: stm32_prioritize_syscall
- *
- * Description:
- * Set the priority of an exception. This function may be needed
- * internally even if support for prioritized interrupts is not enabled.
- *
- ****************************************************************************/
-
-static inline void stm32_prioritize_syscall(int priority)
-{
- uint32_t regval;
-
- /* SVCALL is system handler 11 */
-
- regval = getreg32(NVIC_SYSH8_11_PRIORITY);
- regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
- regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
- putreg32(regval, NVIC_SYSH8_11_PRIORITY);
-}
-
-/****************************************************************************
- * Name: stm32_irqinfo
- *
- * Description:
- * Given an IRQ number, provide the register and bit setting to enable or
- * disable the irq.
- *
- ****************************************************************************/
-
-static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
- uintptr_t offset)
-{
- int n;
-
- DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
-
- /* Check for external interrupt */
-
- if (irq >= STM32_IRQ_FIRST)
- {
- n = irq - STM32_IRQ_FIRST;
- *regaddr = NVIC_IRQ_ENABLE(n) + offset;
- *bit = (uint32_t)1 << (n & 0x1f);
- }
-
- /* Handle processor exceptions. Only a few can be disabled */
-
- else
- {
- *regaddr = NVIC_SYSHCON;
- if (irq == STM32_IRQ_MEMFAULT)
- {
- *bit = NVIC_SYSHCON_MEMFAULTENA;
- }
- else if (irq == STM32_IRQ_BUSFAULT)
- {
- *bit = NVIC_SYSHCON_BUSFAULTENA;
- }
- else if (irq == STM32_IRQ_USAGEFAULT)
- {
- *bit = NVIC_SYSHCON_USGFAULTENA;
- }
- else if (irq == STM32_IRQ_SYSTICK)
- {
- *regaddr = NVIC_SYSTICK_CTRL;
- *bit = NVIC_SYSTICK_CTRL_ENABLE;
- }
- else
- {
- return ERROR; /* Invalid or unsupported exception */
- }
- }
-
- return OK;
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_irqinitialize
- ****************************************************************************/
-
-void up_irqinitialize(void)
-{
- uint32_t regaddr;
- int num_priority_registers;
- int i;
-
- /* Disable all interrupts */
-
- for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32)
- {
- putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
- }
-
- /* The standard location for the vector table is at the beginning of FLASH
- * at address 0x0800:0000. If we are using the STMicro DFU bootloader,
- * then the vector table will be offset to a different location in FLASH
- * and we will need to set the NVIC vector location to this alternative
- * location.
- */
-
- putreg32((uint32_t)_vectors, NVIC_VECTAB);
-
-#ifdef CONFIG_ARCH_RAMVECTORS
- /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
- * vector table that requires special initialization.
- */
-
- up_ramvec_initialize();
-#endif
-
- /* Set all interrupts (and exceptions) to the default priority */
-
- putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
- putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
-
- /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
- * lines that the NVIC supports:
- *
- * 0 -> 32 interrupt lines, 8 priority registers
- * 1 -> 64 " " " ", 16 priority registers
- * 2 -> 96 " " " ", 32 priority registers
- * ...
- */
-
- num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
-
- /* Now set all of the interrupt lines to the default priority */
-
- regaddr = NVIC_IRQ0_3_PRIORITY;
- while (num_priority_registers--)
- {
- putreg32(DEFPRIORITY32, regaddr);
- regaddr += 4;
- }
-
- /* Attach the SVCall and Hard Fault exception handlers. The SVCall
- * exception is used for performing context switches; The Hard Fault
- * must also be caught because a SVCall may show up as a Hard Fault
- * under certain conditions.
- */
-
- irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL);
- irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL);
-
- /* Set the priority of the SVCall interrupt */
-
-#ifdef CONFIG_ARCH_IRQPRIO
-
- /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
-
-#endif
-
- stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
-
- /* If the MPU is enabled, then attach and enable the Memory Management
- * Fault handler.
- */
-
-#ifdef CONFIG_ARM_MPU
- irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
- up_enable_irq(STM32_IRQ_MEMFAULT);
-#endif
-
- /* Attach all other processor exceptions (except reset and sys tick) */
-
-#ifdef CONFIG_DEBUG_FEATURES
- irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL);
-#ifndef CONFIG_ARM_MPU
- irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
-#endif
- irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL);
- irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL);
- irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL);
- arm_enable_dbgmonitor();
- irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
- irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL);
-#endif
-
- stm32_dumpnvic("initial", NR_IRQS);
-
-#ifndef CONFIG_SUPPRESS_INTERRUPTS
-
- /* And finally, enable interrupts */
-
- arm_color_intstack();
- up_irq_enable();
-#endif
-}
-
-/****************************************************************************
- * Name: up_disable_irq
- *
- * Description:
- * Disable the IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void up_disable_irq(int irq)
-{
- uintptr_t regaddr;
- uint32_t regval;
- uint32_t bit;
-
- if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0)
- {
- /* Modify the appropriate bit in the register to disable the interrupt.
- * For normal interrupts, we need to set the bit in the associated
- * Interrupt Clear Enable register. For other exceptions, we need to
- * clear the bit in the System Handler Control and State Register.
- */
-
- if (irq >= STM32_IRQ_FIRST)
- {
- putreg32(bit, regaddr);
- }
- else
- {
- regval = getreg32(regaddr);
- regval &= ~bit;
- putreg32(regval, regaddr);
- }
- }
-}
-
-/****************************************************************************
- * Name: up_enable_irq
- *
- * Description:
- * Enable the IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void up_enable_irq(int irq)
-{
- uintptr_t regaddr;
- uint32_t regval;
- uint32_t bit;
-
- if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0)
- {
- /* Modify the appropriate bit in the register to enable the interrupt.
- * For normal interrupts, we need to set the bit in the associated
- * Interrupt Set Enable register. For other exceptions, we need to
- * set the bit in the System Handler Control and State Register.
- */
-
- if (irq >= STM32_IRQ_FIRST)
- {
- putreg32(bit, regaddr);
- }
- else
- {
- regval = getreg32(regaddr);
- regval |= bit;
- putreg32(regval, regaddr);
- }
- }
-}
-
-/****************************************************************************
- * Name: arm_ack_irq
- *
- * Description:
- * Acknowledge the IRQ
- *
- ****************************************************************************/
-
-void arm_ack_irq(int irq)
-{
-}
-
-/****************************************************************************
- * Name: up_prioritize_irq
- *
- * Description:
- * Set the priority of an IRQ.
- *
- * Since this API is not supported on all architectures, it should be
- * avoided in common implementations where possible.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_IRQPRIO
-int up_prioritize_irq(int irq, int priority)
-{
- uint32_t regaddr;
- uint32_t regval;
- int shift;
-
- DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
- (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
-
- if (irq < STM32_IRQ_FIRST)
- {
- /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
- * registers (0-3 are invalid)
- */
-
- regaddr = NVIC_SYSH_PRIORITY(irq);
- irq -= 4;
- }
- else
- {
- /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
-
- irq -= STM32_IRQ_FIRST;
- regaddr = NVIC_IRQ_PRIORITY(irq);
- }
-
- regval = getreg32(regaddr);
- shift = ((irq & 3) << 3);
- regval &= ~(0xff << shift);
- regval |= (priority << shift);
- putreg32(regval, regaddr);
-
- stm32_dumpnvic("prioritize", irq);
- return OK;
-}
-#endif
diff --git a/arch/arm/src/stm32h5/stm32_mpuinit.h b/arch/arm/src/stm32h5/stm32_mpuinit.h
deleted file mode 100644
index fc1cba96cdc..00000000000
--- a/arch/arm/src/stm32h5/stm32_mpuinit.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/****************************************************************************
- * arch/arm/src/stm32h5/stm32_mpuinit.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STM32H5_STM32_MPUINIT_H
-#define __ARCH_ARM_SRC_STM32H5_STM32_MPUINIT_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: stm32_mpuinitialize
- *
- * Description:
- * Configure the MPU.
- *
- * For FLAT build:
- * - just reset and enable the MPU with the default background region.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARM_MPU
-void stm32_mpuinitialize(void);
-#else
-# define stm32_mpuinitialize()
-#endif
-
-#endif /* __ARCH_ARM_SRC_STM32H5_STM32_MPUINIT_H */
diff --git a/arch/arm/src/stm32h5/stm32_rcc.h b/arch/arm/src/stm32h5/stm32_rcc_m33.h
similarity index 97%
rename from arch/arm/src/stm32h5/stm32_rcc.h
rename to arch/arm/src/stm32h5/stm32_rcc_m33.h
index ac95eadf5b9..19589c06f37 100644
--- a/arch/arm/src/stm32h5/stm32_rcc.h
+++ b/arch/arm/src/stm32h5/stm32_rcc_m33.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32h5/stm32_rcc.h
+ * arch/arm/src/stm32h5/stm32_rcc_m33.h
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -20,8 +20,8 @@
*
****************************************************************************/
-#ifndef __ARCH_ARM_SRC_STM32H5_STM32_RCC_H
-#define __ARCH_ARM_SRC_STM32H5_STM32_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32H5_STM32_RCC_M33_H
+#define __ARCH_ARM_SRC_STM32H5_STM32_RCC_M33_H
/****************************************************************************
* Included Files
@@ -254,4 +254,4 @@ void stm32_rcc_enableperipherals(void);
}
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_STM32H5_STM32_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32H5_STM32_RCC_M33_H */
diff --git a/arch/arm/src/stm32h5/stm32_start.c b/arch/arm/src/stm32h5/stm32_start.c
deleted file mode 100644
index 403125ae88c..00000000000
--- a/arch/arm/src/stm32h5/stm32_start.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/****************************************************************************
- * arch/arm/src/stm32h5/stm32_start.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <assert.h>
-#include <nuttx/debug.h>
-
-#include <nuttx/init.h>
-#include <arch/board/board.h>
-
-#include "arm_internal.h"
-#include "nvic.h"
-
-#include "stm32.h"
-#include "stm32_gpio.h"
-#include "stm32_start.h"
-
-#ifdef CONFIG_ARM_MPU
-# include "stm32_mpuinit.h"
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* STM32H523/533 Memory Map *************************************************/
-
-/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
- * Mapped as boot memory address 0x0000:0000 at reset.
- * 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
- * 0x2000:0000 - Start of internal SRAM1 and start of .data (_sdata)
- * - End of .data (_edata) and start of .bss (_sbss)
- * - End of .bss (_ebss) and bottom of idle stack
- * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
- * start of heap. NOTE that the ARM uses a decrement before
- * store stack so that the correct initial value is the end of
- * the stack + 4;
- * 0x2003:ffff - End of internal SRAM1
- * 0x2004:0000 - Start of internal SRAM2
- * 0x2004:ffff - End of internal SRAM2
- * 0x2005:0000 - Start of internal SRAM3
- * 0x2009:ffff - End of internal SRAM3
- */
-
-/* STM32H562/563/573 Memory Map *********************************************/
-
-/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
- * Mapped as boot memory address 0x0000:0000 at reset.
- * 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
- * 0x2000:0000 - Start of internal SRAM1 and start of .data (_sdata)
- * - End of .data (_edata) and start of .bss (_sbss)
- * - End of .bss (_ebss) and bottom of idle stack
- * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
- * start of heap. NOTE that the ARM uses a decrement before
- * store stack so that the correct initial value is the end of
- * the stack + 4;
- * 0x2001:ffff - End of internal SRAM1
- * 0x2002:0000 - Start of internal SRAM2
- * 0x2002:ffff - End of internal SRAM2
- * 0x2003:0000 - Start of internal SRAM3
- * 0x2003:ffff - End of internal SRAM3
- */
-
-#define SRAM2_START STM32_SRAM2_BASE
-#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE)
-
-#define SRAM3_START STM32_SRAM3_BASE
-#define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE)
-
-#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-const uintptr_t g_idle_topstack = HEAP_BASE;
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: showprogress
- *
- * Description:
- * Print a character on the UART to show boot status.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_DEBUG_FEATURES
-# define showprogress(c) arm_lowputc(c)
-#else
-# define showprogress(c)
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-#ifdef CONFIG_ARMV8M_STACKCHECK
-/* we need to get r10 set before we can allow instrumentation calls */
-
-void __start(void) noinstrument_function;
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: __start
- *
- * Description:
- * This is the reset entry point.
- *
- ****************************************************************************/
-
-void __start(void)
-{
- const uint32_t *src;
- uint32_t *dest;
-
-#ifdef CONFIG_ARMV8M_STACKCHECK
- /* Set the stack limit before we attempt to call any functions */
-
- __asm__ volatile
- ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :);
-#endif
-
- /* Clear .bss. We'll do this inline (vs. calling memset) just to be
- * certain that there are no issues with the state of global variables.
- */
-
- for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
- {
- *dest++ = 0;
- }
-
- /* Move the initialized data section from his temporary holding spot in
- * FLASH into the correct place in SRAM. The correct place in SRAM is
- * give by _sdata and _edata. The temporary location is in FLASH at the
- * end of all of the other read-only data (.text, .rodata) at _eronly.
- */
-
- for (src = (const uint32_t *)_eronly,
- dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata;
- )
- {
- *dest++ = *src++;
- }
-
-#ifdef CONFIG_STM32_SRAM2_INIT
- /* NOTE: this is optional because this may be inappropriate, especially
- * if the memory is being used for it's battery backed purpose. In that
- * case, the first-time initialization needs to be performed by the board
- * under application-specific circumstances. On the other hand, if we're
- * using this memory for, say, additional heap space, then this is handy.
- */
-
- for (dest = (uint32_t *)SRAM2_START; dest < (uint32_t *)SRAM2_END; )
- {
- *dest++ = 0;
- }
-#endif
-
-#ifdef CONFIG_STM32_SRAM3_INIT
- for (dest = (uint32_t *)SRAM3_START; dest < (uint32_t *)SRAM3_END; )
- {
- *dest++ = 0;
- }
-#endif
-
- /* Configure the UART so that we can get debug output as soon as possible */
-
- stm32_clockconfig();
- arm_fpuconfig();
- stm32_lowsetup();
- stm32_gpioinit();
- showprogress('A');
-
-#ifdef CONFIG_ARMV8M_STACKCHECK
- arm_stack_check_init();
-#endif
-
-#ifdef CONFIG_ARCH_PERF_EVENTS
- up_perf_init((void *)STM32_SYSCLK_FREQUENCY);
-#endif
-
- /* Perform early serial initialization */
-
-#ifdef USE_EARLYSERIALINIT
- arm_earlyserialinit();
-#endif
- showprogress('B');
-
- /* Configure the MPU to permit user-space access to its FLASH and RAM (for
- * CONFIG_BUILD_PROTECTED) or to manage cache properties of external
- * memory regions (in a flat build).
- */
-
-#ifdef CONFIG_ARM_MPU
- stm32_mpuinitialize();
-#endif
-
- /* Initialize onboard resources */
-
- stm32_board_initialize();
- showprogress('C');
-
-#ifdef CONFIG_STM32_ICACHE
- stm32_enable_icache();
-#else
- /* Disable an ICACHE left enabled by a bootloader: the OTP and RO flash
- * areas cannot be read through it (RM0481 7.3.2).
- */
-
- if ((getreg32(STM32_ICACHE_CR) & ICACHE_CR_EN) != 0)
- {
- uint32_t regval;
-
- regval = getreg32(STM32_ICACHE_CR);
- regval &= ~(ICACHE_CR_EN);
- putreg32(regval, STM32_ICACHE_CR);
- }
-
-#endif
- showprogress('G');
-
- /* Then start NuttX */
-
- showprogress('\r');
- showprogress('\n');
-
- nx_start();
-
- /* Shouldn't get here */
-
- for (; ; );
-}
diff --git a/arch/arm/src/stm32h5/stm32_start.h b/arch/arm/src/stm32h5/stm32_start.h
deleted file mode 100644
index 07b08a4419c..00000000000
--- a/arch/arm/src/stm32h5/stm32_start.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/****************************************************************************
- * arch/arm/src/stm32h5/stm32_start.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STM32H5_STM32_START_H
-#define __ARCH_ARM_SRC_STM32H5_STM32_START_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: stm32_board_initialize
- *
- * Description:
- * All STM32H5 architectures must provide the following entry point. This
- * entry point is called early in the initialization -- after all memory
- * has been configured and mapped but before any devices have been
- * initialized.
- *
- ****************************************************************************/
-
-void stm32_board_initialize(void);
-
-#endif /* __ARCH_ARM_SRC_STM32H5_STM32_START_H */
diff --git a/arch/arm/src/stm32h5/stm32_timerisr.c b/arch/arm/src/stm32h5/stm32_timerisr.c
deleted file mode 100644
index d985e469cfc..00000000000
--- a/arch/arm/src/stm32h5/stm32_timerisr.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/****************************************************************************
- * arch/arm/src/stm32h5/stm32_timerisr.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdint.h>
-#include <time.h>
-
-#include <nuttx/debug.h>
-#include <nuttx/arch.h>
-#include <arch/board/board.h>
-
-#include "nvic.h"
-#include "clock/clock.h"
-#include "arm_internal.h"
-#include "chip.h"
-#include "stm32.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* The desired timer interrupt frequency is provided by the definition
- * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
- * system clock ticks per second. That value is a user configurable setting
- * that defaults to 100 (100 ticks per second = 10 MS interval).
- *
- * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
- * divided by 8. The SysTick can work either with this clock or with the
- * Cortex clock (HCLK), configurable in the SysTick Control and Status
- * register.
- */
-
-/* Power up default is HCLK, not HCLK/8.
- * And I don't know now to re-configure it yet
- */
-
-#undef CONFIG_STM32_SYSTICK_HCLKd8
-
-#ifdef CONFIG_STM32_SYSTICK_HCLKd8
-# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
-#else
-# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
-#endif
-
-/* The size of the reload field is 24 bits. Verify that the reload value
- * will fit in the reload register.
- */
-
-#if SYSTICK_RELOAD > 0x00ffffff
-# error SYSTICK_RELOAD exceeds the range of the RELOAD register
-#endif
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function: stm32_timerisr
- *
- * Description:
- * The timer ISR will perform a variety of services for various portions
- * of the systems.
- *
- ****************************************************************************/
-
-static int stm32_timerisr(int irq, uint32_t *regs, void *arg)
-{
- /* Process timer interrupt */
-
- nxsched_process_timer();
- return 0;
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function: up_timer_initialize
- *
- * Description:
- * This function is called during start-up to initialize
- * the timer interrupt.
- *
- ****************************************************************************/
-
-void up_timer_initialize(void)
-{
- uint32_t regval;
-
- /* Set the SysTick interrupt to the default priority */
-
- regval = getreg32(NVIC_SYSH12_15_PRIORITY);
- regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
- regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
- putreg32(regval, NVIC_SYSH12_15_PRIORITY);
-
- /* Make sure that the SYSTICK clock source is set correctly */
-
-#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
- regval = getreg32(NVIC_SYSTICK_CTRL);
-#ifdef CONFIG_STM32_SYSTICK_HCLKd8
- regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
-#else
- regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
-#endif
- putreg32(regval, NVIC_SYSTICK_CTRL);
-#endif
-
- /* Configure SysTick to interrupt at the requested rate */
-
- putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
-
- /* Attach the timer interrupt vector */
-
- irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);
-
- /* Enable SysTick interrupts */
-
- putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
- NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
-
- /* And enable the timer interrupt */
-
- up_enable_irq(STM32_IRQ_SYSTICK);
-}