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Posted to commits@nuttx.apache.org by ac...@apache.org on 2022/05/07 14:52:56 UTC
[incubator-nuttx] branch master updated: Added functionality for Audio support with the STM32F746 Discoboard In particular additions to wm8994.h and filled functionality into wm8994.c.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 476770e9fd Added functionality for Audio support with the STM32F746 Discoboard In particular additions to wm8994.h and filled functionality into wm8994.c.
476770e9fd is described below
commit 476770e9fde74cc9c75fda0971880fea3b90722a
Author: okayserh <o....@gmail.com>
AuthorDate: Sat Apr 30 11:10:12 2022 +0200
Added functionality for Audio support with the STM32F746 Discoboard
In particular additions to wm8994.h and filled functionality into
wm8994.c.
Resolved a few more remarks from review.
---
arch/arm/src/stm32f7/stm32_sai.c | 55 +-
arch/arm/src/stm32f7/stm32_sai.h | 6 +-
.../arm/stm32f7/stm32f746g-disco/include/board.h | 4 +-
.../stm32f7/stm32f746g-disco/src/stm32_wm8994.c | 109 +-
drivers/audio/wm8994.c | 971 +++++++++++++-
drivers/audio/wm8994.h | 1360 ++++++++++++--------
6 files changed, 1841 insertions(+), 664 deletions(-)
diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c
index 07370c85f3..7d5175bbbc 100644
--- a/arch/arm/src/stm32f7/stm32_sai.c
+++ b/arch/arm/src/stm32f7/stm32_sai.c
@@ -63,6 +63,7 @@
#include "stm32_dma.h"
#include "stm32_gpio.h"
#include "stm32_sai.h"
+#include "stm32_pwr.h"
#ifdef CONFIG_STM32F7_SAI
@@ -146,41 +147,19 @@
# define SAI_RXDMA16_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \
DMA_SCR_PSIZE_16BITS | DMA_SCR_MSIZE_16BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
-
# define SAI_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
-# define SAI_TXDMA8_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
+
+# define SAI_TXDMA8_CONFIG (DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
-# define SAI_TXDMA16_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
- DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
+# define SAI_TXDMA16_CONFIG (DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
+ DMA_SCR_PSIZE_16BITS | DMA_SCR_MSIZE_16BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
-
-# define SAI_TXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
+# define SAI_TXDMA32_CONFIG (DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4)
-
-#endif
-
-#ifdef DMAMAP_SAI1
-
-/* SAI DMA Channel/Stream selection. There
- * are multiple DMA stream options that must be dis-ambiguated in the board.h
- * file.
- */
-
-# define SAI1_DMACHAN DMAMAP_SAI1
-#endif
-
-#ifdef DMAMAP_SAI2
-
-/* SAI DMA Channel/Stream selection. There
- * are multiple DMA stream options that must be dis-ambiguated in the board.h
- * file.
- */
-
-# define SAI2_DMACHAN DMAMAP_SAI2
#endif
/****************************************************************************
@@ -204,6 +183,10 @@ struct sai_buffer_s
struct stm32f7_sai_s
{
struct i2s_dev_s dev; /* Externally visible I2S interface */
+
+ /* Callback for changes in sample rate */
+
+ stm32_sai_sampleratecb_t sampleratecb;
uintptr_t base; /* SAI block register base address */
sem_t exclsem; /* Assures mutually exclusive access to SAI */
uint32_t frequency; /* SAI clock frequency */
@@ -1151,6 +1134,17 @@ static uint32_t sai_samplerate(struct i2s_dev_s *dev, uint32_t rate)
DEBUGASSERT(priv && rate > 0);
+ /* Call callback to change system clock (needed for STM32F746 Disco) */
+
+ if (priv->sampleratecb != NULL)
+ {
+ priv->frequency = priv->sampleratecb(dev, rate);
+ }
+ else
+ {
+ i2sinfo("No Sample Rate CB set!\n");
+ }
+
/* Save the new sample rate and update the divider */
priv->samplerate = rate;
@@ -1638,7 +1632,8 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv)
*
****************************************************************************/
-struct i2s_dev_s *stm32_sai_initialize(int intf)
+struct i2s_dev_s *stm32_sai_initialize(int intf,
+ stm32_sai_sampleratecb_t sampleratecb)
{
struct stm32f7_sai_s *priv;
irqstate_t flags;
@@ -1652,6 +1647,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf)
{
i2sinfo("SAI1 Block A Selected\n");
priv = &g_sai1a_priv;
+ priv->sampleratecb = sampleratecb;
stm32_configgpio(GPIO_SAI1_SD_A);
# ifndef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B
@@ -1668,6 +1664,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf)
{
i2sinfo("SAI1 Block B Selected\n");
priv = &g_sai1b_priv;
+ priv->sampleratecb = sampleratecb;
stm32_configgpio(GPIO_SAI1_SD_B);
# ifndef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A
@@ -1684,6 +1681,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf)
{
i2sinfo("SAI2 Block A Selected\n");
priv = &g_sai2a_priv;
+ priv->sampleratecb = sampleratecb;
stm32_configgpio(GPIO_SAI2_SD_A);
# ifndef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B
@@ -1700,6 +1698,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf)
{
i2sinfo("SAI2 Block B Selected\n");
priv = &g_sai2b_priv;
+ priv->sampleratecb = sampleratecb;
stm32_configgpio(GPIO_SAI2_SD_B);
# ifndef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A
diff --git a/arch/arm/src/stm32f7/stm32_sai.h b/arch/arm/src/stm32f7/stm32_sai.h
index 9338558a72..23ff0f8741 100644
--- a/arch/arm/src/stm32f7/stm32_sai.h
+++ b/arch/arm/src/stm32f7/stm32_sai.h
@@ -69,6 +69,9 @@ extern "C"
#define EXTERN extern
#endif
+typedef uint32_t (*stm32_sai_sampleratecb_t)(struct i2s_dev_s *dev,
+ uint32_t rate);
+
/****************************************************************************
* Name: stm32_sai_initialize
*
@@ -83,7 +86,8 @@ extern "C"
*
****************************************************************************/
-struct i2s_dev_s *stm32_sai_initialize(int intf);
+struct i2s_dev_s *stm32_sai_initialize(int intf,
+ stm32_sai_sampleratecb_t sampleratecb);
#undef EXTERN
#ifdef __cplusplus
diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h
index 44de107483..cde768f798 100644
--- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h
+++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h
@@ -158,8 +158,8 @@
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(0)
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1)
-#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
-#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
+#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(1)
+#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(1)
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_wm8994.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_wm8994.c
index 25337149e4..2cf5b1f944 100644
--- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_wm8994.c
+++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_wm8994.c
@@ -33,13 +33,18 @@
#include <nuttx/irq.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/audio/i2s.h>
+#include <nuttx/audio/pcm.h>
#include <nuttx/audio/wm8994.h>
#include <arch/board/board.h>
+#include "chip.h"
+
#include "stm32f746g-disco.h"
#include "stm32_i2c.h"
#include "stm32_sai.h"
+#include "stm32_pwr.h"
+#include "stm32_rcc.h"
#define HAVE_WM8994
#define WM8994_I2C_ADDRESS (0x34 >> 1)
@@ -112,6 +117,88 @@ static struct stm32_mwinfo_s g_wm8994 =
* Public Functions
****************************************************************************/
+static uint32_t stm32_wm8994_sampleratecb(struct i2s_dev_s *dev,
+ uint32_t rate)
+{
+ uint32_t frequency = 0;
+ uint32_t regval = 0;
+ uint32_t mask_divq = 0;
+ uint32_t mask_i2s = 0;
+
+ /* Table 210 in "STM32F75xxx and STM32F74xxx advanced Arm(r)-based 32-bit
+ * MCUs - Reference manual" suggests the use of specific sai_x_ker_ck
+ * frequencies for common audio sample frequencies:
+ * For 44.1, 22.05, 11.025 KHz, 44.1 kHz * 256 = 11289600 Hz
+ * For 192, 96, 48, 32, 16, 8 KHz, 192 kHz * 256 = 49152000 Hz
+ *
+ * The below configurations use 429000000 / 19 / 2 = 1128473.x
+ * as approximation for the first group of sample frequencies and
+ * 344000000 / 1 / 7 = 49142857.x as approximation for the second
+ * group of sample frequencies
+ */
+
+ if ((rate == 44100) || (rate == 22050) || (rate == 11025))
+ {
+ /* Division factor has 1 offset! (i.e. 0 = /1, 1 = /2, etc. */
+
+ mask_divq = RCC_DCKCFGR1_PLLI2SDIVQ(18);
+ mask_i2s = RCC_PLLI2SCFGR_PLLI2SN(429) |
+ RCC_PLLI2SCFGR_PLLI2SQ(2);
+ frequency = 11289473;
+ }
+ else
+ {
+ /* Division factor has 1 offset! (i.e. 0 = /1, 1 = /2, etc. */
+
+ mask_divq = RCC_DCKCFGR1_PLLI2SDIVQ(0);
+ mask_i2s = RCC_PLLI2SCFGR_PLLI2SN(344) |
+ RCC_PLLI2SCFGR_PLLI2SQ(7);
+ frequency = 49142857;
+ }
+
+ /* Check if i2s PLL is already in correct configuration */
+
+ if ((getreg32(STM32_RCC_DCKCFGR1) &
+ (RCC_DCKCFGR1_PLLI2SDIVQ_MASK)) != mask_divq)
+ {
+ /* Disable the PLLI2S */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval &= ~(RCC_CR_PLLI2SON);
+ putreg32 (regval, STM32_RCC_CR);
+
+ while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SON))
+ {
+ }
+
+ /* Set PLLI2S Configuration */
+
+ regval = getreg32(STM32_RCC_DCKCFGR1);
+ regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK);
+ regval |= mask_divq;
+ putreg32(regval, STM32_RCC_DCKCFGR1);
+
+ regval = getreg32(STM32_RCC_PLLI2SCFGR);
+ regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
+ | RCC_PLLI2SCFGR_PLLI2SQ_MASK);
+ regval |= mask_i2s;
+ putreg32(regval, STM32_RCC_PLLI2SCFGR);
+
+ /* Enable the PLLI2S */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval |= (RCC_CR_PLLI2SON);
+ putreg32 (regval, STM32_RCC_CR);
+
+ while (!(getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY))
+ {
+ }
+ }
+
+ audinfo("i2s PLL configured for samplerate %lu\n", rate);
+ return frequency;
+}
+
/****************************************************************************
* Name: stm32_wm8994_initialize
*
@@ -132,6 +219,7 @@ static struct stm32_mwinfo_s g_wm8994 =
int stm32_wm8994_initialize(int minor)
{
struct audio_lowerhalf_s *wm8994;
+ struct audio_lowerhalf_s *pcm;
struct i2c_master_s *i2c;
struct i2s_dev_s *i2s;
static bool initialized = false;
@@ -163,7 +251,7 @@ int stm32_wm8994_initialize(int minor)
/* Get an instance of the I2S interface for the CODEC data streams */
- i2s = stm32_sai_initialize(WM8994_SAI_BUS);
+ i2s = stm32_sai_initialize(WM8994_SAI_BUS, stm32_wm8994_sampleratecb);
if (!i2s)
{
auderr("stm32_sai_initialize failed\n");
@@ -183,21 +271,32 @@ int stm32_wm8994_initialize(int minor)
goto error;
}
+ /* No we can embed the WM8994/I2C/I2S conglomerate into a PCM decoder
+ * instance so that we will have a PCM front end for the the WM8994
+ * driver.
+ */
+
+ pcm = pcm_decode_initialize(wm8994);
+ if (pcm == NULL)
+ {
+ auderr("ERROR: Failed create the PCM decoder\n");
+ ret = -ENODEV;
+ goto error;
+ }
+
/* Create a device name */
snprintf(devname, 12, "pcm%d", minor);
-#if 0
+
/* Finally, we can register the ADAU1961/I2C/I2S audio device. */
- ret = audio_register(devname, wm8994);
+ ret = audio_register(devname, pcm);
if (ret < 0)
{
auderr("failed to register /dev/%s device: %d\n", devname, ret);
goto error;
}
-#endif
-
/* Now we are initialized */
initialized = true;
diff --git a/drivers/audio/wm8994.c b/drivers/audio/wm8994.c
index ad756afebc..a7bed7d542 100644
--- a/drivers/audio/wm8994.c
+++ b/drivers/audio/wm8994.c
@@ -84,12 +84,25 @@ static
uint16_t regaddr);
static void wm8994_writereg(FAR struct wm8994_dev_s *priv,
uint16_t regaddr, uint16_t regval);
-static void wm8994_takesem(sem_t *sem);
+static int wm8994_takesem(FAR sem_t *sem);
#define wm8994_givesem(s) nxsem_post(s)
#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME
static inline uint16_t wm8994_scalevolume(uint16_t volume, b16_t scale);
+static void wm8994_setvolume(FAR struct wm8994_dev_s *priv,
+ uint16_t volume, bool mute);
#endif
+#ifndef CONFIG_AUDIO_EXCLUDE_TONE
+static void wm8994_setbass(FAR struct wm8994_dev_s *priv, uint8_t bass);
+static void wm8994_settreble(FAR struct wm8994_dev_s *priv,
+ uint8_t treble);
+#endif
+
+static void wm8994_setdatawidth(FAR struct wm8994_dev_s *priv);
+static void wm8994_setbitrate(FAR struct wm8994_dev_s *priv);
+
+static void wm8994_setdatawidth(FAR struct wm8994_dev_s *priv);
+static void wm8994_setbitrate(FAR struct wm8994_dev_s *priv);
/* Audio lower half methods (and close friends) */
@@ -165,7 +178,6 @@ static void *wm8994_workerthread(pthread_addr_t pvarg);
/* Initialization */
static void wm8994_audio_output(FAR struct wm8994_dev_s *priv);
-static void wm8994_audio_input(FAR struct wm8994_dev_s *priv);
#if 0 /* Not used */
static void wm8994_audio_input(FAR struct wm8994_dev_s *priv);
#endif
@@ -365,6 +377,72 @@ static void wm8994_writereg(FAR struct wm8994_dev_s *priv, uint16_t regaddr,
}
}
+/****************************************************************************
+ * Name: wm8994_setsamplefreq
+ *
+ * Description:
+ * Sets the sample frequency for AIF1
+ *
+ ****************************************************************************/
+
+static void wm8994_setsamplefreq(FAR struct wm8994_dev_s *priv)
+{
+ uint16_t regval;
+
+ /* Table 106 in WM8994 manual */
+
+ switch (priv->samprate)
+ {
+ case 8000:
+ regval = WM8994_AIF1_SR_8K;
+ break;
+ case 11025:
+ regval = WM8994_AIF1_SR_11K;
+ break;
+ case 12000:
+ regval = WM8994_AIF1_SR_12K;
+ break;
+ case 16000:
+ regval = WM8994_AIF1_SR_16K;
+ break;
+ case 22050:
+ regval = WM8994_AIF1_SR_22K;
+ break;
+ case 24000:
+ regval = WM8994_AIF1_SR_24K;
+ break;
+ case 32000:
+ regval = WM8994_AIF1_SR_32K;
+ break;
+ case 44100:
+ regval = WM8994_AIF1_SR_44K;
+ break;
+ case 48000:
+ regval = WM8994_AIF1_SR_48K;
+ break;
+
+ /* If these frequencies should be added, the sample rate
+ * would need to be changed to 32 bit throughout the code
+ */
+
+#if 0
+ case 88200:
+ regval = WM8994_AIF1_SR_88K;
+ break;
+ case 96000:
+ regval = WM8994_AIF1_SR_96K;
+ break;
+#endif
+ default:
+ regval = WM8994_AIF1_SR_11K; /* 11025 as default */
+ }
+
+ /* AIF1CLK / fs ratio = 256 */
+
+ regval |= WM8994_AIF1CLK_RATE_3;
+ wm8994_writereg(priv, WM8994_AIF1_RATE, regval);
+}
+
/* Name: wm8994_takesem
*
* Description:
@@ -373,16 +451,9 @@ static void wm8994_writereg(FAR struct wm8994_dev_s *priv, uint16_t regaddr,
*
*/
-static void wm8994_takesem(sem_t *sem)
+static int wm8994_takesem(FAR sem_t *sem)
{
- int ret;
-
- do
- {
- ret = nxsem_wait(sem);
- DEBUGASSERT(ret == 0 || ret == -EINTR);
- }
- while (ret == -EINTR);
+ return nxsem_wait_uninterruptible(sem);
}
/* Name: wm8994_scalevolume
@@ -400,61 +471,192 @@ static inline uint16_t wm8994_scalevolume(uint16_t volume, b16_t scale)
}
#endif
-/* Name: wm8994_setbitrate
+/****************************************************************************
+ * Name: wm8994_setvolume
*
* Description:
- * Program the FLL to achieve the requested bitrate (fout). Given:
+ * Set the right and left volume values in the WM8994 device based on the
+ * current volume and balance settings.
*
- * samprate - Samples per second
- * nchannels - Number of channels of data
- * bpsamp - Bits per sample
- *
- * Then
- * fout = samprate * nchannels * bpsamp
- *
- * For example:
- * samplerate = 11,025 samples/sec
- * nchannels = 1
- * bpsamp = 16 bits
+ ****************************************************************************/
+
+#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME
+static void wm8994_setvolume(FAR struct wm8994_dev_s *priv, uint16_t volume,
+ bool mute)
+{
+ uint32_t leftlevel;
+ uint32_t rightlevel;
+ uint16_t regval;
+
+ audinfo("volume=%u mute=%u\n", volume, mute);
+
+#ifndef CONFIG_AUDIO_EXCLUDE_BALANCE
+ /* Calculate the left channel volume level {0..1000} */
+
+ if (priv->balance <= (b16HALF - 1))
+ {
+ leftlevel = volume;
+ }
+ else if (priv->balance == b16ONE)
+ {
+ leftlevel = 0;
+ }
+ else
+ {
+ /* Note: b16ONE - balance goes from 0 to 0.5.
+ * Hence need to multiply volume by 2!
+ */
+
+ leftlevel = wm8994_scalevolume(2 * volume,
+ b16ONE - (b16_t)priv->balance);
+ }
+
+ /* Calculate the right channel volume level {0..1000} */
+
+ if (priv->balance >= (b16HALF - 1))
+ {
+ rightlevel = volume;
+ }
+ else if (priv->balance == 0)
+ {
+ rightlevel = 0;
+ }
+ else
+ {
+ /* Note: b16ONE - balance goes from 0 to 0.5.
+ * Hence need to multiply volume by 2!
+ */
+
+ rightlevel = wm8994_scalevolume(2 * volume,
+ (b16_t)priv->balance);
+ }
+#else
+ leftlevel = priv->volume;
+ rightlevel = priv->volume;
+#endif
+
+ /* Set the volume */
+
+ regval = WM8994_HPOUT1_VU_ENABLED | WM8994_HPOUT1L_VOL(leftlevel);
+ if (!mute)
+ {
+ regval |= WM8994_HPOUT1L_MUTE_N_NO;
+ }
+ wm8994_writereg(priv, WM8994_LEFT_OUTPUT_VOL, regval);
+ wm8994_writereg(priv, WM8994_SPEAKER_VOL_LEFT, regval);
+
+ regval = WM8994_HPOUT1_VU_ENABLED | WM8994_HPOUT1R_VOL(rightlevel);
+ if (!mute)
+ {
+ regval |= WM8994_HPOUT1R_MUTE_N_NO;
+ }
+ wm8994_writereg(priv, WM8994_RIGHT_OUTPUT_VOL, regval);
+ wm8994_writereg(priv, WM8994_SPEAKER_VOL_RIGHT, regval);
+
+ /* Remember the volume level and mute settings */
+
+ priv->volume = volume;
+ priv->mute = mute;
+}
+#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */
+
+/****************************************************************************
+ * Name: wm8994_setbass
*
- * Then
- * fout = 11025 samples/sec * 1 * 16 bits/sample = 176.4 bits/sec
+ * Description:
+ * Set the bass level.
*
- * The clocking is configured like this:
- * MCLK is the FLL source clock
- * Fref is the scaled down version of MCLK
- * Fvco is the output frequency from the FLL
- * Fout is the final output from the FLL that drives the SYSCLK
- * SYSCLK can be divided down to generate the BCLK
+ * The level and range are in whole percentage levels (0-100).
*
- * The FLL output frequency is generated at that fout by:
+ ****************************************************************************/
+
+#ifndef CONFIG_AUDIO_EXCLUDE_TONE
+static void wm8994_setbass(FAR struct wm8994_dev_s *priv, uint8_t bass)
+{
+ audinfo("bass=%u\n", bass);
+#warning Missing logic
+}
+#endif /* CONFIG_AUDIO_EXCLUDE_TONE */
+
+/****************************************************************************
+ * Name: wm8994_settreble
*
- * Fout = (Fvco / FLL_OUTDIV)
+ * Description:
+ * Set the treble level .
*
- * The FLL operating frequency is set according to:
+ * The level and range are in whole percentage levels (0-100).
*
- * Fvco = Fref * N.K * FLL_RATIO
+ ****************************************************************************/
+
+#ifndef CONFIG_AUDIO_EXCLUDE_TONE
+static void wm8994_settreble(FAR struct wm8994_dev_s *priv, uint8_t treble)
+{
+ audinfo("treble=%u\n", treble);
+#warning Missing logic
+}
+#endif /* CONFIG_AUDIO_EXCLUDE_TONE */
+
+/****************************************************************************
+ * Name: wm8994_setdatawidth
*
- * Where Fref is the input frequency frequency as determined by
- * FLL_CLK_REF_DIV. Fvco must be in the range of 90-100MHz.
+ * Description:
+ * Set the 8- or 16-bit data modes
*
- * As an example:
- * FLL_CLK_REF_DIV = 16
- * FLL_OUTDIV = 8
- * N.K = 187.25
- * FLL_RATIO=16
- * Fref =32,768
+ ****************************************************************************/
+
+static void wm8994_setdatawidth(FAR struct wm8994_dev_s *priv)
+{
+ /* TODO */
+
+ return;
+}
+
+/* Name: wm8994_setbitrate
*
- * Fvco = 32,768 * 187.25 / 16 = 383,488 Hz
- * Fout = 383,488 / 8 = 47,936 Hz (approx. 48Khz)
+ * Description:
+ * Enter callback function to let the board set
+ * the I2S Frequency appropriately.
*
+ * TODO: Currently the FLL is not used as in the current application
+ * the WM8994 will operate in Slave mode. Code snippet
+ * may be helpful to generalize this code to multiple
+ * outputs and other I2S frame formats.
*/
static void wm8994_setbitrate(FAR struct wm8994_dev_s *priv)
{
+ uint32_t fout;
+ unsigned int framelen;
+
DEBUGASSERT(priv && priv->lower);
- /* TODO */
+ /* First calculate the desired bitrate (fout). This is based on
+ *
+ * 1. The I2S frame length (in bits)
+ * 2. The number of frames per second = nchannels * samplerate
+ *
+ */
+
+ framelen = (priv->bpsamp == 8) ? WM8994_FRAMELEN8 : WM8994_FRAMELEN16;
+ fout = (uint32_t)priv->samprate * (uint32_t)priv->nchannels * framelen;
+
+ audinfo("sample rate=%u nchannels=%u bpsamp=%u framelen=%d fout=%lu\n",
+ priv->samprate, priv->nchannels, priv->bpsamp, framelen,
+ (unsigned long)fout);
+
+ /* The WM8994 does have an internal FLL
+ * However, for the application here, the STM32 I2S PLL is used
+ * Only way to achieve right clock rate is by setting the
+ * SAI clock accordingly (for STM32F746G Discovery)
+ *
+ * TODO: Generalize.
+ */
+
+ wm8994_setsamplefreq(priv);
+
+ I2S_RXSAMPLERATE(priv->i2s, priv->samprate);
+
+ return;
}
/* Name: wm8994_getcaps
@@ -471,7 +673,158 @@ static int wm8994_getcaps(FAR struct audio_lowerhalf_s *dev, int type,
DEBUGASSERT(caps && caps->ac_len >= sizeof(struct audio_caps_s));
audinfo("type=%d ac_type=%d\n", type, caps->ac_type);
- return 0;
+
+ /* Fill in the caller's structure based on requested info */
+
+ caps->ac_format.hw = 0;
+ caps->ac_controls.w = 0;
+
+ switch (caps->ac_type)
+ {
+ /* Caller is querying for the types of units we support */
+
+ case AUDIO_TYPE_QUERY:
+
+ /* Provide our overall capabilities. The interfacing software
+ * must then call us back for specific info for each capability.
+ */
+
+ caps->ac_channels = 2; /* Stereo output */
+
+ switch (caps->ac_subtype)
+ {
+ case AUDIO_TYPE_QUERY:
+
+ /* We don't decode any formats! Only something above us in
+ * the audio stream can perform decoding on our behalf.
+ */
+
+ /* The types of audio units we implement */
+
+ caps->ac_controls.b[0] =
+ AUDIO_TYPE_OUTPUT | AUDIO_TYPE_FEATURE |
+ AUDIO_TYPE_PROCESSING;
+
+ break;
+
+ case AUDIO_FMT_MIDI:
+
+ /* We only support Format 0 */
+
+ caps->ac_controls.b[0] = AUDIO_SUBFMT_END;
+ break;
+
+ default:
+ caps->ac_controls.b[0] = AUDIO_SUBFMT_END;
+ break;
+ }
+
+ break;
+
+ /* Provide capabilities of our OUTPUT unit */
+
+ case AUDIO_TYPE_OUTPUT:
+
+ caps->ac_channels = 2;
+
+ switch (caps->ac_subtype)
+ {
+ case AUDIO_TYPE_QUERY:
+
+ /* Report the Sample rates we support */
+
+ caps->ac_controls.b[0] =
+ AUDIO_SAMP_RATE_8K | AUDIO_SAMP_RATE_11K |
+ AUDIO_SAMP_RATE_16K | AUDIO_SAMP_RATE_22K |
+ AUDIO_SAMP_RATE_32K | AUDIO_SAMP_RATE_44K |
+ AUDIO_SAMP_RATE_48K;
+ break;
+
+ case AUDIO_FMT_MP3:
+ case AUDIO_FMT_WMA:
+ case AUDIO_FMT_PCM:
+ break;
+
+ default:
+ break;
+ }
+
+ break;
+
+ /* Provide capabilities of our FEATURE units */
+
+ case AUDIO_TYPE_FEATURE:
+
+ /* If the sub-type is UNDEF,
+ * then report the Feature Units we support
+ */
+
+ if (caps->ac_subtype == AUDIO_FU_UNDEF)
+ {
+ /* Fill in the ac_controls section with
+ * the Feature Units we have
+ */
+
+ caps->ac_controls.b[0] = AUDIO_FU_VOLUME | AUDIO_FU_BASS |
+ AUDIO_FU_TREBLE;
+ caps->ac_controls.b[1] = AUDIO_FU_BALANCE >> 8;
+ }
+ else
+ {
+ /* TODO: Do we need to provide specific info for the Feature
+ * Units, such as volume setting ranges, etc.?
+ */
+ }
+
+ break;
+
+ /* Provide capabilities of our PROCESSING unit */
+
+ case AUDIO_TYPE_PROCESSING:
+
+ switch (caps->ac_subtype)
+ {
+ case AUDIO_PU_UNDEF:
+
+ /* Provide the type of Processing Units we support */
+
+ caps->ac_controls.b[0] = AUDIO_PU_STEREO_EXTENDER;
+ break;
+
+ case AUDIO_PU_STEREO_EXTENDER:
+
+ /* Provide capabilities of our Stereo Extender */
+
+ caps->ac_controls.b[0] =
+ AUDIO_STEXT_ENABLE | AUDIO_STEXT_WIDTH;
+ break;
+
+ default:
+
+ /* Other types of processing uint we don't support */
+
+ break;
+ }
+
+ break;
+
+ /* All others we don't support */
+
+ default:
+
+ /* Zero out the fields to indicate no support */
+
+ caps->ac_subtype = 0;
+ caps->ac_channels = 0;
+
+ break;
+ }
+
+ /* Return the length of the audio_caps_s struct for validation of
+ * proper Audio device type.
+ */
+
+ return caps->ac_len;
}
/* Name: wm8994_configure
@@ -496,7 +849,158 @@ static int wm8994_configure(FAR struct audio_lowerhalf_s *dev,
DEBUGASSERT(priv != NULL && caps != NULL);
audinfo("ac_type: %d\n", caps->ac_type);
- /* TODO */
+ /* Process the configure operation */
+
+ switch (caps->ac_type)
+ {
+ case AUDIO_TYPE_FEATURE:
+ audinfo(" AUDIO_TYPE_FEATURE\n");
+
+ /* Process based on Feature Unit */
+
+ switch (caps->ac_format.hw)
+ {
+#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME
+ case AUDIO_FU_VOLUME:
+ {
+ /* Set the volume */
+
+ uint16_t volume = caps->ac_controls.hw[0];
+ audinfo(" Volume: %d\n", volume);
+
+ if (volume >= 0 && volume <= 1000)
+ {
+ /* Scale the volume setting to the range {0.. 63} */
+
+ wm8994_setvolume(priv, (63 * volume / 1000), priv->mute);
+ }
+ else
+ {
+ ret = -EDOM;
+ }
+ }
+ break;
+#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */
+
+#ifndef CONFIG_AUDIO_EXCLUDE_BALANCE
+ case AUDIO_FU_BALANCE:
+ {
+ /* Set the balance. The percentage level (0-100) is in the
+ * ac_controls.b[0] parameter.
+ */
+
+ uint16_t balance = caps->ac_controls.hw[0];
+ audinfo(" Balance: %d\n", balance);
+
+ if (balance >= 0 && balance <= 1000)
+ {
+ /* Scale the volume setting to the range {0.. 63} */
+
+ priv->balance = (balance * (b16ONE - 1)) / 1000;
+ wm8994_setvolume(priv, priv->volume, priv->mute);
+ }
+ else
+ {
+ ret = -EDOM;
+ }
+ }
+ break;
+#endif /* CONFIG_AUDIO_EXCLUDE_BALANCE */
+
+#ifndef CONFIG_AUDIO_EXCLUDE_TONE
+ case AUDIO_FU_BASS:
+ {
+ /* Set the bass. The percentage level (0-100) is in the
+ * ac_controls.b[0] parameter.
+ */
+
+ uint8_t bass = caps->ac_controls.b[0];
+ audinfo(" Bass: %d\n", bass);
+
+ if (bass <= 100)
+ {
+ wm8994_setbass(priv, bass);
+ }
+ else
+ {
+ ret = -EDOM;
+ }
+ }
+ break;
+
+ case AUDIO_FU_TREBLE:
+ {
+ /* Set the treble. The percentage level (0-100) is in the
+ * ac_controls.b[0] parameter.
+ */
+
+ uint8_t treble = caps->ac_controls.b[0];
+ audinfo(" Treble: %d\n", treble);
+
+ if (treble <= 100)
+ {
+ wm8994_settreble(priv, treble);
+ }
+ else
+ {
+ ret = -EDOM;
+ }
+ }
+ break;
+#endif /* CONFIG_AUDIO_EXCLUDE_TONE */
+
+ default:
+ auderr(" ERROR: Unrecognized feature unit\n");
+ ret = -ENOTTY;
+ break;
+ }
+ break;
+
+ case AUDIO_TYPE_OUTPUT:
+ {
+ audinfo(" AUDIO_TYPE_OUTPUT:\n");
+ audinfo(" Number of channels: %u\n", caps->ac_channels);
+ audinfo(" Sample rate: %u\n", caps->ac_controls.hw[0]);
+ audinfo(" Sample width: %u\n", caps->ac_controls.b[2]);
+
+ /* Verify that all of the requested values are supported */
+
+ ret = -ERANGE;
+ if (caps->ac_channels != 1 && caps->ac_channels != 2)
+ {
+ auderr("ERROR: Unsupported number of channels: %d\n",
+ caps->ac_channels);
+ break;
+ }
+
+ if (caps->ac_controls.b[2] != 8 && caps->ac_controls.b[2] != 16)
+ {
+ auderr("ERROR: Unsupported bits per sample: %d\n",
+ caps->ac_controls.b[2]);
+ break;
+ }
+
+ /* Save the current stream configuration */
+
+ priv->samprate = caps->ac_controls.hw[0];
+ priv->nchannels = caps->ac_channels;
+ priv->bpsamp = caps->ac_controls.b[2];
+
+ /* Reconfigure the FLL to support the resulting number or channels,
+ * bits per sample, and bitrate.
+ */
+
+ wm8994_setdatawidth(priv);
+ wm8994_setbitrate(priv);
+
+ wm8994_clock_analysis(&priv->dev, "AUDIO_TYPE_OUTPUT");
+ ret = OK;
+ }
+ break;
+
+ case AUDIO_TYPE_PROCESSING:
+ break;
+ }
return ret;
}
@@ -682,7 +1186,12 @@ static int wm8994_sendbuffer(FAR struct wm8994_dev_s *priv)
* only while accessing 'inflight'.
*/
- wm8994_takesem(&priv->pendsem);
+ ret = wm8994_takesem(&priv->pendsem);
+ if (ret < 0)
+ {
+ return ret;
+ }
+
while (priv->inflight < CONFIG_WM8994_INFLIGHT &&
dq_peek(&priv->pendq) != NULL && !priv->paused)
{
@@ -935,7 +1444,12 @@ static int wm8994_enqueuebuffer(FAR struct audio_lowerhalf_s *dev,
/* Add the new buffer to the tail of pending audio buffers */
- wm8994_takesem(&priv->pendsem);
+ ret = wm8994_takesem(&priv->pendsem);
+ if (ret < 0)
+ {
+ return ret;
+ }
+
apb->flags |= AUDIO_APB_OUTPUT_ENQUEUED;
dq_addlast(&apb->dq_entry, &priv->pendq);
wm8994_givesem(&priv->pendsem);
@@ -985,6 +1499,7 @@ static int wm8994_cancelbuffer(FAR struct audio_lowerhalf_s *dev,
static int wm8994_ioctl(FAR struct audio_lowerhalf_s *dev, int cmd,
unsigned long arg)
{
+ int ret = OK;
#ifdef CONFIG_AUDIO_DRIVER_SPECIFIC_BUFFERS
FAR struct ap_buffer_info_s *bufinfo;
#endif
@@ -1022,11 +1537,12 @@ static int wm8994_ioctl(FAR struct audio_lowerhalf_s *dev, int cmd,
#endif
default:
+ ret = -ENOTTY;
audinfo("Ignored\n");
break;
}
- return OK;
+ return ret;
}
/* Name: wm8994_reserve
@@ -1231,6 +1747,7 @@ static void *wm8994_workerthread(pthread_addr_t pvarg)
#ifdef WM8994_USE_FFLOCK_INT
WM8994_ENABLE(priv->lower);
#endif
+ wm8994_setvolume(priv, priv->volume, false);
/* Loop as long as we are supposed to be running and as long as we have
* buffers in-flight.
@@ -1374,24 +1891,330 @@ static void *wm8994_workerthread(pthread_addr_t pvarg)
static void wm8994_audio_output(FAR struct wm8994_dev_s *priv)
{
- /* TODO */
-}
+ uint16_t regval;
+ uint16_t cold_startup = 1;
-/* Name: wm8994_audio_input
- *
- * Description:
- * Initialize and configure the WM8994 device as an audio input device.
- *
- * Input Parameters:
- * priv - A reference to the driver state structure
- *
- * Returned Value:
- * None. No failures are detected.
- *
- */
+ /* Do not change! Currently only headphones are supported! */
-static void wm8994_audio_input(FAR struct wm8994_dev_s *priv)
-{
+ uint16_t hp_out = 1;
+ uint16_t spk_out = 0;
+
+ /* Bias Control.
+ */
+
+ regval = WM8994_STARTUP_BIAS_ENA |
+ WM8994_VMID_BUF_ENA |
+ WM8994_VMID_RAMP_SOFT_FAST_START;
+ wm8994_writereg(priv, WM8994_ANTI_POP2, regval);
+
+ /* VMID Control */
+
+ regval = WM8994_BIAS_ENA |
+ WM8994_VMID_SEL_2X40K;
+ wm8994_writereg(priv, WM8994_PM1, regval);
+
+ up_mdelay(40);
+
+ /* Path configuration for output
+ *
+ * Currently the DAC1 is used and configured for AIF1 Timeslot 0
+ * DAC2 and AIF1 Timeslot 1 remain unused
+ */
+
+ /* Enable DAC1 (Left), Enable DAC1 (Right)
+ * Enable AIF1DAC1L (Left) input path (AIF1, TS0)
+ * Enable AIF1DAC1R (Right) input path (AIF1, TS0)
+ */
+
+ regval = WM8994_AIF1DAC1L_ENA |
+ WM8994_AIF1DAC1R_ENA |
+ WM8994_DAC1L_ENA |
+ WM8994_DAC1R_ENA;
+ wm8994_writereg(priv, WM8994_PM5, regval);
+
+ /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
+
+ regval = WM8994_AIF1DAC1L_TO_DAC1L_ENA;
+ wm8994_writereg(priv, WM8994_DAC1_LEFT_MIXER_ROUTING, regval);
+
+ /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
+
+ regval = WM8994_AIF1DAC1R_TO_DAC1R_ENA;
+ wm8994_writereg(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING, regval);
+
+ /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
+
+ regval = 0x0000;
+ wm8994_writereg(priv, WM8994_DAC2_LEFT_MIXER_ROUTING, regval);
+
+ /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
+
+ regval = 0x0000;
+ wm8994_writereg(priv, WM8994_DAC2_RIGHT_MIXER_ROUTING, regval);
+
+ /* Clock Rates 1.
+ *
+ * Contains settings the control the sample rate.
+ *
+ * Note:
+ * The AIF clock is directly related to the MCLK signal
+ * which is set to fs*256.
+ * As long as DAC_OSR128 is left off, according to
+ * Table 48, a constant AIFnCLK / Fs ratio of
+ * 256 works from 8kHz to 48kHz.
+ */
+
+ wm8994_setsamplefreq (priv);
+
+ /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */
+
+ regval = WM8994_AIF1ADCR_SRC |
+ WM8994_AIF1_FMT_I2S;
+ wm8994_writereg(priv, WM8994_AIF1_CTL1, regval);
+
+ /* Slave mode */
+
+ regval = 0x0000;
+ wm8994_writereg(priv, WM8994_AIF1_MASTER_SLAVE, regval);
+
+ /* Enable the DSP processing clock for AIF1, Enable the core clock */
+
+ regval = WM8994_SYSDSPCLK_ENA |
+ WM8994_AIF1DSPCLK_ENA;
+ wm8994_writereg(priv, WM8994_CLK1, regval);
+
+ /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */
+
+ regval = WM8994_AIF1CLK_ENA;
+ wm8994_writereg(priv, WM8994_AIF1_CLK1, regval);
+
+ /* Select DAC1 (Left) to Left Headphone Output */
+
+ regval = WM8994_DAC1L_TO_HPOUT1L;
+ wm8994_writereg(priv, WM8994_OUTPUT_MIXER1, regval);
+
+ /* Select DAC1 (Right) to Right Headphone Output */
+
+ regval = WM8994_DAC1R_TO_HPOUT1R;
+ wm8994_writereg(priv, WM8994_OUTPUT_MIXER2, regval);
+
+ /* Startup sequence for Headphone */
+
+ if (cold_startup)
+ {
+ regval = WM8994_WSEQ_ENA |
+ WM8994_WSEQ_START |
+ (0x0 << WM8994_WSEQ_START_INDEX_SHIFT); /* Start Index = 0 */
+ wm8994_writereg(priv, WM8994_WR_CTL_SEQ1, regval);
+ up_mdelay(20);
+
+ /* Wait until sequencer indicates that sequence is completed */
+
+ regval = wm8994_readreg(priv, WM8994_WR_CTL_SEQ2);
+ while (regval & WM8994_WSEQ_BUSY)
+ {
+ regval = wm8994_readreg(priv, WM8994_WR_CTL_SEQ2);
+ up_mdelay(20);
+ }
+
+ /* TODO: Manage cold/warm start correctly */
+
+ cold_startup = 0;
+ }
+ else /* Headphone Warm Start-Up */
+ {
+ regval = WM8994_WSEQ_ENA |
+ WM8994_WSEQ_START |
+ (0x8 << WM8994_WSEQ_START_INDEX_SHIFT); /* Start Index = 8 */
+ wm8994_writereg(priv, WM8994_WR_CTL_SEQ1, regval);
+ up_mdelay(20);
+
+ /* Wait until sequencer indicates that sequence is completed */
+
+ regval = wm8994_readreg(priv, WM8994_WR_CTL_SEQ2);
+ while (regval & WM8994_WSEQ_BUSY)
+ {
+ regval = wm8994_readreg(priv, WM8994_WR_CTL_SEQ2);
+ up_mdelay(20);
+ }
+ }
+
+ /* Soft un-Mute the AIF1 Timeslot 0 DAC1 path L&R */
+
+ regval = 0x0000;
+ wm8994_writereg(priv, WM8994_AIF1_DAC1_FILTERS1, regval);
+
+ /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */
+
+ regval = WM8994_SPKRVOL_ENA |
+ WM8994_SPKLVOL_ENA;
+ wm8994_writereg(priv, WM8994_PM3, regval);
+
+ /* Left Speaker Mixer Volume = 0dB */
+
+ regval = 0x0000;
+ wm8994_writereg(priv, WM8994_SPKMIXL_ATT, regval);
+
+ /* Speaker output mode = Class D,
+ * Right Speaker Mixer Volume = 0dB
+ */
+
+ regval = 0x0000;
+ wm8994_writereg(priv, WM8994_SPKMIXR_ATT, regval);
+
+ if (spk_out)
+ {
+ /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path,
+ * Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path
+ */
+
+ regval = WM8994_DAC2L_TO_SPKMIXL |
+ WM8994_DAC2R_TO_SPKMIXR;
+ wm8994_writereg(priv, WM8994_SPEAKER_MIXER, regval);
+
+ /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */
+
+ regval = WM8994_SPKOUTR_ENA |
+ WM8994_SPKOUTL_ENA |
+ WM8994_BIAS_ENA |
+ WM8994_VMID_SEL_2X40K;
+ wm8994_writereg(priv, WM8994_PM1, regval);
+
+ /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */
+
+ regval = WM8994_CP_DYN_PWR;
+ regval = 0x0005; /* TODO: Check where this comes from? */
+ wm8994_writereg(priv, WM8994_CLASS_W_1, regval);
+ }
+
+ /* Enable normal bias generator, Enable VMID */
+
+ regval = WM8994_BIAS_ENA |
+ WM8994_VMID_SEL_2X40K;
+
+ /* Enable speaker */
+
+ if (spk_out)
+ {
+ regval |= WM8994_SPKOUTR_ENA |
+ WM8994_SPKOUTL_ENA;
+ }
+
+ /* Enable HPOUT1 (Left) and
+ * Enable HPOUT1 (Right) input stages
+ */
+
+ if (hp_out)
+ {
+ regval |= WM8994_HPOUT1L_ENA |
+ WM8994_HPOUT1R_ENA;
+ }
+
+ wm8994_writereg(priv, WM8994_PM1, regval);
+
+ /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */
+
+ regval = WM8994_HPOUT1L_DLY |
+ WM8994_HPOUT1R_DLY;
+ wm8994_writereg(priv, WM8994_ANA_HP1, regval);
+
+ /* Enable Charge Pump */
+
+ regval = WM8994_CP_ENA;
+ wm8994_writereg(priv, WM8994_CHARGE_PUMP1, regval);
+
+ /* Add Delay */
+
+ up_mdelay(15);
+
+ /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
+
+ regval = WM8994_DAC1L_TO_MIXOUTL;
+ wm8994_writereg(priv, WM8994_OUTPUT_MIXER1, regval);
+
+ /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
+
+ regval = WM8994_DAC1R_TO_MIXOUTR;
+ wm8994_writereg(priv, WM8994_OUTPUT_MIXER2, regval);
+
+ /* Enable Left Output Mixer (MIXOUTL),
+ * Enable Right Output Mixer (MIXOUTR),
+ * Enable SPKOUTL and SPKOUTR
+ */
+
+ regval =
+ WM8994_MIXOUTL_ENA |
+ WM8994_MIXOUTR_ENA;
+ if (spk_out)
+ {
+ regval |= WM8994_SPKLVOL_ENA |
+ WM8994_SPKRVOL_ENA;
+ }
+ wm8994_writereg(priv, WM8994_PM3, regval);
+
+ /* Enable DC Servo and trigger start-up mode on left and right channels */
+
+ regval = WM8994_DCS_TRIG_STARTUP_1 |
+ WM8994_DCS_TRIG_STARTUP_0 |
+ WM8994_DCS_ENA_CHAN_1 |
+ WM8994_DCS_ENA_CHAN_0;
+ wm8994_writereg(priv, WM8994_DC_SERVO1, regval);
+
+ /* Add Delay */
+
+ up_mdelay(257);
+
+ /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages.
+ * Remove clamps
+ */
+
+ regval = WM8994_HPOUT1L_RMV_SHORT |
+ WM8994_HPOUT1L_OUTP |
+ WM8994_HPOUT1L_DLY |
+ WM8994_HPOUT1R_RMV_SHORT |
+ WM8994_HPOUT1R_OUTP |
+ WM8994_HPOUT1R_DLY;
+ wm8994_writereg(priv, WM8994_ANA_HP1, regval);
+
+ /* Set DAC 1 (Left) to volume 0xC0 */
+
+ if (hp_out)
+ {
+ regval = (0xc0 << WM8994_DAC1L_VOL_SHIFT);
+ wm8994_writereg(priv, WM8994_DAC1_LEFT_VOL, regval);
+
+ /* Set DAC 1 (Right) to volume 0xC0 */
+
+ regval = (0xc0 << WM8994_DAC1R_VOL_SHIFT);
+ wm8994_writereg(priv, WM8994_DAC1_RIGHT_VOL, regval);
+
+ /* Unmute the AIF1 Timeslot 0 DAC path */
+
+ regval = WM8994_AIF1DAC1_UNMUTE_RAMP;
+ wm8994_writereg(priv, WM8994_AIF1_DAC1_FILTERS1, regval);
+ }
+
+ if (spk_out)
+ {
+ /* Set DAC 2 (Left) to volume 0xC0 */
+
+ regval = (0xc0 << WM8994_DAC2L_VOL_SHIFT);
+ wm8994_writereg(priv, WM8994_DAC2_LEFT_VOL, regval);
+
+ /* Set DAC 2 (Right) to volume 0xC0 */
+
+ regval = (0xc0 << WM8994_DAC2R_VOL_SHIFT);
+ wm8994_writereg(priv, WM8994_DAC2_RIGHT_VOL, regval);
+
+ /* Unmute the AIF1 Timeslot 1 DAC2 path */
+
+ regval = WM8994_AIF1DAC2_UNMUTE_RAMP;
+ wm8994_writereg(priv, WM8994_AIF1_DAC2_FILTERS1, regval);
+ }
+
+ /* Volume Control */
+
+ wm8994_setvolume(priv, CONFIG_WM8994_INITVOLUME, true);
}
/* Name: wm8994_audio_input
@@ -1484,7 +2307,7 @@ static void wm8994_hw_reset(FAR struct wm8994_dev_s *priv)
priv->nchannels = WM8994_DEFAULT_NCHANNELS;
priv->bpsamp = WM8994_DEFAULT_BPSAMP;
#if !defined(CONFIG_AUDIO_EXCLUDE_VOLUME) && !defined(CONFIG_AUDIO_EXCLUDE_BALANCE)
- priv->balance = b16HALF; /* Center balance */
+ priv->balance = b16HALF - 1; /* Center balance */
#endif
/* Software reset. This puts all WM8994 registers back in their
@@ -1502,8 +2325,12 @@ static void wm8994_hw_reset(FAR struct wm8994_dev_s *priv)
wm8994_writereg(priv, 0x102, 0x0003);
wm8994_writereg(priv, 0x817, 0x0000);
wm8994_writereg(priv, 0x102, 0x0000);
- uint16_t regval;
+ /* TODO: This code was left in here as reference for
+ * enabling input functionality and multiple outputs
+ * Currently not used
+ */
+#if 0
/* regval=0x006c */
regval = WM8994_VMID_RAMP_SOFT_FAST_START | WM8994_VMID_BUF_ENA
@@ -1913,6 +2740,10 @@ static void wm8994_hw_reset(FAR struct wm8994_dev_s *priv)
wm8994_writereg(priv, 0x410, regval); /* 0x410 = 0x1800 */
}
}
+#endif
+ /* Configure the WM8994 hardware as an audio output device */
+
+ wm8994_audio_output(priv);
/* Configure interrupts */
diff --git a/drivers/audio/wm8994.h b/drivers/audio/wm8994.h
index 6f0fbc7d92..c2a391122d 100644
--- a/drivers/audio/wm8994.h
+++ b/drivers/audio/wm8994.h
@@ -52,302 +52,302 @@
/* Registers Addresses */
-#define WM8994_SWRST 0x00 /* SW Reset and ID */
-#define WM8994_ID 0x00 /* SW Reset and ID */
-
-#define WM8994_PM1 0x01 /* Power Management */
-#define WM8994_PM2 0x02 /* Power Management */
-#define WM8994_PM3 0x03 /* Power Management */
-#define WM8994_PM4 0x04 /* Power Management */
-#define WM8994_PM5 0x05 /* Power Management */
-#define WM8994_PM6 0x06 /* Power Management */
-
-#define WM8994_INPUT_MIXER1 0x15 /* Input Mixer (1) */
-
-#define WM8994_LEFTLINE_12_VOL 0x18 /* Left Line Input 1&2 Volume */
-#define WM8994_LEFTLINE_34_VOL 0x19 /* Left Line Input 3&4 Volume */
-#define WM8994_RIGHTLINE_12_VOL 0x1A /* Right Line Input 1&2 Volume */
-#define WM8994_RIGHTLINE_34_VOL 0x1B /* Right Line Input 3&4 Volume */
-
-#define WM8994_LEFT_OUTPUT_VOL 0x1C /* Left Output Volume */
-#define WM8994_RIGHT_OUTPUT_VOL 0x1D /* Right Output Volume */
-#define WM8994_LINE_OUTPUTS_VOL 0x1E /* Line Outputs Volume */
-#define WM8994_HPOUT2_VOL 0x1F /* HPOUT2 Volume */
-#define WM8994_LEFT_OPGA_VOL 0x20 /* Left OPGA Volume */
-#define WM8994_RIGHT_OPGA_VOL 0x21 /* Right OPGA Volume */
-
-#define WM8994_SPKMIXL_ATT 0x22 /* SPKMIXL Attenuation */
-#define WM8994_SPKMIXR_ATT 0x23 /* SPKMIXR Attenuation */
-#define WM8994_SPKOUT_MIXERS 0x24 /* SPKOUT Mixers */
-
-#define WM8994_CLASS_D 0x25 /* ClassD */
-#define WM8994_SPEAKER_VOL_LEFT 0x26 /* Speaker Volume left */
-#define WM8994_SPEAKER_VOL_RIGHT 0x27 /* Speaker Volume right */
-
-#define WM8994_INPUT_MIXER2 0x28 /* Input Mixer (2) */
-#define WM8994_INPUT_MIXER3 0x29 /* Input Mixer (3) */
-#define WM8994_INPUT_MIXER4 0x2A /* Input Mixer (4) */
-#define WM8994_INPUT_MIXER5 0x2B /* Input Mixer (5) */
-#define WM8994_INPUT_MIXER6 0x2C /* Input Mixer (6) */
-
-#define WM8994_OUTPUT_MIXER1 0x2D /* Output Mixer (1) */
-#define WM8994_OUTPUT_MIXER2 0x2E /* Output Mixer (2) */
-#define WM8994_OUTPUT_MIXER3 0x2F /* Output Mixer (3) */
-#define WM8994_OUTPUT_MIXER4 0x30 /* Output Mixer (4) */
-#define WM8994_OUTPUT_MIXER5 0x31 /* Output Mixer (5) */
-#define WM8994_OUTPUT_MIXER6 0x32 /* Output Mixer (6) */
-
-#define WM8994_HPOUT2_MIXER 0x33 /* HPOUT2 Mixer */
-
-#define WM8994_LINE_MIXER1 0x34 /* Line Mixer (1) */
-#define WM8994_LINE_MIXER2 0x35 /* Line Mixer (2) */
-
-#define WM8994_SPEAKER_MIXER 0x36 /* Speaker Mixer */
-
-#define WM8994_ADDITIONAL_CTL 0x37 /* Additional Control */
-#define WM8994_ANTI_POP1 0x38 /* AntiPOP (1) */
-#define WM8994_ANTI_POP2 0x39 /* AntiPOP (2) */
-
-#define WM8994_MIC_BIAS 0x3A /* MICBIAS */
-
-#define WM8994_LDO_1 0x3B /* LDO 1 */
-#define WM8994_LDO_2 0x3C /* LDO 2 */
-
-#define WM8994_CHARGE_PUMP1 0x4C /* Charge Pump 1 */
-#define WM8994_CHARGE_PUMP2 0x4D /* Charge Pump 2 */
-
-#define WM8994_CLASS_W_1 0x51 /* Class W (1) */
-
-#define WM8994_DC_SERVO1 0x54 /* DC Servo (1) */
-#define WM8994_DC_SERVO2 0x55 /* DC Servo (2) */
-#define WM8994_DC_SERVO_RB 0x58 /* DC Servo Readback */
-#define WM8994_DC_SERVO4 0x59 /* DC Servo (4) */
-
-#define WM8994_ANA_HP1 0x60 /* Analogue HP (1) */
-#define WM8994_CHIP_REV 0x100 /* Chip Revision */
-
-#define WM8994_CTL_IF 0x101 /* Control Interface */
-#define WM8994_WR_CTL_SEQ1 0x110 /* Write Sequencer Ctrl (1) */
-#define WM8994_WR_CTL_SEQ2 0x111 /* Write Sequencer Ctrl (2) */
-
-#define WM8994_AIF1_CLK1 0x200 /* AIF1 Clocking (1) */
-#define WM8994_AIF1_CLK2 0x201 /* AIF1 Clocking (2) */
-#define WM8994_AIF2_CLK1 0x204 /* AIF2 Clocking (1) */
-#define WM8994_AIF2_CLK2 0x205 /* AIF2 Clocking (2) */
-#define WM8994_CLK1 0x208 /* Clocking (1) */
-#define WM8994_CLK2 0x209 /* Clocking (2) */
-
-#define WM8994_AIF1_RATE 0x210 /* AIF1 Rate */
-#define WM8994_AIF2_RATE 0x211 /* AIF2 Rate */
-#define WM8994_RATE_STATUS 0x212 /* Rate Status */
-
-#define WM8994_PLL1_CTL1 0x220 /* PLL1 Control (1) */
-#define WM8994_PLL1_CTL2 0x221 /* PLL1 Control (2) */
-#define WM8994_PLL1_CTL3 0x222 /* PLL1 Control (3) */
-#define WM8994_PLL1_CTL4 0x223 /* PLL1 Control (4) */
-#define WM8994_PLL1_CTL5 0x224 /* PLL1 Control (5) */
-
-#define WM8994_PLL2_CTL1 0x240 /* PLL2 Control (1) */
-#define WM8994_PLL2_CTL2 0x241 /* PLL2 Control (2) */
-#define WM8994_PLL2_CTL3 0x242 /* PLL2 Control (3) */
-#define WM8994_PLL2_CTL4 0x243 /* PLL2 Control (4) */
-#define WM8994_PLL2_CTL5 0x244 /* PLL2 Control (5) */
-
-#define WM8994_AIF1_CTL1 0x300 /* AIF1 Control (1) */
-#define WM8994_AIF1_CTL2 0x301 /* AIF1 Control (2) */
-
-#define WM8994_AIF1_MASTER_SLAVE 0x302 /* AIF1 Master/Slave */
-#define WM8994_AIF1_BCLK 0x303 /* AIF1 BCLK */
-#define WM8994_AIF1_ADC_LRCLK 0x304 /* AIF1 ADC LRCLK */
-#define WM8994_AIF1_DAC_LRCLK 0x305 /* AIF1 DAC LRCLK */
-#define WM8994_AIF1_DAC_DATA 0x306 /* AIF1 DAC DATA */
-#define WM8994_AIF1_ADC_DATA 0x307 /* AIF1 ADC DATA */
-
-#define WM8994_AIF2_CTL1 0x310 /* AIF2 Control (1) */
-#define WM8994_AIF2_CTL2 0x311 /* AIF2 Control (2) */
-#define WM8994_AIF2_MASTER_SLAVE 0x312 /* AIF2 Master/Slave */
-#define WM8994_AIF2_BCLK 0x313 /* AIF2 BCLK */
-#define WM8994_AIF2_ADC_LRCLK 0x314 /* AIF2 ADC LRCLK */
-#define WM8994_AIF2_DAC_LRCLK 0x315 /* AIF2 DAC LRCLK */
-#define WM8994_AIF2_DAC_DATA 0x316 /* AIF2 DAC DATA */
-#define WM8994_AIF2_ADC_DATA 0x317 /* AIF2 ADC DATA */
-
-#define WM8994_AIF1_ADC1_LEFT_VOL 0x400 /* AIF1 ADC1 Left Volume */
-#define WM8994_AIF1_ADC1_RIGHT_VOL 0x401 /* AIF1 ADC1 Right Volume */
-#define WM8994_AIF1_DAC1_LEFT_VOL 0x402 /* AIF1 DAC1 Left Volume */
-#define WM8994_AIF1_DAC1_RIGHT_VOL 0x403 /* AIF1 DAC1 Right Volume */
-
-#define WM8994_AIF1_ADC2_LEFT_VOL 0x404 /* AIF1 ADC2 Left Volume */
-#define WM8994_AIF1_ADC2_RIGHT_VOL 0x405 /* AIF1 ADC2 Right Volume */
-#define WM8994_AIF1_DAC2_LEFT_VOL 0x406 /* AIF1 DAC2 Left Volume */
-#define WM8994_AIF1_DAC2_RIGHT_VOL 0x407 /* AIF1 DAC2 Right Volume */
-
-#define WM8994_AIF1_ADC1_FILTERS 0x410 /* AIF1 ADC1 Filters */
-#define WM8994_AIF1_ADC2_FILTERS 0x411 /* AIF1 ADC2 Filters */
-
-#define WM8994_AIF1_DAC1_FILTERS1 0x420 /* AIF1 DAC1 Filters (1) */
-#define WM8994_AIF1_DAC1_FILTERS2 0x421 /* AIF1 DAC1 Filters (2) */
-#define WM8994_AIF1_DAC2_FILTERS1 0x422 /* AIF1 DAC2 Filters (1) */
-#define WM8994_AIF1_DAC2_FILTERS2 0x423 /* AIF1 DAC2 Filters (2) */
-
-#define WM8994_AIF1_DRC1_1 0x440 /* AIF1 DRC1 (1) */
-#define WM8994_AIF1_DRC1_2 0x441 /* AIF1 DRC1 (2) */
-#define WM8994_AIF1_DRC1_3 0x442 /* AIF1 DRC1 (3) */
-#define WM8994_AIF1_DRC1_4 0x443 /* AIF1 DRC1 (4) */
-#define WM8994_AIF1_DRC1_5 0x444 /* AIF1 DRC1 (5) */
-
-#define WM8994_AIF1_DRC2_1 0x450 /* AIF1 DRC2 (1) */
-#define WM8994_AIF1_DRC2_2 0x451 /* AIF1 DRC2 (2) */
-#define WM8994_AIF1_DRC2_3 0x452 /* AIF1 DRC2 (3) */
-#define WM8994_AIF1_DRC2_4 0x453 /* AIF1 DRC2 (4) */
-#define WM8994_AIF1_DRC2_5 0x454 /* AIF1 DRC2 (5) */
-
-#define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480 /* AIF1 DAC1 EQ Gains (1) */
-#define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481 /* AIF1 DAC1 EQ Gains (2) */
-#define WM8994_AIF1_DAC1_EQ_BAND_1A 0x482 /* AIF1 DAC1 EQ Band 1 A */
-#define WM8994_AIF1_DAC1_EQ_BAND_1B 0x483 /* AIF1 DAC1 EQ Band 1 B */
-#define WM8994_AIF1_DAC1_EQ_BAND_1PG 0x484 /* AIF1 DAC1 EQ Band 1 PG */
-#define WM8994_AIF1_DAC1_EQ_BAND_2A 0x485 /* AIF1 DAC1 EQ Band 2 A */
-#define WM8994_AIF1_DAC1_EQ_BAND_2B 0x486 /* AIF1 DAC1 EQ Band 2 B */
-#define WM8994_AIF1_DAC1_EQ_BAND_2C 0x487 /* AIF1 DAC1 EQ Band 2 C */
-#define WM8994_AIF1_DAC1_EQ_BAND_2PG 0x488 /* AIF1 DAC1 EQ Band 2 PG */
-#define WM8994_AIF1_DAC1_EQ_BAND_3A 0x489 /* AIF1 DAC1 EQ Band 3 A */
-#define WM8994_AIF1_DAC1_EQ_BAND_3B 0x48A /* AIF1 DAC1 EQ Band 3 B */
-#define WM8994_AIF1_DAC1_EQ_BAND_3C 0x48B /* AIF1 DAC1 EQ Band 3 C */
-#define WM8994_AIF1_DAC1_EQ_BAND_3PG 0x48C /* AIF1 DAC1 EQ Band 3 PG */
-#define WM8994_AIF1_DAC1_EQ_BAND_4A 0x48D /* AIF1 DAC1 EQ Band 4 A */
-#define WM8994_AIF1_DAC1_EQ_BAND_4B 0x48E /* AIF1 DAC1 EQ Band 4 B */
-#define WM8994_AIF1_DAC1_EQ_BAND_4C 0x48F /* AIF1 DAC1 EQ Band 4 C */
-#define WM8994_AIF1_DAC1_EQ_BAND_4PG 0x490 /* AIF1 DAC1 EQ Band 4 PG */
-#define WM8994_AIF1_DAC1_EQ_BAND_5A 0x491 /* AIF1 DAC1 EQ Band 5 A */
-#define WM8994_AIF1_DAC1_EQ_BAND_5B 0x492 /* AIF1 DAC1 EQ Band 5 B */
-#define WM8994_AIF1_DAC1_EQ_BAND_5PG 0x493 /* AIF1 DAC1 EQ Band 5 PG */
-
-#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0 /* AIF1 DAC2 EQ Gains (1) */
-#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1 /* AIF1 DAC2 EQ Gains (2) */
-#define WM8994_AIF1_DAC2_EQ_BAND_1A 0x4A2 /* AIF1 DAC2 EQ Band 1 A */
-#define WM8994_AIF1_DAC2_EQ_BAND_1B 0x4A3 /* AIF1 DAC2 EQ Band 1 B */
-#define WM8994_AIF1_DAC2_EQ_BAND_1PG 0x4A4 /* AIF1 DAC2 EQ Band 1 PG */
-#define WM8994_AIF1_DAC2_EQ_BAND_2A 0x4A5 /* AIF1 DAC2 EQ Band 2 A */
-#define WM8994_AIF1_DAC2_EQ_BAND_2B 0x4A6 /* AIF1 DAC2 EQ Band 2 B */
-#define WM8994_AIF1_DAC2_EQ_BAND_2C 0x4A7 /* AIF1 DAC2 EQ Band 2 C */
-#define WM8994_AIF1_DAC2_EQ_BAND_2PG 0x4A8 /* AIF1 DAC2 EQ Band 2 PG */
-#define WM8994_AIF1_DAC2_EQ_BAND_3A 0x4A9 /* AIF1 DAC2 EQ Band 3 A */
-#define WM8994_AIF1_DAC2_EQ_BAND_3B 0x4AA /* AIF1 DAC2 EQ Band 3 B */
-#define WM8994_AIF1_DAC2_EQ_BAND_3C 0x4AB /* AIF1 DAC2 EQ Band 3 C */
-#define WM8994_AIF1_DAC2_EQ_BAND_3PG 0x4AC /* AIF1 DAC2 EQ Band 3 PG */
-#define WM8994_AIF1_DAC2_EQ_BAND_4A 0x4AD /* AIF1 DAC2 EQ Band 4 A */
-#define WM8994_AIF1_DAC2_EQ_BAND_4B 0x4AE /* AIF1 DAC2 EQ Band 4 B */
-#define WM8994_AIF1_DAC2_EQ_BAND_4C 0x4AF /* AIF1 DAC2 EQ Band 4 C */
-#define WM8994_AIF1_DAC2_EQ_BAND_4PG 0x4B0 /* AIF1 DAC2 EQ Band 4 PG */
-#define WM8994_AIF1_DAC2_EQ_BAND_5A 0x4B1 /* AIF1 DAC2 EQ Band 5 A */
-#define WM8994_AIF1_DAC2_EQ_BAND_5B 0x4B2 /* AIF1 DAC2 EQ Band 5 B */
-#define WM8994_AIF1_DAC2_EQ_BAND_5PG 0x4B3 /* AIF1 DAC2 EQ Band 5 PG */
+#define WM8994_SWRST 0x00 /* SW Reset and ID */
+#define WM8994_ID 0x00 /* SW Reset and ID */
+
+#define WM8994_PM1 0x01 /* Power Management */
+#define WM8994_PM2 0x02 /* Power Management */
+#define WM8994_PM3 0x03 /* Power Management */
+#define WM8994_PM4 0x04 /* Power Management */
+#define WM8994_PM5 0x05 /* Power Management */
+#define WM8994_PM6 0x06 /* Power Management */
+
+#define WM8994_INPUT_MIXER1 0x15 /* Input Mixer (1) */
+
+#define WM8994_LEFTLINE_12_VOL 0x18 /* Left Line Input 1&2 Volume */
+#define WM8994_LEFTLINE_34_VOL 0x19 /* Left Line Input 3&4 Volume */
+#define WM8994_RIGHTLINE_12_VOL 0x1A /* Right Line Input 1&2 Volume */
+#define WM8994_RIGHTLINE_34_VOL 0x1B /* Right Line Input 3&4 Volume */
+
+#define WM8994_LEFT_OUTPUT_VOL 0x1C /* Left Output Volume */
+#define WM8994_RIGHT_OUTPUT_VOL 0x1D /* Right Output Volume */
+#define WM8994_LINE_OUTPUTS_VOL 0x1E /* Line Outputs Volume */
+#define WM8994_HPOUT2_VOL 0x1F /* HPOUT2 Volume */
+#define WM8994_LEFT_OPGA_VOL 0x20 /* Left OPGA Volume */
+#define WM8994_RIGHT_OPGA_VOL 0x21 /* Right OPGA Volume */
+
+#define WM8994_SPKMIXL_ATT 0x22 /* SPKMIXL Attenuation */
+#define WM8994_SPKMIXR_ATT 0x23 /* SPKMIXR Attenuation */
+#define WM8994_SPKOUT_MIXERS 0x24 /* SPKOUT Mixers */
+
+#define WM8994_CLASS_D 0x25 /* ClassD */
+#define WM8994_SPEAKER_VOL_LEFT 0x26 /* Speaker Volume left */
+#define WM8994_SPEAKER_VOL_RIGHT 0x27 /* Speaker Volume right */
+
+#define WM8994_INPUT_MIXER2 0x28 /* Input Mixer (2) */
+#define WM8994_INPUT_MIXER3 0x29 /* Input Mixer (3) */
+#define WM8994_INPUT_MIXER4 0x2A /* Input Mixer (4) */
+#define WM8994_INPUT_MIXER5 0x2B /* Input Mixer (5) */
+#define WM8994_INPUT_MIXER6 0x2C /* Input Mixer (6) */
+
+#define WM8994_OUTPUT_MIXER1 0x2D /* Output Mixer (1) */
+#define WM8994_OUTPUT_MIXER2 0x2E /* Output Mixer (2) */
+#define WM8994_OUTPUT_MIXER3 0x2F /* Output Mixer (3) */
+#define WM8994_OUTPUT_MIXER4 0x30 /* Output Mixer (4) */
+#define WM8994_OUTPUT_MIXER5 0x31 /* Output Mixer (5) */
+#define WM8994_OUTPUT_MIXER6 0x32 /* Output Mixer (6) */
+
+#define WM8994_HPOUT2_MIXER 0x33 /* HPOUT2 Mixer */
+
+#define WM8994_LINE_MIXER1 0x34 /* Line Mixer (1) */
+#define WM8994_LINE_MIXER2 0x35 /* Line Mixer (2) */
+
+#define WM8994_SPEAKER_MIXER 0x36 /* Speaker Mixer */
+
+#define WM8994_ADDITIONAL_CTL 0x37 /* Additional Control */
+#define WM8994_ANTI_POP1 0x38 /* AntiPOP (1) */
+#define WM8994_ANTI_POP2 0x39 /* AntiPOP (2) */
+
+#define WM8994_MIC_BIAS 0x3A /* MICBIAS */
+
+#define WM8994_LDO_1 0x3B /* LDO 1 */
+#define WM8994_LDO_2 0x3C /* LDO 2 */
+
+#define WM8994_CHARGE_PUMP1 0x4C /* Charge Pump 1 */
+#define WM8994_CHARGE_PUMP2 0x4D /* Charge Pump 2 */
+
+#define WM8994_CLASS_W_1 0x51 /* Class W (1) */
+
+#define WM8994_DC_SERVO1 0x54 /* DC Servo (1) */
+#define WM8994_DC_SERVO2 0x55 /* DC Servo (2) */
+#define WM8994_DC_SERVO_RB 0x58 /* DC Servo Readback */
+#define WM8994_DC_SERVO4 0x59 /* DC Servo (4) */
+
+#define WM8994_ANA_HP1 0x60 /* Analogue HP (1) */
+#define WM8994_CHIP_REV 0x100 /* Chip Revision */
+
+#define WM8994_CTL_IF 0x101 /* Control Interface */
+#define WM8994_WR_CTL_SEQ1 0x110 /* Write Sequencer Ctrl (1) */
+#define WM8994_WR_CTL_SEQ2 0x111 /* Write Sequencer Ctrl (2) */
+
+#define WM8994_AIF1_CLK1 0x200 /* AIF1 Clocking (1) */
+#define WM8994_AIF1_CLK2 0x201 /* AIF1 Clocking (2) */
+#define WM8994_AIF2_CLK1 0x204 /* AIF2 Clocking (1) */
+#define WM8994_AIF2_CLK2 0x205 /* AIF2 Clocking (2) */
+#define WM8994_CLK1 0x208 /* Clocking (1) */
+#define WM8994_CLK2 0x209 /* Clocking (2) */
+
+#define WM8994_AIF1_RATE 0x210 /* AIF1 Rate */
+#define WM8994_AIF2_RATE 0x211 /* AIF2 Rate */
+#define WM8994_RATE_STATUS 0x212 /* Rate Status */
+
+#define WM8994_PLL1_CTL1 0x220 /* PLL1 Control (1) */
+#define WM8994_PLL1_CTL2 0x221 /* PLL1 Control (2) */
+#define WM8994_PLL1_CTL3 0x222 /* PLL1 Control (3) */
+#define WM8994_PLL1_CTL4 0x223 /* PLL1 Control (4) */
+#define WM8994_PLL1_CTL5 0x224 /* PLL1 Control (5) */
+
+#define WM8994_PLL2_CTL1 0x240 /* PLL2 Control (1) */
+#define WM8994_PLL2_CTL2 0x241 /* PLL2 Control (2) */
+#define WM8994_PLL2_CTL3 0x242 /* PLL2 Control (3) */
+#define WM8994_PLL2_CTL4 0x243 /* PLL2 Control (4) */
+#define WM8994_PLL2_CTL5 0x244 /* PLL2 Control (5) */
+
+#define WM8994_AIF1_CTL1 0x300 /* AIF1 Control (1) */
+#define WM8994_AIF1_CTL2 0x301 /* AIF1 Control (2) */
+
+#define WM8994_AIF1_MASTER_SLAVE 0x302 /* AIF1 Master/Slave */
+#define WM8994_AIF1_BCLK 0x303 /* AIF1 BCLK */
+#define WM8994_AIF1_ADC_LRCLK 0x304 /* AIF1 ADC LRCLK */
+#define WM8994_AIF1_DAC_LRCLK 0x305 /* AIF1 DAC LRCLK */
+#define WM8994_AIF1_DAC_DATA 0x306 /* AIF1 DAC DATA */
+#define WM8994_AIF1_ADC_DATA 0x307 /* AIF1 ADC DATA */
+
+#define WM8994_AIF2_CTL1 0x310 /* AIF2 Control (1) */
+#define WM8994_AIF2_CTL2 0x311 /* AIF2 Control (2) */
+#define WM8994_AIF2_MASTER_SLAVE 0x312 /* AIF2 Master/Slave */
+#define WM8994_AIF2_BCLK 0x313 /* AIF2 BCLK */
+#define WM8994_AIF2_ADC_LRCLK 0x314 /* AIF2 ADC LRCLK */
+#define WM8994_AIF2_DAC_LRCLK 0x315 /* AIF2 DAC LRCLK */
+#define WM8994_AIF2_DAC_DATA 0x316 /* AIF2 DAC DATA */
+#define WM8994_AIF2_ADC_DATA 0x317 /* AIF2 ADC DATA */
+
+#define WM8994_AIF1_ADC1_LEFT_VOL 0x400 /* AIF1 ADC1 Left Volume */
+#define WM8994_AIF1_ADC1_RIGHT_VOL 0x401 /* AIF1 ADC1 Right Volume */
+#define WM8994_AIF1_DAC1_LEFT_VOL 0x402 /* AIF1 DAC1 Left Volume */
+#define WM8994_AIF1_DAC1_RIGHT_VOL 0x403 /* AIF1 DAC1 Right Volume */
+
+#define WM8994_AIF1_ADC2_LEFT_VOL 0x404 /* AIF1 ADC2 Left Volume */
+#define WM8994_AIF1_ADC2_RIGHT_VOL 0x405 /* AIF1 ADC2 Right Volume */
+#define WM8994_AIF1_DAC2_LEFT_VOL 0x406 /* AIF1 DAC2 Left Volume */
+#define WM8994_AIF1_DAC2_RIGHT_VOL 0x407 /* AIF1 DAC2 Right Volume */
+
+#define WM8994_AIF1_ADC1_FILTERS 0x410 /* AIF1 ADC1 Filters */
+#define WM8994_AIF1_ADC2_FILTERS 0x411 /* AIF1 ADC2 Filters */
+
+#define WM8994_AIF1_DAC1_FILTERS1 0x420 /* AIF1 DAC1 Filters (1) */
+#define WM8994_AIF1_DAC1_FILTERS2 0x421 /* AIF1 DAC1 Filters (2) */
+#define WM8994_AIF1_DAC2_FILTERS1 0x422 /* AIF1 DAC2 Filters (1) */
+#define WM8994_AIF1_DAC2_FILTERS2 0x423 /* AIF1 DAC2 Filters (2) */
+
+#define WM8994_AIF1_DRC1_1 0x440 /* AIF1 DRC1 (1) */
+#define WM8994_AIF1_DRC1_2 0x441 /* AIF1 DRC1 (2) */
+#define WM8994_AIF1_DRC1_3 0x442 /* AIF1 DRC1 (3) */
+#define WM8994_AIF1_DRC1_4 0x443 /* AIF1 DRC1 (4) */
+#define WM8994_AIF1_DRC1_5 0x444 /* AIF1 DRC1 (5) */
+
+#define WM8994_AIF1_DRC2_1 0x450 /* AIF1 DRC2 (1) */
+#define WM8994_AIF1_DRC2_2 0x451 /* AIF1 DRC2 (2) */
+#define WM8994_AIF1_DRC2_3 0x452 /* AIF1 DRC2 (3) */
+#define WM8994_AIF1_DRC2_4 0x453 /* AIF1 DRC2 (4) */
+#define WM8994_AIF1_DRC2_5 0x454 /* AIF1 DRC2 (5) */
+
+#define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480 /* AIF1 DAC1 EQ Gains (1) */
+#define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481 /* AIF1 DAC1 EQ Gains (2) */
+#define WM8994_AIF1_DAC1_EQ_BAND_1A 0x482 /* AIF1 DAC1 EQ Band 1 A */
+#define WM8994_AIF1_DAC1_EQ_BAND_1B 0x483 /* AIF1 DAC1 EQ Band 1 B */
+#define WM8994_AIF1_DAC1_EQ_BAND_1PG 0x484 /* AIF1 DAC1 EQ Band 1 PG */
+#define WM8994_AIF1_DAC1_EQ_BAND_2A 0x485 /* AIF1 DAC1 EQ Band 2 A */
+#define WM8994_AIF1_DAC1_EQ_BAND_2B 0x486 /* AIF1 DAC1 EQ Band 2 B */
+#define WM8994_AIF1_DAC1_EQ_BAND_2C 0x487 /* AIF1 DAC1 EQ Band 2 C */
+#define WM8994_AIF1_DAC1_EQ_BAND_2PG 0x488 /* AIF1 DAC1 EQ Band 2 PG */
+#define WM8994_AIF1_DAC1_EQ_BAND_3A 0x489 /* AIF1 DAC1 EQ Band 3 A */
+#define WM8994_AIF1_DAC1_EQ_BAND_3B 0x48A /* AIF1 DAC1 EQ Band 3 B */
+#define WM8994_AIF1_DAC1_EQ_BAND_3C 0x48B /* AIF1 DAC1 EQ Band 3 C */
+#define WM8994_AIF1_DAC1_EQ_BAND_3PG 0x48C /* AIF1 DAC1 EQ Band 3 PG */
+#define WM8994_AIF1_DAC1_EQ_BAND_4A 0x48D /* AIF1 DAC1 EQ Band 4 A */
+#define WM8994_AIF1_DAC1_EQ_BAND_4B 0x48E /* AIF1 DAC1 EQ Band 4 B */
+#define WM8994_AIF1_DAC1_EQ_BAND_4C 0x48F /* AIF1 DAC1 EQ Band 4 C */
+#define WM8994_AIF1_DAC1_EQ_BAND_4PG 0x490 /* AIF1 DAC1 EQ Band 4 PG */
+#define WM8994_AIF1_DAC1_EQ_BAND_5A 0x491 /* AIF1 DAC1 EQ Band 5 A */
+#define WM8994_AIF1_DAC1_EQ_BAND_5B 0x492 /* AIF1 DAC1 EQ Band 5 B */
+#define WM8994_AIF1_DAC1_EQ_BAND_5PG 0x493 /* AIF1 DAC1 EQ Band 5 PG */
+
+#define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0 /* AIF1 DAC2 EQ Gains (1) */
+#define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1 /* AIF1 DAC2 EQ Gains (2) */
+#define WM8994_AIF1_DAC2_EQ_BAND_1A 0x4A2 /* AIF1 DAC2 EQ Band 1 A */
+#define WM8994_AIF1_DAC2_EQ_BAND_1B 0x4A3 /* AIF1 DAC2 EQ Band 1 B */
+#define WM8994_AIF1_DAC2_EQ_BAND_1PG 0x4A4 /* AIF1 DAC2 EQ Band 1 PG */
+#define WM8994_AIF1_DAC2_EQ_BAND_2A 0x4A5 /* AIF1 DAC2 EQ Band 2 A */
+#define WM8994_AIF1_DAC2_EQ_BAND_2B 0x4A6 /* AIF1 DAC2 EQ Band 2 B */
+#define WM8994_AIF1_DAC2_EQ_BAND_2C 0x4A7 /* AIF1 DAC2 EQ Band 2 C */
+#define WM8994_AIF1_DAC2_EQ_BAND_2PG 0x4A8 /* AIF1 DAC2 EQ Band 2 PG */
+#define WM8994_AIF1_DAC2_EQ_BAND_3A 0x4A9 /* AIF1 DAC2 EQ Band 3 A */
+#define WM8994_AIF1_DAC2_EQ_BAND_3B 0x4AA /* AIF1 DAC2 EQ Band 3 B */
+#define WM8994_AIF1_DAC2_EQ_BAND_3C 0x4AB /* AIF1 DAC2 EQ Band 3 C */
+#define WM8994_AIF1_DAC2_EQ_BAND_3PG 0x4AC /* AIF1 DAC2 EQ Band 3 PG */
+#define WM8994_AIF1_DAC2_EQ_BAND_4A 0x4AD /* AIF1 DAC2 EQ Band 4 A */
+#define WM8994_AIF1_DAC2_EQ_BAND_4B 0x4AE /* AIF1 DAC2 EQ Band 4 B */
+#define WM8994_AIF1_DAC2_EQ_BAND_4C 0x4AF /* AIF1 DAC2 EQ Band 4 C */
+#define WM8994_AIF1_DAC2_EQ_BAND_4PG 0x4B0 /* AIF1 DAC2 EQ Band 4 PG */
+#define WM8994_AIF1_DAC2_EQ_BAND_5A 0x4B1 /* AIF1 DAC2 EQ Band 5 A */
+#define WM8994_AIF1_DAC2_EQ_BAND_5B 0x4B2 /* AIF1 DAC2 EQ Band 5 B */
+#define WM8994_AIF1_DAC2_EQ_BAND_5PG 0x4B3 /* AIF1 DAC2 EQ Band 5 PG */
/* AIF2 */
-#define WM8994_AIF2_ADC1_LEFT_VOL 0x500 /* AIF2 ADC1 Left Volume */
-#define WM8994_AIF2_ADC1_RIGHT_VOL 0x501 /* AIF2 ADC1 Right Volume */
-#define WM8994_AIF2_DAC1_LEFT_VOL 0x502 /* AIF2 DAC1 Left Volume */
-#define WM8994_AIF2_DAC1_RIGHT_VOL 0x503 /* AIF2 DAC1 Right Volume */
-
-#define WM8994_AIF2_ADC_FILTERS 0x510 /* AIF2 ADC Filters */
-#define WM8994_AIF2_DAC_FILTERS1 0x520 /* AIF2 DAC Filters (1) */
-#define WM8994_AIF2_DAC_FILTERS2 0x521 /* AIF2 DAC Filters (2) */
-
-#define WM8994_AIF2_DRC_1 0x540 /* AIF2 DRC (1) */
-#define WM8994_AIF2_DRC_2 0x541 /* AIF2 DRC (2) */
-#define WM8994_AIF2_DRC_3 0x542 /* AIF2 DRC (3) */
-#define WM8994_AIF2_DRC_4 0x543 /* AIF2 DRC (4) */
-#define WM8994_AIF2_DRC_5 0x544 /* AIF2 DRC (5) */
-
-#define WM8994_AIF2_EQ_GAINS_1 0x580 /* AIF2 EQ Gains (1) */
-#define WM8994_AIF2_EQ_GAINS_2 0x581 /* AIF2 EQ Gains (2) */
-#define WM8994_AIF2_EQ_BAND_1A 0x582 /* AIF2 EQ Band 1 A */
-#define WM8994_AIF2_EQ_BAND_1B 0x583 /* AIF2 EQ Band 1 B */
-#define WM8994_AIF2_EQ_BAND_1PG 0x584 /* AIF2 EQ Band 1 PG */
-#define WM8994_AIF2_EQ_BAND_2A 0x585 /* AIF2 EQ Band 2 A */
-#define WM8994_AIF2_EQ_BAND_2B 0x586 /* AIF2 EQ Band 2 B */
-#define WM8994_AIF2_EQ_BAND_2C 0x587 /* AIF2 EQ Band 2 C */
-#define WM8994_AIF2_EQ_BAND_2PG 0x588 /* AIF2 EQ Band 2 PG */
-#define WM8994_AIF2_EQ_BAND_3A 0x589 /* AIF2 EQ Band 3 A */
-#define WM8994_AIF2_EQ_BAND_3B 0x58A /* AIF2 EQ Band 3 B */
-#define WM8994_AIF2_EQ_BAND_3C 0x58B /* AIF2 EQ Band 3 C */
-#define WM8994_AIF2_EQ_BAND_3PG 0x58C /* AIF2 EQ Band 3 PG */
-#define WM8994_AIF2_EQ_BAND_4A 0x58D /* AIF2 EQ Band 4 A */
-#define WM8994_AIF2_EQ_BAND_4B 0x58E /* AIF2 EQ Band 4 B */
-#define WM8994_AIF2_EQ_BAND_4C 0x58F /* AIF2 EQ Band 4 C */
-#define WM8994_AIF2_EQ_BAND_4PG 0x490 /* AIF2 EQ Band 4 PG */
-#define WM8994_AIF2_EQ_BAND_5A 0x591 /* AIF2 EQ Band 5 A */
-#define WM8994_AIF2_EQ_BAND_5B 0x592 /* AIF2 EQ Band 5 B */
-#define WM8994_AIF2_EQ_BAND_5PG 0x593 /* AIF2 EQ Band 5 PG */
-
-#define WM8994_DAC1_MIXER_VOLS 0x600 /* DAC1 Mixer Volumes */
-#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 /* DAC1 Left Mixer Routing */
-#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 /* DAC1 Right Mixer Routing */
-
-#define WM8994_DAC2_MIXER_VOLS 0x603 /* DAC2 Mixer Volumes */
-#define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604 /* DAC2 Left Mixer Routing */
-#define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605 /* DAC2 Right Mixer Routing */
-
-#define WM8994_ADC1_LEFT_MIXER_ROUTING 0x606 /* ADC1 Left Mixer Routing */
-#define WM8994_ADC1_RIGHT_MIXER_ROUTING 0x607 /* ADC1 Right Mixer Routing */
-
-#define WM8994_ADC2_LEFT_MIXER_ROUTING 0x608 /* ADC2 Left Mixer Routing */
-#define WM8994_ADC2_RIGHT_MIXER_ROUTING 0x609 /* ADC2 Right Mixer Routing */
-
-#define WM8994_DAC1_LEFT_VOL 0x610 /* DAC1 Left Volume */
-#define WM8994_DAC1_RIGHT_VOL 0x611 /* DAC1 Right Volume */
-
-#define WM8994_DAC2_LEFT_VOL 0x612 /* DAC2 Left Volume */
-#define WM8994_DAC2_RIGHT_VOL 0x613 /* DAC2 Right Volume */
-
-#define WM8994_DAC_SOFT_MUTE 0x614 /* DAC Softmute */
-
-#define WM8994_OVER_SAMPLING 0x620 /* Oversampling */
-#define WM8994_SIDE_TONE 0x621 /* Sidetone */
-
-#define WM8994_GPIO1 0x700 /* GPIO 1 */
-#define WM8994_GPIO2 0x701 /* GPIO 2 */
-#define WM8994_GPIO3 0x702 /* GPIO 3 */
-#define WM8994_GPIO4 0x703 /* GPIO 4 */
-#define WM8994_GPIO5 0x704 /* GPIO 5 */
-#define WM8994_GPIO6 0x705 /* GPIO 6 */
-#define WM8994_GPIO7 0x706 /* GPIO 7 */
-#define WM8994_GPIO8 0x707 /* GPIO 8 */
-#define WM8994_GPIO9 0x708 /* GPIO 9 */
-#define WM8994_GPIO10 0x709 /* GPIO 10 */
-#define WM8994_GPIO11 0x70A /* GPIO 11 */
-
-#define WM8994_PULL_CTL1 0x720 /* Pull Control (1) */
-#define WM8994_PULL_CTL2 0x721 /* Pull Control (2) */
-
-#define WM8994_INT_STATUS1 0x730 /* Interrupt Status 1 */
-#define WM8994_INT_STATUS2 0x731 /* Interrupt Status 2 */
-#define WM8994_INT_RAW_STATUS2 0x732 /* Interrupt Raw Status 2 */
-#define WM8994_INT_STATUS1_MASK 0x738 /* Interrupt Status 1 Mask */
-#define WM8994_INT_STATUS2_MASK 0x739 /* Interrupt Status 2 Mask */
-#define WM8994_INT_CTL 0x740 /* Interrupt Control */
-#define WM8994_INT_DEBOUNCE 0x748 /* IRQ Debounce */
+#define WM8994_AIF2_ADC1_LEFT_VOL 0x500 /* AIF2 ADC1 Left Volume */
+#define WM8994_AIF2_ADC1_RIGHT_VOL 0x501 /* AIF2 ADC1 Right Volume */
+#define WM8994_AIF2_DAC1_LEFT_VOL 0x502 /* AIF2 DAC1 Left Volume */
+#define WM8994_AIF2_DAC1_RIGHT_VOL 0x503 /* AIF2 DAC1 Right Volume */
+
+#define WM8994_AIF2_ADC_FILTERS 0x510 /* AIF2 ADC Filters */
+#define WM8994_AIF2_DAC_FILTERS1 0x520 /* AIF2 DAC Filters (1) */
+#define WM8994_AIF2_DAC_FILTERS2 0x521 /* AIF2 DAC Filters (2) */
+
+#define WM8994_AIF2_DRC_1 0x540 /* AIF2 DRC (1) */
+#define WM8994_AIF2_DRC_2 0x541 /* AIF2 DRC (2) */
+#define WM8994_AIF2_DRC_3 0x542 /* AIF2 DRC (3) */
+#define WM8994_AIF2_DRC_4 0x543 /* AIF2 DRC (4) */
+#define WM8994_AIF2_DRC_5 0x544 /* AIF2 DRC (5) */
+
+#define WM8994_AIF2_EQ_GAINS_1 0x580 /* AIF2 EQ Gains (1) */
+#define WM8994_AIF2_EQ_GAINS_2 0x581 /* AIF2 EQ Gains (2) */
+#define WM8994_AIF2_EQ_BAND_1A 0x582 /* AIF2 EQ Band 1 A */
+#define WM8994_AIF2_EQ_BAND_1B 0x583 /* AIF2 EQ Band 1 B */
+#define WM8994_AIF2_EQ_BAND_1PG 0x584 /* AIF2 EQ Band 1 PG */
+#define WM8994_AIF2_EQ_BAND_2A 0x585 /* AIF2 EQ Band 2 A */
+#define WM8994_AIF2_EQ_BAND_2B 0x586 /* AIF2 EQ Band 2 B */
+#define WM8994_AIF2_EQ_BAND_2C 0x587 /* AIF2 EQ Band 2 C */
+#define WM8994_AIF2_EQ_BAND_2PG 0x588 /* AIF2 EQ Band 2 PG */
+#define WM8994_AIF2_EQ_BAND_3A 0x589 /* AIF2 EQ Band 3 A */
+#define WM8994_AIF2_EQ_BAND_3B 0x58A /* AIF2 EQ Band 3 B */
+#define WM8994_AIF2_EQ_BAND_3C 0x58B /* AIF2 EQ Band 3 C */
+#define WM8994_AIF2_EQ_BAND_3PG 0x58C /* AIF2 EQ Band 3 PG */
+#define WM8994_AIF2_EQ_BAND_4A 0x58D /* AIF2 EQ Band 4 A */
+#define WM8994_AIF2_EQ_BAND_4B 0x58E /* AIF2 EQ Band 4 B */
+#define WM8994_AIF2_EQ_BAND_4C 0x58F /* AIF2 EQ Band 4 C */
+#define WM8994_AIF2_EQ_BAND_4PG 0x590 /* AIF2 EQ Band 4 PG */
+#define WM8994_AIF2_EQ_BAND_5A 0x591 /* AIF2 EQ Band 5 A */
+#define WM8994_AIF2_EQ_BAND_5B 0x592 /* AIF2 EQ Band 5 B */
+#define WM8994_AIF2_EQ_BAND_5PG 0x593 /* AIF2 EQ Band 5 PG */
+
+#define WM8994_DAC1_MIXER_VOLS 0x600 /* DAC1 Mixer Volumes */
+#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 /* DAC1 Left Mixer Routing */
+#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 /* DAC1 Right Mixer Routing */
+
+#define WM8994_DAC2_MIXER_VOLS 0x603 /* DAC2 Mixer Volumes */
+#define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604 /* DAC2 Left Mixer Routing */
+#define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605 /* DAC2 Right Mixer Routing */
+
+#define WM8994_ADC1_LEFT_MIXER_ROUTING 0x606 /* ADC1 Left Mixer Routing */
+#define WM8994_ADC1_RIGHT_MIXER_ROUTING 0x607 /* ADC1 Right Mixer Routing */
+
+#define WM8994_ADC2_LEFT_MIXER_ROUTING 0x608 /* ADC2 Left Mixer Routing */
+#define WM8994_ADC2_RIGHT_MIXER_ROUTING 0x609 /* ADC2 Right Mixer Routing */
+
+#define WM8994_DAC1_LEFT_VOL 0x610 /* DAC1 Left Volume */
+#define WM8994_DAC1_RIGHT_VOL 0x611 /* DAC1 Right Volume */
+
+#define WM8994_DAC2_LEFT_VOL 0x612 /* DAC2 Left Volume */
+#define WM8994_DAC2_RIGHT_VOL 0x613 /* DAC2 Right Volume */
+
+#define WM8994_DAC_SOFT_MUTE 0x614 /* DAC Softmute */
+
+#define WM8994_OVER_SAMPLING 0x620 /* Oversampling */
+#define WM8994_SIDE_TONE 0x621 /* Sidetone */
+
+#define WM8994_GPIO1 0x700 /* GPIO 1 */
+#define WM8994_GPIO2 0x701 /* GPIO 2 */
+#define WM8994_GPIO3 0x702 /* GPIO 3 */
+#define WM8994_GPIO4 0x703 /* GPIO 4 */
+#define WM8994_GPIO5 0x704 /* GPIO 5 */
+#define WM8994_GPIO6 0x705 /* GPIO 6 */
+#define WM8994_GPIO7 0x706 /* GPIO 7 */
+#define WM8994_GPIO8 0x707 /* GPIO 8 */
+#define WM8994_GPIO9 0x708 /* GPIO 9 */
+#define WM8994_GPIO10 0x709 /* GPIO 10 */
+#define WM8994_GPIO11 0x70A /* GPIO 11 */
+
+#define WM8994_PULL_CTL1 0x720 /* Pull Control (1) */
+#define WM8994_PULL_CTL2 0x721 /* Pull Control (2) */
+
+#define WM8994_INT_STATUS1 0x730 /* Interrupt Status 1 */
+#define WM8994_INT_STATUS2 0x731 /* Interrupt Status 2 */
+#define WM8994_INT_RAW_STATUS2 0x732 /* Interrupt Raw Status 2 */
+#define WM8994_INT_STATUS1_MASK 0x738 /* Interrupt Status 1 Mask */
+#define WM8994_INT_STATUS2_MASK 0x739 /* Interrupt Status 2 Mask */
+#define WM8994_INT_CTL 0x740 /* Interrupt Control */
+#define WM8994_INT_DEBOUNCE 0x748 /* IRQ Debounce */
#if 0
-#define WM8994_WR_SEQ0 0x3000 /* Write Sequencer 0 */
-#define WM8994_WR_SEQ1 0x3001 /* Write Sequencer 1 */
-#define WM8994_WR_SEQ2 0x3002 /* Write Sequencer 2 */
-#define WM8994_WR_SEQ3 0x3003 /* Write Sequencer 3 */
-
-#define WM8994_WR_SEQ508 0x31FC /* Write Sequencer 508 */
-#define WM8994_WR_SEQ509 0x31FD /* Write Sequencer 509 */
-#define WM8994_WR_SEQ510 0x31FE /* Write Sequencer 510 */
-#define WM8994_WR_SEQ511 0x31FF /* Write Sequencer 511 */
+#define WM8994_WR_SEQ0 0x3000 /* Write Sequencer 0 */
+#define WM8994_WR_SEQ1 0x3001 /* Write Sequencer 1 */
+#define WM8994_WR_SEQ2 0x3002 /* Write Sequencer 2 */
+#define WM8994_WR_SEQ3 0x3003 /* Write Sequencer 3 */
+
+#define WM8994_WR_SEQ508 0x31FC /* Write Sequencer 508 */
+#define WM8994_WR_SEQ509 0x31FD /* Write Sequencer 509 */
+#define WM8994_WR_SEQ510 0x31FE /* Write Sequencer 510 */
+#define WM8994_WR_SEQ511 0x31FF /* Write Sequencer 511 */
#endif
-#define WM8994_WR_SEQ(x) (0x3000+(x))
+#define WM8994_WR_SEQ(x) (0x3000+(x))
-#define WM8994_WR_SEQ_NUM (511)
+#define WM8994_WR_SEQ_NUM (511)
-#define WM8994_REGISTER_COUNT 736
-#define WM8994_MAX_REGISTER 0x31FF
-#define WM8994_MAX_CACHED_REGISTER 0x749
+#define WM8994_REGISTER_COUNT 736
+#define WM8994_MAX_REGISTER 0x31FF
+#define WM8994_MAX_CACHED_REGISTER 0x749
/* Field Definitions.
*/
@@ -363,10 +363,10 @@
#define WM8994_BIAS_ENA (1 << 0) /* Bit 0: Enables the Normal bias current generator (for all analogue functions */
#define WM8994_BIAS_ENA_DISABLE (0) /* Disabled */
#define WM8994_BIAS_ENA_ENABLE WM8994_BIAS_ENA /* Enabled */
-#define WM8994_VMID_SEL_SHITF (1) /* Bits 1-2: VMID Divider Enable and Select */
+#define WM8994_VMID_SEL_SHIFT (1) /* Bits 1-2: VMID Divider Enable and Select */
#define WM8994_VMID_SEL_DISABLE (0 << WM8994_VMID_SEL_SHIFT) /* VMID disabled (for OFF mode) */
-#define WM8994_VMID_SEL_2x40K (1 << WM8994_VMID_SEL_SHIFT) /* 2*40k divider (for normal operation */
-#define WM8994_VMID_SEL_2x240K (2 << WM8994_VMID_SEL_SHIFT) /* 2*240k divider (for low power standby*/
+#define WM8994_VMID_SEL_2X40K (1 << WM8994_VMID_SEL_SHIFT) /* 2*40k divider (for normal operation */
+#define WM8994_VMID_SEL_2X240K (2 << WM8994_VMID_SEL_SHIFT) /* 2*240k divider (for low power standby*/
/* Bit 3: Reserved */
#define WM8994_MICB1_ENA (1 << 4) /* Bit 4; Microphone Bias 1 Enable */
@@ -510,170 +510,172 @@
/* R5 (0x05) - Power Management (5)
*/
-#define WM8994_DAC1R_ENA (1 << 0) /* Bit 0: Right DAC1 Enable */
-#define WM8994_DAC1L_ENA (1 << 1) /* Bit 1: Left DAC1 Enable */
-#define WM8994_DAC2R_ENA (1 << 2) /* Bit 2: Right DAC2 Enable */
-#define WM8994_DAC2L_ENA (1 << 3) /* Bit 3: Left DAC2 Enable */
-#define WM8994_AIF1DAC1R_ENA (1 << 8) /* Bit 8: Enable AIF1DAC1(Right) input path (AIF1, Timeslot 0) */
-#define WM8994_AIF1DAC1L_ENA (1 << 9) /* Bit 9: Enable AIF1DAC1(Left) input path (AIF1, Timeslot 0) */
-#define WM8994_AIF1DAC2R_ENA (1 << 10) /* Bit 10: Enable AIF1DAC2(Right) input path (AIF1, Timeslot 1) */
-#define WM8994_AIF1DAC2L_ENA (1 << 11) /* Bit 11: Enable AIF1DAC2(Left) input path (AIF1, Timeslot 1) */
-#define WM8994_AIF2DACR_ENA (1 << 12) /* Bit 12: Enable AIF2DAC(Right) input path */
-#define WM8994_AIF2DACL_ENA (1 << 13) /* Bit 13: Enable AIF2DAC(Left) input path */
+#define WM8994_DAC1R_ENA (1 << 0) /* Bit 0: Right DAC1 Enable */
+#define WM8994_DAC1L_ENA (1 << 1) /* Bit 1: Left DAC1 Enable */
+#define WM8994_DAC2R_ENA (1 << 2) /* Bit 2: Right DAC2 Enable */
+#define WM8994_DAC2L_ENA (1 << 3) /* Bit 3: Left DAC2 Enable */
+#define WM8994_AIF1DAC1R_ENA (1 << 8) /* Bit 8: Enable AIF1DAC1(Right) input path (AIF1, Timeslot 0) */
+#define WM8994_AIF1DAC1L_ENA (1 << 9) /* Bit 9: Enable AIF1DAC1(Left) input path (AIF1, Timeslot 0) */
+#define WM8994_AIF1DAC2R_ENA (1 << 10) /* Bit 10: Enable AIF1DAC2(Right) input path (AIF1, Timeslot 1) */
+#define WM8994_AIF1DAC2L_ENA (1 << 11) /* Bit 11: Enable AIF1DAC2(Left) input path (AIF1, Timeslot 1) */
+#define WM8994_AIF2DACR_ENA (1 << 12) /* Bit 12: Enable AIF2DAC(Right) input path */
+#define WM8994_AIF2DACL_ENA (1 << 13) /* Bit 13: Enable AIF2DAC(Left) input path */
/* Bits 14-15: Reserved */
/* R6 (0x06) - Power Management (6)
*/
-#define WM8994_AIF1_DACDAT_SRC (1 << 0) /* Bit 0: AIF1 DACDAT Source Select */
-#define WM8994_AIF1_DACDAT_SRC_DACDAT1 (0) /* DACDAT1 */
-#define WM8994_AIF1_DACDAT_SRC_GPIO8_DACDAT3 (WM8994_AIF1_DACDAT_SRC) /* GPIO8/DACDAT3 */
-#define WM8994_AIF2_DACDAT_SRC (1 << 1) /* Bit 1: AIF2 DACDAT Source Select */
-#define WM8994_AIF2_DACDAT_SRC_GPIO5_DACDAT1 (0) /* GPIO5/DACDAT2 */
-#define WM8994_AIF2_DACDAT_SRC_GPIO8_DACDAT3 (WM8994_AIF2_DACDAT_SRC) /* GPIO8/DACDAT3 */
-#define WM8994_AIF2_ADCDAT_SRC (1 << 2) /* Bit 2: GPIO7/ADCDAT Source Select */
-#define WM8994_AIF2_ADCDAT_SRC_ADCDAT2 (0) /* AIF2 ADCDAT2 */
-#define WM8994_AIF2_ADCDAT_SRC_GPIO8_DACDAT3 (WM8994_AIF2_ADCDAT_SRC) /* GPIO8/DACDAT3 */
-#define WM8994_AIF3_ADCDAT_SRC (1 << 3) /* Bits 3-4: GPIO9/ADCDAT3 Source Select */
-#define WM8994_AIF3_ADCDAR_SRC_AIF1_ADCDAT1 (0) /* AIF1 ADCDAT1 */
-#define WM8994_AIF3_ADCDAR_SRC_AIF2_ADCDAT1 (1 << 3) /* AIF2 ADCDAT2 */
-#define WM8994_AIF3_ADCDAR_SRC_GPIO5_DACDAT2 (2 << 3) /* GPIO5/DACDAT2 */
-#define WM8994_AIF3_TRI (1 << 5) /* Bit 5: AIF3 Audio Interface tri-state */
-#define WM8994_AIF3_TRI_NO (0) /* AIF3 pins operate normally */
-#define WM8994_AIF3_TRI_YES (WM8994_AIF3_TRI) /* Tri-State all AIF3 interface pins */
+#define WM8994_AIF1_DACDAT_SRC (1 << 0) /* Bit 0: AIF1 DACDAT Source Select */
+#define WM8994_AIF1_DACDAT_SRC_DACDAT1 (0) /* DACDAT1 */
+#define WM8994_AIF1_DACDAT_SRC_GPIO8_DACDAT3 (WM8994_AIF1_DACDAT_SRC) /* GPIO8/DACDAT3 */
+#define WM8994_AIF2_DACDAT_SRC (1 << 1) /* Bit 1: AIF2 DACDAT Source Select */
+#define WM8994_AIF2_DACDAT_SRC_GPIO5_DACDAT1 (0) /* GPIO5/DACDAT2 */
+#define WM8994_AIF2_DACDAT_SRC_GPIO8_DACDAT3 (WM8994_AIF2_DACDAT_SRC) /* GPIO8/DACDAT3 */
+#define WM8994_AIF2_ADCDAT_SRC (1 << 2) /* Bit 2: GPIO7/ADCDAT Source Select */
+#define WM8994_AIF2_ADCDAT_SRC_ADCDAT2 (0) /* AIF2 ADCDAT2 */
+#define WM8994_AIF2_ADCDAT_SRC_GPIO8_DACDAT3 (WM8994_AIF2_ADCDAT_SRC) /* GPIO8/DACDAT3 */
+#define WM8994_AIF3_ADCDAT_SRC (1 << 3) /* Bits 3-4: GPIO9/ADCDAT3 Source Select */
+#define WM8994_AIF3_ADCDAR_SRC_AIF1_ADCDAT1 (0) /* AIF1 ADCDAT1 */
+#define WM8994_AIF3_ADCDAR_SRC_AIF2_ADCDAT1 (1 << 3) /* AIF2 ADCDAT2 */
+#define WM8994_AIF3_ADCDAR_SRC_GPIO5_DACDAT2 (2 << 3) /* GPIO5/DACDAT2 */
+#define WM8994_AIF3_TRI (1 << 5) /* Bit 5: AIF3 Audio Interface tri-state */
+#define WM8994_AIF3_TRI_NO (0) /* AIF3 pins operate normally */
+#define WM8994_AIF3_TRI_YES (WM8994_AIF3_TRI) /* Tri-State all AIF3 interface pins */
/* R21 (0x15) - Input Mixer (1)
*/
/* Bits 0-5: Reserved */
-#define WM8994_INPUTS_CLAMP (1 << 6) /* Bit 6: Input pad VMID clamp */
-#define WM8994_INPUTS_CLAMP_DE_ACTIVATED (0) /* Clamp de-activated */
-#define WM8994_INPUTS_CLAMP_ACTIVATED (WM8994_INPUTS_CLAMP) /* Clamp activated */
-#define WM8994_IN1LP_MIXINL_BOOST (1 << 7) /* Bit 7: IN1LP Pin (PGA Bypass) to MIXINL Gain Boost. The bit seletcs the maximum gain setting of the IN1LP_MIXINL_VOL register. */
-#define WM8994_IN1LP_MIXINL_BOOST_P_6dB (0) /* Maximum gain is +6dB */
-#define WM8994_IN1LP_MIXINL_BOOST_P_15dB (WM8994_IN1LP_MIXINL_BOOST) /* Maximu gain is +15dB */
-#define WM8994_IN1RP_MIXINR_BOOST (1 << 8) /* Bit 8: IN1RP Pin (PGA Bypass) to MIXINR Gain Boost. The bit seletcs the maximum gain setting of the IN1RP_MIXINR_VOL register. */
-#define WM8994_IN1RP_MIXINR_BOOST_P_6dB (0) /* Maximum gain is +6dB */
-#define WM8994_IN1RP_MIXINR_BOOST_P_15dB (WM8994_IN1RP_MIXINR_BOOST) /* Maximu gain is +15dB */
+#define WM8994_INPUTS_CLAMP (1 << 6) /* Bit 6: Input pad VMID clamp */
+#define WM8994_INPUTS_CLAMP_DE_ACTIVATED (0) /* Clamp de-activated */
+#define WM8994_INPUTS_CLAMP_ACTIVATED (WM8994_INPUTS_CLAMP) /* Clamp activated */
+#define WM8994_IN1LP_MIXINL_BOOST (1 << 7) /* Bit 7: IN1LP Pin (PGA Bypass) to MIXINL Gain Boost. The bit seletcs the maximum gain setting of the IN1LP_MIXINL_VOL register. */
+#define WM8994_IN1LP_MIXINL_BOOST_P_6dB (0) /* Maximum gain is +6dB */
+#define WM8994_IN1LP_MIXINL_BOOST_P_15dB (WM8994_IN1LP_MIXINL_BOOST) /* Maximu gain is +15dB */
+#define WM8994_IN1RP_MIXINR_BOOST (1 << 8) /* Bit 8: IN1RP Pin (PGA Bypass) to MIXINR Gain Boost. The bit seletcs the maximum gain setting of the IN1RP_MIXINR_VOL register. */
+#define WM8994_IN1RP_MIXINR_BOOST_P_6dB (0) /* Maximum gain is +6dB */
+#define WM8994_IN1RP_MIXINR_BOOST_P_15dB (WM8994_IN1RP_MIXINR_BOOST) /* Maximu gain is +15dB */
/* Bits 9-15: Reserved */
/* R24 (0x18) - Left Line Input 1&2 Volume
*/
-#define WM8994_IN1L_VOL (0) /* Bits 0-4: IN1L Volume */
-#define WM8994_IN1L_VOL_MIN (0 << 0) /* -16.5dB */
-#define WM8994_IN1L_VOL_DEFAULT (11 << 0) /* -16.5dB to +30dB in 1.5dB steps */
-#define WM8994_IN1L_VOL_MAX (31 << 0) /* +30dB */
+#define WM8994_IN1L_VOL (0) /* Bits 0-4: IN1L Volume */
+#define WM8994_IN1L_VOL_MIN (0 << 0) /* -16.5dB */
+#define WM8994_IN1L_VOL_DEFAULT (11 << 0) /* -16.5dB to +30dB in 1.5dB steps */
+#define WM8994_IN1L_VOL_MAX (31 << 0) /* +30dB */
/* Bit 5: Reserved */
-#define WM8994_IN1L_ZC (1 << 6) /* Bit 6: IN1L PGA Zero Cross Detector */
-#define WM8994_IN1L_ZC_NO (0) /* Change gain immediately */
-#define WM8994_IN1L_ZC_YES (WM8994_IN1L_ZC) /* Change gain on zero cross only */
-#define WM8994_IN1L_MUTE (1 << 7) /* Bit 7: IN1L PGA Mute */
-#define WM8994_IN1L_MUTE_DISABLE (0) /* Disabled */
-#define WM8994_IN1L_MUTE_ENABLE (WM8994_IN1L_MUTE) /* Enabled */
-#define WM8994_IN1_VU (1 << 8) /* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause IN1L and IN1R input PGA volumes to updated simultaneously */
+#define WM8994_IN1L_ZC (1 << 6) /* Bit 6: IN1L PGA Zero Cross Detector */
+#define WM8994_IN1L_ZC_NO (0) /* Change gain immediately */
+#define WM8994_IN1L_ZC_YES (WM8994_IN1L_ZC) /* Change gain on zero cross only */
+#define WM8994_IN1L_MUTE (1 << 7) /* Bit 7: IN1L PGA Mute */
+#define WM8994_IN1L_MUTE_DISABLE (0) /* Disabled */
+#define WM8994_IN1L_MUTE_ENABLE (WM8994_IN1L_MUTE) /* Enabled */
+#define WM8994_IN1_VU (1 << 8) /* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause IN1L and IN1R input PGA volumes to updated simultaneously */
- /* Bits 9-15: Reserved */
+ /* Bits 9-15: Reserved */
/* R25 (0x19) - Left Line Input 3&4 Volume
*/
-#define WM8994_IN2L_VOL_SHIFT (0) /* Bits 0-4: IN2L Volume */
-#define WM8994_IN2L_VOL_MIN (0 << WM8994_IN2L_VOL_SHIFT) /* -16.5dB */
-#define WM8994_IN2L_VOL_DEFAULT (11 << WM8994_IN2L_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */
-#define WM8994_IN2L_VOL_MAX (31 << WM8994_IN2L_VOL_SHIFT) /* +30dB */
+#define WM8994_IN2L_VOL_SHIFT (0) /* Bits 0-4: IN2L Volume */
+#define WM8994_IN2L_VOL_MIN (0 << WM8994_IN2L_VOL_SHIFT) /* -16.5dB */
+#define WM8994_IN2L_VOL_DEFAULT (11 << WM8994_IN2L_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */
+#define WM8994_IN2L_VOL_MAX (31 << WM8994_IN2L_VOL_SHIFT) /* +30dB */
/* Bit 5: Reserved */
-#define WM8994_IN2L_ZC (1 << 6) /* Bit 6: IN2L PGA Zero Cross Detector */
-#define WM8994_IN2L_ZC_NO (0) /* Change gain immediately */
-#define WM8994_IN2L_ZC_YES (WM8994_IN2L_ZC) /* Change gain on zero cross only */
-#define WM8994_IN2L_MUTE (1 << 7) /* Bit 7: IN2L PGA Mute */
-#define WM8994_IN2L_MUTE_DISABLE (0) /* Disabled */
-#define WM8994_IN2L_MUTE_ENABLE (WM8994_IN2L_MUTE) /* Enabled */
-#define WM8994_IN2_VU (1 << 8) /* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause IN2L and IN2R input PGA volumes to updated simultaneously */
+#define WM8994_IN2L_ZC (1 << 6) /* Bit 6: IN2L PGA Zero Cross Detector */
+#define WM8994_IN2L_ZC_NO (0) /* Change gain immediately */
+#define WM8994_IN2L_ZC_YES (WM8994_IN2L_ZC) /* Change gain on zero cross only */
+#define WM8994_IN2L_MUTE (1 << 7) /* Bit 7: IN2L PGA Mute */
+#define WM8994_IN2L_MUTE_DISABLE (0) /* Disabled */
+#define WM8994_IN2L_MUTE_ENABLE (WM8994_IN2L_MUTE) /* Enabled */
+#define WM8994_IN2_VU (1 << 8) /* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause IN2L and IN2R input PGA volumes to updated simultaneously */
- /* Bits 9-15: Reserved */
+ /* Bits 9-15: Reserved */
/* R26 (0x1A) - Right Line Input 1&2 Volume
*/
-#define WM8994_IN1R_VOL_SHIFT (0) /* Bits 0-4: IN1R Volume */
-#define WM8994_IN1R_VOL_MIN (0 << WM8994_IN1R_VOL_SHIFT) /* -16.5dB */
-#define WM8994_IN1R_VOL_DEFAULT (11 << WM8994_IN1R_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */
-#define WM8994_IN1R_VOL_MAX (31 << WM8994_IN1R_VOL_SHIFT) /* +30dB */
+#define WM8994_IN1R_VOL_SHIFT (0) /* Bits 0-4: IN1R Volume */
+#define WM8994_IN1R_VOL_MIN (0 << WM8994_IN1R_VOL_SHIFT) /* -16.5dB */
+#define WM8994_IN1R_VOL_DEFAULT (11 << WM8994_IN1R_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */
+#define WM8994_IN1R_VOL_MAX (31 << WM8994_IN1R_VOL_SHIFT) /* +30dB */
/* Bit 5: Reserved */
-#define WM8994_IN1R_ZC_SHIFT (6) /* Bit 6: IN1R PGA Zero Cross Detector */
-#define WM8994_IN1R_ZC_NO (0) /* Change gain immediately */
-#define WM8994_IN1R_ZC_YES (1 << WM8994_IN1R_ZC_SHIFT) /* Change gain on zero cross only */
-#define WM8994_IN1R_MUTE_SHIFT (7) /* Bit 7: IN1R PGA Mute */
-#define WM8994_IN1R_MUTE_DISABLE (0) /* Disabled */
-#define WM8994_IN1R_MUTE_ENABLE (WM8994_IN1R_MUTE_SHIFT) /* Enabled */
+#define WM8994_IN1R_ZC_SHIFT (6) /* Bit 6: IN1R PGA Zero Cross Detector */
+#define WM8994_IN1R_ZC_NO (0) /* Change gain immediately */
+#define WM8994_IN1R_ZC_YES (1 << WM8994_IN1R_ZC_SHIFT) /* Change gain on zero cross only */
+#define WM8994_IN1R_MUTE_SHIFT (7) /* Bit 7: IN1R PGA Mute */
+#define WM8994_IN1R_MUTE_DISABLE (0) /* Disabled */
+#define WM8994_IN1R_MUTE_ENABLE (WM8994_IN1R_MUTE_SHIFT) /* Enabled */
#if 0
-#define WM8994_IN1_VU (1 << 8) /* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause IN1L and IN1R input PGA volumes to updated simultaneously */
+#define WM8994_IN1_VU (1 << 8) /* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause IN1L and IN1R input PGA volumes to updated simultaneously */
#endif
- /* Bits 9-15: Reserved */
+ /* Bits 9-15: Reserved */
/* R27 (0x1B) - Right Line Input 3&4 Volume
*/
-#define WM8994_IN2R_VOL_SHIFT (0) /* Bits 0-4: IN2R Volume */
-#define WM8994_IN2R_VOL_MIN (0 << WM8994_IN2R_VOL_SHIFT) /* -16.5dB */
-#define WM8994_IN2R_VOL_DEFAULT (11 << WM8994_IN2R_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */
-#define WM8994_IN2R_VOL_MAX (31 << WM8994_IN2R_VOL_SHIFT) /* +30dB */
+#define WM8994_IN2R_VOL_SHIFT (0) /* Bits 0-4: IN2R Volume */
+#define WM8994_IN2R_VOL_MIN (0 << WM8994_IN2R_VOL_SHIFT) /* -16.5dB */
+#define WM8994_IN2R_VOL_DEFAULT (11 << WM8994_IN2R_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */
+#define WM8994_IN2R_VOL_MAX (31 << WM8994_IN2R_VOL_SHIFT) /* +30dB */
/* Bit 5: Reserved */
-#define WM8994_IN2R_ZC_SHIFT (6) /* Bit 6: IN2R PGA Zero Cross Detector */
-#define WM8994_IN2R_ZC_NO (0) /* Change gain immediately */
-#define WM8994_IN2R_ZC_YES (1 << WM8994_IN2R_ZC_SHIFT) /* Change gain on zero cross only */
-#define WM8994_IN2R_MUTE_SHIFT (7) /* Bit 7: IN2R PGA Mute */
-#define WM8994_IN2R_MUTE_DISABLE (0) /* Disabled */
-#define WM8994_IN2R_MUTE_ENABLED (1 << WM8994_IN2R_MUTE_SHIFT) /* Enabled */
+#define WM8994_IN2R_ZC_SHIFT (6) /* Bit 6: IN2R PGA Zero Cross Detector */
+#define WM8994_IN2R_ZC_NO (0) /* Change gain immediately */
+#define WM8994_IN2R_ZC_YES (1 << WM8994_IN2R_ZC_SHIFT) /* Change gain on zero cross only */
+#define WM8994_IN2R_MUTE_SHIFT (7) /* Bit 7: IN2R PGA Mute */
+#define WM8994_IN2R_MUTE_DISABLE (0) /* Disabled */
+#define WM8994_IN2R_MUTE_ENABLED (1 << WM8994_IN2R_MUTE_SHIFT) /* Enabled */
#if 0
-#define WM8994_IN2_VU (1 << 8) /* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause IN2L and IN2R input PGA volumes to updated simultaneously */
+#define WM8994_IN2_VU (1 << 8) /* Bit 8: Input PGA Voluem Update. Writing a 1 to this bit cause IN2L and IN2R input PGA volumes to updated simultaneously */
#endif
/* R28 (0x1C) - Left Output Volume
*/
-#define WM8994_HPOUT1L_VOL_SHIFT (0) /* Bits 0-5: HPOUT1LVOL (Left Headphone Output PGA) Volume */
-#define WM8994_HPOUT1L_VOL_MIN (0 << WM8994_HPOUT1L_VOL_SHIFT) /* -57dB */
-#define WM8994_HPOUT1L_VOL_DEFAULT (0 << WM8994_HPOUT1L_VOL_SHIFT) /* -57dB to +6dB in 1 dB steps*/
-#define WM8994_HPOUT1L_VOL_MAX (0x3F << WM8994_HPOUT1L_VOL_SHIFT) /* +6dB */
-#define WM8994_HPOUT1L_MUTE_N_SHIFT (6) /* Bit 6: HPOUT1LVOL (Left Headphone Output PGA) Mute */
-#define WM8994_HPOUT1L_MUTE_N_YES (0) /* Mute */
-#define WM8994_HPOUT1L_MUTE_N_NO (1 << WM8994_HPOUT1L_MUTE_N_SHIFT) /* Un-Mute */
-#define WM8994_HPOUT1L_ZC_SHIFT (7) /* Bit 7: HPOUT1LVOL (Left Headphone Output PGA) Zero Cross */
-#define WM8994_HPOUT1L_ZC_DIABLED (0) /* Zero cross disabled */
-#define WM8994_HPOUT1L_ZC_ENABLED (WM8994_HPOUT1L_ZC_SHIFT) /* Zero cross enabled */
-#define WM8994_HPOUT1_VU_SHIFT (8) /* Bit 8: Headphone Output PGA Volume Update */
-#define WM8994_HPOUT1_VU_DISABLE (0)
-#define WM8994_HPOUT1_VU_ENABLED (WM8994_HPOUT1L_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and
+#define WM8994_HPOUT1L_VOL_SHIFT (0) /* Bits 0-5: HPOUT1LVOL (Left Headphone Output PGA) Volume */
+#define WM8994_HPOUT1L_VOL_MIN (0 << WM8994_HPOUT1L_VOL_SHIFT) /* -57dB */
+#define WM8994_HPOUT1L_VOL_DEFAULT (0 << WM8994_HPOUT1L_VOL_SHIFT) /* -57dB to +6dB in 1 dB steps*/
+#define WM8994_HPOUT1L_VOL_MAX (0x3F << WM8994_HPOUT1L_VOL_SHIFT) /* +6dB */
+# define WM8994_HPOUT1L_VOL(n) ((uint16_t)(n) << WM8994_HPOUT1L_VOL_SHIFT) /* Set volume to defined value */
+#define WM8994_HPOUT1L_MUTE_N_SHIFT (6) /* Bit 6: HPOUT1LVOL (Left Headphone Output PGA) Mute */
+#define WM8994_HPOUT1L_MUTE_N_YES (0) /* Mute */
+#define WM8994_HPOUT1L_MUTE_N_NO (1 << WM8994_HPOUT1L_MUTE_N_SHIFT) /* Un-Mute */
+#define WM8994_HPOUT1L_ZC_SHIFT (7) /* Bit 7: HPOUT1LVOL (Left Headphone Output PGA) Zero Cross */
+#define WM8994_HPOUT1L_ZC_DIABLED (0) /* Zero cross disabled */
+#define WM8994_HPOUT1L_ZC_ENABLED (1 << WM8994_HPOUT1L_ZC_SHIFT) /* Zero cross enabled */
+#define WM8994_HPOUT1_VU_SHIFT (8) /* Bit 8: Headphone Output PGA Volume Update */
+#define WM8994_HPOUT1_VU_DISABLE (0)
+#define WM8994_HPOUT1_VU_ENABLED (1 << WM8994_HPOUT1_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and
* HPOUT1RVOL volumes simultaneously */
/* R29 (0x1D) - Right Output Volume
*/
-#define WM8994_HPOUT1R_VOL_SHIFT (0) /* Bits 0-5: HPOUT1RVOL (Right Headphone Output PGA) Volume */
-#define WM8994_HPOUT1R_VOL_MIN (0 << WM8994_HPOUT1R_VOL_SHIFT) /* -57dB */
-#define WM8994_HPOUT1R_VOL_DEFAULT (0 << WM8994_HPOUT1R_VOL_SHIFT) /* -57dB to +6dB in 1 dB steps*/
-#define WM8994_HPOUT1R_VOL_MAX (0x3F << WM8994_HPOUT1R_VOL_SHIFT) /* +6dB */
-#define WM8994_HPOUT1R_MUTE_N_SHIFT (6) /* Bit 6: HPOUT1RVOL (Left Headphone Output PGA) Mute */
-#define WM8994_HPOUT1R_MUTE_N_YES (0) /* Mute */
-#define WM8994_HPOUT1R_MUTE_N_NO (1 << WM8994_HPOUT1R_MUTE_N_SHIFT) /* Un-Mute */
-#define WM8994_HPOUT1R_ZC_SHIFT (7) /* Bit 7: HPOUT1RVOL (Left Headphone Output PGA) Zero Cross */
-#define WM8994_HPOUT1R_ZC_DIABLED (0) /* Zero cross disabled */
-#define WM8994_HPOUT1R_ZC_ENABLED (WM8994_HPOUT1R_ZC_SHIFT) /* Zero cross enabled */
+#define WM8994_HPOUT1R_VOL_SHIFT (0) /* Bits 0-5: HPOUT1RVOL (Right Headphone Output PGA) Volume */
+#define WM8994_HPOUT1R_VOL_MIN (0 << WM8994_HPOUT1R_VOL_SHIFT) /* -57dB */
+#define WM8994_HPOUT1R_VOL_DEFAULT (0 << WM8994_HPOUT1R_VOL_SHIFT) /* -57dB to +6dB in 1 dB steps*/
+#define WM8994_HPOUT1R_VOL_MAX (0x3F << WM8994_HPOUT1R_VOL_SHIFT) /* +6dB */
+# define WM8994_HPOUT1R_VOL(n) ((uint16_t)(n) << WM8994_HPOUT1R_VOL_SHIFT) /* Set volume to defined value */
+#define WM8994_HPOUT1R_MUTE_N_SHIFT (6) /* Bit 6: HPOUT1RVOL (Left Headphone Output PGA) Mute */
+#define WM8994_HPOUT1R_MUTE_N_YES (0) /* Mute */
+#define WM8994_HPOUT1R_MUTE_N_NO (1 << WM8994_HPOUT1R_MUTE_N_SHIFT) /* Un-Mute */
+#define WM8994_HPOUT1R_ZC_SHIFT (7) /* Bit 7: HPOUT1RVOL (Left Headphone Output PGA) Zero Cross */
+#define WM8994_HPOUT1R_ZC_DIABLED (0) /* Zero cross disabled */
+#define WM8994_HPOUT1R_ZC_ENABLED (1 << WM8994_HPOUT1R_ZC_SHIFT) /* Zero cross enabled */
#if 0
-#define WM8994_HPOUT1_VU_SHIFT (1 << 8) /* Bit 8: Headphone Output PGA Volume Update */
-#define WM8994_HPOUT1_VU_DISABLE (0)
-#define WM8994_HPOUT1_VU_ENABLED (WM8994_HPOUT1L_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and
+#define WM8994_HPOUT1_VU_SHIFT (1 << 8) /* Bit 8: Headphone Output PGA Volume Update */
+#define WM8994_HPOUT1_VU_DISABLE (0)
+#define WM8994_HPOUT1_VU_ENABLED (1 << WM8994_HPOUT1L_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and
* HPOUT1RVOL volumes simultaneously */
#endif
/* R30 (0x1E) - Line Outputs Volume
*/
-#define WM8994_LINEOUT2_VOL_SHIFT (0) /* LINEOUT2 Line Output Volume */
-#define WM8994_LINEOUT2_VOL_0dB (0) /* 0dB */
-#define WM8994_LINEOUT2_VOL_n6dB (1 << WM8994_LINEOUT2_VOL_SHIFT) /* -6dB */
-#define WM8994_LINEOUT2P_MUTE (1) /* LINEOUT2P Line Output Mute */
+#define WM8994_LINEOUT2_VOL_SHIFT (0) /* LINEOUT2 Line Output Volume */
+#define WM8994_LINEOUT2_VOL_0dB (0) /* 0dB */
+#define WM8994_LINEOUT2_VOL_n6dB (1 << WM8994_LINEOUT2_VOL_SHIFT) /* -6dB */
+#define WM8994_LINEOUT2P_MUTE (1) /* LINEOUT2P Line Output Mute */
/* R31 (0x1F) - HPOUT2 Volume
*/
@@ -720,38 +722,66 @@
/* R45 (0x2D) - Output Mixer (1)
*/
-#define WM8994_DAC1L_TO_MIXOUTL (1 << 0) /* Bit 0: Left DAC1 to MIXOUTL Mute */
-#define WM8994_DAC1L_TO_MIXOUTL_MUTE (0) /* Mute */
-#define WM8994_DAC1L_TO_MIXOUTL_UNMUTE (WM8994_DAC1L_TO_MIXOUTL) /* Un-mute */
-#define WM8994_IN2LP_TO_MIXOUTL (1 << 1) /* Bit 1: IN2LP to MIXOUTL Mute */
-#define WM8994_IN2LP_TO_MIXOUTL_MUTE (0) /* Mute */
-#define WM8994_IN2LP_TO_MIXOUTL_UNMUTE (WM8994_IN2LP_TO_MIXOUTL) /* Un-mute */
-#define WM8994_IN1L_TO_MIXOUTL (1 << 2) /* Bit 2: IN1L PGA Output to MIXOUTL Mute */
-#define WM8994_IN1L_TO_MIXOUTL_MUTE (0) /* Mute */
-#define WM8994_IN1L_TO_MIXOUTL_UNMUTE (WM8994_IN1L_TO_MIXOUTL_MUTE) /* Un-mute */
-#define WM8994_IN1R_TO_MIXOUTL (1 << 3) /* Bit 3: IN1R PGA Output to MIXOUTL Mute */
-#define WM8994_IN1R_TO_MIXOUTL_MUTE (0) /* Mute */
-#define WM8994_IN1R_TO_MIXOUTL_UNMUTE (WM8994_IN1R_TO_MIXOUTL_MUTE) /* Un-mute */
-#define WM8994_IN2LN_TO_MIXOUTL (1 << 4) /* Bit 4: IN2LN to MIXOUTL Mute */
-#define WM8994_IN2LN_TO_MIXOUTL_MUTE (0) /* Mute */
-#define WM8994_IN2LN_TO_MIXOUTL_UNMUTE (WM8994_IN2LN_TO_MIXOUTL) /* Un-mute */
-#define WM8994_IN2RN_TO_MIXOUTL (1 << 5) /* Bit 5: IN2RN to MIXOUTL Mute */
-#define WM8994_IN2RN_TO_MIXOUTL_MUTE (0) /* Mute */
-#define WM8994_IN2RN_TO_MIXOUTL_UNMUTE (WM8994_IN2RN_TO_MIXOUTL) /* Un-mute */
-#define WM8994_MIXINL_TO_MIXOUTL (1 << 6) /* Bit 6: MIXINL Output(Left ADC bypass) to MIXOUTL Mute */
-#define WM8994_MIXINL_TO_MIXOUTL_MUTE (0) /* mute */
-#define WM8994_MIXINL_TO_MIXOUTL_UNMUTE (WM8994_MIXINL_TO_MIXOUTL) /* Un-mute */
-#define WM8994_MIXINR_TO_MIXOUTL (1 << 7) /* Bit 7: MIXINR Output(Left ADC bypass) to MIXOUTL Mute */
-#define WM8994_MIXINR_TO_MIXOUTL_MUTE (0) /* mute */
-#define WM8994_MIXINR_TO_MIXOUTL_UNMUTE (WM8994_MIXINR_TO_MIXOUTL) /* Un-mute */
-#define WM8994_DAC1L_TO_HPOUT1L (1 << 8) /* Bit 8: HPOUT1LVOL(Left Headphone Output PGA) Input Select */
-#define WM8994_DAC1L_TO_HPOUT1L_MIXOUTL (0) /* MIXOUTL */
-#define WM8994_DAC1L_TO_HPOUT1L_DAC1L (WM8994_DAC1L_TO_HPOUT1L) /* DAC1L */
+#define WM8994_DAC1L_TO_MIXOUTL (1 << 0) /* Bit 0: Left DAC1 to MIXOUTL Mute */
+#define WM8994_DAC1L_TO_MIXOUTL_MUTE (0) /* Mute */
+#define WM8994_DAC1L_TO_MIXOUTL_UNMUTE (WM8994_DAC1L_TO_MIXOUTL) /* Un-mute */
+#define WM8994_IN2LP_TO_MIXOUTL (1 << 1) /* Bit 1: IN2LP to MIXOUTL Mute */
+#define WM8994_IN2LP_TO_MIXOUTL_MUTE (0) /* Mute */
+#define WM8994_IN2LP_TO_MIXOUTL_UNMUTE (WM8994_IN2LP_TO_MIXOUTL) /* Un-mute */
+#define WM8994_IN1L_TO_MIXOUTL (1 << 2) /* Bit 2: IN1L PGA Output to MIXOUTL Mute */
+#define WM8994_IN1L_TO_MIXOUTL_MUTE (0) /* Mute */
+#define WM8994_IN1L_TO_MIXOUTL_UNMUTE (WM8994_IN1L_TO_MIXOUTL_MUTE) /* Un-mute */
+#define WM8994_IN1R_TO_MIXOUTL (1 << 3) /* Bit 3: IN1R PGA Output to MIXOUTL Mute */
+#define WM8994_IN1R_TO_MIXOUTL_MUTE (0) /* Mute */
+#define WM8994_IN1R_TO_MIXOUTL_UNMUTE (WM8994_IN1R_TO_MIXOUTL_MUTE) /* Un-mute */
+#define WM8994_IN2LN_TO_MIXOUTL (1 << 4) /* Bit 4: IN2LN to MIXOUTL Mute */
+#define WM8994_IN2LN_TO_MIXOUTL_MUTE (0) /* Mute */
+#define WM8994_IN2LN_TO_MIXOUTL_UNMUTE (WM8994_IN2LN_TO_MIXOUTL) /* Un-mute */
+#define WM8994_IN2RN_TO_MIXOUTL (1 << 5) /* Bit 5: IN2RN to MIXOUTL Mute */
+#define WM8994_IN2RN_TO_MIXOUTL_MUTE (0) /* Mute */
+#define WM8994_IN2RN_TO_MIXOUTL_UNMUTE (WM8994_IN2RN_TO_MIXOUTL) /* Un-mute */
+#define WM8994_MIXINL_TO_MIXOUTL (1 << 6) /* Bit 6: MIXINL Output(Left ADC bypass) to MIXOUTL Mute */
+#define WM8994_MIXINL_TO_MIXOUTL_MUTE (0) /* mute */
+#define WM8994_MIXINL_TO_MIXOUTL_UNMUTE (WM8994_MIXINL_TO_MIXOUTL) /* Un-mute */
+#define WM8994_MIXINR_TO_MIXOUTL (1 << 7) /* Bit 7: MIXINR Output(Left ADC bypass) to MIXOUTL Mute */
+#define WM8994_MIXINR_TO_MIXOUTL_MUTE (0) /* mute */
+#define WM8994_MIXINR_TO_MIXOUTL_UNMUTE (WM8994_MIXINR_TO_MIXOUTL) /* Un-mute */
+#define WM8994_DAC1L_TO_HPOUT1L (1 << 8) /* Bit 8: HPOUT1LVOL(Left Headphone Output PGA) Input Select */
+#define WM8994_DAC1L_TO_HPOUT1L_MIXOUTL (0) /* MIXOUTL */
+#define WM8994_DAC1L_TO_HPOUT1L_DAC1L (WM8994_DAC1L_TO_HPOUT1L) /* DAC1L */
/* Bits 9-15: Reserved */
/* R46 (0x2E) - Output Mixer (2)
*/
+#define WM8994_DAC1R_TO_MIXOUTR (1 << 0) /* Bit 0: Right DAC1 to MIXOUTR Mute */
+#define WM8994_DAC1R_TO_MIXOUTR_MUTE (0) /* Mute */
+#define WM8994_DAC1R_TO_MIXOUTR_UNMUTE (WM8994_DAC1R_TO_MIXOUTR) /* Un-mute */
+#define WM8994_IN2RP_TO_MIXOUTR (1 << 1) /* Bit 1: IN2RP to MIXOUTR Mute */
+#define WM8994_IN2RP_TO_MIXOUTR_MUTE (0) /* Mute */
+#define WM8994_IN2RP_TO_MIXOUTR_UNMUTE (WM8994_IN2RP_TO_MIXOUTR) /* Un-mute */
+#define WM8994_IN1R_TO_MIXOUTR (1 << 2) /* Bit 2: IN1R PGA Output to MIXOUTR Mute */
+#define WM8994_IN1R_TO_MIXOUTR_MUTE (0) /* Mute */
+#define WM8994_IN1R_TO_MIXOUTR_UNMUTE (WM8994_IN1R_TO_MIXOUTR_MUTE) /* Un-mute */
+#define WM8994_IN1L_TO_MIXOUTR (1 << 3) /* Bit 3: IN1L PGA Output to MIXOUTR Mute */
+#define WM8994_IN1L_TO_MIXOUTR_MUTE (0) /* Mute */
+#define WM8994_IN1L_TO_MIXOUTR_UNMUTE (WM8994_IN1L_TO_MIXOUTR_MUTE) /* Un-mute */
+#define WM8994_IN2RN_TO_MIXOUTR (1 << 4) /* Bit 4: IN2RN to MIXOUTR Mute */
+#define WM8994_IN2RN_TO_MIXOUTR_MUTE (0) /* Mute */
+#define WM8994_IN2RN_TO_MIXOUTR_UNMUTE (WM8994_IN2RN_TO_MIXOUTR) /* Un-mute */
+#define WM8994_IN2LN_TO_MIXOUTR (1 << 5) /* Bit 5: IN2LN to MIXOUTR Mute */
+#define WM8994_IN2LN_TO_MIXOUTR_MUTE (0) /* Mute */
+#define WM8994_IN2LN_TO_MIXOUTR_UNMUTE (WM8994_IN2LN_TO_MIXOUTR) /* Un-mute */
+#define WM8994_MIXINR_TO_MIXOUTR (1 << 6) /* Bit 6: MIXINR Output(Left ADC bypass) to MIXOUTR Mute */
+#define WM8994_MIXINR_TO_MIXOUTR_MUTE (0) /* mute */
+#define WM8994_MIXINR_TO_MIXOUTR_UNMUTE (WM8994_MIXINR_TO_MIXOUTR) /* Un-mute */
+#define WM8994_MIXINL_TO_MIXOUTR (1 << 7) /* Bit 7: MIXINL Output(Left ADC bypass) to MIXOUTR Mute */
+#define WM8994_MIXINL_TO_MIXOUTR_MUTE (0) /* mute */
+#define WM8994_MIXINL_TO_MIXOUTR_UNMUTE (WM8994_MIXINL_TO_MIXOUTR) /* Un-mute */
+#define WM8994_DAC1R_TO_HPOUT1R (1 << 8) /* Bit 8: HPOUT1RVOL(Left Headphone Output PGA) Input Select */
+#define WM8994_DAC1R_TO_HPOUT1R_MIXOUTL (0) /* MIXOUTR */
+#define WM8994_DAC1R_TO_HPOUT1R_DAC1L (WM8994_DAC1R_TO_HPOUT1R) /* DAC1R */
+
/* R47 (0x2F) - Output Mixer (3)
*/
@@ -775,6 +805,36 @@
/* R54 (0x36) - Speaker Mixer
*/
+#define WM8994_DAC2L_TO_SPKMIXL (1 << 9) /* Bit 9: Left DAC2 to SPKMXL Mute */
+#define WM8994_DAC2L_TO_SPKMIXL_MUTE (0) /* Mute */
+#define WM8994_DAC2L_TO_SPKMIXL_UNMUTE (WM8994_DAC2L_TO_SPKMIXL) /* Un-mute */
+#define WM8994_DAC2R_TO_SPKMIXR (1 << 8) /* Bit 8: Right DAC2 to SPKMXL Mute */
+#define WM8994_DAC2R_TO_SPKMIXL_MUTE (0) /* Mute */
+#define WM8994_DAC2R_TO_SPKMIXL_UNMUTE (WM8994_DAC2R_TO_SPKMIXL) /* Un-mute */
+#define WM8994_MIXINL_TO_SPKMIXL (1 << 7) /* Bit 7: MIXINL (Left ADC bypass) to SPKMIXL Mute */
+#define WM8994_MIXINL_TO_SPKMIXL_MUTE (0) /* Mute */
+#define WM8994_MIXINL_TO_SPKMIXL_UNMUTE (WM8994_MIXINL_TO_SPKMIXL) /* Un-mute */
+#define WM8994_MIXINR_TO_SPKMIXR (1 << 6) /* Bit 6: MIXINR (Right ADC bypass) to SPKMIXR Mute */
+#define WM8994_MIXINR_TO_SPKMIXR_MUTE (0) /* Mute */
+#define WM8994_MIXINR_TO_SPKMIXR_UNMUTE (WM8994_MIXINR_TO_SPKMIXR) /* Un-mute */
+#define WM8994_IN1LP_TO_SPKMIXL (1 << 5) /* Bit 5: IN1LP to SPKMIXL Mute */
+#define WM8994_IN1LP_TO_SPKMIXL_MUTE (0) /* Mute */
+#define WM8994_IN1LP_TO_SPKMIXL_UNMUTE (WM8994_IN1LP_TO_SPKMIXL) /* Un-mute */
+#define WM8994_IN1RP_TO_SPKMIXR (1 << 4) /* Bit 4: IN1RP to SPKMIXR Mute */
+#define WM8994_IN1RP_TO_SPKMIXR_MUTE (0) /* Mute */
+#define WM8994_IN1RP_TO_SPKMIXR_UNMUTE (WM8994_IN1RP_TO_SPKMIXR) /* Un-mute */
+#define WM8994_MIXOUTL_TO_SPKMIXL (1 << 3) /* Bit 3: MIXOUTL to SPKMIXL Mute */
+#define WM8994_MIXOUTL_TO_SPKMIXL_MUTE (0) /* Mute */
+#define WM8994_MIXOUTL_TO_SPKMIXL_UNMUTE (WM8994_MIXOUTL_TO_SPKMIXL) /* Un-mute */
+#define WM8994_MIXOUTR_TO_SPKMIXR (1 << 2) /* Bit 2: MIXOUTR to SPKMIXR Mute */
+#define WM8994_MIXOUTR_TO_SPKMIXR_MUTE (0) /* Mute */
+#define WM8994_MIXOUTR_TO_SPKMIXR_UNMUTE (WM8994_MIXOUTR_TO_SPKMIXR) /* Un-mute */
+#define WM8994_DAC1L_TO_SPKMIXL (1 << 1) /* Bit 1: DAC1L to SPKMIXL Mute */
+#define WM8994_DAC1L_TO_SPKMIXL_MUTE (0) /* Mute */
+#define WM8994_DAC1L_TO_SPKMIXL_UNMUTE (WM8994_DAC1L_TO_SPKMIXL) /* Un-mute */
+#define WM8994_DAC1R_TO_SPKMIXR (1 << 0) /* Bit 0: DAC1R to SPKMIXR Mute */
+#define WM8994_DAC1R_TO_SPKMIXR_MUTE (0) /* Mute */
+#define WM8994_DAC1R_TO_SPKMIXR_UNMUTE (WM8994_DAC1R_TO_SPKMIXR) /* Un-mute */
/* R55 (0x37) - Additional Control
*/
@@ -785,28 +845,28 @@
/* R57 (0x39) - AntiPOP (2)
*/
- /* Bits 8-15: Reserved */
-#define WM8994_MICB2_DISCH (1 << 8) /* Bit 7: Microphone Bias 2 Discharge */
-#define WM8994_MICB2_DISCH_FLOAT (0) /* MICBIAS2 floating when disabled */
-#define WM8994_MICB2_DISCH_DISCHARGED WM8994_MICB2_DISCH /* MICBIAS2 disharged when disabled */
-#define WM8994_MICB1_DISCH (1 << 7) /* Bit 7: Microphone Bias 1 Discharge */
-#define WM8994_MICB1_DISCH_FLOAT (0) /* MICBIAS1 floating when disabled */
-#define WM8994_MICB1_DISCH_DISCHARGED WM8994_MICB1_DISCH /* MICBIAS1 disharged when disabled */
-
-#define WM8994_VMID_DISCH (1 << 0) /* Bit 0:Connects VMID to ground */
-#define WM8994_VMID_DISCH_DISABLE (0) /* Disabled */
-#define WM8994_VMID_DISCH_ENABLE WM8994_VMID_DISCH /* Enabled */
-#define WM8994_BIAS_SRC (1 << 1) /* Bit 1: Selects the bias current source */
-# define WM8994_BIAS_SRC_NORMAL_BIAS (0) /* Normal bias */
-# define WM8994_BIAS_SRC_STARTUP_BIAS WM8994_BIAS_SRC /* Start-Up bias */
-#define WM8994_STARTUP_BIAS_ENA (1 << 2) /* Bit 2: Enables the Start-Up bias current generator */
-#define WM8994_VMID_BUF_ENA (1 << 3) /* Bit 3: VMID Buffer Enable */
-#define WM8994_VMID_RAMP_SHIFT (5) /* Bits 5-6: VMID soft start enable/slew rate control */
-#define WM8994_VMID_RAMP_MASK (3 << WM8994_VMID_RAMP_SHIFT)
-#define WM8994_VMID_RAMP_NORMAL_SLOW_START (0 << WM8994_VMID_RAMP_SHIFT) /* Normal slow start */
-#define WM8994_VMID_RAMP_NORMAL_FAST_START (1 << WM8994_VMID_RAMP_SHIFT) /* Normal fast start */
-#define WM8994_VMID_RAMP_SOFT_SLOW_START (2 << WM8994_VMID_RAMP_SHIFT) /* Soft slow start */
-#define WM8994_VMID_RAMP_SOFT_FAST_START (3 << WM8994_VMID_RAMP_SHIFT) /* Soft fast start */
+ /* Bits 8-15: Reserved */
+#define WM8994_MICB2_DISCH (1 << 8) /* Bit 7: Microphone Bias 2 Discharge */
+#define WM8994_MICB2_DISCH_FLOAT (0) /* MICBIAS2 floating when disabled */
+#define WM8994_MICB2_DISCH_DISCHARGED WM8994_MICB2_DISCH /* MICBIAS2 disharged when disabled */
+#define WM8994_MICB1_DISCH (1 << 7) /* Bit 7: Microphone Bias 1 Discharge */
+#define WM8994_MICB1_DISCH_FLOAT (0) /* MICBIAS1 floating when disabled */
+#define WM8994_MICB1_DISCH_DISCHARGED WM8994_MICB1_DISCH /* MICBIAS1 disharged when disabled */
+
+#define WM8994_VMID_DISCH (1 << 0) /* Bit 0:Connects VMID to ground */
+#define WM8994_VMID_DISCH_DISABLE (0) /* Disabled */
+#define WM8994_VMID_DISCH_ENABLE WM8994_VMID_DISCH /* Enabled */
+#define WM8994_BIAS_SRC (1 << 1) /* Bit 1: Selects the bias current source */
+# define WM8994_BIAS_SRC_NORMAL_BIAS (0) /* Normal bias */
+# define WM8994_BIAS_SRC_STARTUP_BIAS WM8994_BIAS_SRC /* Start-Up bias */
+#define WM8994_STARTUP_BIAS_ENA (1 << 2) /* Bit 2: Enables the Start-Up bias current generator */
+#define WM8994_VMID_BUF_ENA (1 << 3) /* Bit 3: VMID Buffer Enable */
+#define WM8994_VMID_RAMP_SHIFT (5) /* Bits 5-6: VMID soft start enable/slew rate control */
+#define WM8994_VMID_RAMP_MASK (3 << WM8994_VMID_RAMP_SHIFT)
+#define WM8994_VMID_RAMP_NORMAL_SLOW_START (0 << WM8994_VMID_RAMP_SHIFT) /* Normal slow start */
+#define WM8994_VMID_RAMP_NORMAL_FAST_START (1 << WM8994_VMID_RAMP_SHIFT) /* Normal fast start */
+#define WM8994_VMID_RAMP_SOFT_SLOW_START (2 << WM8994_VMID_RAMP_SHIFT) /* Soft slow start */
+#define WM8994_VMID_RAMP_SOFT_FAST_START (3 << WM8994_VMID_RAMP_SHIFT) /* Soft fast start */
/* R58 (0x3A) - MICBIAS
*/
@@ -829,15 +889,81 @@
/* R76 (0x4C) - Charge Pump (1)
*/
+#define WM8994_CP_ENA (1 << 15) /* Bit 15: Enable charge-pump digits */
+#define WM8994_CP_ENA_DISABLE (0) /* Diable */
+#define WM8994_CP_ENA_ENABLE (WM8994_CP_ENA) /* Enable */
+
/* R77 (0x4D) - Charge Pump (2)
*/
+#define WM8994_CP_DISCH (1 << 15) /* Bit 15: Charge Pump Discharge Select */
+#define WM8994_CP_DISCH_FLOAT (0) /* Charge Pump outputs floating when disabled */
+#define WM8994_CP_DISCH_DISCHARGE (WM8994_CP_DISCH) /* Charge Pump outputs discharged when disabled */
+
/* R81 (0x51) - Class W (1)
*/
+#define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* Bits 8-9: Selects the digitial audio source for
+ * envelope tracking */
+#define WM8994_CP_DYN_SRC_SEL_MASK (3 << WM8994_CP_DYN_SRC_SEL_SHIFT)
+#define WM8994_CP_DYN_SRC_SEL_AIF1_TS0 (0 << WM8994_CP_DYN_SRC_SEL_SHIFT) /* AIF1, DAC Timeslot 0 */
+#define WM8994_CP_DYN_SRC_SEL_AIF1_TS1 (1 << WM8994_CP_DYN_SRC_SEL_SHIFT) /* AIF1, DAC Timeslot 1 */
+#define WM8994_CP_DYN_SRC_SEL_AIF2_DATA (2 << WM8994_CP_DYN_SRC_SEL_SHIFT) /* AIF2, DAC data */
+
+#define WM8994_CP_DYN_PWR (1 << 0) /* Bit 0: Enable dynamic charge pump power control */
+#define WM8994_CP_DYN_PWR_CG (0) /* Charge pump controlled by volume register (Class G) */
+#define WM8994_CP_DYN_PWR_CW (WM8994_CP_DYN_PWR) /* Charge pump controlled by real-time audio lev. (Class W) */
+
/* R84 (0x54) - DC Servo (1)
*/
+#define WM8994_DCS_TRIG_SINGLE_1 (1 << 13) /* Bit 13: Writing 1 to this bit selects a single DC offset
+ * correction for HPOUT1R. In readback, a value of 1
+ * indicates that the DC Servo single correction is
+ * in progress
+ */
+#define WM8994_DCS_TRIG_SINGLE_0 (1 << 12) /* Bit 12: Writing 1 to this bit selects a single DC offset
+ * correction for HPOUT1L. In readback, a value of 1
+ * indicates that the DC Servo single correction is
+ * in progress
+ */
+#define WM8994_DCS_TRIG_SERIES_1 (1 << 9) /* Bit 9: Writing 1 to this bit selects a series of DC offset
+ * corrections for HPOUT1R. In readback, a value of 1
+ * indicates that the DC Servo DAC write correction is
+ * in progress
+ */
+#define WM8994_DCS_TRIG_SERIES_0 (1 << 8) /* Bit 8: Writing 1 to this bit selects a series of DC offset
+ * corrections for HPOUT1L. In readback, a value of 1
+ * indicates that the DC Servo DAC write correction is
+ * in progress
+ */
+#define WM8994_DCS_TRIG_STARTUP_1 (1 << 5) /* Bit 5: Writing 1 to this bit selects Start-Up DC
+ * Servo mode for HPOUT1R. In readback, a value of 1
+ * indicates that the DC Servo Start-Up correction is
+ * in progress
+ */
+#define WM8994_DCS_TRIG_STARTUP_0 (1 << 4) /* Bit 4: Writing 1 to this bit selects Start-Up DC
+ * Servo mode for HPOUT1L. In readback, a value of 1
+ * indicates that the DC Servo Start-Up correction is
+ * in progress
+ */
+#define WM8994_DCS_TRIG_DAC_WR_1 (1 << 3) /* Bit 3: Writing 1 to this bit selects DAC Write
+ * DC Servo mode for HPOUT1R. In readback, a value of 1
+ * indicates that the DC Servo DAC Write correction is
+ * in progress
+ */
+#define WM8994_DCS_TRIG_DAC_WR_0 (1 << 2) /* Bit 2: Writing 1 to this bit selects DAC Write
+ * DC Servo mode for HPOUT1L. In readback, a value of 1
+ * indicates that the DC Servo DAC Write correction is
+ * in progress
+ */
+#define WM8994_DCS_ENA_CHAN_1 (1 << 1) /* Bit 1: DC Servo enable for HPOUT1R */
+#define WM8994_DCS_ENA_CHAN_1_DISABLE (0) /* Diable */
+#define WM8994_DCS_ENA_CHAN_1_ENABLE (WM8994_DCS_ENA_CHAN_1) /* Enable */
+#define WM8994_DCS_ENA_CHAN_0 (1 << 0) /* Bit 0: DC Servo enable for HPOUT1L */
+#define WM8994_DCS_ENA_CHAN_0_DISABLE (0) /* Diable */
+#define WM8994_DCS_ENA_CHAN_0_ENABLE (WM8994_DCS_ENA_CHAN_1) /* Enable */
+
/* R85 (0x55) - DC Servo (2)
*/
@@ -850,6 +976,25 @@
/* R96 (0x60) - Analogue HP (1)
*/
+#define WM8994_HPOUT1L_RMV_SHORT (1 << 7) /* Bit 7: Removes HPOUT1L short */
+#define WM8994_HPOUT1L_RMV_SHORT_DISABLE (0) /* HPOUT1L short diabled */
+#define WM8994_HPOUT1L_RMV_SHORT_ENABLE (WM8994_HPOUT1L_RMV_SHORT) /* HPOUT1L short enabled */
+#define WM8994_HPOUT1L_OUTP (1 << 6) /* Bit 6: Enables HPOUT1L output stage */
+#define WM8994_HPOUT1L_OUTP_DISABLE (0) /* Diable */
+#define WM8994_HPOUT1L_OUTP_ENABLE (WM8994_HPOUT1L_OUTP) /* Enable */
+#define WM8994_HPOUT1L_DLY (1 << 5) /* Bit 5: Enables HPOUT1L intermediate stage */
+#define WM8994_HPOUT1L_DLY_DISABLE (0) /* Diable */
+#define WM8994_HPOUT1L_DLY_ENABLE (WM8994_HPOUT1L_DLY) /* Enable */
+#define WM8994_HPOUT1R_RMV_SHORT (1 << 3) /* Bit 3: Removes HPOUT1R short */
+#define WM8994_HPOUT1R_RMV_SHORT_DISABLE (0) /* HPOUT1R short diabled */
+#define WM8994_HPOUT1R_RMV_SHORT_ENABLE (WM8994_HPOUT1R_RMV_SHORT) /* HPOUT1R short enabled */
+#define WM8994_HPOUT1R_OUTP (1 << 2) /* Bit 2: Enables HPOUT1R output stage */
+#define WM8994_HPOUT1R_OUTP_DISABLE (0) /* Diable */
+#define WM8994_HPOUT1R_OUTP_ENABLE (WM8994_HPOUT1R_OUTP) /* Enable */
+#define WM8994_HPOUT1R_DLY (1 << 1) /* Bit 1: Enables HPOUT1R intermediate stage */
+#define WM8994_HPOUT1R_DLY_DISABLE (0) /* Diable */
+#define WM8994_HPOUT1R_DLY_ENABLE (WM8994_HPOUT1R_DLY) /* Enable */
+
/* R208 (0xD0) - Mic Detect 1
*/
@@ -868,9 +1013,21 @@
/* R272 (0x110) - Write Sequencer Ctrl (1)
*/
+#define WM8994_WSEQ_ENA (1 << 15) /* Bit 15: Write Sequencer Enable */
+#define WM8994_WSEQ_ENA_DISABLE (0) /* Diable */
+#define WM8994_WSEQ_ENA_ENABLE (WM8994_WSEQ_ENA) /* Enable */
+#define WM8994_WSEQ_ABORT (1 << 9) /* Bit 9: Writing 1 to this bit aborts the current seq. */
+#define WM8994_WSEQ_START (1 << 8) /* Bit 8: Writing 1 to this bit starts the seq. */
+#define WM8994_WSEQ_START_INDEX_SHIFT (0) /* Bits 0-6: Sequence start index */
+#define WM8994_WSEQ_START_INDEX_MASK (0x7F << WM8994_WSEQ_START_INDEX_SHIFT)
+
/* R273 (0x111) - Write Sequencer Ctrl (2)
*/
+#define WM8994_WSEQ_BUSY (1 << 8) /* Bit 8: Sequencer busy flag (read only) */
+#define WM8994_WSEQ_CURRENT_INDEX_SHIFT (0) /* Bits 0-6: Sequence current index */
+#define WM8994_WSEQ_CURRENT_INDEX_MASK (0x7F << W8994_WSEQ_CURRENT_INDEX_SHIFT)
+
/* R512 (0x200) - AIF1 Clocking (1)
*/
@@ -901,13 +1058,13 @@
/* R520 (0x208) - Clocking (1)
*/
-#define WM8994_SYSCLK_SRC (1 << 0) /* Bit 0: SYSCLK Source Select */
-#define WM8994_SYSCLK_SRC_AIF1CLK (0) /* AIF1CLK */
-#define WM8994_SYSCLK_SRC_AIF2CLK (WM8994_SYSCLK_SRC) /* AIF2CLK */
-#define WM8994_SYSDSPCLK_ENA (1 << 1) /* Bit 1: Digital Mixing Processor Clock Enable */
-#define WM8994_AIF2DSPCLK_ENA (1 << 2) /* Bit 2: AIF2 Processor Clock Enable */
-#define WM8994_AIF1DSPCLK_ENA (1 << 3) /* Bit 3: AIF1 Processor Clock Enable */
-#define WM8994_TOCLK_ENA (1 << 4) /* Bit 4: Slow Clock(TOCLK) Enable */
+#define WM8994_SYSCLK_SRC (1 << 0) /* Bit 0: SYSCLK Source Select */
+#define WM8994_SYSCLK_SRC_AIF1CLK (0) /* AIF1CLK */
+#define WM8994_SYSCLK_SRC_AIF2CLK (WM8994_SYSCLK_SRC) /* AIF2CLK */
+#define WM8994_SYSDSPCLK_ENA (1 << 1) /* Bit 1: Digital Mixing Processor Clock Enable */
+#define WM8994_AIF2DSPCLK_ENA (1 << 2) /* Bit 2: AIF2 Processor Clock Enable */
+#define WM8994_AIF1DSPCLK_ENA (1 << 3) /* Bit 3: AIF1 Processor Clock Enable */
+#define WM8994_TOCLK_ENA (1 << 4) /* Bit 4: Slow Clock(TOCLK) Enable */
/* Bits 5-15: Reserved */
/* R521 (0x209) - Clocking (2)
@@ -916,31 +1073,31 @@
/* R528 (0x210) - AIF1 Rate
*/
-#define WM8994_AIF1CLK_RATE_SHIFT (0) /* Bits 0-3: Selects the AIF1CLK/fs ratio */
-#define WM8994_AIF1CLK_RATE_MASK (0xf << WM8994_AIF1CLK_RATE_SHIFT)
-#define WM8994_AIF1CLK_RATE_0 (0 << WM8994_AIF1CLK_RATE_SHIFT) /* Reserved */
-#define WM8994_AIF1CLK_RATE_1 (1 << WM8994_AIF1CLK_RATE_SHIFT) /* 128 */
-#define WM8994_AIF1CLK_RATE_2 (2 << WM8994_AIF1CLK_RATE_SHIFT) /* 192 */
-#define WM8994_AIF1CLK_RATE_3 (3 << WM8994_AIF1CLK_RATE_SHIFT) /* 256 */
-#define WM8994_AIF1CLK_RATE_4 (4 << WM8994_AIF1CLK_RATE_SHIFT) /* 384 */
-#define WM8994_AIF1CLK_RATE_5 (5 << WM8994_AIF1CLK_RATE_SHIFT) /* 512 */
-#define WM8994_AIF1CLK_RATE_6 (6 << WM8994_AIF1CLK_RATE_SHIFT) /* 768 */
-#define WM8994_AIF1CLK_RATE_7 (7 << WM8994_AIF1CLK_RATE_SHIFT) /* 1024 */
-#define WM8994_AIF1CLK_RATE_8 (8 << WM8994_AIF1CLK_RATE_SHIFT) /* 1408 */
-#define WM8994_AIF1CLK_RATE_9 (9 << WM8994_AIF1CLK_RATE_SHIFT) /* 1536 */
-#define WM8994_AIF1_SR_SHIFT (4) /* Bits 4-7: Selects the AIF1 Sample Rate (fs) */
-#define WM8994_AIF1_SR_MASK (0xf << WM8994_AIF1CLK_RATE_SHIFT)
-#define WM8994_AIF1_SR_8K (0 << WM8994_AIF1CLK_RATE_SHIFT) /* 8kHz */
-#define WM8994_AIF1_SR_11K (1 << WM8994_AIF1CLK_RATE_SHIFT) /* 11.025kHz */
-#define WM8994_AIF1_SR_12K (2 << WM8994_AIF1CLK_RATE_SHIFT) /* 12kHz */
-#define WM8994_AIF1_SR_16K (3 << WM8994_AIF1CLK_RATE_SHIFT) /* 16kHz */
-#define WM8994_AIF1_SR_22K (4 << WM8994_AIF1CLK_RATE_SHIFT) /* 22.05kHz */
-#define WM8994_AIF1_SR_24K (5 << WM8994_AIF1CLK_RATE_SHIFT) /* 24kHz */
-#define WM8994_AIF1_SR_32K (6 << WM8994_AIF1CLK_RATE_SHIFT) /* 32kHz */
-#define WM8994_AIF1_SR_44K (7 << WM8994_AIF1CLK_RATE_SHIFT) /* 44.1kHz */
-#define WM8994_AIF1_SR_48K (8 << WM8994_AIF1CLK_RATE_SHIFT) /* 48kHz */
-#define WM8994_AIF1_SR_88K (9 << WM8994_AIF1CLK_RATE_SHIFT) /* 88.2kHz */
-#define WM8994_AIF1_SR_96K (10 << WM8994_AIF1CLK_RATE_SHIFT) /* 96kHz */
+#define WM8994_AIF1CLK_RATE_SHIFT (0) /* Bits 0-3: Selects the AIF1CLK/fs ratio */
+#define WM8994_AIF1CLK_RATE_MASK (0xf << WM8994_AIF1CLK_RATE_SHIFT)
+#define WM8994_AIF1CLK_RATE_0 (0 << WM8994_AIF1CLK_RATE_SHIFT) /* Reserved */
+#define WM8994_AIF1CLK_RATE_1 (1 << WM8994_AIF1CLK_RATE_SHIFT) /* 128 */
+#define WM8994_AIF1CLK_RATE_2 (2 << WM8994_AIF1CLK_RATE_SHIFT) /* 192 */
+#define WM8994_AIF1CLK_RATE_3 (3 << WM8994_AIF1CLK_RATE_SHIFT) /* 256 */
+#define WM8994_AIF1CLK_RATE_4 (4 << WM8994_AIF1CLK_RATE_SHIFT) /* 384 */
+#define WM8994_AIF1CLK_RATE_5 (5 << WM8994_AIF1CLK_RATE_SHIFT) /* 512 */
+#define WM8994_AIF1CLK_RATE_6 (6 << WM8994_AIF1CLK_RATE_SHIFT) /* 768 */
+#define WM8994_AIF1CLK_RATE_7 (7 << WM8994_AIF1CLK_RATE_SHIFT) /* 1024 */
+#define WM8994_AIF1CLK_RATE_8 (8 << WM8994_AIF1CLK_RATE_SHIFT) /* 1408 */
+#define WM8994_AIF1CLK_RATE_9 (9 << WM8994_AIF1CLK_RATE_SHIFT) /* 1536 */
+#define WM8994_AIF1_SR_SHIFT (4) /* Bits 4-7: Selects the AIF1 Sample Rate (fs) */
+#define WM8994_AIF1_SR_MASK (0xf << WM8994_AIF1_SR_SHIFT)
+#define WM8994_AIF1_SR_8K (0 << WM8994_AIF1_SR_SHIFT) /* 8kHz */
+#define WM8994_AIF1_SR_11K (1 << WM8994_AIF1_SR_SHIFT) /* 11.025kHz */
+#define WM8994_AIF1_SR_12K (2 << WM8994_AIF1_SR_SHIFT) /* 12kHz */
+#define WM8994_AIF1_SR_16K (3 << WM8994_AIF1_SR_SHIFT) /* 16kHz */
+#define WM8994_AIF1_SR_22K (4 << WM8994_AIF1_SR_SHIFT) /* 22.05kHz */
+#define WM8994_AIF1_SR_24K (5 << WM8994_AIF1_SR_SHIFT) /* 24kHz */
+#define WM8994_AIF1_SR_32K (6 << WM8994_AIF1_SR_SHIFT) /* 32kHz */
+#define WM8994_AIF1_SR_44K (7 << WM8994_AIF1_SR_SHIFT) /* 44.1kHz */
+#define WM8994_AIF1_SR_48K (8 << WM8994_AIF1_SR_SHIFT) /* 48kHz */
+#define WM8994_AIF1_SR_88K (9 << WM8994_AIF1_SR_SHIFT) /* 88.2kHz */
+#define WM8994_AIF1_SR_96K (10 << WM8994_AIF1_SR_SHIFT) /* 96kHz */
/* Bits 8-15: Reserved */
/* R529 (0x211) - AIF2 Rate
@@ -994,28 +1151,28 @@
/* R768 (0x300) - AIF1 Control (1)
*/
- /* Bits 0-2: Reserved */
-#define WM8994_AIF1_FMT_SHIFT (3) /* Bits 3-4: AIF1 Digital Audio Interface Format */
-#define WM8994_AIF1_FMT_MASK (3 << WM8994_AIF1_FMT_SHIFT)
-#define WM8994_AIF1_FMT_RIGHT (0 << WM8994_AIF1_FMT_SHIFT) /* Right justified */
-#define WM8994_AIF1_FMT_LEFT (1 << WM8994_AIF1_FMT_SHIFT) /* Left justified */
-#define WM8994_AIF1_FMT_I2S (2 << WM8994_AIF1_FMT_SHIFT) /* I2S Format */
-#define WM8994_AIF1_FMT_DSP (3 << WM8994_AIF1_FMT_SHIFT) /* DSP Mode */
-#define WM8994_AIF1_WL_SHIFT (5) /* Bits 5-6: AIF1 Digital Audio Interface Word Length */
-#define WM8994_AIF1_WL_MASK (3 << WM8994_AIF1_WL_SHIFT)
-#define WM8994_AIF1_WL_16BITS (0 << WM8994_AIF1_WL_SHIFT) /* 16 bits */
-#define WM8994_AIF1_WL_20BITS (1 << WM8994_AIF1_WL_SHIFT) /* 20 bits */
-#define WM8994_AIF1_WL_24BITS (2 << WM8994_AIF1_WL_SHIFT) /* 24 bits */
-#define WM8994_AIF1_WL_32BITS (3 << WM8994_AIF1_WL_SHIFT) /* 32 bits */
-#define WM8994_AIF1ADC_TDM (1 << 13) /* Bit 13: AIF1 transmit (ADC) TDM control */
-#define WM8994_AIF1ADC_TDM_0 (0) /* ADCDAT1 driver logic '0' when not transmit data */
-#define WM8994_AIF1ADC_TDM_TRI (WM8994_AIF1ADC_TDM) /* ADCDAT1 is tri-stated when not transmit data */
-#define WM8994_AIF1ADCR_SRC (1 << 14) /* Bit 14: AIF1 Right Audio Interface Source */
-#define WM8994_AIF1ADCR_LEFT_ADC (0) /* Left ADC data is output on right channel */
-#define WM8994_AIF1ADCR_RIGHT_ADC (WM8994_AIF1ADCR_SRC) /* Right ADC data is output on right channel */
-#define WM8994_AIF1ADCL_SRC (1 << 15) /* Bit 15: AIF1 Left Audio Interface Source */
-#define WM8994_AIF1ADCL_LEFT_ADC (0) /* Left ADC data is output on left channel */
-#define WM8994_AIF1ADCL_RIGHT_ADC (WM8994_AIF1ADCL_SRC) /* Right ADC data is output on left channel */
+ /* Bits 0-2: Reserved */
+#define WM8994_AIF1_FMT_SHIFT (3) /* Bits 3-4: AIF1 Digital Audio Interface Format */
+#define WM8994_AIF1_FMT_MASK (3 << WM8994_AIF1_FMT_SHIFT)
+#define WM8994_AIF1_FMT_RIGHT (0 << WM8994_AIF1_FMT_SHIFT) /* Right justified */
+#define WM8994_AIF1_FMT_LEFT (1 << WM8994_AIF1_FMT_SHIFT) /* Left justified */
+#define WM8994_AIF1_FMT_I2S (2 << WM8994_AIF1_FMT_SHIFT) /* I2S Format */
+#define WM8994_AIF1_FMT_DSP (3 << WM8994_AIF1_FMT_SHIFT) /* DSP Mode */
+#define WM8994_AIF1_WL_SHIFT (5) /* Bits 5-6: AIF1 Digital Audio Interface Word Length */
+#define WM8994_AIF1_WL_MASK (3 << WM8994_AIF1_WL_SHIFT)
+#define WM8994_AIF1_WL_16BITS (0 << WM8994_AIF1_WL_SHIFT) /* 16 bits */
+#define WM8994_AIF1_WL_20BITS (1 << WM8994_AIF1_WL_SHIFT) /* 20 bits */
+#define WM8994_AIF1_WL_24BITS (2 << WM8994_AIF1_WL_SHIFT) /* 24 bits */
+#define WM8994_AIF1_WL_32BITS (3 << WM8994_AIF1_WL_SHIFT) /* 32 bits */
+#define WM8994_AIF1ADC_TDM (1 << 13) /* Bit 13: AIF1 transmit (ADC) TDM control */
+#define WM8994_AIF1ADC_TDM_0 (0) /* ADCDAT1 driver logic '0' when not transmit data */
+#define WM8994_AIF1ADC_TDM_TRI (WM8994_AIF1ADC_TDM) /* ADCDAT1 is tri-stated when not transmit data */
+#define WM8994_AIF1ADCR_SRC (1 << 14) /* Bit 14: AIF1 Right Audio Interface Source */
+#define WM8994_AIF1ADCR_LEFT_ADC (0) /* Left ADC data is output on right channel */
+#define WM8994_AIF1ADCR_RIGHT_ADC (WM8994_AIF1ADCR_SRC) /* Right ADC data is output on right channel */
+#define WM8994_AIF1ADCL_SRC (1 << 15) /* Bit 15: AIF1 Left Audio Interface Source */
+#define WM8994_AIF1ADCL_LEFT_ADC (0) /* Left ADC data is output on left channel */
+#define WM8994_AIF1ADCL_RIGHT_ADC (WM8994_AIF1ADCL_SRC) /* Right ADC data is output on left channel */
/* R769 (0x301) - AIF1 Control (2)
*/
@@ -1023,19 +1180,19 @@
/* R770 (0x302) - AIF1 Master/Slave
*/
- /* Bits 0-11: Reserved */
-#define WM8994_AIF1_LRCLK_FRC (1 << 12) /* Bit 12: Forces LRCLK1 and ADCLRCLK1 to enabled when all AIF1 audio channels are disabled */
-#define WM8994_AIF1_LRCLK_FRC_NORMAL (0) /* Normal */
-#define WM8994_AIF1_LRCLK_FRC_YES (WM8994_AIF1_LRCLK_FRC) /* LRCLK1 and ADCLRCLK1 always enabled in Master Mode */
-#define WM8994_AIF1_CLK_FRC (1 << 13) /* Bit 13: Forces BCLK1, LRCLK1 and ADCLRCLK1 to enabled when all AIF1 audio channels are disabled */
-#define WM8994_AIF1_CLK_FRC_NORMAL (0) /* Normal */
-#define WM8994_AIF1_CLK_FRC_YES (WM8994_AIF1_CLK_FRC) /* BLCK1, LRCLK1 and ADCLRCLK1 always enabled in Master Mode */
-#define WM8994_AIF1_MSTR (1 << 14) /* Bit 14: AIF1 Audio Interface Master Mode Select */
-#define WM8994_AIF1_MSTR_SLAVE_MODE (0) /* Slave Mode */
-#define WM8994_AIF1_MSTR_MASTER_MODE (WM8994_AIF1_MSTR) /* Master Mode */
-#define WM8994_AIF1_TRI (1 << 15) /* Bit 15: AIF1 Audio Interface tri-state */
-#define WM8994_AIF1_TRI_NORMAL (0) /* AIF1 pins operate normally */
-#define WM8994_AIF1_TRI_TRI (WM8994_AIF1_TRI) /* Tri-state all AIF1 interface pins */
+ /* Bits 0-11: Reserved */
+#define WM8994_AIF1_LRCLK_FRC (1 << 12) /* Bit 12: Forces LRCLK1 and ADCLRCLK1 to enabled when all AIF1 audio channels are disabled */
+#define WM8994_AIF1_LRCLK_FRC_NORMAL (0) /* Normal */
+#define WM8994_AIF1_LRCLK_FRC_YES (WM8994_AIF1_LRCLK_FRC) /* LRCLK1 and ADCLRCLK1 always enabled in Master Mode */
+#define WM8994_AIF1_CLK_FRC (1 << 13) /* Bit 13: Forces BCLK1, LRCLK1 and ADCLRCLK1 to enabled when all AIF1 audio channels are disabled */
+#define WM8994_AIF1_CLK_FRC_NORMAL (0) /* Normal */
+#define WM8994_AIF1_CLK_FRC_YES (WM8994_AIF1_CLK_FRC) /* BLCK1, LRCLK1 and ADCLRCLK1 always enabled in Master Mode */
+#define WM8994_AIF1_MSTR (1 << 14) /* Bit 14: AIF1 Audio Interface Master Mode Select */
+#define WM8994_AIF1_MSTR_SLAVE_MODE (0) /* Slave Mode */
+#define WM8994_AIF1_MSTR_MASTER_MODE (WM8994_AIF1_MSTR) /* Master Mode */
+#define WM8994_AIF1_TRI (1 << 15) /* Bit 15: AIF1 Audio Interface tri-state */
+#define WM8994_AIF1_TRI_NORMAL (0) /* AIF1 pins operate normally */
+#define WM8994_AIF1_TRI_TRI (WM8994_AIF1_TRI) /* Tri-state all AIF1 interface pins */
/* R771 (0x303) - AIF1 BCLK
*/
@@ -1097,9 +1254,16 @@
/* R1026 (0x402) - AIF1 DAC1 Left Volume
*/
+#define WM8994_AIF1DAC1_VU (1 << 8) /* Bit 8: AIF1DAC1 input path (AIF1, TS 0) Vol Update */
+#define WM8994_AIF1DAC1L_VOL_SHIFT (0) /* Bits 0-7: AIF1DAC1 (Left) input path, Digital Vol. */
+#define WM8994_AIF1DAC1L_VOL_MASK (0xFF << WM8994_AIF1DAC1L_VOL_SHIFT)
+
/* R1027 (0x403) - AIF1 DAC1 Right Volume
*/
+#define WM8994_AIF1DAC1R_VOL_SHIFT (0) /* Bits 0-7: AIF1DAC1 (Right) input path, Digital Vol. */
+#define WM8994_AIF1DAC1R_VOL_MASK (0xFF << WM8994_AIF1DAC1R_VOL_SHIFT)
+
/* R1028 (0x404) - AIF1 ADC2 Left Volume
*/
@@ -1109,36 +1273,82 @@
/* R1030 (0x406) - AIF1 DAC2 Left Volume
*/
+#define WM8994_AIF1DAC2_VU (1 << 8) /* Bit 8: AIF1DAC2 input path (AIF1, TS 1) Vol Update */
+#define WM8994_AIF1DAC2L_VOL_SHIFT (0) /* Bits 0-7: AIF1DAC2 (Left) input path, Digital Vol. */
+#define WM8994_AIF1DAC2L_VOL_MASK (0xFF << WM8994_AIF1DAC2L_VOL_SHIFT)
+
/* R1031 (0x407) - AIF1 DAC2 Right Volume
*/
+#define WM8994_AIF1DAC2R_VOL_SHIFT (0) /* Bits 0-7: AIF1DAC2 (Right) input path, Digital Vol. */
+#define WM8994_AIF1DAC2R_VOL_MASK (0xFF << WM8994_AIF1DAC2R_VOL_SHIFT)
+
/* R1040 (0x410) - AIF1 ADC1 Filters
*/
/* R1041 (0x411) - AIF1 ADC2 Filters
*/
-#define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */
-#define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */
-#define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */
-#define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */
-#define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */
-#define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */
-#define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */
-#define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */
-#define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */
-#define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */
-#define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */
+#define WM8994_AIF1ADC2_HPF_CUT_SHIFT (13) /* Bits 13-14: AIF1ADC2 output path (AIF1, TS 1), HPF CO */
+#define WM8994_AIF1ADC2_HPF_CUT_MASK (3 << WM8994_AIF1ADC2_HPF_CUT_SHIFT)
+#define WM8994_AIF1ADC2_HPF_CUT_HIFI (0 << WM8994_AIF1ADC2_HPF_CUT_SHIFT) /* Hi-fi mode (fc = 4 Hz at fs = 48kHz) */
+#define WM8994_AIF1ADC2_HPF_CUT_VOICE1 (1 << WM8994_AIF1ADC2_HPF_CUT_SHIFT) /* Voice mode 1 (fc = 127 Hz at fs = 8kHz) */
+#define WM8994_AIF1ADC2_HPF_CUT_VOICE2 (2 << WM8994_AIF1ADC2_HPF_CUT_SHIFT) /* Voice mode 2 (fc = 130 Hz at fs = 8kHz) */
+#define WM8994_AIF1ADC2_HPF_CUT_VOICE3 (3 << WM8994_AIF1ADC2_HPF_CUT_SHIFT) /* Voice mode 3 (fc = 267 Hz at fs = 8kHz) */
+#define WM8994_AIF1ADC2L_HPF (1 << 12) /* Bit 12: AIF1ADC2 (Left) output path (AIF1, TS 1) Dig. HPF */
+#define WM8994_AIF1ADC2L_HPF_DISABLE (0) /* Disable */
+#define WM8994_AIF1ADC2L_HPF_ENABLE (WM8994_AIF1ADC2L_HPF) /* Enable */
+#define WM8994_AIF1ADC2R_HPF (1 << 11) /* Bit 11: AIF1ADC2 (Right) output path (AIF1, TS 1) Dig. HPF */
+#define WM8994_AIF1ADC2R_HPF_DISABLE (0) /* Disable */
+#define WM8994_AIF1ADC2R_HPF_ENABLE (WM8994_AIF1ADC2R_HPF) /* Enable */
/* R1056 (0x420) - AIF1 DAC1 Filters (1)
*/
+#define WM8994_AIF1DAC1_MUTE (1 << 9) /* Bit 9: AIF1DAC1 input path (AIF1, TS 0) Soft Mute Control */
+#define WM8994_AIF1DAC1_MUTE_UNMUTE (0) /* Un-mute */
+#define WM8994_AIF1DAC1_MUTE_MUTE (WM8994_AIF1DAC1_MUTE) /* Mute */
+#define WM8994_AIF1DAC1_MONO (1 << 7) /* Bit 7: AIF1DAC1 input path (AIF1, TS 0) Mono Mix Control */
+#define WM8994_AIF1DAC1_MONO_DISABLE (0) /* Disabled */
+#define WM8994_AIF1DAC1_MONO_ENABLE (WM8994_AIF1DAC1_MONO) /* Enabled */
+#define WM8994_AIF1DAC1_MUTERATE (1 << 5) /* Bit 5: AIF1DAC1 input path (AIF1, TS 0) Soft Mute Ramp Rate */
+#define WM8994_AIF1DAC1_MUTERATE_FAST (0) /* Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48kHz */
+#define WM8994_AIF1DAC1_MUTERATE_SLOW (WM8994_AIF1DAC1_MUTERATE) /* Slow ramp (fs/32, maximum ramp time is 171ms at fs=48kHz */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP (1 << 4) /* Bit 4: AIF1DAC1 input path (AIF1, TS 0) Unmute Ramp select */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP_IMMEDIATE (0) /* Volume change immediately to AIF1DAC1L_VOL */
+#define WM8994_AIF1DAC1_UNMUTE_RAMP_GRADUAL (WM8994_AIF1DAC1_UNMUTE_RAMP) /* Volume change gradually to AIF1DAC1R_VOL */
+#define WM8994_AIF1DAC1_DEEMP_SHIFT (1) /* Bit 1-2: AIF1DAC1 input path (AIF1, TS 0), De-Emphasis */
+#define WM8994_AIF1DAC1_DEEMP_MASK (3 << WM8994_AIF1DAC1_DEEMP_SHIFT)
+#define WM8994_AIF1DAC1_DEEMP_NO (0 << WM8994_AIF1DAC1_DEEMP_SHIFT) /* No de-emphasis */
+#define WM8994_AIF1DAC1_DEEMP_32KHZ (1 << WM8994_AIF1DAC1_DEEMP_SHIFT) /* 32kHz sample rate */
+#define WM8994_AIF1DAC1_DEEMP_44KHZ (2 << WM8994_AIF1DAC1_DEEMP_SHIFT) /* 44.1kHz sample rate */
+#define WM8994_AIF1DAC1_DEEMP_48KHZ (3 << WM8994_AIF1DAC1_DEEMP_SHIFT) /* 48kHz sample rate*/
+
/* R1057 (0x421) - AIF1 DAC1 Filters (2)
*/
/* R1058 (0x422) - AIF1 DAC2 Filters (1)
*/
+#define WM8994_AIF1DAC2_MUTE (1 << 9) /* Bit 9: AIF1DAC2 input path (AIF1, TS 1) Soft Mute Control */
+#define WM8994_AIF1DAC2_MUTE_UNMUTE (0) /* Un-mute */
+#define WM8994_AIF1DAC2_MUTE_MUTE (WM8994_AIF1DAC2_MUTE) /* Mute */
+#define WM8994_AIF1DAC2_MONO (1 << 7) /* Bit 7: AIF1DAC2 input path (AIF1, TS 1) Mono Mix Control */
+#define WM8994_AIF1DAC2_MONO_DISABLE (0) /* Disabled */
+#define WM8994_AIF1DAC2_MONO_ENABLE (WM8994_AIF1DAC2_MONO) /* Enabled */
+#define WM8994_AIF1DAC2_MUTERATE (1 << 5) /* Bit 5: AIF1DAC2 input path (AIF1, TS 1) Soft Mute Ramp Rate */
+#define WM8994_AIF1DAC2_MUTERATE_FAST (0) /* Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48kHz */
+#define WM8994_AIF1DAC2_MUTERATE_SLOW (WM8994_AIF1DAC2_MUTERATE) /* Slow ramp (fs/32, maximum ramp time is 171ms at fs=48kHz */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP (1 << 4) /* Bit 4: AIF1DAC2 input path (AIF1, TS 1) Unmute Ramp select */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP_IMMEDIATE (0) /* Volume change immediately to AIF1DAC1L_VOL */
+#define WM8994_AIF1DAC2_UNMUTE_RAMP_GRADUAL (WM8994_AIF1DAC2_UNMUTE_RAMP) /* Volume change gradually to AIF1DAC1R_VOL */
+#define WM8994_AIF1DAC2_DEEMP_SHIFT (1) /* Bit 1-2: AIF1DAC2 input path (AIF1, TS 1), De-Emphasis */
+#define WM8994_AIF1DAC2_DEEMP_MASK (3 << WM8994_AIF1DAC2_DEEMP_SHIFT)
+#define WM8994_AIF1DAC2_DEEMP_NO (0 << WM8994_AIF1DAC2_DEEMP_SHIFT) /* No de-emphasis */
+#define WM8994_AIF1DAC2_DEEMP_32KHZ (1 << WM8994_AIF1DAC2_DEEMP_SHIFT) /* 32kHz sample rate */
+#define WM8994_AIF1DAC2_DEEMP_44KHZ (2 << WM8994_AIF1DAC2_DEEMP_SHIFT) /* 44.1kHz sample rate */
+#define WM8994_AIF1DAC2_DEEMP_48KHZ (3 << WM8994_AIF1DAC2_DEEMP_SHIFT) /* 48kHz sample rate*/
+
/* R1059 (0x423) - AIF1 DAC2 Filters (2)
*/
@@ -1403,49 +1613,54 @@
/* R1537 (0x601) - DAC1 Left Mixer Routing
*/
-#define WM8994_AIF1DAC1L_TO_DAC1L_ENA (1 << 0) /* Bit 0: Enable AIF1(Timeslot 0, Left) to DAC1L */
-#define WM8994_AIF1DAC2L_TO_DAC1L_ENA (1 << 1) /* Bit 1: Enable AIF1(Timeslot 1, Left) to DAC1L */
-#define WM8994_AIF2DACL_TO_DAC1L_ENA (1 << 2) /* Bit 2: Enable AIF2(Left) to DAC1L */
- /* Bit 3: Reserved */
-#define WM8994_ADCL_TO_DAC1L_ENA (1 << 4) /* Bit 4: Enable Sidetone STL to DAC1L */
-#define WM8994_ADCR_TO_DAC1L_ENA (1 << 5) /* Bit 5: Enable Sidetone STR to DAC1L */
- /* Bits 6-15: Reserved */
+#define WM8994_AIF1DAC1L_TO_DAC1L_ENA (1 << 0) /* Bit 0: Enable AIF1(Timeslot 0, Left) to DAC1L */
+#define WM8994_AIF1DAC2L_TO_DAC1L_ENA (1 << 1) /* Bit 1: Enable AIF1(Timeslot 1, Left) to DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L_ENA (1 << 2) /* Bit 2: Enable AIF2(Left) to DAC1L */
+ /* Bit 3: Reserved */
+#define WM8994_ADCL_TO_DAC1L_ENA (1 << 4) /* Bit 4: Enable Sidetone STL to DAC1L */
+#define WM8994_ADCR_TO_DAC1L_ENA (1 << 5) /* Bit 5: Enable Sidetone STR to DAC1L */
+ /* Bits 6-15: Reserved */
/* R1538 (0x602) - DAC1 Right Mixer Routing
*/
-#define WM8994_AIF1DAC1R_TO_DAC1R_ENA (1 << 0) /* Bit 0: Enable AIF1(Timeslot 0, Right) to DAC1R */
-#define WM8994_AIF1DAC2R_TO_DAC1R_ENA (1 << 1) /* Bit 1: Enable AIF1(Timeslot 1, Right) to DAC1R */
-#define WM8994_AIF2DACR_TO_DAC1R_ENA (1 << 2) /* Bit 2: Enable AIF2(Right) to DAC1R */
- /* Bit 3: Reserved */
-#define WM8994_ADCL_TO_DAC1R_ENA (1 << 4) /* Bit 4: Enable Sidetone STL to DAC1R */
-#define WM8994_ADCR_TO_DAC1R_ENA (1 << 5) /* Bit 5: Enable Sidetone STR to DAC1R */
- /* Bits 6-15: Reserved */
+#define WM8994_AIF1DAC1R_TO_DAC1R_ENA (1 << 0) /* Bit 0: Enable AIF1(Timeslot 0, Right) to DAC1R */
+#define WM8994_AIF1DAC2R_TO_DAC1R_ENA (1 << 1) /* Bit 1: Enable AIF1(Timeslot 1, Right) to DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R_ENA (1 << 2) /* Bit 2: Enable AIF2(Right) to DAC1R */
+ /* Bit 3: Reserved */
+#define WM8994_ADCL_TO_DAC1R_ENA (1 << 4) /* Bit 4: Enable Sidetone STL to DAC1R */
+#define WM8994_ADCR_TO_DAC1R_ENA (1 << 5) /* Bit 5: Enable Sidetone STR to DAC1R */
+ /* Bits 6-15: Reserved */
/* R1539 (0x603) - DAC2 Mixer Volumes
*/
+#define WM8994_ADCR_DAC2_VOL_SHIFT (5) /* Bits 5-8: Sidetone STR to DAC2L and DAC2R Volume */
+#define WM8994_ADCR_DAC2_VOL_MASK (0xF << WM8994_ADCR_DAC2_VOL_SHIFT) /* 0000 = -36 DB, 1100 = 0dB */
+#define WM8994_ADCL_DAC2_VOL_SHIFT (0) /* Bits 0-3: Sidetone STL to DAC2L and DAC2R Volume */
+#define WM8994_ADCL_DAC2_VOL_MASK (0xF << WM8994_ADCL_DAC2_VOL_SHIFT /* 0000 = -36 DB, 1100 = 0dB */
+
/* R1540 (0x604) - DAC2 Left Mixer Routing
*/
-#define WM8994_AIF1DAC1L_TO_DAC2L_ENA (1 << 0) /* Bit 0: Enable AIF1(Timeslot 0, Left) to DAC2L */
-#define WM8994_AIF1DAC2L_TO_DAC2L_ENA (1 << 1) /* Bit 1: Enable AIF1(Timeslot 1, Left) to DAC2L */
-#define WM8994_AIF2DACL_TO_DAC2L_ENA (1 << 2) /* Bit 2: Enable AIF2(Left) to DAC2L */
- /* Bit 3: Reserved */
-#define WM8994_ADCL_TO_DAC2L_ENA (1 << 4) /* Bit 4: Enable Sidetone STL to DAC2L */
-#define WM8994_ADCR_TO_DAC2L_ENA (1 << 5) /* Bit 5: Enable Sidetone STR to DAC2L */
- /* Bits 6-15: Reserved */
+#define WM8994_AIF1DAC1L_TO_DAC2L_ENA (1 << 0) /* Bit 0: Enable AIF1(Timeslot 0, Left) to DAC2L */
+#define WM8994_AIF1DAC2L_TO_DAC2L_ENA (1 << 1) /* Bit 1: Enable AIF1(Timeslot 1, Left) to DAC2L */
+#define WM8994_AIF2DACL_TO_DAC2L_ENA (1 << 2) /* Bit 2: Enable AIF2(Left) to DAC2L */
+ /* Bit 3: Reserved */
+#define WM8994_ADCL_TO_DAC2L_ENA (1 << 4) /* Bit 4: Enable Sidetone STL to DAC2L */
+#define WM8994_ADCR_TO_DAC2L_ENA (1 << 5) /* Bit 5: Enable Sidetone STR to DAC2L */
+ /* Bits 6-15: Reserved */
/* R1541 (0x605) - DAC2 Right Mixer Routing
*/
-#define WM8994_AIF1DAC1R_TO_DAC2R_ENA (1 << 0) /* Bit 0: Enable AIF1(Timeslot 0, Right) to DAC2R */
-#define WM8994_AIF1DAC2R_TO_DAC2R_ENA (1 << 1) /* Bit 1: Enable AIF1(Timeslot 1, Right) to DAC2R */
-#define WM8994_AIF2DACR_TO_DAC2R_ENA (1 << 2) /* Bit 2: Enable AIF2(Right) to DAC2R */
- /* Bit 3: Reserved */
-#define WM8994_ADCL_TO_DAC2R_ENA (1 << 4) /* Bit 4: Enable Sidetone STL to DAC2R */
-#define WM8994_ADCR_TO_DAC2R_ENA (1 << 5) /* Bit 5: Enable Sidetone STR to DAC2R */
- /* Bits 6-15: Reserved */
+#define WM8994_AIF1DAC1R_TO_DAC2R_ENA (1 << 0) /* Bit 0: Enable AIF1(Timeslot 0, Right) to DAC2R */
+#define WM8994_AIF1DAC2R_TO_DAC2R_ENA (1 << 1) /* Bit 1: Enable AIF1(Timeslot 1, Right) to DAC2R */
+#define WM8994_AIF2DACR_TO_DAC2R_ENA (1 << 2) /* Bit 2: Enable AIF2(Right) to DAC2R */
+ /* Bit 3: Reserved */
+#define WM8994_ADCL_TO_DAC2R_ENA (1 << 4) /* Bit 4: Enable Sidetone STL to DAC2R */
+#define WM8994_ADCR_TO_DAC2R_ENA (1 << 5) /* Bit 5: Enable Sidetone STR to DAC2R */
+ /* Bits 6-15: Reserved */
/* R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
*/
@@ -1462,15 +1677,41 @@
/* R1552 (0x610) - DAC1 Left Volume
*/
+#define WM8994_DAC1L_MUTE (1 << 9) /* Bit 9: DAC1L Soft Mute Control */
+#define WM8994_DAC1L_MUTE_UNMUTE (0) /* DAC Un-mute */
+#define WM8994_DAC1L_MUTE_MUTE (WM8994_DAC1L_MUTE) /* DAC Mute */
+#define WM8994_DAC1_VU (1 << 8) /* Bit 8: DAC1L and DAC1R Volume Update */
+#define WM8994_DAC1L_VOL_SHIFT (0) /* Bits 0-7: DAC1L Digital Volume */
+#define WM8994_DAC1L_VOL_MASK (0xFF << WM8994_DAC1L_VOL_SHIFT)
+
/* R1553 (0x611) - DAC1 Right Volume
*/
+#define WM8994_DAC1R_MUTE (1 << 9) /* Bit 9: DAC1R Soft Mute Control */
+#define WM8994_DAC1R_MUTE_UNMUTE (0) /* DAC Un-mute */
+#define WM8994_DAC1R_MUTE_MUTE (WM8994_DAC1L_MUTE) /* DAC Mute */
+#define WM8994_DAC1R_VOL_SHIFT (0) /* Bits 0-7: DAC1R Digital Volume */
+#define WM8994_DAC1R_VOL_MASK (0xFF << WM8994_DAC1R_VOL_SHIFT)
+
/* R1554 (0x612) - DAC2 Left Volume
*/
+#define WM8994_DAC2L_MUTE (1 << 9) /* Bit 9: DAC2L Soft Mute Control */
+#define WM8994_DAC2L_MUTE_UNMUTE (0) /* DAC Un-mute */
+#define WM8994_DAC2L_MUTE_MUTE (WM8994_DAC2L_MUTE) /* DAC Mute */
+#define WM8994_DAC2_VU (1 << 8) /* Bit 8: DAC2L and DAC2R Volume Update */
+#define WM8994_DAC2L_VOL_SHIFT (0) /* Bits 0-7: DAC2L Digital Volume */
+#define WM8994_DAC2L_VOL_MASK (0xFF << WM8994_DAC2L_VOL_SHIFT)
+
/* R1555 (0x613) - DAC2 Right Volume
*/
+#define WM8994_DAC2R_MUTE (1 << 9) /* Bit 9: DAC2R Soft Mute Control */
+#define WM8994_DAC2R_MUTE_UNMUTE (0) /* DAC Un-mute */
+#define WM8994_DAC2R_MUTE_MUTE (WM8994_DAC2R_MUTE) /* DAC Mute */
+#define WM8994_DAC2R_VOL_SHIFT (0) /* Bits 0-7: DAC2R Digital Volume */
+#define WM8994_DAC2R_VOL_MASK (0xFF << WM8994_DAC2R_VOL_SHIFT)
+
/* R1556 (0x614) - DAC Softmute
*/
@@ -1539,6 +1780,9 @@
#define WM8994_BCLK_MAXDIV 30
#define WM8994_NFLLRATIO 30
+#define WM8994_FRAMELEN8 16 /* Bits per frame for 8-bit data */
+#define WM8994_FRAMELEN16 32 /* Bits per frame for 16-bit data */
+
/* Commonly defined and redefined macros */
#ifndef MIN