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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/07/09 15:37:40 UTC
[incubator-nuttx] 01/02: arch/stm32f0l0g0: add support for stm32l053
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit b179c46178123df5490239ca7e17d3a47bf3398b
Author: raiden00pl <ra...@railab.me>
AuthorDate: Thu Jul 7 19:19:06 2022 +0200
arch/stm32f0l0g0: add support for stm32l053
---
arch/arm/include/stm32f0l0g0/chip.h | 52 +++++++++++++++++++++++++++++++++++++
arch/arm/src/stm32f0l0g0/Kconfig | 14 ++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h
index 3e34932593..31d9f78db9 100644
--- a/arch/arm/include/stm32f0l0g0/chip.h
+++ b/arch/arm/include/stm32f0l0g0/chip.h
@@ -320,6 +320,58 @@
# define STM32_NCAP 0 /* 0 Capacitive sensing channels */
# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
+#elif defined(CONFIG_ARCH_CHIP_STM32L053C8)
+# define STM32_NATIM 0 /* No advanced timers */
+# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3
+ * (with DMA) and TIM22 without DMA */
+# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
+# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */
+ /* 1 LPTIMER */
+# define STM32_NSPI 2 /* 2 SPI modules SPI1 */
+# define STM32_NI2S 1 /* 1 I2S module */
+# define STM32_NI2C 2 /* 2 I2C */
+# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
+# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */
+ /* 1 LPUART */
+# define STM32_NCAN 0 /* 0 CAN controllers */
+# define STM32_NLCD 1 /* 1 LCD */
+# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */
+# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
+# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
+# define STM32_NADC 1 /* One 12-bit module */
+# define STM32_NDAC 0 /* 0 DAC channel */
+# define STM32_NCOMP 2 /* 2 Analog Comparators */
+# define STM32_NCRC 0 /* 0 CRC module */
+# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
+# define STM32_NCAP 24 /* 24 Capacitive sensing channels */
+# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32L053R8)
+# define STM32_NATIM 0 /* No advanced timers */
+# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3
+ * (with DMA) and TIM22 without DMA */
+# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */
+# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */
+ /* 1 LPTIMER */
+# define STM32_NSPI 2 /* 2 SPI modules SPI1 */
+# define STM32_NI2S 1 /* 1 I2S module */
+# define STM32_NI2C 2 /* 2 I2C */
+# define STM32_NDMA 1 /* 1 DMA1, 7-channels */
+# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */
+ /* 1 LPUART */
+# define STM32_NCAN 0 /* 0 CAN controllers */
+# define STM32_NLCD 1 /* 1 LCD */
+# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */
+# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */
+# define STM32_NCEC 0 /* 0 HDMI-CEC controller */
+# define STM32_NADC 1 /* One 12-bit module */
+# define STM32_NDAC 0 /* 0 DAC channel */
+# define STM32_NCOMP 2 /* 2 Analog Comparators */
+# define STM32_NCRC 0 /* 0 CRC module */
+# define STM32_NRNG 0 /* 0 Random number generator (RNG) */
+# define STM32_NCAP 24 /* 24 Capacitive sensing channels */
+# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
+
#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \
defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \
defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \
diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig
index 0d69e29634..9e18961dd1 100644
--- a/arch/arm/src/stm32f0l0g0/Kconfig
+++ b/arch/arm/src/stm32f0l0g0/Kconfig
@@ -530,6 +530,16 @@ config ARCH_CHIP_STM32G071RB
select STM32F0L0G0_STM32G0
depends on ARCH_CHIP_STM32G0
+config ARCH_CHIP_STM32L053C8
+ bool "STM32L053C8"
+ select ARCH_CHIP_STM32L053XX
+ depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L053R8
+ bool "STM32L053R8"
+ select ARCH_CHIP_STM32L053XX
+ depends on ARCH_CHIP_STM32L0
+
config ARCH_CHIP_STM32L071K8
bool "STM32L071K8"
select ARCH_CHIP_STM32L071XX
@@ -878,6 +888,10 @@ config STM32F0L0G0_ENERGYLITE
bool
default n
+config ARCH_CHIP_STM32L053XX
+ bool
+ select STM32F0L0G0_STM32L0
+
config ARCH_CHIP_STM32L071XX
bool
select STM32F0L0G0_STM32L0