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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2022/04/25 04:05:35 UTC

[GitHub] [tvm] Hzfengsy commented on a diff in pull request #11110: [TIR] Get read/write access precisely for opaque access.

Hzfengsy commented on code in PR #11110:
URL: https://github.com/apache/tvm/pull/11110#discussion_r857244593


##########
tests/python/unittest/test_tir_schedule_compute_inline.py:
##########
@@ -185,7 +185,7 @@ def opaque_access_load(a: T.handle, c: T.handle) -> None:
             T.writes(C[0:128, 0:128])
             T.evaluate(
                 T.tvm_access_ptr(
-                    T.type_annotation(dtype="float32"), B.data, 0, 128, "r", dtype="handle"
+                    T.type_annotation(dtype="float32"), B.data, 0, 128, 1, dtype="handle"

Review Comment:
   It would be great if we could also handle `"r"` and `"w"` for better readability



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