You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by ut...@apache.org on 2018/04/18 21:56:24 UTC
[mynewt-core] 01/13: Comment on nucleo-f401 i2c usage
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit a9e286f0a6abce2cbf440fb84bac57f7a81ae762
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Wed Mar 21 17:07:39 2018 -0300
Comment on nucleo-f401 i2c usage
---
hw/bsp/nucleo-f401re/src/hal_bsp.c | 30 ++++++++++++++++++------------
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/hw/bsp/nucleo-f401re/src/hal_bsp.c b/hw/bsp/nucleo-f401re/src/hal_bsp.c
index d86d7e7..60640bc 100644
--- a/hw/bsp/nucleo-f401re/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f401re/src/hal_bsp.c
@@ -49,10 +49,10 @@ static const struct stm32f4_uart_cfg uart_cfg[UART_CNT] = {
.suc_uart = USART2,
.suc_rcc_reg = &RCC->APB1ENR,
.suc_rcc_dev = RCC_APB1ENR_USART2EN,
- .suc_pin_tx = MCU_GPIO_PORTA(2), /* PA2 */
- .suc_pin_rx = MCU_GPIO_PORTA(3), /* PA3 */
- .suc_pin_rts = MCU_GPIO_PORTA(1), /* PA1 */
- .suc_pin_cts = MCU_GPIO_PORTA(0), /* PA0 */
+ .suc_pin_tx = MCU_GPIO_PORTA(2), /* PA2 */
+ .suc_pin_rx = MCU_GPIO_PORTA(3), /* PA3 */
+ .suc_pin_rts = MCU_GPIO_PORTA(1), /* PA1 */
+ .suc_pin_cts = MCU_GPIO_PORTA(0), /* PA0 */
.suc_pin_af = GPIO_AF7_USART2,
.suc_irqn = USART2_IRQn
}
@@ -67,24 +67,30 @@ static const struct hal_bsp_mem_dump dump_cfg[] = {
};
#if MYNEWT_VAL(I2C_0)
+/*
+ * The PB8 and PB9 pins are connected through jumpers in the board to
+ * both AIN and I2C pins. To enable I2C functionality SB51/SB56 need to
+ * be removed (they are the default connections) and SB46/SB52 need to
+ * be added.
+ */
static struct stm32f4_hal_i2c_cfg i2c_cfg0 = {
.hic_i2c = I2C1,
.hic_rcc_reg = &RCC->APB1ENR,
.hic_rcc_dev = RCC_APB1ENR_I2C1EN,
- .hic_pin_sda = MCU_GPIO_PORTB(9), /* PB9 */
- .hic_pin_scl = MCU_GPIO_PORTB(8), /* PB8 */
+ .hic_pin_sda = MCU_GPIO_PORTB(9), /* PB9 - D14 on CN5 */
+ .hic_pin_scl = MCU_GPIO_PORTB(8), /* PB8 - D15 on CN5 */
.hic_pin_af = GPIO_AF4_I2C1,
.hic_10bit = 0,
- .hic_speed = 100000 /* 100kHz */
+ .hic_speed = 100000, /* 100kHz */
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_0_MASTER)
-struct stm32_hal_spi_cfg spi0_cfg = {
- .ss_pin = MCU_GPIO_PORTA(4), /* PA4 */
- .sck_pin = MCU_GPIO_PORTA(5), /* PA5 */
- .miso_pin = MCU_GPIO_PORTA(6), /* PA6 */
- .mosi_pin = MCU_GPIO_PORTA(7), /* PA7 */
+struct stm32f4_hal_spi_cfg spi0_cfg = {
+ .ss_pin = MCU_GPIO_PORTA(4), /* PA4 */
+ .sck_pin = MCU_GPIO_PORTA(5), /* PA5 */
+ .miso_pin = MCU_GPIO_PORTA(6), /* PA6 */
+ .mosi_pin = MCU_GPIO_PORTB(5), /* PB5 */
.irq_prio = 2
};
#endif
--
To stop receiving notification emails like this one, please contact
utzig@apache.org.