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Posted to commits@nuttx.apache.org by xi...@apache.org on 2021/04/13 04:20:27 UTC
[incubator-nuttx] branch master updated (0d1d42e -> 3f6bb76)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 0d1d42e boards: spresense: Update defconfigs for rndis and rndis_smp
new ea36c2c Remove MPU_RASR_S bit from stm32f7 MPU user mode intsram configration
new 3f6bb76 arch/arm/src/stm32f7/stm32_allocateheap.c: Fix MPU alignments
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Summary of changes:
arch/arm/src/stm32/stm32_allocateheap.c | 2 --
arch/arm/src/stm32f7/stm32_allocateheap.c | 45 +++++++++++++------------------
arch/arm/src/stm32f7/stm32_mpuinit.c | 32 +++++++++++++++++++---
3 files changed, 48 insertions(+), 31 deletions(-)
[incubator-nuttx] 01/02: Remove MPU_RASR_S bit from stm32f7 MPU
user mode intsram configration
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit ea36c2c7eaa5c020e65c6f3462a5f485f2449eef
Author: Jukka Laitinen <ju...@ssrc.tii.ae>
AuthorDate: Mon Jan 25 11:51:06 2021 +0200
Remove MPU_RASR_S bit from stm32f7 MPU user mode intsram configration
For some reason, setting the "shareable" bit makes the SRAM not writable
Signed-off-by: Jukka Laitinen <ju...@ssrc.tii.ae>
---
arch/arm/src/stm32f7/stm32_mpuinit.c | 32 +++++++++++++++++++++++++++++---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/stm32f7/stm32_mpuinit.c b/arch/arm/src/stm32f7/stm32_mpuinit.c
index 28e6732..f0564cb 100644
--- a/arch/arm/src/stm32f7/stm32_mpuinit.c
+++ b/arch/arm/src/stm32f7/stm32_mpuinit.c
@@ -70,12 +70,25 @@ void stm32_mpuinitialize(void)
mpu_showtype();
- /* Configure user flash and SRAM space */
+ /* Configure user flash space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
- mpu_user_intsram(datastart, dataend - datastart);
+ /* Configure user SRAM space
+ * Ordered
+ * Cacheable
+ * Not Bufferable
+ * Not Shareable
+ * P:RW U:RW
+ * Instruction access
+ */
+
+ mpu_configure_region(datastart, dataend - datastart,
+ MPU_RASR_TEX_SO |
+ MPU_RASR_C |
+ MPU_RASR_AP_RWRW
+ );
/* Then enable the MPU */
@@ -94,7 +107,20 @@ void stm32_mpuinitialize(void)
void stm32_mpu_uheap(uintptr_t start, size_t size)
{
- mpu_user_intsram(start, size);
+ /* Configure the user SRAM space
+ * Ordered
+ * Cacheable
+ * Not Bufferable
+ * Not Shareable
+ * P:RW U:RW
+ * Instruction access
+ */
+
+ mpu_configure_region(start, size,
+ MPU_RASR_TEX_SO |
+ MPU_RASR_C |
+ MPU_RASR_AP_RWRW
+ );
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */
[incubator-nuttx] 02/02: arch/arm/src/stm32f7/stm32_allocateheap.c:
Fix MPU alignments
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 3f6bb76e01b356bc9d7852fe2b900d367e3deea9
Author: Jukka Laitinen <ju...@ssrc.tii.ae>
AuthorDate: Fri Feb 5 16:41:25 2021 +0200
arch/arm/src/stm32f7/stm32_allocateheap.c: Fix MPU alignments
Change the logic for allocating user heap for PROTECTED_BUILD:
- Don't rely on SRAM1_END alignment
- Make better use of MPU subregions when allocating the heap
- Don't duplicate the calculation of user heap start in kernel heap
allocation; use the previous calculation directly
Signed-off-by: Jukka Laitinen <ju...@ssrc.tii.ae>
---
arch/arm/src/stm32/stm32_allocateheap.c | 2 --
arch/arm/src/stm32f7/stm32_allocateheap.c | 45 +++++++++++++------------------
2 files changed, 19 insertions(+), 28 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c
index 9d56750..eeb0f0f 100644
--- a/arch/arm/src/stm32/stm32_allocateheap.c
+++ b/arch/arm/src/stm32/stm32_allocateheap.c
@@ -677,7 +677,6 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
*/
log2 = (int)mpu_log2regionfloor(usize);
- DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = SRAM1_END - usize;
@@ -740,7 +739,6 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
*/
log2 = (int)mpu_log2regionfloor(usize);
- DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = SRAM1_END - usize;
diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c
index 3757eb2..df9705b 100644
--- a/arch/arm/src/stm32f7/stm32_allocateheap.c
+++ b/arch/arm/src/stm32f7/stm32_allocateheap.c
@@ -273,20 +273,29 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
+ size_t subreg_mask;
int log2;
- DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
-
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
- log2 = (int)mpu_log2regionfloor(usize);
- DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
+ /* align the ubase initially to a suitable mpu subregion start */
+
+ log2 = (int)mpu_log2regionceil(usize);
+ subreg_mask = (1 << log2) / 8 - 1;
+ if (ubase & subreg_mask)
+ {
+ ubase = (ubase | subreg_mask) + 1;
+ }
+
+ DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
+
+ /* reset the size to fit in SRAM and align down to subregion size */
- usize = (1 << log2);
- ubase = SRAM1_END - usize;
+ usize = SRAM1_END - ubase;
+ usize &= ~subreg_mask;
/* Return the user-space heap settings */
@@ -328,35 +337,19 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
{
- /* Get the unaligned size and position of the user-space heap.
- * This heap begins after the user-space .bss section at an offset
- * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+ /* User heap was just initialized, with proper MPU alignment, in nx_start,
+ * store the user heap start address
*/
- uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
- CONFIG_MM_KERNEL_HEAPSIZE;
- size_t usize = SRAM1_END - ubase;
- int log2;
-
+ uintptr_t ubase = (uintptr_t)*heap_start;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
- /* Adjust that size to account for MPU alignment requirements.
- * NOTE that there is an implicit assumption that the SRAM1_END
- * is aligned to the MPU requirement.
- */
-
- log2 = (int)mpu_log2regionfloor(usize);
- DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
-
- usize = (1 << log2);
- ubase = SRAM1_END - usize;
-
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void *)USERSPACE->us_bssend;
- *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
+ *heap_size = ubase - USERSPACE->us_bssend;
}
#endif