You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/07/23 19:51:04 UTC
[GitHub] [incubator-nuttx] acassis commented on a diff in pull request #6692: stm32f0l0g0: fixes for SPI half duplex
acassis commented on code in PR #6692:
URL: https://github.com/apache/incubator-nuttx/pull/6692#discussion_r928158975
##########
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h:
##########
@@ -96,42 +96,6 @@
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
-#if STM32_NSPI > 3
-# define STM32_SPI4_CR1 (STM32_SPI4_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI4_CR2 (STM32_SPI4_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI4_SR (STM32_SPI4_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI4_DR (STM32_SPI4_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI4_CRCPR (STM32_SPI4_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI4_I2SPR (STM32_SPI4_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 4
-# define STM32_SPI5_CR1 (STM32_SPI5_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI5_CR2 (STM32_SPI5_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI5_SR (STM32_SPI5_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI5_DR (STM32_SPI5_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI5_CRCPR (STM32_SPI5_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI5_I2SPR (STM32_SPI5_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 5
-# define STM32_SPI6_CR1 (STM32_SPI6_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI6_CR2 (STM32_SPI6_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI6_SR (STM32_SPI6_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI6_DR (STM32_SPI6_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI6_CRCPR (STM32_SPI6_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI6_I2SPR (STM32_SPI6_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
Review Comment:
@raiden00pl are you sure none STM32L0xx, STM32F0xx, STM32L0xx, STM32G0xx have SPI4/5/6 ?
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org