[GitHub] [incubator-tvm] cbalint13 commented on a change in pull request #6714: More flexible conv2d_NCHWc_int8 generic operator.

[GitBox <gi...@apache.org>]

cbalint13 commented on a change in pull request #6714:
URL: https://github.com/apache/incubator-tvm/pull/6714#discussion_r514604768



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File path: python/tvm/topi/generic/conv2d.py
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@@ -51,7 +51,7 @@ def fallback_schedule_cpu_common_int8(cfg, wkl, int32_lanes, num_int8_elements):
         num_int8_elements,
     )
 
-    oc_bn = int32_lanes
+    oc_bn = int32_lanes if int32_lanes >= num_int8_elements else num_int8_elements

Review comment:
       @giuseros,
   
   It is "vector size" of a specific machine, but can vary from "machine" to "machine".
   
   * From HW point ```lanes``` are registers (N x 32bit) where data products ```num_int8``` accumulates after multiplications.
   * I.E. case of ARM & Intel, the design is: 16 lanes (16 registers) where 4 multiplies (instant ones) accumulates into each.
   
   Now e.g. MARLANN uses 2 lanes, each one accumulating 8 multiplies, see: [ISA](https://github.com/SymbioticEDA/MARLANN/blob/master/docs/isa.md)
   Furthermore, working on a more generic HW accelerator where design may be parametrizable: ```lanes```, ```macs```.
   
   **Goal:** would like to reuse existing TVM routines as templates, but without the hard coded lanes/macs .
   
   




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