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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/05/01 02:49:22 UTC
[incubator-nuttx] branch master updated: arch/risc-v/src: Rename
files starting by up_ to risc_ to conform to the naming standard.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 21302fc arch/risc-v/src: Rename files starting by up_ to risc_ to conform to the naming standard.
21302fc is described below
commit 21302fcdaec44524eae5f9ac3e8c250b38236ebe
Author: Ouss4 <ab...@gmail.com>
AuthorDate: Thu Apr 30 23:53:05 2020 +0100
arch/risc-v/src: Rename files starting by up_ to risc_ to conform to the
naming standard.
---
.../{up_allocateheap.c => riscv_allocateheap.c} | 6 +-
arch/risc-v/src/common/{up_arch.h => riscv_arch.h} | 2 +-
.../common/{up_checkstack.c => riscv_checkstack.c} | 4 +-
.../{up_createstack.c => riscv_createstack.c} | 6 +-
arch/risc-v/src/common/{up_exit.c => riscv_exit.c} | 4 +-
arch/risc-v/src/common/{up_idle.c => riscv_idle.c} | 22 +++----
.../common/{up_initialize.c => riscv_initialize.c} | 6 +-
.../src/common/{up_internal.h => riscv_internal.h} | 2 +-
...interruptcontext.c => riscv_interruptcontext.c} | 4 +-
.../src/common/{up_mdelay.c => riscv_mdelay.c} | 2 +-
.../{up_modifyreg32.c => riscv_modifyreg32.c} | 4 +-
.../{up_pthread_start.c => riscv_pthread_start.c} | 4 +-
arch/risc-v/src/common/{up_puts.c => riscv_puts.c} | 4 +-
.../{up_releasestack.c => riscv_releasestack.c} | 4 +-
.../common/{up_stackframe.c => riscv_stackframe.c} | 4 +-
.../common/{up_task_start.c => riscv_task_start.c} | 4 +-
.../src/common/{up_udelay.c => riscv_udelay.c} | 2 +-
.../src/common/{up_usestack.c => riscv_usestack.c} | 4 +-
arch/risc-v/src/fe310/Make.defs | 20 +++----
arch/risc-v/src/fe310/fe310.h | 2 +-
arch/risc-v/src/fe310/fe310_clockconfig.c | 2 +-
arch/risc-v/src/fe310/fe310_gpio.c | 2 +-
arch/risc-v/src/fe310/fe310_gpio.h | 4 +-
arch/risc-v/src/fe310/fe310_idle.c | 2 +-
arch/risc-v/src/fe310/fe310_irq.c | 6 +-
arch/risc-v/src/fe310/fe310_irq_dispatch.c | 4 +-
arch/risc-v/src/fe310/fe310_lowputc.c | 4 +-
...hedulesigaction.c => fe310_schedulesigaction.c} | 6 +-
arch/risc-v/src/fe310/fe310_serial.c | 8 +--
arch/risc-v/src/fe310/fe310_timerisr.c | 2 +-
arch/risc-v/src/gap8/Make.defs | 18 +++---
arch/risc-v/src/gap8/gap8_allocateheap.c | 13 +++--
.../src/gap8/{startup_gap8.S => gap8_head.S} | 2 +-
arch/risc-v/src/gap8/gap8_idle.c | 2 +-
arch/risc-v/src/gap8/gap8_schedulesigaction.c | 4 +-
arch/risc-v/src/k210/Make.defs | 26 ++++-----
arch/risc-v/src/k210/k210.h | 2 +-
arch/risc-v/src/k210/k210_clockconfig.c | 2 +-
arch/risc-v/src/k210/k210_cpuidlestack.c | 2 +-
arch/risc-v/src/k210/k210_cpuindex.c | 2 +-
arch/risc-v/src/k210/k210_cpupause.c | 4 +-
arch/risc-v/src/k210/k210_cpustart.c | 4 +-
arch/risc-v/src/k210/k210_idle.c | 2 +-
arch/risc-v/src/k210/k210_irq.c | 4 +-
arch/risc-v/src/k210/k210_irq_dispatch.c | 4 +-
arch/risc-v/src/k210/k210_lowputc.c | 4 +-
...chedulesigaction.c => k210_schedulesigaction.c} | 6 +-
arch/risc-v/src/k210/k210_serial.c | 8 +--
arch/risc-v/src/k210/k210_start.c | 2 +-
arch/risc-v/src/k210/k210_timerisr.c | 2 +-
arch/risc-v/src/litex/Make.defs | 20 +++----
arch/risc-v/src/litex/litex.h | 2 +-
arch/risc-v/src/litex/litex_clockconfig.c | 2 +-
arch/risc-v/src/litex/litex_idle.c | 2 +-
arch/risc-v/src/litex/litex_irq.c | 4 +-
arch/risc-v/src/litex/litex_irq_dispatch.c | 4 +-
arch/risc-v/src/litex/litex_lowputc.c | 4 +-
...hedulesigaction.c => litex_schedulesigaction.c} | 6 +-
arch/risc-v/src/litex/litex_serial.c | 4 +-
arch/risc-v/src/litex/litex_timerisr.c | 2 +-
arch/risc-v/src/nr5m100/Make.defs | 16 +++---
arch/risc-v/src/nr5m100/nr5.h | 10 ++--
arch/risc-v/src/nr5m100/nr5_irq_dispatch.c | 62 ++++++++++----------
arch/risc-v/src/nr5m100/nr5_lowputc.c | 20 ++++---
...schedulesigaction.c => nr5_schedulesigaction.c} | 6 +-
arch/risc-v/src/nr5m100/nr5_serial.c | 67 +++++++++++++---------
arch/risc-v/src/nr5m100/nr5_timer.c | 15 +++--
arch/risc-v/src/nr5m100/nr5_timerisr.c | 2 +-
.../src/rv32im/{up_assert.c => riscv_assert.c} | 59 ++++++++++---------
.../rv32im/{up_blocktask.c => riscv_blocktask.c} | 2 +-
.../rv32im/{up_copystate.c => riscv_copystate.c} | 2 +-
.../src/rv32im/{up_doirq.c => riscv_doirq.c} | 8 +--
arch/risc-v/src/rv32im/{up_fpu.S => riscv_fpu.S} | 0
.../{up_initialstate.c => riscv_initialstate.c} | 4 +-
...{up_releasepending.c => riscv_releasepending.c} | 3 +-
...p_reprioritizertr.c => riscv_reprioritizertr.c} | 6 +-
.../rv32im/{up_sigdeliver.c => riscv_sigdeliver.c} | 7 ++-
.../src/rv32im/{up_swint.c => riscv_swint.c} | 51 +++++++++-------
.../src/rv32im/{up_syscall.S => riscv_syscall.S} | 0
.../{up_unblocktask.c => riscv_unblocktask.c} | 2 +-
.../src/rv32im/{up_vfork.c => riscv_vfork.c} | 11 ++--
.../src/rv32im/{up_vfork.h => riscv_vfork.h} | 10 ++--
.../src/rv64gc/{up_assert.c => riscv_assert.c} | 4 +-
.../rv64gc/{up_blocktask.c => riscv_blocktask.c} | 2 +-
.../rv64gc/{up_copystate.c => riscv_copystate.c} | 2 +-
.../src/rv64gc/{up_fault.c => riscv_fault.c} | 4 +-
.../{up_initialstate.c => riscv_initialstate.c} | 4 +-
...{up_releasepending.c => riscv_releasepending.c} | 2 +-
...p_reprioritizertr.c => riscv_reprioritizertr.c} | 4 +-
.../rv64gc/{up_sigdeliver.c => riscv_sigdeliver.c} | 4 +-
...p_signal_dispatch.c => riscv_signal_dispatch.c} | 2 +-
...{up_signal_handler.S => riscv_signal_handler.S} | 0
.../src/rv64gc/{up_swint.c => riscv_swint.c} | 20 ++++---
.../src/rv64gc/{up_testset.S => riscv_testset.S} | 0
.../{up_unblocktask.c => riscv_unblocktask.c} | 2 +-
95 files changed, 382 insertions(+), 344 deletions(-)
diff --git a/arch/risc-v/src/common/up_allocateheap.c b/arch/risc-v/src/common/riscv_allocateheap.c
similarity index 97%
rename from arch/risc-v/src/common/up_allocateheap.c
rename to arch/risc-v/src/common/riscv_allocateheap.c
index 002c853..f71c4b9 100644
--- a/arch/risc-v/src/common/up_allocateheap.c
+++ b/arch/risc-v/src/common/riscv_allocateheap.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_allocateheap.c
+ * arch/risc-v/src/common/riscv_allocateheap.c
*
* Copyright (C) 2010, 2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -46,8 +46,8 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/risc-v/src/common/up_arch.h b/arch/risc-v/src/common/riscv_arch.h
similarity index 98%
rename from arch/risc-v/src/common/up_arch.h
rename to arch/risc-v/src/common/riscv_arch.h
index 8720fdf..6d8fe8e 100644
--- a/arch/risc-v/src/common/up_arch.h
+++ b/arch/risc-v/src/common/riscv_arch.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_arch.h
+ * arch/risc-v/src/common/riscv_arch.h
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
diff --git a/arch/risc-v/src/common/up_checkstack.c b/arch/risc-v/src/common/riscv_checkstack.c
similarity index 98%
rename from arch/risc-v/src/common/up_checkstack.c
rename to arch/risc-v/src/common/riscv_checkstack.c
index f76d34a..3c87d67 100644
--- a/arch/risc-v/src/common/up_checkstack.c
+++ b/arch/risc-v/src/common/riscv_checkstack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_checkstack.c
+ * arch/risc-v/src/common/riscv_checkstack.c
*
* Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -50,7 +50,7 @@
#include <nuttx/board.h>
#include "sched/sched.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
#ifdef CONFIG_STACK_COLORATION
diff --git a/arch/risc-v/src/common/up_createstack.c b/arch/risc-v/src/common/riscv_createstack.c
similarity index 98%
rename from arch/risc-v/src/common/up_createstack.c
rename to arch/risc-v/src/common/riscv_createstack.c
index 5da7c59..b8c09ca 100644
--- a/arch/risc-v/src/common/up_createstack.c
+++ b/arch/risc-v/src/common/riscv_createstack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/riscv/src/common/up_createstack.c
+ * arch/riscv/src/common/riscv_createstack.c
*
* Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -49,8 +49,8 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Macros
diff --git a/arch/risc-v/src/common/up_exit.c b/arch/risc-v/src/common/riscv_exit.c
similarity index 98%
rename from arch/risc-v/src/common/up_exit.c
rename to arch/risc-v/src/common/riscv_exit.c
index 19334fd..59d8799 100644
--- a/arch/risc-v/src/common/up_exit.c
+++ b/arch/risc-v/src/common/riscv_exit.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_exit.c
+ * arch/risc-v/src/common/riscv_exit.c
*
* Copyright (C) 2011, 2013-2014, 2017-2018 Gregory Nutt. All rights
* reserved.
@@ -54,7 +54,7 @@
#include "task/task.h"
#include "sched/sched.h"
#include "group/group.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/risc-v/src/common/up_idle.c b/arch/risc-v/src/common/riscv_idle.c
similarity index 82%
rename from arch/risc-v/src/common/up_idle.c
rename to arch/risc-v/src/common/riscv_idle.c
index e2fffe8..24aae0f 100644
--- a/arch/risc-v/src/common/up_idle.c
+++ b/arch/risc-v/src/common/riscv_idle.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_idle.c
+ * arch/risc-v/src/common/riscv_idle.c
*
* Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -41,7 +41,7 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
@@ -74,17 +74,13 @@ void up_idle(void)
* sleep in a reduced power mode until an interrupt occurs to save power
*/
- /* This is a kludge that I still don't understand. The call to kmm_trysemaphore()
- * in the nx_start.c IDLE loop seems necessary for the good health of the IDLE
- * loop. When the work queue is enabled, this logic is removed from the IDLE
- * loop and it appears that we are somehow left idling with interrupts non-
- * functional. The following should be no-op, it just disables then re-enables
- * interrupts. But it fixes the problem and will stay here until I understand
- * the problem/fix better.
- *
- * And no, the contents of the CP0 status register are not incorrect. But for
- * some reason the status register needs to be re-written again on this thread
- * for it to take effect. This might be a PIC32-only issue?
+ /* This is a kludge that I still don't understand. The call to
+ * kmm_trysemaphore() in the nx_start.c IDLE loop seems necessary for the
+ * good health of the IDLE loop. When the work queue is enabled, this
+ * logic is removed from the IDLE loop and it appears that we are somehow
+ * left idling with interrupts non-functional. The following should be
+ * no-op, it just disables then re-enables interrupts. But it fixes the
+ * problem and will stay here until I understand the problem/fix better.
*/
#ifdef CONFIG_SCHED_WORKQUEUE
diff --git a/arch/risc-v/src/common/up_initialize.c b/arch/risc-v/src/common/riscv_initialize.c
similarity index 98%
rename from arch/risc-v/src/common/up_initialize.c
rename to arch/risc-v/src/common/riscv_initialize.c
index 2aed49b..c21353f 100644
--- a/arch/risc-v/src/common/up_initialize.c
+++ b/arch/risc-v/src/common/riscv_initialize.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_initialize.c
+ * arch/risc-v/src/common/riscv_initialize.c
*
* Copyright (C) 2007-2010, 2012-2015, 2017 Gregory Nutt. All rights
* reserved.
@@ -51,8 +51,8 @@
#include <arch/board/board.h>
#include "sched/sched.h"
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
/****************************************************************************
* Private Functions
diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/riscv_internal.h
similarity index 99%
rename from arch/risc-v/src/common/up_internal.h
rename to arch/risc-v/src/common/riscv_internal.h
index 29dc0c0..0bc188a 100644
--- a/arch/risc-v/src/common/up_internal.h
+++ b/arch/risc-v/src/common/riscv_internal.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_internal.h
+ * arch/risc-v/src/common/riscv_internal.h
*
* Copyright (C) 2007-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
diff --git a/arch/risc-v/src/common/up_interruptcontext.c b/arch/risc-v/src/common/riscv_interruptcontext.c
similarity index 97%
rename from arch/risc-v/src/common/up_interruptcontext.c
rename to arch/risc-v/src/common/riscv_interruptcontext.c
index cdf69bf..c5980d7 100644
--- a/arch/risc-v/src/common/up_interruptcontext.c
+++ b/arch/risc-v/src/common/riscv_interruptcontext.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_interruptcontext.c
+ * arch/risc-v/src/common/riscv_interruptcontext.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -43,7 +43,7 @@
#include <nuttx/arch.h>
#include <nuttx/irq.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Private Types
diff --git a/arch/risc-v/src/common/up_mdelay.c b/arch/risc-v/src/common/riscv_mdelay.c
similarity index 98%
rename from arch/risc-v/src/common/up_mdelay.c
rename to arch/risc-v/src/common/riscv_mdelay.c
index 094592a..3efc011 100644
--- a/arch/risc-v/src/common/up_mdelay.c
+++ b/arch/risc-v/src/common/riscv_mdelay.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_mdelay.c
+ * arch/risc-v/src/common/riscv_mdelay.c
*
* Copyright (C) 2007, 2008, 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
diff --git a/arch/risc-v/src/common/up_modifyreg32.c b/arch/risc-v/src/common/riscv_modifyreg32.c
similarity index 97%
rename from arch/risc-v/src/common/up_modifyreg32.c
rename to arch/risc-v/src/common/riscv_modifyreg32.c
index 96f9fca..ee99893 100644
--- a/arch/risc-v/src/common/up_modifyreg32.c
+++ b/arch/risc-v/src/common/riscv_modifyreg32.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_modifyreg32.c
+ * arch/risc-v/src/common/riscv_modifyreg32.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -45,7 +45,7 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/common/up_pthread_start.c b/arch/risc-v/src/common/riscv_pthread_start.c
similarity index 97%
rename from arch/risc-v/src/common/up_pthread_start.c
rename to arch/risc-v/src/common/riscv_pthread_start.c
index 156a3c2..b27df8b 100644
--- a/arch/risc-v/src/common/up_pthread_start.c
+++ b/arch/risc-v/src/common/riscv_pthread_start.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_pthread_start.c
+ * arch/risc-v/src/common/riscv_pthread_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -27,7 +27,7 @@
#include <nuttx/arch.h>
#include "svcall.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_PTHREAD)
diff --git a/arch/risc-v/src/common/up_puts.c b/arch/risc-v/src/common/riscv_puts.c
similarity index 97%
rename from arch/risc-v/src/common/up_puts.c
rename to arch/risc-v/src/common/riscv_puts.c
index baba677..5e54626 100644
--- a/arch/risc-v/src/common/up_puts.c
+++ b/arch/risc-v/src/common/riscv_puts.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_puts.c
+ * arch/risc-v/src/common/riscv_puts.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -40,7 +40,7 @@
#include <nuttx/config.h>
#include <nuttx/arch.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/common/up_releasestack.c b/arch/risc-v/src/common/riscv_releasestack.c
similarity index 98%
rename from arch/risc-v/src/common/up_releasestack.c
rename to arch/risc-v/src/common/riscv_releasestack.c
index 137fae9..219062d 100644
--- a/arch/risc-v/src/common/up_releasestack.c
+++ b/arch/risc-v/src/common/riscv_releasestack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_releasestack.c
+ * arch/risc-v/src/common/riscv_releasestack.c
*
* Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -45,7 +45,7 @@
#include <nuttx/arch.h>
#include <nuttx/kmalloc.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Private Types
diff --git a/arch/risc-v/src/common/up_stackframe.c b/arch/risc-v/src/common/riscv_stackframe.c
similarity index 98%
rename from arch/risc-v/src/common/up_stackframe.c
rename to arch/risc-v/src/common/riscv_stackframe.c
index fbc73a7..5478cad 100644
--- a/arch/risc-v/src/common/up_stackframe.c
+++ b/arch/risc-v/src/common/riscv_stackframe.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_stackframe.c
+ * arch/risc-v/src/common/riscv_stackframe.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -46,7 +46,7 @@
#include <nuttx/arch.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Macros
diff --git a/arch/risc-v/src/common/up_task_start.c b/arch/risc-v/src/common/riscv_task_start.c
similarity index 97%
rename from arch/risc-v/src/common/up_task_start.c
rename to arch/risc-v/src/common/riscv_task_start.c
index 48ff179..37b3252 100644
--- a/arch/risc-v/src/common/up_task_start.c
+++ b/arch/risc-v/src/common/riscv_task_start.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_task_start.c
+ * arch/risc-v/src/common/riscv_task_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -26,7 +26,7 @@
#include <nuttx/arch.h>
#include "svcall.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
#if defined(CONFIG_BUILD_PROTECTED) || defined(CONFIG_BUILD_KERNEL)
diff --git a/arch/risc-v/src/common/up_udelay.c b/arch/risc-v/src/common/riscv_udelay.c
similarity index 98%
rename from arch/risc-v/src/common/up_udelay.c
rename to arch/risc-v/src/common/riscv_udelay.c
index 7aec676..bf5905d 100644
--- a/arch/risc-v/src/common/up_udelay.c
+++ b/arch/risc-v/src/common/riscv_udelay.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_udelay.c
+ * arch/risc-v/src/common/riscv_udelay.c
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
diff --git a/arch/risc-v/src/common/up_usestack.c b/arch/risc-v/src/common/riscv_usestack.c
similarity index 98%
rename from arch/risc-v/src/common/up_usestack.c
rename to arch/risc-v/src/common/riscv_usestack.c
index 353fd38..ec033a2 100644
--- a/arch/risc-v/src/common/up_usestack.c
+++ b/arch/risc-v/src/common/riscv_usestack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/up_usestack.c
+ * arch/risc-v/src/common/riscv_usestack.c
*
* Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -47,7 +47,7 @@
#include <nuttx/kmalloc.h>
#include <nuttx/arch.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/risc-v/src/fe310/Make.defs b/arch/risc-v/src/fe310/Make.defs
index 5d1d41e..edebdac 100644
--- a/arch/risc-v/src/fe310/Make.defs
+++ b/arch/risc-v/src/fe310/Make.defs
@@ -35,23 +35,23 @@
HEAD_ASRC = fe310_vectors.S
# Specify our general Assembly files
-CHIP_ASRCS = fe310_head.S up_syscall.S
+CHIP_ASRCS = fe310_head.S riscv_syscall.S
# Specify C code within the common directory to be included
-CMN_CSRCS += up_initialize.c up_swint.c
-CMN_CSRCS += up_allocateheap.c up_createstack.c up_exit.c
-CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c
-CMN_CSRCS += up_interruptcontext.c up_modifyreg32.c up_puts.c up_mdelay.c
-CMN_CSRCS += up_releasepending.c up_reprioritizertr.c
-CMN_CSRCS += up_releasestack.c up_stackframe.c up_schedulesigaction.c
-CMN_CSRCS += up_sigdeliver.c up_udelay.c up_unblocktask.c up_usestack.c
+CMN_CSRCS += riscv_initialize.c riscv_swint.c
+CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
+CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
+CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
+CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
+CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c fe310_schedulesigaction.c
+CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c
ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += up_checkstack.c
+CMN_CSRCS += riscv_checkstack.c
endif
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_CSRCS += up_vfork.c
+CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included
diff --git a/arch/risc-v/src/fe310/fe310.h b/arch/risc-v/src/fe310/fe310.h
index 77aec61..e703442 100644
--- a/arch/risc-v/src/fe310/fe310.h
+++ b/arch/risc-v/src/fe310/fe310.h
@@ -46,7 +46,7 @@
#include <stdbool.h>
#include <arch/irq.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
#include "chip.h"
#include "fe310_lowputc.h"
diff --git a/arch/risc-v/src/fe310/fe310_clockconfig.c b/arch/risc-v/src/fe310/fe310_clockconfig.c
index 3568846..f328e32 100644
--- a/arch/risc-v/src/fe310/fe310_clockconfig.c
+++ b/arch/risc-v/src/fe310/fe310_clockconfig.c
@@ -46,7 +46,7 @@
#include <nuttx/arch.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "fe310_clockconfig.h"
/****************************************************************************
diff --git a/arch/risc-v/src/fe310/fe310_gpio.c b/arch/risc-v/src/fe310/fe310_gpio.c
index c990547..938fce5 100644
--- a/arch/risc-v/src/fe310/fe310_gpio.c
+++ b/arch/risc-v/src/fe310/fe310_gpio.c
@@ -46,7 +46,7 @@
#include <nuttx/arch.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "fe310_gpio.h"
#include "fe310_memorymap.h"
diff --git a/arch/risc-v/src/fe310/fe310_gpio.h b/arch/risc-v/src/fe310/fe310_gpio.h
index 95d05dc..4ec7e27 100644
--- a/arch/risc-v/src/fe310/fe310_gpio.h
+++ b/arch/risc-v/src/fe310/fe310_gpio.h
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <stdint.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
#include "chip.h"
/****************************************************************************
@@ -157,7 +157,7 @@
#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
/****************************************************************************
- * Public Functions
+ * Public Functions Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
diff --git a/arch/risc-v/src/fe310/fe310_idle.c b/arch/risc-v/src/fe310/fe310_idle.c
index 286456c..82f2405 100644
--- a/arch/risc-v/src/fe310/fe310_idle.c
+++ b/arch/risc-v/src/fe310/fe310_idle.c
@@ -45,7 +45,7 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c
index a2ad7ba..bbaac0e 100644
--- a/arch/risc-v/src/fe310/fe310_irq.c
+++ b/arch/risc-v/src/fe310/fe310_irq.c
@@ -48,8 +48,8 @@
#include <arch/irq.h>
#include <arch/board/board.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "fe310.h"
@@ -65,7 +65,7 @@ void up_irqinitialize(void)
{
/* Disable Machine interrupts */
- up_irq_save();
+ up_irq_save();
/* Disable all global interrupts */
diff --git a/arch/risc-v/src/fe310/fe310_irq_dispatch.c b/arch/risc-v/src/fe310/fe310_irq_dispatch.c
index e323023..0163450 100644
--- a/arch/risc-v/src/fe310/fe310_irq_dispatch.c
+++ b/arch/risc-v/src/fe310/fe310_irq_dispatch.c
@@ -44,8 +44,8 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "fe310_gpio.h"
#include "fe310.h"
diff --git a/arch/risc-v/src/fe310/fe310_lowputc.c b/arch/risc-v/src/fe310/fe310_lowputc.c
index fd79a52..b241eca 100644
--- a/arch/risc-v/src/fe310/fe310_lowputc.c
+++ b/arch/risc-v/src/fe310/fe310_lowputc.c
@@ -43,8 +43,8 @@
#include <arch/board/board.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "fe310_config.h"
#include "hardware/fe310_memorymap.h"
diff --git a/arch/risc-v/src/fe310/up_schedulesigaction.c b/arch/risc-v/src/fe310/fe310_schedulesigaction.c
similarity index 98%
rename from arch/risc-v/src/fe310/up_schedulesigaction.c
rename to arch/risc-v/src/fe310/fe310_schedulesigaction.c
index 10906c9..4beed8d 100644
--- a/arch/risc-v/src/fe310/up_schedulesigaction.c
+++ b/arch/risc-v/src/fe310/fe310_schedulesigaction.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/fe310/up_schedulesigaction.c
+ * arch/risc-v/src/fe310/fe310_schedulesigaction.c
*
* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
* Author: Masayuki Ishikawa <ma...@gmail.com>
@@ -50,8 +50,8 @@
#include <arch/fe310/irq.h>
#include "sched/sched.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/fe310/fe310_serial.c b/arch/risc-v/src/fe310/fe310_serial.c
index 394dc94..81c4bc5 100644
--- a/arch/risc-v/src/fe310/fe310_serial.c
+++ b/arch/risc-v/src/fe310/fe310_serial.c
@@ -53,8 +53,8 @@
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "fe310_config.h"
#include "chip.h"
@@ -309,7 +309,7 @@ static void up_shutdown(struct uart_dev_s *dev)
* Name: up_attach
*
* Description:
- * Configure the UART to operation in interrupt driven mode. This method is
+ * Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
@@ -348,7 +348,7 @@ static int up_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
- * closed normally just before the shutdown method is called. The exception
+ * closed normally just before the shutdown method is called. The exception
* is the serial console which is never shutdown.
*
****************************************************************************/
diff --git a/arch/risc-v/src/fe310/fe310_timerisr.c b/arch/risc-v/src/fe310/fe310_timerisr.c
index 0a4f18e..a888661 100644
--- a/arch/risc-v/src/fe310/fe310_timerisr.c
+++ b/arch/risc-v/src/fe310/fe310_timerisr.c
@@ -47,7 +47,7 @@
#include <nuttx/clock.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "fe310.h"
diff --git a/arch/risc-v/src/gap8/Make.defs b/arch/risc-v/src/gap8/Make.defs
index 04a676e..df49628 100644
--- a/arch/risc-v/src/gap8/Make.defs
+++ b/arch/risc-v/src/gap8/Make.defs
@@ -33,11 +33,11 @@
# Specify our HEAD assembly file. This will be linked as the first object
# file, so it will appear at address 0
-HEAD_ASRC = startup_gap8.S
+HEAD_ASRC = gap8_head.S
# Specify our general Assembly files
-CHIP_ASRCS = up_syscall.S
+CHIP_ASRCS = riscv_syscall.S
# Override the arch to enable hardware MUL during assembly.
# This is to support our hardware mul test. For that test,
@@ -50,15 +50,15 @@ ASARCHCPUFLAGS += -march=rv32imcxgap8 -mPE=8 -mFC=1 -D__riscv__ -D__pulp__ -D__G
# Specify C code within the common directory to be included
-CMN_CSRCS += up_initialize.c up_swint.c
-CMN_CSRCS += up_createstack.c up_exit.c
-CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c
-CMN_CSRCS += up_interruptcontext.c up_releasepending.c up_reprioritizertr.c
-CMN_CSRCS += up_releasestack.c up_stackframe.c up_sigdeliver.c
-CMN_CSRCS += up_unblocktask.c up_usestack.c
+CMN_CSRCS += riscv_initialize.c riscv_swint.c
+CMN_CSRCS += riscv_createstack.c riscv_exit.c
+CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
+CMN_CSRCS += riscv_interruptcontext.c riscv_releasepending.c riscv_reprioritizertr.c
+CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_sigdeliver.c
+CMN_CSRCS += riscv_unblocktask.c riscv_usestack.c
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_CSRCS += up_vfork.c
+CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included
diff --git a/arch/risc-v/src/gap8/gap8_allocateheap.c b/arch/risc-v/src/gap8/gap8_allocateheap.c
index 8b8dcda..687cbdb 100644
--- a/arch/risc-v/src/gap8/gap8_allocateheap.c
+++ b/arch/risc-v/src/gap8/gap8_allocateheap.c
@@ -46,8 +46,8 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
@@ -72,7 +72,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
/* These values come from GAP8.ld */
- extern uint8_t *_heap_start, *_heap_end;
+ extern uint8_t *_heap_start;
+ extern uint8_t *_heap_end;
uint32_t hstart = (uint32_t)&_heap_start;
uint32_t hend = (uint32_t)&_heap_end;
@@ -80,16 +81,16 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
*heap_size = hend - hstart;
}
-/************************************************************************************
+/****************************************************************************
* Name: up_addregion
*
* Description:
* RAM may be added in non-contiguous chunks. This routine adds all chunks
* that may be used for heap.
*
- ************************************************************************************/
+ ****************************************************************************/
void up_addregion(void)
{
- // TODO: add L1 memories
+ /* TODO: add L1 memorie */
}
diff --git a/arch/risc-v/src/gap8/startup_gap8.S b/arch/risc-v/src/gap8/gap8_head.S
similarity index 99%
rename from arch/risc-v/src/gap8/startup_gap8.S
rename to arch/risc-v/src/gap8/gap8_head.S
index 3dc0631..0d2e732 100644
--- a/arch/risc-v/src/gap8/startup_gap8.S
+++ b/arch/risc-v/src/gap8/gap8_head.S
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/gapuino/startup_gap8.S
+ * arch/risc-v/src/gapuino/gap8_head.S
* Startup file for FC of GAP8
* Interrupt vector and reset handler
*
diff --git a/arch/risc-v/src/gap8/gap8_idle.c b/arch/risc-v/src/gap8/gap8_idle.c
index ae04454..0f96593 100644
--- a/arch/risc-v/src/gap8/gap8_idle.c
+++ b/arch/risc-v/src/gap8/gap8_idle.c
@@ -41,7 +41,7 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/gap8/gap8_schedulesigaction.c b/arch/risc-v/src/gap8/gap8_schedulesigaction.c
index d7a7d0a..4c2a7fb 100644
--- a/arch/risc-v/src/gap8/gap8_schedulesigaction.c
+++ b/arch/risc-v/src/gap8/gap8_schedulesigaction.c
@@ -52,8 +52,8 @@
#include <arch/nr5m100/irq.h>
#include "sched/sched.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/k210/Make.defs b/arch/risc-v/src/k210/Make.defs
index 8b3032f..f6b8f72 100644
--- a/arch/risc-v/src/k210/Make.defs
+++ b/arch/risc-v/src/k210/Make.defs
@@ -37,23 +37,23 @@ HEAD_ASRC = k210_vectors.S
# Specify our general Assembly files
CHIP_ASRCS = k210_head.S
-CMN_ASRCS += up_testset.S
+CMN_ASRCS += riscv_testset.S
# Specify C code within the common directory to be included
-CMN_CSRCS += up_initialize.c up_swint.c
-CMN_CSRCS += up_allocateheap.c up_createstack.c up_exit.c up_fault.c
-CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c
-CMN_CSRCS += up_interruptcontext.c up_modifyreg32.c up_puts.c
-CMN_CSRCS += up_releasepending.c up_reprioritizertr.c
-CMN_CSRCS += up_releasestack.c up_stackframe.c up_schedulesigaction.c
-CMN_CSRCS += up_sigdeliver.c up_unblocktask.c up_usestack.c
+CMN_CSRCS += riscv_initialize.c riscv_swint.c
+CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_fault.c
+CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
+CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c
+CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
+CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c k210_schedulesigaction.c
+CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += up_checkstack.c
+CMN_CSRCS += riscv_checkstack.c
endif
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_CSRCS += up_vfork.c
+CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included
@@ -68,9 +68,9 @@ CHIP_CSRCS += k210_cpupause.c k210_cpustart.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
-CMN_CSRCS += up_task_start.c up_pthread_start.c
-CMN_CSRCS += up_signal_dispatch.c
-CMN_UASRCS += up_signal_handler.S
+CMN_CSRCS += riscv_task_start.c riscv_pthread_start.c
+CMN_CSRCS += riscv_signal_dispatch.c
+CMN_UASRCS += riscv_signal_handler.S
CHIP_CSRCS += k210_userspace.c
endif
diff --git a/arch/risc-v/src/k210/k210.h b/arch/risc-v/src/k210/k210.h
index b255223..cad6adc 100644
--- a/arch/risc-v/src/k210/k210.h
+++ b/arch/risc-v/src/k210/k210.h
@@ -46,7 +46,7 @@
#include <stdbool.h>
#include <arch/irq.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
#include "chip.h"
#include "k210_lowputc.h"
diff --git a/arch/risc-v/src/k210/k210_clockconfig.c b/arch/risc-v/src/k210/k210_clockconfig.c
index b707453..af2f164 100644
--- a/arch/risc-v/src/k210/k210_clockconfig.c
+++ b/arch/risc-v/src/k210/k210_clockconfig.c
@@ -46,7 +46,7 @@
#include <nuttx/arch.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "k210_clockconfig.h"
/****************************************************************************
diff --git a/arch/risc-v/src/k210/k210_cpuidlestack.c b/arch/risc-v/src/k210/k210_cpuidlestack.c
index de21901..750fa5d 100644
--- a/arch/risc-v/src/k210/k210_cpuidlestack.c
+++ b/arch/risc-v/src/k210/k210_cpuidlestack.c
@@ -44,7 +44,7 @@
#include <nuttx/arch.h>
#include <nuttx/sched.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
#ifdef CONFIG_SMP
diff --git a/arch/risc-v/src/k210/k210_cpuindex.c b/arch/risc-v/src/k210/k210_cpuindex.c
index 055aa76..71d9f94 100644
--- a/arch/risc-v/src/k210/k210_cpuindex.c
+++ b/arch/risc-v/src/k210/k210_cpuindex.c
@@ -41,7 +41,7 @@
#include <stdint.h>
#include <nuttx/arch.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#ifdef CONFIG_SMP
diff --git a/arch/risc-v/src/k210/k210_cpupause.c b/arch/risc-v/src/k210/k210_cpupause.c
index f02e269..c5a0af1 100644
--- a/arch/risc-v/src/k210/k210_cpupause.c
+++ b/arch/risc-v/src/k210/k210_cpupause.c
@@ -49,9 +49,9 @@
#include <nuttx/spinlock.h>
#include <nuttx/sched_note.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "sched/sched.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
#include "chip.h"
/****************************************************************************
diff --git a/arch/risc-v/src/k210/k210_cpustart.c b/arch/risc-v/src/k210/k210_cpustart.c
index c611f9b..ff37349 100644
--- a/arch/risc-v/src/k210/k210_cpustart.c
+++ b/arch/risc-v/src/k210/k210_cpustart.c
@@ -50,10 +50,10 @@
#include <nuttx/spinlock.h>
#include <nuttx/sched_note.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "sched/sched.h"
#include "init/init.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
#include "chip.h"
#ifdef CONFIG_SMP
diff --git a/arch/risc-v/src/k210/k210_idle.c b/arch/risc-v/src/k210/k210_idle.c
index 76919a5..abbefc0 100644
--- a/arch/risc-v/src/k210/k210_idle.c
+++ b/arch/risc-v/src/k210/k210_idle.c
@@ -43,7 +43,7 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/k210/k210_irq.c b/arch/risc-v/src/k210/k210_irq.c
index 7812351..d1c9fe5 100644
--- a/arch/risc-v/src/k210/k210_irq.c
+++ b/arch/risc-v/src/k210/k210_irq.c
@@ -46,8 +46,8 @@
#include <nuttx/arch.h>
#include <arch/irq.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "k210.h"
diff --git a/arch/risc-v/src/k210/k210_irq_dispatch.c b/arch/risc-v/src/k210/k210_irq_dispatch.c
index ced4c40..86d193b 100644
--- a/arch/risc-v/src/k210/k210_irq_dispatch.c
+++ b/arch/risc-v/src/k210/k210_irq_dispatch.c
@@ -44,8 +44,8 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "group/group.h"
diff --git a/arch/risc-v/src/k210/k210_lowputc.c b/arch/risc-v/src/k210/k210_lowputc.c
index 8fba280..fcdb845 100644
--- a/arch/risc-v/src/k210/k210_lowputc.c
+++ b/arch/risc-v/src/k210/k210_lowputc.c
@@ -43,8 +43,8 @@
#include <arch/board/board.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "k210_config.h"
#include "hardware/k210_memorymap.h"
diff --git a/arch/risc-v/src/k210/up_schedulesigaction.c b/arch/risc-v/src/k210/k210_schedulesigaction.c
similarity index 99%
rename from arch/risc-v/src/k210/up_schedulesigaction.c
rename to arch/risc-v/src/k210/k210_schedulesigaction.c
index 0a5a75e..1f2e7cd 100644
--- a/arch/risc-v/src/k210/up_schedulesigaction.c
+++ b/arch/risc-v/src/k210/k210_schedulesigaction.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/k210/up_schedulesigaction.c
+ * arch/risc-v/src/k210/k210_schedulesigaction.c
*
* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
* Author: Masayuki Ishikawa <ma...@gmail.com>
@@ -50,8 +50,8 @@
#include <arch/k210/irq.h>
#include "sched/sched.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "irq/irq.h"
diff --git a/arch/risc-v/src/k210/k210_serial.c b/arch/risc-v/src/k210/k210_serial.c
index 6af8ecc..b769ef8 100644
--- a/arch/risc-v/src/k210/k210_serial.c
+++ b/arch/risc-v/src/k210/k210_serial.c
@@ -53,8 +53,8 @@
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "k210_config.h"
#include "chip.h"
@@ -309,7 +309,7 @@ static void up_shutdown(struct uart_dev_s *dev)
* Name: up_attach
*
* Description:
- * Configure the UART to operation in interrupt driven mode. This method is
+ * Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
@@ -348,7 +348,7 @@ static int up_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
- * closed normally just before the shutdown method is called. The exception
+ * closed normally just before the shutdown method is called. The exception
* is the serial console which is never shutdown.
*
****************************************************************************/
diff --git a/arch/risc-v/src/k210/k210_start.c b/arch/risc-v/src/k210/k210_start.c
index 194bbd1..88b1c38 100644
--- a/arch/risc-v/src/k210/k210_start.c
+++ b/arch/risc-v/src/k210/k210_start.c
@@ -39,7 +39,7 @@
#include <nuttx/arch.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "k210_clockconfig.h"
#include "k210_userspace.h"
#include "k210.h"
diff --git a/arch/risc-v/src/k210/k210_timerisr.c b/arch/risc-v/src/k210/k210_timerisr.c
index c10e398..57a1e2d 100644
--- a/arch/risc-v/src/k210/k210_timerisr.c
+++ b/arch/risc-v/src/k210/k210_timerisr.c
@@ -46,7 +46,7 @@
#include <nuttx/arch.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "k210.h"
#include "k210_clockconfig.h"
diff --git a/arch/risc-v/src/litex/Make.defs b/arch/risc-v/src/litex/Make.defs
index 7a49f3f..e0faa24 100644
--- a/arch/risc-v/src/litex/Make.defs
+++ b/arch/risc-v/src/litex/Make.defs
@@ -23,23 +23,23 @@
HEAD_ASRC = litex_vectors.S
# Specify our general Assembly files
-CHIP_ASRCS = litex_head.S up_syscall.S
+CHIP_ASRCS = litex_head.S riscv_syscall.S
# Specify C code within the common directory to be included
-CMN_CSRCS += up_initialize.c up_swint.c
-CMN_CSRCS += up_allocateheap.c up_createstack.c up_exit.c
-CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c
-CMN_CSRCS += up_interruptcontext.c up_modifyreg32.c up_puts.c up_mdelay.c
-CMN_CSRCS += up_releasepending.c up_reprioritizertr.c
-CMN_CSRCS += up_releasestack.c up_stackframe.c up_schedulesigaction.c
-CMN_CSRCS += up_sigdeliver.c up_udelay.c up_unblocktask.c up_usestack.c
+CMN_CSRCS += riscv_initialize.c riscv_swint.c
+CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
+CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
+CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
+CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
+CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c litex_schedulesigaction.c
+CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c
ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += up_checkstack.c
+CMN_CSRCS += riscv_checkstack.c
endif
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_CSRCS += up_vfork.c
+CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included
diff --git a/arch/risc-v/src/litex/litex.h b/arch/risc-v/src/litex/litex.h
index 70c4fa8..2b40683 100644
--- a/arch/risc-v/src/litex/litex.h
+++ b/arch/risc-v/src/litex/litex.h
@@ -31,7 +31,7 @@
#include <stdbool.h>
#include <arch/irq.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
#include "chip.h"
#include "litex_lowputc.h"
diff --git a/arch/risc-v/src/litex/litex_clockconfig.c b/arch/risc-v/src/litex/litex_clockconfig.c
index 5622ae0..05ece91 100644
--- a/arch/risc-v/src/litex/litex_clockconfig.c
+++ b/arch/risc-v/src/litex/litex_clockconfig.c
@@ -31,7 +31,7 @@
#include <nuttx/arch.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "litex_clockconfig.h"
/****************************************************************************
diff --git a/arch/risc-v/src/litex/litex_idle.c b/arch/risc-v/src/litex/litex_idle.c
index b94230a..be8f3cf 100644
--- a/arch/risc-v/src/litex/litex_idle.c
+++ b/arch/risc-v/src/litex/litex_idle.c
@@ -28,7 +28,7 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/litex/litex_irq.c b/arch/risc-v/src/litex/litex_irq.c
index 0df390b..81520e4 100644
--- a/arch/risc-v/src/litex/litex_irq.c
+++ b/arch/risc-v/src/litex/litex_irq.c
@@ -33,8 +33,8 @@
#include <arch/irq.h>
#include <arch/board/board.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "litex.h"
diff --git a/arch/risc-v/src/litex/litex_irq_dispatch.c b/arch/risc-v/src/litex/litex_irq_dispatch.c
index 9381076..43fe03bf 100644
--- a/arch/risc-v/src/litex/litex_irq_dispatch.c
+++ b/arch/risc-v/src/litex/litex_irq_dispatch.c
@@ -32,8 +32,8 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "litex.h"
diff --git a/arch/risc-v/src/litex/litex_lowputc.c b/arch/risc-v/src/litex/litex_lowputc.c
index 20054ee..79b7329 100644
--- a/arch/risc-v/src/litex/litex_lowputc.c
+++ b/arch/risc-v/src/litex/litex_lowputc.c
@@ -28,8 +28,8 @@
#include <arch/board/board.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "litex_config.h"
#include "hardware/litex_memorymap.h"
diff --git a/arch/risc-v/src/litex/up_schedulesigaction.c b/arch/risc-v/src/litex/litex_schedulesigaction.c
similarity index 98%
rename from arch/risc-v/src/litex/up_schedulesigaction.c
rename to arch/risc-v/src/litex/litex_schedulesigaction.c
index 1becce5..77c5c2b 100644
--- a/arch/risc-v/src/litex/up_schedulesigaction.c
+++ b/arch/risc-v/src/litex/litex_schedulesigaction.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/litex/up_schedulesigaction.c
+ * arch/risc-v/src/litex/litex_schedulesigaction.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -33,8 +33,8 @@
#include <arch/litex/irq.h>
#include "sched/sched.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/litex/litex_serial.c b/arch/risc-v/src/litex/litex_serial.c
index 02b5235..f6085cc 100644
--- a/arch/risc-v/src/litex/litex_serial.c
+++ b/arch/risc-v/src/litex/litex_serial.c
@@ -38,8 +38,8 @@
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "litex_config.h"
#include "chip.h"
diff --git a/arch/risc-v/src/litex/litex_timerisr.c b/arch/risc-v/src/litex/litex_timerisr.c
index 48449a4..396c3d3 100644
--- a/arch/risc-v/src/litex/litex_timerisr.c
+++ b/arch/risc-v/src/litex/litex_timerisr.c
@@ -32,7 +32,7 @@
#include <nuttx/clock.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "litex.h"
#include "litex_clockconfig.h"
diff --git a/arch/risc-v/src/nr5m100/Make.defs b/arch/risc-v/src/nr5m100/Make.defs
index aeed1ec..450bd63 100644
--- a/arch/risc-v/src/nr5m100/Make.defs
+++ b/arch/risc-v/src/nr5m100/Make.defs
@@ -35,7 +35,7 @@
HEAD_ASRC = nr5_vectors.S
# Specify our general Assembly files
-CHIP_ASRCS = nr5_head.S nr5_csr.S up_syscall.S
+CHIP_ASRCS = nr5_head.S nr5_csr.S riscv_syscall.S
# If we are compiling the NELIB library, then specify it
# in AFLAGS so we can change up our startup behavior
@@ -52,15 +52,15 @@ endif
ASARCHCPUFLAGS += -march=RV32IMXcustom
# Specify C code within the common directory to be included
-CMN_CSRCS += up_initialize.c up_swint.c
-CMN_CSRCS += up_allocateheap.c up_createstack.c up_exit.c up_idle.c
-CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c
-CMN_CSRCS += up_interruptcontext.c up_releasepending.c up_reprioritizertr.c
-CMN_CSRCS += up_releasestack.c up_stackframe.c up_schedulesigaction.c up_sigdeliver.c
-CMN_CSRCS += up_unblocktask.c up_usestack.c
+CMN_CSRCS += riscv_initialize.c riscv_swint.c
+CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_idle.c
+CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
+CMN_CSRCS += riscv_interruptcontext.c riscv_releasepending.c riscv_reprioritizertr.c
+CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c nr5_schedulesigaction.c riscv_sigdeliver.c
+CMN_CSRCS += riscv_unblocktask.c riscv_usestack.c
ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
-CMN_CSRCS += up_vfork.c
+CMN_CSRCS += riscv_vfork.c
endif
# Specify our C code within this directory to be included
diff --git a/arch/risc-v/src/nr5m100/nr5.h b/arch/risc-v/src/nr5m100/nr5.h
index 90faecc..eeb3cd0 100644
--- a/arch/risc-v/src/nr5m100/nr5.h
+++ b/arch/risc-v/src/nr5m100/nr5.h
@@ -50,11 +50,7 @@
#include <stdbool.h>
#include <arch/irq.h>
-#include "up_internal.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+#include "riscv_internal.h"
/* Peripherals **********************************************************************/
@@ -64,4 +60,8 @@
#include "nr5_timer.h"
#include "nr5_uart.h"
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
#endif /* __ARCH_RISCV_SRC_NR5_NR5_H */
diff --git a/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c b/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c
index ba853bf..919c90f 100644
--- a/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c
+++ b/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/risc-v/src/nr5m100/nr5_irq_dispatch.c
*
* Copyright (C) 2016 Ken Pettit. All rights reserved.
@@ -33,7 +33,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
/****************************************************************************
* Included Files
@@ -49,8 +49,8 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "group/group.h"
@@ -76,8 +76,9 @@ volatile uint32_t * g_current_regs;
uint32_t * irq_dispatch_all(uint32_t *regs, uint32_t irqmask)
{
- int next, mask;
- mask = irqmask & 0xFFFF;
+ int next;
+ int mask;
+ mask = irqmask & 0xffff;
board_autoled_on(LED_INIRQ);
@@ -97,43 +98,44 @@ uint32_t * irq_dispatch_all(uint32_t *regs, uint32_t irqmask)
next = up_lsbenc(mask);
while (next != -1)
- {
- /* Deliver the IRQ */
+ {
+ /* Deliver the IRQ */
- irq_dispatch(next, regs);
+ irq_dispatch(next, regs);
- /* Clear the IRQ from the mask */
+ /* Clear the IRQ from the mask */
- mask &= !(1 << next);
- next = up_lsbenc(mask);
+ mask &= !(1 << next);
+ next = up_lsbenc(mask);
#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
- /* Check for a context switch. If a context switch occurred, then
- * g_current_regs will have a different value than it did on entry. If an
- * interrupt level context switch has occurred, then restore the floating
- * point state and the establish the correct address environment before
- * returning from the interrupt.
- */
- if (regs != g_current_regs)
- {
+ /* Check for a context switch. If a context switch occurred, then
+ * g_current_regs will have a different value than it did on entry.
+ * If an interrupt level context switch has occurred, then restore the
+ * floating point state and the establish the correct address
+ * environment before returning from the interrupt.
+ */
+
+ if (regs != g_current_regs)
+ {
#ifdef CONFIG_ARCH_FPU
- /* Restore floating point registers */
+ /* Restore floating point registers */
- up_restorefpu((uint32_t *)g_current_regs);
+ up_restorefpu((uint32_t *)g_current_regs);
#endif
#ifdef CONFIG_ARCH_ADDRENV
- /* Make sure that the address environment for the previously
- * running task is closed down gracefully (data caches dump,
- * MMU flushed) and set up the address environment for the new
- * thread at the head of the ready-to-run list.
- */
+ /* Make sure that the address environment for the previously
+ * running task is closed down gracefully (data caches dump,
+ * MMU flushed) and set up the address environment for the new
+ * thread at the head of the ready-to-run list.
+ */
- group_addrenv(NULL);
+ group_addrenv(NULL);
#endif
- }
+ }
#endif
- }
+ }
#endif
diff --git a/arch/risc-v/src/nr5m100/nr5_lowputc.c b/arch/risc-v/src/nr5m100/nr5_lowputc.c
index effafb0..62b34eb 100644
--- a/arch/risc-v/src/nr5m100/nr5_lowputc.c
+++ b/arch/risc-v/src/nr5m100/nr5_lowputc.c
@@ -48,8 +48,8 @@
#include <arch/board/board.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "nr5_config.h"
#include "nr5.h"
@@ -85,11 +85,11 @@
# if defined(CONFIG_NR5_NR5M1XX)
- /* Baud rate for standard UART:
- *
- * In case of oversampling by 16, the equation is:
- * UARTDIV = fCK / 32 / baud
- */
+ /* Baud rate for standard UART:
+ *
+ * In case of oversampling by 16, the equation is:
+ * UARTDIV = fCK / 32 / baud
+ */
# define NR5_UARTDIV \
((NR5_HCLK_FREQUENCY >> 5) / NR5_CONSOLE_BAUD)
@@ -134,7 +134,8 @@ void up_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE
/* Wait until the TX data register is empty */
- while ((getreg32(NR5_CONSOLE_BASE + NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) == 0)
+ while ((getreg32(NR5_CONSOLE_BASE + NR5_UART_STATUS_REG_OFFSET) &
+ NR5_UART_STATUS_TX_EMPTY) == 0)
;
/* Then send the character */
@@ -170,7 +171,8 @@ void nr5_lowsetup(void)
/* Configure the RX interrupt */
- putreg32(NR5_UART_CTRL_ENABLE_RX_IRQ, NR5_CONSOLE_BASE + NR5_UART_CTRL_REG_OFFSET);
+ putreg32(NR5_UART_CTRL_ENABLE_RX_IRQ,
+ NR5_CONSOLE_BASE + NR5_UART_CTRL_REG_OFFSET);
#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_UART */
diff --git a/arch/risc-v/src/nr5m100/up_schedulesigaction.c b/arch/risc-v/src/nr5m100/nr5_schedulesigaction.c
similarity index 98%
rename from arch/risc-v/src/nr5m100/up_schedulesigaction.c
rename to arch/risc-v/src/nr5m100/nr5_schedulesigaction.c
index 7fba9a2..375f7f1 100644
--- a/arch/risc-v/src/nr5m100/up_schedulesigaction.c
+++ b/arch/risc-v/src/nr5m100/nr5_schedulesigaction.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/nr5m100/up_schedulesigaction.c
+ * arch/risc-v/src/nr5m100/nr5_schedulesigaction.c
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -53,8 +53,8 @@
#include <arch/nr5m100/irq.h>
#include "sched/sched.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/nr5m100/nr5_serial.c b/arch/risc-v/src/nr5m100/nr5_serial.c
index ac4d991..f63cce1 100644
--- a/arch/risc-v/src/nr5m100/nr5_serial.c
+++ b/arch/risc-v/src/nr5m100/nr5_serial.c
@@ -62,8 +62,8 @@
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "nr5_config.h"
#include "chip.h"
@@ -72,6 +72,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* If we are not using the serial driver for the console, then we still must
* provide some minimal implementation of up_putc.
*/
@@ -132,7 +133,7 @@
struct up_dev_s
{
- uintptr_t uartbase; /* Base address of UART registers */
+ uintptr_t uartbase; /* Base address of UART registers */
uint32_t baud; /* Configured baud */
uint8_t irqrx; /* RX IRQ associated with this UART (for enable) */
uint8_t irqtx; /* TX IRQ associated with this UART (for enable) */
@@ -147,7 +148,8 @@ struct up_dev_s
/* Low-level helpers */
static inline uint32_t up_serialin(struct up_dev_s *priv, int offset);
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value);
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+ uint32_t value);
static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im);
static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im);
@@ -227,7 +229,7 @@ static uart_dev_t g_uart1port =
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
- },
+ },
.ops = &g_uart_ops,
.priv = &g_uart1priv,
};
@@ -250,7 +252,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
* Name: up_serialout
****************************************************************************/
-static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+static inline void up_serialout(struct up_dev_s *priv, int offset,
+ uint32_t value)
{
putreg32(value, priv->uartbase + offset);
}
@@ -263,7 +266,9 @@ static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im)
{
irqstate_t flags;
- /* Re-enable/re-disable interrupts corresponding to the state of bits in im */
+ /* Re-enable/re-disable interrupts corresponding to the state of bits
+ * in im
+ */
flags = enter_critical_section();
up_rxint(dev, RX_ENABLED(im));
@@ -282,9 +287,10 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im)
flags = enter_critical_section();
if (im)
- {
- *im = priv->im;
- }
+ {
+ *im = priv->im;
+ }
+
up_restoreuartint(dev, 0);
leave_critical_section(flags);
}
@@ -301,12 +307,10 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im)
static int up_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
-// struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
/* Configure the UART as an RS-232 UART */
- //pic32mx_uartconfigure(priv->uartbase, priv->baud, priv->parity,
- // priv->bits, priv->stopbits2);
#endif
#ifdef CONFIG_ARCH_IRQPRIO
@@ -329,7 +333,9 @@ static int up_setup(struct uart_dev_s *dev)
static void up_shutdown(struct uart_dev_s *dev)
{
- //struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+#if 0
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+#endif
/* Disable interrupts */
@@ -337,21 +343,24 @@ static void up_shutdown(struct uart_dev_s *dev)
/* Reset hardware and disable Rx and Tx */
- //nr5_uartreset(priv->uartbase);
+#if 0
+ nr5_uartreset(priv->uartbase);
+#endif
}
/****************************************************************************
* Name: up_attach
*
* Description:
- * Configure the UART to operation in interrupt driven mode. This method is
- * called when the serial port is opened. Normally, this is just after the
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
- * interrupts are not enabled until the txint() and rxint() methods are called.
+ * interrupts are not enabled until the txint() and rxint() methods are
+ * called.
*
****************************************************************************/
@@ -377,7 +386,7 @@ static int up_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
- * closed normally just before the shutdown method is called. The exception
+ * closed normally just before the shutdown method is called. The exception
* is the serial console which is never shutdown.
*
****************************************************************************/
@@ -450,8 +459,8 @@ static int up_interrupt(int irq, void *context, FAR void *arg)
/* Handle outgoing, transmit bytes The RT FIFO is configured to
* interrupt only when the TX FIFO is empty. There are not many
* options on trigger TX interrupts. The FIFO-not-full might generate
- * better through-put but with a higher interrupt rate. FIFO-empty should
- * lower the interrupt rate but result in a burstier output. If
+ * better through-put but with a higher interrupt rate. FIFO-empty
+ * should lower the interrupt rate but result in a burstier output. If
* you change this, You will probably need to change the conditions for
* clearing the pending TX interrupt below.
*
@@ -537,8 +546,6 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
*/
priv->baud = cfgetispeed(termiosp);
- //pic32mx_uartconfigure(priv->uartbase, priv->baud, priv->parity,
- // priv->bits, priv->stopbits2);
}
break;
@@ -597,8 +604,8 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
im = priv->im;
if (enable)
{
- /* Receive an interrupt when their is anything in the Rx data register (or an Rx
- * timeout occurs).
+ /* Receive an interrupt when their is anything in the Rx data register
+ * (or an Rx timeout occurs).
*/
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
@@ -611,6 +618,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
up_disable_irq(priv->irqrx);
DISABLE_RX(im);
}
+
priv->im = im;
leave_critical_section(flags);
}
@@ -629,7 +637,8 @@ static bool up_rxavailable(struct uart_dev_s *dev)
/* Return true is data is available in the receive data buffer */
- return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_RX_AVAIL) != 0;
+ return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) &
+ NR5_UART_STATUS_RX_AVAIL) != 0;
}
/****************************************************************************
@@ -703,7 +712,8 @@ static bool up_txready(struct uart_dev_s *dev)
/* Return TRUE if the Transmit buffer register is not full */
- return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) != 0;
+ return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) &
+ NR5_UART_STATUS_TX_EMPTY) != 0;
}
/****************************************************************************
@@ -720,7 +730,8 @@ static bool up_txempty(struct uart_dev_s *dev)
/* Return TRUE if the Transmit shift register is empty */
- return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) != 0;
+ return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) &
+ NR5_UART_STATUS_TX_EMPTY) != 0;
}
/****************************************************************************
diff --git a/arch/risc-v/src/nr5m100/nr5_timer.c b/arch/risc-v/src/nr5m100/nr5_timer.c
index d03fbff..ecdcee9 100644
--- a/arch/risc-v/src/nr5m100/nr5_timer.c
+++ b/arch/risc-v/src/nr5m100/nr5_timer.c
@@ -51,18 +51,19 @@
#include <nuttx/arch.h>
#include "chip.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
#include "nr5.h"
/************************************************************************************
* Private Types
************************************************************************************/
+
/* Configuration ********************************************************************/
-/* This module then only compiles if there are enabled timers that are not intended for
- * some other purpose.
+/* This module then only compiles if there are enabled timers that are not intended
+ * for some other purpose.
*/
#if defined(CONFIG_NR5_TIMER0) || defined(CONFIG_NR5_TIMER1) || defined(CONFIG_NR5_TIMER2) || \
@@ -331,7 +332,11 @@ static int nr5_timer_setmode(FAR struct nr5_timer_dev_s *dev, nr5_timer_mode_t m
case NR5_TIMER_MODE_UPDOWN:
val |= ATIM_CR1_CENTER1;
- // Our default: Interrupts are generated on compare, when counting down
+
+ /* Our default: Interrupts are generated on compare, when counting
+ * down
+ */
+
break;
case NR5_TIMER_MODE_PULSE:
diff --git a/arch/risc-v/src/nr5m100/nr5_timerisr.c b/arch/risc-v/src/nr5m100/nr5_timerisr.c
index be2e05f..6478812 100644
--- a/arch/risc-v/src/nr5m100/nr5_timerisr.c
+++ b/arch/risc-v/src/nr5m100/nr5_timerisr.c
@@ -51,7 +51,7 @@
#include <nuttx/arch.h>
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "nr5.h"
diff --git a/arch/risc-v/src/rv32im/up_assert.c b/arch/risc-v/src/rv32im/riscv_assert.c
similarity index 89%
rename from arch/risc-v/src/rv32im/up_assert.c
rename to arch/risc-v/src/rv32im/riscv_assert.c
index 0542b6c..97f5756 100644
--- a/arch/risc-v/src/rv32im/up_assert.c
+++ b/arch/risc-v/src/rv32im/riscv_assert.c
@@ -52,9 +52,9 @@
#include <arch/board/board.h>
-#include "up_arch.h"
+#include "riscv_arch.h"
#include "sched/sched.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
@@ -74,7 +74,6 @@
* Private Functions
****************************************************************************/
-
#ifdef CONFIG_ARCH_STACKDUMP
/****************************************************************************
@@ -113,7 +112,6 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
}
}
-
/****************************************************************************
* Name: up_taskdump
****************************************************************************/
@@ -162,29 +160,35 @@ static inline void up_registerdump(void)
{
_alert("EPC:%08x \n",
g_current_regs[REG_EPC]);
- _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n",
- g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2],
- g_current_regs[REG_A3], g_current_regs[REG_A4], g_current_regs[REG_A5],
+ _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x "
+ "A6:%08x A7:%08x\n",
+ g_current_regs[REG_A0], g_current_regs[REG_A1],
+ g_current_regs[REG_A2], g_current_regs[REG_A3],
+ g_current_regs[REG_A4], g_current_regs[REG_A5],
g_current_regs[REG_A6], g_current_regs[REG_A7]);
_alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n",
- g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2],
- g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5],
+ g_current_regs[REG_T0], g_current_regs[REG_T1],
+ g_current_regs[REG_T2], g_current_regs[REG_T3],
+ g_current_regs[REG_T4], g_current_regs[REG_T5],
g_current_regs[REG_T6]);
- _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n",
- g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2],
- g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5],
+ _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
+ "S6:%08x S7:%08x\n",
+ g_current_regs[REG_S0], g_current_regs[REG_S1],
+ g_current_regs[REG_S2], g_current_regs[REG_S3],
+ g_current_regs[REG_S4], g_current_regs[REG_S5],
g_current_regs[REG_S6], g_current_regs[REG_S7]);
_alert("S8:%08x S9:%08x S10:%08x S11:%08x\n",
- g_current_regs[REG_S8], g_current_regs[REG_S9], g_current_regs[REG_S10],
- g_current_regs[REG_S11]);
+ g_current_regs[REG_S8], g_current_regs[REG_S9],
+ g_current_regs[REG_S10], g_current_regs[REG_S11]);
#ifdef RISCV_SAVE_GP
_alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n",
- g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP],
- g_current_regs[REG_TP], g_current_regs[REG_RA]);
+ g_current_regs[REG_GP], g_current_regs[REG_SP],
+ g_current_regs[REG_FP], g_current_regs[REG_TP],
+ g_current_regs[REG_RA]);
#else
_alert("SP:%08x FP:%08x TP:%08x RA:%08x\n",
- g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_TP],
- g_current_regs[REG_RA]);
+ g_current_regs[REG_SP], g_current_regs[REG_FP],
+ g_current_regs[REG_TP], g_current_regs[REG_RA]);
#endif
}
}
@@ -285,7 +289,6 @@ static void up_dumpstate(void)
#endif /* CONFIG_ARCH_STACKDUMP */
-
/****************************************************************************
* Name: _up_assert
****************************************************************************/
@@ -301,19 +304,19 @@ static void _up_assert(int errorcode)
if (g_current_regs || running_task()->flink == NULL)
{
- up_irq_save();
- for (; ; )
- {
+ up_irq_save();
+ for (; ; )
+ {
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
- board_reset(CONFIG_BOARD_ASSERT_RESET_VALUE);
+ board_reset(CONFIG_BOARD_ASSERT_RESET_VALUE);
#endif
#ifdef CONFIG_ARCH_LEDS
- board_autoled_on(LED_PANIC);
- up_mdelay(250);
- board_autoled_off(LED_PANIC);
- up_mdelay(250);
+ board_autoled_on(LED_PANIC);
+ up_mdelay(250);
+ board_autoled_off(LED_PANIC);
+ up_mdelay(250);
#endif
- }
+ }
}
else
{
diff --git a/arch/risc-v/src/rv32im/up_blocktask.c b/arch/risc-v/src/rv32im/riscv_blocktask.c
similarity index 99%
rename from arch/risc-v/src/rv32im/up_blocktask.c
rename to arch/risc-v/src/rv32im/riscv_blocktask.c
index 6abe5f8..7ee27d4 100644
--- a/arch/risc-v/src/rv32im/up_blocktask.c
+++ b/arch/risc-v/src/rv32im/riscv_blocktask.c
@@ -49,7 +49,7 @@
#include "sched/sched.h"
#include "group/group.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/rv32im/up_copystate.c b/arch/risc-v/src/rv32im/riscv_copystate.c
similarity index 99%
rename from arch/risc-v/src/rv32im/up_copystate.c
rename to arch/risc-v/src/rv32im/riscv_copystate.c
index 8e373eb..08fc953 100644
--- a/arch/risc-v/src/rv32im/up_copystate.c
+++ b/arch/risc-v/src/rv32im/riscv_copystate.c
@@ -42,7 +42,7 @@
#include <stdint.h>
#include <arch/irq.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/risc-v/src/rv32im/up_doirq.c b/arch/risc-v/src/rv32im/riscv_doirq.c
similarity index 97%
rename from arch/risc-v/src/rv32im/up_doirq.c
rename to arch/risc-v/src/rv32im/riscv_doirq.c
index eb090c2..77ce6b9 100644
--- a/arch/risc-v/src/rv32im/up_doirq.c
+++ b/arch/risc-v/src/rv32im/riscv_doirq.c
@@ -47,8 +47,8 @@
#include <nuttx/board.h>
#include <arch/board/board.h>
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
#include "group/group.h"
@@ -87,8 +87,8 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
DEBUGASSERT(g_current_regs == NULL);
g_current_regs = regs;
- /* Disable further occurrences of this interrupt (until the interrupt sources
- * have been clear by the driver).
+ /* Disable further occurrences of this interrupt (until the interrupt
+ * sources have been clear by the driver).
*/
up_disable_irq(irq);
diff --git a/arch/risc-v/src/rv32im/up_fpu.S b/arch/risc-v/src/rv32im/riscv_fpu.S
similarity index 100%
rename from arch/risc-v/src/rv32im/up_fpu.S
rename to arch/risc-v/src/rv32im/riscv_fpu.S
diff --git a/arch/risc-v/src/rv32im/up_initialstate.c b/arch/risc-v/src/rv32im/riscv_initialstate.c
similarity index 98%
rename from arch/risc-v/src/rv32im/up_initialstate.c
rename to arch/risc-v/src/rv32im/riscv_initialstate.c
index 9b0d9d5..5f0ae55 100644
--- a/arch/risc-v/src/rv32im/up_initialstate.c
+++ b/arch/risc-v/src/rv32im/riscv_initialstate.c
@@ -46,8 +46,8 @@
#include <nuttx/arch.h>
#include <arch/irq.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/rv32im/up_releasepending.c b/arch/risc-v/src/rv32im/riscv_releasepending.c
similarity index 99%
rename from arch/risc-v/src/rv32im/up_releasepending.c
rename to arch/risc-v/src/rv32im/riscv_releasepending.c
index 814b1f3..799be84 100644
--- a/arch/risc-v/src/rv32im/up_releasepending.c
+++ b/arch/risc-v/src/rv32im/riscv_releasepending.c
@@ -48,7 +48,7 @@
#include "sched/sched.h"
#include "group/group.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
@@ -74,6 +74,7 @@ void up_release_pending(void)
/* Merge the g_pendingtasks list into the ready-to-run task list */
/* sched_lock(); */
+
if (sched_mergepending())
{
/* The currently active task has changed! We will need to switch
diff --git a/arch/risc-v/src/rv32im/up_reprioritizertr.c b/arch/risc-v/src/rv32im/riscv_reprioritizertr.c
similarity index 97%
rename from arch/risc-v/src/rv32im/up_reprioritizertr.c
rename to arch/risc-v/src/rv32im/riscv_reprioritizertr.c
index 9848555..f33f452 100644
--- a/arch/risc-v/src/rv32im/up_reprioritizertr.c
+++ b/arch/risc-v/src/rv32im/riscv_reprioritizertr.c
@@ -50,7 +50,7 @@
#include "sched/sched.h"
#include "group/group.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
@@ -138,7 +138,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
sched_suspend_scheduler(rtcb);
- /* Are we in an interrupt handler? */
+ /* Are we in an interrupt handler? */
if (g_current_regs)
{
@@ -194,7 +194,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
/* up_switchcontext forces a context switch to the task at the
* head of the ready-to-run list. It does not 'return' in the
- * normal sense. When it does return, it is because the blocked
+ * normal sense. When it does return, it is because the blocked
* task is again ready to run and has execution priority.
*/
}
diff --git a/arch/risc-v/src/rv32im/up_sigdeliver.c b/arch/risc-v/src/rv32im/riscv_sigdeliver.c
similarity index 97%
rename from arch/risc-v/src/rv32im/up_sigdeliver.c
rename to arch/risc-v/src/rv32im/riscv_sigdeliver.c
index 5423d42..d1276bc 100644
--- a/arch/risc-v/src/rv32im/up_sigdeliver.c
+++ b/arch/risc-v/src/rv32im/riscv_sigdeliver.c
@@ -55,8 +55,8 @@
#include <arch/board/board.h>
#include "sched/sched.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
@@ -111,7 +111,8 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sinfo("Resuming EPC: %08x INT_CTX: %08x\n", regs[REG_EPC], regs[REG_INT_CTX]);
+ sinfo("Resuming EPC: %08x INT_CTX: %08x\n",
+ regs[REG_EPC], regs[REG_INT_CTX]);
up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/risc-v/src/rv32im/up_swint.c b/arch/risc-v/src/rv32im/riscv_swint.c
similarity index 89%
rename from arch/risc-v/src/rv32im/up_swint.c
rename to arch/risc-v/src/rv32im/riscv_swint.c
index fab0d4b..471c676 100644
--- a/arch/risc-v/src/rv32im/up_swint.c
+++ b/arch/risc-v/src/rv32im/riscv_swint.c
@@ -50,7 +50,7 @@
#include <arch/irq.h>
#include "signal/signal.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Private Functions
@@ -65,20 +65,23 @@ static void up_registerdump(const uint32_t *regs)
{
svcinfo("EPC:%08x\n",
regs[REG_EPC]);
- svcinfo("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n",
+ svcinfo("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x "
+ "A6:%08x A7:%08x\n",
regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3],
regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
svcinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n",
regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3],
regs[REG_T4], regs[REG_T5], regs[REG_T6]);
- svcinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n",
+ svcinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
+ "S6:%08x S7:%08x\n",
regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3],
regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
svcinfo("S8:%08x S9:%08x S10:%08x S11:%08x\n",
regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]);
#ifdef MIPS32_SAVE_GP
svcinfo("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n",
- regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]);
+ regs[REG_GP], regs[REG_SP], regs[REG_FP],
+ regs[REG_TP], regs[REG_RA]);
#else
svcinfo("SP:%08x FP:%08x TP:%08x RA:%08x\n",
regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]);
@@ -102,17 +105,20 @@ static void dispatch_syscall(void)
{
# error "Missing logic"
-/* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for ARM */
-/* __asm__ __volatile__ */
-/* ( */
-/* Save registers */
-/* Get the base of the stub lookup table */
-/* Get the offset of the stub for this syscall */
-/* Load the entry of the stub for this syscall */
-/* Call the stub */
-/* Restore registers */
-/* Return from the syscall */
-/* ); */
+ /* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for
+ * ARM
+ *
+ * __asm__ __volatile__
+ * (
+ * Save registers
+ * Get the base of the stub lookup table
+ * Get the offset of the stub for this syscall
+ * Load the entry of the stub for this syscall
+ * Call the stub
+ * Restore registers
+ * Return from the syscall
+ * );
+ */
}
#endif
@@ -151,17 +157,18 @@ int up_swint(int irq, FAR void *context, FAR void *arg)
{
/* A0=SYS_restore_context: This a restore context command:
*
- * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
+ * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
* At this point, the following values are saved in context:
*
* A0 = SYS_restore_context
* A1 = restoreregs
*
- * In this case, we simply need to set g_current_regs to restore register
- * area referenced in the saved R1. context == g_current_regs is the normal
- * exception return. By setting g_current_regs = context[R1], we force
- * the return to the saved context referenced in $a1.
+ * In this case, we simply need to set g_current_regs to restore
+ * register area referenced in the saved R1. context == g_current_regs
+ * is the normal exception return.
+ * By setting g_current_regs = context[R1], we force the return to the
+ * saved context referenced in $a1.
*/
case SYS_restore_context:
@@ -279,7 +286,9 @@ int up_swint(int irq, FAR void *context, FAR void *arg)
break;
}
- /* Report what happened. That might difficult in the case of a context switch */
+ /* Report what happened. That might difficult in the case of a context
+ * switch
+ */
#ifdef CONFIG_DEBUG_SYSCALL_INFO
if (regs != g_current_regs)
diff --git a/arch/risc-v/src/rv32im/up_syscall.S b/arch/risc-v/src/rv32im/riscv_syscall.S
similarity index 100%
rename from arch/risc-v/src/rv32im/up_syscall.S
rename to arch/risc-v/src/rv32im/riscv_syscall.S
diff --git a/arch/risc-v/src/rv32im/up_unblocktask.c b/arch/risc-v/src/rv32im/riscv_unblocktask.c
similarity index 99%
rename from arch/risc-v/src/rv32im/up_unblocktask.c
rename to arch/risc-v/src/rv32im/riscv_unblocktask.c
index ecb24f9..9d7d8e8 100644
--- a/arch/risc-v/src/rv32im/up_unblocktask.c
+++ b/arch/risc-v/src/rv32im/riscv_unblocktask.c
@@ -49,7 +49,7 @@
#include "sched/sched.h"
#include "group/group.h"
#include "clock/clock.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/rv32im/up_vfork.c b/arch/risc-v/src/rv32im/riscv_vfork.c
similarity index 98%
rename from arch/risc-v/src/rv32im/up_vfork.c
rename to arch/risc-v/src/rv32im/riscv_vfork.c
index 0eb311d..9790e9e 100644
--- a/arch/risc-v/src/rv32im/up_vfork.c
+++ b/arch/risc-v/src/rv32im/riscv_vfork.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/mips/src/mips32/up_vfork.c
+ * arch/riscv/src/rv32im/riscv_vfork.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -49,7 +49,7 @@
#include <nuttx/arch.h>
#include <arch/irq.h>
-#include "up_vfork.h"
+#include "riscv_vfork.h"
#include "sched/sched.h"
/****************************************************************************
@@ -84,8 +84,8 @@
* 1) User code calls vfork(). vfork() collects context information and
* transfers control up up_vfork().
* 2) up_vfork()and calls nxtask_vforksetup().
- * 3) nxtask_vforksetup() allocates and configures the child task's TCB. This
- * consists of:
+ * 3) nxtask_vforksetup() allocates and configures the child task's TCB.
+ * This consists of:
* - Allocation of the child task's TCB.
* - Initialization of file descriptors and streams
* - Configuration of environment variables
@@ -98,7 +98,8 @@
* 5) up_vfork() then calls nxtask_vforkstart()
* 6) nxtask_vforkstart() then executes the child thread.
*
- * nxtask_vforkabort() may be called if an error occurs between steps 3 and 6.
+ * nxtask_vforkabort() may be called if an error occurs between steps 3
+ * and 6.
*
* Input Parameters:
* context - Caller context information saved by vfork()
diff --git a/arch/risc-v/src/rv32im/up_vfork.h b/arch/risc-v/src/rv32im/riscv_vfork.h
similarity index 97%
rename from arch/risc-v/src/rv32im/up_vfork.h
rename to arch/risc-v/src/rv32im/riscv_vfork.h
index 079a744..5cb6aa4 100644
--- a/arch/risc-v/src/rv32im/up_vfork.h
+++ b/arch/risc-v/src/rv32im/riscv_vfork.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/mips/src/mips/up_vfork.h
+ * arch/riscv/src/rv32im/riscv_vfork.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -46,6 +46,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Register r30 may be a frame pointer in some ABIs. Or may just be saved
* register s8. It makes a difference for vfork handling.
*/
@@ -60,7 +61,8 @@
* preserved across function calls.
* r8-r15 t0-t7 Temporary registers used for expression evaluation; values
* are not preserved across function calls.
- * r16-r23 s0-s7 Saved registers; values are preserved across function calls.
+ * r16-r23 s0-s7 Saved registers; values are preserved across function
+ * calls.
* r24-r25 t8-t9 Temporary registers used for expression evaluations; values
* are not preserved across function calls. When calling
* position independent functions r25 must contain the address
@@ -119,8 +121,8 @@ struct vfork_s
#else
uint32_t s8; /* Saved register s8 */
#endif
- uint32_t sp; /* Stack pointer*/
- uint32_t ra; /* Return address*/
+ uint32_t sp; /* Stack pointer */
+ uint32_t ra; /* Return address */
#ifdef MIPS32_SAVE_GP
uint32_t gp; /* Global pointer */
#endif
diff --git a/arch/risc-v/src/rv64gc/up_assert.c b/arch/risc-v/src/rv64gc/riscv_assert.c
similarity index 99%
rename from arch/risc-v/src/rv64gc/up_assert.c
rename to arch/risc-v/src/rv64gc/riscv_assert.c
index 40dd255..b0fe071 100644
--- a/arch/risc-v/src/rv64gc/up_assert.c
+++ b/arch/risc-v/src/rv64gc/riscv_assert.c
@@ -55,8 +55,8 @@
#include "sched/sched.h"
#include "irq/irq.h"
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/risc-v/src/rv64gc/up_blocktask.c b/arch/risc-v/src/rv64gc/riscv_blocktask.c
similarity index 99%
rename from arch/risc-v/src/rv64gc/up_blocktask.c
rename to arch/risc-v/src/rv64gc/riscv_blocktask.c
index 610e286..1701ae9 100644
--- a/arch/risc-v/src/rv64gc/up_blocktask.c
+++ b/arch/risc-v/src/rv64gc/riscv_blocktask.c
@@ -49,7 +49,7 @@
#include "sched/sched.h"
#include "group/group.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/rv64gc/up_copystate.c b/arch/risc-v/src/rv64gc/riscv_copystate.c
similarity index 99%
rename from arch/risc-v/src/rv64gc/up_copystate.c
rename to arch/risc-v/src/rv64gc/riscv_copystate.c
index 1ba967c..8b8fe6d 100644
--- a/arch/risc-v/src/rv64gc/up_copystate.c
+++ b/arch/risc-v/src/rv64gc/riscv_copystate.c
@@ -42,7 +42,7 @@
#include <stdint.h>
#include <arch/irq.h>
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/risc-v/src/rv64gc/up_fault.c b/arch/risc-v/src/rv64gc/riscv_fault.c
similarity index 98%
rename from arch/risc-v/src/rv64gc/up_fault.c
rename to arch/risc-v/src/rv64gc/riscv_fault.c
index 5075f9e..d60710f 100644
--- a/arch/risc-v/src/rv64gc/up_fault.c
+++ b/arch/risc-v/src/rv64gc/riscv_fault.c
@@ -54,8 +54,8 @@
#include "sched/sched.h"
#include "irq/irq.h"
-#include "up_arch.h"
-#include "up_internal.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/rv64gc/up_initialstate.c b/arch/risc-v/src/rv64gc/riscv_initialstate.c
similarity index 98%
rename from arch/risc-v/src/rv64gc/up_initialstate.c
rename to arch/risc-v/src/rv64gc/riscv_initialstate.c
index 8fbad33..caa0c37 100644
--- a/arch/risc-v/src/rv64gc/up_initialstate.c
+++ b/arch/risc-v/src/rv64gc/riscv_initialstate.c
@@ -46,8 +46,8 @@
#include <nuttx/arch.h>
#include <arch/irq.h>
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/rv64gc/up_releasepending.c b/arch/risc-v/src/rv64gc/riscv_releasepending.c
similarity index 99%
rename from arch/risc-v/src/rv64gc/up_releasepending.c
rename to arch/risc-v/src/rv64gc/riscv_releasepending.c
index 1d6bf45..312b6c6 100644
--- a/arch/risc-v/src/rv64gc/up_releasepending.c
+++ b/arch/risc-v/src/rv64gc/riscv_releasepending.c
@@ -48,7 +48,7 @@
#include "sched/sched.h"
#include "group/group.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/rv64gc/up_reprioritizertr.c b/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c
similarity index 98%
rename from arch/risc-v/src/rv64gc/up_reprioritizertr.c
rename to arch/risc-v/src/rv64gc/riscv_reprioritizertr.c
index 049a103..00e8c3d 100644
--- a/arch/risc-v/src/rv64gc/up_reprioritizertr.c
+++ b/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c
@@ -50,7 +50,7 @@
#include "sched/sched.h"
#include "group/group.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions
@@ -194,7 +194,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
/* up_switchcontext forces a context switch to the task at the
* head of the ready-to-run list. It does not 'return' in the
- * normal sense. When it does return, it is because the blocked
+ * normal sense. When it does return, it is because the blocked
* task is again ready to run and has execution priority.
*/
}
diff --git a/arch/risc-v/src/rv64gc/up_sigdeliver.c b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c
similarity index 99%
rename from arch/risc-v/src/rv64gc/up_sigdeliver.c
rename to arch/risc-v/src/rv64gc/riscv_sigdeliver.c
index e7eaa87..073647e 100644
--- a/arch/risc-v/src/rv64gc/up_sigdeliver.c
+++ b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c
@@ -55,8 +55,8 @@
#include <arch/board/board.h>
#include "sched/sched.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
diff --git a/arch/risc-v/src/rv64gc/up_signal_dispatch.c b/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
similarity index 99%
rename from arch/risc-v/src/rv64gc/up_signal_dispatch.c
rename to arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
index ac83c96..1aa1298 100644
--- a/arch/risc-v/src/rv64gc/up_signal_dispatch.c
+++ b/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
@@ -26,7 +26,7 @@
#include <nuttx/arch.h>
#include "svcall.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
#if (defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
defined(CONFIG_BUILD_KERNEL)
diff --git a/arch/risc-v/src/rv64gc/up_signal_handler.S b/arch/risc-v/src/rv64gc/riscv_signal_handler.S
similarity index 100%
rename from arch/risc-v/src/rv64gc/up_signal_handler.S
rename to arch/risc-v/src/rv64gc/riscv_signal_handler.S
diff --git a/arch/risc-v/src/rv64gc/up_swint.c b/arch/risc-v/src/rv64gc/riscv_swint.c
similarity index 96%
rename from arch/risc-v/src/rv64gc/up_swint.c
rename to arch/risc-v/src/rv64gc/riscv_swint.c
index 0accebf..59c3c4b 100644
--- a/arch/risc-v/src/rv64gc/up_swint.c
+++ b/arch/risc-v/src/rv64gc/riscv_swint.c
@@ -54,7 +54,7 @@
#include "signal/signal.h"
#include "svcall.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Private Functions
@@ -69,13 +69,15 @@ static void up_registerdump(const uint64_t *regs)
{
svcinfo("EPC:%08x\n",
regs[REG_EPC]);
- svcinfo("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n",
+ svcinfo("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x "
+ "A6:%08x A7:%08x\n",
regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3],
regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
svcinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n",
regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3],
regs[REG_T4], regs[REG_T5], regs[REG_T6]);
- svcinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n",
+ svcinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
+ "S6:%08x S7:%08x\n",
regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3],
regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
svcinfo("S8:%08x S9:%08x S10:%08x S11:%08x\n",
@@ -167,7 +169,7 @@ int up_swint(int irq, FAR void *context, FAR void *arg)
{
/* A0=SYS_restore_context: This a restore context command:
*
- * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
+ * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
* At this point, the following values are saved in context:
*
@@ -175,9 +177,9 @@ int up_swint(int irq, FAR void *context, FAR void *arg)
* A1 = restoreregs
*
* In this case, we simply need to set CURRENT_REGS to restore register
- * area referenced in the saved R1. context == CURRENT_REGS is the normal
- * exception return. By setting CURRENT_REGS = context[R1], we force
- * the return to the saved context referenced in $a1.
+ * area referenced in the saved R1. context == CURRENT_REGS is the
+ * normal exception return. By setting CURRENT_REGS = context[R1], we
+ * force the return to the saved context referenced in $a1.
*/
case SYS_restore_context:
@@ -443,7 +445,9 @@ int up_swint(int irq, FAR void *context, FAR void *arg)
break;
}
- /* Report what happened. That might difficult in the case of a context switch */
+ /* Report what happened. That might difficult in the case of a context
+ * switch
+ */
#ifdef CONFIG_DEBUG_SYSCALL_INFO
if (regs != CURRENT_REGS)
diff --git a/arch/risc-v/src/rv64gc/up_testset.S b/arch/risc-v/src/rv64gc/riscv_testset.S
similarity index 100%
rename from arch/risc-v/src/rv64gc/up_testset.S
rename to arch/risc-v/src/rv64gc/riscv_testset.S
diff --git a/arch/risc-v/src/rv64gc/up_unblocktask.c b/arch/risc-v/src/rv64gc/riscv_unblocktask.c
similarity index 99%
rename from arch/risc-v/src/rv64gc/up_unblocktask.c
rename to arch/risc-v/src/rv64gc/riscv_unblocktask.c
index ae0f1c9..142ef0b 100644
--- a/arch/risc-v/src/rv64gc/up_unblocktask.c
+++ b/arch/risc-v/src/rv64gc/riscv_unblocktask.c
@@ -49,7 +49,7 @@
#include "sched/sched.h"
#include "group/group.h"
#include "clock/clock.h"
-#include "up_internal.h"
+#include "riscv_internal.h"
/****************************************************************************
* Public Functions