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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2020/07/30 19:28:09 UTC
[GitHub] [incubator-nuttx] acassis opened a new pull request #1491: xtensa/esp32: Add SPI Flash device driver
acassis opened a new pull request #1491:
URL: https://github.com/apache/incubator-nuttx/pull/1491
ESP32 runs code in a SPI Flash, so users can also use it to store
data directly or mount some parts into a filesystem.
The SPI Flash usually use SPI0.
This driver was implemented by Dong Heng <do...@espressif.com>
and modified to fix coding style by Alan Carvalho de Assis.
## Summary
## Impact
## Testing
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[GitHub] [incubator-nuttx] Ouss4 merged pull request #1491: xtensa/esp32: Add SPI Flash device driver
Posted by GitBox <gi...@apache.org>.
Ouss4 merged pull request #1491:
URL: https://github.com/apache/incubator-nuttx/pull/1491
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[GitHub] [incubator-nuttx] patacongo commented on a change in pull request #1491: xtensa/esp32: Add SPI Flash device driver
Posted by GitBox <gi...@apache.org>.
patacongo commented on a change in pull request #1491:
URL: https://github.com/apache/incubator-nuttx/pull/1491#discussion_r463247483
##########
File path: arch/xtensa/src/esp32/rom/esp32_spiflash.h
##########
@@ -0,0 +1,823 @@
+/*****************************************************************************
+ * arch/xtensa/src/esp32/rom/esp32_spiflash.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *****************************************************************************/
+
+#ifndef _ROM_SPI_FLASH_H_
+#define _ROM_SPI_FLASH_H_
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** \defgroup spi_flash_apis, spi flash operation related apis
+ * @brief spi_flash apis
+ */
+
+/** @addtogroup spi_flash_apis
+ * @{
+ */
+
+/*****************************************************************************
+ * Note
+ *****************************************************************************
+ * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
+ * used as an SPI master to access Flash and ext-SRAM by
+ * Cache module. It will support Decryto read for Flash,
+ * read/write for ext-SRAM. And SPI1 is also used as an
+ * SPI master for Flash read/write and ext-SRAM read/write.
+ * It will support Encrypto write for Flash.
+ * 2. As an SPI master, SPI support Highest clock to 80M,
+ * however, Flash with 80M Clock should be configured
+ * for different Flash chips. If you want to use 80M
+ * clock We should use the SPI that is certified by
+ * Espressif. However, the certification is not started
+ * at the time, so please use 40M clock at the moment.
+ * 3. SPI Flash can use 2 lines or 4 lines mode. If you
+ * use 2 lines mode, you can save two pad SPIHD and
+ * SPIWP for gpio. ESP32 support configured SPI pad for
+ * Flash, the configuration is stored in efuse and flash.
+ * However, the configurations of pads should be certified
+ * by Espressif. If you use this function, please use 40M
+ * clock at the moment.
+ * 4. ESP32 support to use Common SPI command to configure
+ * Flash to QIO mode, if you failed to configure with fix
+ * command. With Common SPI Command, ESP32 can also provide
+ * a way to use same Common SPI command groups on different
+ * Flash chips.
+ * 5. This functions are not protected by packeting, Please use the
+ *****************************************************************************/
+
+#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1)
+#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1)
+#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1)
+#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1)
+#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1)
+#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1)
+#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1)
+#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1)
+#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1)
+#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1)
+#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1)
+#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1)
+
+#define SPI0_R_QIO_DUMMY_CYCLELEN 3
+#define SPI0_R_QIO_ADDR_BITSLEN 31
+#define SPI0_R_FAST_DUMMY_CYCLELEN 7
+#define SPI0_R_DIO_DUMMY_CYCLELEN 1
+#define SPI0_R_DIO_ADDR_BITSLEN 27
+#define SPI0_R_FAST_ADDR_BITSLEN 23
+#define SPI0_R_SIO_ADDR_BITSLEN 23
+
+#define SPI1_R_QIO_DUMMY_CYCLELEN 3
+#define SPI1_R_QIO_ADDR_BITSLEN 31
+#define SPI1_R_FAST_DUMMY_CYCLELEN 7
+#define SPI1_R_DIO_DUMMY_CYCLELEN 3
+#define SPI1_R_DIO_ADDR_BITSLEN 31
+#define SPI1_R_FAST_ADDR_BITSLEN 23
+#define SPI1_R_SIO_ADDR_BITSLEN 23
+
+#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
+
+#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B
+
+/* SPI address register */
+
+#define ESP_ROM_SPIFLASH_BYTES_LEN 24
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f
+
+/* SPI status register */
+
+#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
+#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
+#define ESP_ROM_SPIFLASH_BP0 BIT2
+#define ESP_ROM_SPIFLASH_BP1 BIT3
+#define ESP_ROM_SPIFLASH_BP2 BIT4
+#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|\
+ ESP_ROM_SPIFLASH_BP1|\
+ ESP_ROM_SPIFLASH_BP2)
+#define ESP_ROM_SPIFLASH_QE BIT9
+
+/* Extra dummy for flash read */
+
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2
+
+#define FLASH_ID_GD25LQ32C 0xC86016
+
+typedef enum
+{
+ ESP_ROM_SPIFLASH_QIO_MODE = 0,
+ ESP_ROM_SPIFLASH_QOUT_MODE,
+ ESP_ROM_SPIFLASH_DIO_MODE,
+ ESP_ROM_SPIFLASH_DOUT_MODE,
+ ESP_ROM_SPIFLASH_FASTRD_MODE,
+ ESP_ROM_SPIFLASH_SLOWRD_MODE
+} esp_rom_spiflash_read_mode_t;
+
+typedef enum
+{
+ ESP_ROM_SPIFLASH_RESULT_OK,
+ ESP_ROM_SPIFLASH_RESULT_ERR,
+ ESP_ROM_SPIFLASH_RESULT_TIMEOUT
+} esp_rom_spiflash_result_t;
+
+typedef struct
+{
+ uint32_t device_id;
+ uint32_t chip_size; /* chip size in bytes */
+ uint32_t block_size;
+ uint32_t sector_size;
+ uint32_t page_size;
+ uint32_t status_mask;
+} esp32_spiflash_chip_t;
+
+typedef struct
+{
+ uint8_t data_length;
+ uint8_t read_cmd0;
+ uint8_t read_cmd1;
+ uint8_t write_cmd;
+ uint16_t data_mask;
+ uint16_t data;
+} esp_rom_spiflash_common_cmd_t;
Review comment:
All of the about typedefs belong in a "Public Types", not under "Pre-processor Definitions"
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[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #1491: xtensa/esp32: Add SPI Flash device driver
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on a change in pull request #1491:
URL: https://github.com/apache/incubator-nuttx/pull/1491#discussion_r463237748
##########
File path: arch/xtensa/src/esp32/esp32_spiflash.c
##########
@@ -0,0 +1,1194 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_spiflash.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifdef CONFIG_ESP32_SPIFLASH
+
+#include <stdint.h>
+#include <debug.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/errno.h>
+
+#include <nuttx/mtd/mtd.h>
+
+#include "xtensa.h"
+#include "hardware/esp32_spi.h"
+#include "rom/esp32_spiflash.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define SPI_FLASH_WRITE_BUF_SIZE (32)
+#define SPI_FLASH_READ_BUF_SIZE (64)
+
+#define ESP32_MTD_OFFSET CONFIG_ESP32_MTD_OFFSET
+#define ESP32_MTD_SIZE CONFIG_ESP32_MTD_SIZE
+
+#define MTD2PRIV(_dev) ((FAR struct esp32_spiflash_s *)_dev)
+#define MTD_SIZE(_priv) ((_priv)->chip->chip_size)
+#define MTD_BLKSIZE(_priv) ((_priv)->chip->page_size)
+#define MTD_ERASESIZE(_priv) ((_priv)->chip->sector_size)
+#define MTD_BLK2SIZE(_priv, _b) (MTD_BLKSIZE(_priv) * (_b))
+#define MTD_SIZE2BLK(_priv, _s) ((_s) / MTD_BLKSIZE(_priv))
+
+#ifndef MIN
+# define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* SPI Flash device hardware configuration */
+
+struct esp32_spiflash_config_s
+{
+ /* SPI register base address */
+
+ uint32_t reg_base;
+};
+
+/* SPI Flash device private data */
+
+struct esp32_spiflash_s
+{
+ struct mtd_dev_s mtd;
+
+ /* Port configuration */
+
+ const struct esp32_spiflash_config_s *config;
+
+ /* SPI Flash data */
+
+ esp32_spiflash_chip_t *chip;
+
+ /* SPI Flash communication dummy number */
+
+ uint8_t *dummies;
+};
+
+/****************************************************************************
+ * Private Functions Prototypes
+ ****************************************************************************/
+
+static int esp32_erase(FAR struct mtd_dev_s *dev, off_t startblock,
+ size_t nblocks);
+
+static ssize_t esp32_read(FAR struct mtd_dev_s *dev, off_t offset,
+ size_t nbytes, FAR uint8_t *buffer);
+
+static ssize_t esp32_bread(FAR struct mtd_dev_s *dev, off_t startblock,
+ size_t nblocks, FAR uint8_t *buffer);
+
+static ssize_t esp32_write(FAR struct mtd_dev_s *dev, off_t offset,
+ size_t nbytes, FAR const uint8_t *buffer);
+
+static ssize_t esp32_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
+ size_t nblocks, FAR const uint8_t *buffer);
+
+static int esp32_ioctl(FAR struct mtd_dev_s *dev, int cmd,
+ unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct esp32_spiflash_config_s s_esp32_spiflash1_config =
+{
+ .reg_base = REG_SPI_BASE(1)
+};
+
+static struct esp32_spiflash_s s_esp32_spiflash1 =
+{
+ .mtd =
+ {
+ .erase = esp32_erase,
+ .bread = esp32_bread,
+ .bwrite = esp32_bwrite,
+ .read = esp32_read,
+ .ioctl = esp32_ioctl,
+#if defined(CONFIG_MTD_BYTE_WRITE) && !defined(CONFIG_W25_READONLY)
Review comment:
```suggestion
#if defined(CONFIG_MTD_BYTE_WRITE)
```
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[GitHub] [incubator-nuttx] acassis commented on a change in pull request #1491: xtensa/esp32: Add SPI Flash device driver
Posted by GitBox <gi...@apache.org>.
acassis commented on a change in pull request #1491:
URL: https://github.com/apache/incubator-nuttx/pull/1491#discussion_r463248284
##########
File path: arch/xtensa/src/esp32/rom/esp32_spiflash.h
##########
@@ -0,0 +1,823 @@
+/*****************************************************************************
+ * arch/xtensa/src/esp32/rom/esp32_spiflash.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *****************************************************************************/
+
+#ifndef _ROM_SPI_FLASH_H_
+#define _ROM_SPI_FLASH_H_
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** \defgroup spi_flash_apis, spi flash operation related apis
+ * @brief spi_flash apis
+ */
+
+/** @addtogroup spi_flash_apis
+ * @{
+ */
Review comment:
Ok, I changed almost all Doxygen to NuttX standard, but these two were missed. Thank you Greg!
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[GitHub] [incubator-nuttx] patacongo commented on a change in pull request #1491: xtensa/esp32: Add SPI Flash device driver
Posted by GitBox <gi...@apache.org>.
patacongo commented on a change in pull request #1491:
URL: https://github.com/apache/incubator-nuttx/pull/1491#discussion_r463246880
##########
File path: arch/xtensa/src/esp32/rom/esp32_spiflash.h
##########
@@ -0,0 +1,823 @@
+/*****************************************************************************
+ * arch/xtensa/src/esp32/rom/esp32_spiflash.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *****************************************************************************/
+
+#ifndef _ROM_SPI_FLASH_H_
+#define _ROM_SPI_FLASH_H_
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** \defgroup spi_flash_apis, spi flash operation related apis
+ * @brief spi_flash apis
+ */
+
+/** @addtogroup spi_flash_apis
+ * @{
+ */
Review comment:
Use of Doxygen tags is specifically forbidden by the NuttX coding standard. Please remove lines 36-42 and 815-817.
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[GitHub] [incubator-nuttx] acassis commented on a change in pull request #1491: xtensa/esp32: Add SPI Flash device driver
Posted by GitBox <gi...@apache.org>.
acassis commented on a change in pull request #1491:
URL: https://github.com/apache/incubator-nuttx/pull/1491#discussion_r463256160
##########
File path: arch/xtensa/src/esp32/rom/esp32_spiflash.h
##########
@@ -0,0 +1,823 @@
+/*****************************************************************************
+ * arch/xtensa/src/esp32/rom/esp32_spiflash.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *****************************************************************************/
+
+#ifndef _ROM_SPI_FLASH_H_
+#define _ROM_SPI_FLASH_H_
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** \defgroup spi_flash_apis, spi flash operation related apis
+ * @brief spi_flash apis
+ */
+
+/** @addtogroup spi_flash_apis
+ * @{
+ */
+
+/*****************************************************************************
+ * Note
+ *****************************************************************************
+ * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
+ * used as an SPI master to access Flash and ext-SRAM by
+ * Cache module. It will support Decryto read for Flash,
+ * read/write for ext-SRAM. And SPI1 is also used as an
+ * SPI master for Flash read/write and ext-SRAM read/write.
+ * It will support Encrypto write for Flash.
+ * 2. As an SPI master, SPI support Highest clock to 80M,
+ * however, Flash with 80M Clock should be configured
+ * for different Flash chips. If you want to use 80M
+ * clock We should use the SPI that is certified by
+ * Espressif. However, the certification is not started
+ * at the time, so please use 40M clock at the moment.
+ * 3. SPI Flash can use 2 lines or 4 lines mode. If you
+ * use 2 lines mode, you can save two pad SPIHD and
+ * SPIWP for gpio. ESP32 support configured SPI pad for
+ * Flash, the configuration is stored in efuse and flash.
+ * However, the configurations of pads should be certified
+ * by Espressif. If you use this function, please use 40M
+ * clock at the moment.
+ * 4. ESP32 support to use Common SPI command to configure
+ * Flash to QIO mode, if you failed to configure with fix
+ * command. With Common SPI Command, ESP32 can also provide
+ * a way to use same Common SPI command groups on different
+ * Flash chips.
+ * 5. This functions are not protected by packeting, Please use the
+ *****************************************************************************/
+
+#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1)
+#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1)
+#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1)
+#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1)
+#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1)
+#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1)
+#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1)
+#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1)
+#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1)
+#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1)
+#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1)
+#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1)
+
+#define SPI0_R_QIO_DUMMY_CYCLELEN 3
+#define SPI0_R_QIO_ADDR_BITSLEN 31
+#define SPI0_R_FAST_DUMMY_CYCLELEN 7
+#define SPI0_R_DIO_DUMMY_CYCLELEN 1
+#define SPI0_R_DIO_ADDR_BITSLEN 27
+#define SPI0_R_FAST_ADDR_BITSLEN 23
+#define SPI0_R_SIO_ADDR_BITSLEN 23
+
+#define SPI1_R_QIO_DUMMY_CYCLELEN 3
+#define SPI1_R_QIO_ADDR_BITSLEN 31
+#define SPI1_R_FAST_DUMMY_CYCLELEN 7
+#define SPI1_R_DIO_DUMMY_CYCLELEN 3
+#define SPI1_R_DIO_ADDR_BITSLEN 31
+#define SPI1_R_FAST_ADDR_BITSLEN 23
+#define SPI1_R_SIO_ADDR_BITSLEN 23
+
+#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
+
+#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B
+
+/* SPI address register */
+
+#define ESP_ROM_SPIFLASH_BYTES_LEN 24
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f
+
+/* SPI status register */
+
+#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
+#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
+#define ESP_ROM_SPIFLASH_BP0 BIT2
+#define ESP_ROM_SPIFLASH_BP1 BIT3
+#define ESP_ROM_SPIFLASH_BP2 BIT4
+#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|\
+ ESP_ROM_SPIFLASH_BP1|\
+ ESP_ROM_SPIFLASH_BP2)
+#define ESP_ROM_SPIFLASH_QE BIT9
+
+/* Extra dummy for flash read */
+
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
+#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2
+
+#define FLASH_ID_GD25LQ32C 0xC86016
+
+typedef enum
+{
+ ESP_ROM_SPIFLASH_QIO_MODE = 0,
+ ESP_ROM_SPIFLASH_QOUT_MODE,
+ ESP_ROM_SPIFLASH_DIO_MODE,
+ ESP_ROM_SPIFLASH_DOUT_MODE,
+ ESP_ROM_SPIFLASH_FASTRD_MODE,
+ ESP_ROM_SPIFLASH_SLOWRD_MODE
+} esp_rom_spiflash_read_mode_t;
+
+typedef enum
+{
+ ESP_ROM_SPIFLASH_RESULT_OK,
+ ESP_ROM_SPIFLASH_RESULT_ERR,
+ ESP_ROM_SPIFLASH_RESULT_TIMEOUT
+} esp_rom_spiflash_result_t;
+
+typedef struct
+{
+ uint32_t device_id;
+ uint32_t chip_size; /* chip size in bytes */
+ uint32_t block_size;
+ uint32_t sector_size;
+ uint32_t page_size;
+ uint32_t status_mask;
+} esp32_spiflash_chip_t;
+
+typedef struct
+{
+ uint8_t data_length;
+ uint8_t read_cmd0;
+ uint8_t read_cmd1;
+ uint8_t write_cmd;
+ uint16_t data_mask;
+ uint16_t data;
+} esp_rom_spiflash_common_cmd_t;
Review comment:
Thank you Greg!
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