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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/01/16 15:11:37 UTC
[incubator-nuttx] branch master updated: arch/risc-v: Refine riscv_cpupause.c
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new e97ba17 arch/risc-v: Refine riscv_cpupause.c
e97ba17 is described below
commit e97ba17451d989030b8f01753435294eb9297b64
Author: Huang Qi <hu...@xiaomi.com>
AuthorDate: Sat Jan 15 21:55:36 2022 +0800
arch/risc-v: Refine riscv_cpupause.c
Signed-off-by: Huang Qi <hu...@xiaomi.com>
---
.../k210_cpupause.c => common/riscv_cpupause.c} | 20 +++++---------------
arch/risc-v/src/k210/Make.defs | 4 ++--
arch/risc-v/src/k210/hardware/k210_clint.h | 2 ++
3 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/arch/risc-v/src/k210/k210_cpupause.c b/arch/risc-v/src/common/riscv_cpupause.c
similarity index 94%
rename from arch/risc-v/src/k210/k210_cpupause.c
rename to arch/risc-v/src/common/riscv_cpupause.c
index 40270b7..10d22bd 100644
--- a/arch/risc-v/src/k210/k210_cpupause.c
+++ b/arch/risc-v/src/common/riscv_cpupause.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/k210/k210_cpupause.c
+ * arch/risc-v/src/common/riscv_cpupause.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -40,16 +40,6 @@
#include "chip.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#if 0
-#define DPRINTF(fmt, args...) llinfo(fmt, ##args)
-#else
-#define DPRINTF(fmt, args...) do {} while (0)
-#endif
-
-/****************************************************************************
* Public Data
****************************************************************************/
@@ -193,7 +183,7 @@ int riscv_pause_handler(int irq, void *c, void *arg)
/* Clear machine software interrupt */
- putreg32(0, (uintptr_t)K210_CLINT_MSIP + (4 * cpu));
+ putreg32(0, (uintptr_t)RISCV_CLINT_MSIP + (4 * cpu));
/* Check for false alarms. Such false could occur as a consequence of
* some deadlock breaking logic that might have already serviced the SG2
@@ -243,7 +233,7 @@ int riscv_pause_handler(int irq, void *c, void *arg)
int up_cpu_pause(int cpu)
{
- DPRINTF("cpu=%d\n", cpu);
+ sinfo("cpu=%d\n", cpu);
#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify of the pause event */
@@ -269,7 +259,7 @@ int up_cpu_pause(int cpu)
/* Execute Pause IRQ to CPU(cpu) */
- putreg32(1, (uintptr_t)K210_CLINT_MSIP + (4 * cpu));
+ putreg32(1, (uintptr_t)RISCV_CLINT_MSIP + (4 * cpu));
/* Wait for the other CPU to unlock g_cpu_paused meaning that
* it is fully paused and ready for up_cpu_resume();
@@ -308,7 +298,7 @@ int up_cpu_pause(int cpu)
int up_cpu_resume(int cpu)
{
- DPRINTF("cpu=%d\n", cpu);
+ sinfo("cpu=%d\n", cpu);
#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify of the resume event */
diff --git a/arch/risc-v/src/k210/Make.defs b/arch/risc-v/src/k210/Make.defs
index 45a409e..36c3fb5 100644
--- a/arch/risc-v/src/k210/Make.defs
+++ b/arch/risc-v/src/k210/Make.defs
@@ -36,7 +36,7 @@ CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
CMN_CSRCS += riscv_mdelay.c riscv_copyfullstate.c
ifeq ($(CONFIG_SMP), y)
-CMN_CSRCS += riscv_cpuindex.c
+CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
@@ -59,7 +59,7 @@ CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c
ifeq ($(CONFIG_SMP), y)
CHIP_CSRCS += k210_cpuidlestack.c
-CHIP_CSRCS += k210_cpupause.c k210_cpustart.c
+CHIP_CSRCS += k210_cpustart.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
diff --git a/arch/risc-v/src/k210/hardware/k210_clint.h b/arch/risc-v/src/k210/hardware/k210_clint.h
index a715a07..5c34329 100644
--- a/arch/risc-v/src/k210/hardware/k210_clint.h
+++ b/arch/risc-v/src/k210/hardware/k210_clint.h
@@ -29,4 +29,6 @@
#define K210_CLINT_MTIMECMP (K210_CLINT_BASE + 0x4000)
#define K210_CLINT_MTIME (K210_CLINT_BASE + 0xbff8)
+#define RISCV_CLINT_MSIP K210_CLINT_MSIP
+
#endif /* __ARCH_RISCV_SRC_K210_HARDWARE_K210_CLINT_H */