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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/09/28 01:39:01 UTC
[incubator-nuttx] branch master updated (078a0486f5 -> 41b4af1ec3)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from 078a0486f5 armv7-a: SMP hande all cores start at same time
new bbf3f2866d Fixed non-UTF8 characters.
new 41b4af1ec3 Style fixes.
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/a1x/hardware/a10_memorymap.h | 8 +--
arch/arm/src/armv7-a/arm.h | 8 +--
arch/arm/src/armv7-a/arm_l2cc_pl310.c | 2 +-
arch/arm/src/armv7-a/cp15.h | 10 +--
arch/arm/src/armv7-a/l2cc_pl310.h | 2 +-
arch/arm/src/armv7-a/mmu.h | 10 +--
arch/arm/src/armv7-r/arm_l2cc_pl310.c | 2 +-
arch/arm/src/armv7-r/cp15.h | 2 +-
arch/arm/src/armv7-r/l2cc_pl310.h | 2 +-
arch/arm/src/kinetis/hardware/kinetis_ewm.h | 2 +-
arch/arm/src/kinetis/hardware/kinetis_rngb.h | 2 +-
arch/arm/src/kinetis/hardware/kinetis_tsi.h | 4 +-
arch/arm/src/kinetis/hardware/kinetis_wdog.h | 4 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c | 2 +-
arch/arm/src/lpc31xx/lpc31_analogdie.h | 4 +-
arch/arm/src/lpc31xx/lpc31_bcrndx.c | 2 +-
arch/arm/src/lpc31xx/lpc31_cgu.h | 2 +-
arch/arm/src/lpc31xx/lpc31_cgudrvr.h | 2 +-
arch/arm/src/lpc31xx/lpc31_clkdomain.c | 2 +-
arch/arm/src/lpc31xx/lpc31_clkfreq.c | 2 +-
arch/arm/src/lpc31xx/lpc31_esrndx.c | 2 +-
arch/arm/src/lpc31xx/lpc31_fdcndx.c | 2 +-
arch/arm/src/lpc31xx/lpc31_fdivinit.c | 6 +-
arch/arm/src/lpc31xx/lpc31_pllconfig.c | 2 +-
arch/arm/src/lpc31xx/lpc31_setfreqin.c | 2 +-
arch/arm/src/lpc31xx/lpc31_softreset.c | 2 +-
arch/arm/src/lpc43xx/hardware/lpc43_i2s.h | 4 +-
arch/arm/src/sam34/hardware/sam_rtc.h | 10 +--
arch/arm/src/sama5/hardware/sam_xdmac.h | 4 +-
arch/arm/src/samd2l2/hardware/samd20_memorymap.h | 2 +-
arch/arm/src/samd2l2/hardware/samd20_pinmap.h | 2 +-
arch/arm/src/samd2l2/hardware/samd21_memorymap.h | 2 +-
arch/arm/src/samd2l2/hardware/samd21_pinmap.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_evsys.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_fuses.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_gclk.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_i2c_master.h | 8 +--
arch/arm/src/samd2l2/hardware/samd_i2c_slave.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_nvmctrl.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_pm.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_port.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_sercom.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_spi.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_sysctrl.h | 68 ++++++++++----------
arch/arm/src/samd2l2/hardware/samd_usart.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_wdt.h | 4 +-
arch/arm/src/samd2l2/hardware/saml_i2c_master.h | 6 +-
arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h | 16 ++---
arch/arm/src/samd2l2/hardware/saml_oscctrl.h | 64 +++++++++----------
arch/arm/src/samd2l2/hardware/saml_wdt.h | 2 +-
arch/arm/src/samd2l2/sam_lowputc.c | 2 +-
arch/arm/src/samd2l2/sam_port.c | 2 +-
arch/arm/src/samd2l2/sam_sercom.c | 2 +-
arch/arm/src/samd2l2/samd_clockconfig.c | 4 +-
arch/arm/src/samd5e5/hardware/sam_i2c_master.h | 6 +-
arch/arm/src/samd5e5/hardware/sam_oscctrl.h | 32 +++++-----
arch/arm/src/samd5e5/hardware/sam_wdt.h | 2 +-
arch/arm/src/samv7/hardware/sam_xdmac.h | 4 +-
arch/arm/src/stm32/stm32f30xxx_rcc.c | 2 +-
arch/hc/include/hcs12/irq.h | 2 +-
arch/hc/src/m9s12/chip.h | 48 +++++++-------
arch/mips/include/mips32/cp0.h | 10 +--
arch/mips/include/pic32mx/cp0.h | 2 +-
arch/mips/src/pic32mx/pic32mx_devcfg.h | 2 +-
arch/x86/include/i486/irq.h | 2 +-
arch/z80/include/z180/chip.h | 2 +-
arch/z80/include/z180/irq.h | 4 +-
boards/arm/a1x/pcduino-a10/README.txt | 2 +-
boards/arm/imx6/sabre-6quad/README.txt | 2 +-
boards/arm/kinetis/twr-k60n512/README.txt | 2 +-
boards/arm/lpc31xx/ea3131/src/lpc31_clkinit.c | 2 +-
boards/arm/lpc31xx/ea3131/src/lpc31_mem.c | 16 ++---
boards/arm/lpc31xx/ea3131/tools/lpchdr.h | 10 +--
boards/arm/lpc31xx/ea3152/src/lpc31_clkinit.c | 2 +-
boards/arm/lpc31xx/ea3152/src/lpc31_mem.c | 16 ++---
boards/arm/lpc31xx/ea3152/tools/lpchdr.h | 10 +--
.../lpc31xx/olimex-lpc-h3131/src/lpc31_clkinit.c | 2 +-
boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h | 10 +--
.../arm/sama5/sama5d2-xult/include/board_384mhz.h | 4 +-
.../arm/sama5/sama5d2-xult/include/board_396mhz.h | 2 +-
.../arm/sama5/sama5d2-xult/include/board_528mhz.h | 2 +-
.../arm/sama5/sama5d2-xult/include/board_sdram.h | 2 +-
.../sama5/sama5d3-xplained/include/board_384mhz.h | 4 +-
.../sama5/sama5d3-xplained/include/board_396mhz.h | 2 +-
.../sama5/sama5d3-xplained/include/board_528mhz.h | 2 +-
.../sama5/sama5d3-xplained/include/board_sdram.h | 2 +-
.../arm/sama5/sama5d3-xplained/src/sam_ethernet.c | 4 +-
boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c | 4 +-
.../arm/sama5/sama5d3x-ek/include/board_384mhz.h | 4 +-
.../arm/sama5/sama5d3x-ek/include/board_396mhz.h | 2 +-
.../arm/sama5/sama5d3x-ek/include/board_528mhz.h | 2 +-
boards/arm/sama5/sama5d3x-ek/include/board_sdram.h | 2 +-
boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c | 4 +-
boards/arm/sama5/sama5d4-ek/include/board_384mhz.h | 4 +-
boards/arm/sama5/sama5d4-ek/include/board_396mhz.h | 2 +-
boards/arm/sama5/sama5d4-ek/include/board_528mhz.h | 2 +-
boards/arm/sama5/sama5d4-ek/include/board_sdram.h | 2 +-
boards/arm/sama5/sama5d4-ek/src/sam_sdram.c | 2 +-
boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h | 6 +-
boards/arm/samd2l2/samd20-xplained/README.txt | 8 +--
boards/arm/samd2l2/samd21-xplained/README.txt | 8 +--
.../samd21-xplained/src/sam_ug2832hsweg04.c | 4 +-
boards/arm/samd2l2/saml21-xplained/README.txt | 8 +--
boards/arm/tiva/ekk-lm3s9b96/README.txt | 22 +++----
boards/arm/tiva/lm3s6432-s2e/README.txt | 10 +--
boards/arm/tiva/lm3s8962-ek/README.txt | 20 +++---
boards/arm/tiva/lm4f120-launchpad/README.txt | 20 +++---
boards/avr/at32uc3/avr32dev1/README.txt | 2 +-
boards/avr/at90usb/teensy-2.0/README.txt | 2 +-
boards/hc/m9s12/demo9s12ne64/README.txt | 72 ++++++++++-----------
boards/hc/m9s12/ne64badge/README.txt | 74 +++++++++++-----------
drivers/analog/pga11x.c | 2 +-
drivers/input/stmpe811_temp.c | 2 +-
drivers/lcd/sd1329.h | 20 +++---
drivers/power/battery/max1704x.c | 2 +-
drivers/wireless/spirit/include/spirit_regs.h | 38 +++++------
drivers/wireless/spirit/lib/spirit_pktmbus.c | 4 +-
include/nuttx/binfmt/ieee695.h | 10 +--
include/nuttx/usb/audio.h | 4 +-
include/nuttx/usb/ehci.h | 10 +--
120 files changed, 460 insertions(+), 460 deletions(-)
[incubator-nuttx] 02/02: Style fixes.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 41b4af1ec31e430bcfa330e1aa6ab2d0405d86e6
Author: Fotis Panagiotopoulos <f....@amco.gr>
AuthorDate: Tue Sep 27 17:24:21 2022 +0300
Style fixes.
---
boards/arm/lpc31xx/ea3131/src/lpc31_mem.c | 12 ++++++------
boards/arm/lpc31xx/ea3152/src/lpc31_mem.c | 12 ++++++------
boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c | 4 ++--
boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c | 4 ++--
boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c | 4 ++--
5 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c b/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
index 5c235d3cfb..edd0bdcdb3 100644
--- a/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
+++ b/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
@@ -103,12 +103,12 @@
* pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP.
*
- * "Starting at some point during this 100µs period and continuing at least
- * through the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied. Once the 100µs delay has been satisfied with at least one
- * COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
- * should be applied. All banks must then be precharged, thereby placing
- * the device in the all banks idle state.
+ * "Starting at some point during this 100µs period and continuing at
+ * least through the end of this period, COMMAND INHIBIT or NOP commands
+ * should be applied. Once the 100µs delay has been satisfied with at
+ * least one COMMAND INHIBIT or NOP command having been applied, a
+ * PRECHARGE command should be applied. All banks must then be precharged,
+ * thereby placing the device in the all banks idle state.
*
* "Once in the idle state, two AUTO REFRESH cycles must be performed.
* After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode
diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c b/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c
index 7e9eca4867..b7b94cf60b 100644
--- a/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c
+++ b/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c
@@ -103,12 +103,12 @@
* pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP.
*
- * "Starting at some point during this 100µs period and continuing at least
- * through the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied. Once the 100µs delay has been satisfied with at least one
- * COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
- * should be applied. All banks must then be precharged, thereby placing
- * the device in the all banks idle state.
+ * "Starting at some point during this 100µs period and continuing at
+ * least through the end of this period, COMMAND INHIBIT or NOP commands
+ * should be applied. Once the 100µs delay has been satisfied with at
+ * least one COMMAND INHIBIT or NOP command having been applied, a
+ * PRECHARGE command should be applied. All banks must then be precharged,
+ * thereby placing the device in the all banks idle state.
*
* "Once in the idle state, two AUTO REFRESH cycles must be performed.
* After the AUTO REFRESH cycles are complete, the SDRAM is ready for
diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c b/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c
index c2f971d96c..39bd08c6dd 100644
--- a/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c
+++ b/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c
@@ -166,8 +166,8 @@ void weak_function sam_netinitialize(void)
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential
- * pair signals designated from GRX± and GTx± plus control signals for link
- * activity indicators. These signals can be used to connect to a
+ * pair signals designated from GRX± and GTx± plus control signals for
+ * link activity indicators. These signals can be used to connect to a
* 10/100/1000 BaseT RJ45 connector integrated on the main board.
*
* The KSZ9021/31 interrupt is available on PB35 INT_GETH0
diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c b/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c
index ae3250e0fe..c272fb23e2 100644
--- a/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c
+++ b/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c
@@ -137,8 +137,8 @@ static inline void sam_sdram_delay(unsigned int loops)
* Per the SAMA5D3-Xplained User guide:
* "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte).
* The board includes 2 Gbits of on-board soldered DDR2 (double data rate)
- * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron®
- * for a total of 512 MBytes of DDR2 memory.
+ * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from
+ * Micron® for a total of 512 MBytes of DDR2 memory.
* The memory bus is 32 bits wide and operates with a frequency of up
* to 166 MHz."
*
diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c b/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c
index 85008aab2f..4223f03dfb 100644
--- a/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c
+++ b/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c
@@ -166,8 +166,8 @@ void weak_function sam_netinitialize(void)
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential
- * pair signals designated from GRX± and GTx± plus control signals for link
- * activity indicators. These signals can be used to connect to a
+ * pair signals designated from GRX± and GTx± plus control signals for
+ * link activity indicators. These signals can be used to connect to a
* 10/100/1000 BaseT RJ45 connector integrated on the main board.
*
* The KSZ9021/31 interrupt is available on PB35 INT_GETH0
[incubator-nuttx] 01/02: Fixed non-UTF8 characters.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit bbf3f2866db83fd9f5e2abc2eaf654d359d2e4f9
Author: Fotis Panagiotopoulos <f....@amco.gr>
AuthorDate: Tue Sep 27 15:14:07 2022 +0300
Fixed non-UTF8 characters.
---
arch/arm/src/a1x/hardware/a10_memorymap.h | 8 +--
arch/arm/src/armv7-a/arm.h | 8 +--
arch/arm/src/armv7-a/arm_l2cc_pl310.c | 2 +-
arch/arm/src/armv7-a/cp15.h | 10 +--
arch/arm/src/armv7-a/l2cc_pl310.h | 2 +-
arch/arm/src/armv7-a/mmu.h | 10 +--
arch/arm/src/armv7-r/arm_l2cc_pl310.c | 2 +-
arch/arm/src/armv7-r/cp15.h | 2 +-
arch/arm/src/armv7-r/l2cc_pl310.h | 2 +-
arch/arm/src/kinetis/hardware/kinetis_ewm.h | 2 +-
arch/arm/src/kinetis/hardware/kinetis_rngb.h | 2 +-
arch/arm/src/kinetis/hardware/kinetis_tsi.h | 4 +-
arch/arm/src/kinetis/hardware/kinetis_wdog.h | 4 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c | 2 +-
arch/arm/src/lpc31xx/lpc31_analogdie.h | 4 +-
arch/arm/src/lpc31xx/lpc31_bcrndx.c | 2 +-
arch/arm/src/lpc31xx/lpc31_cgu.h | 2 +-
arch/arm/src/lpc31xx/lpc31_cgudrvr.h | 2 +-
arch/arm/src/lpc31xx/lpc31_clkdomain.c | 2 +-
arch/arm/src/lpc31xx/lpc31_clkfreq.c | 2 +-
arch/arm/src/lpc31xx/lpc31_esrndx.c | 2 +-
arch/arm/src/lpc31xx/lpc31_fdcndx.c | 2 +-
arch/arm/src/lpc31xx/lpc31_fdivinit.c | 6 +-
arch/arm/src/lpc31xx/lpc31_pllconfig.c | 2 +-
arch/arm/src/lpc31xx/lpc31_setfreqin.c | 2 +-
arch/arm/src/lpc31xx/lpc31_softreset.c | 2 +-
arch/arm/src/lpc43xx/hardware/lpc43_i2s.h | 4 +-
arch/arm/src/sam34/hardware/sam_rtc.h | 10 +--
arch/arm/src/sama5/hardware/sam_xdmac.h | 4 +-
arch/arm/src/samd2l2/hardware/samd20_memorymap.h | 2 +-
arch/arm/src/samd2l2/hardware/samd20_pinmap.h | 2 +-
arch/arm/src/samd2l2/hardware/samd21_memorymap.h | 2 +-
arch/arm/src/samd2l2/hardware/samd21_pinmap.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_evsys.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_fuses.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_gclk.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_i2c_master.h | 8 +--
arch/arm/src/samd2l2/hardware/samd_i2c_slave.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_nvmctrl.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_pm.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_port.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_sercom.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_spi.h | 2 +-
arch/arm/src/samd2l2/hardware/samd_sysctrl.h | 68 ++++++++++----------
arch/arm/src/samd2l2/hardware/samd_usart.h | 4 +-
arch/arm/src/samd2l2/hardware/samd_wdt.h | 4 +-
arch/arm/src/samd2l2/hardware/saml_i2c_master.h | 6 +-
arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h | 16 ++---
arch/arm/src/samd2l2/hardware/saml_oscctrl.h | 64 +++++++++----------
arch/arm/src/samd2l2/hardware/saml_wdt.h | 2 +-
arch/arm/src/samd2l2/sam_lowputc.c | 2 +-
arch/arm/src/samd2l2/sam_port.c | 2 +-
arch/arm/src/samd2l2/sam_sercom.c | 2 +-
arch/arm/src/samd2l2/samd_clockconfig.c | 4 +-
arch/arm/src/samd5e5/hardware/sam_i2c_master.h | 6 +-
arch/arm/src/samd5e5/hardware/sam_oscctrl.h | 32 +++++-----
arch/arm/src/samd5e5/hardware/sam_wdt.h | 2 +-
arch/arm/src/samv7/hardware/sam_xdmac.h | 4 +-
arch/arm/src/stm32/stm32f30xxx_rcc.c | 2 +-
arch/hc/include/hcs12/irq.h | 2 +-
arch/hc/src/m9s12/chip.h | 48 +++++++-------
arch/mips/include/mips32/cp0.h | 10 +--
arch/mips/include/pic32mx/cp0.h | 2 +-
arch/mips/src/pic32mx/pic32mx_devcfg.h | 2 +-
arch/x86/include/i486/irq.h | 2 +-
arch/z80/include/z180/chip.h | 2 +-
arch/z80/include/z180/irq.h | 4 +-
boards/arm/a1x/pcduino-a10/README.txt | 2 +-
boards/arm/imx6/sabre-6quad/README.txt | 2 +-
boards/arm/kinetis/twr-k60n512/README.txt | 2 +-
boards/arm/lpc31xx/ea3131/src/lpc31_clkinit.c | 2 +-
boards/arm/lpc31xx/ea3131/src/lpc31_mem.c | 8 +--
boards/arm/lpc31xx/ea3131/tools/lpchdr.h | 10 +--
boards/arm/lpc31xx/ea3152/src/lpc31_clkinit.c | 2 +-
boards/arm/lpc31xx/ea3152/src/lpc31_mem.c | 8 +--
boards/arm/lpc31xx/ea3152/tools/lpchdr.h | 10 +--
.../lpc31xx/olimex-lpc-h3131/src/lpc31_clkinit.c | 2 +-
boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h | 10 +--
.../arm/sama5/sama5d2-xult/include/board_384mhz.h | 4 +-
.../arm/sama5/sama5d2-xult/include/board_396mhz.h | 2 +-
.../arm/sama5/sama5d2-xult/include/board_528mhz.h | 2 +-
.../arm/sama5/sama5d2-xult/include/board_sdram.h | 2 +-
.../sama5/sama5d3-xplained/include/board_384mhz.h | 4 +-
.../sama5/sama5d3-xplained/include/board_396mhz.h | 2 +-
.../sama5/sama5d3-xplained/include/board_528mhz.h | 2 +-
.../sama5/sama5d3-xplained/include/board_sdram.h | 2 +-
.../arm/sama5/sama5d3-xplained/src/sam_ethernet.c | 2 +-
boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c | 2 +-
.../arm/sama5/sama5d3x-ek/include/board_384mhz.h | 4 +-
.../arm/sama5/sama5d3x-ek/include/board_396mhz.h | 2 +-
.../arm/sama5/sama5d3x-ek/include/board_528mhz.h | 2 +-
boards/arm/sama5/sama5d3x-ek/include/board_sdram.h | 2 +-
boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c | 2 +-
boards/arm/sama5/sama5d4-ek/include/board_384mhz.h | 4 +-
boards/arm/sama5/sama5d4-ek/include/board_396mhz.h | 2 +-
boards/arm/sama5/sama5d4-ek/include/board_528mhz.h | 2 +-
boards/arm/sama5/sama5d4-ek/include/board_sdram.h | 2 +-
boards/arm/sama5/sama5d4-ek/src/sam_sdram.c | 2 +-
boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h | 6 +-
boards/arm/samd2l2/samd20-xplained/README.txt | 8 +--
boards/arm/samd2l2/samd21-xplained/README.txt | 8 +--
.../samd21-xplained/src/sam_ug2832hsweg04.c | 4 +-
boards/arm/samd2l2/saml21-xplained/README.txt | 8 +--
boards/arm/tiva/ekk-lm3s9b96/README.txt | 22 +++----
boards/arm/tiva/lm3s6432-s2e/README.txt | 10 +--
boards/arm/tiva/lm3s8962-ek/README.txt | 20 +++---
boards/arm/tiva/lm4f120-launchpad/README.txt | 20 +++---
boards/avr/at32uc3/avr32dev1/README.txt | 2 +-
boards/avr/at90usb/teensy-2.0/README.txt | 2 +-
boards/hc/m9s12/demo9s12ne64/README.txt | 72 ++++++++++-----------
boards/hc/m9s12/ne64badge/README.txt | 74 +++++++++++-----------
drivers/analog/pga11x.c | 2 +-
drivers/input/stmpe811_temp.c | 2 +-
drivers/lcd/sd1329.h | 20 +++---
drivers/power/battery/max1704x.c | 2 +-
drivers/wireless/spirit/include/spirit_regs.h | 38 +++++------
drivers/wireless/spirit/lib/spirit_pktmbus.c | 4 +-
include/nuttx/binfmt/ieee695.h | 10 +--
include/nuttx/usb/audio.h | 4 +-
include/nuttx/usb/ehci.h | 10 +--
120 files changed, 449 insertions(+), 449 deletions(-)
diff --git a/arch/arm/src/a1x/hardware/a10_memorymap.h b/arch/arm/src/a1x/hardware/a10_memorymap.h
index 58fa460db4..40465dc56b 100644
--- a/arch/arm/src/a1x/hardware/a10_memorymap.h
+++ b/arch/arm/src/a1x/hardware/a10_memorymap.h
@@ -46,7 +46,7 @@
#define A1X_SRAMC_PSECTION 0x01d00000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_PSECTION 0x01e00000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
#define A1X_DDR_PSECTION 0x40000000 /* DDR-II/DDR-III 0x4000:0000-0xbfff:ffff 2G */
-#define A1X_BROM_PSECTION 0xfff00000 /* BROM 0xffff:0000�0xffff:7fff 32K */
+#define A1X_BROM_PSECTION 0xfff00000 /* BROM 0xffff:0000-0xffff:7fff 32K */
/* A1X Offsets from the internal memory section base address */
@@ -136,7 +136,7 @@
/* A1X offsets from the BRROM section base address */
-#define A1X_BROM_OFFSET 0x000f0000 /* BROM 0xffff:0000�0xffff:7fff 32K */
+#define A1X_BROM_OFFSET 0x000f0000 /* BROM 0xffff:0000-0xffff:7fff 32K */
/* A1X internal memory physical base addresses */
@@ -239,7 +239,7 @@
#define A1X_PERIPH_SIZE 0x00050000 /* Peripherals 0x01c0:0000-0x01c4:ffff */
#define A1X_SRAMC_SIZE 0x00100000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_SIZE 0x000c0000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
-#define A1X_BROM_SIZE 0x000f8000 /* BROM 0xfff0:0000�0xffff:7fff 32K */
+#define A1X_BROM_SIZE 0x000f8000 /* BROM 0xfff0:0000-0xffff:7fff 32K */
/* Force configured sizes that might exceed 2GB to be unsigned long */
@@ -303,7 +303,7 @@
#define A1X_SRAMC_VSECTION 0x01d00000 /* SRAM C 0x01d0:0000-0x01df:ffff Module sram */
#define A1X_DE_VSECTION 0x01e00000 /* DE, MP, AVG 0x01e0:0000-0x01eb:ffff */
#define A1X_DDR_VSECTION 0x40000000 /* DDR-II/DDR-III 0x4000:0000-0xbfff:ffff 2G */
-#define A1X_BROM_VSECTION 0xfff00000 /* BROM 0xffff:0000�0xffff:7fff 32K */
+#define A1X_BROM_VSECTION 0xfff00000 /* BROM 0xffff:0000-0xffff:7fff 32K */
#endif
diff --git a/arch/arm/src/armv7-a/arm.h b/arch/arm/src/armv7-a/arm.h
index 7ef21e1bfa..8683a318a8 100644
--- a/arch/arm/src/armv7-a/arm.h
+++ b/arch/arm/src/armv7-a/arm.h
@@ -19,10 +19,10 @@
****************************************************************************/
/* References:
- * "Cortex-A5� MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright � 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM� Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright � 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
+ * "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
+ * Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
+ * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
+ * Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* ARM DDI 0406C.b (ID072512)
*/
diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
index 9d9058077f..4338d7dab3 100644
--- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
@@ -18,7 +18,7 @@
*
****************************************************************************/
-/* Reference: "CoreLink� Level 2 Cache Controller L2C-310", Revision r3p2,
+/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*
* NOTE: This logic is incompatible with older versions of the PL310!
diff --git a/arch/arm/src/armv7-a/cp15.h b/arch/arm/src/armv7-a/cp15.h
index 587e883e6a..1e0ce774da 100644
--- a/arch/arm/src/armv7-a/cp15.h
+++ b/arch/arm/src/armv7-a/cp15.h
@@ -20,10 +20,10 @@
/* References:
*
- * "Cortex-A5� MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright � 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM� Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright � 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
+ * "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
+ * Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
+ * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
+ * Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* ARM DDI 0406C.b (ID072512)
*/
@@ -55,7 +55,7 @@
* <CRm> is the operational register
* <Op2> is the Opcode_2 value for the register.
*
- * Reference: Cortex-A5� MPCore, Technical Reference Manual, Paragraph 4.2.
+ * Reference: Cortex-A5 MPCore, Technical Reference Manual, Paragraph 4.2.
*/
#ifdef __ASSEMBLY__
diff --git a/arch/arm/src/armv7-a/l2cc_pl310.h b/arch/arm/src/armv7-a/l2cc_pl310.h
index 26e14035a1..edc8381346 100644
--- a/arch/arm/src/armv7-a/l2cc_pl310.h
+++ b/arch/arm/src/armv7-a/l2cc_pl310.h
@@ -18,7 +18,7 @@
*
****************************************************************************/
-/* Reference: "CoreLink� Level 2 Cache Controller L2C-310", Revision r3p2,
+/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*/
diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h
index 093a56018e..b45671d6f0 100644
--- a/arch/arm/src/armv7-a/mmu.h
+++ b/arch/arm/src/armv7-a/mmu.h
@@ -19,10 +19,10 @@
****************************************************************************/
/* References:
- * "Cortex-A5� MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright � 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM� Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright � 1996-1998, 2000, 2004-2012 ARM.
+ * "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
+ * Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
+ * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
+ * Copyright © 1996-1998, 2000, 2004-2012 ARM.
* All rights reserved. ARM DDI 0406C.b (ID072512)
*/
@@ -62,7 +62,7 @@
/* MMU CP15 Register Bit Definitions ****************************************/
-/* Reference: Cortex-A5� MPCore
+/* Reference: Cortex-A5™ MPCore
* Paragraph 6.7, "MMU software accessible registers."
*/
diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
index c7af8c32b5..885166e91e 100644
--- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
@@ -18,7 +18,7 @@
*
****************************************************************************/
-/* Reference: "CoreLink� Level 2 Cache Controller L2C-310", Revision r3p2,
+/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*
* NOTE: This logic is incompatible with older versions of the PL310!
diff --git a/arch/arm/src/armv7-r/cp15.h b/arch/arm/src/armv7-r/cp15.h
index 074d10314a..fef9b48641 100644
--- a/arch/arm/src/armv7-r/cp15.h
+++ b/arch/arm/src/armv7-r/cp15.h
@@ -52,7 +52,7 @@
* <CRm> is the operational register
* <Op2> is the Opcode_2 value for the register.
*
- * Reference: Cortex-A5� MPCore, Technical Reference Manual, Paragraph 4.2.
+ * Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.2.
*/
#ifdef __ASSEMBLY__
diff --git a/arch/arm/src/armv7-r/l2cc_pl310.h b/arch/arm/src/armv7-r/l2cc_pl310.h
index cdb4546904..da6c4acc11 100644
--- a/arch/arm/src/armv7-r/l2cc_pl310.h
+++ b/arch/arm/src/armv7-r/l2cc_pl310.h
@@ -18,7 +18,7 @@
*
****************************************************************************/
-/* Reference: "CoreLink� Level 2 Cache Controller L2C-310", Revision r3p2,
+/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
*/
diff --git a/arch/arm/src/kinetis/hardware/kinetis_ewm.h b/arch/arm/src/kinetis/hardware/kinetis_ewm.h
index 665b69e8c4..f961fa5c69 100644
--- a/arch/arm/src/kinetis/hardware/kinetis_ewm.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_ewm.h
@@ -54,7 +54,7 @@
#define EWM_CTRL_EWMEN (1 << 0) /* Bit 0: EWM enable */
#define EWM_CTRL_ASSIN (1 << 2) /* Bit 1: EWM_in's Assertion State Select */
#define EWM_CTRL_INEN (1 << 3) /* Bit 2: Input Enable */
- /* Bits 7�3: Reserved */
+ /* Bits 7-3: Reserved */
/* Service Register (8-bit values: 0xb4 followed by 0x2c) */
diff --git a/arch/arm/src/kinetis/hardware/kinetis_rngb.h b/arch/arm/src/kinetis/hardware/kinetis_rngb.h
index 00003bf1be..42e697ee4f 100644
--- a/arch/arm/src/kinetis/hardware/kinetis_rngb.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_rngb.h
@@ -61,7 +61,7 @@
#define RNG_VER_MINOR_MASK (0xff << RNG_VER_MINOR_SHIFT)
#define RNG_VER_MAJOR_SHIFT (8) /* Bits 8-15: Major version number */
#define RNG_VER_MAJOR_MASK (0xff << RNG_VER_MAJOR_SHIFT)
- /* Bits 27�16: Reserved */
+ /* Bits 27-16: Reserved */
#define RNG_VER_TYPE_SHIFT (28) /* Bits 28-31: Random number generator type */
#define RNG_VER_TYPE_MASK (15 << RNG_VER_TYPE_SHIFT)
# define RNG_VER_TYPE_RNGA (0 << RNG_VER_TYPE_SHIFT)
diff --git a/arch/arm/src/kinetis/hardware/kinetis_tsi.h b/arch/arm/src/kinetis/hardware/kinetis_tsi.h
index a2de3b0a01..79b28623dd 100644
--- a/arch/arm/src/kinetis/hardware/kinetis_tsi.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_tsi.h
@@ -199,7 +199,7 @@
#define TSI_SCANC_EXTCHRG_SHIFT (19) /* Bits 19-23: External oscillator charge current select */
#define TSI_SCANC_EXTCHRG_MASK (31 << TSI_SCANC_EXTCHRG_SHIFT)
-# define TSI_SCANC_EXTCHRG_UA(n) (((n)-1) << TSI_SCANC_EXTCHRG_SHIFT) /* n �A charge current, n=1..32 */
+# define TSI_SCANC_EXTCHRG_UA(n) (((n)-1) << TSI_SCANC_EXTCHRG_SHIFT) /* n µA charge current, n=1..32 */
#define TSI_SCANC_CAPTRM_SHIFT (24) /* Bits 24-26: Internal capacitance trim value */
#define TSI_SCANC_CAPTRM_MASK (7 << TSI_SCANC_CAPTRM_SHIFT)
@@ -214,7 +214,7 @@
#define TSI_SCANC_REFCHRG_SHIFT (27) /* Bits 27-31: Reference oscillator charge current select */
#define TSI_SCANC_REFCHRG_MASK (31 << TSI_SCANC_REFCHRG_SHIFT)
-# define TSI_SCANC_REFCHRG_UA(n) (((n)-1) << TSI_SCANC_REFCHRG_SHIFT) /* n �A charge current, n=1..32 */
+# define TSI_SCANC_REFCHRG_UA(n) (((n)-1) << TSI_SCANC_REFCHRG_SHIFT) /* n µA charge current, n=1..32 */
/* Pin enable register */
diff --git a/arch/arm/src/kinetis/hardware/kinetis_wdog.h b/arch/arm/src/kinetis/hardware/kinetis_wdog.h
index 050048cfd5..21adf4e146 100644
--- a/arch/arm/src/kinetis/hardware/kinetis_wdog.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_wdog.h
@@ -67,7 +67,7 @@
/* Watchdog Status and Control Register High (16-bit) */
-#define WDOG_STCTRLH_WDOGEN (1 << 0) /* Bit 0: Enables or disables the WDOG�s operation */
+#define WDOG_STCTRLH_WDOGEN (1 << 0) /* Bit 0: Enables or disables the WDOG's operation */
#define WDOG_STCTRLH_CLKSRC (1 << 1) /* Bit 1: Selects clock source for the WDOG timer */
#define WDOG_STCTRLH_IRQRSTEN (1 << 2) /* Bit 2: Enable the debug breadcrumbs feature */
#define WDOG_STCTRLH_WINEN (1 << 3) /* Bit 3: Enable windowing mode */
@@ -88,7 +88,7 @@
# define WDOG_STCTRLH_BYTESEL_BYTE2 (2 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 2 selected */
# define WDOG_STCTRLH_BYTESEL_BYTE3 (3 << WDOG_STCTRLH_BYTESEL_SHIFT) /* Byte 3 selected */
-#define WDOG_STCTRLH_DISTESTWDOG (1 << 14) /* Bit 14: Disable WDOG�s functional test mode */
+#define WDOG_STCTRLH_DISTESTWDOG (1 << 14) /* Bit 14: Disable WDOG's functional test mode */
/* Bit 15: Reserved */
/* Watchdog Status and Control Register Low (16-bit) */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
index e1729383d3..28b29943fc 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
@@ -613,7 +613,7 @@ void lpc17_40_dmastop(DMA_HANDLE handle)
/* Disable this channel and mask any further interrupts from the channel.
* this channel. The channel is disabled by clearning the channel
- * enable bit. Any outstanding data in the FIFO�s is lost.
+ * enable bit. Any outstanding data in the FIFO's is lost.
*/
regaddr = LPC17_40_DMACH_CONFIG((uint32_t)dmach->chn);
diff --git a/arch/arm/src/lpc31xx/lpc31_analogdie.h b/arch/arm/src/lpc31xx/lpc31_analogdie.h
index a0fcd9b889..ba5e3840fa 100644
--- a/arch/arm/src/lpc31xx/lpc31_analogdie.h
+++ b/arch/arm/src/lpc31xx/lpc31_analogdie.h
@@ -295,9 +295,9 @@
#define CODEC_DEC_DCFILTO (1 << 18) /* Bit 18: Enable DC blocking filter after decimation filters */
#define CODEC_DEC_DBLIN (1 << 17) /* Bit 17: Enable soft start-up after a reset */
#define CODEC_DEC_DELAY_DBLIN (1 << 16) /* Bit 16: Enable delay timer after a reset */
-#define CODEC_DEC_GAINL_SHIFT (8) /* Bits 8-15: Gain settings, LEFT channel (2�s compliment format 0.5dB/bit) */
+#define CODEC_DEC_GAINL_SHIFT (8) /* Bits 8-15: Gain settings, LEFT channel (2's compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINL_MASK (0xff << CODEC_DEC_GAINL_SHIFT)
-#define CODEC_DEC_GAINR_SHIFT (0) /* Bits 0-7: Gain settings RIGHT channel (2�s compliment format 0.5dB/bit) */
+#define CODEC_DEC_GAINR_SHIFT (0) /* Bits 0-7: Gain settings RIGHT channel (2's compliment format 0.5dB/bit) */
#define CODEC_DEC_GAINR_MASK (0xff << CODEC_DEC_GAINR_SHIFT)
/* Interpolator control */
diff --git a/arch/arm/src/lpc31xx/lpc31_bcrndx.c b/arch/arm/src/lpc31xx/lpc31_bcrndx.c
index 20b7403b52..eaf1933e65 100644
--- a/arch/arm/src/lpc31xx/lpc31_bcrndx.c
+++ b/arch/arm/src/lpc31xx/lpc31_bcrndx.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc31xx/lpc31_cgu.h b/arch/arm/src/lpc31xx/lpc31_cgu.h
index 293ad81880..0f8e054df5 100644
--- a/arch/arm/src/lpc31xx/lpc31_cgu.h
+++ b/arch/arm/src/lpc31xx/lpc31_cgu.h
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
*/
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_CGU_H
diff --git a/arch/arm/src/lpc31xx/lpc31_cgudrvr.h b/arch/arm/src/lpc31xx/lpc31_cgudrvr.h
index 40b9287334..ec6822da9e 100644
--- a/arch/arm/src/lpc31xx/lpc31_cgudrvr.h
+++ b/arch/arm/src/lpc31xx/lpc31_cgudrvr.h
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc31xx/lpc31_clkdomain.c b/arch/arm/src/lpc31xx/lpc31_clkdomain.c
index a21e393f72..35b9fe9e9f 100644
--- a/arch/arm/src/lpc31xx/lpc31_clkdomain.c
+++ b/arch/arm/src/lpc31xx/lpc31_clkdomain.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc31xx/lpc31_clkfreq.c b/arch/arm/src/lpc31xx/lpc31_clkfreq.c
index 77cbee56fc..a68713ec61 100644
--- a/arch/arm/src/lpc31xx/lpc31_clkfreq.c
+++ b/arch/arm/src/lpc31xx/lpc31_clkfreq.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc31xx/lpc31_esrndx.c b/arch/arm/src/lpc31xx/lpc31_esrndx.c
index dd7241d055..a80ab08da8 100644
--- a/arch/arm/src/lpc31xx/lpc31_esrndx.c
+++ b/arch/arm/src/lpc31xx/lpc31_esrndx.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc31xx/lpc31_fdcndx.c b/arch/arm/src/lpc31xx/lpc31_fdcndx.c
index 3fff0aaacb..82d9ce671e 100644
--- a/arch/arm/src/lpc31xx/lpc31_fdcndx.c
+++ b/arch/arm/src/lpc31xx/lpc31_fdcndx.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc31xx/lpc31_fdivinit.c b/arch/arm/src/lpc31xx/lpc31_fdivinit.c
index ecdc282be0..18e4259d27 100644
--- a/arch/arm/src/lpc31xx/lpc31_fdivinit.c
+++ b/arch/arm/src/lpc31xx/lpc31_fdivinit.c
@@ -62,7 +62,7 @@
* Say an input frequency of 13 MHz is given while a frequency of 12
* MHz is required. In this case we want a frequency
*
- * f� = 12/13 � f
+ * f' = 12/13 x f
*
* So n = 12 and m = 13. This then gives
*
@@ -77,8 +77,8 @@
* 4 bits. If madd/msub bit width has been set to say 8 bits, it is allowed
* to shift 4 bits, giving:
*
- * msub� = -(12<<4)= -12 � 24 = -12 � 16 = -192
- * madd� = 1<<4 = 24 = 16
+ * msub' = -(12<<4)= -12 x 24 = -12 x 16 = -192
+ * madd' = 1<<4 = 24 = 16
*
****************************************************************************/
diff --git a/arch/arm/src/lpc31xx/lpc31_pllconfig.c b/arch/arm/src/lpc31xx/lpc31_pllconfig.c
index 4bc4bcec30..5cfebad25f 100644
--- a/arch/arm/src/lpc31xx/lpc31_pllconfig.c
+++ b/arch/arm/src/lpc31xx/lpc31_pllconfig.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc31xx/lpc31_setfreqin.c b/arch/arm/src/lpc31xx/lpc31_setfreqin.c
index fe7bc25662..df7a007633 100644
--- a/arch/arm/src/lpc31xx/lpc31_setfreqin.c
+++ b/arch/arm/src/lpc31xx/lpc31_setfreqin.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc31xx/lpc31_softreset.c b/arch/arm/src/lpc31xx/lpc31_softreset.c
index b1d0b27b8c..c7e583caf1 100644
--- a/arch/arm/src/lpc31xx/lpc31_softreset.c
+++ b/arch/arm/src/lpc31xx/lpc31_softreset.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/arch/arm/src/lpc43xx/hardware/lpc43_i2s.h b/arch/arm/src/lpc43xx/hardware/lpc43_i2s.h
index 7f9bdef4ca..af25afccd4 100644
--- a/arch/arm/src/lpc43xx/hardware/lpc43_i2s.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_i2s.h
@@ -113,9 +113,9 @@
#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
/* Bits 15-31: Reserved */
-/* Transmit FIFO: 8 � 32-bit transmit FIFO */
+/* Transmit FIFO: 8 x 32-bit transmit FIFO */
-/* Receive FIFO: 8 � 32-bit receive FIFO */
+/* Receive FIFO: 8 x 32-bit receive FIFO */
/* Status Feedback Register */
diff --git a/arch/arm/src/sam34/hardware/sam_rtc.h b/arch/arm/src/sam34/hardware/sam_rtc.h
index 42d9444db6..5c73406abe 100644
--- a/arch/arm/src/sam34/hardware/sam_rtc.h
+++ b/arch/arm/src/sam34/hardware/sam_rtc.h
@@ -120,11 +120,11 @@
# define RTC_MR_THIGH_31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
# define RTC_MR_THIGH_16MS (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
# define RTC_MR_THIGH_4MS (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
-# define RTC_MR_THIGH_976US (3 << RTC_MR_THIGH_SHIFT) /* 976 �s */
-# define RTC_MR_THIGH_488US (4 << RTC_MR_THIGH_SHIFT) /* 488 �s */
-# define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 �s */
-# define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 �s */
-# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 �s */
+# define RTC_MR_THIGH_976US (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
+# define RTC_MR_THIGH_488US (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
+# define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
+# define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
+# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */
# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT)
diff --git a/arch/arm/src/sama5/hardware/sam_xdmac.h b/arch/arm/src/sama5/hardware/sam_xdmac.h
index f4d1bfe625..5e8fb1314c 100644
--- a/arch/arm/src/sama5/hardware/sam_xdmac.h
+++ b/arch/arm/src/sama5/hardware/sam_xdmac.h
@@ -51,7 +51,7 @@
#define SAM_XDMAC_GSWR_OFFSET 0x0038 /* Global Channel Software Request Register */
#define SAM_XDMAC_GSWS_OFFSET 0x003c /* Global Channel Software Request Status Register */
#define SAM_XDMAC_GSWF_OFFSET 0x0040 /* Global Channel Software Flush Request Register */
- /* 0x0044�0x004c Reserved */
+ /* 0x0044-0x004c Reserved */
/* Offsets to the base of the DMA channel registers */
@@ -92,7 +92,7 @@
#define SAM_XDMACH_CSUS_OFFSET 0x0030 /* Channel Source Microblock Stride */
#define SAM_XDMACH_CDUS_OFFSET 0x0034 /* Channel Destination Microblock Stride */
/* 0x0038-0x003c Reserved */
- /* 0x0fec�0x0ffc Reserved */
+ /* 0x0fec-0x0ffc Reserved */
/* XDMAC Register Addresses *************************************************/
diff --git a/arch/arm/src/samd2l2/hardware/samd20_memorymap.h b/arch/arm/src/samd2l2/hardware/samd20_memorymap.h
index cece10823e..2363b0618f 100644
--- a/arch/arm/src/samd2l2/hardware/samd20_memorymap.h
+++ b/arch/arm/src/samd2l2/hardware/samd20_memorymap.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H
diff --git a/arch/arm/src/samd2l2/hardware/samd20_pinmap.h b/arch/arm/src/samd2l2/hardware/samd20_pinmap.h
index 23c990b0c1..64e6171372 100644
--- a/arch/arm/src/samd2l2/hardware/samd20_pinmap.h
+++ b/arch/arm/src/samd2l2/hardware/samd20_pinmap.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H
diff --git a/arch/arm/src/samd2l2/hardware/samd21_memorymap.h b/arch/arm/src/samd2l2/hardware/samd21_memorymap.h
index 6901392ca0..0db9196b93 100644
--- a/arch/arm/src/samd2l2/hardware/samd21_memorymap.h
+++ b/arch/arm/src/samd2l2/hardware/samd21_memorymap.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H
diff --git a/arch/arm/src/samd2l2/hardware/samd21_pinmap.h b/arch/arm/src/samd2l2/hardware/samd21_pinmap.h
index 4ae16a2066..1fdcd1b86a 100644
--- a/arch/arm/src/samd2l2/hardware/samd21_pinmap.h
+++ b/arch/arm/src/samd2l2/hardware/samd21_pinmap.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_evsys.h b/arch/arm/src/samd2l2/hardware/samd_evsys.h
index 88e1f08a7e..191f6df8b8 100644
--- a/arch/arm/src/samd2l2/hardware/samd_evsys.h
+++ b/arch/arm/src/samd2l2/hardware/samd_evsys.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_fuses.h b/arch/arm/src/samd2l2/hardware/samd_fuses.h
index 413b32def4..d683183477 100644
--- a/arch/arm/src/samd2l2/hardware/samd_fuses.h
+++ b/arch/arm/src/samd2l2/hardware/samd_fuses.h
@@ -41,9 +41,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_gclk.h b/arch/arm/src/samd2l2/hardware/samd_gclk.h
index 75b30e78b3..085bb908d8 100644
--- a/arch/arm/src/samd2l2/hardware/samd_gclk.h
+++ b/arch/arm/src/samd2l2/hardware/samd_gclk.h
@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_i2c_master.h b/arch/arm/src/samd2l2/hardware/samd_i2c_master.h
index 642952cca1..222a525779 100644
--- a/arch/arm/src/samd2l2/hardware/samd_i2c_master.h
+++ b/arch/arm/src/samd2l2/hardware/samd_i2c_master.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H
@@ -203,9 +203,9 @@
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
-# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60�s) */
-# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110�s) */
-# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210�s) */
+# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
+# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
+# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
diff --git a/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h b/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
index 95e086462a..3c85d1b11a 100644
--- a/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
+++ b/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h b/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
index 00c6131ad2..e8b7dc48d5 100644
--- a/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
+++ b/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_pm.h b/arch/arm/src/samd2l2/hardware/samd_pm.h
index 7935af3491..20e3ec76ec 100644
--- a/arch/arm/src/samd2l2/hardware/samd_pm.h
+++ b/arch/arm/src/samd2l2/hardware/samd_pm.h
@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_port.h b/arch/arm/src/samd2l2/hardware/samd_port.h
index 6f85a7822f..9f57077ae8 100644
--- a/arch/arm/src/samd2l2/hardware/samd_port.h
+++ b/arch/arm/src/samd2l2/hardware/samd_port.h
@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_sercom.h b/arch/arm/src/samd2l2/hardware/samd_sercom.h
index 10d935c3ca..bf778b46a6 100644
--- a/arch/arm/src/samd2l2/hardware/samd_sercom.h
+++ b/arch/arm/src/samd2l2/hardware/samd_sercom.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_spi.h b/arch/arm/src/samd2l2/hardware/samd_spi.h
index 9b8b7fb5ab..ceccd9e14a 100644
--- a/arch/arm/src/samd2l2/hardware/samd_spi.h
+++ b/arch/arm/src/samd2l2/hardware/samd_spi.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_sysctrl.h b/arch/arm/src/samd2l2/hardware/samd_sysctrl.h
index 20dd512b9e..c20132cff4 100644
--- a/arch/arm/src/samd2l2/hardware/samd_sysctrl.h
+++ b/arch/arm/src/samd2l2/hardware/samd_sysctrl.h
@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H
@@ -154,22 +154,22 @@
#define SYSCTRL_XOSC_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define SYSCTRL_XOSC_STARTUP_MASK (15 << SYSCTRL_XOSC_STARTUP_SHIFT)
# define SYSCTRL_XOSC_STARTUP(n) ((n) << SYSCTRL_XOSC_STARTUP_SHIFT)
-# define SYSCTRL_XOSC_STARTUP_31US (0 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31�s */
-# define SYSCTRL_XOSC_STARTUP_61US (1 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 61�s */
-# define SYSCTRL_XOSC_STARTUP_122US (2 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 122�s */
-# define SYSCTRL_XOSC_STARTUP_244US (3 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 244�s */
-# define SYSCTRL_XOSC_STARTUP_488US (4 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 488�s */
-# define SYSCTRL_XOSC_STARTUP_977US (5 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 977�s */
-# define SYSCTRL_XOSC_STARTUP_2MS (6 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1953�s */
-# define SYSCTRL_XOSC_STARTUP_4MS (7 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 3906�s */
-# define SYSCTRL_XOSC_STARTUP_8MS (8 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 7813�s */
-# define SYSCTRL_XOSC_STARTUP_16MS (9 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 15625�s */
-# define SYSCTRL_XOSC_STARTUP_31MS (10 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31250�s */
-# define SYSCTRL_XOSC_STARTUP_63MS (11 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 62500�s */
-# define SYSCTRL_XOSC_STARTUP_125MS (12 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 125000�s */
-# define SYSCTRL_XOSC_STARTUP_250MS (13 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 250000�s */
-# define SYSCTRL_XOSC_STARTUP_500MS (14 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 500000�s */
-# define SYSCTRL_XOSC_STARTUP_1S (15 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1000000�s */
+# define SYSCTRL_XOSC_STARTUP_31US (0 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31µs */
+# define SYSCTRL_XOSC_STARTUP_61US (1 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 61µs */
+# define SYSCTRL_XOSC_STARTUP_122US (2 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 122µs */
+# define SYSCTRL_XOSC_STARTUP_244US (3 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 244µs */
+# define SYSCTRL_XOSC_STARTUP_488US (4 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 488µs */
+# define SYSCTRL_XOSC_STARTUP_977US (5 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 977µs */
+# define SYSCTRL_XOSC_STARTUP_2MS (6 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1953µs */
+# define SYSCTRL_XOSC_STARTUP_4MS (7 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 3906µs */
+# define SYSCTRL_XOSC_STARTUP_8MS (8 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 7813µs */
+# define SYSCTRL_XOSC_STARTUP_16MS (9 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 15625µs */
+# define SYSCTRL_XOSC_STARTUP_31MS (10 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 31250µs */
+# define SYSCTRL_XOSC_STARTUP_63MS (11 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 62500µs */
+# define SYSCTRL_XOSC_STARTUP_125MS (12 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 125000µs */
+# define SYSCTRL_XOSC_STARTUP_250MS (13 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 250000µs */
+# define SYSCTRL_XOSC_STARTUP_500MS (14 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 500000µs */
+# define SYSCTRL_XOSC_STARTUP_1S (15 << SYSCTRL_XOSC_STARTUP_SHIFT) /* 1000000µs */
/* 32kHz external crystal oscillator control register */
@@ -183,14 +183,14 @@
#define SYSCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define SYSCTRL_XOSC32K_STARTUP_MASK (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT)
# define SYSCTRL_XOSC32K_STARTUP(n) ((n) << SYSCTRL_XOSC32K_STARTUP_SHIFT)
-# define SYSCTRL_XOSC32K_STARTUP_122US (0 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 122�s */
-# define SYSCTRL_XOSC32K_STARTUP_1MS (1 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1068�s */
-# define SYSCTRL_XOSC32K_STARTUP_63MS (2 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 62592�s */
-# define SYSCTRL_XOSC32K_STARTUP_125MS (3 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 125092�s */
-# define SYSCTRL_XOSC32K_STARTUP_500MS (4 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 500092�s */
-# define SYSCTRL_XOSC32K_STARTUP_1S (5 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1000092�s */
-# define SYSCTRL_XOSC32K_STARTUP_2S (6 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 2000092�s */
-# define SYSCTRL_XOSC32K_STARTUP_4S (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 4000092�s */
+# define SYSCTRL_XOSC32K_STARTUP_122US (0 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 122µs */
+# define SYSCTRL_XOSC32K_STARTUP_1MS (1 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1068µs */
+# define SYSCTRL_XOSC32K_STARTUP_63MS (2 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 62592µs */
+# define SYSCTRL_XOSC32K_STARTUP_125MS (3 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 125092µs */
+# define SYSCTRL_XOSC32K_STARTUP_500MS (4 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 500092µs */
+# define SYSCTRL_XOSC32K_STARTUP_1S (5 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 1000092µs */
+# define SYSCTRL_XOSC32K_STARTUP_2S (6 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 2000092µs */
+# define SYSCTRL_XOSC32K_STARTUP_4S (7 << SYSCTRL_XOSC32K_STARTUP_SHIFT) /* 4000092µs */
#define SYSCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
@@ -208,14 +208,14 @@
#define SYSCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define SYSCTRL_OSC32K_STARTUP_MASK (7 << SYSCTRL_OSC32K_STARTUP_SHIFT)
# define SYSCTRL_OSC32K_STARTUP(n) ((n) << SYSCTRL_OSC32K_STARTUP_SHIFT)
-# define SYSCTRL_OSC32K_STARTUP_92US (0 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 92�s */
-# define SYSCTRL_OSC32K_STARTUP_122US (1 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 122�s */
-# define SYSCTRL_OSC32K_STARTUP_183US (2 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 183�s */
-# define SYSCTRL_OSC32K_STARTUP_305US (3 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 305�s */
-# define SYSCTRL_OSC32K_STARTUP_549US (4 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 549�s */
-# define SYSCTRL_OSC32K_STARTUP_1MS (5 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 1038�s */
-# define SYSCTRL_OSC32K_STARTUP_2MS (6 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 2014�s */
-# define SYSCTRL_OSC32K_STARTUP_4MS (7 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 3967�s */
+# define SYSCTRL_OSC32K_STARTUP_92US (0 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
+# define SYSCTRL_OSC32K_STARTUP_122US (1 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
+# define SYSCTRL_OSC32K_STARTUP_183US (2 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
+# define SYSCTRL_OSC32K_STARTUP_305US (3 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
+# define SYSCTRL_OSC32K_STARTUP_549US (4 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
+# define SYSCTRL_OSC32K_STARTUP_1MS (5 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
+# define SYSCTRL_OSC32K_STARTUP_2MS (6 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
+# define SYSCTRL_OSC32K_STARTUP_4MS (7 << SYSCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
#define SYSCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define SYSCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */
diff --git a/arch/arm/src/samd2l2/hardware/samd_usart.h b/arch/arm/src/samd2l2/hardware/samd_usart.h
index 4bad8d3a12..c92252ab60 100644
--- a/arch/arm/src/samd2l2/hardware/samd_usart.h
+++ b/arch/arm/src/samd2l2/hardware/samd_usart.h
@@ -20,9 +20,9 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H
diff --git a/arch/arm/src/samd2l2/hardware/samd_wdt.h b/arch/arm/src/samd2l2/hardware/samd_wdt.h
index 52c2aed9df..3300e31757 100644
--- a/arch/arm/src/samd2l2/hardware/samd_wdt.h
+++ b/arch/arm/src/samd2l2/hardware/samd_wdt.h
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H
@@ -72,7 +72,7 @@
/* Configuration register */
-#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0�3: Time-Out Period */
+#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0-3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */
diff --git a/arch/arm/src/samd2l2/hardware/saml_i2c_master.h b/arch/arm/src/samd2l2/hardware/saml_i2c_master.h
index 15fda6fc03..5221cbabaa 100644
--- a/arch/arm/src/samd2l2/hardware/saml_i2c_master.h
+++ b/arch/arm/src/samd2l2/hardware/saml_i2c_master.h
@@ -164,9 +164,9 @@
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
-# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60�s) */
-# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110�s) */
-# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210�s) */
+# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
+# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
+# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
diff --git a/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h b/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
index 9bfbee3d38..b1b6339ca7 100644
--- a/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
+++ b/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
@@ -115,14 +115,14 @@
#define OSC32KCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define OSC32KCTRL_OSC32K_STARTUP_MASK (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT)
# define OSC32KCTRL_OSC32K_STARTUP(n) ((n) << OSC32KCTRL_OSC32K_STARTUP_SHIFT)
-# define OSC32KCTRL_OSC32K_STARTUP_92US (0 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 92�s */
-# define OSC32KCTRL_OSC32K_STARTUP_122US (1 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 122�s */
-# define OSC32KCTRL_OSC32K_STARTUP_183US (2 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 183�s */
-# define OSC32KCTRL_OSC32K_STARTUP_305US (3 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 305�s */
-# define OSC32KCTRL_OSC32K_STARTUP_549US (4 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 549�s */
-# define OSC32KCTRL_OSC32K_STARTUP_1MS (5 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 1038�s */
-# define OSC32KCTRL_OSC32K_STARTUP_2MS (6 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 2014�s */
-# define OSC32KCTRL_OSC32K_STARTUP_4MS (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 3967�s */
+# define OSC32KCTRL_OSC32K_STARTUP_92US (0 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
+# define OSC32KCTRL_OSC32K_STARTUP_122US (1 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
+# define OSC32KCTRL_OSC32K_STARTUP_183US (2 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
+# define OSC32KCTRL_OSC32K_STARTUP_305US (3 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
+# define OSC32KCTRL_OSC32K_STARTUP_549US (4 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
+# define OSC32KCTRL_OSC32K_STARTUP_1MS (5 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
+# define OSC32KCTRL_OSC32K_STARTUP_2MS (6 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
+# define OSC32KCTRL_OSC32K_STARTUP_4MS (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
#define OSC32KCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define OSC32KCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */
diff --git a/arch/arm/src/samd2l2/hardware/saml_oscctrl.h b/arch/arm/src/samd2l2/hardware/saml_oscctrl.h
index f2b33db71e..54efc40c1e 100644
--- a/arch/arm/src/samd2l2/hardware/saml_oscctrl.h
+++ b/arch/arm/src/samd2l2/hardware/saml_oscctrl.h
@@ -117,22 +117,22 @@
#define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP(n) ((n) << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
-# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000�s */
+# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
/* 16MHz internal oscillator control register */
@@ -159,22 +159,22 @@
#define OSCCTRL_OSC16MCTRL_STARTUP_SHIFT (12) /* Bits 12-15: Start-up time */
#define OSCCTRL_OSC16MCTRL_STARTUP_MASK (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT)
# define OSCCTRL_OSC16MCTRL_STARTUP(n) ((n) << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT)
-# define OSCCTRL_OSC16MCTRL_STARTUP_31US (0 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_61US (1 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 61�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_122US (2 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 122�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_244US (3 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 244�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_488US (4 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 488�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_977US (5 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 977�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_2MS (6 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1953�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_4MS (7 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 3906�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_8MS (8 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 7813�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_16MS (9 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 15625�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_31MS (10 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31250�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_63MS (11 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 62500�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_125MS (12 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 125000�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_250MS (13 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 250000�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_500MS (14 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 500000�s */
-# define OSCCTRL_OSC16MCTRL_STARTUP_1S (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1000000�s */
+# define OSCCTRL_OSC16MCTRL_STARTUP_31US (0 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_61US (1 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 61µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_122US (2 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 122µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_244US (3 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 244µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_488US (4 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 488µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_977US (5 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 977µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_2MS (6 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1953µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_4MS (7 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 3906µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_8MS (8 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 7813µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_16MS (9 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 15625µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_31MS (10 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 31250µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_63MS (11 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 62500µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_125MS (12 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 125000µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_250MS (13 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 250000µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_500MS (14 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 500000µs */
+# define OSCCTRL_OSC16MCTRL_STARTUP_1S (15 << OSCCTRL_OSC16MCTRL_STARTUP_SHIFT) /* 1000000µs */
/* DFLL48M control register */
diff --git a/arch/arm/src/samd2l2/hardware/saml_wdt.h b/arch/arm/src/samd2l2/hardware/saml_wdt.h
index 7d6d32f95e..32d515a4b8 100644
--- a/arch/arm/src/samd2l2/hardware/saml_wdt.h
+++ b/arch/arm/src/samd2l2/hardware/saml_wdt.h
@@ -72,7 +72,7 @@
/* Configuration register */
-#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0�3: Time-Out Period */
+#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0-3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */
diff --git a/arch/arm/src/samd2l2/sam_lowputc.c b/arch/arm/src/samd2l2/sam_lowputc.c
index 6741a3995a..f393516063 100644
--- a/arch/arm/src/samd2l2/sam_lowputc.c
+++ b/arch/arm/src/samd2l2/sam_lowputc.c
@@ -20,7 +20,7 @@
/* References:
* 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* 2. Atmel sample code. This code has an ASF license with is compatible
* with the NuttX BSD license, but includes the provision that this
* code not be used in non-Atmel products. That sample code was used
diff --git a/arch/arm/src/samd2l2/sam_port.c b/arch/arm/src/samd2l2/sam_port.c
index 0734d4ad04..b8cf604719 100644
--- a/arch/arm/src/samd2l2/sam_port.c
+++ b/arch/arm/src/samd2l2/sam_port.c
@@ -20,7 +20,7 @@
/* References:
* "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
/****************************************************************************
diff --git a/arch/arm/src/samd2l2/sam_sercom.c b/arch/arm/src/samd2l2/sam_sercom.c
index edebcd3bd2..d7f42b2f51 100644
--- a/arch/arm/src/samd2l2/sam_sercom.c
+++ b/arch/arm/src/samd2l2/sam_sercom.c
@@ -20,7 +20,7 @@
/* References:
* 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
*/
/****************************************************************************
diff --git a/arch/arm/src/samd2l2/samd_clockconfig.c b/arch/arm/src/samd2l2/samd_clockconfig.c
index 57356836d9..cdcc9ac06f 100644
--- a/arch/arm/src/samd2l2/samd_clockconfig.c
+++ b/arch/arm/src/samd2l2/samd_clockconfig.c
@@ -20,9 +20,9 @@
/* References:
* 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller
- * Datasheet", 42129J�SAM�12/2013
+ * Datasheet", 42129J-SAM-12/2013
* 2. "Atmel SAM D21E / SAM D21G / SAM D21J SMART ARM-Based Microcontroller
- * Datasheet", Atmel-42181E�SAM-D21_Datasheet�02/2015
+ * Datasheet", Atmel-42181E-SAM-D21_Datasheet-02/2015
* 3. Atmel sample code for the SAMD20. This code has an ASF license
* with is compatible with the NuttX BSD license, but includes the
* provision that this code not be used in non-Atmel products. That
diff --git a/arch/arm/src/samd5e5/hardware/sam_i2c_master.h b/arch/arm/src/samd5e5/hardware/sam_i2c_master.h
index f836d883bc..091fab06e8 100644
--- a/arch/arm/src/samd5e5/hardware/sam_i2c_master.h
+++ b/arch/arm/src/samd5e5/hardware/sam_i2c_master.h
@@ -184,9 +184,9 @@
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
-# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60�s) */
-# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110�s) */
-# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210�s) */
+# define I2C_CTRLA_INACTOUT_55US (1 << I2C_CTRLA_INACTOUT_SHIFT) /* 5-6 SCL cycle time-out (50-60µs) */
+# define I2C_CTRLA_INACTOUT_105US (2 << I2C_CTRLA_INACTOUT_SHIFT) /* 10-11 SCL cycle time-out (100-110µs) */
+# define I2C_CTRLA_INACTOUT_205US (3 << I2C_CTRLA_INACTOUT_SHIFT) /* 20-21 SCL cycle time-out (200-210µs) */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
/* Control B register */
diff --git a/arch/arm/src/samd5e5/hardware/sam_oscctrl.h b/arch/arm/src/samd5e5/hardware/sam_oscctrl.h
index 553dd85c67..2da4336f87 100644
--- a/arch/arm/src/samd5e5/hardware/sam_oscctrl.h
+++ b/arch/arm/src/samd5e5/hardware/sam_oscctrl.h
@@ -153,22 +153,22 @@
#define OSCCTRL_XOSCCTRL_STARTUP_SHIFT (20) /* Bits 20-23: Start-up time */
#define OSCCTRL_XOSCCTRL_STARTUP_MASK (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
# define OSCCTRL_XOSCCTRL_STARTUP(n) ((n) << OSCCTRL_XOSCCTRL_STARTUP_SHIFT)
-# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000�s */
-# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000�s */
+# define OSCCTRL_XOSCCTRL_STARTUP_31US (0 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_61US (1 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 61µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_122US (2 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 122µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_244US (3 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 244µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_488US (4 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 488µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_977US (5 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 977µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_2MS (6 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1953µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_4MS (7 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 3906µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_8MS (8 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 7813µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_16MS (9 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 15625µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_31MS (10 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 31250µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_63MS (11 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 62500µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_125MS (12 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 125000µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_250MS (13 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 250000µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_500MS (14 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 500000µs */
+# define OSCCTRL_XOSCCTRL_STARTUP_1S (15 << OSCCTRL_XOSCCTRL_STARTUP_SHIFT) /* 1000000µs */
#define OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT (24) /* Bits 24-27: Clock Failure Detector Prescaler */
#define OSCCTRL_XOSCCTRL_CFDPRESC_MASK (15 << OSCCTRL_XOSCCTRL_CFDPRESC_SHIFT)
diff --git a/arch/arm/src/samd5e5/hardware/sam_wdt.h b/arch/arm/src/samd5e5/hardware/sam_wdt.h
index 80cda66cd5..fdf3dd11f2 100644
--- a/arch/arm/src/samd5e5/hardware/sam_wdt.h
+++ b/arch/arm/src/samd5e5/hardware/sam_wdt.h
@@ -65,7 +65,7 @@
/* Configuration register */
-#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0�3: Time-Out Period */
+#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0-3: Time-Out Period */
#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */
diff --git a/arch/arm/src/samv7/hardware/sam_xdmac.h b/arch/arm/src/samv7/hardware/sam_xdmac.h
index d0010fe3ce..c1be36a7e8 100644
--- a/arch/arm/src/samv7/hardware/sam_xdmac.h
+++ b/arch/arm/src/samv7/hardware/sam_xdmac.h
@@ -51,7 +51,7 @@
#define SAM_XDMAC_GSWR_OFFSET 0x0038 /* Global Channel Software Request Register */
#define SAM_XDMAC_GSWS_OFFSET 0x003c /* Global Channel Software Request Status Register */
#define SAM_XDMAC_GSWF_OFFSET 0x0040 /* Global Channel Software Flush Request Register */
- /* 0x0044�0x004c Reserved */
+ /* 0x0044-0x004c Reserved */
/* Offsets to the base of the DMA channel registers */
@@ -100,7 +100,7 @@
#define SAM_XDMACH_CSUS_OFFSET 0x0030 /* Channel Source Microblock Stride */
#define SAM_XDMACH_CDUS_OFFSET 0x0034 /* Channel Destination Microblock Stride */
/* 0x0038-0x003c Reserved */
- /* 0x0fec�0x0ffc Reserved */
+ /* 0x0fec-0x0ffc Reserved */
/* XDMAC Register Addresses *************************************************/
diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32/stm32f30xxx_rcc.c
index ee7212cc43..f18af94a00 100644
--- a/arch/arm/src/stm32/stm32f30xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f30xxx_rcc.c
@@ -186,7 +186,7 @@ static inline void rcc_enableapb1(void)
#ifdef CONFIG_STM32_USB
/* USB clock divider. This bit must be valid before enabling the USB
- * clock in the RCC_APB1ENR register. This bit can�t be reset if the USB
+ * clock in the RCC_APB1ENR register. This bit can't be reset if the USB
* clock is enabled.
*/
diff --git a/arch/hc/include/hcs12/irq.h b/arch/hc/include/hcs12/irq.h
index 713765fcaa..007108411a 100644
--- a/arch/hc/include/hcs12/irq.h
+++ b/arch/hc/include/hcs12/irq.h
@@ -39,7 +39,7 @@
/* CCR bit definitions */
#define HCS12_CCR_C (1 << 0) /* Bit 0: Carry/Borrow status bit */
-#define HCS12_CCR_V (1 << 1) /* Bit 1: Two�s complement overflow status bit */
+#define HCS12_CCR_V (1 << 1) /* Bit 1: Two's complement overflow status bit */
#define HCS12_CCR_Z (1 << 2) /* Bit 2: Zero status bit */
#define HCS12_CCR_N (1 << 3) /* Bit 3: Negative status bit */
#define HCS12_CCR_I (1 << 4) /* Bit 4: Maskable interrupt control bit */
diff --git a/arch/hc/src/m9s12/chip.h b/arch/hc/src/m9s12/chip.h
index 70473e2cac..a6710e8b54 100644
--- a/arch/hc/src/m9s12/chip.h
+++ b/arch/hc/src/m9s12/chip.h
@@ -34,8 +34,8 @@
/* Memory Map.
*
* At reset:
- * 0x0000�0x03ff: register space
- * 0x0000�0x1fff: 7K RAM (1K RAM hidden behind register space)
+ * 0x0000-0x03ff: register space
+ * 0x0000-0x1fff: 7K RAM (1K RAM hidden behind register space)
*/
#define HCS12_REG_BASE 0x0000 /* 0x0000-0x03ff: Mapped Register base address */
@@ -47,30 +47,30 @@
/* Device Register Map Overview (all relative to HCS12_REG_BASE) */
-#define HCS12_CORE1_BASE 0x0000 /* 0x0000�0x0017: Ports A, B, E, Modes, Inits (MMC, INT, MEBI) */
- /* 0x0018�0x0019: Reserved */
+#define HCS12_CORE1_BASE 0x0000 /* 0x0000-0x0017: Ports A, B, E, Modes, Inits (MMC, INT, MEBI) */
+ /* 0x0018-0x0019: Reserved */
#define HCS12_DEVID_BASE 0x001a /* 0x001a-0x001b: Device ID register (PARTID) */
-#define HCS12_CORE2_BASE 0x001c /* 0x001c�0x001f: MEMSIZ, IRQ, HPRIO (INT, MMC) */
+#define HCS12_CORE2_BASE 0x001c /* 0x001c-0x001f: MEMSIZ, IRQ, HPRIO (INT, MMC) */
#define HCS12_CORE3_BASE 0x0020 /* 0x0020-0x002f: DBG */
-#define HCS12_CORE4_BASE 0x0030 /* 0x0030�0x0033: PPAGE, Port K (MEBI, MMC) */
-#define HCS12_CRG_BASE 0x0034 /* 0x0034�0x003f: Clock and Reset Generator (PLL, RTI, COP) */
-#define HCS12_TIM_BASE 0x0040 /* 0x0040�0x006f: Standard Timer 16-bit 4 channels (TIM) */
- /* 0x0070�0x007f: Reserved */
-#define HCS12_ATD_BASE 0x0080 /* 0x0080�0x009f: Analog-to-Digital Converter 10-bit, 8-channel (ATD) */
- /* 0x00a0�0x00c7: Reserved */
-#define HCS12_SCI0_BASE 0x00c8 /* 0x00c8�0x00cf: Serial Communications Interface 0 (SCI0) */
-#define HCS12_SCI1_BASE 0x00d0 /* 0x00d0�0x00d7: Serial Communications Interface 1 (SCI1) */o
-#define HCS12_SPI_BASE 0x00d8 /* 0x00d8�0x00df: Serial Peripheral Interface (SPI) */
-#define HCS12_IIC_BASE 0x00e0 /* 0x00e0�0x00e7: Inter IC Bus (IIC) */
- /* 0x00e8�0x00ff: Reserved */
-#define HCS12_FLASH_BASE 0x0100 /* 0x0100�0x010f: FLASH Control Register */
- /* 0x0110�0x011f: Reserved */
-#define HCS12_EPHY_BASE 0x0120 /* 0x0120�0x0123: Ethernet Physical Interface (EPHY) */
- /* 0x0124�0x013f: Reserved */
-#define HCS12_EMAC_BASE 0x0140 /* 0x0140�0x016f: Ethernet Media Access Controller (EMAC) */
- /* 0x0170�0x023f: Reserved */
-#define HCS12_PIM_BASE 0x0240 /* 0x0240�0x026f: Port Integration Module (PIM) */
- /* 0x0270�0x03ff: Reserved */
+#define HCS12_CORE4_BASE 0x0030 /* 0x0030-0x0033: PPAGE, Port K (MEBI, MMC) */
+#define HCS12_CRG_BASE 0x0034 /* 0x0034-0x003f: Clock and Reset Generator (PLL, RTI, COP) */
+#define HCS12_TIM_BASE 0x0040 /* 0x0040-0x006f: Standard Timer 16-bit 4 channels (TIM) */
+ /* 0x0070-0x007f: Reserved */
+#define HCS12_ATD_BASE 0x0080 /* 0x0080-0x009f: Analog-to-Digital Converter 10-bit, 8-channel (ATD) */
+ /* 0x00a0-0x00c7: Reserved */
+#define HCS12_SCI0_BASE 0x00c8 /* 0x00c8-0x00cf: Serial Communications Interface 0 (SCI0) */
+#define HCS12_SCI1_BASE 0x00d0 /* 0x00d0-0x00d7: Serial Communications Interface 1 (SCI1) */o
+#define HCS12_SPI_BASE 0x00d8 /* 0x00d8-0x00df: Serial Peripheral Interface (SPI) */
+#define HCS12_IIC_BASE 0x00e0 /* 0x00e0-0x00e7: Inter IC Bus (IIC) */
+ /* 0x00e8-0x00ff: Reserved */
+#define HCS12_FLASH_BASE 0x0100 /* 0x0100-0x010f: FLASH Control Register */
+ /* 0x0110-0x011f: Reserved */
+#define HCS12_EPHY_BASE 0x0120 /* 0x0120-0x0123: Ethernet Physical Interface (EPHY) */
+ /* 0x0124-0x013f: Reserved */
+#define HCS12_EMAC_BASE 0x0140 /* 0x0140-0x016f: Ethernet Media Access Controller (EMAC) */
+ /* 0x0170-0x023f: Reserved */
+#define HCS12_PIM_BASE 0x0240 /* 0x0240-0x026f: Port Integration Module (PIM) */
+ /* 0x0270-0x03ff: Reserved */
/****************************************************************************
* Public Types
diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h
index 9d702ddc5c..73d6f8333e 100644
--- a/arch/mips/include/mips32/cp0.h
+++ b/arch/mips/include/mips32/cp0.h
@@ -41,7 +41,7 @@
# define MIPS32_CP0_ENTRYLO11 $3,0 /* LS TLB entry for odd-numbered pages */
# define MIPS32_CP0_CONTEXT2 $4,0 /* Page table address */
# define MIPS32_CP0_PAGEMASK1 $5,0 /* Variable page sizes in TLB entries */
-# define MIPS32_CP0_WIRED1 $6,0 /* umber of fixed (�wired�) TLB entries */
+# define MIPS32_CP0_WIRED1 $6,0 /* Number of fixed ('wired') TLB entries */
# define MIPS32_CP0_BADVADDR $8,0 /* Address of most recent exception */
# define MIPS32_CP0_COUNT $9,0 /* Processor cycle count */
# define MIPS32_CP0_ENTRYHI1 $10,0 /* High-order portion of the TLB entry */
@@ -140,7 +140,7 @@
# define CP0_PAGEMASK_256MB (0xffff << CP0_PAGEMASK_SHIFT)
/* Register Number: 6 Sel: 0 Name: Wired
- * Function: Controls the number of fixed (�wired�) TLB entries
+ * Function: Controls the number of fixed ('wired') TLB entries
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*
* This is a 32-bit register containing the TLB wired boundary.
@@ -232,7 +232,7 @@
#define CP0_STATUS_TS (1 << 21) /* Bit 21: TLB detected match on multiple entries */
#define CP0_STATUS_BEV (1 << 22) /* Bit 22: Location of exception vectors 1->Bootstrap */
#define CP0_STATUS_PX (1 << 23) /* Bit 23: Enables 64-bit operations (Not MIPS32) */
-#define CP0_STATUS_MX (1 << 24) /* Bit 24: Enables MDMX� (Not MIPS32) */
+#define CP0_STATUS_MX (1 << 24) /* Bit 24: Enables MDMX™ (Not MIPS32) */
#define CP0_STATUS_RE (1 << 25) /* Bit 25: Enable reverse-endian memory in user mode */
#define CP0_STATUS_FR (1 << 26) /* Bit 26: Controls the floating point register mode (Not MIPS32) */
#define CP0_STATUS_RP (1 << 27) /* Bit 27: Enables reduced power mode */
@@ -432,12 +432,12 @@
*/
#define CP0_CONFIG3_TL (1 << 0) /* Bit 0: Trace Logic implemented */
-#define CP0_CONFIG3_SM (1 << 1) /* Bit 1: SmartMIPS� ASE implemented */
+#define CP0_CONFIG3_SM (1 << 1) /* Bit 1: SmartMIPS™ ASE implemented */
#define CP0_CONFIG3_CDMM (1 << 3) /* Bit 3: Common Device Memory Map */
#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Small page bit */
#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */
#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */
-#define CP0_CONFIG3_ITL (1 << 8) /* Bit 8: Flowtrace� Hardware bit */
+#define CP0_CONFIG3_ITL (1 << 8) /* Bit 8: Flowtrace® Hardware bit */
#define CP0_CONFIG3_DSPP (1 << 10) /* Bit 10: MIPS DSP ASE Presence bit */
#define CP0_CONFIG3_DSP2 (1 << 11) /* Bit 11: MIPS DSP ASE Revision 2 Presence bit */
#define CP0_CONFIG3_RXI (1 << 12) /* Bit 12: RIE and XIE Implemented in PageGrain bit */
diff --git a/arch/mips/include/pic32mx/cp0.h b/arch/mips/include/pic32mx/cp0.h
index 9ccc80024c..49013bd454 100644
--- a/arch/mips/include/pic32mx/cp0.h
+++ b/arch/mips/include/pic32mx/cp0.h
@@ -115,7 +115,7 @@
* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
- * CP0_STATUS_MX Bit 24: Enables MDMX� (Not MIPS32)
+ * CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32)
*/
#undef CP0_STATUS_UX
diff --git a/arch/mips/src/pic32mx/pic32mx_devcfg.h b/arch/mips/src/pic32mx/pic32mx_devcfg.h
index fe01a5135e..c567c0f792 100644
--- a/arch/mips/src/pic32mx/pic32mx_devcfg.h
+++ b/arch/mips/src/pic32mx/pic32mx_devcfg.h
@@ -51,7 +51,7 @@
/* Device configuration word 3 */
-#define DEVCFG3_USERID_SHIFT (0) /* Bits 0-15: User-defined, readable via ICSP� and JTAG */
+#define DEVCFG3_USERID_SHIFT (0) /* Bits 0-15: User-defined, readable via ICSP™ and JTAG */
#define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT)
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
diff --git a/arch/x86/include/i486/irq.h b/arch/x86/include/i486/irq.h
index c0b46eb0b6..ffad1ece32 100644
--- a/arch/x86/include/i486/irq.h
+++ b/arch/x86/include/i486/irq.h
@@ -76,7 +76,7 @@
#define IRQ0 32 /* System timer (cannot be changed) */
#define IRQ1 33 /* Keyboard controller (cannot be changed) */
-#define IRQ2 34 /* Cascaded signals from IRQs 8�15 */
+#define IRQ2 34 /* Cascaded signals from IRQs 8-15 */
#define IRQ3 35 /* Serial port controller for COM2/4 */
#define IRQ4 36 /* serial port controller for COM1/3 */
#define IRQ5 37 /* LPT port 2 or sound card */
diff --git a/arch/z80/include/z180/chip.h b/arch/z80/include/z180/chip.h
index e7b9d411c1..3e2036af32 100644
--- a/arch/z80/include/z180/chip.h
+++ b/arch/z80/include/z180/chip.h
@@ -387,7 +387,7 @@
* External Memory - 1
* Voltage Range - 5.0V
* Communications Controller - CSIO, UART
- * Other Features - 1MB MMU, 2xDMA�s, 2xUARTs
+ * Other Features - 1MB MMU, 2xDMAs, 2xUARTs
* Speed (MHz) - 20, 10, 33
* Core / CPU Used - Z180
* Pin Count - 64, 68, 80
diff --git a/arch/z80/include/z180/irq.h b/arch/z80/include/z180/irq.h
index fc180955cf..3fb3b25cd0 100644
--- a/arch/z80/include/z180/irq.h
+++ b/arch/z80/include/z180/irq.h
@@ -74,10 +74,10 @@
/* INT0
*
* INT0 (only) has 3 different software programmable interrupt response
- * modes�Mode 0, Mode 1 and Mode 2.
+ * modes: Mode 0, Mode 1 and Mode 2.
*
* - INT0 Mode 0. During the interrupt acknowledge cycle, an instruction
- * is fetched from the data bus (DO�D7) at the rising edge of T3.
+ * is fetched from the data bus (DO-D7) at the rising edge of T3.
*
* - INT0 Mode 1. The PC is stacked and instruction execution restarts at
* logical address 0x0038.
diff --git a/boards/arm/a1x/pcduino-a10/README.txt b/boards/arm/a1x/pcduino-a10/README.txt
index 6ebf35399c..ba82db2902 100644
--- a/boards/arm/a1x/pcduino-a10/README.txt
+++ b/boards/arm/a1x/pcduino-a10/README.txt
@@ -56,7 +56,7 @@ README
(See http://www.allwinnertech.com/en/product/a10.html):
CPU
- - ARM Cortex�-A8
+ - ARM Cortex™-A8
- 32KB I-Cache
- 32KB D-Cache
- 256KB L2 Cache
diff --git a/boards/arm/imx6/sabre-6quad/README.txt b/boards/arm/imx6/sabre-6quad/README.txt
index f623ed96c4..4c24e59671 100644
--- a/boards/arm/imx6/sabre-6quad/README.txt
+++ b/boards/arm/imx6/sabre-6quad/README.txt
@@ -213,7 +213,7 @@ Debug:
- JTAG connector (20-pin)
- 1x Serial-to-USB connector (for JTAG)
OS Support:
- - Linux� and Android� from NXP/Freescale
+ - Linux® and Android™ from NXP/Freescale
- Others supported via third party (QNX, Windows Embedded)
Tools Support:
- Manufacturing tool from NXP/Freescale
diff --git a/boards/arm/kinetis/twr-k60n512/README.txt b/boards/arm/kinetis/twr-k60n512/README.txt
index 319e94c548..19f159a0e0 100644
--- a/boards/arm/kinetis/twr-k60n512/README.txt
+++ b/boards/arm/kinetis/twr-k60n512/README.txt
@@ -35,7 +35,7 @@ Kinetis TWR-K60N512 Features:
o Touch TWRPI Socket adds support for various capacitive touch boards
(e.g. keypads, rotary dials, sliders, etc.)
o Tower connectivity for access to USB, Ethernet, RS232/RS485, CAN, SPI,
- I�C, Flexbus, etc.
+ I²C, Flexbus, etc.
o Plus: Potentiometer, 4 LEDs, 2 pushbuttons, infrared port
Kinetis TWR-K60N512 Pin Configuration
diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_clkinit.c b/boards/arm/lpc31xx/ea3131/src/lpc31_clkinit.c
index ddc729ba5f..caa8268228 100644
--- a/boards/arm/lpc31xx/ea3131/src/lpc31_clkinit.c
+++ b/boards/arm/lpc31xx/ea3131/src/lpc31_clkinit.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c b/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
index 1cba6f0c09..5c235d3cfb 100644
--- a/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
+++ b/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
@@ -100,12 +100,12 @@
* undefined operation. Once power is applied to VDD and VDDQ
* (simultaneously) and the clock is stable (stable clock is defined as
* a signal cycling within timing constraints specified for the clock
- * pin), the SDRAM requires a 100�s delay prior to issuing any command
+ * pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP.
*
- * "Starting at some point during this 100�s period and continuing at least
+ * "Starting at some point during this 100µs period and continuing at least
* through the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied. Once the 100�s delay has been satisfied with at least one
+ * be applied. Once the 100µs delay has been satisfied with at least one
* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
* should be applied. All banks must then be precharged, thereby placing
* the device in the all banks idle state.
diff --git a/boards/arm/lpc31xx/ea3131/tools/lpchdr.h b/boards/arm/lpc31xx/ea3131/tools/lpchdr.h
index 30b6f30243..8298e1445b 100644
--- a/boards/arm/lpc31xx/ea3131/tools/lpchdr.h
+++ b/boards/arm/lpc31xx/ea3131/tools/lpchdr.h
@@ -46,13 +46,13 @@ struct lpc31_header_s
* valid image header. This field should always
* be set to 0x41676d69. */
uint32_t execution_crc32; /* 0x08 CRC32 value of execution part of the image. If
- * the �image_type� is set to �0xA�, this field
+ * the 'image_type' is set to '0xA', this field
* is ignored by boot ROM. */
uint32_t reserved0[4]; /* 0x0c-0x18: Should be zero. */
uint32_t imagetype; /* 0x1c Specifies whether CRC check should be done
* on the image or not:
- * 0xA � No CRC check required.
- * 0xB � Do CRC32 check on both header and
+ * 0xA - No CRC check required.
+ * 0xB - Do CRC32 check on both header and
* execution part of the image. */
uint32_t imagelength; /* 0x20 Total image length including header rounded
* up to the nearest 512 byte boundary. In C
@@ -68,8 +68,8 @@ struct lpc31_header_s
uint32_t sbzbootparameter; /* 0x2c hould be zero. */
uint32_t cust_reserved[15]; /* 0x30-0x68: Reserved for customer use (60 bytes) */
uint32_t header_crc32; /* 0x6c CRC32 value of the header (bytes 0x00 to 0x6C
- * of the image). If the �image_type� is set
- * to �0xA�, this field is ignored by boot ROM. */
+ * of the image). If the 'image_type' is set
+ * to '0xA', this field is ignored by boot ROM. */
uint32_t reserved1[4]; /* 0x70-0x7c: Should be zero. */
/* 0x80 Start of program code (128Kb max). The final
* image has to be padded to the nearest 512
diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_clkinit.c b/boards/arm/lpc31xx/ea3152/src/lpc31_clkinit.c
index 39316eae1d..38c9321ce7 100644
--- a/boards/arm/lpc31xx/ea3152/src/lpc31_clkinit.c
+++ b/boards/arm/lpc31xx/ea3152/src/lpc31_clkinit.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c b/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c
index b374d62fc8..7e9eca4867 100644
--- a/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c
+++ b/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
@@ -100,12 +100,12 @@
* undefined operation. Once power is applied to VDD and VDDQ
* (simultaneously) and the clock is stable (stable clock is defined as
* a signal cycling within timing constraints specified for the clock
- * pin), the SDRAM requires a 100�s delay prior to issuing any command
+ * pin), the SDRAM requires a 100µs delay prior to issuing any command
* other than a COMMAND INHIBIT or NOP.
*
- * "Starting at some point during this 100�s period and continuing at least
+ * "Starting at some point during this 100µs period and continuing at least
* through the end of this period, COMMAND INHIBIT or NOP commands should
- * be applied. Once the 100�s delay has been satisfied with at least one
+ * be applied. Once the 100µs delay has been satisfied with at least one
* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
* should be applied. All banks must then be precharged, thereby placing
* the device in the all banks idle state.
diff --git a/boards/arm/lpc31xx/ea3152/tools/lpchdr.h b/boards/arm/lpc31xx/ea3152/tools/lpchdr.h
index 3d59d81c14..9097b01b34 100644
--- a/boards/arm/lpc31xx/ea3152/tools/lpchdr.h
+++ b/boards/arm/lpc31xx/ea3152/tools/lpchdr.h
@@ -48,15 +48,15 @@ struct lpc31_header_s
* should always be set to 0x41676d69.
*/
uint32_t execution_crc32; /* 0x08 CRC32 value of execution part of
- * the image. If the �image_type� is set
- * to �0xA�, this field is ignored by boot
+ * the image. If the 'image_type' is set
+ * to '0xA', this field is ignored by boot
* ROM.
*/
uint32_t reserved0[4]; /* 0x0c-0x18: Should be zero. */
uint32_t imagetype; /* 0x1c Specifies whether CRC check should be
* done on the image or not:
- * 0xA � No CRC check required.
- * 0xB � Do CRC32 check on both header and
+ * 0xA - No CRC check required.
+ * 0xB - Do CRC32 check on both header and
* execution part of the image.
*/
uint32_t imagelength; /* 0x20 Total image length including header
@@ -82,7 +82,7 @@ struct lpc31_header_s
*/
uint32_t header_crc32; /* 0x6c CRC32 value of the header
* (bytes 0x00 to 0x6C of the image).
- * If the �image_type� is set to �0xA�,
+ * If the 'image_type' is set to '0xA',
* this field is ignored by boot ROM.
*/
uint32_t reserved1[4]; /* 0x70-0x7c: Should be zero. */
diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_clkinit.c b/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_clkinit.c
index 4f011b4188..41c0b52fbf 100644
--- a/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_clkinit.c
+++ b/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_clkinit.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 - 9 September 2009
* - NXP lpc313x.cdl.drivers.zip example driver code
*/
diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h
index 4b4f50b3df..5d1bf766fb 100644
--- a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h
+++ b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/lpchdr.h
@@ -46,13 +46,13 @@ struct lpc31_header_s
* valid image header. This field should always
* be set to 0x41676d69. */
uint32_t execution_crc32; /* 0x08 CRC32 value of execution part of the image. If
- * the �image_type� is set to �0xA�, this field
+ * the 'image_type' is set to '0xA', this field
* is ignored by boot ROM. */
uint32_t reserved0[4]; /* 0x0c-0x18: Should be zero. */
uint32_t imagetype; /* 0x1c Specifies whether CRC check should be done
* on the image or not:
- * 0xA � No CRC check required.
- * 0xB � Do CRC32 check on both header and
+ * 0xA - No CRC check required.
+ * 0xB - Do CRC32 check on both header and
* execution part of the image. */
uint32_t imagelength; /* 0x20 Total image length including header rounded
* up to the nearest 512 byte boundary. In C
@@ -68,8 +68,8 @@ struct lpc31_header_s
uint32_t sbzbootparameter; /* 0x2c hould be zero. */
uint32_t cust_reserved[15]; /* 0x30-0x68: Reserved for customer use (60 bytes) */
uint32_t header_crc32; /* 0x6c CRC32 value of the header (bytes 0x00 to 0x6C
- * of the image). If the �image_type� is set
- * to �0xA�, this field is ignored by boot ROM. */
+ * of the image). If the 'image_type' is set
+ * to '0xA', this field is ignored by boot ROM. */
uint32_t reserved1[4]; /* 0x70-0x7c: Should be zero. */
/* 0x80 Start of program code (128Kb max). The final
* image has to be padded to the nearest 512
diff --git a/boards/arm/sama5/sama5d2-xult/include/board_384mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_384mhz.h
index b7585bf63d..36b9e3c66a 100644
--- a/boards/arm/sama5/sama5d2-xult/include/board_384mhz.h
+++ b/boards/arm/sama5/sama5d2-xult/include/board_384mhz.h
@@ -102,7 +102,7 @@
*
* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
* full-speed operations. These clocks must be generated by a PLL with a
- * correct accuracy of � 0.25% thanks to USBDIV field.
+ * correct accuracy of ± 0.25% thanks to USBDIV field.
*
* "Thus the USB Host peripheral receives three clocks from the Power
* Management Controller (PMC): the Peripheral Clock (MCK domain), the
@@ -142,7 +142,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d2-xult/include/board_396mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_396mhz.h
index 04e8ebeaf1..6fa733366a 100644
--- a/boards/arm/sama5/sama5d2-xult/include/board_396mhz.h
+++ b/boards/arm/sama5/sama5d2-xult/include/board_396mhz.h
@@ -98,7 +98,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d2-xult/include/board_528mhz.h b/boards/arm/sama5/sama5d2-xult/include/board_528mhz.h
index 634b9470cd..bb823a7420 100644
--- a/boards/arm/sama5/sama5d2-xult/include/board_528mhz.h
+++ b/boards/arm/sama5/sama5d2-xult/include/board_528mhz.h
@@ -97,7 +97,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d2-xult/include/board_sdram.h b/boards/arm/sama5/sama5d2-xult/include/board_sdram.h
index d7827936ab..d1920d243b 100644
--- a/boards/arm/sama5/sama5d2-xult/include/board_sdram.h
+++ b/boards/arm/sama5/sama5d2-xult/include/board_sdram.h
@@ -107,7 +107,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* HSMCI clocking
diff --git a/boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h b/boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h
index cc967b9e7b..e6418d3a59 100644
--- a/boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h
+++ b/boards/arm/sama5/sama5d3-xplained/include/board_384mhz.h
@@ -103,7 +103,7 @@
*
* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
* full-speed operations. These clocks must be generated by a PLL with a
- * correct accuracy of � 0.25% thanks to USBDIV field.
+ * correct accuracy of ± 0.25% thanks to USBDIV field.
*
* "Thus the USB Host peripheral receives three clocks from the Power
* Management Controller (PMC): the Peripheral Clock (MCK domain), the
@@ -143,7 +143,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h b/boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h
index b75ceac524..015b609a94 100644
--- a/boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h
+++ b/boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h
@@ -100,7 +100,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h b/boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h
index ecb6ab06f6..d3e7eb8f58 100644
--- a/boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h
+++ b/boards/arm/sama5/sama5d3-xplained/include/board_528mhz.h
@@ -99,7 +99,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d3-xplained/include/board_sdram.h b/boards/arm/sama5/sama5d3-xplained/include/board_sdram.h
index c8612f2976..190976d577 100644
--- a/boards/arm/sama5/sama5d3-xplained/include/board_sdram.h
+++ b/boards/arm/sama5/sama5d3-xplained/include/board_sdram.h
@@ -111,7 +111,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* HSMCI clocking
diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c b/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c
index 331d81d2bb..c2f971d96c 100644
--- a/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c
+++ b/boards/arm/sama5/sama5d3-xplained/src/sam_ethernet.c
@@ -166,7 +166,7 @@ void weak_function sam_netinitialize(void)
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential
- * pair signals designated from GRX� and GTx� plus control signals for link
+ * pair signals designated from GRX± and GTx± plus control signals for link
* activity indicators. These signals can be used to connect to a
* 10/100/1000 BaseT RJ45 connector integrated on the main board.
*
diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c b/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c
index a887847b38..ae3250e0fe 100644
--- a/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c
+++ b/boards/arm/sama5/sama5d3-xplained/src/sam_sdram.c
@@ -137,7 +137,7 @@ static inline void sam_sdram_delay(unsigned int loops)
* Per the SAMA5D3-Xplained User guide:
* "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte).
* The board includes 2 Gbits of on-board soldered DDR2 (double data rate)
- * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron�
+ * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron®
* for a total of 512 MBytes of DDR2 memory.
* The memory bus is 32 bits wide and operates with a frequency of up
* to 166 MHz."
diff --git a/boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h b/boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h
index d5eccb3fd0..e0da4e4a73 100644
--- a/boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h
+++ b/boards/arm/sama5/sama5d3x-ek/include/board_384mhz.h
@@ -104,7 +104,7 @@
*
* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
* full-speed operations. These clocks must be generated by a PLL with a
- * correct accuracy of � 0.25% thanks to USBDIV field.
+ * correct accuracy of ± 0.25% thanks to USBDIV field.
*
* "Thus the USB Host peripheral receives three clocks from the Power
* Management Controller (PMC): the Peripheral Clock (MCK domain), the
@@ -144,7 +144,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h b/boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h
index e633779e35..e93dfe7e71 100644
--- a/boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h
+++ b/boards/arm/sama5/sama5d3x-ek/include/board_396mhz.h
@@ -100,7 +100,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h b/boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h
index d6598fadc9..c610c3677b 100644
--- a/boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h
+++ b/boards/arm/sama5/sama5d3x-ek/include/board_528mhz.h
@@ -99,7 +99,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d3x-ek/include/board_sdram.h b/boards/arm/sama5/sama5d3x-ek/include/board_sdram.h
index 72d243a907..966b4bcc89 100644
--- a/boards/arm/sama5/sama5d3x-ek/include/board_sdram.h
+++ b/boards/arm/sama5/sama5d3x-ek/include/board_sdram.h
@@ -110,7 +110,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* HSMCI clocking
diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c b/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c
index 392682796d..85008aab2f 100644
--- a/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c
+++ b/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c
@@ -166,7 +166,7 @@ void weak_function sam_netinitialize(void)
* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
* The board supports RGMII interface mode.
* The Ethernet interface consists of 4 pairs of low voltage differential
- * pair signals designated from GRX� and GTx� plus control signals for link
+ * pair signals designated from GRX± and GTx± plus control signals for link
* activity indicators. These signals can be used to connect to a
* 10/100/1000 BaseT RJ45 connector integrated on the main board.
*
diff --git a/boards/arm/sama5/sama5d4-ek/include/board_384mhz.h b/boards/arm/sama5/sama5d4-ek/include/board_384mhz.h
index 7cfc18fee2..94378c69ab 100644
--- a/boards/arm/sama5/sama5d4-ek/include/board_384mhz.h
+++ b/boards/arm/sama5/sama5d4-ek/include/board_384mhz.h
@@ -102,7 +102,7 @@
*
* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
* full-speed operations. These clocks must be generated by a PLL with a
- * correct accuracy of � 0.25% thanks to USBDIV field.
+ * correct accuracy of ± 0.25% thanks to USBDIV field.
*
* "Thus the USB Host peripheral receives three clocks from the Power
* Management Controller (PMC): the Peripheral Clock (MCK domain), the
@@ -142,7 +142,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d4-ek/include/board_396mhz.h b/boards/arm/sama5/sama5d4-ek/include/board_396mhz.h
index 8b2a1fdf6f..dd30c5a9ec 100644
--- a/boards/arm/sama5/sama5d4-ek/include/board_396mhz.h
+++ b/boards/arm/sama5/sama5d4-ek/include/board_396mhz.h
@@ -98,7 +98,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d4-ek/include/board_528mhz.h b/boards/arm/sama5/sama5d4-ek/include/board_528mhz.h
index 46c6363618..64b712f3c3 100644
--- a/boards/arm/sama5/sama5d4-ek/include/board_528mhz.h
+++ b/boards/arm/sama5/sama5d4-ek/include/board_528mhz.h
@@ -97,7 +97,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* Resulting frequencies */
diff --git a/boards/arm/sama5/sama5d4-ek/include/board_sdram.h b/boards/arm/sama5/sama5d4-ek/include/board_sdram.h
index 8c59f223e6..bc8ea43f7a 100644
--- a/boards/arm/sama5/sama5d4-ek/include/board_sdram.h
+++ b/boards/arm/sama5/sama5d4-ek/include/board_sdram.h
@@ -106,7 +106,7 @@
#define BOARD_ADC_PRESCAL (7)
#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
-#define BOARD_TSD_TRACKTIM (2000) /* Min 1�s at 8MHz */
+#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
/* HSMCI clocking
diff --git a/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c b/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c
index b5a6ea280e..c05e71c50c 100644
--- a/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c
+++ b/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c
@@ -274,7 +274,7 @@ static void sam_config_slaveddr(void)
* "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte).
* The board includes 2 Gbits of on-board solderedDDR2 (double data rate)
* SDRAM. The footprints can also host two DDR2 (MT47H128M16RT) from
- * Micron� for a total of 512 MBytes of DDR2 memory. The memory bus is 32
+ * Micron® for a total of 512 MBytes of DDR2 memory. The memory bus is 32
* bits wide and operates with a frequency of up to 166 MHz."
*
* From the Atmel Code Example:
diff --git a/boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h b/boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h
index 47c33e0977..2a9ada1fd0 100644
--- a/boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h
+++ b/boards/arm/sama5/sama5d4-ek/src/sama5d4-ek.h
@@ -536,9 +536,9 @@
*
* - 7 inch LCD at 800x480 18-bit RGB resolution and white backlight
* - Projected Capacitive Multi-Touch Controller based on the Atmel
- * MXT768E maXTouch� IC
- * - 4 Capacitive �Navigation� Keys available via an Atmel AT42QT1070
- * QTouch� Button Sensor IC
+ * MXT768E maXTouch™ IC
+ * - 4 Capacitive "Navigation" Keys available via an Atmel AT42QT1070
+ * QTouch™ Button Sensor IC
* - 200 bytes of non-volatile serial EEPROM
*
* Both the MXT768E and the AT42QT1070 are I2C devices with interrupting
diff --git a/boards/arm/samd2l2/samd20-xplained/README.txt b/boards/arm/samd2l2/samd20-xplained/README.txt
index 66f224d406..baea4f10e4 100644
--- a/boards/arm/samd2l2/samd20-xplained/README.txt
+++ b/boards/arm/samd2l2/samd20-xplained/README.txt
@@ -108,10 +108,10 @@ Modules
10 microSD_DETECT 10 PB05 GPIO 10 PB15 GPIO
----------------- ---------------------- ---------------------- ------------------------------------
11 TWI SDA 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0] EXT1, EXT2, EXT3 and EDBG
- I�C SDA I�C SDA
+ I²C SDA I²C SDA
----------------- ---------------------- ---------------------- ------------------------------------
12 TWI SCL 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1] EXT2, EXT3 and EDBG
- I�C SCL I�C SCL
+ I²C SCL I²C SCL
----------------- ---------------------- ---------------------- ------------------------------------
13 USART RX 13 PB09 SERCOM4 PAD[1] 13 PB13 SERCOM4 PAD[1] The SERCOM4 module is shared between
USART RX USART RX EXT1, 2 and 3 USART's, but uses
@@ -221,10 +221,10 @@ Modules
10 DISPLAY_RESET 10 PB05 GPIO 10 PB15 GPIO
----------------- ---------------------- ---------------------- ------------------------------------
11 N/C 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0] EXT1, EXT2, EXT3 and EDBG
- I�C SDA I�C SDA
+ I²C SDA I²C SDA
----------------- ---------------------- ---------------------- ------------------------------------
12 N/C 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1] EXT2, EXT3 and EDBG
- I�C SCL I�C SCL
+ I²C SCL I²C SCL
----------------- ---------------------- ---------------------- ------------------------------------
13 N/C 13 PB09 SERCOM4 PAD[1] 13 PB13 SERCOM4 PAD[1] The SERCOM4 module is shared between
USART RX USART RX EXT1, 2 and 3 USART's, but uses
diff --git a/boards/arm/samd2l2/samd21-xplained/README.txt b/boards/arm/samd2l2/samd21-xplained/README.txt
index 51fe25a2f1..483d494f51 100644
--- a/boards/arm/samd2l2/samd21-xplained/README.txt
+++ b/boards/arm/samd2l2/samd21-xplained/README.txt
@@ -100,10 +100,10 @@ Modules
10 microSD_DETECT 10 PB05 GPIO 10 PB15 GPIO
----------------- ---------------------- ---------------------- ------------------------------------
11 TWI SDA 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0] EXT1, EXT2, EXT3 and EDBG
- I�C SDA I�C SDA
+ I²C SDA I²C SDA
----------------- ---------------------- ---------------------- ------------------------------------
12 TWI SCL 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1] EXT2, EXT3 and EDBG
- I�C SCL I�C SCL
+ I²C SCL I²C SCL
----------------- ---------------------- ---------------------- ------------------------------------
13 USART RX 13 PB09 SERCOM4 PAD[1] 13 PB11 SERCOM4 PAD[1] EXT3
USART RX USART RX
@@ -211,10 +211,10 @@ Modules
10 DISPLAY_RESET 10 PB05 GPIO 10 PB15 GPIO
----------------- ---------------------- ---------------------- ------------------------------------
11 N/C 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0] EXT1, EXT2, EXT3 and EDBG
- I�C SDA I�C SDA
+ I²C SDA I²C SDA
----------------- ---------------------- ---------------------- ------------------------------------
12 N/C 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1] EXT2, EXT3 and EDBG
- I�C SCL I�C SCL
+ I²C SCL I²C SCL
----------------- ---------------------- ---------------------- ------------------------------------
13 N/C 13 PB09 SERCOM4 PAD[1] 13 PB11 SERCOM4 PAD[1] EXT3
USART RX USART RX
diff --git a/boards/arm/samd2l2/samd21-xplained/src/sam_ug2832hsweg04.c b/boards/arm/samd2l2/samd21-xplained/src/sam_ug2832hsweg04.c
index 94147d82d5..09822a366f 100644
--- a/boards/arm/samd2l2/samd21-xplained/src/sam_ug2832hsweg04.c
+++ b/boards/arm/samd2l2/samd21-xplained/src/sam_ug2832hsweg04.c
@@ -45,10 +45,10 @@
* 10 DISPLAY_RESET 10 PB05 PORT 10 PB15 PORT
* ----------------- ---------------------- ----------------------
* 11 N/C 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0]
- * I�C SDA I�C SDA
+ * I²C SDA I²C SDA
* ----------------- ---------------------- ----------------------
* 12 N/C 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1]
- * I�C SCL I�C SCL
+ * I²C SCL I²C SCL
* ----------------- ---------------------- ----------------------
* 13 N/C 13 PB09 SERCOM4 PAD[1] 13 PB11 SERCOM4 PAD[1]
* USART RX USART RX
diff --git a/boards/arm/samd2l2/saml21-xplained/README.txt b/boards/arm/samd2l2/saml21-xplained/README.txt
index 5ee7ddc8de..d52e2c8742 100644
--- a/boards/arm/samd2l2/saml21-xplained/README.txt
+++ b/boards/arm/samd2l2/saml21-xplained/README.txt
@@ -90,10 +90,10 @@ Modules
10 microSD_DETECT 10 PA02 GPIO 10 PB15 GPIO
----------------- ---------------------- ---------------------- ------------------------------------
11 TWI SDA 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0] EXT1, EXT2, EXT3 and EDBG
- I�C SDA I�C SDA
+ I²C SDA I²C SDA
----------------- ---------------------- ---------------------- ------------------------------------
12 TWI SCL 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1] EXT2, EXT3 and EDBG
- I�C SCL I�C SCL
+ I²C SCL I²C SCL
----------------- ---------------------- ---------------------- ------------------------------------
13 USART RX 13 PB09 SERCOM4 PAD[1] 13 PA19 SERCOM1 PAD[3] The SERCOM4 module is shared between
USART RX USART RX EXT1, 2 and 3 USART's, but uses
@@ -203,10 +203,10 @@ Modules
10 DISPLAY_RESET 10 PA02 GPIO 10 PB15 GPIO
----------------- ---------------------- ---------------------- ------------------------------------
11 N/C 11 PA08 SERCOM2 PAD[0] 11 PA08 SERCOM2 PAD[0] EXT1, EXT2, EXT3 and EDBG
- I�C SDA I�C SDA
+ I²C SDA I²C SDA
----------------- ---------------------- ---------------------- ------------------------------------
12 N/C 12 PA09 SERCOM2 PAD[1] 12 PA09 SERCOM2 PAD[1] EXT2, EXT3 and EDBG
- I�C SCL I�C SCL
+ I²C SCL I²C SCL
----------------- ---------------------- ---------------------- ------------------------------------
13 N/C 13 PB09 SERCOM4 PAD[1] 13 PA19 SERCOM1 PAD[3] The SERCOM4 module is shared between
USART RX USART RX EXT1, 2 and 3 USART's, but uses
diff --git a/boards/arm/tiva/ekk-lm3s9b96/README.txt b/boards/arm/tiva/ekk-lm3s9b96/README.txt
index b63c50474d..89713f1a11 100644
--- a/boards/arm/tiva/ekk-lm3s9b96/README.txt
+++ b/boards/arm/tiva/ekk-lm3s9b96/README.txt
@@ -16,11 +16,11 @@ Stellaris EKK-LM3S9B96 Evaluation Kit
The EKK-LM3S9B96 evaluation kit provides the following features:
o LM3S9B96 high-performance Stellaris microcontroller and large memory
- � 32-bit ARM� Cortex�-M3 core
- � 256 KB single-cycle Flash memory, 96 KB single-cycle SRAM, 23.7 KB single-cycle ROM
+ - 32-bit ARM® Cortex™-M3 core
+ - 256 KB single-cycle Flash memory, 96 KB single-cycle SRAM, 23.7 KB single-cycle ROM
o Ethernet 10/100 port with two LED indicators
o USB 2.0 Full-Speed OTG port
- o SAFERTOS� operating system in microcontroller ROM
+ o SAFERTOS™ operating system in microcontroller ROM
o Virtual serial communications port capability
o Oversized board pads for GPIO access
o User pushbutton and LED
@@ -29,10 +29,10 @@ The EKK-LM3S9B96 evaluation kit provides the following features:
Features of the LM3S9B96 Microcontroller
- o ARM� Cortex�-M3 architecture
- � 80-MHz operation
- � ARM Cortex SysTick Timer
- � Integrated Nested Vectored Interrupt Controller (NVIC)
+ o ARM® Cortex™-M3 architecture
+ - 80-MHz operation
+ - ARM Cortex SysTick Timer
+ - Integrated Nested Vectored Interrupt Controller (NVIC)
o External Peripheral Interface (EPI)
o 256 KB single-cycle flash
o 96 KB single-cycle SRAM
@@ -46,10 +46,10 @@ Features of the LM3S9B96 Microcontroller
o Two SSI modules
o Two Watchdog Timers (32-bit)
o Three PWM generator blocks
- � One 16-bit counter
- � Two comparators
- � Produces eight independent PWM signals
- � One dead-band generator
+ - One 16-bit counter
+ - Two comparators
+ - Produces eight independent PWM signals
+ - One dead-band generator
o Two QEI modules with position integrator for tracking encoder position
o Up to 65 GPIOs, depending on user configuration
o On-chip low drop-out (LDO) voltage regulator
diff --git a/boards/arm/tiva/lm3s6432-s2e/README.txt b/boards/arm/tiva/lm3s6432-s2e/README.txt
index d50082bd23..22abd0429a 100644
--- a/boards/arm/tiva/lm3s6432-s2e/README.txt
+++ b/boards/arm/tiva/lm3s6432-s2e/README.txt
@@ -27,7 +27,7 @@ The Stellaris RDK-S2E Reference Design Kit includes the following features:
Features of the LM3S6432 Microcontroller
- o 32-bit RISC performance using ARM� Cortex�-M3 v7M architecture
+ o 32-bit RISC performance using ARM® Cortex™-M3 v7M architecture
- 50-MHz operation
- Hardware-division and single-cycle-multiplication
- Integrated Nested Vectored Interrupt Controller (NVIC)
@@ -41,10 +41,10 @@ Features of the LM3S6432 Microcontroller
o Two independent integrated analog comparators
o One I2C module
o One PWM generator block
- � One 16-bit counter
- � Two comparators
- � Produces two independent PWM signals
- � One dead-band generator
+ - One 16-bit counter
+ - Two comparators
+ - Produces two independent PWM signals
+ - One dead-band generator
o 0 to 43 GPIOs, depending on user configuration
o On-chip low drop-out (LDO) voltage regulator
diff --git a/boards/arm/tiva/lm3s8962-ek/README.txt b/boards/arm/tiva/lm3s8962-ek/README.txt
index 05325231bd..9fab10084d 100644
--- a/boards/arm/tiva/lm3s8962-ek/README.txt
+++ b/boards/arm/tiva/lm3s8962-ek/README.txt
@@ -25,17 +25,17 @@ The Stellaris LM3S8962 Evaluation Board includes the following features:
o User LED, navigation switches, and select pushbuttons
o Magnetic speaker
o LM3S8962 I/O available on labeled break-out pads
- o Standard ARM� 20-pin JTAG debug connector with input and output modes
+ o Standard ARM® 20-pin JTAG debug connector with input and output modes
o USB interface for debugging and power supply
o MicroSD card slot
Features of the LM3S8962 Microcontroller
- o 32-bit RISC performance using ARM� Cortex�-M3 v7M architecture
- � 50-MHz operation
- � Hardware-division and single-cycle-multiplication
- � Integrated Nested Vectored Interrupt Controller (NVIC)
- � 42 interrupt channels with eight priority levels
+ o 32-bit RISC performance using ARM® Cortex™-M3 v7M architecture
+ - 50-MHz operation
+ - Hardware-division and single-cycle-multiplication
+ - Integrated Nested Vectored Interrupt Controller (NVIC)
+ - 42 interrupt channels with eight priority levels
o 256 KB single-cycle flash
o 64 KB single-cycle SRAM
o Four general-purpose 32-bit timers
@@ -45,10 +45,10 @@ Features of the LM3S8962 Microcontroller
o Two independent integrated analog comparators
o Two I2C modules
o Three PWM generator blocks
- � One 16-bit counter
- � Two comparators
- � Produces two independent PWM signals
- � One dead-band generator
+ - One 16-bit counter
+ - Two comparators
+ - Produces two independent PWM signals
+ - One dead-band generator
o Two QEI modules with position integrator for tracking encoder position
o 0 to 42 GPIOs, depending on user configuration
o On-chip low drop-out (LDO) voltage regulator
diff --git a/boards/arm/tiva/lm4f120-launchpad/README.txt b/boards/arm/tiva/lm4f120-launchpad/README.txt
index 5c655ab4e6..f93b06db55 100644
--- a/boards/arm/tiva/lm4f120-launchpad/README.txt
+++ b/boards/arm/tiva/lm4f120-launchpad/README.txt
@@ -2,8 +2,8 @@ README
^^^^^^
README for NuttX port to the Stellaris LM4F120 LaunchPad.
-The Stellaris� LM4F120 LaunchPad Evaluation Board is a low-cost evaluation
-platform for ARM� Cortex�-M4F-based microcontrollers from Texas Instruments.
+The Stellaris® LM4F120 LaunchPad Evaluation Board is a low-cost evaluation
+platform for ARM® Cortex™-M4F-based microcontrollers from Texas Instruments.
Contents
^^^^^^^^
@@ -20,19 +20,19 @@ Contents
Stellaris LM4F120 LaunchPad
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-The Stellaris� LM4F120 LaunchPad Evaluation Kit offers these features:
+The Stellaris® LM4F120 LaunchPad Evaluation Kit offers these features:
-o A Stellaris� LaunchPad Evaluation board (EK-LM4F120XL)
-o On-board Stellaris� In-Circuit Debug Interface (ICDI)
+o A Stellaris® LaunchPad Evaluation board (EK-LM4F120XL)
+o On-board Stellaris® In-Circuit Debug Interface (ICDI)
o Programmable user buttons and an RGB LED for custom applications.
o USB Micro-B plug to USB-A plug cable
Features of the LM4F120H5QR Microcontroller
-o 32-bit ARM� Cortex�-M4F 80-MHz processor core.
+o 32-bit ARM® Cortex™-M4F 80-MHz processor core.
o On-chip memory, featuring 256 KB single-cycle Flash up to 40 MHz (a
prefetch buffer improves performance above 40 MHz), 32 KB single-cycle
- SRAM; internal ROM loaded with StellarisWare� software; 2KB EEPROM
+ SRAM; internal ROM loaded with StellarisWare® software; 2KB EEPROM
o Two Controller Area Network (CAN) modules, using CAN protocol version
2.0 part A/B and with bit rates up to 1 Mbps
o Universal Serial Bus (USB) controller with USB 2.0 full-speed (12 Mbps)
@@ -45,8 +45,8 @@ o Advanced serial integration, featuring: eight UARTs with IrDA, 9-bit, and
interfaces; four Inter-Integrated Circuit (I2C) modules, providing
Standard (100 Kbps) and Fast (400 Kbps) transmission and support for
sending and receiving data as either a master or a slave
-o ARM PrimeCell� 32-channel configurable �DMA controller, providing a way to
- offload data transfer tasks from the Cortex�-M4F processor, allowing for
+o ARM PrimeCell® 32-channel configurable µDMA controller, providing a way to
+ offload data transfer tasks from the Cortex™-M4F processor, allowing for
more efficient use of the processor and the available bus bandwidth
o Analog support, featuring: two 12-bit Analog-to-Digital Converters (ADC)
with 12 analog input channels and a sample rate of one million
@@ -69,7 +69,7 @@ o Multiple clock sources for microcontroller system clock: Precision
for the Hibernation Module, and Internal 30-kHz Oscillator
o Full-featured debug solution with debug access via JTAG and Serial Wire
interfaces, and IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
-o Industrial-range (-40�C to 85�C) RoHS-compliant 64-pin LQFP
+o Industrial-range (-40°C to 85°C) RoHS-compliant 64-pin LQFP
On-Board GPIO Usage
===================
diff --git a/boards/avr/at32uc3/avr32dev1/README.txt b/boards/avr/at32uc3/avr32dev1/README.txt
index 6d18e27049..dcac01fdd6 100644
--- a/boards/avr/at32uc3/avr32dev1/README.txt
+++ b/boards/avr/at32uc3/avr32dev1/README.txt
@@ -235,7 +235,7 @@ AVR32 Bootloader
"To launch BatchISP, open a command prompt. Windows or Cygwin command
prompt can be used provided that the bin folder of the FLIP installation
- directory is in the PATH (Windows� or Cygwin�s) environment variable.
+ directory is in the PATH (Windows' or Cygwin's) environment variable.
When running BatchISP on AT32UC3xxxxx, the target part has to be specified
with -device at32uc3xxxxx and the communication port with -hardware usb.
Commands can then be placed after -operation. These commands are executed
diff --git a/boards/avr/at90usb/teensy-2.0/README.txt b/boards/avr/at90usb/teensy-2.0/README.txt
index 55b4a0c7f8..387a1df3fb 100644
--- a/boards/avr/at90usb/teensy-2.0/README.txt
+++ b/boards/avr/at90usb/teensy-2.0/README.txt
@@ -156,7 +156,7 @@ I have the SD-ADP SD/MMC Card Adaptor from www.gravitech.com
o Connect directly to 3.3V or 5.0V microcontroller
o Card detect LED
o Includes 11-pin male header
- o Board dimension: 2.0�x1.3�
+ o Board dimension: 2.0"x1.3"
SD-ADP Pinout / SD Connection
diff --git a/boards/hc/m9s12/demo9s12ne64/README.txt b/boards/hc/m9s12/demo9s12ne64/README.txt
index 29b42cbc9b..894c7b606f 100644
--- a/boards/hc/m9s12/demo9s12ne64/README.txt
+++ b/boards/hc/m9s12/demo9s12ne64/README.txt
@@ -6,21 +6,21 @@ README
CONTENTS
^^^^^^^^
- � MC9S12NE64 Features
- � Development Environment
- � NuttX Buildroot Toolchain
- � FreeScale HCS12 Serial Monitor
- � Soft Registers
- � HCS12/DEMO9S12NEC64-specific Configuration Options
- � Configurations
+ o MC9S12NE64 Features
+ o Development Environment
+ o NuttX Buildroot Toolchain
+ o FreeScale HCS12 Serial Monitor
+ o Soft Registers
+ o HCS12/DEMO9S12NEC64-specific Configuration Options
+ o Configurations
MC9S12NE64 Features
^^^^^^^^^^^^^^^^^^^
- � 16-bit HCS12 core
+ o 16-bit HCS12 core
- HCS12 CPU
- Upward compatible with M68HC11 instruction set
- - Interrupt stacking and programmer�s model identical to M68HC11
+ - Interrupt stacking and programmer's model identical to M68HC11
- Instruction queue
- Enhanced indexed addressing
- Memory map and interface (MMC)
@@ -30,16 +30,16 @@ MC9S12NE64 Features
trace buffer (DBG)
- Multiplexed expansion bus interface (MEBI) - available only in
112-pin package version
- � Wakeup interrupt inputs
+ o Wakeup interrupt inputs
- Up to 21 port bits available for wakeup interrupt function with
digital filtering
- � Memory
+ o Memory
- 64K bytes of FLASH EEPROM
- 8K bytes of RAM
- � Analog-to-digital converter (ATD)
+ o Analog-to-digital converter (ATD)
- One 8-channel module with 10-bit resolution
- External conversion trigger capability
- � Timer module (TIM)
+ o Timer module (TIM)
- 4-channel timer
- Each channel configurable as either input capture or output
compare
@@ -48,11 +48,11 @@ MC9S12NE64 Features
- 16-bit pulse accumulator
- External event counting
- Gated time accumulation
- � Serial interfaces
+ o Serial interfaces
- Two asynchronous serial communications interface (SCI)
- One synchronous serial peripheral interface (SPI)
- One inter-IC bus (IIC)
- � Ethernet Media access controller (EMAC)
+ o Ethernet Media access controller (EMAC)
- IEEE 802.3 compliant
- Medium-independent interface (MII)
- Full-duplex and half-duplex modes
@@ -64,10 +64,10 @@ MC9S12NE64 Features
- Exact match for single 48-bit individual (unicast) address
- Hash (64-bit hash) check of group (multicast) addresses
- Promiscuous mode
- � Ethertype filter
- � Loopback mode
- � Two receive and one transmit Ethernet buffer interfaces
- � Ethernet 10/100 Mbps transceiver (EPHY)
+ o Ethertype filter
+ o Loopback mode
+ o Two receive and one transmit Ethernet buffer interfaces
+ o Ethernet 10/100 Mbps transceiver (EPHY)
- IEEE 802.3 compliant
- Digital adaptive equalization
- Half-duplex and full-duplex
@@ -76,7 +76,7 @@ MC9S12NE64 Features
- 125-MHz clock generator and timing recovery
- Integrated wave-shaping circuitry
- Loopback modes
- � CRG (clock and reset generator module)
+ o CRG (clock and reset generator module)
- Windowed COP watchdog
- Real-time interrupt
- Clock monitor
@@ -84,19 +84,19 @@ MC9S12NE64 Features
- Phase-locked loop clock frequency multiplier
- Limp home mode in absence of external clock
- 25-MHz crystal oscillator reference clock
- � Operating frequency
+ o Operating frequency
- 50 MHz equivalent to 25 MHz bus speed for single chip
- 32 MHz equivalent to 16 MHz bus speed in expanded bus modes
- � Internal 2.5-V regulator
- - Supports an input voltage range from 3.3 V � 5%
+ o Internal 2.5-V regulator
+ - Supports an input voltage range from 3.3 V ± 5%
- Low-power mode capability
- Includes low-voltage reset (LVR) circuitry
- � 80-pin TQFP-EP or 112-pin LQFP package
+ o 80-pin TQFP-EP or 112-pin LQFP package
- Up to 70 I/O pins with 3.3 V input and drive capability (112-pin
package)
- Up to two dedicated 3.3 V input only lines (IRQ, XIRQ)
- � Development support
- - Single-wire background debug� mode (BDM)
+ o Development support
+ - Single-wire background debug™ mode (BDM)
- On-chip hardware breakpoints
- Enhanced DBG debug features
@@ -175,21 +175,21 @@ FreeScale HCS12 Serial Monitor
Memory Configuration:
Registers:
- � Register space is located at 0x0000�0x03ff.
+ o Register space is located at 0x0000-0x03ff.
FLASH:
- � FLASH memory is any address greater than 0x4000. All paged
+ o FLASH memory is any address greater than 0x4000. All paged
addresses are assumed to be FLASH memory.
- � Application code should exclude the 0xf780�0xff7f memory.
+ o Application code should exclude the 0xf780-0xff7f memory.
SRAM:
- � RAM ends at 0x3FFF and builds down to the limit of the device�s
+ o RAM ends at 0x3FFF and builds down to the limit of the device's
available RAM.
- � The serial monitor's stack pointer is set to the end of RAM+1
+ o The serial monitor's stack pointer is set to the end of RAM+1
(0x4000).
EEPROM:
- � EEPROM (if the target device has any) is limited to the available
- space between the registers and the RAM (0x0400�to start of RAM).
+ o EEPROM (if the target device has any) is limited to the available
+ space between the registers and the RAM (0x0400 to start of RAM).
External Devices:
- � External devices attached to the multiplexed external bus
+ o External devices attached to the multiplexed external bus
interface are not supported
Serial Communications:
@@ -200,10 +200,10 @@ FreeScale HCS12 Serial Monitor
Interrupts:
The serial monitor redirects interrupt vectors to an unprotected
portion of FLASH just before the protected monitor program
- (0xf780�0xf7fe). The monitor will automatically redirect vector
+ (0xf780-0xf7fe). The monitor will automatically redirect vector
programming operations to these user vectors. The user code should
therefore keep the normal (non-monitor) vector locations
- (0xff80�0xfffe).
+ (0xff80-0xfffe).
Soft Registers
^^^^^^^^^^^^^^
diff --git a/boards/hc/m9s12/ne64badge/README.txt b/boards/hc/m9s12/ne64badge/README.txt
index 7fcc795f95..b3fbaa3955 100644
--- a/boards/hc/m9s12/ne64badge/README.txt
+++ b/boards/hc/m9s12/ne64badge/README.txt
@@ -7,22 +7,22 @@ README
CONTENTS
^^^^^^^^
- � MC9S12NE64 Features
- � NE64 Badge Pin Usage
- � Development Environment
- � NuttX Buildroot Toolchain
- � FreeScale HCS12 Serial Monitor
- � Soft Registers
- � HCS12/NE64BADGE-specific Configuration Options
- � Configurations
+ o MC9S12NE64 Features
+ o NE64 Badge Pin Usage
+ o Development Environment
+ o NuttX Buildroot Toolchain
+ o FreeScale HCS12 Serial Monitor
+ o Soft Registers
+ o HCS12/NE64BADGE-specific Configuration Options
+ o Configurations
MC9S12NE64 Features
^^^^^^^^^^^^^^^^^^^
- � 16-bit HCS12 core
+ o 16-bit HCS12 core
- HCS12 CPU
- Upward compatible with M68HC11 instruction set
- - Interrupt stacking and programmer�s model identical to M68HC11
+ - Interrupt stacking and programmer's model identical to M68HC11
- Instruction queue
- Enhanced indexed addressing
- Memory map and interface (MMC)
@@ -32,16 +32,16 @@ MC9S12NE64 Features
trace buffer (DBG)
- Multiplexed expansion bus interface (MEBI) - available only in
112-pin package version
- � Wakeup interrupt inputs
+ o Wakeup interrupt inputs
- Up to 21 port bits available for wakeup interrupt function with
digital filtering
- � Memory
+ o Memory
- 64K bytes of FLASH EEPROM
- 8K bytes of RAM
- � Analog-to-digital converter (ATD)
+ o Analog-to-digital converter (ATD)
- One 8-channel module with 10-bit resolution
- External conversion trigger capability
- � Timer module (TIM)
+ o Timer module (TIM)
- 4-channel timer
- Each channel configurable as either input capture or output
compare
@@ -50,11 +50,11 @@ MC9S12NE64 Features
- 16-bit pulse accumulator
- External event counting
- Gated time accumulation
- � Serial interfaces
+ o Serial interfaces
- Two asynchronous serial communications interface (SCI)
- One synchronous serial peripheral interface (SPI)
- One inter-IC bus (IIC)
- � Ethernet Media access controller (EMAC)
+ o Ethernet Media access controller (EMAC)
- IEEE 802.3 compliant
- Medium-independent interface (MII)
- Full-duplex and half-duplex modes
@@ -66,10 +66,10 @@ MC9S12NE64 Features
- Exact match for single 48-bit individual (unicast) address
- Hash (64-bit hash) check of group (multicast) addresses
- Promiscuous mode
- � Ethertype filter
- � Loopback mode
- � Two receive and one transmit Ethernet buffer interfaces
- � Ethernet 10/100 Mbps transceiver (EPHY)
+ o Ethertype filter
+ o Loopback mode
+ o Two receive and one transmit Ethernet buffer interfaces
+ o Ethernet 10/100 Mbps transceiver (EPHY)
- IEEE 802.3 compliant
- Digital adaptive equalization
- Half-duplex and full-duplex
@@ -78,7 +78,7 @@ MC9S12NE64 Features
- 125-MHz clock generator and timing recovery
- Integrated wave-shaping circuitry
- Loopback modes
- � CRG (clock and reset generator module)
+ o CRG (clock and reset generator module)
- Windowed COP watchdog
- Real-time interrupt
- Clock monitor
@@ -86,19 +86,19 @@ MC9S12NE64 Features
- Phase-locked loop clock frequency multiplier
- Limp home mode in absence of external clock
- 25-MHz crystal oscillator reference clock
- � Operating frequency
+ o Operating frequency
- 50 MHz equivalent to 25 MHz bus speed for single chip
- 32 MHz equivalent to 16 MHz bus speed in expanded bus modes
- � Internal 2.5-V regulator
- - Supports an input voltage range from 3.3 V � 5%
+ o Internal 2.5-V regulator
+ - Supports an input voltage range from 3.3 V ± 5%
- Low-power mode capability
- Includes low-voltage reset (LVR) circuitry
- � 80-pin TQFP-EP or 112-pin LQFP package
+ o 80-pin TQFP-EP or 112-pin LQFP package
- Up to 70 I/O pins with 3.3 V input and drive capability (112-pin
package)
- Up to two dedicated 3.3 V input only lines (IRQ, XIRQ)
- � Development support
- - Single-wire background debug� mode (BDM)
+ o Development support
+ - Single-wire background debug mode (BDM)
- On-chip hardware breakpoints
- Enhanced DBG debug features
@@ -282,21 +282,21 @@ FreeScale HCS12 Serial Monitor
Memory Configuration:
Registers:
- � Register space is located at 0x0000�0x03ff.
+ o Register space is located at 0x0000-0x03ff.
FLASH:
- � FLASH memory is any address greater than 0x4000. All paged
+ o FLASH memory is any address greater than 0x4000. All paged
addresses are assumed to be FLASH memory.
- � Application code should exclude the 0xf780�0xff7f memory.
+ o Application code should exclude the 0xf780-0xff7f memory.
SRAM:
- � RAM ends at 0x3FFF and builds down to the limit of the device�s
+ o RAM ends at 0x3FFF and builds down to the limit of the device's
available RAM.
- � The serial monitor's stack pointer is set to the end of RAM+1
+ o The serial monitor's stack pointer is set to the end of RAM+1
(0x4000).
EEPROM:
- � EEPROM (if the target device has any) is limited to the available
- space between the registers and the RAM (0x0400�to start of RAM).
+ o EEPROM (if the target device has any) is limited to the available
+ space between the registers and the RAM (0x0400 to start of RAM).
External Devices:
- � External devices attached to the multiplexed external bus
+ o External devices attached to the multiplexed external bus
interface are not supported
Serial Communications:
@@ -307,10 +307,10 @@ FreeScale HCS12 Serial Monitor
Interrupts:
The serial monitor redirects interrupt vectors to an unprotected
portion of FLASH just before the protected monitor program
- (0xf780�0xf7fe). The monitor will automatically redirect vector
+ (0xf780-0xf7fe). The monitor will automatically redirect vector
programming operations to these user vectors. The user code should
therefore keep the normal (non-monitor) vector locations
- (0xff80�0xfffe).
+ (0xff80-0xfffe).
Soft Registers
^^^^^^^^^^^^^^
diff --git a/drivers/analog/pga11x.c b/drivers/analog/pga11x.c
index 81a9648307..d0d74d5e27 100644
--- a/drivers/analog/pga11x.c
+++ b/drivers/analog/pga11x.c
@@ -19,7 +19,7 @@
/****************************************************************************
* References:
- * "PGA112, PGA113, PGA116, PGA117: Zer�-Drift PROGRAMMABLE GAIN AMPLIFIER
+ * "PGA112, PGA113, PGA116, PGA117: Zerø-Drift PROGRAMMABLE GAIN AMPLIFIER
* with MUX", SBOS424B, March 2008, Revised September 2008, Texas
* Instruments Incorporated"
*
diff --git a/drivers/input/stmpe811_temp.c b/drivers/input/stmpe811_temp.c
index 8c7bff3f57..f3dbaeafcc 100644
--- a/drivers/input/stmpe811_temp.c
+++ b/drivers/input/stmpe811_temp.c
@@ -19,7 +19,7 @@
****************************************************************************/
/* References:
- * "STMPE811 S-Touch� advanced resistive touchscreen controller with 8-bit
+ * "STMPE811 S-Touch® advanced resistive touchscreen controller with 8-bit
* GPIO expander," Doc ID 14489 Rev 6, CD00186725, STMicroelectronics"
*/
diff --git a/drivers/lcd/sd1329.h b/drivers/lcd/sd1329.h
index 926150ecbd..0b99f61d88 100644
--- a/drivers/lcd/sd1329.h
+++ b/drivers/lcd/sd1329.h
@@ -305,7 +305,7 @@
* Normal Display, Entire Display ON, Entire Display OFF or Inverse Display.
*
* Normal Display (0xa4)
- * Reset the �Entire Display ON, Entire Display OFF or Inverse Display�
+ * Reset the "Entire Display ON, Entire Display OFF or Inverse Display"
* effects and turn the data to ON at the corresponding gray level.
*
* Set Entire Display ON (0xa5)
@@ -318,7 +318,7 @@
*
* Inverse Display (0xa7)
* The gray scale level of display data are swapped such that
- * �GS0� <-> �GS15�, �GS1� <-> �GS14�, etc.
+ * "GS0" <-> "GS15", "GS1" <-> "GS14", etc.
*
* Byte 1: Display mode command
*/
@@ -359,27 +359,27 @@
* is defined separately. The lower nibble adjusts the phase length of Reset
* (phase 1). The higher nibble is used to select the phase length of first
* pre-charge phase (phase 2). The phase length is ranged from 1 to 16
- * DCLK's. RESET for A[3:0] is set to 3 which means 4 DCLK�s selected for
- * Reset phase. POR for A[7:4] is set to 5 which means 6 DCLK�s is selected
+ * DCLK's. RESET for A[3:0] is set to 3 which means 4 DCLK's selected for
+ * Reset phase. POR for A[7:4] is set to 5 which means 6 DCLK's is selected
* for first pre-charge phase.
* Please refer to Table 9-1 for detail breakdown levels of each step.
*
* Byte 1: 0xb1
- * Byte 2: A[3:0]: Phase 1 period of 1~16 DCLK�s
- * A[7:4]: Phase 2 period of 1~16 DCLK�s
+ * Byte 2: A[3:0]: Phase 1 period of 1~16 DCLK's
+ * A[7:4]: Phase 2 period of 1~16 DCLK's
*/
#define SSD1329_PHASE_LENGTH 0xb1
/* Set Frame Frequency
*
- * This double byte command is used to set the number of DCLK�s per row
+ * This double byte command is used to set the number of DCLK's per row
* between the range of 0x14 and 0x7f. Then the Frame frequency of the
* matrix display is equal to DCLK frequency / A[6:0].
*
* Byte 1: 0xb2
- * Byte 2: A[6:0]:Total number of DCLK�s per row. Ranging from
- * 0x14 to 0x4e DCLK�s. frame Frequency = DCLK freq /A[6:0].
+ * Byte 2: A[6:0]:Total number of DCLK's per row. Ranging from
+ * 0x14 to 0x4e DCLK's. frame Frequency = DCLK freq /A[6:0].
*/
#define SSD1329_FRAME_FREQ 0xb2
@@ -420,7 +420,7 @@
* Except gray scale level GS0 that has no pre-charge and current drive, each
* gray scale level is programmed in the length of current drive stage pulse
* width with unit of DCLK. The longer the length of the pulse width, the
- * brighter the OLED pixel when it�s turned ON.
+ * brighter the OLED pixel when it's turned ON.
*
* The setting of gray scale table entry can perform gamma correction on OLED
* panel display. Normally, it is desired that the brightness response of the
diff --git a/drivers/power/battery/max1704x.c b/drivers/power/battery/max1704x.c
index 7b8049991f..151a385b4b 100644
--- a/drivers/power/battery/max1704x.c
+++ b/drivers/power/battery/max1704x.c
@@ -98,7 +98,7 @@
/* "SOC Register. The SOC register is a read-only register that displays the
* state of charge of the cell as calculated by the ModelGauge algorithm.
- * The result is displayed as a percentage of the cell�s full capacity...
+ * The result is displayed as a percentage of the cell's full capacity...
*
* "...Units of % can be directly determined by observing only the high byte
* of the SOC register. The low byte provides additional resolution in units
diff --git a/drivers/wireless/spirit/include/spirit_regs.h b/drivers/wireless/spirit/include/spirit_regs.h
index 8f23711379..4637f502a3 100644
--- a/drivers/wireless/spirit/include/spirit_regs.h
+++ b/drivers/wireless/spirit/include/spirit_regs.h
@@ -242,13 +242,13 @@
* low), default configuration after POR */
#define CONF_GPIO_OUT_POR_Inv ((uint8_t)0x08) /* POR inverted (active low) */
#define CONF_GPIO_OUT_WUT_Exp ((uint8_t)0x10) /* Wake-Up Timer expiration:
- * �1� when WUT has expired */
-#define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /* Low battery detection: �1� when
+ * '1' when WUT has expired */
+#define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /* Low battery detection: '1' when
* battery is below threshold setting */
#define CONF_GPIO_OUT_TX_Data ((uint8_t)0x20) /* TX data internal clock output (TX
* data are sampled on the rising edge
* of it) */
-#define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /* TX state indication: �1� when
+#define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /* TX state indication: '1' when
* Spirit1 is transiting in the TX state */
#define CONF_GPIO_OUT_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x30) /* TX FIFO Almost Empty Flag */
@@ -257,7 +257,7 @@
#define CONF_GPIO_OUT_RX_Data ((uint8_t)0x40) /* RX data output */
#define CONF_GPIO_OUT_RX_Clock ((uint8_t)0x48) /* RX clock output (recovered from
* received data) */
-#define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /* RX state indication: �1� when
+#define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /* RX state indication: '1' when
* Spirit1 is transiting in the RX state */
#define CONF_GPIO_OUT_RX_FIFO_ALMOST_FULL ((uint8_t)0x58) /* RX FIFO Almost Full Flag */
@@ -407,7 +407,7 @@
* The valid range depends on fXO and REFDIV settings;
* for fXO=26MHz
* REFDIV = 0 - SYNT[25:21] = 11...13
- * REFDIV = 1 - SYNT[25:21] = 22�27
+ * REFDIV = 1 - SYNT[25:21] = 22...27
*/
#define SYNT3_BASE ((uint8_t)0x08) /* [4:0] -> SYNT[25:21], highest 5
@@ -540,9 +540,9 @@
*
* 7:4 Reserved.
* 3:0 FC_OFFSET[11:8]: Carrier offset. This value is the higher part of a
- * 12-bit 2�s complement integer representing an
+ * 12-bit 2's complement integer representing an
* offset in 99Hz(2) units added/subtracted to the
- * carrier frequency set by registers SYNT3�SYNT0.
+ * carrier frequency set by registers SYNT3...SYNT0.
* This register can be used to set a fixed
* correction value obtained e.g. from crystal
* measurements.
@@ -556,20 +556,20 @@
* Default value: 0x00
* Read Write
* 7:0 FC_OFFSET[7:0]: Carrier offset. This value is the lower part of a
- * 12-bit 2�s complement integer representing an
+ * 12-bit 2's complement integer representing an
* offset in 99Hz(2) units added/subtracted to the
- * carrier frequency set by registers SYNT3�SYNT0.
+ * carrier frequency set by registers SYNT3...SYNT0.
* This register can be used to set a fixed correction
* value obtained e.g. from crystal measurements.
*/
#define FC_OFFSET0_BASE ((uint8_t)0x0f) /* [7:0] -> [7:0] Carrier offset
* (lower part). This value is a 12-bit
- * 2�s complement integer representing
+ * 2's complement integer representing
* an offset in fXO/2^18 (99Hz for 26
* MHz XO) units added/subtracted to
* the carrier frequency set by registers
- * SYNT3�SYNT0. Range is +/-200kHz with 26
+ * SYNT3...SYNT0. Range is +/-200kHz with 26
* MHz XO */
/* PA_LEVEL_x_Registers */
@@ -1338,7 +1338,7 @@
* Read Write
*
* 7 Reserved.
- * 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - �OR� logical function applied to
+ * 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - 'OR' logical function applied to
* CS/SQI/PQI values (masked by 7:5
* bits in PROTOCOL register)
* 5 CONTROL_FILTERING[0]: 1 - RX packet accepted if its control
@@ -1379,7 +1379,7 @@
* [RX] */
#define PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK ((uint8_t)0x20)
/* Packet discarded if the x-byte
- * (x=1�4) control field (masked by
+ * (x=1,4) control field (masked by
* the CONTROLx_MASK register) differs
* from CONTROLx_FIELD register [RX] */
#define PCKT_FLT_OPTIONS_RX_TIMEOUT_AND_OR_SELECT ((uint8_t)0x40)
@@ -1446,7 +1446,7 @@
*
* 7:0 RX_PCKT_LEN1[7:0]: Length (number of bytes) of the received
* packet:
- * RX_PCKT_LEN=RX_PCKT_LEN1 � 256 + RX_PCKT_LEN0
+ * RX_PCKT_LEN=RX_PCKT_LEN1 x 256 + RX_PCKT_LEN0
* This value is packet_length/256
*/
@@ -1460,11 +1460,11 @@
*
* 7:0 RX_PCKT_LEN0[7:0]: Length (number of bytes) of the received
* packet:
- * RX_PCKT_LEN=RX_PCKT_LEN1 � 256 + RX_PCKT_LEN0
+ * RX_PCKT_LEN=RX_PCKT_LEN1 x 256 + RX_PCKT_LEN0
* This value is packet_length%256
*/
#define RX_PCKT_LEN0_BASE ((uint8_t)0xca) /* RX_PCKT_LEN=RX_PCKT_LEN1
- * � 256 + RX_PCKT_LEN0 */
+ * x 256 + RX_PCKT_LEN0 */
/* CRC_FIELD[2:0] registers
*
@@ -1693,7 +1693,7 @@
* Read Write
* 7:2 BU_PRESCALER[5:0]: Used to program the back-off unit BU
* 1:0 CCA_PERIOD[1:0]: Used to program the Tcca time
- * (64 / 128 /256 / 512 � Tbit.
+ * (64 / 128 /256 / 512 x Tbit.
*/
#define CSMA_CONFIG1_BASE ((uint8_t)0x66) /* CSMA/CA: Prescaler of the back-off
@@ -2184,7 +2184,7 @@
* 27 | TX circuitry start-up time
* 28 | RX circuitry start-up time
* 29 | RX operation timeout
- * 30 | Others AES End�of �Operation
+ * 30 | Others AES End-of-Operation
* 31 | Reserved
*/
@@ -2320,7 +2320,7 @@
* 27 | TX circuitry start-up time
* 28 | RX circuitry start-up time
* 29 | RX operation timeout
- * 30 | Others AES End�of �Operation
+ * 30 | Others AES End-of-Operation
* 31 | Reserved
*/
diff --git a/drivers/wireless/spirit/lib/spirit_pktmbus.c b/drivers/wireless/spirit/lib/spirit_pktmbus.c
index c040a85f50..0b0f79e0d0 100644
--- a/drivers/wireless/spirit/lib/spirit_pktmbus.c
+++ b/drivers/wireless/spirit/lib/spirit_pktmbus.c
@@ -208,7 +208,7 @@ int spirit_pktmbus_set_format(FAR struct spirit_library_s *spirit)
* Name: spirit_pktmbus_set_preamble
*
* Description:
- * Sets how many chip sequence �01� shall be added in the preamble respect
+ * Sets how many chip sequence '01' shall be added in the preamble respect
* to the minimum value as defined according to the specified sub-mode.
*
* Input Parameters:
@@ -260,7 +260,7 @@ uint8_t spirit_pktmbus_get_preamble(FAR struct spirit_library_s *spirit)
* Name: spirit_pktmbus_set_postamble
*
* Description:
- * Sets how many chip sequence �01� will be used in postamble
+ * Sets how many chip sequence '01' will be used in postamble
*
* Input Parameters:
* spirit - Reference to a Spirit library state structure instance
diff --git a/include/nuttx/binfmt/ieee695.h b/include/nuttx/binfmt/ieee695.h
index 5358f87029..770d621819 100644
--- a/include/nuttx/binfmt/ieee695.h
+++ b/include/nuttx/binfmt/ieee695.h
@@ -106,7 +106,7 @@
#define IEEE695_COMENT_TRANSLATOR 0x00 /* Translator (may name the source language or translator) */
#define IEEE695_COMENT_INTELCOPY 0x01 /* Intel copyright (ignored) */
- /* 0x2�0x9b Intel reserved */
+ /* 0x2-0x9b Intel reserved */
#define IEEE695_COMENT_LIBSPEC 0x81 /* Library specifier (Replaced by comment class 9f) */
#define IEEE695_COMENT_MSDOSVER 0x9c /* MS-DOS version (obsolete) */
#define IEEE695_COMENT_MEMMODEL 0x9d /* Memory model */
@@ -373,7 +373,7 @@ struct ieee695_record_s
#define SIZEOF_IEEE695_RECORD(len) (sizeof(struct ieee695_record_s)+(len))
-/* 80H THEADR�Translator Header Record */
+/* 80H THEADR - Translator Header Record */
struct ieee695_theadr_s
{
@@ -383,7 +383,7 @@ struct ieee695_theadr_s
uint8_t name[1]; /* Name string data begins here */
};
-/* 82H LHEADR�Library Module Header Record */
+/* 82H LHEADR - Library Module Header Record */
struct ieee695_lheadr_s
{
@@ -393,7 +393,7 @@ struct ieee695_lheadr_s
uint8_t name[1]; /* Name string data begins here */
};
-/* 88H COMENT�Comment Record */
+/* 88H COMENT - Comment Record */
struct ieee695_coment_s
{
@@ -405,7 +405,7 @@ struct ieee695_coment_s
uint8_t cstring[1]; /* Commentary Byte String (optional) */
};
-/* 8AH or 8BH MODEND�Module End Record */
+/* 8AH or 8BH MODEND - Module End Record */
struct ieee695_modend_s
{
diff --git a/include/nuttx/usb/audio.h b/include/nuttx/usb/audio.h
index 001cdf512f..5be41dac1c 100644
--- a/include/nuttx/usb/audio.h
+++ b/include/nuttx/usb/audio.h
@@ -346,7 +346,7 @@
#define ADC_UD_CONTROL_OVERFLOW 0x05
#define ADC_UD_CONTROL_LATENCY 0x06
-/* Dolby Prologic� Processing Unit Control Selectors */
+/* Dolby Prologic™ Processing Unit Control Selectors */
#define ADC_DP_CONTROL_UNDEF 0x00
#define ADC_DP_CONTROL_ENABLE 0x01
@@ -1155,7 +1155,7 @@ struct adc_mpeg_decoder_desc_s
* 00 = Not supported
* 01 = Supported at Fs
* 10 = Reserved
- * 11 = Supported at Fs and �Fs.
+ * 11 = Supported at Fs and ½Fs.
* Bit 10:
* Bit 11-15: Reserved */
uint8_t md_features; /* 7: MPEG features
diff --git a/include/nuttx/usb/ehci.h b/include/nuttx/usb/ehci.h
index e37f54b5d7..ac351b6f4c 100644
--- a/include/nuttx/usb/ehci.h
+++ b/include/nuttx/usb/ehci.h
@@ -544,10 +544,10 @@
/* Micro-frame Schedule Control. Table 3-10 */
-#define SITD_FMSCHED_SSMASK_SHIFT (0) /* Bitx 0-7: Split Start Mask (�Frame S-mask) */
+#define SITD_FMSCHED_SSMASK_SHIFT (0) /* Bitx 0-7: Split Start Mask (µFrame S-mask) */
#define SITD_FMSCHED_SSMASK_MASK (0xff << SITD_FMSCHED_SSMASK_SHIFT)
# define SITD_FMSCHED_SSMASK(n) ((n) << SITD_FMSCHED_SSMASK_SHIFT)
-#define SITD_FMSCHED_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (�Frame C-Mask) */
+#define SITD_FMSCHED_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (µFrame C-Mask) */
#define SITD_FMSCHED_SCMASK_MASK (0xff << SITD_FMSCHED_SCMASK_SHIFT)
# define SITD_FMSCHED_SCMASK(n) ((n) << SITD_FMSCHED_SCMASK_SHIFT)
/* Bits 16-31: Reserved */
@@ -556,7 +556,7 @@
#define SITD_XFRSTATE_STATUS_SHIFT (0) /* Bits 0-7: Status */
#define SITD_XFRSTATE_STATUS_MASK (0xff << SITD_XFRSTATE_STATUS_SHIFT)
-#define SITD_XFRSTATE_CPROGMASK_SHIFT (8) /* Bits 8-15: �Frame Complete-split Progress Mask */
+#define SITD_XFRSTATE_CPROGMASK_SHIFT (8) /* Bits 8-15: µFrame Complete-split Progress Mask */
#define SITD_XFRSTATE_CPROGMASK_MASK (0xff << SITD_XFRSTATE_CPROGMASK_SHIFT)
#define SITD_XFRSTATE_NBYTES_SHIFT (16) /* Bits 16-25: Total Bytes To Transfer */
#define SITD_XFRSTATE_NBYTES_MASK (0x3ff << SITD_XFRSTATE_NBYTES_SHIFT)
@@ -704,10 +704,10 @@
/* Endpoint Capabilities: Queue Head DWord 2. Table 3-20 */
-#define QH_EPCAPS_SSMASK_SHIFT (0) /* Bitx 0-7: Interrupt Schedule Mask (�Frame S-mask) */
+#define QH_EPCAPS_SSMASK_SHIFT (0) /* Bitx 0-7: Interrupt Schedule Mask (µFrame S-mask) */
#define QH_EPCAPS_SSMASK_MASK (0xff << QH_EPCAPS_SSMASK_SHIFT)
# define QH_EPCAPS_SSMASK(n) ((n) << QH_EPCAPS_SSMASK_SHIFT)
-#define QH_EPCAPS_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (�Frame C-Mask) */
+#define QH_EPCAPS_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (µFrame C-Mask) */
#define QH_EPCAPS_SCMASK_MASK (0xff << QH_EPCAPS_SCMASK_SHIFT)
# define QH_EPCAPS_SCMASK(n) ((n) << QH_EPCAPS_SCMASK_SHIFT)
#define QH_EPCAPS_HUBADDR_SHIFT (16) /* Bitx 16-22: Hub Address */