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Posted to commits@mynewt.apache.org by ad...@apache.org on 2016/06/15 22:04:30 UTC
[47/51] [partial] incubator-mynewt-site git commit: Fixed broken
Quick Start link and added OpenOCD option for Arduino Primo debugging
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/dcc.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/dcc.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/dcc.c
new file mode 100755
index 0000000..6ab2417
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/dcc.c
@@ -0,0 +1,51 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+#include "dcc.h"
+
+
+/* debug channel read (debugger->MCU) */
+uint32 dcc_rd(void)
+{
+ volatile uint32 dcc_reg;
+
+ do {
+ asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) :);
+ } while ((dcc_reg&1) == 0);
+
+ asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) :);
+ return dcc_reg;
+}
+
+
+/* debug channel write (MCU->debugger) */
+int dcc_wr(uint32 data)
+{
+ volatile uint32 dcc_reg;
+
+ do {
+ asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) :);
+ /* operation controled by master, cancel operation
+ upon reception of data for immediate response */
+ if (dcc_reg&1) return -1;
+ } while (dcc_reg&2);
+
+ asm volatile ("mcr p14, 0, %0, C1, C0" : : "r" (data));
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/dcc.h
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/dcc.h b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/dcc.h
new file mode 100755
index 0000000..a3c1393
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/dcc.h
@@ -0,0 +1,31 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+#ifndef dccH
+#define dccH
+
+#include "platform.h"
+
+/* debug channel read (debugger->MCU) */
+uint32 dcc_rd(void);
+
+/* debug channel write (MCU->debugger) */
+int dcc_wr(uint32 data);
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/main.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/main.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/main.c
new file mode 100755
index 0000000..c4b4dcf
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/main.c
@@ -0,0 +1,107 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+#include "platform.h"
+
+#include <flash/nor/ocl.h>
+#include "dcc.h"
+#include "samflash.h"
+
+
+#define BUFSIZE 1024 /* words, i.e. 4 KiB */
+uint32 buffer[1024];
+
+void cmd_flash(uint32 cmd)
+{
+ unsigned int len;
+ uint32 adr;
+ uint32 chksum;
+ unsigned int bi; /* buffer index */
+ unsigned int bi_start; /* receive start mark */
+ unsigned int bi_end; /* receive end mark */
+ unsigned int ofs;
+ int pagenum;
+ int result;
+
+ adr = dcc_rd();
+ len = cmd&0xffff;
+ ofs = adr%flash_page_size;
+ bi_start = ofs/4;
+ bi_end = (ofs + len + 3)/4;
+
+ if (bi_end > BUFSIZE) {
+ dcc_wr(OCL_BUFF_OVER);
+ return;
+ }
+
+ chksum = OCL_CHKS_INIT;
+ for (bi = 0; bi < bi_end; bi++) chksum^=buffer[bi]=dcc_rd();
+
+ if (dcc_rd() != chksum) {
+ dcc_wr(OCL_CHKS_FAIL);
+ return;
+ }
+
+ /* fill in unused positions with unprogrammed values */
+ for (bi = 0; bi < bi_start; bi++) buffer[bi]=0xffffffff;
+ for (bi = bi_end; bi%flash_page_size; bi++) buffer[bi]=0xffffffff;
+
+ result = 0;
+ pagenum = adr/flash_page_size;
+ for (bi = 0; bi < bi_end; bi += flash_page_size/4) {
+ result = flash_page_program(buffer + bi, pagenum++);
+ if (result) break;
+ }
+
+ /* verify written data */
+ if (!result) result = flash_verify(adr, len, ((uint8 *)buffer) + ofs);
+
+ dcc_wr(OCL_CMD_DONE | result);
+}
+
+
+int main (void)
+{
+ uint32 cmd;
+
+ for (;;) {
+ cmd = dcc_rd();
+ switch (cmd&OCL_CMD_MASK) {
+ case OCL_PROBE:
+ dcc_wr(OCL_CMD_DONE | flash_init());
+ dcc_wr(0x100000); /* base */
+ dcc_wr(flash_page_count*flash_page_size); /* size */
+ dcc_wr(1); /* num_sectors */
+ dcc_wr(4096 | ((unsigned long) flash_page_size << 16)); /* buflen and bufalign */
+ break;
+ case OCL_ERASE_ALL:
+ dcc_wr(OCL_CMD_DONE | flash_erase_all());
+ break;
+ case OCL_FLASH_BLOCK:
+ cmd_flash(cmd);
+ break;
+ default:
+ /* unknown command */
+ dcc_wr(OCL_CMD_ERR);
+ break;
+ }
+ }
+
+ return(0); /* we shall never get here, just to supress compiler warning */
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/ocl.h
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/ocl.h b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/ocl.h
new file mode 100755
index 0000000..1fe4596
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/ocl.h
@@ -0,0 +1,40 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+#ifndef OCL_H
+#define OCL_H
+
+/* command/response mask */
+#define OCL_CMD_MASK 0xFFFF0000L
+
+/* commads */
+#define OCL_FLASH_BLOCK 0x0CFB0000L
+#define OCL_ERASE_BLOCK 0x0CEB0000L
+#define OCL_ERASE_ALL 0x0CEA0000L
+#define OCL_PROBE 0x0CBE0000L
+
+/* responses */
+#define OCL_CMD_DONE 0x0ACD0000L
+#define OCL_CMD_ERR 0x0ACE0000L
+#define OCL_CHKS_FAIL 0x0ACF0000L
+#define OCL_BUFF_OVER 0x0AB00000L
+
+#define OCL_CHKS_INIT 0xC100CD0CL
+
+#endif /* OCL_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/platform.h
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/platform.h b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/platform.h
new file mode 100755
index 0000000..2b26e4b
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/platform.h
@@ -0,0 +1,46 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+#ifndef platformH
+#define platformH
+
+#include "samregs.h"
+
+
+#define outb(_reg, _val) (*((volatile unsigned char *)(_reg)) = (_val))
+#define outw(_reg, _val) (*((volatile unsigned short *)(_reg)) = (_val))
+#define outr(_reg, _val) (*((volatile unsigned int *)(_reg)) = (_val))
+
+#define inb(_reg) (*((volatile unsigned char *)(_reg)))
+#define inw(_reg) (*((volatile unsigned short *)(_reg)))
+#define inr(_reg) (*((volatile unsigned int *)(_reg)))
+
+#define _BV(bit) (1 << (bit))
+
+
+typedef signed char int8;
+typedef unsigned char uint8;
+
+typedef signed short int16;
+typedef unsigned short uint16;
+
+typedef signed int int32;
+typedef unsigned int uint32;
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samflash.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samflash.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samflash.c
new file mode 100755
index 0000000..49c84c8
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samflash.c
@@ -0,0 +1,196 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+#include "samflash.h"
+
+
+unsigned int flash_page_count = 1024;
+unsigned int flash_page_size = 256;
+
+/* pages per lock bit */
+unsigned int flash_lock_pages = 1024/16;
+
+
+/* detect chip and set loader parameters */
+int flash_init(void)
+{
+ unsigned int nvpsiz;
+
+ nvpsiz = (inr(DBGU_CIDR) >> 8)&0xf;
+
+ switch (nvpsiz) {
+ case 3:
+ /* AT91SAM7x32 */
+ flash_page_count = 256;
+ flash_page_size = 128;
+ flash_lock_pages = 256/8;
+ break;
+ case 5:
+ /* AT91SAM7x64 */
+ flash_page_count = 512;
+ flash_page_size = 128;
+ flash_lock_pages = 512/16;
+ break;
+ case 7:
+ /* AT91SAM7x128*/
+ flash_page_count = 512;
+ flash_page_size = 256;
+ flash_lock_pages = 512/8;
+ break;
+ case 9:
+ /* AT91SAM7x256 */
+ flash_page_count = 1024;
+ flash_page_size = 256;
+ flash_lock_pages = 1024/16;
+ break;
+ case 10:
+ /* AT91SAM7x512 */
+ flash_page_count = 2048;
+ flash_page_size = 256;
+ flash_lock_pages = 2048/32;
+ break;
+ default:
+ return FLASH_STAT_INITE;
+ }
+ return FLASH_STAT_OK;
+}
+
+
+/* program single flash page */
+int flash_page_program(uint32 *data, int page_num)
+{
+ int i;
+ int efc_ofs;
+
+ uint32 *flash_ptr;
+ uint32 *data_ptr;
+
+ /* select proper controller */
+ if (page_num >= 1024) efc_ofs = 0x10;
+ else efc_ofs = 0;
+
+ /* wait until FLASH is ready, just for sure */
+ while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
+
+ /* calculate page address, only lower 8 bits are used to address the latch,
+ but the upper part of address is needed for writing to proper EFC */
+ flash_ptr = (uint32 *)(FLASH_AREA_ADDR + (page_num*flash_page_size));
+ data_ptr = data;
+
+ /* copy data to latch */
+ for (i = flash_page_size/4; i; i--) {
+ /* we do not use memcpy to be sure that only 32 bit access is used */
+ *(flash_ptr++)=*(data_ptr++);
+ }
+
+ /* page number and page write command to FCR */
+ outr(MC_FCR + efc_ofs, ((page_num&0x3ff) << 8) | MC_KEY | MC_FCMD_WP);
+
+ /* wait until it's done */
+ while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
+
+ /* check for errors */
+ if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
+ if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
+
+#if 0
+ /* verify written data */
+ flash_ptr = (uint32 *)(FLASH_AREA_ADDR + (page_num*flash_page_size));
+ data_ptr = data;
+
+ for (i = flash_page_size/4; i; i--) {
+ if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE;
+ }
+#endif
+
+ return FLASH_STAT_OK;
+}
+
+
+int flash_erase_plane(int efc_ofs)
+{
+ unsigned int lockbits;
+ int page_num;
+
+ page_num = 0;
+ lockbits = inr(MC_FSR + efc_ofs) >> 16;
+ while (lockbits) {
+ if (lockbits&1) {
+
+ /* wait until FLASH is ready, just for sure */
+ while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
+
+ outr(MC_FCR + efc_ofs, ((page_num&0x3ff) << 8) | 0x5a000004);
+
+ /* wait until it's done */
+ while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
+
+ /* check for errors */
+ if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
+ if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
+
+ }
+ if ((page_num += flash_lock_pages) > flash_page_count) break;
+ lockbits>>=1;
+ }
+
+ /* wait until FLASH is ready, just for sure */
+ while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
+
+ /* erase all command to FCR */
+ outr(MC_FCR + efc_ofs, 0x5a000008);
+
+ /* wait until it's done */
+ while ((inr(MC_FSR + efc_ofs)&MC_FRDY) == 0);
+
+ /* check for errors */
+ if ((inr(MC_FSR + efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
+ if ((inr(MC_FSR + efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
+
+ /* set no erase before programming */
+ outr(MC_FMR + efc_ofs, inr(MC_FMR + efc_ofs) | 0x80);
+
+ return FLASH_STAT_OK;
+}
+
+
+/* erase whole chip */
+int flash_erase_all(void)
+{
+ int result;
+
+ if ((result = flash_erase_plane(0)) != FLASH_STAT_OK) return result;
+
+ /* the second flash controller, if any */
+ if (flash_page_count > 1024) result = flash_erase_plane(0x10);
+
+ return result;
+}
+
+
+int flash_verify(uint32 adr, unsigned int len, uint8 *src)
+{
+ unsigned char *flash_ptr;
+
+ flash_ptr = (uint8 *)FLASH_AREA_ADDR + adr;
+ for (;len; len--) {
+ if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE;
+ }
+ return FLASH_STAT_OK;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samflash.h
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samflash.h b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samflash.h
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--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samflash.h
@@ -0,0 +1,48 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+#ifndef samflashH
+#define samflashH
+
+#include "platform.h"
+
+#define FLASH_AREA_ADDR 0x100000
+
+#define FLASH_STAT_OK 0
+#define FLASH_STAT_PROGE 1
+#define FLASH_STAT_LOCKE 2
+#define FLASH_STAT_VERIFE 3
+#define FLASH_STAT_INITE 4
+
+extern unsigned int flash_page_count;
+extern unsigned int flash_page_size; /* words */
+
+/* detect chip and set loader parameters */
+int flash_init(void);
+
+/* program single flash page */
+int flash_page_program(uint32 *data, int page_num);
+
+/* erase whole chip */
+int flash_erase_all(void);
+
+/* verify written data */
+int flash_verify(uint32 adr, unsigned int len, uint8 *src);
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samregs.h
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samregs.h b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samregs.h
new file mode 100755
index 0000000..b206fd2
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/samregs.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+
+#ifndef samregsH
+#define samregsH
+
+
+/*
+ * Register definitions below copied from NutOS
+ */
+
+#define DBGU_BASE 0xFFFFF200 /*!< \brief DBGU base address. */
+
+#define DBGU_CIDR_OFF 0x00000040 /*!< \brief DBGU chip ID register offset. */
+#define DBGU_CIDR (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */
+
+
+#define MC_BASE 0xFFFFFF00 /*!< \brief Memory controller base. */
+
+#define MC_FMR_OFF 0x00000060 /*!< \brief MC flash mode register offset. */
+#define MC_FMR (MC_BASE + MC_FMR_OFF) /*!< \brief MC flash mode register address. */
+#define MC_FRDY 0x00000001 /*!< \brief Flash ready. */
+#define MC_LOCKE 0x00000004 /*!< \brief Lock error. */
+#define MC_PROGE 0x00000008 /*!< \brief Programming error. */
+#define MC_NEBP 0x00000080 /*!< \brief No erase before programming. */
+#define MC_FWS_MASK 0x00000300 /*!< \brief Flash wait state mask. */
+#define MC_FWS_1R2W 0x00000000 /*!< \brief 1 cycle for read, 2 for write operations. */
+#define MC_FWS_2R3W 0x00000100 /*!< \brief 2 cycles for read, 3 for write operations. */
+#define MC_FWS_3R4W 0x00000200 /*!< \brief 3 cycles for read, 4 for write operations. */
+#define MC_FWS_4R4W 0x00000300 /*!< \brief 4 cycles for read and write operations. */
+#define MC_FMCN_MASK 0x00FF0000 /*!< \brief Flash microsecond cycle number mask. */
+
+#define MC_FCR_OFF 0x00000064 /*!< \brief MC flash command register offset. */
+#define MC_FCR (MC_BASE + MC_FCR_OFF) /*!< \brief MC flash command register address. */
+#define MC_FCMD_MASK 0x0000000F /*!< \brief Flash command mask. */
+#define MC_FCMD_NOP 0x00000000 /*!< \brief No command. */
+#define MC_FCMD_WP 0x00000001 /*!< \brief Write page. */
+#define MC_FCMD_SLB 0x00000002 /*!< \brief Set lock bit. */
+#define MC_FCMD_WPL 0x00000003 /*!< \brief Write page and lock. */
+#define MC_FCMD_CLB 0x00000004 /*!< \brief Clear lock bit. */
+#define MC_FCMD_EA 0x00000008 /*!< \brief Erase all. */
+#define MC_FCMD_SGPB 0x0000000B /*!< \brief Set general purpose NVM bit. */
+#define MC_FCMD_CGPB 0x0000000D /*!< \brief Clear general purpose NVM bit. */
+#define MC_FCMD_SSB 0x0000000F /*!< \brief Set security bit. */
+#define MC_PAGEN_MASK 0x0003FF00 /*!< \brief Page number mask. */
+#define MC_KEY 0x5A000000 /*!< \brief Writing protect key. */
+
+#define MC_FSR_OFF 0x00000068 /*!< \brief MC flash status register offset. */
+#define MC_FSR (MC_BASE + MC_FSR_OFF) /*!< \brief MC flash status register address. */
+#define MC_SECURITY 0x00000010 /*!< \brief Security bit status. */
+
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/cortex-m0.S
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/cortex-m0.S b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/cortex-m0.S
new file mode 100755
index 0000000..a905a36
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/cortex-m0.S
@@ -0,0 +1,72 @@
+/***************************************************************************
+ * Copyright (C) 2014 by Angus Gratton *
+ * Derived from stm32f1x.S:
+ * Copyright (C) 2011 by Andreas Fritiofson *
+ * andreas.fritiofson@gmail.com *
+ * Copyright (C) 2013 by Roman Dmitrienko *
+ * me@iamroman.org *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+ .text
+ .syntax unified
+ .cpu cortex-m0
+ .thumb
+ .thumb_func
+
+/* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is
+ * very generic (CPU blocks during flash writes), so this is actually
+ * just a generic word-oriented copy routine for cortex-m0 (also
+ * suitable for cortex m0plus/m3/m4.)
+ *
+ * To assemble:
+ * arm-none-eabi-gcc -c cortex-m0.S
+ *
+ * To disassemble:
+ * arm-none-eabi-objdump -o cortex-m0.o
+ *
+ * Thanks to Jens Bauer for providing advice on some of the tweaks.
+ */
+
+ /* Params:
+ * r0 - byte count (in)
+ * r1 - workarea start
+ * r2 - workarea end
+ * r3 - target address
+ * Clobbered:
+ * r4 - rp
+ * r5 - wp, tmp
+ */
+
+wait_fifo:
+ ldr r5, [r1, #0] /* read wp */
+ cmp r5, #0 /* abort if wp == 0 */
+ beq exit
+ ldr r4, [r1, #4] /* read rp */
+ cmp r4, r5 /* wait until rp != wp */
+ beq wait_fifo
+
+ ldmia r4!, {r5} /* "*target_address++ = *rp++" */
+ stmia r3!, {r5}
+
+ cmp r4, r2 /* wrap rp at end of work area buffer */
+ bcc no_wrap
+ mov r4, r1
+ adds r4, #8 /* skip rp,wp at start of work area */
+no_wrap:
+ str r4, [r1, #4] /* write back rp */
+ subs r0, #4 /* decrement byte count */
+ bne wait_fifo /* loop if not done */
+exit:
+ bkpt #0
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/efm32.S
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/efm32.S b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/efm32.S
new file mode 100755
index 0000000..25d6301
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/efm32.S
@@ -0,0 +1,114 @@
+/***************************************************************************
+ * Copyright (C) 2011 by Andreas Fritiofson *
+ * andreas.fritiofson@gmail.com *
+ * Copyright (C) 2013 by Roman Dmitrienko *
+ * me@iamroman.org *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .syntax unified
+ .cpu cortex-m0
+ .thumb
+ .thumb_func
+
+ /* Params:
+ * r0 - flash base (in), status (out)
+ * r1 - count (word-32bit)
+ * r2 - workarea start
+ * r3 - workarea end
+ * r4 - target address
+ * Clobbered:
+ * r5 - rp
+ * r6 - wp, tmp
+ * r7 - tmp
+ */
+
+/* offsets of registers from flash reg base */
+#define EFM32_MSC_WRITECTRL_OFFSET 0x008
+#define EFM32_MSC_WRITECMD_OFFSET 0x00c
+#define EFM32_MSC_ADDRB_OFFSET 0x010
+#define EFM32_MSC_WDATA_OFFSET 0x018
+#define EFM32_MSC_STATUS_OFFSET 0x01c
+#define EFM32_MSC_LOCK_OFFSET 0x03c
+
+ /* unlock MSC */
+ ldr r6, =#0x1b71
+ str r6, [r0, #EFM32_MSC_LOCK_OFFSET]
+ /* set WREN to 1 */
+ movs r6, #1
+ str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
+
+wait_fifo:
+ ldr r6, [r2, #0] /* read wp */
+ cmp r6, #0 /* abort if wp == 0 */
+ beq exit
+ ldr r5, [r2, #4] /* read rp */
+ cmp r5, r6 /* wait until rp != wp */
+ beq wait_fifo
+
+ /* store address in MSC_ADDRB */
+ str r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
+ /* set LADDRIM bit */
+ movs r6, #1
+ str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
+ /* check status for INVADDR and/or LOCKED */
+ ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
+ movs r7, #6
+ tst r6, r7
+ bne error
+
+ /* wait for WDATAREADY */
+wait_wdataready:
+ ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
+ movs r7, #8
+ tst r6, r7
+ beq wait_wdataready
+
+ /* load data to WDATA */
+ ldr r6, [r5]
+ str r6, [r0, #EFM32_MSC_WDATA_OFFSET]
+ /* set WRITEONCE bit */
+ movs r6, #8
+ str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
+
+ adds r5, #4 /* rp++ */
+ adds r4, #4 /* target_address++ */
+
+ /* wait until BUSY flag is reset */
+busy:
+ ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
+ movs r7, #1
+ tst r6, r7
+ bne busy
+
+ cmp r5, r3 /* wrap rp at end of buffer */
+ bcc no_wrap
+ mov r5, r2
+ adds r5, #8
+no_wrap:
+ str r5, [r2, #4] /* store rp */
+ subs r1, r1, #1 /* decrement word count */
+ cmp r1, #0
+ beq exit /* loop if not done */
+ b wait_fifo
+error:
+ movs r0, #0
+ str r0, [r2, #4] /* set rp = 0 on error */
+exit:
+ mov r0, r6 /* return status in r0 */
+ bkpt #0
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/erase.S
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/erase.S b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/erase.S
new file mode 100755
index 0000000..6fdf81d
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/erase.S
@@ -0,0 +1,77 @@
+/*
+ * Spansion FM4 flash sector erase algorithm
+ *
+ * Copyright (c) 2015 Andreas F�rber
+ *
+ * Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
+ */
+
+#include "fm4.h"
+
+#define RESULT_OKAY 0
+#define RESULT_NONE 1
+#define RESULT_TIMEOUT 2
+
+ .macro busy_wait, res, addr, tmp1, tmp2, tmp3
+
+ ldrb \tmp1, [\addr] /* ignore */
+1001:
+ ldrb \tmp1, [\addr]
+ ldrb \tmp2, [\addr]
+
+ and \tmp3, \tmp1, #FLASH_TOGG
+ and \tmp2, \tmp2, #FLASH_TOGG
+ cmp \tmp3, \tmp2
+ beq 1010f
+
+ and \tmp2, \tmp1, #FLASH_TLOV
+ cmp \tmp2, #0
+ beq 1001b
+
+ ldrb \tmp1, [\addr]
+ ldrb \tmp2, [\addr]
+
+ and \tmp3, \tmp1, #FLASH_TOGG
+ and \tmp2, \tmp2, #FLASH_TOGG
+ cmp \tmp3, \tmp2
+ beq 1010f
+
+ mov \res, #RESULT_TIMEOUT
+ bkpt #0
+1010:
+ mov \res, #RESULT_OKAY
+
+ .endm
+
+
+ .macro erase, cmdseqaddr1, cmdseqaddr2, sa, res, tmp1, tmp2, tmp3
+
+ mov \res, #RESULT_NONE
+
+ mov \tmp1, #0xAA
+ strh \tmp1, [\cmdseqaddr1]
+ mov \tmp2, #0x55
+ strh \tmp2, [\cmdseqaddr2]
+ mov \tmp3, #0x80
+ strh \tmp3, [\cmdseqaddr1]
+ strh \tmp1, [\cmdseqaddr1]
+ strh \tmp2, [\cmdseqaddr2]
+ mov \tmp3, #0x30
+ strh \tmp3, [\sa]
+
+ busy_wait \res, \sa, \tmp1, \tmp2, \tmp3
+
+ .endm
+
+
+ /* r0 = 0xAA8
+ * r1 = 0x554
+ * r2 = SA
+ * r3 = result
+ */
+erase:
+ erase r0, r1, r2, r3, r4, r5, r6
+
+ bkpt #0
+
+data:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/erase.inc
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/erase.inc b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/erase.inc
new file mode 100755
index 0000000..9f38067
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/erase.inc
@@ -0,0 +1,7 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x4f,0xf0,0x01,0x03,0x4f,0xf0,0xaa,0x04,0x04,0x80,0x4f,0xf0,0x55,0x05,0x0d,0x80,
+0x4f,0xf0,0x80,0x06,0x06,0x80,0x04,0x80,0x0d,0x80,0x4f,0xf0,0x30,0x06,0x16,0x80,
+0x14,0x78,0x14,0x78,0x15,0x78,0x04,0xf0,0x40,0x06,0x05,0xf0,0x40,0x05,0xae,0x42,
+0x0e,0xd0,0x04,0xf0,0x20,0x05,0x00,0x2d,0xf3,0xd0,0x14,0x78,0x15,0x78,0x04,0xf0,
+0x40,0x06,0x05,0xf0,0x40,0x05,0xae,0x42,0x02,0xd0,0x4f,0xf0,0x02,0x03,0x00,0xbe,
+0x4f,0xf0,0x00,0x03,0x00,0xbe,
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/fm4.h
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/fm4.h b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/fm4.h
new file mode 100755
index 0000000..603aac8
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/fm4.h
@@ -0,0 +1,19 @@
+/*
+ * Spansion FM4 flash macros
+ *
+ * Copyright (c) 2015 Andreas F�rber
+ *
+ * Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
+ */
+
+ .text
+ .syntax unified
+ .cpu cortex-m4
+ .thumb
+ .thumb_func
+
+
+#define FLASH_DPOL (1 << 7)
+#define FLASH_TOGG (1 << 6)
+#define FLASH_TLOV (1 << 5)
+#define FLASH_TOGG2 (1 << 2)
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/write.S
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/write.S b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/write.S
new file mode 100755
index 0000000..a8d01cd
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/write.S
@@ -0,0 +1,85 @@
+/*
+ * Spansion FM4 flash write algorithm
+ *
+ * Copyright (c) 2015 Andreas F�rber
+ *
+ * Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
+ */
+
+#include "fm4.h"
+
+#define RESULT_OKAY 0
+#define RESULT_NONE 1
+#define RESULT_TIMEOUT 2
+
+ .macro busy_wait, res, addr, data, tmp1, tmp2, tmp3
+
+ ldrb \tmp1, [\addr] /* ignore */
+ and \tmp2, \data, #FLASH_DPOL
+1001:
+ ldrb \tmp1, [\addr]
+ and \tmp3, \tmp1, #FLASH_DPOL
+ cmp \tmp3, \tmp2
+ beq 1010f
+
+ and \tmp3, \tmp1, #FLASH_TLOV
+ cmp \tmp3, #0
+ beq 1001b
+
+ ldrb \tmp1, [\addr]
+ and \tmp3, \tmp1, #FLASH_DPOL
+ cmp \tmp3, \tmp2
+ beq 1010f
+
+ mov \res, #RESULT_TIMEOUT
+ bkpt #0
+1010:
+ .endm
+
+
+ .macro write_one, res, cmdseqaddr1, cmdseqaddr2, pa, pd, tmp1, tmp2, tmp3
+
+ mov \tmp1, #0xAA
+ strh \tmp1, [\cmdseqaddr1]
+ mov \tmp1, #0x55
+ strh \tmp1, [\cmdseqaddr2]
+ mov \tmp1, #0xA0
+ strh \tmp1, [\cmdseqaddr1]
+ strh \pd, [\pa]
+
+ busy_wait \res, \pa, \pd, \tmp1, \tmp2, \tmp3
+
+ .endm
+
+
+ .macro write, cmdseqaddr1, cmdseqaddr2, dest, src, cnt, res, tmp1, tmp2, tmp3, tmp4
+
+ mov \res, #RESULT_NONE
+2001:
+ cbz \cnt, 2010f
+
+ ldrh \tmp1, [\src]
+ write_one \res, \cmdseqaddr1, \cmdseqaddr2, \dest, \tmp1, \tmp2, \tmp3, \tmp4
+
+ sub \cnt, \cnt, #1
+ add \dest, \dest, #2
+ add \src, \src, #2
+ b 2001b
+2010:
+ mov \res, #RESULT_OKAY
+ .endm
+
+
+ /* r0 = 0xAA8
+ * r1 = 0x554
+ * r2 = dest
+ * r3 = src
+ * r4 = cnt
+ * r5 = result
+ */
+write:
+ write r0, r1, r2, r3, r4, r5, r6, r7, r8, r9
+
+ bkpt #0
+
+data:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/write.inc
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/write.inc b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/write.inc
new file mode 100755
index 0000000..3d8472b
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fm4/write.inc
@@ -0,0 +1,7 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x4f,0xf0,0x01,0x05,0x34,0xb3,0x1e,0x88,0x4f,0xf0,0xaa,0x07,0x07,0x80,0x4f,0xf0,
+0x55,0x07,0x0f,0x80,0x4f,0xf0,0xa0,0x07,0x07,0x80,0x16,0x80,0x17,0x78,0x06,0xf0,
+0x80,0x08,0x17,0x78,0x07,0xf0,0x80,0x09,0xc1,0x45,0x0c,0xd0,0x07,0xf0,0x20,0x09,
+0xb9,0xf1,0x00,0x0f,0xf5,0xd0,0x17,0x78,0x07,0xf0,0x80,0x09,0xc1,0x45,0x02,0xd0,
+0x4f,0xf0,0x02,0x05,0x00,0xbe,0xa4,0xf1,0x01,0x04,0x02,0xf1,0x02,0x02,0x03,0xf1,
+0x02,0x03,0xd7,0xe7,0x4f,0xf0,0x00,0x05,0x00,0xbe,
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fpga/xilinx_bscan_spi.py
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fpga/xilinx_bscan_spi.py b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fpga/xilinx_bscan_spi.py
new file mode 100755
index 0000000..a107a6a
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/fpga/xilinx_bscan_spi.py
@@ -0,0 +1,317 @@
+#!/usr/bin/python3
+#
+# Copyright (C) 2015 Robert Jordens <jo...@gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+from migen.fhdl.std import *
+from mibuild.generic_platform import *
+from mibuild.xilinx import XilinxPlatform
+from mibuild.xilinx.vivado import XilinxVivadoToolchain
+from mibuild.xilinx.ise import XilinxISEToolchain
+
+
+"""
+This migen script produces proxy bitstreams to allow programming SPI flashes
+behind FPGAs. JTAG signalling is connected directly to SPI signalling. CS_N is
+asserted when the JTAG IR contains the USER1 instruction and the state is
+SHIFT-DR.
+
+Xilinx bscan cells sample TDO on falling TCK and forward it.
+MISO requires sampling on rising CLK and leads to one cycle of latency.
+
+https://github.com/m-labs/migen
+"""
+
+
+class Spartan3(Module):
+ macro = "BSCAN_SPARTAN3"
+
+ def __init__(self, platform):
+ self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
+ spi = platform.request("spiflash")
+ shift = Signal()
+ tdo = Signal()
+ sel1 = Signal()
+ self.comb += [
+ self.cd_jtag.clk.eq(spi.clk),
+ spi.cs_n.eq(~shift | ~sel1),
+ ]
+ self.sync.jtag += tdo.eq(spi.miso)
+ self.specials += Instance(self.macro,
+ o_DRCK1=spi.clk, o_SHIFT=shift,
+ o_TDI=spi.mosi, i_TDO1=tdo, i_TDO2=0,
+ o_SEL1=sel1)
+
+
+class Spartan3A(Spartan3):
+ macro = "BSCAN_SPARTAN3A"
+
+
+class Spartan6(Module):
+ def __init__(self, platform):
+ self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
+ spi = platform.request("spiflash")
+ shift = Signal()
+ tdo = Signal()
+ sel = Signal()
+ self.comb += self.cd_jtag.clk.eq(spi.clk), spi.cs_n.eq(~shift | ~sel)
+ self.sync.jtag += tdo.eq(spi.miso)
+ self.specials += Instance("BSCAN_SPARTAN6", p_JTAG_CHAIN=1,
+ o_TCK=spi.clk, o_SHIFT=shift, o_SEL=sel,
+ o_TDI=spi.mosi, i_TDO=tdo)
+
+
+class Series7(Module):
+ def __init__(self, platform):
+ self.clock_domains.cd_jtag = ClockDomain(reset_less=True)
+ spi = platform.request("spiflash")
+ clk = Signal()
+ shift = Signal()
+ tdo = Signal()
+ sel = Signal()
+ self.comb += self.cd_jtag.clk.eq(clk), spi.cs_n.eq(~shift | ~sel)
+ self.sync.jtag += tdo.eq(spi.miso)
+ self.specials += Instance("BSCANE2", p_JTAG_CHAIN=1,
+ o_SHIFT=shift, o_TCK=clk, o_SEL=sel,
+ o_TDI=spi.mosi, i_TDO=tdo)
+ self.specials += Instance("STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0,
+ i_KEYCLEARB=0, i_PACK=1, i_USRCCLKO=clk,
+ i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
+
+
+class XilinxBscanSpi(XilinxPlatform):
+ pinouts = {
+ # bitstreams are named by die, package does not matter, speed grade
+ # should not matter.
+ # cs_n, clk, mosi, miso, *pullups
+ "xc3s100e": ("cp132",
+ ["M2", "N12", "N2", "N8"],
+ "LVCMOS33", Spartan3),
+ "xc3s1200e": ("fg320",
+ ["U3", "U16", "T4", "N10"],
+ "LVCMOS33", Spartan3),
+ "xc3s1400a": ("fg484",
+ ["Y4", "AA20", "AB14", "AB20"],
+ "LVCMOS33", Spartan3A),
+ "xc3s1400an": ("fgg484",
+ ["Y4", "AA20", "AB14", "AB20"],
+ "LVCMOS33", Spartan3A),
+ "xc3s1600e": ("fg320",
+ ["U3", "U16", "T4", "N10"],
+ "LVCMOS33", Spartan3),
+ "xc3s200a": ("fg320",
+ ["V3", "U16", "T11", "V16"],
+ "LVCMOS33", Spartan3A),
+ "xc3s200an": ("ftg256",
+ ["T2", "R14", "P10", "T14"],
+ "LVCMOS33", Spartan3A),
+ "xc3s250e": ("cp132",
+ ["M2", "N12", "N2", "N8"],
+ "LVCMOS33", Spartan3),
+ "xc3s400a": ("fg320",
+ ["V3", "U16", "T11", "V16"],
+ "LVCMOS33", Spartan3A),
+ "xc3s400an": ("fgg400",
+ ["Y2", "Y19", "W12", "W18"],
+ "LVCMOS33", Spartan3A),
+ "xc3s500e": ("cp132",
+ ["M2", "N12", "N2", "N8"],
+ "LVCMOS33", Spartan3),
+ "xc3s50a": ("ft256",
+ ["T2", "R14", "P10", "T14"],
+ "LVCMOS33", Spartan3A),
+ "xc3s50an": ("ftg256",
+ ["T2", "R14", "P10", "T14"],
+ "LVCMOS33", Spartan3A),
+ "xc3s700a": ("fg400",
+ ["Y2", "Y19", "W12", "W18"],
+ "LVCMOS33", Spartan3A),
+ "xc3s700an": ("fgg484",
+ ["Y4", "AA20", "AB14", "AB20"],
+ "LVCMOS33", Spartan3A),
+ "xc3sd1800a": ("cs484",
+ ["U7", "V17", "V13", "W17"],
+ "LVCMOS33", Spartan3A),
+ "xc3sd3400a": ("cs484",
+ ["U7", "V17", "V13", "W17"],
+ "LVCMOS33", Spartan3A),
+
+ "xc6slx100": ("csg484-2",
+ ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
+ "LVCMOS33", Spartan6),
+ "xc6slx100t": ("csg484-2",
+ ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
+ "LVCMOS33", Spartan6),
+ "xc6slx150": ("csg484-2",
+ ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
+ "LVCMOS33", Spartan6),
+ "xc6slx150t": ("csg484-2",
+ ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
+ "LVCMOS33", Spartan6),
+ "xc6slx16": ("cpg196-2",
+ ["P2", "N13", "P11", "N11", "N10", "P10"],
+ "LVCMOS33", Spartan6),
+ "xc6slx25": ("csg324-2",
+ ["V3", "R15", "T13", "R13", "T14", "V14"],
+ "LVCMOS33", Spartan6),
+ "xc6slx25t": ("csg324-2",
+ ["V3", "R15", "T13", "R13", "T14", "V14"],
+ "LVCMOS33", Spartan6),
+ "xc6slx45": ("csg324-2",
+ ["V3", "R15", "T13", "R13", "T14", "V14"],
+ "LVCMOS33", Spartan6),
+ "xc6slx45t": ("csg324-2",
+ ["V3", "R15", "T13", "R13", "T14", "V14"],
+ "LVCMOS33", Spartan6),
+ "xc6slx4": ("cpg196-2",
+ ["P2", "N13", "P11", "N11", "N10", "P10"],
+ "LVCMOS33", Spartan6),
+ "xc6slx4t": ("qg144-2",
+ ["P38", "P70", "P64", "P65", "P62", "P61"],
+ "LVCMOS33", Spartan6),
+ "xc6slx75": ("csg484-2",
+ ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
+ "LVCMOS33", Spartan6),
+ "xc6slx75t": ("csg484-2",
+ ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
+ "LVCMOS33", Spartan6),
+ "xc6slx9": ("cpg196-2",
+ ["P2", "N13", "P11", "N11", "N10", "P10"],
+ "LVCMOS33", Spartan6),
+ "xc6slx9t": ("qg144-2",
+ ["P38", "P70", "P64", "P65", "P62", "P61"],
+ "LVCMOS33", Spartan6),
+
+ "xc7a100t": ("csg324-1",
+ ["L13", None, "K17", "K18", "L14", "M14"],
+ "LVCMOS25", Series7),
+ "xc7a15t": ("cpg236-1",
+ ["K19", None, "D18", "D19", "G18", "F18"],
+ "LVCMOS25", Series7),
+ "xc7a200t": ("fbg484-1",
+ ["T19", None, "P22", "R22", "P21", "R21"],
+ "LVCMOS25", Series7),
+ "xc7a35t": ("cpg236-1",
+ ["K19", None, "D18", "D19", "G18", "F18"],
+ "LVCMOS25", Series7),
+ "xc7a50t": ("cpg236-1",
+ ["K19", None, "D18", "D19", "G18", "F18"],
+ "LVCMOS25", Series7),
+ "xc7a75t": ("csg324-1",
+ ["L13", None, "K17", "K18", "L14", "M14"],
+ "LVCMOS25", Series7),
+ "xc7k160t": ("fbg484-1",
+ ["L16", None, "H18", "H19", "G18", "F19"],
+ "LVCMOS25", Series7),
+ "xc7k325t": ("fbg676-1",
+ ["C23", None, "B24", "A25", "B22", "A22"],
+ "LVCMOS25", Series7),
+ "xc7k355t": ("ffg901-1",
+ ["V26", None, "R30", "T30", "R28", "T28"],
+ "LVCMOS25", Series7),
+ "xc7k410t": ("fbg676-1",
+ ["C23", None, "B24", "A25", "B22", "A22"],
+ "LVCMOS25", Series7),
+ "xc7k420t": ("ffg1156-1",
+ ["V30", None, "AA33", "AA34", "Y33", "Y34"],
+ "LVCMOS25", Series7),
+ "xc7k480t": ("ffg1156-1",
+ ["V30", None, "AA33", "AA34", "Y33", "Y34"],
+ "LVCMOS25", Series7),
+ "xc7k70t": ("fbg484-1",
+ ["L16", None, "H18", "H19", "G18", "F19"],
+ "LVCMOS25", Series7),
+ "xc7v2000t": ("fhg1761-1",
+ ["AL36", None, "AM36", "AN36", "AJ36", "AJ37"],
+ "LVCMOS18", Series7),
+ "xc7v585t": ("ffg1157-1",
+ ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
+ "LVCMOS18", Series7),
+ "xc7vh580t": ("flg1155-1",
+ ["AL28", None, "AE28", "AF28", "AJ29", "AJ30"],
+ "LVCMOS18", Series7),
+ "xc7vh870t": ("flg1932-1",
+ ["V32", None, "T33", "R33", "U31", "T31"],
+ "LVCMOS18", Series7),
+ "xc7vx1140t": ("flg1926-1",
+ ["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
+ "LVCMOS18", Series7),
+ "xc7vx330t": ("ffg1157-1",
+ ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
+ "LVCMOS18", Series7),
+ "xc7vx415t": ("ffg1157-1",
+ ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
+ "LVCMOS18", Series7),
+ "xc7vx485t": ("ffg1157-1",
+ ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
+ "LVCMOS18", Series7),
+ "xc7vx550t": ("ffg1158-1",
+ ["C24", None, "A23", "A24", "B26", "A26"],
+ "LVCMOS18", Series7),
+ "xc7vx690t": ("ffg1157-1",
+ ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
+ "LVCMOS18", Series7),
+ "xc7vx980t": ("ffg1926-1",
+ ["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
+ "LVCMOS18", Series7),
+ }
+
+ def __init__(self, device, pins, std):
+ cs_n, clk, mosi, miso = pins[:4]
+ io = ["spiflash", 0,
+ Subsignal("cs_n", Pins(cs_n)),
+ Subsignal("mosi", Pins(mosi)),
+ Subsignal("miso", Pins(miso), Misc("PULLUP")),
+ IOStandard(std),
+ ]
+ if clk:
+ io.append(Subsignal("clk", Pins(clk)))
+ for i, p in enumerate(pins[4:]):
+ io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP")))
+
+ XilinxPlatform.__init__(self, device, [io])
+ if isinstance(self.toolchain, XilinxVivadoToolchain):
+ self.toolchain.bitstream_commands.append(
+ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]"
+ )
+ elif isinstance(self.toolchain, XilinxISEToolchain):
+ self.toolchain.bitgen_opt += " -g compress"
+
+ @classmethod
+ def make(cls, device, errors=False):
+ pkg, pins, std, Top = cls.pinouts[device]
+ platform = cls("{}-{}".format(device, pkg), pins, std)
+ top = Top(platform)
+ name = "bscan_spi_{}".format(device)
+ dir = "build_{}".format(device)
+ try:
+ platform.build(top, build_name=name, build_dir=dir)
+ except Exception as e:
+ print("ERROR: build failed for {}: {}".format(device, e))
+ if errors:
+ raise
+
+
+if __name__ == "__main__":
+ import argparse
+ import multiprocessing
+ p = argparse.ArgumentParser(description="build bscan_spi bitstreams "
+ "for openocd jtagspi flash driver")
+ p.add_argument("device", nargs="*",
+ default=sorted(list(XilinxBscanSpi.pinouts)),
+ help="build for these devices (default: %(default)s)")
+ p.add_argument("-p", "--parallel", default=1, type=int,
+ help="number of parallel builds (default: %(default)s)")
+ args = p.parse_args()
+ pool = multiprocessing.Pool(args.parallel)
+ pool.map(XilinxBscanSpi.make, args.device, chunksize=1)
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/k1921vk01t.S
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/k1921vk01t.S b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/k1921vk01t.S
new file mode 100755
index 0000000..b8f0b53
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/k1921vk01t.S
@@ -0,0 +1,112 @@
+/***************************************************************************
+ * Copyright (C) 2015 by Bogdan Kolbov *
+ * kolbov@niiet.ru *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc. *
+ ***************************************************************************/
+
+ .text
+ .syntax unified
+ .cpu cortex-m4
+ .thumb
+ .thumb_func
+
+/* K1921VK01T has 128-bitwidth flash, so it`s able to load 4x32-bit words at the time.
+ * And only after all words loaded we can start write
+ */
+
+/* Registers addresses */
+#define FLASH_FMA 0x00 /* Address reg */
+#define FLASH_FMD1 0x04 /* Data1 reg */
+#define FLASH_FMC 0x08 /* Command reg */
+#define FLASH_FCIS 0x0C /* Operation Status reg */
+#define FLASH_FCIC 0x14 /* Operation Status Clear reg */
+#define FLASH_FMD2 0x50 /* Data2 reg */
+#define FLASH_FMD3 0x54 /* Data3 reg */
+#define FLASH_FMD4 0x58 /* Data4 reg*/
+
+ /* Params:
+ * r0 - write cmd (in), status (out)
+ * r1 - count
+ * r2 - workarea start
+ * r3 - workarea end
+ * r4 - target address
+ * Clobbered:
+ * r5 - rp
+ * r6 - wp, tmp
+ * r7 - flash base
+ */
+
+ldr r7, =#0xA001C000 /* Flash reg base*/
+
+wait_fifo:
+ ldr r6, [r2, #0] /* read wp */
+ cmp r6, #0 /* abort if wp == 0 */
+ beq exit
+ ldr r5, [r2, #4] /* read rp */
+ cmp r5, r6 /* wait until rp != wp */
+ beq wait_fifo
+
+
+load_data:
+ ldr r6, [r5] /* read data1 */
+ str r6, [r7, #FLASH_FMD1]
+ adds r5, #4
+
+ ldr r6, [r5] /* read data2 */
+ str r6, [r7, #FLASH_FMD2]
+ adds r5, #4
+
+ ldr r6, [r5] /* read data3 */
+ str r6, [r7, #FLASH_FMD3]
+ adds r5, #4
+
+ ldr r6, [r5] /* read data4 */
+ str r6, [r7, #FLASH_FMD4]
+ adds r5, #4
+
+start_write:
+ str r4, [r7, #FLASH_FMA] /* set addr */
+ adds r4, #16
+ str r0, [r7, #FLASH_FMC] /* write cmd */
+
+busy:
+ ldr r6, [r7, #FLASH_FCIS] /* wait until flag set */
+ cmp r6, #0x0
+ beq busy
+
+ cmp r6, #2 /* check the error bit */
+ beq error
+
+ movs r6, #1 /* clear flags */
+ str r6, [r7, #FLASH_FCIC]
+
+ cmp r5, r3 /* wrap rp at end of buffer */
+ bcc no_wrap
+ mov r5, r2
+ adds r5, #8
+no_wrap:
+ str r5, [r2, #4] /* store rp */
+ subs r1, r1, #1 /* decrement 16-byte block count */
+ cmp r1, #0
+ beq exit /* loop if not done */
+ b wait_fifo
+
+error:
+ movs r0, #0
+ str r0, [r2, #4] /* set rp = 0 on error */
+exit:
+ mov r0, r6 /* return status in r0 */
+ bkpt #0
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.inc
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.inc b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.inc
new file mode 100755
index 0000000..9bb0fa8
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.inc
@@ -0,0 +1,15 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x16,0x68,0x00,0x2e,0xfe,0xd0,0x55,0x68,0xb5,0x42,0xf9,0xd0,0x2f,0x4e,0x30,0x27,
+0x37,0x70,0x2f,0x4e,0x00,0x27,0x37,0x70,0x2e,0x4e,0x06,0x27,0x37,0x70,0x07,0x0c,
+0x2d,0x4e,0x37,0x70,0x2a,0x4e,0x01,0x27,0x37,0x70,0xc7,0xb2,0x2a,0x4e,0x37,0x70,
+0x07,0x0a,0x28,0x4e,0x37,0x70,0x26,0x4e,0x02,0x27,0x37,0x70,0x6f,0x78,0x25,0x4e,
+0x37,0x70,0x2f,0x78,0x24,0x4e,0x37,0x70,0x21,0x4e,0x03,0x27,0x37,0x70,0xef,0x78,
+0x20,0x4e,0x37,0x70,0xaf,0x78,0x20,0x4e,0x37,0x70,0x01,0x39,0x04,0x30,0x04,0x35,
+0x9d,0x42,0x01,0xd3,0x15,0x1c,0x08,0x35,0x00,0x29,0x1b,0xd0,0x16,0x68,0xae,0x42,
+0x18,0xd0,0x17,0x4e,0x04,0x27,0x37,0x70,0x6f,0x78,0x16,0x4e,0x37,0x70,0x2f,0x78,
+0x15,0x4e,0x37,0x70,0x12,0x4e,0x05,0x27,0x37,0x70,0xef,0x78,0x11,0x4e,0x37,0x70,
+0xaf,0x78,0x11,0x4e,0x37,0x70,0x01,0x39,0x04,0x30,0x04,0x35,0x9d,0x42,0x01,0xd3,
+0x15,0x1c,0x08,0x35,0x09,0x4e,0x80,0x27,0x37,0x70,0x08,0x4e,0x36,0x78,0x3e,0x42,
+0xfb,0xd0,0x30,0x27,0x3e,0x42,0x04,0xd1,0x00,0x26,0x55,0x60,0x00,0x29,0x02,0xd0,
+0x9e,0xe7,0x00,0x20,0x50,0x60,0x30,0x1c,0x00,0xbe,0xc0,0x46,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s
new file mode 100755
index 0000000..1fa7613
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s
@@ -0,0 +1,184 @@
+/***************************************************************************
+ * Copyright (C) 2015 by Ivan Meleca *
+ * ivan@artekit.eu *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ ***************************************************************************/
+
+ /* Params:
+ * r0 = flash destination address, status
+ * r1 = longword count
+ * r2 = workarea start address
+ * r3 = workarea end address
+ */
+
+ .text
+ .cpu cortex-m0plus
+ .code 16
+ .thumb_func
+
+ .align 2
+
+ /* r5 = rp
+ * r6 = wp, tmp
+ * r7 = tmp
+ */
+
+wait_fifo:
+ ldr r6, [r2, #0] /* read wp */
+ cmp r6, #0 /* abort if wp == 0 */
+ beq exit
+ ldr r5, [r2, #4] /* read rp */
+ cmp r5, r6 /* wait until rp != wp */
+ beq wait_fifo
+
+ ldr r6, fstat /* Clear error flags */
+ mov r7, #48
+ strb r7, [r6]
+
+ ldr r6, fccobix /* FCCOBIX = 0 */
+ mov r7, #0
+ strb r7, [r6]
+
+ ldr r6, fccobhi /* Program FLASH command */
+ mov r7, #6 /* FCCOBHI = 6 */
+ strb r7, [r6]
+
+ lsr r7, r0, #16 /* FCCOBLO = flash destination address >> 16 */
+ ldr r6, fccoblo
+ strb r7, [r6]
+
+ ldr r6, fccobix /* Index for lower byte address bits[15:0] */
+ mov r7, #1
+ strb r7, [r6] /* FCCOBIX = 1*/
+
+ uxtb r7, r0 /* Memory address bits[15:0] */
+ ldr r6, fccoblo
+ strb r7, [r6] /* FCCOBLO = flash destination address */
+
+ lsr r7, r0, #8
+ ldr r6, fccobhi
+ strb r7, [r6] /* FCCOBHI = flash destination address >> 8 */
+
+ ldr r6, fccobix /* FCCOBIX = 2 */
+ mov r7, #2
+ strb r7, [r6]
+
+ ldrb r7, [r5, #1] /* FCCOBHI = rp >> 8 */
+ ldr r6, fccobhi
+ strb r7, [r6]
+
+ ldrb r7, [r5] /* FCCOBLO = rp */
+ ldr r6, fccoblo
+ strb r7, [r6]
+
+ ldr r6, fccobix /* FCCOBIX = 3 */
+ mov r7, #3
+ strb r7, [r6]
+
+ ldrb r7, [r5, #3] /* FCCOBHI = rp >> 24 */
+ ldr r6, fccobhi
+ strb r7, [r6]
+
+ ldrb r7, [r5, #2] /* FCCOBLO = rp >> 16 */
+ ldr r6, fccoblo
+ strb r7, [r6]
+
+ sub r1, r1, #1 /* Two words (4 bytes) queued, decrement counter */
+ add r0, r0, #4 /* flash address += 4 */
+ add r5, r5, #4 /* rp += 4 */
+
+ cmp r5, r3 /* Wrap? */
+ bcc no_wrap
+ mov r5, r2
+ add r5, r5, #8
+
+no_wrap:
+ cmp r1, #0 /* Done? */
+ beq execute
+
+ ldr r6, [r2, #0] /* read wp */
+ cmp r6, r5
+ beq execute /* execute if rp == wp */
+
+ ldr r6, fccobix /* FCCOBIX = 4 */
+ mov r7, #4
+ strb r7, [r6]
+
+ ldrb r7, [r5, #1] /* FCCOBHI = rp >> 8 */
+ ldr r6, fccobhi
+ strb r7, [r6]
+
+ ldrb r7, [r5] /* FCCOBLO = rp */
+ ldr r6, fccoblo
+ strb r7, [r6]
+
+ ldr r6, fccobix /* FCCOBIX = 5 */
+ mov r7, #5
+ strb r7, [r6]
+
+ ldrb r7, [r5, #3] /* FCCOBHI = rp >> 24 */
+ ldr r6, fccobhi
+ strb r7, [r6]
+
+ ldrb r7, [r5, #2] /* FCCOBLO = rp >> 16 */
+ ldr r6, fccoblo
+ strb r7, [r6]
+
+ sub r1, r1, #1 /* Two words (4 bytes) queued, decrement counter */
+ add r0, r0, #4 /* flash address += 4 */
+ add r5, r5, #4 /* rp += 4 */
+
+ cmp r5, r3 /* Wrap? */
+ bcc execute
+ mov r5, r2
+ add r5, r5, #8
+
+execute:
+ ldr r6, fstat /* Launch the command */
+ mov r7, #128
+ strb r7, [r6]
+
+wait_busy:
+ ldr r6, fstat
+ ldrb r6, [r6] /* Wait until finished */
+ tst r6, r7
+ beq wait_busy
+
+ mov r7, #48 /* Check error */
+ tst r6, r7
+ bne error
+
+ mov r6, #0 /* Clear error */
+
+ str r5, [r2, #4] /* Store rp */
+
+ cmp r1, #0 /* Done? */
+ beq done
+ b wait_fifo
+
+error:
+ mov r0, #0
+ str r0, [r2, #4] /* set rp = 0 on error */
+
+done:
+ mov r0, r6 /* Set result code */
+ bkpt #0
+
+ .align 2
+fstat:
+ .word 0
+fccobix:
+ .word 0
+fccobhi:
+ .word 0
+fccoblo:
+ .word 0
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.inc
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.inc b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.inc
new file mode 100755
index 0000000..44a9d5e
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.inc
@@ -0,0 +1,4 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x07,0x4b,0x7f,0x22,0x1d,0x78,0x5c,0x78,0x2a,0x40,0x06,0x4d,0x98,0x88,0xd9,0x88,
+0x5d,0x80,0x05,0x4d,0x5d,0x80,0x5c,0x70,0x98,0x80,0xd9,0x80,0x1a,0x70,0x00,0xbe,
+0x00,0x20,0x05,0x40,0xc5,0x20,0x00,0x00,0xd9,0x28,0x00,0x00,
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s
new file mode 100755
index 0000000..289662d
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s
@@ -0,0 +1,47 @@
+/***************************************************************************
+ * Copyright (C) 2015 by Ivan Meleca *
+ * ivan@artekit.eu *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ ***************************************************************************/
+
+ .text
+ .cpu cortex-m0plus
+ .code 16
+ .thumb_func
+
+ .align 2
+
+ ldr r3, wdog_cs1
+ mov r2, #127
+ ldrb r5, [r3]
+ ldrb r4, [r3, #1]
+ and r2, r5
+ ldr r5, unlock1
+ ldrh r0, [r3, #4]
+ ldrh r1, [r3, #6]
+ strh r5, [r3, #2]
+ ldr r5, unlock2
+ strh r5, [r3, #2]
+ strb r4, [r3, #1]
+ strh r0, [r3, #4]
+ strh r1, [r3, #6]
+ strb r2, [r3]
+ bkpt #0
+
+ .align 2
+
+wdog_cs1:
+ .word 0x40052000 // Watchdog Control and Status Register 1
+unlock1:
+ .word 0x20C5 // 1st unlock word
+unlock2:
+ .word 0x28D9 // 2nd unlock word
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/lpcspifi_erase.S
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/lpcspifi_erase.S b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/lpcspifi_erase.S
new file mode 100755
index 0000000..350aa93
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/lpcspifi_erase.S
@@ -0,0 +1,176 @@
+/***************************************************************************
+ * Copyright (C) 2012 by George Harris *
+ * george@luminairecoffee.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .syntax unified
+ .cpu cortex-m3
+ .thumb
+ .thumb_func
+
+/*
+ * Params :
+ * r0 = start address, status (out)
+ * r1 = count
+ * r2 = erase command
+ * r3 = block size
+ */
+
+#define SSP_BASE_HIGH 0x4008
+#define SSP_BASE_LOW 0x3000
+#define SSP_CR0_OFFSET 0x00
+#define SSP_CR1_OFFSET 0x04
+#define SSP_DATA_OFFSET 0x08
+#define SSP_CPSR_OFFSET 0x10
+#define SSP_SR_OFFSET 0x0c
+
+#define SSP_CLOCK_BASE_HIGH 0x4005
+#define SSP_CLOCK_BASE_LOW 0x0000
+#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
+#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
+#define SSP_BASE_CLOCK_OFFSET 0x94
+#define SSP_BRANCH_CLOCK_OFFSET 0x700
+
+#define IOCONFIG_BASE_HIGH 0x4008
+#define IOCONFIG_BASE_LOW 0x6000
+#define IOCONFIG_SCK_OFFSET 0x18c
+#define IOCONFIG_HOLD_OFFSET 0x190
+#define IOCONFIG_WP_OFFSET 0x194
+#define IOCONFIG_MISO_OFFSET 0x198
+#define IOCONFIG_MOSI_OFFSET 0x19c
+#define IOCONFIG_CS_OFFSET 0x1a0
+
+#define IO_BASE_HIGH 0x400f
+#define IO_BASE_LOW 0x4000
+#define IO_CS_OFFSET 0xab
+#define IODIR_BASE_HIGH 0x400f
+#define IODIR_BASE_LOW 0x6000
+#define IO_CS_DIR_OFFSET 0x14
+
+
+setup: /* Initialize SSP pins and module */
+ mov.w r10, #IOCONFIG_BASE_LOW
+ movt r10, #IOCONFIG_BASE_HIGH
+ mov.w r8, #0xea
+ str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
+ mov.w r8, #0x40
+ str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
+ mov.w r8, #0x40
+ str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
+ mov.w r8, #0xed
+ str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
+ mov.w r8, #0xed
+ str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
+ mov.w r8, #0x44
+ str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
+
+ mov.w r10, #IODIR_BASE_LOW
+ movt r10, #IODIR_BASE_HIGH
+ mov.w r8, #0x800
+ str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
+ mov.w r10, #IO_BASE_LOW
+ movt r10, #IO_BASE_HIGH
+ mov.w r8, #0xff
+ str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
+
+ mov.w r10, #SSP_CLOCK_BASE_LOW
+ movt r10, #SSP_CLOCK_BASE_HIGH
+ mov.w r8, #0x0000
+ movt r8, #0x0100
+ str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
+
+ mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
+ movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
+ mov.w r8, #0x01
+ str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
+
+ mov.w r10, #SSP_BASE_LOW
+ movt r10, #SSP_BASE_HIGH
+ mov.w r8, #0x07
+ str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
+ mov.w r8, #0x02
+ str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
+ str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
+write_enable:
+ bl cs_down
+ mov.w r9, #0x06 /* Send the write enable command */
+ bl write_data
+ bl cs_up
+
+ bl cs_down
+ mov.w r9, #0x05 /* Get status register */
+ bl write_data
+ mov.w r9, #0x00 /* Dummy data to clock in status */
+ bl write_data
+ bl cs_up
+
+ tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
+ beq error
+erase:
+ bl cs_down
+ mov.w r9, r2 /* Send the erase command */
+ bl write_data
+write_address:
+ lsr r9, r0, #16 /* Send the current 24-bit write address, MSB first */
+ bl write_data
+ lsr r9, r0, #8
+ bl write_data
+ mov.w r9, r0
+ bl write_data
+ bl cs_up
+wait_flash_busy: /* Wait for the flash to finish the previous erase */
+ bl cs_down
+ mov.w r9, #0x05 /* Get status register */
+ bl write_data
+ mov.w r9, #0x00 /* Dummy data to clock in status */
+ bl write_data
+ bl cs_up
+ tst r9, #0x01 /* If it isn't done, keep waiting */
+ bne wait_flash_busy
+
+ subs r1, r1, #1 /* decrement count */
+ cbz r1, exit /* Exit if we have written everything */
+ add r0, r3 /* Move the address up by the block size */
+ b write_enable /* Start a new block erase */
+write_data: /* Send/receive 1 byte of data over SSP */
+ mov.w r10, #SSP_BASE_LOW
+ movt r10, #SSP_BASE_HIGH
+ str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
+wait_transmit:
+ ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
+ tst r9, #0x0010 /* Check if BSY bit is set */
+ bne wait_transmit /* If still transmitting, keep waiting */
+ ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
+ bx lr /* Exit subroutine */
+cs_up:
+ mov.w r8, #0xff
+ b cs_write
+cs_down:
+ mov.w r8, #0x0000
+cs_write:
+ mov.w r10, #IO_BASE_LOW
+ movt r10, #IO_BASE_HIGH
+ str.w r8, [r10, #IO_CS_OFFSET]
+ bx lr
+error:
+ movs r0, #0
+exit:
+ bkpt #0x00
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/lpcspifi_init.S
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/lpcspifi_init.S b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/lpcspifi_init.S
new file mode 100755
index 0000000..9872892
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/lpcspifi_init.S
@@ -0,0 +1,102 @@
+/***************************************************************************
+ * Copyright (C) 2012 by George Harris *
+ * george@luminairecoffee.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+/***************************************************************************
+* This is an algorithm for the LPC43xx family (and probably the LPC18xx *
+* family as well, though they have not been tested) that will initialize *
+* memory-mapped SPI flash accesses. Unfortunately NXP has published *
+* neither the ROM source code that performs this initialization nor the *
+* register descriptions necessary to do so, so this code is necessary to *
+* call into the ROM SPIFI API. *
+***************************************************************************/
+
+ .text
+ .syntax unified
+ .arch armv7-m
+ .thumb
+ .thumb_func
+
+ .align 2
+
+/*
+ * Params :
+ * r0 = spifi clock speed
+ */
+
+#define IOCONFIG_BASE_HIGH 0x4008
+#define IOCONFIG_BASE_LOW 0x6000
+#define IOCONFIG_SCK_OFFSET 0x18c
+#define IOCONFIG_HOLD_OFFSET 0x190
+#define IOCONFIG_WP_OFFSET 0x194
+#define IOCONFIG_MISO_OFFSET 0x198
+#define IOCONFIG_MOSI_OFFSET 0x19c
+#define IOCONFIG_CS_OFFSET 0x1a0
+
+#define SPIFI_ROM_TABLE_BASE_HIGH 0x1040
+#define SPIFI_ROM_TABLE_BASE_LOW 0x0118
+
+code:
+ mov.w r8, r0
+ sub sp, #0x84
+ add r7, sp, #0x0
+ /* Initialize SPIFI pins */
+ mov.w r3, #IOCONFIG_BASE_LOW
+ movt r3, #IOCONFIG_BASE_HIGH
+ mov.w r2, #0xf3
+ str.w r2, [r3, #IOCONFIG_SCK_OFFSET]
+ mov.w r3, #IOCONFIG_BASE_LOW
+ movt r3, #IOCONFIG_BASE_HIGH
+ mov.w r2, #IOCONFIG_BASE_LOW
+ movt r2, #IOCONFIG_BASE_HIGH
+ mov.w r1, #IOCONFIG_BASE_LOW
+ movt r1, #IOCONFIG_BASE_HIGH
+ mov.w r0, #IOCONFIG_BASE_LOW
+ movt r0, #IOCONFIG_BASE_HIGH
+ mov.w r4, #0xd3
+ str.w r4, [r0, #IOCONFIG_MOSI_OFFSET]
+ mov r0, r4
+ str.w r0, [r1, #IOCONFIG_MISO_OFFSET]
+ mov r1, r0
+ str.w r1, [r2, #IOCONFIG_WP_OFFSET]
+ str.w r1, [r3, #IOCONFIG_HOLD_OFFSET]
+ mov.w r3, #IOCONFIG_BASE_LOW
+ movt r3, #IOCONFIG_BASE_HIGH
+ mov.w r2, #0x13
+ str.w r2, [r3, #IOCONFIG_CS_OFFSET]
+
+ /* Perform SPIFI init. See spifi_rom_api.h (in NXP lpc43xx driver package) for details */
+ /* on initialization arguments. */
+ movw r3, #SPIFI_ROM_TABLE_BASE_LOW /* The ROM API table is located @ 0x10400118, and */
+ movt r3, #SPIFI_ROM_TABLE_BASE_HIGH /* the first pointer in the struct is to the init function. */
+ ldr r3, [r3, #0x0]
+ ldr r4, [r3, #0x0] /* Grab the init function pointer from the table */
+ /* Set up function arguments */
+ movw r0, #0x3b4
+ movt r0, #0x1000 /* Pointer to a SPIFI data struct that we don't care about */
+ mov.w r1, #0x3 /* "csHigh". Not 100% sure what this does. */
+ mov.w r2, #0xc0 /* The configuration word: S_RCVCLOCK | S_FULLCLK */
+ mov.w r3, r8 /* SPIFI clock speed (12MHz) */
+ blx r4 /* Call the init function */
+ b done
+
+done:
+ bkpt #0
+
+ .end