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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/07/13 06:52:48 UTC
[GitHub] [incubator-nuttx] qinwei2004 opened a new pull request, #6478: arch: arm64: ARMv8-A support for NuttX
qinwei2004 opened a new pull request, #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478
## Summary:
Arm64 support for NuttX, Features supported:
1. Cotex-a53 single core and SMP support: it's can run into nsh shell at
qemu virt machine.
2. qemu-a53 board configuration support: it's only for evaluate propose
3. FPU support for armv8-a: FPU context switching at NEON/floating-point
TRAP is supported.
4. psci interface, armv8 cache operation(data cache) and smccc support.
Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail
Signed-off-by: qinwei1 <qi...@xiaomi.com>
## Impact
No impact to the other platform
## Testing
testing with ostest, smp.
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[GitHub] [incubator-nuttx] pkarashchenko commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1184351344
Please squash into a single commit
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902289974
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm);
+
+ __asm__ __volatile__
+ (
+ "hlt %1"
+ : "=r"(reg0)
+ : "i"(SYS_smhcall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* Result from SMC/HVC call
+ * a0-a7 result values from registers 0 to 7
+ */
+
+struct arm64_smccc_res
+{
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+};
+
+typedef struct arm64_smccc_res arm64_smccc_res_t;
+
+enum arm64_smccc_conduit
+{
+ SMCCC_CONDUIT_NONE,
+ SMCCC_CONDUIT_SMC,
+ SMCCC_CONDUIT_HVC,
+};
+
+/* Make HVC calls
+ *
+ * param a0 function identifier
+ * param a1-a7 parameters registers
+ * param res results
+ */
+
+void arm64_smccc_hvc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm64_smccc_res *res);
Review Comment:
```suggestion
void arm64_smccc_hvc(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3,
unsigned long a4, unsigned long a5,
unsigned long a6, unsigned long a7,
struct arm64_smccc_res *res);
```
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm);
+
+ __asm__ __volatile__
+ (
+ "hlt %1"
+ : "=r"(reg0)
+ : "i"(SYS_smhcall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* Result from SMC/HVC call
+ * a0-a7 result values from registers 0 to 7
+ */
+
+struct arm64_smccc_res
+{
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+};
+
+typedef struct arm64_smccc_res arm64_smccc_res_t;
+
+enum arm64_smccc_conduit
+{
+ SMCCC_CONDUIT_NONE,
+ SMCCC_CONDUIT_SMC,
+ SMCCC_CONDUIT_HVC,
+};
+
+/* Make HVC calls
+ *
+ * param a0 function identifier
+ * param a1-a7 parameters registers
+ * param res results
+ */
+
+void arm64_smccc_hvc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm64_smccc_res *res);
+
+/* Make SMC calls
+ *
+ * param a0 function identifier
+ * param a1-a7 parameters registers
+ * param res results
+ */
+
+void arm64_smccc_smc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm64_smccc_res *res);
Review Comment:
```suggestion
void arm64_smccc_smc(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3,
unsigned long a4, unsigned long a5,
unsigned long a6, unsigned long a7,
struct arm64_smccc_res *res);
```
##########
arch/arm64/src/common/arm64_copystate.c:
##########
@@ -0,0 +1,120 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_copystate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <sched.h>
+#include <debug.h>
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <arch/syscall.h>
+#include <arch/irq.h>
+
+#include "arm64_internal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+int arch_save_fpucontext(void *saveregs)
+{
+ irqstate_t flags;
+ uint64_t * p_save;
+
+ /* Take a snapshot of the thread context right now */
+
+ flags = enter_critical_section();
+
+ p_save = saveregs + XCPTCONTEXT_GP_SIZE;
+ arm64_fpu_save((struct fpu_reg *)p_save);
+ __DSB();
+
+ leave_critical_section(flags);
+ return 0;
+}
+#endif
+
+int arm64_syscall_save_context(uint64_t * regs)
+{
+ struct regs_context * f_regs;
+ uint64_t * p_save;
+ int i;
+
+#ifdef CONFIG_ARCH_FPU
+ uint64_t * p_fpu;
+ struct tcb_s * rtcb;
+ struct tcb_s * rtcb_cur = (struct tcb_s *)arch_get_current_tcb();
Review Comment:
```suggestion
struct regs_context *f_regs;
uint64_t *p_save;
int i;
#ifdef CONFIG_ARCH_FPU
uint64_t *p_fpu;
struct tcb_s *rtcb;
struct tcb_s *rtcb_cur = (struct tcb_s *)arch_get_current_tcb();
```
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
+
+ /* for statistic propose */
+
+ int save_count;
+ int restore_count;
+ int switch_count;
+ int exe_depth_count;
+};
+
+static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/***************************************************************************
+ * Public Functions
+ ***************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb)
+{
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ memset(&g_cpu_fpu_ctx[this_cpu()], 0,
+ sizeof(struct arm64_cpu_fpu_context));
+ g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb;
+
+ tcb->xcp.fpu_regs = &g_idle_thread_fpu[this_cpu()];
+ }
+
+ memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg));
+ tcb->xcp.fpu_regs->fpu_trap = 0;
+}
+
+void arm64_destory_fpu(struct tcb_s * tcb)
+{
+ struct tcb_s * owner;
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner == tcb)
+ {
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+}
+
+/* enable FPU access trap */
+
+static void arm64_fpu_access_trap_enable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+ cpacr &= ~CPACR_EL1_FPEN_NOTRAP;
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/* disable FPU access trap */
+
+static void arm64_fpu_access_trap_disable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+
+ cpacr |= CPACR_EL1_FPEN_NOTRAP;
+
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/***************************************************************************
+ * Name: arm64_fpu_enter_exception
+ *
+ * Description:
+ * called at every time get into a exception
+ *
+ ***************************************************************************/
+
+void arm64_fpu_enter_exception(void)
+{
+}
+
+void arm64_fpu_exit_exception(void)
+{
+}
+
+void arm64_fpu_trap(struct esf_reg * regs)
+{
+ struct tcb_s * owner;
+
+ /* disable fpu trap access */
+
+ arm64_fpu_access_trap_disable();
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner != NULL)
+ {
+ arm64_fpu_save(owner->xcp.fpu_regs);
+ __DSB();
+ g_cpu_fpu_ctx[this_cpu()].save_count++;
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+
+ if (arch_get_exception_depth() > 1)
+ {
+ /* if get_exception_depth > 1
+ * it means FPU access exception occurred in exception context
+ * switch FPU owner to idle thread
+ */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].idle_thread;
+ }
+ else
+ {
+ owner = (struct tcb_s *)arch_get_current_tcb();
+ }
+
+ /* restore our content */
+
+ arm64_fpu_restore(owner->xcp.fpu_regs);
+ g_cpu_fpu_ctx[this_cpu()].restore_count++;
+
+ /* become new owner */
+
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = owner;
+ owner->xcp.fpu_regs->fpu_trap = 1;
+}
+
+void arm64_fpu_context_restore(void)
+{
+ struct tcb_s *new_tcb = (struct tcb_s *)arch_get_current_tcb();
+
+ arm64_fpu_access_trap_enable();
+
+ if (new_tcb->xcp.fpu_regs->fpu_trap == 0)
+ {
+ /* FPU trap hasn't happened at this task */
+
+ arm64_fpu_access_trap_enable();
+ }
+ else
+ {
+ /* FPU trap has happened at this task */
+
+ if (new_tcb == g_cpu_fpu_ctx[this_cpu()].fpu_owner)
+ {
+ arm64_fpu_access_trap_disable();
+ }
+ else
+ {
+ arm64_fpu_access_trap_enable();
+ }
+ }
+
+ g_cpu_fpu_ctx[this_cpu()].switch_count++;
+}
+
+void arm64_fpu_enable(void)
+{
+ irqstate_t flags = up_irq_save();
+
+ arm64_fpu_access_trap_enable();
+ up_irq_restore(flags);
+}
+
+void arm64_fpu_disable(void)
+{
+ irqstate_t flags = up_irq_save();
+
+ arm64_fpu_access_trap_disable();
+ up_irq_restore(flags);
+}
+
+/***************************************************************************
+ * Name: up_fpucmp
+ *
+ * Description:
+ * compare FPU areas from thread context
+ *
+ ***************************************************************************/
+
+bool up_fpucmp(const void *saveregs1, const void *saveregs2)
+{
+ const uint64_t *regs1 = saveregs1 + XCPTCONTEXT_GP_SIZE;
+ const uint64_t *regs2 = saveregs2 + XCPTCONTEXT_GP_SIZE;
Review Comment:
```suggestion
const uint64_t *regs1 = saveregs1 + XCPTCONTEXT_GP_SIZE;
const uint64_t *regs2 = saveregs2 + XCPTCONTEXT_GP_SIZE;
```
##########
arch/arm64/src/common/arm64_fpu.h:
##########
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb);
+void arm64_destory_fpu(struct tcb_s * tcb);
+
+void arm64_fpu_disable(void);
+void arm64_fpu_enable(void);
+
+void arm64_fpu_save(struct fpu_reg *saved_fp_context);
+void arm64_fpu_restore(struct fpu_reg *saved_fp_context);
+
+#endif //__ASSEMBLY__
+
+#endif /* __ARCH_ARM_SRC_ARMV7_A_ARM_H */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H */
```
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H
```
##########
arch/arm64/src/common/arm64_backtrace.c:
##########
@@ -0,0 +1,184 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+
+#include "sched/sched.h"
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_FRAME_POINTER)
+
+/****************************************************************************
+ * Name: backtrace
+ *
+ * Description:
+ * backtrace() parsing the return address through frame pointer
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int backtrace(uintptr_t *base, uintptr_t *limit,
+ uintptr_t *fp, uintptr_t *pc,
+ void **buffer, int size, int *skip)
+{
+ int i = 0;
+
+ if (pc)
+ {
+ i++;
+ if (*skip-- <= 0)
+ {
+ *buffer++ = pc;
+ }
+ }
+
+ for (; i < size; fp = (uintptr_t *)*(fp - 1), i++)
+ {
+ if (fp > limit || fp < base || *fp == 0)
+ {
+ break;
+ }
+
+ if (*skip-- <= 0)
+ {
+ *buffer++ = (void *)*fp;
+ }
+ }
+
+ return i;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_backtrace
+ *
+ * Description:
+ * up_backtrace() returns a backtrace for the TCB, in the array
+ * pointed to by buffer. A backtrace is the series of currently active
+ * function calls for the program. Each item in the array pointed to by
+ * buffer is of type void *, and is the return address from the
+ * corresponding stack frame. The size argument specifies the maximum
+ * number of addresses that can be stored in buffer. If the backtrace is
+ * larger than size, then the addresses corresponding to the size most
+ * recent function calls are returned; to obtain the complete backtrace,
+ * make sure that buffer and size are large enough.
+ *
+ * Input Parameters:
+ * tcb - Address of the task's TCB
+ * buffer - Return address from the corresponding stack frame
+ * size - Maximum number of addresses that can be stored in buffer
+ * skip - number of addresses to be skipped
+ *
+ * Returned Value:
+ * up_backtrace() returns the number of addresses returned in buffer
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+int up_backtrace(struct tcb_s *tcb,
+ void **buffer, int size, int skip)
+{
+ struct tcb_s *rtcb = (struct tcb_s *)arch_get_current_tcb();
+ struct regs_context * p_regs;
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
+ void *istacklimit;
+#endif
+ irqstate_t flags;
+ int ret;
+
+ if (size <= 0 || !buffer)
+ {
+ return 0;
+ }
+
+ if (tcb == NULL || tcb == rtcb)
+ {
+ if (up_interrupt_context())
+ {
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
+# ifdef CONFIG_SMP
+ istacklimit = (void *)arm64_intstack_top();
+# else
+ istacklimit = g_interrupt_stack + INTSTACK_SIZE;
+# endif /* CONFIG_SMP */
+ ret = backtrace(istacklimit - (CONFIG_ARCH_INTERRUPTSTACK & ~15),
+ istacklimit,
+ (void *)__builtin_frame_address(0),
+ NULL, buffer, size, &skip);
+#else
+ ret = backtrace(rtcb->stack_base_ptr,
+ rtcb->stack_base_ptr + rtcb->adj_stack_size,
+ (void *)__builtin_frame_address(0),
+ NULL, buffer, size, &skip);
+#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */
+ if (ret < size)
+ {
+ p_regs = (struct regs_context *)CURRENT_REGS;
+ ret += backtrace(rtcb->stack_base_ptr,
+ rtcb->stack_base_ptr + rtcb->adj_stack_size,
+ (void *)p_regs->regs[REG_X29],
+ (void *)p_regs->elr,
+ &buffer[ret], size - ret, &skip);
+ }
+ }
+ else
+ {
+ ret = backtrace(rtcb->stack_base_ptr,
+ rtcb->stack_base_ptr + rtcb->adj_stack_size,
+ (void *)__builtin_frame_address(0),
+ NULL, buffer, size, &skip);
+ }
+ }
+ else
+ {
+ flags = enter_critical_section();
+ p_regs = (struct regs_context *)CURRENT_REGS;
+
+ ret = backtrace(tcb->stack_base_ptr,
+ tcb->stack_base_ptr + tcb->adj_stack_size,
+ (void *)p_regs->regs[REG_X29],
+ (void *)p_regs->elr,
+ buffer, size, &skip);
+
+ leave_critical_section(flags);
+ }
+
+ return ret;
+}
+#endif /* CONFIG_FRAME_POINTER && !CONFIG_ARM_THUMB */
Review Comment:
comment seems to be wrong
##########
arch/arm64/src/common/arm64_cache.c:
##########
@@ -0,0 +1,449 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cache.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* Common operations for the caches
+ *
+ * WB means write-back and intends to transfer dirty cache lines to memory in
+ * a copy-back cache policy. May be a no-op in write-back cache policy.
+ *
+ * INVD means invalidate and will mark cache lines as not valid. A future
+ * access to the associated address is guaranteed to generate a memory fetch.
+ *
+ * armv8 data cahce instruction:
+ *
+ * DC CIVAC (WB+INVD):
+ * Data or unified Cache line Clean and Invalidate by VA to PoC
+ * Clean and Invalidate data cache by address to Point of Coherency.
+ *
+ * DC CVAC (WB):
+ * Data or unified Cache line Clean by VA to PoC
+ * Clean data cache by address to Point of Coherency.
+ *
+ * DC IVAC (INVD):
+ * Data or unified Cache line Invalidate by VA to PoC
+ * Invalidate data cache by address to Point of Coherency
+ */
+
+#define CACHE_OP_WB BIT(0)
+#define CACHE_OP_INVD BIT(1)
+#define CACHE_OP_WB_INVD (CACHE_OP_WB | CACHE_OP_INVD)
+
+#define LINE_MASK(line) (line - 1)
Review Comment:
```suggestion
#define LINE_MASK(line) ((line) - 1)
```
##########
arch/arm64/src/common/arm64_arch_timer.h:
##########
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H
```
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <arch/syscall.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+#define PSCI_RET_INVALID_ADDRESS -9
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+uint32_t psci_version(void);
+
+typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long,
Review Comment:
is `*` missing here?
##########
arch/arm64/src/common/arm64_arch_timer.h:
##########
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_gic.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CONFIG_ARM_TIMER_SECURE_IRQ (GIC_PPI_INT_BASE + 13)
+#define CONFIG_ARM_TIMER_NON_SECURE_IRQ (GIC_PPI_INT_BASE + 14)
+#define CONFIG_ARM_TIMER_VIRTUAL_IRQ (GIC_PPI_INT_BASE + 11)
+#define CONFIG_ARM_TIMER_HYP_IRQ (GIC_PPI_INT_BASE + 10)
+
+#define ARM_ARCH_TIMER_IRQ CONFIG_ARM_TIMER_VIRTUAL_IRQ
+#define ARM_ARCH_TIMER_PRIO IRQ_DEFAULT_PRIORITY
+#define ARM_ARCH_TIMER_FLAGS IRQ_TYPE_LEVEL
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+extern uint64_t arch_counter_read(void);
+extern void arch_timer_delay(long mini_sec);
+extern void arch_start_timer(void);
+
+#ifdef CONFIG_SMP
+void arm64_smp_timer_init(void);
+#endif
+
+#endif //__ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H */
```
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <arch/syscall.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+#define PSCI_RET_INVALID_ADDRESS -9
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+uint32_t psci_version(void);
+
+typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long,
+ unsigned long);
+
+struct psci_interface
+{
+ enum arm64_smccc_conduit conduit;
+ psci_fn *invoke_psci_fn;
+ uint32_t version;
+};
+
+int pcsi_cpu_off(void);
+int pcsi_cpu_on(unsigned long cpuid, uintptr_t entry_point);
+
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H */
```
##########
arch/arm64/src/common/arm64_fatal.h:
##########
@@ -0,0 +1,77 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__
+
+/**
+ * @defgroup fatal_apis Fatal error APIs
+ * @ingroup kernel_apis
+ * @{
+ */
+
+#define K_ERR_CPU_EXCEPTION (0)
+#define K_ERR_CPU_MODE32 (1)
+#define K_ERR_SPURIOUS_IRQ (2)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_fatal_error
+ *
+ * Description:
+ * fatal error handle for arm64
+ * Input Parameters:
+ * reason: error reason
+ * reg: exception stack reg context
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+void arm64_fatal_error(unsigned int reason, struct regs_context * reg);
+void arm64_dump_fatal(struct regs_context * reg);
+
+#define __builtin_unreachable() \
+ do { \
+ sinfo("Unreachable code\n"); \
+ PANIC(); \
+ } while (true)
+
+#endif //__ASSEMBLY__
+
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H */
```
##########
arch/arm64/src/common/arm64_copystate.c:
##########
@@ -0,0 +1,120 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_copystate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <sched.h>
+#include <debug.h>
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <arch/syscall.h>
+#include <arch/irq.h>
+
+#include "arm64_internal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+int arch_save_fpucontext(void *saveregs)
+{
+ irqstate_t flags;
+ uint64_t * p_save;
Review Comment:
```suggestion
uint64_t *p_save;
```
##########
arch/arm64/src/common/arm64_fpu.h:
##########
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H
```
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
+#define GIC_DIST_IGROUPR 0x0080
+#define GIC_DIST_ISENABLER 0x0100
+#define GIC_DIST_ICENABLER 0x0180
+#define GIC_DIST_ISPENDR 0x0200
+#define GIC_DIST_ICPENDR 0x0280
+#define GIC_DIST_ISACTIVER 0x0300
+#define GIC_DIST_ICACTIVER 0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR 0x0800
+#define GIC_DIST_ICFGR 0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR 0x0f00
+
+/* GICD GICR common access macros */
+
+#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD_PIDR2 : Peripheral ID2 Register
+ * bit assignments
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+#define GICD_PIDR2_ARCH_MASK 0xf0
+#define GICD_PIDR2_ARCH_GICV3 0x30
+#define GICD_PIDR2_ARCH_GICV4 0x40
+
+/* GICD_TYPER : Interrupt Controller Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+#define GICD_TYPER_RSS (1U << 26)
+#define GICD_TYPER_LPIS (1U << 17)
+#define GICD_TYPER_MBIS (1U << 16)
+#define GICD_TYPER_ESPI (1U << 8)
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
+#define GICD_TYPER_ESPIS(typer) \
+ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
+
+/* Common Helper Constants */
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
+ ((intid) < GIC_PPI_INT_BASE))
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_NUM_INTR_PER_REG 32
+#define GIC_NUM_CFG_PER_REG 16
+#define GIC_NUM_PRI_PER_REG 4
+
+/* GIC idle priority : value '0xff' will allow all interrupts */
+
+#define GIC_IDLE_PRIO 0xff
+
+/* Priority levels 0:255 */
+
+#define GIC_PRI_MASK 0xff
+
+/* '0xa0'is used to initialize each interrtupt default priority.
+ * This is an arbitrary value in current context.
+ * Any value '0x80' to '0xff' will work for both NS and S state.
+ * The values of individual interrupt and default has to be chosen
+ * carefully if PMR and BPR based nesting and preemption has to be done.
+ */
+
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
+
+/* Register bit definitions */
+
+/* GICD_CTLR Interrupt group definitions */
+#define GICD_CTLR_ENABLE_G0 0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S 2
+#define GICD_CTRL_ARE_S 4
+#define GICD_CTRL_ARE_NS 5
+#define GICD_CTRL_NS 6
+#define GICD_CGRL_E1NWF 7
+
+/* GICD_CTLR Register write progress bit */
+#define GICD_CTLR_RWP 31
+
+/* GICR_CTLR */
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP 3
+
+/* GICD_TYPER.ITLinesNumber 0:4 */
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICR： Re-Distributor registers, offsets from RD_base(n) */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00A0
+#define GICR_INVALLR 0x00B0
+#define GICR_SYNCR 0x00C0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+#define GICR_IDREGS 0xFFD0
+#define GICR_PIDR2 0xFFE8
+
+/* GICR_PIDR2 : Peripheral ID2 Register
+ * bit assignments are the same as those for GICD_PIDR2)
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+
+#define GICR_PIDR2_ARCH_MASK 0xf0
+#define GICR_PIDR2_ARCH_GICV3 0x30
+#define GICR_PIDR2_ARCH_GICV4 0x40
+
+/* GICR_TYPER : Redistributor Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ * chapter 9.11.35 for detail descriptions
+ */
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_DIRECTLPIS (1U << 3)
+#define GICR_TYPER_LAST (1U << 4)
+
+/* GICR_WAKER */
+#define GICR_WAKER_PS 1
+#define GICR_WAKER_CA 2
+
+/* SGI base is at 64K offset from Redistributor */
+#define GICR_SGI_BASE_OFF 0x10000
+
+/* GICD_ICFGR */
+#define GICD_ICFGR_MASK BIT_MASK(2)
+#define GICD_ICFGR_TYPE BIT(1)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_SPI_MAX_INTID 1019
+#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \
+ ((intid) <= GIC_SPI_MAX_INTID))
+
+/* GITCD_IROUTER */
+#define GIC_DIST_IROUTER 0x6000
+#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define IRQ_DEFAULT_PRIORITY 0xa0
+
+#define GIC_IRQ_SGI0 0
+#define GIC_IRQ_SGI1 1
+#define GIC_IRQ_SGI2 2
+#define GIC_IRQ_SGI3 3
+#define GIC_IRQ_SGI4 4
+#define GIC_IRQ_SGI5 5
+#define GIC_IRQ_SGI6 6
+#define GIC_IRQ_SGI7 7
+#define GIC_IRQ_SGI8 8
+#define GIC_IRQ_SGI9 9
+#define GIC_IRQ_SGI10 10
+#define GIC_IRQ_SGI11 11
+#define GIC_IRQ_SGI12 12
+#define GIC_IRQ_SGI13 13
+#define GIC_IRQ_SGI14 14
+#define GIC_IRQ_SGI15 15
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+bool arm64_gic_irq_is_enabled(unsigned int intid);
+int arm64_gic_initialize(void);
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags);
+
+/****************************************************************************
+ * Name: arm64_decodeirq
+ *
+ * Description:
+ * This function is called from the IRQ vector handler in arm_vectors.S.
+ * At this point, the interrupt has been taken and the registers have
+ * been saved on the stack. This function simply needs to determine the
+ * the irq number of the interrupt and then to call arm_doirq to dispatch
+ * the interrupt.
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area on the stack.
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_decodeirq(uint64_t * regs);
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list);
+
+#ifdef CONFIG_SMP
+
+#define SGI_CPU_PAUSE GIC_IRQ_SGI0
+
+/****************************************************************************
+ * Name: arm64_pause_handler
+ *
+ * Description:
+ * This is the handler for SGI2. It performs the following operations:
+ *
+ * 1. It saves the current task state at the head of the current assigned
+ * task list.
+ * 2. It waits on a spinlock, then
+ * 3. Returns from interrupt, restoring the state of the new task at the
+ * head of the ready to run list.
+ *
+ * Input Parameters:
+ * Standard interrupt handling
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int arm64_pause_handler(int irq, void *context, void *arg);
+
+void arm64_gic_secondary_init(void);
+
+int arm64_smp_sgi_init(void);
+
+#endif
+
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H */
```
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
```
##########
arch/arm64/src/common/arm64_fatal.h:
##########
@@ -0,0 +1,77 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,438 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
Review Comment:
```suggestion
#define ARM64_FPU_REGS (66)
#else
#define ARM64_FPU_REGS (0)
```
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915024647
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
But second parameter should be void * context and return value should be int.
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915056594
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+}
+
+#else
+
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
@hartmannathan FAR is for the legacy 16bit target, we don't need add FAR for arm64.
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915946669
##########
arch/arm64/include/types.h:
##########
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm64/include/types.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_TYPES_H
+#define __ARCH_ARM64_INCLUDE_TYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types. NOTE that these type
+ * names have a leading underscore character. This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character. This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char _int8_t;
+typedef unsigned char _uint8_t;
+
+typedef signed short _int16_t;
+typedef unsigned short _uint16_t;
+
+typedef signed int _int32_t;
+typedef unsigned int _uint32_t;
+
+typedef signed long _int64_t;
+typedef unsigned long _uint64_t;
+#define __INT64_DEFINED
+
+typedef _int64_t _intmax_t;
+typedef _uint64_t _uintmax_t;
+
+#if defined(__WCHAR_TYPE__)
+typedef __WCHAR_TYPE__ _wchar_t;
+#else
+typedef int _wchar_t;
+#endif
+
+#if defined(__SIZE_TYPE__)
+/* If __SIZE_TYPE__ is defined we define ssize_t based on size_t.
+ * We simply change "unsigned" to "signed" for this single definition
+ * to make sure ssize_t and size_t only differ by their signedness.
+ */
+
+#define unsigned signed
+typedef __SIZE_TYPE__ _ssize_t;
+#undef unsigned
+typedef __SIZE_TYPE__ _size_t;
+
+#elif defined(CONFIG_ARCH_SIZET_LONG)
+
+typedef signed long _ssize_t;
+typedef unsigned long _size_t;
+
+#else
+
+typedef signed int _ssize_t;
+typedef unsigned int _size_t;
Review Comment:
I check risc-v 64 bit and x86_64
it's same defined, why we need do this?
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916004637
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
Review Comment:
but for following code, it's used, and arm is samed code:
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1181733247
@xiaoxiang781216 @hartmannathan @pkarashchenko
Please check again
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1163841723
> Accidentally merged some unrelated commits into this PR? Some changes in graphics, drivers, etc., which are good changes, seem unrelated to this PR. Suggest to separate these and submit in other PRs. Not necessary to wait for this PR to be merged, IMO. Thanks!
----Sorry, error submit and fix already, please check again
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1166838087
> @qinwei2004 you can fix only critical items like `assert(1)` and `psci_fn` and other style issues can be fixed in the next PR
Please check again
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r918046448
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,618 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one
+ * complete table */
+#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX 3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+ (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+
+#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT \
+ (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT \
+ (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT \
+ (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+ (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+ (XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+ ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21) - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \
+ ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \
+ ? 0U \
+ : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \
+ ? 1U \
+ : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \
+ ? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \
+ (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
+ CONFIG_ARM64_VA_BITS)
+
+static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
+ NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
+
+static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+
+#if (CONFIG_ARM64_PA_BITS == 48)
+#define TCR_PS_BITS TCR_PS_BITS_256TB
+#elif (CONFIG_ARM64_PA_BITS == 44)
+#define TCR_PS_BITS TCR_PS_BITS_16TB
+#elif (CONFIG_ARM64_PA_BITS == 42)
+#define TCR_PS_BITS TCR_PS_BITS_4TB
+#elif (CONFIG_ARM64_PA_BITS == 40)
+#define TCR_PS_BITS TCR_PS_BITS_1TB
+#elif (CONFIG_ARM64_PA_BITS == 36)
+#define TCR_PS_BITS TCR_PS_BITS_64GB
+#else
+#define TCR_PS_BITS TCR_PS_BITS_4GB
+#endif
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/* NuttX RTOS execution regions with appropriate attributes */
+
+static const struct arm_mmu_region mmu_nxrt_regions[] =
+{
+ /* Mark text segment cacheable,read only and executable */
+
+ MMU_REGION_FLAT_ENTRY("nx_code",
+ (uint64_t)_stext,
+ (uint64_t)_sztext,
+ MT_CODE | MT_SECURE),
+
+ /* Mark rodata segment cacheable, read only and execute-never */
+
+ MMU_REGION_FLAT_ENTRY("nx_rodata",
+ (uint64_t)_srodata,
+ (uint64_t)_szrodata,
+ MT_RODATA | MT_SECURE),
+
+ /* Mark rest of the mirtos execution regions (data, bss, noinit, etc.)
+ * cacheable, read-write
+ * Note: read-write region is marked execute-ever internally
+ */
+
+ MMU_REGION_FLAT_ENTRY("nx_data",
+ (uint64_t)_sdata,
+ (uint64_t)_szdata,
+ MT_NORMAL | MT_RW | MT_SECURE),
+};
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Translation table control register settings */
+
+static uint64_t get_tcr(int el)
+{
+ uint64_t tcr;
+ uint64_t va_bits = CONFIG_ARM64_VA_BITS;
+ uint64_t tcr_ps_bits;
+
+ tcr_ps_bits = TCR_PS_BITS;
+
+ if (el == 1)
+ {
+ tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+
+ /* TCR_EL1.EPD1: Disable translation table walk for addresses
+ * that are translated using TTBR1_EL1.
+ */
+
+ tcr |= TCR_EPD1_DISABLE;
+ }
+ else
+ {
+ tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+ }
+
+ tcr |= TCR_T0SZ(va_bits);
+
+ /* Translation table walk is cacheable, inner/outer WBWA and
+ * inner shareable
+ */
+
+ tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+ return tcr;
+}
+
+static int pte_desc_type(uint64_t *pte)
+{
+ return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static uint64_t *calculate_pte_index(uint64_t addr, int level)
+{
+ int base_level = XLAT_TABLE_BASE_LEVEL;
+ uint64_t *pte;
+ uint64_t idx;
+ unsigned int i;
+
+ /* Walk through all translation tables to find pte index */
+
+ pte = (uint64_t *)base_xlat_table;
+ for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++)
+ {
+ idx = XLAT_TABLE_VA_IDX(addr, i);
+ pte += idx;
+
+ /* Found pte index */
+
+ if (i == level)
+ {
+ return pte;
+ }
+
+ /* if PTE is not table desc, can't traverse */
+
+ if (pte_desc_type(pte) != PTE_TABLE_DESC)
+ {
+ return NULL;
+ }
+
+ /* Move to the next translation table level */
+
+ pte = (uint64_t *)(*pte & 0x0000fffffffff000);
+ }
+
+ return NULL;
+}
+
+static void set_pte_table_desc(uint64_t *pte, uint64_t *table,
+ unsigned int level)
+{
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: [Table] %p\n", pte, table);
+#endif
+
+ /* Point pte to new table */
+
+ *pte = PTE_TABLE_DESC | (uint64_t)table;
+}
+
+static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
+ unsigned int attrs, unsigned int level)
+{
+ uint64_t desc = addr_pa;
+ unsigned int mem_type;
+
+ desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+ /* NS bit for security memory access from secure state */
+
+ desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+ /* AP bits for Data access permission */
+
+ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+ /* the access flag */
+
+ desc |= PTE_BLOCK_DESC_AF;
+
+ /* memory attribute index field */
+
+ mem_type = MT_TYPE(attrs);
+ desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+ switch (mem_type)
+ {
+ case MT_DEVICE_NGNRNE:
+ case MT_DEVICE_NGNRE:
+ case MT_DEVICE_GRE:
+ {
+ /* Access to Device memory and non-cacheable memory are coherent
+ * for all observers in the system and are treated as
+ * Outer shareable, so, for these 2 types of memory,
+ * it is not strictly needed to set shareability field
+ */
+
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+
+ /* Map device memory as execute-never */
+
+ desc |= PTE_BLOCK_DESC_PXN;
+ desc |= PTE_BLOCK_DESC_UXN;
+ break;
+ }
+
+ case MT_NORMAL_NC:
+ case MT_NORMAL:
+ {
+ /* Make Normal RW memory as execute never */
+
+ if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+ {
+ desc |= PTE_BLOCK_DESC_PXN;
+ }
+
+ if (mem_type == MT_NORMAL)
+ {
+ desc |= PTE_BLOCK_DESC_INNER_SHARE;
+ }
+ else
+ {
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+ }
+ }
+ }
+
+#if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE)
+ sinfo("%s ", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: ", pte);
+ sinfo("%s ",
+ (mem_type ==
+ MT_NORMAL) ? "MEM" :((mem_type == MT_NORMAL_NC) ? "NC" : "DEV"));
+ sinfo("%s ", (attrs & MT_RW) ? "-RW" : "-RO");
+ sinfo("%s ", (attrs & MT_NS) ? "-NS" : "-S");
+ sinfo("%s ", (attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC");
+ sinfo("\n");
+#endif
+
+ *pte = desc;
+}
+
+/* Returns a new reallocated table */
+
+static uint64_t *new_prealloc_table(void)
+{
+ static unsigned int table_idx;
+
+ __MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
+ "Enough xlat tables not allocated");
+
+ return (uint64_t *)(xlat_tables[table_idx++]);
+}
+
+/* Splits a block into table with entries spanning the old block */
+
+static void split_pte_block_desc(uint64_t *pte, int level)
+{
+ uint64_t old_block_desc = *pte;
+ uint64_t *new_table;
+ unsigned int i = 0;
+
+ /* get address size shift bits for next level */
+
+ int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1);
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("Splitting existing PTE %p(L%d)\n", pte, level);
+#endif
+
+ new_table = new_prealloc_table();
+
+ for (i = 0; i < XLAT_TABLE_ENTRIES; i++)
+ {
+ new_table[i] = old_block_desc | (i << levelshift);
+
+ if ((level + 1) == 3)
+ {
+ new_table[i] |= PTE_PAGE_DESC;
+ }
+ }
+
+ /* Overwrite existing PTE set the new table into effect */
+
+ set_pte_table_desc(pte, new_table, level);
+}
+
+/* Create/Populate translation table(s) for given region */
+
+static void init_xlat_tables(const struct arm_mmu_region *region)
+{
+ uint64_t *pte;
+ uint64_t virt = region->base_va;
+ uint64_t phys = region->base_pa;
+ uint64_t size = region->size;
+ uint64_t attrs = region->attrs;
+ uint64_t level_size;
+ uint64_t *new_table;
+ unsigned int level = XLAT_TABLE_BASE_LEVEL;
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("mmap: virt %llx phys %llx size %llx\n", virt, phys, size);
+#endif
+
+ /* check minimum alignment requirement for given mmap region */
+
+ __MMU_ASSERT(((virt & (PAGE_SIZE - 1)) == 0) &&
+ ((size & (PAGE_SIZE - 1)) == 0),
+ "address/size are not page aligned\n");
+
+ while (size)
+ {
+ __MMU_ASSERT(level <= XLAT_TABLE_LEVEL_MAX,
+ "max translation table level exceeded\n");
+
+ /* Locate PTE for given virtual address and page table level */
+
+ pte = calculate_pte_index(virt, level);
+ __MMU_ASSERT(pte != NULL, "pte not found\n");
+
+ level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level);
+
+ if (size >= level_size && !(virt & (level_size - 1)))
+ {
+ /* Given range fits into level size,
+ * create block/page descriptor
+ */
+
+ set_pte_block_desc(pte, phys, attrs, level);
+ virt += level_size;
+ phys += level_size;
+ size -= level_size;
+
+ /* Range is mapped, start again for next range */
+
+ level = XLAT_TABLE_BASE_LEVEL;
+ }
+ else if (pte_desc_type(pte) == PTE_INVALID_DESC)
+ {
+ /* Range doesn't fit, create subtable */
+
+ new_table = new_prealloc_table();
+ set_pte_table_desc(pte, new_table, level);
+ level++;
+ }
+ else if (pte_desc_type(pte) == PTE_BLOCK_DESC)
+ {
+ split_pte_block_desc(pte, level);
+ level++;
+ }
+ else if (pte_desc_type(pte) == PTE_TABLE_DESC)
+ {
+ level++;
+ }
+ }
+}
+
+static void setup_page_tables(void)
+{
+ unsigned int index;
+ const struct arm_mmu_region *region;
+ uint64_t max_va = 0, max_pa = 0;
+
+ for (index = 0; index < mmu_config.num_regions; index++)
+ {
+ region = &mmu_config.mmu_regions[index];
+ max_va = MAX(max_va, region->base_va + region->size);
+ max_pa = MAX(max_pa, region->base_pa + region->size);
+ }
+
+ __MMU_ASSERT(max_va <= (1ULL << CONFIG_ARM64_VA_BITS),
+ "Maximum VA not supported\n");
+ __MMU_ASSERT(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS),
+ "Maximum PA not supported\n");
+
+ /* create translation tables for user provided platform regions */
+
+ for (index = 0; index < mmu_config.num_regions; index++)
+ {
+ region = &mmu_config.mmu_regions[index];
+ if (region->size || region->attrs)
+ {
+ init_xlat_tables(region);
+ }
+ }
+
+ /* setup translation table for mirtos execution regions */
+
+ for (index = 0; index < ARRAY_SIZE(mmu_nxrt_regions); index++)
+ {
+ region = &mmu_nxrt_regions[index];
+ if (region->size || region->attrs)
+ {
+ init_xlat_tables(region);
+ }
+ }
+}
+
+static void enable_mmu_el1(unsigned int flags)
+{
+ uint64_t value;
+
Review Comment:
Maybe add:
`UNUSED(flags);
`
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,873 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y))
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ bool is_console;
+};
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1U << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535U << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1U << PL011_FBRD_WIDTH) - 1U);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
Review Comment:
Maybe add:
```
UNUSED(filep);
UNUSED(arg);
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,873 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y))
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ bool is_console;
+};
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1U << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535U << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1U << PL011_FBRD_WIDTH) - 1U);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
Review Comment:
Maybe add:
```
UNUSED(irq);
UNUSED(context);
```
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,240 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* enable FPU access trap */
+
+static void arm64_fpu_access_trap_enable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+ cpacr &= ~CPACR_EL1_FPEN_NOTRAP;
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/* disable FPU access trap */
+
+static void arm64_fpu_access_trap_disable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+ cpacr |= CPACR_EL1_FPEN_NOTRAP;
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/***************************************************************************
+ * Public Functions
+ ***************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb)
+{
+ struct fpu_reg *fpu_reg;
+
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ memset(&g_cpu_fpu_ctx[this_cpu()], 0,
+ sizeof(struct arm64_cpu_fpu_context));
+ g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb;
+
+ tcb->xcp.fpu_regs = (uint64_t *)&g_idle_thread_fpu[this_cpu()];
+ }
+
+ memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg));
+ fpu_reg = (struct fpu_reg *)tcb->xcp.fpu_regs;
+ fpu_reg->fpu_trap = 0;
+}
+
+void arm64_destory_fpu(struct tcb_s * tcb)
+{
+ struct tcb_s * owner;
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner == tcb)
+ {
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+}
+
+/***************************************************************************
+ * Name: arm64_fpu_enter_exception
+ *
+ * Description:
+ * called at every time get into a exception
+ *
+ ***************************************************************************/
+
+void arm64_fpu_enter_exception(void)
+{
+}
+
+void arm64_fpu_exit_exception(void)
+{
+}
+
+void arm64_fpu_trap(struct regs_context * regs)
+{
+ struct tcb_s * owner;
+ struct fpu_reg *fpu_reg;
+
Review Comment:
Maybe add:
`UNUSED(regs);`
##########
arch/arm64/src/common/arm64_exit.c:
##########
@@ -0,0 +1,157 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_exit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#ifdef CONFIG_DUMP_ON_EXIT
+# include <nuttx/fs/fs.h>
+#endif
+
+#include "task/task.h"
+#include "sched/sched.h"
+#include "group/group.h"
+#include "irq/irq.h"
+#include "arm64_internal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_DEBUG_SCHED_INFO
+# undef CONFIG_DUMP_ON_EXIT
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _up_dumponexit
+ *
+ * Description:
+ * Dump the state of all tasks whenever on task exits. This is debug
+ * instrumentation that was added to check file-related reference counting
+ * but could be useful again sometime in the future.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DUMP_ON_EXIT
+static void _up_dumponexit(struct tcb_s *tcb, void *arg)
+{
+ struct filelist *filelist;
+ int i;
+ int j;
+
+ sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->name, tcb->pid);
+ sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state);
+
+ filelist = tcb->group->tg_filelist;
+ for (i = 0; i < filelist->fl_rows; i++)
+ {
+ for (j = 0; j < CONFIG_NFILE_DESCRIPTORS_PER_BLOCK; j++)
+ {
+ struct inode *inode = filelist->fl_files[i][j].f_inode;
+ if (inode)
+ {
+ sinfo(" fd=%d refcount=%d\n",
+ i * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK + j,
+ inode->i_crefs);
+ }
+ }
+ }
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_exit
+ *
+ * Description:
+ * This function causes the currently executing task to cease
+ * to exist. This is a special case of task_delete() where the task to
+ * be deleted is the currently executing task. It is more complex because
+ * a context switch must be perform to the next ready to run task.
+ *
+ ****************************************************************************/
+
+void up_exit(int status)
+{
+ struct tcb_s *tcb = this_task();
+
Review Comment:
Maybe add:
`UNUSED(status);
`
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,253 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ UNUSED(regs);
+ UNUSED(arg);
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#else
+
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+ uint64_t next_cycle;
+
+ UNUSED(regs);
+ UNUSED(arg);
+
Review Comment:
Also add here
`UNUSED(irq);`
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,873 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y))
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ bool is_console;
+};
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1U << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535U << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1U << PL011_FBRD_WIDTH) - 1U);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport;
+ struct pl011_data *data;
+ int ret;
+
+ sport = (struct pl011_uart_port_s *)dev->priv;
+ data = &sport->data;
+
+ ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev);
+ arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0);
+
+ if (ret == OK)
+ {
+ up_enable_irq(sport->irq_num);
+ }
+ else
+ {
+ sinfo("error ret=%d\n", ret);
+ }
+
+ if (!data->sbsa)
+ {
+ pl011_enable(sport);
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_shutdown(struct uart_dev_s *dev)
+{
+ sinfo("%s: call unexpected\n", __func__);
Review Comment:
Add
`UNUSED(dev);
`
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1185097313
> I would like to say Congratulations on this HUGE PR!
>
> In the Single Core case, `ostest` is running successfully for me.
>
> In the SMP case, it seems that `ostest` fails or hangs in different places, but my system is ancient and I am running QEMU 3.1.0 (!!!), so it is possible that I am seeing old bugs in QEMU. I would need to upgrade my system and try the latest QEMU before I could draw any conclusions.
>
> Anyway, this PR is a very good starting point for NuttX on Arm64 and I look forward to seeing NuttX on real Arm64 hardware!
Yes, for SMP，the PR in qemu seem behave very different!!
In the beginning, I debug the PR with Ubuntu which is running in VMware. For Single Core, everything is OK, but for SMP, ostest hangs in different places just like your description. After fix some cache sync issue, the crash is occurred at signal testing every time, I check the crash with GDB and see a very strange phenomenon that data is different between CPU register and seeing with GDB, so it seem a data sync issue. I try different cache sync operation at this crash point but not work at all
things change when I debug the PR with a real Ubuntu PC, the crash not occurs anymore in that environment. I cannot explain why I see the phenomenon, but I cannot say it's certain a bug in qemu. because maybe with different speed it have different execution order between these two environment.
My real Ubuntu environment
Ubuntu 18.04.6 LTS
QEMU emulator version 4.0.1 (v4.0.1)
Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz
memory: 16GB
I have a IMX8 porting patch but some change need to be done, I will testing it and submit ASAP
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915062286
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
> @xiaoxiang781216 Maybe we don't need FAR keyword here?
Yes, other 32/64bit target already remove FAR:
https://github.com/apache/incubator-nuttx/pull/6086
https://github.com/apache/incubator-nuttx/pull/6092
https://github.com/apache/incubator-nuttx/pull/6093
https://github.com/apache/incubator-nuttx/pull/6095
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915013799
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+}
+
+#else
+
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
Same as tickless version of this function:
Should be:
`static int arm64_arch_timer_compare_isr(int irq, void *context, void *arg)`
At top of function, add:
`regs = (uint64_t) context;`
At end of function, add:
`return OK;`
(Edit: Removed FAR. Not needed for arm64.)
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r901559732
##########
arch/arm64/include/arch.h:
##########
@@ -0,0 +1,155 @@
+/****************************************************************************
+ * arch/arm64/include/arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_ARCH_H__
+#define __ARCH_ARM64_INCLUDE_ARCH_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <nuttx/pgalloc.h>
+# include <nuttx/addrenv.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+#if CONFIG_MM_PGSIZE != 4096
+# error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
+#endif
+
+#endif /* CONFIG_ARCH_ADDRENV */
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsp
+ ****************************************************************************/
+
+static inline uint64_t up_getsp(void)
+{
+ uint64_t sp;
+ __asm__
+ (
+ "\tmov %0, sp\n\t"
+ : "=r"(sp)
+ );
+
+ return sp;
+}
+
Review Comment:
Should we use `#define up_getsp() (uintptr_t)__builtin_frame_address(0)` the same as for ARM32?
##########
arch/arm64/include/limits.h:
##########
@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/arm64/include/limits.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H__
+#define __ARCH_ARM64_INCLUDE_LIMITS_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H
#define __ARCH_ARM64_INCLUDE_LIMITS_H
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,438 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H__
+#define __ARCH_ARM64_INCLUDE_IRQ_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+#ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+#endif
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* In this configuration, all syscalls execute from an internal kernel
+ * stack. Why? Because when we instantiate and initialize the address
+ * environment of the new user process, we will temporarily lose the
+ * address environment of the old user process, including its stack
+ * contents. The kernel C logic will crash immediately with no valid
+ * stack in place.
+ */
+
+ uint64_t *ustkptr; /* Saved user stack pointer */
+ uint64_t *kstack; /* Allocate base of the (aligned) kernel stack */
+ uint64_t *kstkptr; /* Saved kernel stack pointer */
+#endif
+#endif
+};
+
+/* Name: up_irq_save, up_irq_restore, and friends.
+ *
+ * NOTE: This function should never be called from application code and,
+ * as a general rule unless you really know what you are doing, this
+ * function should not be called directly from operation system code either:
+ * Typically, the wrapper functions, enter_critical_section() and
+ * leave_critical section(), are probably what you really want.
+ */
+
+/* Return the current IRQ state */
+
+static inline irqstate_t irqstate(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__
+ (
+ "mrs %0, daif" : "=r" (flags):: "memory"
+ );
+
+ return flags;
+}
+
+/* Disable IRQs and return the previous IRQ state */
+
+static inline irqstate_t up_irq_save(void)
+{
+ irqstate_t flags;
+ __asm__ __volatile__
+ (
+ "mrs %0, daif \n"
+ "msr daifset, #2\n"
+ : "=r" (flags)
+ :
+ : "memory"
+ );
+
+ return flags;
+}
+
+/* Enable IRQs and return the previous IRQ state */
+
+static inline irqstate_t up_irq_enable(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__
+ (
+ "mrs %0, daif \n"
+ "msr daifclr, #2\n"
+ : "=r" (flags)
+ :
+ : "memory"
+ );
+ return flags;
+}
+
+/* Restore saved IRQ & FIQ state */
+
+static inline void up_irq_restore(irqstate_t flags)
+{
+ __asm__ __volatile__("msr daif, %0" :: "r" (flags): "memory");
+}
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ * corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
+#else
+# define up_cpu_index() (0)
+#endif
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description: Return true is we are currently executing in
+ * the interrupt handler context.
+ *
+ ****************************************************************************/
+
+static inline bool up_interrupt_context(void)
+{
+#ifdef CONFIG_SMP
+ irqstate_t flags = up_irq_save();
+#endif
+
+ bool ret = (CURRENT_REGS != NULL);
+
+#ifdef CONFIG_SMP
+ up_irq_restore(flags);
+#endif
+
+ return ret;
+}
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM64_INCLUDE_IRQ_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_IRQ_H */
```
##########
arch/arm64/include/spinlock.h:
##########
@@ -0,0 +1,90 @@
+/****************************************************************************
+ * arch/arm64/include/spinlock.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_SPINLOCK_H__
+#define __ARCH_ARM64_INCLUDE_SPINLOCK_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_SPINLOCK_H
#define __ARCH_ARM64_INCLUDE_SPINLOCK_H
```
##########
arch/arm64/include/arch.h:
##########
@@ -0,0 +1,155 @@
+/****************************************************************************
+ * arch/arm64/include/arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_ARCH_H__
+#define __ARCH_ARM64_INCLUDE_ARCH_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_ARCH_H
#define __ARCH_ARM64_INCLUDE_ARCH_H
```
##########
boards/arm64/qemu/qemu-a53/include/board_memorymap.h:
##########
@@ -0,0 +1,59 @@
+/****************************************************************************
+ * boards/arm64/qemu/qemu-a53/include/board_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM64_QEMU_QEMU_A53_INCLUDE_BOARD_MEMORYMAP_H__
+#define __BOARDS_ARM64_QEMU_QEMU_A53_INCLUDE_BOARD_MEMORYMAP_H__
Review Comment:
```suggestion
#ifndef __BOARDS_ARM64_QEMU_QEMU_A53_INCLUDE_BOARD_MEMORYMAP_H
#define __BOARDS_ARM64_QEMU_QEMU_A53_INCLUDE_BOARD_MEMORYMAP_H
```
##########
arch/arm64/include/inttypes.h:
##########
@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/arm64/include/inttypes.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_INTTYPES_H__
+#define __ARCH_ARM64_INCLUDE_INTTYPES_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_INTTYPES_H
#define __ARCH_ARM64_INCLUDE_INTTYPES_H
```
##########
arch/arm64/include/limits.h:
##########
@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/arm64/include/limits.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H__
+#define __ARCH_ARM64_INCLUDE_LIMITS_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <limits.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT 8
+#define SCHAR_MIN (-SCHAR_MAX - 1)
+#define SCHAR_MAX 127
+#define UCHAR_MAX 255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
+#define CHAR_MIN 0
+#define CHAR_MAX UCHAR_MAX
+#else
+#define CHAR_MIN SCHAR_MIN
+#define CHAR_MAX SCHAR_MAX
+#endif
+
+#define SHRT_MIN (-SHRT_MAX - 1)
+#define SHRT_MAX 32767
+#define USHRT_MAX 65535U
+
+#define INT_MIN (-INT_MAX - 1)
+#define INT_MAX 2147483647
+#define UINT_MAX 4294967295U
+
+/* For 64-bit arm64 with Linux ABI, long is identical to long long */
+
+#define LONG_MIN LLONG_MIN
+#define LONG_MAX LLONG_MAX
+#define ULONG_MAX ULLONG_MAX
+
+#define LLONG_MIN (-LLONG_MAX - 1)
+#define LLONG_MAX 9223372036854775807ll
+#define ULLONG_MAX 18446744073709551615ull
+
+/* A pointer is 8 bytes */
+
+#define PTR_MIN (-PTR_MAX - 1)
+#define PTR_MAX LLONG_MAX
+#define UPTR_MAX ULLONG_MAX
+
+#endif /* __ARCH_ARM64_INCLUDE_LIMITS_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_LIMITS_H */
```
##########
arch/arm64/include/limits.h:
##########
@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/arm64/include/limits.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H__
+#define __ARCH_ARM64_INCLUDE_LIMITS_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <limits.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT 8
+#define SCHAR_MIN (-SCHAR_MAX - 1)
+#define SCHAR_MAX 127
+#define UCHAR_MAX 255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
Review Comment:
I think WCHAR defines are mossing
##########
arch/arm64/include/inttypes.h:
##########
@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/arm64/include/inttypes.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_INTTYPES_H__
+#define __ARCH_ARM64_INCLUDE_INTTYPES_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PRId8 "d"
+#define PRId16 "d"
+#define PRId32 "d"
+#define PRId64 "ld"
+
+#define PRIdPTR "ld"
+
+#define PRIi8 "i"
+#define PRIi16 "i"
+#define PRIi32 "i"
+#define PRIi64 "li"
+
+#define PRIiPTR "li"
+
+#define PRIo8 "o"
+#define PRIo16 "o"
+#define PRIo32 "o"
+#define PRIo64 "lo"
+
+#define PRIoPTR "lo"
+
+#define PRIu8 "u"
+#define PRIu16 "u"
+#define PRIu32 "u"
+#define PRIu64 "lu"
+
+#define PRIuPTR "lu"
+
+#define PRIx8 "x"
+#define PRIx16 "x"
+#define PRIx32 "x"
+#define PRIx64 "lx"
+
+#define PRIxPTR "lx"
+
+#define PRIX8 "X"
+#define PRIX16 "X"
+#define PRIX32 "X"
+#define PRIX64 "lX"
+
+#define PRIXPTR "lX"
+
+#define SCNd8 "hhd"
+#define SCNd16 "hd"
+#define SCNd32 "d"
+#define SCNd64 "ld"
+
+#define SCNdPTR "ld"
+
+#define SCNi8 "hhi"
+#define SCNi16 "hi"
+#define SCNi32 "i"
+#define SCNi64 "li"
+
+#define SCNiPTR "li"
+
+#define SCNo8 "hho"
+#define SCNo16 "ho"
+#define SCNo32 "o"
+#define SCNo64 "lo"
+
+#define SCNoPTR "lo"
+
+#define SCNu8 "hhu"
+#define SCNu16 "hu"
+#define SCNu32 "u"
+#define SCNu64 "lu"
+
+#define SCNuPTR "u"
+
+#define SCNx8 "hhx"
+#define SCNx16 "hx"
+#define SCNx32 "x"
+#define SCNx64 "lx"
+
+#define SCNxPTR "lx"
+
+#define INT8_C(x) x
+#define INT16_C(x) x
+#define INT32_C(x) x
+#define INT64_C(x) x ## l
+
+#define UINT8_C(x) x
+#define UINT16_C(x) x
+#define UINT32_C(x) x ## u
+#define UINT64_C(x) x ## ul
+
+#endif /* __ARCH_ARM64_INCLUDE_INTEL64_INTTYPES_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_INTTYPES_H */
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,438 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H__
+#define __ARCH_ARM64_INCLUDE_IRQ_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
#define __ARCH_ARM64_INCLUDE_IRQ_H
```
##########
arch/arm64/include/qemu/chip.h:
##########
@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/arm64/include/qemu/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_QEMU_CHIP_H__
+#define __ARCH_ARM64_INCLUDE_QEMU_CHIP_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
#define __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
```
##########
arch/arm64/include/arch.h:
##########
@@ -0,0 +1,155 @@
+/****************************************************************************
+ * arch/arm64/include/arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_ARCH_H__
+#define __ARCH_ARM64_INCLUDE_ARCH_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <nuttx/pgalloc.h>
+# include <nuttx/addrenv.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+#if CONFIG_MM_PGSIZE != 4096
+# error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
+#endif
+
+#endif /* CONFIG_ARCH_ADDRENV */
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsp
+ ****************************************************************************/
+
+static inline uint64_t up_getsp(void)
+{
+ uint64_t sp;
+ __asm__
+ (
+ "\tmov %0, sp\n\t"
+ : "=r"(sp)
+ );
+
+ return sp;
+}
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+/* The task group resources are retained in a single structure, task_group_s
+ * that is defined in the header file nuttx/include/nuttx/sched.h. The type
+ * group_addrenv_t must be defined by platform specific logic in
+ * nuttx/arch/<architecture>/include/arch.h.
+ *
+ * These tables would hold the physical address of the level 2 page tables.
+ * All would be initially NULL and would not be backed up with physical
+ * memory until mappings in the level 2 page table are required.
+ */
+
+struct group_addrenv_s
+{
+ /* Level 1 page table entries for each group section */
+
+ uintptr_t *text[ARCH_TEXT_NSECTS];
+ uintptr_t *data[ARCH_DATA_NSECTS];
+#ifdef CONFIG_BUILD_KERNEL
+ uintptr_t *heap[ARCH_HEAP_NSECTS];
+#ifdef CONFIG_MM_SHM
+ uintptr_t *shm[ARCH_SHM_NSECTS];
+#endif
+
+ /* Initial heap allocation (in bytes). This exists only provide an
+ * indirect path for passing the size of the initial heap to the heap
+ * initialization logic. These operations are separated in time and
+ * architecture. REVISIT: I would like a better way to do this.
+ */
+
+ size_t heapsize;
+#endif
+};
+
+typedef struct group_addrenv_s group_addrenv_t;
+
+/* This type is used when the OS needs to temporarily instantiate a
+ * different address environment. Used in the implementation of
+ *
+ * int up_addrenv_select(group_addrenv_t addrenv, save_addrenv_t *oldenv);
+ * int up_addrenv_restore(save_addrenv_t oldenv);
+ *
+ * In this case, the saved valued in the L1 page table are returned
+ */
+
+struct save_addrenv_s
+{
+ uint32_t text[ARCH_TEXT_NSECTS];
+ uint32_t data[ARCH_DATA_NSECTS];
+#ifdef CONFIG_BUILD_KERNEL
+ uint32_t heap[ARCH_HEAP_NSECTS];
+#ifdef CONFIG_MM_SHM
+ uint32_t shm[ARCH_SHM_NSECTS];
+#endif
+#endif
+};
+
+typedef struct save_addrenv_s save_addrenv_t;
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_ARCH_H */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_ARCH_H */
```
##########
arch/arm64/include/qemu/chip.h:
##########
@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/arm64/include/qemu/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_QEMU_CHIP_H__
+#define __ARCH_ARM64_INCLUDE_QEMU_CHIP_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_QEMU_A53)
+
+#define CONFIG_GICD_BASE 0x8000000
+#define CONFIG_GICR_BASE 0x80a0000
+
+#define CONFIG_RAMBANK1_ADDR 0x40000000
+#define CONFIG_RAMBANK1_SIZE MB(128)
+
+#define CONFIG_DEVICEIO_BASEADDR 0x7000000
+#define CONFIG_DEVICEIO_SIZE MB(512)
+
+#define CONFIG_LOAD_BASE 0x40280000
+
+#endif
+
+#endif /* __ARCH_ARM64_INCLUDE_QEMU_CHIP_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_QEMU_CHIP_H */
```
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H__
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm);
+
+ __asm__ __volatile__
+ (
+ "hlt %1"
+ : "=r"(reg0)
+ : "i"(SYS_smhcall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* Result from SMC/HVC call
+ * a0-a7 result values from registers 0 to 7
+ */
+
+struct arm64_smccc_res
+{
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+};
+
+typedef struct arm64_smccc_res arm64_smccc_res_t;
+
+enum arm64_smccc_conduit
+{
+ SMCCC_CONDUIT_NONE,
+ SMCCC_CONDUIT_SMC,
+ SMCCC_CONDUIT_HVC,
+};
+
+/* Make HVC calls
+ *
+ * param a0 function identifier
+ * param a1-a7 parameters registers
+ * param res results
+ */
+
+void arm64_smccc_hvc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm64_smccc_res *res);
+
+/* Make SMC calls
+ *
+ * param a0 function identifier
+ * param a1-a7 parameters registers
+ * param res results
+ */
+
+void arm64_smccc_smc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm64_smccc_res *res);
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM64_INCLUDE_SYSCALL_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_SYSCALL_H */
```
##########
arch/arm64/include/qemu/irq.h:
##########
@@ -0,0 +1,34 @@
+/****************************************************************************
+ * arch/arm64/include/qemu/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_QEMU_IRQ_H__
+#define __ARCH_ARM64_INCLUDE_QEMU_IRQ_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define NR_IRQS 220 /* Total number of interrupts */
+
+#endif /* __ARCH_ARM64_INCLUDE_QEMU_IRQ_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_QEMU_IRQ_H */
```
##########
arch/arm64/include/qemu/irq.h:
##########
@@ -0,0 +1,34 @@
+/****************************************************************************
+ * arch/arm64/include/qemu/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_QEMU_IRQ_H__
+#define __ARCH_ARM64_INCLUDE_QEMU_IRQ_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_QEMU_IRQ_H
#define __ARCH_ARM64_INCLUDE_QEMU_IRQ_H
```
##########
arch/arm64/include/types.h:
##########
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm64/include/types.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_TYPES_H__
+#define __ARCH_ARM64_INCLUDE_TYPES_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_TYPES_H
#define __ARCH_ARM64_INCLUDE_TYPES_H
```
##########
boards/arm64/qemu/qemu-a53/src/qemu-a53.h:
##########
@@ -0,0 +1,59 @@
+/****************************************************************************
+ * boards/arm64/qemu/qemu-a53/src/qemu-a53.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM64_QEMU_QEMU_A53_SRC_QEMU_A53_H__
+#define __BOARDS_ARM64_QEMU_QEMU_A53_SRC_QEMU_A53_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Functions Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: qemu_bringup
+ *
+ * Description:
+ * Bring up board features
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE)
+int qemu_bringup(void);
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_ARM64_QEMU_QEMU_A53_SRC_QEMU_A53_H__ */
Review Comment:
```suggestion
#endif /* __BOARDS_ARM64_QEMU_QEMU_A53_SRC_QEMU_A53_H */
```
##########
arch/arm64/include/types.h:
##########
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm64/include/types.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_TYPES_H__
+#define __ARCH_ARM64_INCLUDE_TYPES_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types. NOTE that these type
+ * names have a leading underscore character. This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character. This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char _int8_t;
+typedef unsigned char _uint8_t;
+
+typedef signed short _int16_t;
+typedef unsigned short _uint16_t;
+
+typedef signed int _int32_t;
+typedef unsigned int _uint32_t;
+
+typedef signed long _int64_t;
+typedef unsigned long _uint64_t;
+#define __INT64_DEFINED
+
+typedef _int64_t _intmax_t;
+typedef _uint64_t _uintmax_t;
+
+#if defined(__WCHAR_TYPE__)
+typedef __WCHAR_TYPE__ _wchar_t;
+#else
+typedef int _wchar_t;
+#endif
+
+#if defined(__SIZE_TYPE__)
+/* If __SIZE_TYPE__ is defined we define ssize_t based on size_t.
+ * We simply change "unsigned" to "signed" for this single definition
+ * to make sure ssize_t and size_t only differ by their signedness.
+ */
+
+#define unsigned signed
+typedef __SIZE_TYPE__ _ssize_t;
+#undef unsigned
+typedef __SIZE_TYPE__ _size_t;
+
+#elif defined(CONFIG_ARCH_SIZET_LONG)
+
+typedef signed long _ssize_t;
+typedef unsigned long _size_t;
+
+#else
+
+typedef signed int _ssize_t;
+typedef unsigned int _size_t;
+
+#endif
+
+/* This is the size of the interrupt state save returned by
+ * up_irq_save()
+ */
+
+typedef unsigned int irqstate_t;
+
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM64_INCLUDE_TYPES_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_TYPES_H */
```
##########
boards/arm64/qemu/qemu-a53/scripts/Make.defs:
##########
@@ -0,0 +1,51 @@
+############################################################################
+# boards/arm64/imx8/imx8qm-mek/scripts/Make.defs
Review Comment:
```suggestion
# boards/arm64/qemu/qemu-a53/scripts/Make.defs
```
##########
boards/arm64/qemu/qemu-a53/src/qemu-a53.h:
##########
@@ -0,0 +1,59 @@
+/****************************************************************************
+ * boards/arm64/qemu/qemu-a53/src/qemu-a53.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM64_QEMU_QEMU_A53_SRC_QEMU_A53_H__
+#define __BOARDS_ARM64_QEMU_QEMU_A53_SRC_QEMU_A53_H__
Review Comment:
```suggestion
#ifndef __BOARDS_ARM64_QEMU_QEMU_A53_SRC_QEMU_A53_H
#define __BOARDS_ARM64_QEMU_QEMU_A53_SRC_QEMU_A53_H
```
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H__
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
#define __ARCH_ARM64_INCLUDE_SYSCALL_H
```
##########
boards/arm64/qemu/qemu-a53/scripts/dramboot.ld:
##########
@@ -0,0 +1,125 @@
+/****************************************************************************
+ * boards/arm64/imx8/imx8qm-mek/scripts/dramboot.ld
Review Comment:
```suggestion
* boards/arm64/qemu/qemu-a53/scripts/dramboot.ld
```
##########
boards/arm64/qemu/qemu-a53/include/board_memorymap.h:
##########
@@ -0,0 +1,59 @@
+/****************************************************************************
+ * boards/arm64/qemu/qemu-a53/include/board_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM64_QEMU_QEMU_A53_INCLUDE_BOARD_MEMORYMAP_H__
+#define __BOARDS_ARM64_QEMU_QEMU_A53_INCLUDE_BOARD_MEMORYMAP_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_ARM64_QEMU_QEMU_A53_INCLUDE_BOARD_MEMORYMAP_H__ */
Review Comment:
```suggestion
#endif /* __BOARDS_ARM64_QEMU_QEMU_A53_INCLUDE_BOARD_MEMORYMAP_H */
```
##########
arch/arm64/include/spinlock.h:
##########
@@ -0,0 +1,90 @@
+/****************************************************************************
+ * arch/arm64/include/spinlock.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_SPINLOCK_H__
+#define __ARCH_ARM64_INCLUDE_SPINLOCK_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Spinlock states */
+
+#define SP_UNLOCKED 0 /* The Un-locked state */
+#define SP_LOCKED 1 /* The Locked state */
+
+/* Memory barriers for use with NuttX spinlock logic
+ *
+ * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
+ * explicit memory accesses that appear in program order before the DMB
+ * instruction are observed before any explicit memory accesses that appear
+ * in program order after the DMB instruction. It does not affect the
+ * ordering of any other instructions executing on the processor
+ *
+ * dmb st - Data memory barrier. Wait for stores to complete.
+ *
+ * Data Synchronization Barrier (DSB) acts as a special kind of memory
+ * barrier. No instruction in program order after this instruction executes
+ * until this instruction completes. This instruction completes when: (1) All
+ * explicit memory accesses before this instruction complete, and (2) all
+ * Cache, Branch predictor and TLB maintenance operations before this
+ * instruction complete.
+ *
+ * dsb sy - Data syncrhonization barrier. Assures that the CPU waits until
+ * all memory accesses are complete
+ */
+
+#define SP_DSB(n) __asm__ __volatile__ ("dsb sy" : : : "memory")
+#define SP_DMB(n) __asm__ __volatile__ ("dmb st" : : : "memory")
+
+#define SP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
+#define SP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
+
+#ifndef __ASSEMBLY__
+
+/* The Type of a spinlock.
+ * ARM official document
+ * ARM® Cortex®-A Series, Version: 1.0, Programmer’s Guide for ARMv8-A
+ * ARM DEN0024A (ID050815)
+ *
+ * chapter 14.1.4 Synchronization
+ *
+ * The A64 instruction set has instructions for implementing
+ * synchronization functions:
+ * -- Load Exclusive (LDXR): LDXR W|Xt, [Xn]
+ * -- Store Exclusive (STXR): STXR Ws, W|Xt, [Xn] where Ws
+ * indicates whether the store completed successfully.
+ * 0 = success.
+ * -- Clear Exclusive access monitor (CLREX) This is used to
+ * clear the state of the Local Exclusive Monitor.
+ */
+
+typedef uint64_t spinlock_t;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM64_INCLUDE_SPINLOCK_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_INCLUDE_SPINLOCK_H */
```
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902414338
##########
arch/arm64/src/common/arm64_arch_timer.h:
##########
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/src/common/arm64_arch_timer.h:
##########
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_gic.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CONFIG_ARM_TIMER_SECURE_IRQ (GIC_PPI_INT_BASE + 13)
+#define CONFIG_ARM_TIMER_NON_SECURE_IRQ (GIC_PPI_INT_BASE + 14)
+#define CONFIG_ARM_TIMER_VIRTUAL_IRQ (GIC_PPI_INT_BASE + 11)
+#define CONFIG_ARM_TIMER_HYP_IRQ (GIC_PPI_INT_BASE + 10)
+
+#define ARM_ARCH_TIMER_IRQ CONFIG_ARM_TIMER_VIRTUAL_IRQ
+#define ARM_ARCH_TIMER_PRIO IRQ_DEFAULT_PRIORITY
+#define ARM_ARCH_TIMER_FLAGS IRQ_TYPE_LEVEL
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+extern uint64_t arch_counter_read(void);
+extern void arch_timer_delay(long mini_sec);
+extern void arch_start_timer(void);
+
+#ifdef CONFIG_SMP
+void arm64_smp_timer_init(void);
+#endif
+
+#endif //__ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H__
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915836788
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
Review Comment:
This is AArch64 Naming conventions for float registers
https://developer.arm.com/documentation/den0024/a/ARMv8-Registers/NEON-and-floating-point-registers/Scalar-register-sizes
Q means Quadword, it's different with D Doubleword like armv7
So i perfer to keep consistent with armv8
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1182665736
I squashed all change into two commit, please check
@xiaoxiang781216, @hartmannathan @pkarashchenko
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r903373497
##########
tools/ci/testlist/other.dat:
##########
@@ -20,3 +20,7 @@
# Sparc-gaisler-elf toolchain doesn't provide macOS binaries
/sparc
-xx3823:nsh
+
Review Comment:
done
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1184336158
@pkarashchenko , please check again
thanks for you careful check
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[GitHub] [incubator-nuttx] hartmannathan merged pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan merged PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r920722016
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,619 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
Review Comment:
The current macro is dangerous because (ptr) - sizeof(type) if using ptr size type for calculation. So if ptr is uint8_t * then it will jump back by sizeof(type) bytes, but if it is uint64_t * than by sizeof(type) * 8 bytes
--- I try to following container_of defined in NuttX, please check
but actually if we want to get a completely safety version, we maybe need to follow container_of in Linux kernel
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916015151
##########
arch/arm64/src/Toolchain.defs:
##########
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm64/src/Toolchain.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+#
+# Supported toolchains
+#
+# Each toolchain definition should set:
+#
+# CROSSDEV The GNU toolchain triple (command prefix)
+# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
+# FPU options, etc.
+# ARCHOPTIMIZATION The optimization level that results in
+# reliable code generation.
+#
+
+ifeq ($(CONFIG_ARCH_ARMV8A),y)
+ARCHCPUFLAGS += -march=armv8-a
+endif
+
+ifeq ($(CONFIG_ARCH_CORTEX_A53),y)
+ARCHCPUFLAGS += -mtune=cortex-a53
+endif
+
+ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
+ ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL)
+else ifeq ($(CONFIG_DEBUG_FULLOPT),y)
+ ARCHOPTIMIZATION += -Os
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += -fno-strict-aliasing
+endif
+
+ifeq ($(CONFIG_FRAME_POINTER),y)
+ ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls
+else
+ ARCHOPTIMIZATION += -fomit-frame-pointer
+endif
+
+ifeq ($(CONFIG_STACK_CANARIES),y)
+ ARCHOPTIMIZATION += -fstack-protector-all
+endif
+
+ifeq ($(CONFIG_ARCH_COVERAGE),y)
+ ARCHOPTIMIZATION += -fprofile-generate -ftest-coverage
+endif
+ARCHCFLAGS += -fno-common
+ARCHCXXFLAGS += -fno-common -nostdinc++
+
+ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Werror
+ARCHCXXFLAGS += -Wall -Wshadow -Wundef
+
+ifneq ($(CONFIG_CXX_EXCEPTION),y)
+ ARCHCXXFLAGS += -fno-exceptions -fcheck-new
+endif
+
+ifneq ($(CONFIG_CXX_RTTI),y)
+ ARCHCXXFLAGS += -fno-rtti
+endif
+
+LDFLAGS += -nostdlib
+
+# Optimization of unused sections
+
+ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y)
+ LDFLAGS += --gc-sections
+ ARCHOPTIMIZATION += -ffunction-sections -fdata-sections
+endif
+
+# Debug link map
+
+ifeq ($(CONFIG_DEBUG_LINK_MAP),y)
+ LDFLAGS += --cref -Map=$(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx.map)
+endif
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+ ARCHOPTIMIZATION += -g
+endif
+CROSSDEV ?= aarch64-none-elf-
+
+# Default toolchain
+
+CC = $(CROSSDEV)gcc
Review Comment:
what about to add clang support at next PR ?
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916775163
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
Review Comment:
it's use at arm64_initialstate.c
arm64_new_task, to allocate a strcut size from stack
only for readable purpose
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915966821
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm);
+
+ __asm__ __volatile__
+ (
+ "hlt %1"
+ : "=r"(reg0)
+ : "i"(SYS_smhcall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* Result from SMC/HVC call
+ * a0-a7 result values from registers 0 to 7
+ */
+
+struct arm64_smccc_res
+{
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+};
+
+typedef struct arm64_smccc_res arm64_smccc_res_t;
+
+enum arm64_smccc_conduit
Review Comment:
I think it's need to keep in this haeder
in arm64, smc and hvc is samed like svc, they are syscall instruction which is trap into EL2 or EL3 to call routine provide by hypervisor or security firmware
PSCI is not only routines provided by firmware, if we need to call other function present at EL2 or EL3, we need to use these define, so i think we need keep these define at syscall.h
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r917707332
##########
arch/arm64/include/types.h:
##########
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm64/include/types.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_TYPES_H
+#define __ARCH_ARM64_INCLUDE_TYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types. NOTE that these type
+ * names have a leading underscore character. This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character. This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char _int8_t;
+typedef unsigned char _uint8_t;
+
+typedef signed short _int16_t;
+typedef unsigned short _uint16_t;
+
+typedef signed int _int32_t;
+typedef unsigned int _uint32_t;
+
+typedef signed long _int64_t;
+typedef unsigned long _uint64_t;
+#define __INT64_DEFINED
+
+typedef _int64_t _intmax_t;
+typedef _uint64_t _uintmax_t;
+
+#if defined(__WCHAR_TYPE__)
+typedef __WCHAR_TYPE__ _wchar_t;
+#else
+typedef int _wchar_t;
+#endif
+
+#if defined(__SIZE_TYPE__)
+/* If __SIZE_TYPE__ is defined we define ssize_t based on size_t.
+ * We simply change "unsigned" to "signed" for this single definition
+ * to make sure ssize_t and size_t only differ by their signedness.
+ */
+
+#define unsigned signed
+typedef __SIZE_TYPE__ _ssize_t;
+#undef unsigned
+typedef __SIZE_TYPE__ _size_t;
+
+#elif defined(CONFIG_ARCH_SIZET_LONG)
+
+typedef signed long _ssize_t;
+typedef unsigned long _size_t;
+
+#else
+
+typedef signed int _ssize_t;
+typedef unsigned int _size_t;
+
+#endif
+
+/* This is the size of the interrupt state save returned by
+ * up_irq_save()
+ */
+
+typedef unsigned int irqstate_t;
Review Comment:
Ok
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1164378705
> > Accidentally merged some unrelated commits into this PR? Some changes in graphics, drivers, etc., which are good changes, seem unrelated to this PR. Suggest to separate these and submit in other PRs. Not necessary to wait for this PR to be merged, IMO. Thanks!
>
> ----Sorry, error submit and fix already, please check again, thanks
Yes, this looks much better. Thanks!
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906659963
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,438 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+#ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+#endif
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* In this configuration, all syscalls execute from an internal kernel
+ * stack. Why? Because when we instantiate and initialize the address
+ * environment of the new user process, we will temporarily lose the
+ * address environment of the old user process, including its stack
+ * contents. The kernel C logic will crash immediately with no valid
+ * stack in place.
+ */
+
+ uint64_t *ustkptr; /* Saved user stack pointer */
+ uint64_t *kstack; /* Allocate base of the (aligned) kernel stack */
+ uint64_t *kstkptr; /* Saved kernel stack pointer */
+#endif
+#endif
+};
+
+/* Name: up_irq_save, up_irq_restore, and friends.
+ *
+ * NOTE: This function should never be called from application code and,
+ * as a general rule unless you really know what you are doing, this
+ * function should not be called directly from operation system code either:
+ * Typically, the wrapper functions, enter_critical_section() and
+ * leave_critical section(), are probably what you really want.
+ */
+
+/* Return the current IRQ state */
+
+static inline irqstate_t irqstate(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__
Review Comment:
Minor, optional. Can be one line as in `up_irq_restore`
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
Review Comment:
```suggestion
# define MIN(a, b) (((a) < (b)) ? (a) : (b))
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#define BIT(n) (1UL << (n))
+#define BIT64(_n) (1ULL << (_n))
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
Review Comment:
Optional
```suggestion
#define BIT64_MASK(n) (BIT64(n) - BIT64(0))
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#define BIT(n) (1UL << (n))
Review Comment:
optional
```suggestion
#define BIT(n) (UINT32_C(1) << (n))
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#define BIT(n) (1UL << (n))
+#define BIT64(_n) (1ULL << (_n))
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+#define DAIFSET_FIQ_BIT BIT(0)
+#define DAIFSET_IRQ_BIT BIT(1)
+#define DAIFSET_ABT_BIT BIT(2)
+#define DAIFSET_DBG_BIT BIT(3)
+
+#define DAIFCLR_FIQ_BIT BIT(0)
+#define DAIFCLR_IRQ_BIT BIT(1)
+#define DAIFCLR_ABT_BIT BIT(2)
+#define DAIFCLR_DBG_BIT BIT(3)
+
+#define DAIF_FIQ_BIT BIT(6)
+#define DAIF_IRQ_BIT BIT(7)
+#define DAIF_ABT_BIT BIT(8)
+#define DAIF_DBG_BIT BIT(9)
+
+#define DAIF_MASK (0xf << 6)
+
+/* SPSR M[3:0] define
+ *
+ * Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ * SPSR_EL1: Saved Program Status Register (EL1)
+ * SPSR_EL2: Saved Program Status Register (EL2)
+ * SPSR_EL3: Saved Program Status Register (EL3)
+ *
+ * reference to Programmer’s Guide for ARMv8-A
+ * (ARM DEN0024A, ID050815 ), 4.1.2 Stack pointer
+ *
+ * The T suffix, indicates use of the SP_EL0 stack pointer.
+ * The H suffix, indicates use of the SP_ELx stack pointer.
+ *
+ */
+
+#define SPSR_DAIF_SHIFT (6)
+#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE_EL0T (0x0)
+#define SPSR_MODE_EL1T (0x4)
+#define SPSR_MODE_EL1H (0x5)
+#define SPSR_MODE_EL2T (0x8)
+#define SPSR_MODE_EL2H (0x9)
+#define SPSR_MODE_MASK (0xf)
+
+/* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ *
+ * SCTLR_EL1: System Control Register (EL1)
+ * SCTLR_EL2: System Control Register (EL2)
+ * SCTLR_EL3: System Control Register (EL3)
+ *
+ */
+
+#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(20) | BIT(11))
+
+#define SCTLR_M_BIT BIT(0)
+#define SCTLR_A_BIT BIT(1)
+#define SCTLR_C_BIT BIT(2)
+#define SCTLR_SA_BIT BIT(3)
+#define SCTLR_I_BIT BIT(12)
+
+/* CurrentEL: Current Exception Level */
+
+#define MODE_EL_SHIFT (0x2)
+#define MODE_EL_MASK (0x3)
+
+#define MODE_EL3 (0x3)
+#define MODE_EL2 (0x2)
+#define MODE_EL1 (0x1)
+#define MODE_EL0 (0x0)
+
+#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
+
+/* MPIDR_EL1, Multiprocessor Affinity Register */
+
+#define MPIDR_AFFLVL_MASK (0xff)
+
+#define MPIDR_AFF0_SHIFT (0)
+#define MPIDR_AFF1_SHIFT (8)
+#define MPIDR_AFF2_SHIFT (16)
+#define MPIDR_AFF3_SHIFT (32)
+
+#define MPIDR_AFFLVL(mpidr, aff_level) \
+ (((mpidr) >> MPIDR_AFF ## aff_level ## _SHIFT) & MPIDR_AFFLVL_MASK)
+
+#define GET_MPIDR() read_sysreg(mpidr_el1)
+#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0)
Review Comment:
```suggestion
#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL((mpidr), 0)
```
##########
arch/arm64/src/common/arm64_cache.c:
##########
@@ -0,0 +1,449 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cache.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* Common operations for the caches
+ *
+ * WB means write-back and intends to transfer dirty cache lines to memory in
+ * a copy-back cache policy. May be a no-op in write-back cache policy.
+ *
+ * INVD means invalidate and will mark cache lines as not valid. A future
+ * access to the associated address is guaranteed to generate a memory fetch.
+ *
+ * armv8 data cache instruction:
+ *
+ * DC CIVAC (WB+INVD):
+ * Data or unified Cache line Clean and Invalidate by VA to PoC
+ * Clean and Invalidate data cache by address to Point of Coherency.
+ *
+ * DC CVAC (WB):
+ * Data or unified Cache line Clean by VA to PoC
+ * Clean data cache by address to Point of Coherency.
+ *
+ * DC IVAC (INVD):
+ * Data or unified Cache line Invalidate by VA to PoC
+ * Invalidate data cache by address to Point of Coherency
+ */
+
+#define CACHE_OP_WB BIT(0)
+#define CACHE_OP_INVD BIT(1)
+#define CACHE_OP_WB_INVD (CACHE_OP_WB | CACHE_OP_INVD)
+
+#define LINE_MASK(line) ((line) - 1)
+#define LINE_ALIGN_DOWN(a, line) ((a) & ~LINE_MASK(line))
+#define LINE_ALIGN_UP(a, line) \
+ (((a) + LINE_MASK(line)) & ~LINE_MASK(line))
+
+#define dc_ops(op, val) \
+ ({ \
+ __asm__ volatile ("dc " op ", %0" : : "r" (val) : "memory"); \
+ })
+
+/* IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
+ * Purpose
+ * Invalidate all instruction caches in the Inner Shareable domain of
+ * the PE executing the instruction to the Point of Unification.
+ */
+
+static inline void __ic_iallu(void)
+{
+ __asm__ volatile ("ic iallu" : : : "memory");
+}
+
+/* IC IALLU, Instruction Cache Invalidate All to PoU
+ * Purpose
+ * Invalidate all instruction caches of the PE executing
+ * the instruction to the Point of Unification.
+ */
+
+static inline void __ic_ialluis(void)
+{
+ __asm__ volatile ("ic ialluis" : : : "memory");
+}
+
+size_t dcache_line_size;
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* operation for data cache by virtual address to PoC */
+
+static inline int arm64_dcache_range(uintptr_t start_addr,
+ uintptr_t end_addr, int op)
+{
+ /* Align address to line size */
+
+ start_addr = LINE_ALIGN_DOWN(start_addr, dcache_line_size);
+
+ while (start_addr < end_addr)
+ {
+ switch (op)
+ {
+ case CACHE_OP_WB:
+ {
+ dc_ops("cvac", start_addr);
+ break;
+ }
+
+ case CACHE_OP_INVD:
+ {
+ dc_ops("ivac", start_addr);
+ break;
+ }
+
+ case CACHE_OP_WB_INVD:
+ {
+ dc_ops("civac", start_addr);
+ break;
+ }
Review Comment:
add 2 spaces and maybe `default`
##########
arch/arm64/src/common/arm64_fatal.c:
##########
@@ -0,0 +1,360 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <debug.h>
+#include <assert.h>
+#include <sched.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/tls.h>
+#include <nuttx/board.h>
+#include <arch/chip/chip.h>
+#include <nuttx/syslog/syslog.h>
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+#include "arm64_fatal.h"
+#include "arm64_arch_timer.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: print_ec_cause
+ ****************************************************************************/
+
+static void print_ec_cause(uint64_t esr)
+{
+ uint32_t ec = (uint32_t)esr >> 26;
+
+ switch (ec)
+ {
+ case 0b000000:
+ {
+ sinfo("Unknown reason\n");
+ break;
+ }
+
+ case 0b000001:
+ {
+ sinfo("Trapped WFI or WFE instruction execution\n");
+ break;
+ }
+
+ case 0b000011:
+ {
+ sinfo(
+ "Trapped MCR or MRC access with (coproc==0b1111) that "
+ "is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000100:
+ {
+ sinfo(
+ "Trapped MCRR or MRRC access with (coproc==0b1111) "
+ "that is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000101:
+ {
+ sinfo("Trapped MCR or MRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b000110:
+ {
+ sinfo("Trapped LDC or STC access\n");
+ break;
+ }
+
+ case 0b000111:
+ {
+ sinfo(
+ "Trapped access to SVE, Advanced SIMD, or "
+ "floating-point functionality\n");
+ break;
+ }
+
+ case 0b001100:
+ {
+ sinfo("Trapped MRRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b001101:
+ {
+ sinfo("Branch Target Exception\n");
+ break;
+ }
+
+ case 0b001110:
+ {
+ sinfo("Illegal Execution state\n");
+ break;
+ }
+
+ case 0b010001:
+ {
+ sinfo("SVC instruction execution in AArch32 state\n");
+ break;
+ }
+
+ case 0b011000:
+ {
+ sinfo(
+ "Trapped MSR, MRS or System instruction execution in "
+ "AArch64 state, that is not reported using EC "
+ "0b000000, 0b000001 or 0b000111\n");
+ break;
+ }
+
+ case 0b011001:
+ {
+ sinfo("Trapped access to SVE functionality\n");
+ break;
+ }
+
+ case 0b100000:
+ {
+ sinfo(
+ "Instruction Abort from a lower Exception level, that "
+ "might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b100001:
+ {
+ sinfo(
+ "Instruction Abort taken without a change in Exception level.\n");
+ break;
+ }
+
+ case 0b100010:
+ {
+ sinfo("PC alignment fault exception.\n");
+ break;
+ }
+
+ case 0b100100:
+ {
+ sinfo(
+ "Data Abort from a lower Exception level, that might "
+ "be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b100101:
+ {
+ sinfo("Data Abort taken without a change in Exception level\n");
+ break;
+ }
+
+ case 0b100110:
+ {
+ sinfo("SP alignment fault exception\n");
+ break;
+ }
+
+ case 0b101000:
+ {
+ sinfo("Trapped floating-point exception taken from AArch32 state\n");
+ break;
+ }
+
+ case 0b101100:
+ {
+ sinfo("Trapped floating-point exception taken from AArch64 state.\n");
+ break;
+ }
+
+ case 0b101111:
+ {
+ sinfo("SError interrupt\n");
+ break;
+ }
+
+ case 0b110000:
+ {
+ sinfo(
+ "Breakpoint exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110001:
+ {
+ sinfo(
+ "Breakpoint exception taken without a change in "
+ "Exception level\n");
+ break;
+ }
+
+ case 0b110010:
+ {
+ sinfo(
+ "Software Step exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110011:
+ {
+ sinfo(
+ "Software Step exception taken without a change in "
+ "Exception level\n");
+ break;
+ }
+
+ case 0b110100:
+ {
+ sinfo(
+ "Watchpoint exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110101:
+ {
+ sinfo(
+ "Watchpoint exception taken without a change in "
+ "Exception level.\n");
+ break;
+ }
+
+ case 0b111000:
+ {
+ sinfo("BKPT instruction execution in AArch32 state\n");
+ break;
+ }
+
+ case 0b111100:
+ {
+ sinfo("BRK instruction execution in AArch64 state.\n");
+ break;
+ }
+
+ default:
+ break;
+ }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_fatal_error
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void arm64_fatal_error(unsigned int reason, struct regs_context * reg)
+{
+ uint64_t el, esr, elr, far;
+ int cpu = up_cpu_index();
+
+ sinfo("reason = %d\n", reason);
+ sinfo("arm64_fatal_error: CPU%d task: %s\n", cpu, running_task()->name);
+
+ if (reason != K_ERR_SPURIOUS_IRQ)
+ {
+ __asm__ volatile ("mrs %0, CurrentEL" : "=r" (el));
+
+ switch (GET_EL(el))
+ {
+ case MODE_EL1:
+ {
+ sinfo("CurrentEL: MODE_EL1\n");
+ __asm__ volatile ("mrs %0, esr_el1" : "=r" (esr));
+ __asm__ volatile ("mrs %0, far_el1" : "=r" (far));
+ __asm__ volatile ("mrs %0, elr_el1" : "=r" (elr));
+ break;
+ }
+
+ case MODE_EL2:
+ {
+ sinfo("CurrentEL: MODE_EL2\n");
+ __asm__ volatile ("mrs %0, esr_el2" : "=r" (esr));
+ __asm__ volatile ("mrs %0, far_el2" : "=r" (far));
+ __asm__ volatile ("mrs %0, elr_el2" : "=r" (elr));
+ break;
+ }
+
+ case MODE_EL3:
+ {
+ sinfo("CurrentEL: MODE_EL3\n");
+ __asm__ volatile ("mrs %0, esr_el3" : "=r" (esr));
+ __asm__ volatile ("mrs %0, far_el3" : "=r" (far));
+ __asm__ volatile ("mrs %0, elr_el3" : "=r" (elr));
+ break;
+ }
+
+ default:
+ {
+ sinfo("CurrentEL: unknown\n");
Review Comment:
Add 2 spaces fro `case` scope
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
Review Comment:
```suggestion
# include <stdint.h>
```
##########
arch/arm64/src/common/addrenv.h:
##########
@@ -0,0 +1,105 @@
+/****************************************************************************
+ * arch/arm64/src/common/addrenv.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ADDRENV_H
+#define __ARCH_ARM64_SRC_COMMON_ADDRENV_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include "arm64_internal.h"
+
+#ifdef CONFIG_ARCH_ADDRENV
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Aligned size of the kernel stack */
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+# define ARCH_KERNEL_STACKSIZE STACK_ALIGN_UP(CONFIG_ARCH_KERNEL_STACKSIZE)
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_addrenv_create_region
+ *
+ * Description:
+ * Create one memory region.
+ *
+ * Returned Value:
+ * On success, the number of pages allocated is returned. Otherwise, a
+ * negated errno value is returned.
+ *
+ ****************************************************************************/
+
+int arm64_addrenv_create_region(uintptr_t **list, size_t listlen,
+ uintptr_t vaddr, size_t regionsize,
+ uint32_t mmuflags);
+
+/****************************************************************************
+ * Name: arm_addrenv_destroy_region
+ *
+ * Description:
+ * Destroy one memory region.
+ *
+ ****************************************************************************/
+
+void arm64_addrenv_destroy_region(uintptr_t **list, size_tt listlen,
Review Comment:
```suggestion
void arm64_addrenv_destroy_region(uintptr_t **list, size_t listlen,
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#define BIT(n) (1UL << (n))
+#define BIT64(_n) (1ULL << (_n))
Review Comment:
```suggestion
#define BIT64(n) (1ULL << (n))
```
or even
```suggestion
#define BIT64(n) (UINT64_C(1) << (n))
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#define BIT(n) (1UL << (n))
+#define BIT64(_n) (1ULL << (_n))
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+#define DAIFSET_FIQ_BIT BIT(0)
+#define DAIFSET_IRQ_BIT BIT(1)
+#define DAIFSET_ABT_BIT BIT(2)
+#define DAIFSET_DBG_BIT BIT(3)
+
+#define DAIFCLR_FIQ_BIT BIT(0)
+#define DAIFCLR_IRQ_BIT BIT(1)
+#define DAIFCLR_ABT_BIT BIT(2)
+#define DAIFCLR_DBG_BIT BIT(3)
+
+#define DAIF_FIQ_BIT BIT(6)
+#define DAIF_IRQ_BIT BIT(7)
+#define DAIF_ABT_BIT BIT(8)
+#define DAIF_DBG_BIT BIT(9)
+
+#define DAIF_MASK (0xf << 6)
+
+/* SPSR M[3:0] define
+ *
+ * Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ * SPSR_EL1: Saved Program Status Register (EL1)
+ * SPSR_EL2: Saved Program Status Register (EL2)
+ * SPSR_EL3: Saved Program Status Register (EL3)
+ *
+ * reference to Programmer’s Guide for ARMv8-A
+ * (ARM DEN0024A, ID050815 ), 4.1.2 Stack pointer
+ *
+ * The T suffix, indicates use of the SP_EL0 stack pointer.
+ * The H suffix, indicates use of the SP_ELx stack pointer.
+ *
+ */
+
+#define SPSR_DAIF_SHIFT (6)
+#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE_EL0T (0x0)
+#define SPSR_MODE_EL1T (0x4)
+#define SPSR_MODE_EL1H (0x5)
+#define SPSR_MODE_EL2T (0x8)
+#define SPSR_MODE_EL2H (0x9)
+#define SPSR_MODE_MASK (0xf)
+
+/* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ *
+ * SCTLR_EL1: System Control Register (EL1)
+ * SCTLR_EL2: System Control Register (EL2)
+ * SCTLR_EL3: System Control Register (EL3)
+ *
+ */
+
+#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(20) | BIT(11))
+
+#define SCTLR_M_BIT BIT(0)
+#define SCTLR_A_BIT BIT(1)
+#define SCTLR_C_BIT BIT(2)
+#define SCTLR_SA_BIT BIT(3)
+#define SCTLR_I_BIT BIT(12)
+
+/* CurrentEL: Current Exception Level */
+
+#define MODE_EL_SHIFT (0x2)
+#define MODE_EL_MASK (0x3)
+
+#define MODE_EL3 (0x3)
+#define MODE_EL2 (0x2)
+#define MODE_EL1 (0x1)
+#define MODE_EL0 (0x0)
+
+#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
Review Comment:
optional
```suggestion
#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
Review Comment:
```suggestion
# define MAX(a, b) (((a) > (b)) ? (a) : (b))
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
Review Comment:
`GB` is `10 + 10 +10 == 30` bits shift, but only 2 bits left for value. Maybe can be converted to `uul` or use `UINT64_C` at least for `GB`?
##########
arch/arm64/src/common/arm64_assert.c:
##########
@@ -0,0 +1,582 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_assert.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/board.h>
+#include <nuttx/syslog/syslog.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* USB trace dumping */
+
+#ifndef CONFIG_USBDEV_TRACE
+# undef CONFIG_ARCH_USBDUMP
+#endif
+
+#ifndef CONFIG_BOARD_RESET_ON_ASSERT
+# define CONFIG_BOARD_RESET_ON_ASSERT 0
+#endif
+
+/****************************************************************************
+ * Name: arm_registerdump
+ ****************************************************************************/
+
+static void arm64_registerdump(struct regs_context * regs)
+{
+ _alert("stack = %p\n", regs);
+ _alert("x0: 0x%-16"PRIx64" x1: 0x%"PRIx64"\n",
+ regs->regs[REG_X0], regs->regs[REG_X1]);
+ _alert("x2: 0x%-16"PRIx64" x3: 0x%"PRIx64"\n",
+ regs->regs[REG_X2], regs->regs[REG_X3]);
+ _alert("x4: 0x%-16"PRIx64" x5: 0x%"PRIx64"\n",
+ regs->regs[REG_X4], regs->regs[REG_X5]);
+ _alert("x6: 0x%-16"PRIx64" x7: 0x%"PRIx64"\n",
+ regs->regs[REG_X6], regs->regs[REG_X7]);
+ _alert("x8: 0x%-16"PRIx64" x9: 0x%"PRIx64"\n",
+ regs->regs[REG_X8], regs->regs[REG_X9]);
+ _alert("x10: 0x%-16"PRIx64" x11: 0x%"PRIx64"\n",
+ regs->regs[REG_X10], regs->regs[REG_X11]);
+ _alert("x12: 0x%-16"PRIx64" x13: 0x%"PRIx64"\n",
+ regs->regs[REG_X12], regs->regs[REG_X13]);
+ _alert("x14: 0x%-16"PRIx64" x15: 0x%"PRIx64"\n",
+ regs->regs[REG_X14], regs->regs[REG_X15]);
+ _alert("x16: 0x%-16"PRIx64" x17: 0x%"PRIx64"\n",
+ regs->regs[REG_X16], regs->regs[REG_X17]);
+ _alert("x18: 0x%-16"PRIx64" x19: 0x%"PRIx64"\n",
+ regs->regs[REG_X18], regs->regs[REG_X19]);
+ _alert("x20: 0x%-16"PRIx64" x21: 0x%"PRIx64"\n",
+ regs->regs[REG_X20], regs->regs[REG_X21]);
+ _alert("x22: 0x%-16"PRIx64" x23: 0x%"PRIx64"\n",
+ regs->regs[REG_X22], regs->regs[REG_X23]);
+ _alert("x24: 0x%-16"PRIx64" x25: 0x%"PRIx64"\n",
+ regs->regs[REG_X24], regs->regs[REG_X25]);
+ _alert("x26: 0x%-16"PRIx64" x27: 0x%"PRIx64"\n",
+ regs->regs[REG_X26], regs->regs[REG_X27]);
+ _alert("x28: 0x%-16"PRIx64" x29: 0x%"PRIx64"\n",
+ regs->regs[REG_X28], regs->regs[REG_X29]);
+ _alert("x30: 0x%-16"PRIx64"\n", regs->regs[REG_X30]);
+
+ _alert("\n");
+ _alert("STATUS Registers:\n");
+ _alert("SPSR: 0x%-16"PRIx64"\n", regs->spsr);
+ _alert("ELR: 0x%-16"PRIx64"\n", regs->elr);
+ _alert("SP_EL0: 0x%-16"PRIx64"\n", regs->sp_el0);
+ _alert("SP_ELX: 0x%-16"PRIx64"\n", regs->sp_elx);
+ _alert("TPIDR_EL0: 0x%-16"PRIx64"\n", regs->tpidr_el0);
+ _alert("TPIDR_EL1: 0x%-16"PRIx64"\n", regs->tpidr_el1);
+ _alert("EXE_DEPTH: 0x%-16"PRIx64"\n", regs->exe_depth);
+}
+
+#ifdef CONFIG_ARCH_STACKDUMP
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_stackdump
+ ****************************************************************************/
+
+static void arm64_stackdump(uint64_t sp, uint64_t stack_top)
+{
+ uint64_t stack;
+
+ /* Flush any buffered SYSLOG data to avoid overwrite */
+
+ syslog_flush();
+
+ for (stack = sp & ~0x1f; stack < (stack_top & ~0x1f); stack += 64)
+ {
+ uint64_t *ptr = (uint64_t *)stack;
+ _alert("%08" PRIx64 ": %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 " %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 "\n",
+ stack, ptr[0], ptr[1], ptr[2], ptr[3],
+ ptr[4], ptr[5], ptr[6], ptr[7]);
+ }
+}
+
+/****************************************************************************
+ * Name: arm_dump_task
+ ****************************************************************************/
+
+static void arm64_dump_task(struct tcb_s *tcb, void *arg)
+{
+ char args[64] = "";
+#ifdef CONFIG_STACK_COLORATION
+ uint64_t stack_filled = 0;
+ uint64_t stack_used;
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ struct cpuload_s cpuload;
+ uint64_t fracpart;
+ uint64_t intpart;
+ uint64_t tmp;
+
+ clock_cpuload(tcb->pid, &cpuload);
+
+ if (cpuload.total > 0)
+ {
+ tmp = (1000 * cpuload.active) / cpuload.total;
+ intpart = tmp / 10;
+ fracpart = tmp - 10 * intpart;
+ }
+ else
+ {
+ intpart = 0;
+ fracpart = 0;
+ }
+#endif
+
+#ifdef CONFIG_STACK_COLORATION
+ stack_used = up_check_tcbstack(tcb);
+ if (tcb->adj_stack_size > 0 && stack_used > 0)
+ {
+ /* Use fixed-point math with one decimal place */
+
+ stack_filled = 10 * 100 * stack_used / tcb->adj_stack_size;
+ }
+#endif
+
+#ifndef CONFIG_DISABLE_PTHREAD
+ if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD)
+ {
+ struct pthread_tcb_s *ptcb = (struct pthread_tcb_s *)tcb;
+
+ snprintf(args, sizeof(args), "%p ", ptcb->arg);
+ }
+ else
+#endif
+ {
+ FAR char **argv = tcb->group->tg_info->argv + 1;
Review Comment:
```suggestion
char **argv = tcb->group->tg_info->argv + 1;
```
##########
arch/arm64/src/common/arm64_cache.c:
##########
@@ -0,0 +1,449 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cache.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* Common operations for the caches
+ *
+ * WB means write-back and intends to transfer dirty cache lines to memory in
+ * a copy-back cache policy. May be a no-op in write-back cache policy.
+ *
+ * INVD means invalidate and will mark cache lines as not valid. A future
+ * access to the associated address is guaranteed to generate a memory fetch.
+ *
+ * armv8 data cache instruction:
+ *
+ * DC CIVAC (WB+INVD):
+ * Data or unified Cache line Clean and Invalidate by VA to PoC
+ * Clean and Invalidate data cache by address to Point of Coherency.
+ *
+ * DC CVAC (WB):
+ * Data or unified Cache line Clean by VA to PoC
+ * Clean data cache by address to Point of Coherency.
+ *
+ * DC IVAC (INVD):
+ * Data or unified Cache line Invalidate by VA to PoC
+ * Invalidate data cache by address to Point of Coherency
+ */
+
+#define CACHE_OP_WB BIT(0)
+#define CACHE_OP_INVD BIT(1)
+#define CACHE_OP_WB_INVD (CACHE_OP_WB | CACHE_OP_INVD)
+
+#define LINE_MASK(line) ((line) - 1)
+#define LINE_ALIGN_DOWN(a, line) ((a) & ~LINE_MASK(line))
+#define LINE_ALIGN_UP(a, line) \
+ (((a) + LINE_MASK(line)) & ~LINE_MASK(line))
+
+#define dc_ops(op, val) \
+ ({ \
+ __asm__ volatile ("dc " op ", %0" : : "r" (val) : "memory"); \
+ })
+
+/* IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
+ * Purpose
+ * Invalidate all instruction caches in the Inner Shareable domain of
+ * the PE executing the instruction to the Point of Unification.
+ */
+
+static inline void __ic_iallu(void)
+{
+ __asm__ volatile ("ic iallu" : : : "memory");
+}
+
+/* IC IALLU, Instruction Cache Invalidate All to PoU
+ * Purpose
+ * Invalidate all instruction caches of the PE executing
+ * the instruction to the Point of Unification.
+ */
+
+static inline void __ic_ialluis(void)
+{
+ __asm__ volatile ("ic ialluis" : : : "memory");
+}
+
+size_t dcache_line_size;
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* operation for data cache by virtual address to PoC */
+
+static inline int arm64_dcache_range(uintptr_t start_addr,
+ uintptr_t end_addr, int op)
Review Comment:
```suggestion
uintptr_t end_addr, int op)
```
##########
arch/arm64/src/common/arm64_assert.c:
##########
@@ -0,0 +1,582 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_assert.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/board.h>
+#include <nuttx/syslog/syslog.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* USB trace dumping */
+
+#ifndef CONFIG_USBDEV_TRACE
+# undef CONFIG_ARCH_USBDUMP
+#endif
+
+#ifndef CONFIG_BOARD_RESET_ON_ASSERT
+# define CONFIG_BOARD_RESET_ON_ASSERT 0
+#endif
+
+/****************************************************************************
+ * Name: arm_registerdump
+ ****************************************************************************/
+
+static void arm64_registerdump(struct regs_context * regs)
+{
+ _alert("stack = %p\n", regs);
+ _alert("x0: 0x%-16"PRIx64" x1: 0x%"PRIx64"\n",
+ regs->regs[REG_X0], regs->regs[REG_X1]);
+ _alert("x2: 0x%-16"PRIx64" x3: 0x%"PRIx64"\n",
+ regs->regs[REG_X2], regs->regs[REG_X3]);
+ _alert("x4: 0x%-16"PRIx64" x5: 0x%"PRIx64"\n",
+ regs->regs[REG_X4], regs->regs[REG_X5]);
+ _alert("x6: 0x%-16"PRIx64" x7: 0x%"PRIx64"\n",
+ regs->regs[REG_X6], regs->regs[REG_X7]);
+ _alert("x8: 0x%-16"PRIx64" x9: 0x%"PRIx64"\n",
+ regs->regs[REG_X8], regs->regs[REG_X9]);
+ _alert("x10: 0x%-16"PRIx64" x11: 0x%"PRIx64"\n",
+ regs->regs[REG_X10], regs->regs[REG_X11]);
+ _alert("x12: 0x%-16"PRIx64" x13: 0x%"PRIx64"\n",
+ regs->regs[REG_X12], regs->regs[REG_X13]);
+ _alert("x14: 0x%-16"PRIx64" x15: 0x%"PRIx64"\n",
+ regs->regs[REG_X14], regs->regs[REG_X15]);
+ _alert("x16: 0x%-16"PRIx64" x17: 0x%"PRIx64"\n",
+ regs->regs[REG_X16], regs->regs[REG_X17]);
+ _alert("x18: 0x%-16"PRIx64" x19: 0x%"PRIx64"\n",
+ regs->regs[REG_X18], regs->regs[REG_X19]);
+ _alert("x20: 0x%-16"PRIx64" x21: 0x%"PRIx64"\n",
+ regs->regs[REG_X20], regs->regs[REG_X21]);
+ _alert("x22: 0x%-16"PRIx64" x23: 0x%"PRIx64"\n",
+ regs->regs[REG_X22], regs->regs[REG_X23]);
+ _alert("x24: 0x%-16"PRIx64" x25: 0x%"PRIx64"\n",
+ regs->regs[REG_X24], regs->regs[REG_X25]);
+ _alert("x26: 0x%-16"PRIx64" x27: 0x%"PRIx64"\n",
+ regs->regs[REG_X26], regs->regs[REG_X27]);
+ _alert("x28: 0x%-16"PRIx64" x29: 0x%"PRIx64"\n",
+ regs->regs[REG_X28], regs->regs[REG_X29]);
+ _alert("x30: 0x%-16"PRIx64"\n", regs->regs[REG_X30]);
+
+ _alert("\n");
+ _alert("STATUS Registers:\n");
+ _alert("SPSR: 0x%-16"PRIx64"\n", regs->spsr);
+ _alert("ELR: 0x%-16"PRIx64"\n", regs->elr);
+ _alert("SP_EL0: 0x%-16"PRIx64"\n", regs->sp_el0);
+ _alert("SP_ELX: 0x%-16"PRIx64"\n", regs->sp_elx);
+ _alert("TPIDR_EL0: 0x%-16"PRIx64"\n", regs->tpidr_el0);
+ _alert("TPIDR_EL1: 0x%-16"PRIx64"\n", regs->tpidr_el1);
+ _alert("EXE_DEPTH: 0x%-16"PRIx64"\n", regs->exe_depth);
+}
+
+#ifdef CONFIG_ARCH_STACKDUMP
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_stackdump
+ ****************************************************************************/
+
+static void arm64_stackdump(uint64_t sp, uint64_t stack_top)
+{
+ uint64_t stack;
+
+ /* Flush any buffered SYSLOG data to avoid overwrite */
+
+ syslog_flush();
+
+ for (stack = sp & ~0x1f; stack < (stack_top & ~0x1f); stack += 64)
+ {
+ uint64_t *ptr = (uint64_t *)stack;
+ _alert("%08" PRIx64 ": %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 " %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 "\n",
+ stack, ptr[0], ptr[1], ptr[2], ptr[3],
+ ptr[4], ptr[5], ptr[6], ptr[7]);
+ }
+}
+
+/****************************************************************************
+ * Name: arm_dump_task
+ ****************************************************************************/
+
+static void arm64_dump_task(struct tcb_s *tcb, void *arg)
+{
+ char args[64] = "";
+#ifdef CONFIG_STACK_COLORATION
+ uint64_t stack_filled = 0;
+ uint64_t stack_used;
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ struct cpuload_s cpuload;
+ uint64_t fracpart;
+ uint64_t intpart;
+ uint64_t tmp;
+
+ clock_cpuload(tcb->pid, &cpuload);
+
+ if (cpuload.total > 0)
+ {
+ tmp = (1000 * cpuload.active) / cpuload.total;
+ intpart = tmp / 10;
+ fracpart = tmp - 10 * intpart;
+ }
+ else
+ {
+ intpart = 0;
+ fracpart = 0;
+ }
+#endif
+
+#ifdef CONFIG_STACK_COLORATION
+ stack_used = up_check_tcbstack(tcb);
+ if (tcb->adj_stack_size > 0 && stack_used > 0)
+ {
+ /* Use fixed-point math with one decimal place */
+
+ stack_filled = 10 * 100 * stack_used / tcb->adj_stack_size;
+ }
+#endif
+
+#ifndef CONFIG_DISABLE_PTHREAD
+ if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD)
+ {
+ struct pthread_tcb_s *ptcb = (struct pthread_tcb_s *)tcb;
+
+ snprintf(args, sizeof(args), "%p ", ptcb->arg);
+ }
+ else
+#endif
+ {
+ FAR char **argv = tcb->group->tg_info->argv + 1;
+ size_t npos = 0;
+
+ while (*argv != NULL && npos < sizeof(args))
+ {
+ npos += snprintf(args + npos, sizeof(args) - npos, " %s", *argv++);
+ }
+ }
+
+ /* Dump interesting properties of this task */
+
+ _alert(" %4d %4d"
+#ifdef CONFIG_SMP
+ " %4d"
+#endif
+#ifdef CONFIG_STACK_COLORATION
+ " %7lu"
+#endif
+ " %7lu"
+#ifdef CONFIG_STACK_COLORATION
+ " %3" PRId64 ".%1" PRId64 "%%%c"
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ " %3" PRId64 ".%01" PRId64 "%%"
+#endif
+#if CONFIG_TASK_NAME_SIZE > 0
+ " %s %s\n",
+#else
+ " %s\n",
+#endif
+ tcb->pid, tcb->sched_priority,
+#ifdef CONFIG_SMP
+ tcb->cpu,
+#endif
+#ifdef CONFIG_STACK_COLORATION
+ (unsigned long)up_check_tcbstack(tcb),
+#endif
+ (unsigned long)tcb->adj_stack_size
+#ifdef CONFIG_STACK_COLORATION
+ , stack_filled / 10, stack_filled % 10,
+ (stack_filled >= 10 * 80 ? '!' : ' ')
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ , intpart, fracpart
+#endif
+#if CONFIG_TASK_NAME_SIZE > 0
Review Comment:
Please sync this file with ARM 32 version. It has been reworked a bit.
##########
arch/arm64/src/common/arm64_boot.c:
##########
@@ -0,0 +1,185 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/init.h>
+
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+
+extern void *_vector_table[];
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_boot_el3_init(void)
+{
+ uint64_t reg;
+
+ /* Setup vector table */
+
+ write_sysreg((uint64_t)_vector_table, vbar_el3);
+ __ISB();
+
+ reg = 0U; /* Mostly RES0 */
+ reg &= ~(CPTR_TTA_BIT | /* Do not trap sysreg accesses */
+ CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
+ CPTR_TCPAC_BIT); /* Do not trap CPTR_EL2 / CPACR_EL1 accesses
+ */
+
+ /* CPTR_EL3, Architectural Feature Trap Register (EL3) */
+
+ write_sysreg(reg, cptr_el3);
+
+ reg = 0U; /* Reset */
+ reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */
+ reg |= (SCR_RES1 | /* RES1 */
+ SCR_RW_BIT | /* EL2 execution state is AArch64 */
+ SCR_ST_BIT | /* Do not trap EL1 accesses to timer */
+ SCR_HCE_BIT | /* Do not trap HVC */
+ SCR_SMD_BIT); /* Do not trap SMC */
+ write_sysreg(reg, scr_el3);
+
+ reg = read_sysreg(ICC_SRE_EL3);
+ reg |= (ICC_SRE_ELX_DFB_BIT | /* Disable FIQ bypass */
+ ICC_SRE_ELX_DIB_BIT | /* Disable IRQ bypass */
+ ICC_SRE_ELX_SRE_BIT | /* System register interface is used */
+ ICC_SRE_EL3_EN_BIT); /* Enables lower Exception level access to
+ * ICC_SRE_EL1 */
+ write_sysreg(reg, ICC_SRE_EL3);
+
+ __ISB();
+}
+
+void arm64_boot_el3_get_next_el(uint64_t switch_addr)
+{
+ uint64_t spsr;
+
+ write_sysreg(switch_addr, elr_el3);
+
+ /* Mask the DAIF */
+
+ spsr = SPSR_DAIF_MASK;
+ spsr |= SPSR_MODE_EL2T;
+
+ write_sysreg(spsr, spsr_el3);
+}
+
+void arm64_boot_el2_init(void)
+{
+ uint64_t reg;
+
+ reg = read_sysreg(sctlr_el2);
+ reg |= (SCTLR_EL2_RES1 | /* RES1 */
+ SCTLR_I_BIT | /* Enable i-cache */
+ SCTLR_SA_BIT); /* Enable SP alignment check */
+ write_sysreg(reg, sctlr_el2);
+
+ reg = read_sysreg(hcr_el2);
+ reg |= HCR_RW_BIT; /* EL1 Execution state is AArch64 */
+ write_sysreg(reg, hcr_el2);
+
+ reg = 0U; /* RES0 */
+ reg |= CPTR_EL2_RES1; /* RES1 */
+ reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
+ CPTR_TCPAC_BIT); /* Do not trap CPACR_EL1 accesses */
+ write_sysreg(reg, cptr_el2);
+
+ /* Enable EL1 access to timers */
+
+ reg = read_sysreg(cnthctl_el2);
+ reg |= (CNTHCTL_EL2_EL1PCEN_EN | CNTHCTL_EL2_EL1PCTEN_EN);
+ write_sysreg(reg, cnthctl_el2);
+
+ zero_sysreg(cntvoff_el2); /* Set 64-bit virtual timer offset to 0 */
+
+#ifdef CONFIG_ARCH_ARMV8R
+ zero_sysreg(cnthps_ctl_el2);
+#else
+ zero_sysreg(cnthp_ctl_el2);
+#endif
+
+ /* Enable this if/when we use the hypervisor timer.
+ * write_cnthp_cval_el2(~(uint64_t)0);
+ */
+
+ __ISB();
+}
+
+void arm64_boot_el1_init(void)
+{
+ uint64_t reg;
+
+ /* Setup vector table */
+
+ write_sysreg((uint64_t)_vector_table, vbar_el1);
+ __ISB();
+
+ reg = 0U; /* RES0 */
+ reg |= CPACR_EL1_FPEN_NOTRAP; /* Do not trap NEON/SIMD/FP initially */
+
+ /* TODO: CONFIG_FLOAT_*_FORBIDDEN */
+
+ write_sysreg(reg, cpacr_el1);
+
+ reg = read_sysreg(sctlr_el1);
+ reg |= (SCTLR_EL1_RES1 | /* RES1 */
+ SCTLR_I_BIT | /* Enable i-cache */
+ SCTLR_SA_BIT); /* Enable SP alignment check */
+ write_sysreg(reg, sctlr_el1);
+
+ write_sysreg((~(uint64_t)0), cntv_cval_el0);
+
+ /* Enable these if/when we use the corresponding timers.
+ * write_cntp_cval_el0(~(uint64_t)0);
+ * write_cntps_cval_el1(~(uint64_t)0);
+ */
+
+ __ISB();
+}
+
+/* These simple memset alternatives are necessary
+ * as the function at libc is depend on the MMU
+ * to be active.
+ */
+
+static void boot_early_memset(void *dst, int c, size_t n)
+{
+ uint8_t *d = dst;
+
+ while (n--)
+ {
+ *d++ = c;
+ }
+}
+
+void arm64_boot_primary_c_routine(void)
+{
+ boot_early_memset(_sbss, 0, _ebss - _sbss);
Review Comment:
Can we clear with 64bits loop?
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
+
+ /* for statistic propose */
+
+ int save_count;
+ int restore_count;
+ int switch_count;
+ int exe_depth_count;
+};
+
+static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/***************************************************************************
+ * Public Functions
+ ***************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb)
+{
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ memset(&g_cpu_fpu_ctx[this_cpu()], 0,
+ sizeof(struct arm64_cpu_fpu_context));
+ g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb;
+
+ tcb->xcp.fpu_regs = &g_idle_thread_fpu[this_cpu()];
+ }
+
+ memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg));
+ tcb->xcp.fpu_regs->fpu_trap = 0;
+}
+
+void arm64_destory_fpu(struct tcb_s * tcb)
+{
+ struct tcb_s * owner;
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner == tcb)
+ {
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+}
+
+/* enable FPU access trap */
+
+static void arm64_fpu_access_trap_enable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+ cpacr &= ~CPACR_EL1_FPEN_NOTRAP;
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/* disable FPU access trap */
+
+static void arm64_fpu_access_trap_disable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+
+ cpacr |= CPACR_EL1_FPEN_NOTRAP;
+
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/***************************************************************************
+ * Name: arm64_fpu_enter_exception
+ *
+ * Description:
+ * called at every time get into a exception
+ *
+ ***************************************************************************/
+
+void arm64_fpu_enter_exception(void)
+{
+}
+
+void arm64_fpu_exit_exception(void)
+{
+}
+
+void arm64_fpu_trap(struct esf_reg * regs)
+{
+ struct tcb_s * owner;
+
+ /* disable fpu trap access */
+
+ arm64_fpu_access_trap_disable();
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner != NULL)
+ {
+ arm64_fpu_save(owner->xcp.fpu_regs);
+ __DSB();
+ g_cpu_fpu_ctx[this_cpu()].save_count++;
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+
+ if (arch_get_exception_depth() > 1)
+ {
+ /* if get_exception_depth > 1
+ * it means FPU access exception occurred in exception context
+ * switch FPU owner to idle thread
+ */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].idle_thread;
+ }
+ else
+ {
+ owner = (struct tcb_s *)arch_get_current_tcb();
+ }
+
+ /* restore our context */
+
+ arm64_fpu_restore(owner->xcp.fpu_regs);
+ g_cpu_fpu_ctx[this_cpu()].restore_count++;
+
+ /* become new owner */
+
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = owner;
+ owner->xcp.fpu_regs->fpu_trap = 1;
+}
+
+void arm64_fpu_context_restore(void)
+{
+ struct tcb_s *new_tcb = (struct tcb_s *)arch_get_current_tcb();
+
+ arm64_fpu_access_trap_enable();
+
+ if (new_tcb->xcp.fpu_regs->fpu_trap == 0)
+ {
+ /* FPU trap hasn't happened at this task */
+
+ arm64_fpu_access_trap_enable();
+ }
+ else
+ {
+ /* FPU trap has happened at this task */
+
+ if (new_tcb == g_cpu_fpu_ctx[this_cpu()].fpu_owner)
+ {
+ arm64_fpu_access_trap_disable();
+ }
+ else
+ {
+ arm64_fpu_access_trap_enable();
+ }
+ }
+
+ g_cpu_fpu_ctx[this_cpu()].switch_count++;
+}
+
+void arm64_fpu_enable(void)
+{
+ irqstate_t flags = up_irq_save();
+
+ arm64_fpu_access_trap_enable();
+ up_irq_restore(flags);
+}
+
+void arm64_fpu_disable(void)
+{
+ irqstate_t flags = up_irq_save();
+
+ arm64_fpu_access_trap_disable();
+ up_irq_restore(flags);
+}
+
+/***************************************************************************
+ * Name: up_fpucmp
+ *
+ * Description:
+ * compare FPU areas from thread context
+ *
+ ***************************************************************************/
+
+bool up_fpucmp(const void *saveregs1, const void *saveregs2)
+{
+ const uint64_t *regs1 = saveregs1 + XCPTCONTEXT_GP_SIZE;
+ const uint64_t *regs2 = saveregs2 + XCPTCONTEXT_GP_SIZE;
Review Comment:
```suggestion
const uint64_t *regs1 = saveregs1 + XCPTCONTEXT_GP_SIZE;
const uint64_t *regs2 = saveregs2 + XCPTCONTEXT_GP_SIZE;
```
##########
arch/arm64/src/common/arm64_fatal.h:
##########
@@ -0,0 +1,77 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
+
+/**
+ * @defgroup fatal_apis Fatal error APIs
+ * @ingroup kernel_apis
+ * @{
+ */
+
+#define K_ERR_CPU_EXCEPTION (0)
+#define K_ERR_CPU_MODE32 (1)
+#define K_ERR_SPURIOUS_IRQ (2)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
Review Comment:
`#include <stdbool.h>`
##########
arch/arm64/src/common/arm64_cache.c:
##########
@@ -0,0 +1,449 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cache.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* Common operations for the caches
+ *
+ * WB means write-back and intends to transfer dirty cache lines to memory in
+ * a copy-back cache policy. May be a no-op in write-back cache policy.
+ *
+ * INVD means invalidate and will mark cache lines as not valid. A future
+ * access to the associated address is guaranteed to generate a memory fetch.
+ *
+ * armv8 data cache instruction:
+ *
+ * DC CIVAC (WB+INVD):
+ * Data or unified Cache line Clean and Invalidate by VA to PoC
+ * Clean and Invalidate data cache by address to Point of Coherency.
+ *
+ * DC CVAC (WB):
+ * Data or unified Cache line Clean by VA to PoC
+ * Clean data cache by address to Point of Coherency.
+ *
+ * DC IVAC (INVD):
+ * Data or unified Cache line Invalidate by VA to PoC
+ * Invalidate data cache by address to Point of Coherency
+ */
+
+#define CACHE_OP_WB BIT(0)
+#define CACHE_OP_INVD BIT(1)
+#define CACHE_OP_WB_INVD (CACHE_OP_WB | CACHE_OP_INVD)
+
+#define LINE_MASK(line) ((line) - 1)
+#define LINE_ALIGN_DOWN(a, line) ((a) & ~LINE_MASK(line))
+#define LINE_ALIGN_UP(a, line) \
+ (((a) + LINE_MASK(line)) & ~LINE_MASK(line))
+
+#define dc_ops(op, val) \
+ ({ \
+ __asm__ volatile ("dc " op ", %0" : : "r" (val) : "memory"); \
+ })
+
+/* IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
+ * Purpose
+ * Invalidate all instruction caches in the Inner Shareable domain of
+ * the PE executing the instruction to the Point of Unification.
+ */
+
+static inline void __ic_iallu(void)
+{
+ __asm__ volatile ("ic iallu" : : : "memory");
+}
+
+/* IC IALLU, Instruction Cache Invalidate All to PoU
+ * Purpose
+ * Invalidate all instruction caches of the PE executing
+ * the instruction to the Point of Unification.
+ */
+
+static inline void __ic_ialluis(void)
+{
+ __asm__ volatile ("ic ialluis" : : : "memory");
+}
+
+size_t dcache_line_size;
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* operation for data cache by virtual address to PoC */
+
+static inline int arm64_dcache_range(uintptr_t start_addr,
+ uintptr_t end_addr, int op)
+{
+ /* Align address to line size */
+
+ start_addr = LINE_ALIGN_DOWN(start_addr, dcache_line_size);
+
+ while (start_addr < end_addr)
+ {
+ switch (op)
+ {
+ case CACHE_OP_WB:
+ {
+ dc_ops("cvac", start_addr);
+ break;
+ }
+
+ case CACHE_OP_INVD:
+ {
+ dc_ops("ivac", start_addr);
+ break;
+ }
+
+ case CACHE_OP_WB_INVD:
+ {
+ dc_ops("civac", start_addr);
+ break;
+ }
+ }
+ start_addr += dcache_line_size;
+ }
+
+ __DSB();
+
+ return 0;
+}
+
+/* operation for all data cache */
+
+static inline int arm64_dcache_all(int op)
+{
+ uint32_t clidr_el1;
+ uint32_t csselr_el1;
+ uint32_t ccsidr_el1;
+ uint8_t loc;
+ uint8_t ctype;
+ uint8_t cache_level;
+ uint8_t line_size;
+ uint8_t way_pos;
+ uint32_t max_ways;
+ uint32_t max_sets;
+ uint32_t dc_val;
+ uint32_t set;
+ uint32_t way;
+
+ /* Data barrier before start */
+
+ __DSB();
+
+ clidr_el1 = read_sysreg(clidr_el1);
+
+ loc = (clidr_el1 >> CLIDR_EL1_LOC_SHIFT) & CLIDR_EL1_LOC_MASK;
+ if (!loc)
+ {
+ return 0;
+ }
+
+ for (cache_level = 0; cache_level < loc; cache_level++)
+ {
+ ctype =
+ (clidr_el1 >>
+ CLIDR_EL1_CTYPE_SHIFT(cache_level)) & CLIDR_EL1_CTYPE_MASK;
+
+ /* No data cache, continue */
+
+ if (ctype < 2)
+ {
+ continue;
+ }
+
+ /* select cache level */
+
+ csselr_el1 = cache_level << 1;
+ write_sysreg(csselr_el1, csselr_el1);
+ __ISB();
+
+ ccsidr_el1 = read_sysreg(ccsidr_el1);
+ line_size =
+ (ccsidr_el1 >> CCSIDR_EL1_LN_SZ_SHIFT & CCSIDR_EL1_LN_SZ_MASK) + 4;
+ max_ways =
+ (ccsidr_el1 >> CCSIDR_EL1_WAYS_SHIFT) & CCSIDR_EL1_WAYS_MASK;
+ max_sets =
+ (ccsidr_el1 >> CCSIDR_EL1_SETS_SHIFT) & CCSIDR_EL1_SETS_MASK;
+
+ /* 32-log2(ways), bit position of way in DC operand */
+
+ way_pos = __builtin_clz(max_ways);
+
+ for (set = 0; set <= max_sets; set++)
+ {
+ for (way = 0; way <= max_ways; way++)
+ {
+ /* way number, aligned to pos in DC operand */
+
+ dc_val = way << way_pos;
+
+ /* cache level, aligned to pos in DC operand */
+
+ dc_val |= csselr_el1;
+
+ /* set number, aligned to pos in DC operand */
+
+ dc_val |= set << line_size;
+ switch (op)
+ {
+ case CACHE_OP_WB:
+ {
+ dc_ops("csw", dc_val);
+ break;
+ }
+
+ case CACHE_OP_INVD:
+ {
+ dc_ops("isw", dc_val);
+ break;
+ }
+
+ case CACHE_OP_WB_INVD:
+ {
+ dc_ops("cisw", dc_val);
+ break;
+ }
Review Comment:
Add two spaces and maybe `default` case
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r903373205
##########
boards/Kconfig:
##########
@@ -1575,6 +1575,15 @@ config ARCH_BOARD_SABRE_6QUAD
This options selects support for NuttX on the NXP/Freescale Sabre
board featuring the iMX 6Quad CPU.
+
+config ARCH_BOARD_QEMU_A53
Review Comment:
done
--
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r905001017
##########
tools/ci/testlist/macos.dat:
##########
@@ -36,3 +36,9 @@
# x86_64
/x86_64/intel64/qemu-intel64/configs/nsh
+
+# The gcc 11.2 toolcain for MACOS maybe fail when compile
+# with float, disable the cibuild check for MACOS
+# it will be enbale while new toolchain release
Review Comment:
s/enbale/enabled/
##########
arch/arm64/src/common/arm64_initialstate.c:
##########
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialstate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tcb)
+{
+ char * stack_ptr = tcb->stack_base_ptr + tcb->adj_stack_size;
+ struct regs_context * pinitctx;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * pfpuctx;
+ pfpuctx = STACK_PTR_TO_FRAME(struct fpu_reg, stack_ptr);
+ tcb->xcp.fpu_regs = pfpuctx;
+
+ /* set fpu context */
+
+ arm64_init_fpu(tcb);
+ stack_ptr = (char *)pfpuctx;
+#endif
+
+ pinitctx = STACK_PTR_TO_FRAME(struct regs_context, stack_ptr);
+ memset(pinitctx, 0, sizeof(struct regs_context));
+ pinitctx->elr = (uint64_t)tcb->start;
+
+ /* Keep using SP_EL1 */
+
+ pinitctx->spsr = SPSR_MODE_EL1H;
+
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ pinitctx->spsr |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT);
+#endif /* CONFIG_SUPPRESS_INTERRUPTS */
+
+ pinitctx->sp_elx = (uint64_t)pinitctx;
+ pinitctx->sp_el0 = (uint64_t)pinitctx;
+ pinitctx->exe_depth = 0;
+ pinitctx->tpidr_el0 = (uint64_t)tcb;
+ pinitctx->tpidr_el1 = (uint64_t)tcb;
+
+ tcb->xcp.regs = (uint64_t *)pinitctx;
+}
+
+/****************************************************************************
+ * Name: up_initial_state
+ *
+ * Description:
+ * A new thread is being started and a new TCB has been created. This
+ * function is called to initialize the processor specific portions of
+ * the new TCB.
+ *
+ * This function must setup the initial architecture registers and/or
+ * stack so that execution will begin at tcb->start on the next context
+ * switch.
+ *
+ ****************************************************************************/
+
+void up_initial_state(struct tcb_s *tcb)
+{
+ struct xcptcontext *xcp = &tcb->xcp;
+
+ memset(xcp, 0, sizeof(struct xcptcontext));
+
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ /* Initialize the idle thread stack */
+#ifdef CONFIG_SMP
+ tcb->stack_alloc_ptr = (void *)(g_cpu_idlestackalloc[0]);
+#else
+ tcb->stack_alloc_ptr = (void *)(g_idle_stack);
+#endif
+ tcb->stack_base_ptr = tcb->stack_alloc_ptr;
+ tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
+
+#ifdef CONFIG_ARCH_FPU
+ /* set fpu context */
+
+ arm64_init_fpu(tcb);
+#endif
+ /* set initialize idle thread id and exeception depth */
Review Comment:
s/exeception/exception/
##########
arch/arm64/src/common/arm64_head.S:
##########
@@ -0,0 +1,291 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_head.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ * DESCRIPTION
+ * Bring-up code for ARMv8.
+ * Based on head.S(arm64 porting) at Xen Hypervisor Project
+ * Based on reset.S(aarch64 porting) at Zephyr RTOS Project
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "arm64_arch.h"
+#include "arm64_macro.inc"
+
+/* macro define from xen head, for efi head define */
+#define PAGE_SHIFT 12
+#define __HEAD_FLAG_PAGE_SIZE ((PAGE_SHIFT - 10) / 2)
+
+#define __HEAD_FLAG_PHYS_BASE 1
+
+
+#define __HEAD_FLAGS ((__HEAD_FLAG_PAGE_SIZE << 1) | \
+ (__HEAD_FLAG_PHYS_BASE << 3))
+
+#ifdef CONFIG_DEBUG_FEATURES
+
+#define RODATA_STR(label, msg) \
+.pushsection .rodata.str, "aMS", %progbits, 1 ; \
+label: .asciz msg; \
+.popsection
+
+/* Macro to print a string to the UART, if there is one.
+ * Clobbers x0 - x3, x30 is lr for return
+ */
+#define PRINT(_s) \
+ mov x3, x30 ; \
+ adr x1, 98f ; \
+ bl boot_stage_puts; \
+ mov x30, x3 ; \
+ RODATA_STR(98, _s)
+#else
+#define PRINT(s)
+#endif /* CONFIG_DEBUG_FEATURES */
+
+ /* Kernel startup entry point.
+ * ---------------------------
+ *
+ * The requirements are:
+ * MMU = off, D-cache = off, I-cache = on or off,
+ * x0 = physical address to the FDT blob.
+ * it will be used when NuttX support divice tree in the feature
+ *
+ * This must be the very first address in the loaded image.
+ * It should be loaded at any 4K-aligned address.
+ */
+ .globl __start;
+__start:
+
+ /* DO NOT MODIFY. Image header expected by Linux boot-loaders.
+ *
+ * This add instruction has no meaningful effect except that
+ * its opcode forms the magic "MZ" signature of a PE/COFF file
+ * that is required for UEFI applications.
+ *
+ * Some bootloader (such imx8 uboot) checking the magic "MZ" to see
+ * if the image is a valid Linux image. but modifing the bootLoader is
Review Comment:
s/modifing/modifying/
##########
arch/arm64/src/common/arm64_syscall.c:
##########
@@ -0,0 +1,541 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_syscall.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+#include <syscall.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/addrenv.h>
+
+#include "arch/irq.h"
+#include "signal/signal.h"
+#include "addrenv.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dispatch_syscall
+ *
+ * Description:
+ * Call the stub function corresponding to the system call. NOTE the non-
+ * standard parameter passing:
+ *
+ * x0 = SYS_ call number
+ * x1 = parm0
+ * x2 = parm1
+ * x3 = parm2
+ * x4 = parm3
+ * x5 = parm4
+ * x6 = parm5
+ *
+ * The values of X4-X5 may be preserved in the proxy called by the user
+ * code if they are used (but otherwise will not be).
+ *
+ * WARNING: There are hard-coded values in this logic!
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LIB_SYSCALL
+static void dispatch_syscall(void) naked_function;
+static void dispatch_syscall(void)
+{
+ __asm__ __volatile__
+ (
+ " sub sp, sp, #16\n" /* Create a stack frame to hold 3 parms + lr */
+ " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */
+ " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */
+ " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */
+ " str lr, [sp, #12]\n" /* Save lr in the stack frame */
+ " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
+ " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */
+ " blx ip\n" /* Call the stub (modifies lr) */
+ " ldr lr, [sp, #12]\n" /* Restore lr */
+ " add sp, sp, #16\n" /* Destroy the stack frame */
+ " mov r2, r0\n" /* R2=Save return value in R2 */
+ " mov r0, %0\n" /* R0=SYS_syscall_return */
+ " svc %1\n"::"i"(SYS_syscall_return),
+ "i"(SYS_syscall) /* Return from the SYSCALL */
+ );
+}
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void arm64_dump_syscall(const char *tag, uint64_t cmd,
+ const struct regs_context * f_regs)
+{
+ svcinfo("SYSCALL %s: regs: %p cmd: %" PRId64 "\n", tag, f_regs, cmd);
+
+ svcinfo("x0: 0x%-16lx x1: 0x%lx\n",
+ f_regs->regs[REG_X0], f_regs->regs[REG_X1]);
+ svcinfo("x2: 0x%-16lx x3: 0x%lx\n",
+ f_regs->regs[REG_X2], f_regs->regs[REG_X3]);
+ svcinfo("x4: 0x%-16lx x5: 0x%lx\n",
+ f_regs->regs[REG_X4], f_regs->regs[REG_X5]);
+ svcinfo("x6: 0x%-16lx x7: 0x%lx\n",
+ f_regs->regs[REG_X6], f_regs->regs[REG_X7]);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_syscall_switch
+ *
+ * Description:
+ * task swith syscall
Review Comment:
s/swith/switch/
##########
arch/arm64/src/common/arm64_head.S:
##########
@@ -0,0 +1,291 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_head.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ * DESCRIPTION
+ * Bring-up code for ARMv8.
+ * Based on head.S(arm64 porting) at Xen Hypervisor Project
+ * Based on reset.S(aarch64 porting) at Zephyr RTOS Project
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "arm64_arch.h"
+#include "arm64_macro.inc"
+
+/* macro define from xen head, for efi head define */
+#define PAGE_SHIFT 12
+#define __HEAD_FLAG_PAGE_SIZE ((PAGE_SHIFT - 10) / 2)
+
+#define __HEAD_FLAG_PHYS_BASE 1
+
+
+#define __HEAD_FLAGS ((__HEAD_FLAG_PAGE_SIZE << 1) | \
+ (__HEAD_FLAG_PHYS_BASE << 3))
+
+#ifdef CONFIG_DEBUG_FEATURES
+
+#define RODATA_STR(label, msg) \
+.pushsection .rodata.str, "aMS", %progbits, 1 ; \
+label: .asciz msg; \
+.popsection
+
+/* Macro to print a string to the UART, if there is one.
+ * Clobbers x0 - x3, x30 is lr for return
+ */
+#define PRINT(_s) \
+ mov x3, x30 ; \
+ adr x1, 98f ; \
+ bl boot_stage_puts; \
+ mov x30, x3 ; \
+ RODATA_STR(98, _s)
+#else
+#define PRINT(s)
+#endif /* CONFIG_DEBUG_FEATURES */
+
+ /* Kernel startup entry point.
+ * ---------------------------
+ *
+ * The requirements are:
+ * MMU = off, D-cache = off, I-cache = on or off,
+ * x0 = physical address to the FDT blob.
+ * it will be used when NuttX support divice tree in the feature
Review Comment:
s/divice/device/
s/feature/future/
##########
arch/arm64/src/qemu/qemu_lowputc.S:
##########
@@ -0,0 +1,83 @@
+/****************************************************************************
+ * arch/arm64/src/qemu/qemu_lowputc.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************
+ *
+ * DESCRIPTION
+ * Wrapper for early printk
+ *
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "arm64_macro.inc"
+
+/* 32-bit register definition for imx8qm uart */
+
+#define UART1_BASE_ADDRESS 0x9000000
+#define EARLY_UART_PL011_BAUD_RATE 115200
+
+/* PL011 UART initialization
+ * xb: register which containts the UART base address
Review Comment:
s/containts/contains/
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906674372
##########
arch/arm64/src/common/arm64_boot.c:
##########
@@ -0,0 +1,185 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/init.h>
+
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+
+extern void *_vector_table[];
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_boot_el3_init(void)
+{
+ uint64_t reg;
+
+ /* Setup vector table */
+
+ write_sysreg((uint64_t)_vector_table, vbar_el3);
+ __ISB();
+
+ reg = 0U; /* Mostly RES0 */
+ reg &= ~(CPTR_TTA_BIT | /* Do not trap sysreg accesses */
+ CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
+ CPTR_TCPAC_BIT); /* Do not trap CPTR_EL2 / CPACR_EL1 accesses
+ */
+
+ /* CPTR_EL3, Architectural Feature Trap Register (EL3) */
+
+ write_sysreg(reg, cptr_el3);
+
+ reg = 0U; /* Reset */
+ reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */
+ reg |= (SCR_RES1 | /* RES1 */
+ SCR_RW_BIT | /* EL2 execution state is AArch64 */
+ SCR_ST_BIT | /* Do not trap EL1 accesses to timer */
+ SCR_HCE_BIT | /* Do not trap HVC */
+ SCR_SMD_BIT); /* Do not trap SMC */
+ write_sysreg(reg, scr_el3);
+
+ reg = read_sysreg(ICC_SRE_EL3);
+ reg |= (ICC_SRE_ELX_DFB_BIT | /* Disable FIQ bypass */
+ ICC_SRE_ELX_DIB_BIT | /* Disable IRQ bypass */
+ ICC_SRE_ELX_SRE_BIT | /* System register interface is used */
+ ICC_SRE_EL3_EN_BIT); /* Enables lower Exception level access to
+ * ICC_SRE_EL1 */
+ write_sysreg(reg, ICC_SRE_EL3);
+
+ __ISB();
+}
+
+void arm64_boot_el3_get_next_el(uint64_t switch_addr)
+{
+ uint64_t spsr;
+
+ write_sysreg(switch_addr, elr_el3);
+
+ /* Mask the DAIF */
+
+ spsr = SPSR_DAIF_MASK;
+ spsr |= SPSR_MODE_EL2T;
+
+ write_sysreg(spsr, spsr_el3);
+}
+
+void arm64_boot_el2_init(void)
+{
+ uint64_t reg;
+
+ reg = read_sysreg(sctlr_el2);
+ reg |= (SCTLR_EL2_RES1 | /* RES1 */
+ SCTLR_I_BIT | /* Enable i-cache */
+ SCTLR_SA_BIT); /* Enable SP alignment check */
+ write_sysreg(reg, sctlr_el2);
+
+ reg = read_sysreg(hcr_el2);
+ reg |= HCR_RW_BIT; /* EL1 Execution state is AArch64 */
+ write_sysreg(reg, hcr_el2);
+
+ reg = 0U; /* RES0 */
+ reg |= CPTR_EL2_RES1; /* RES1 */
+ reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
+ CPTR_TCPAC_BIT); /* Do not trap CPACR_EL1 accesses */
+ write_sysreg(reg, cptr_el2);
+
+ /* Enable EL1 access to timers */
+
+ reg = read_sysreg(cnthctl_el2);
+ reg |= (CNTHCTL_EL2_EL1PCEN_EN | CNTHCTL_EL2_EL1PCTEN_EN);
+ write_sysreg(reg, cnthctl_el2);
+
+ zero_sysreg(cntvoff_el2); /* Set 64-bit virtual timer offset to 0 */
+
+#ifdef CONFIG_ARCH_ARMV8R
+ zero_sysreg(cnthps_ctl_el2);
+#else
+ zero_sysreg(cnthp_ctl_el2);
+#endif
+
+ /* Enable this if/when we use the hypervisor timer.
+ * write_cnthp_cval_el2(~(uint64_t)0);
+ */
+
+ __ISB();
+}
+
+void arm64_boot_el1_init(void)
+{
+ uint64_t reg;
+
+ /* Setup vector table */
+
+ write_sysreg((uint64_t)_vector_table, vbar_el1);
+ __ISB();
+
+ reg = 0U; /* RES0 */
+ reg |= CPACR_EL1_FPEN_NOTRAP; /* Do not trap NEON/SIMD/FP initially */
+
+ /* TODO: CONFIG_FLOAT_*_FORBIDDEN */
+
+ write_sysreg(reg, cpacr_el1);
+
+ reg = read_sysreg(sctlr_el1);
+ reg |= (SCTLR_EL1_RES1 | /* RES1 */
+ SCTLR_I_BIT | /* Enable i-cache */
+ SCTLR_SA_BIT); /* Enable SP alignment check */
+ write_sysreg(reg, sctlr_el1);
+
+ write_sysreg((~(uint64_t)0), cntv_cval_el0);
+
+ /* Enable these if/when we use the corresponding timers.
+ * write_cntp_cval_el0(~(uint64_t)0);
+ * write_cntps_cval_el1(~(uint64_t)0);
+ */
+
+ __ISB();
+}
+
+/* These simple memset alternatives are necessary
+ * as the function at libc is depend on the MMU
+ * to be active.
+ */
+
+static void boot_early_memset(void *dst, int c, size_t n)
+{
+ uint8_t *d = dst;
+
+ while (n--)
+ {
+ *d++ = c;
+ }
+}
+
+void arm64_boot_primary_c_routine(void)
+{
+ boot_early_memset(_sbss, 0, _ebss - _sbss);
Review Comment:
No, at this stage, the MMU is not enable, and maybe alignment check is enable
so it's safe operation to clear as byte
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906687696
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#define BIT(n) (1UL << (n))
+#define BIT64(_n) (1ULL << (_n))
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
Review Comment:
Sure
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906698456
##########
arch/arm64/src/common/arm64_assert.c:
##########
@@ -0,0 +1,582 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_assert.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/board.h>
+#include <nuttx/syslog/syslog.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* USB trace dumping */
+
+#ifndef CONFIG_USBDEV_TRACE
+# undef CONFIG_ARCH_USBDUMP
+#endif
+
+#ifndef CONFIG_BOARD_RESET_ON_ASSERT
+# define CONFIG_BOARD_RESET_ON_ASSERT 0
+#endif
+
+/****************************************************************************
+ * Name: arm_registerdump
+ ****************************************************************************/
+
+static void arm64_registerdump(struct regs_context * regs)
+{
+ _alert("stack = %p\n", regs);
+ _alert("x0: 0x%-16"PRIx64" x1: 0x%"PRIx64"\n",
+ regs->regs[REG_X0], regs->regs[REG_X1]);
+ _alert("x2: 0x%-16"PRIx64" x3: 0x%"PRIx64"\n",
+ regs->regs[REG_X2], regs->regs[REG_X3]);
+ _alert("x4: 0x%-16"PRIx64" x5: 0x%"PRIx64"\n",
+ regs->regs[REG_X4], regs->regs[REG_X5]);
+ _alert("x6: 0x%-16"PRIx64" x7: 0x%"PRIx64"\n",
+ regs->regs[REG_X6], regs->regs[REG_X7]);
+ _alert("x8: 0x%-16"PRIx64" x9: 0x%"PRIx64"\n",
+ regs->regs[REG_X8], regs->regs[REG_X9]);
+ _alert("x10: 0x%-16"PRIx64" x11: 0x%"PRIx64"\n",
+ regs->regs[REG_X10], regs->regs[REG_X11]);
+ _alert("x12: 0x%-16"PRIx64" x13: 0x%"PRIx64"\n",
+ regs->regs[REG_X12], regs->regs[REG_X13]);
+ _alert("x14: 0x%-16"PRIx64" x15: 0x%"PRIx64"\n",
+ regs->regs[REG_X14], regs->regs[REG_X15]);
+ _alert("x16: 0x%-16"PRIx64" x17: 0x%"PRIx64"\n",
+ regs->regs[REG_X16], regs->regs[REG_X17]);
+ _alert("x18: 0x%-16"PRIx64" x19: 0x%"PRIx64"\n",
+ regs->regs[REG_X18], regs->regs[REG_X19]);
+ _alert("x20: 0x%-16"PRIx64" x21: 0x%"PRIx64"\n",
+ regs->regs[REG_X20], regs->regs[REG_X21]);
+ _alert("x22: 0x%-16"PRIx64" x23: 0x%"PRIx64"\n",
+ regs->regs[REG_X22], regs->regs[REG_X23]);
+ _alert("x24: 0x%-16"PRIx64" x25: 0x%"PRIx64"\n",
+ regs->regs[REG_X24], regs->regs[REG_X25]);
+ _alert("x26: 0x%-16"PRIx64" x27: 0x%"PRIx64"\n",
+ regs->regs[REG_X26], regs->regs[REG_X27]);
+ _alert("x28: 0x%-16"PRIx64" x29: 0x%"PRIx64"\n",
+ regs->regs[REG_X28], regs->regs[REG_X29]);
+ _alert("x30: 0x%-16"PRIx64"\n", regs->regs[REG_X30]);
+
+ _alert("\n");
+ _alert("STATUS Registers:\n");
+ _alert("SPSR: 0x%-16"PRIx64"\n", regs->spsr);
+ _alert("ELR: 0x%-16"PRIx64"\n", regs->elr);
+ _alert("SP_EL0: 0x%-16"PRIx64"\n", regs->sp_el0);
+ _alert("SP_ELX: 0x%-16"PRIx64"\n", regs->sp_elx);
+ _alert("TPIDR_EL0: 0x%-16"PRIx64"\n", regs->tpidr_el0);
+ _alert("TPIDR_EL1: 0x%-16"PRIx64"\n", regs->tpidr_el1);
+ _alert("EXE_DEPTH: 0x%-16"PRIx64"\n", regs->exe_depth);
+}
+
+#ifdef CONFIG_ARCH_STACKDUMP
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_stackdump
+ ****************************************************************************/
+
+static void arm64_stackdump(uint64_t sp, uint64_t stack_top)
+{
+ uint64_t stack;
+
+ /* Flush any buffered SYSLOG data to avoid overwrite */
+
+ syslog_flush();
+
+ for (stack = sp & ~0x1f; stack < (stack_top & ~0x1f); stack += 64)
+ {
+ uint64_t *ptr = (uint64_t *)stack;
+ _alert("%08" PRIx64 ": %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 " %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 "\n",
+ stack, ptr[0], ptr[1], ptr[2], ptr[3],
+ ptr[4], ptr[5], ptr[6], ptr[7]);
+ }
+}
+
+/****************************************************************************
+ * Name: arm_dump_task
+ ****************************************************************************/
+
+static void arm64_dump_task(struct tcb_s *tcb, void *arg)
+{
+ char args[64] = "";
+#ifdef CONFIG_STACK_COLORATION
+ uint64_t stack_filled = 0;
+ uint64_t stack_used;
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ struct cpuload_s cpuload;
+ uint64_t fracpart;
+ uint64_t intpart;
+ uint64_t tmp;
+
+ clock_cpuload(tcb->pid, &cpuload);
+
+ if (cpuload.total > 0)
+ {
+ tmp = (1000 * cpuload.active) / cpuload.total;
+ intpart = tmp / 10;
+ fracpart = tmp - 10 * intpart;
+ }
+ else
+ {
+ intpart = 0;
+ fracpart = 0;
+ }
+#endif
+
+#ifdef CONFIG_STACK_COLORATION
+ stack_used = up_check_tcbstack(tcb);
+ if (tcb->adj_stack_size > 0 && stack_used > 0)
+ {
+ /* Use fixed-point math with one decimal place */
+
+ stack_filled = 10 * 100 * stack_used / tcb->adj_stack_size;
+ }
+#endif
+
+#ifndef CONFIG_DISABLE_PTHREAD
+ if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD)
+ {
+ struct pthread_tcb_s *ptcb = (struct pthread_tcb_s *)tcb;
+
+ snprintf(args, sizeof(args), "%p ", ptcb->arg);
+ }
+ else
+#endif
+ {
+ FAR char **argv = tcb->group->tg_info->argv + 1;
+ size_t npos = 0;
+
+ while (*argv != NULL && npos < sizeof(args))
+ {
+ npos += snprintf(args + npos, sizeof(args) - npos, " %s", *argv++);
+ }
+ }
+
+ /* Dump interesting properties of this task */
+
+ _alert(" %4d %4d"
+#ifdef CONFIG_SMP
+ " %4d"
+#endif
+#ifdef CONFIG_STACK_COLORATION
+ " %7lu"
+#endif
+ " %7lu"
+#ifdef CONFIG_STACK_COLORATION
+ " %3" PRId64 ".%1" PRId64 "%%%c"
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ " %3" PRId64 ".%01" PRId64 "%%"
+#endif
+#if CONFIG_TASK_NAME_SIZE > 0
+ " %s %s\n",
+#else
+ " %s\n",
+#endif
+ tcb->pid, tcb->sched_priority,
+#ifdef CONFIG_SMP
+ tcb->cpu,
+#endif
+#ifdef CONFIG_STACK_COLORATION
+ (unsigned long)up_check_tcbstack(tcb),
+#endif
+ (unsigned long)tcb->adj_stack_size
+#ifdef CONFIG_STACK_COLORATION
+ , stack_filled / 10, stack_filled % 10,
+ (stack_filled >= 10 * 80 ? '!' : ' ')
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ , intpart, fracpart
+#endif
+#if CONFIG_TASK_NAME_SIZE > 0
Review Comment:
Done
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915846897
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
Review Comment:
done
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915894535
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
Review Comment:
I move the define into arch/arm64/src/common/arm64_arch.h, which is a private header file
i define these struct for 2 propose
1. in C level, it's more readable and convenient to access by struct, since the register context is included 128bit, 64bit and 32bit register
2. for GDB debug propose, when I p *val, it's convenient to show register
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915116673
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+}
+
+#else
+
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
@xiaoxiang781216 thank you. I will edit my comment above to remove FAR.
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916777030
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
Review Comment:
remove, it's old unused macro
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1182836547
the comments have merge, please check
@xiaoxiang781216
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r919662832
##########
arch/arm64/src/Toolchain.defs:
##########
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm64/src/Toolchain.defs
Review Comment:
Ok
##########
arch/arm64/src/Toolchain.defs:
##########
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm64/src/Toolchain.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+#
+# Supported toolchains
+#
+# Each toolchain definition should set:
+#
+# CROSSDEV The GNU toolchain triple (command prefix)
+# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
+# FPU options, etc.
+# ARCHOPTIMIZATION The optimization level that results in
+# reliable code generation.
+#
+
+ifeq ($(CONFIG_ARCH_ARMV8A),y)
+ARCHCPUFLAGS += -march=armv8-a
+endif
+
+ifeq ($(CONFIG_ARCH_CORTEX_A53),y)
+ARCHCPUFLAGS += -mtune=cortex-a53
+endif
+
+ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
+ ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL)
+else ifeq ($(CONFIG_DEBUG_FULLOPT),y)
+ ARCHOPTIMIZATION += -Os
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += -fno-strict-aliasing
+endif
+
+ifeq ($(CONFIG_FRAME_POINTER),y)
+ ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls
+else
+ ARCHOPTIMIZATION += -fomit-frame-pointer
+endif
+
+ifeq ($(CONFIG_STACK_CANARIES),y)
+ ARCHOPTIMIZATION += -fstack-protector-all
+endif
+
+ifeq ($(CONFIG_ARCH_COVERAGE),y)
+ ARCHOPTIMIZATION += -fprofile-generate -ftest-coverage
+endif
+ARCHCFLAGS += -fno-common
+ARCHCXXFLAGS += -fno-common -nostdinc++
+
+ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Werror
+ARCHCXXFLAGS += -Wall -Wshadow -Wundef
+
+ifneq ($(CONFIG_CXX_EXCEPTION),y)
+ ARCHCXXFLAGS += -fno-exceptions -fcheck-new
+endif
+
+ifneq ($(CONFIG_CXX_RTTI),y)
+ ARCHCXXFLAGS += -fno-rtti
+endif
+
+LDFLAGS += -nostdlib
+
+# Optimization of unused sections
+
+ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y)
+ LDFLAGS += --gc-sections
+ ARCHOPTIMIZATION += -ffunction-sections -fdata-sections
+endif
+
+# Debug link map
+
+ifeq ($(CONFIG_DEBUG_LINK_MAP),y)
+ LDFLAGS += --cref -Map=$(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx.map)
+endif
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+ ARCHOPTIMIZATION += -g
+endif
+CROSSDEV ?= aarch64-none-elf-
+
+# Default toolchain
+
+CC = $(CROSSDEV)gcc
Review Comment:
OK
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r903193687
##########
arch/Kconfig:
##########
@@ -22,6 +22,20 @@ config ARCH_ARM
---help---
The ARM architectures
+config ARCH_ARM64
Review Comment:
done
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902417084
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/src/common/arm64_fatal.h:
##########
@@ -0,0 +1,77 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1166241837
@xiaoxiang781216 , @hartmannathan , @pkarashchenko
check is complete, please review again
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906673839
##########
arch/arm64/src/common/arm64_assert.c:
##########
@@ -0,0 +1,582 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_assert.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/board.h>
+#include <nuttx/syslog/syslog.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* USB trace dumping */
+
+#ifndef CONFIG_USBDEV_TRACE
+# undef CONFIG_ARCH_USBDUMP
+#endif
+
+#ifndef CONFIG_BOARD_RESET_ON_ASSERT
+# define CONFIG_BOARD_RESET_ON_ASSERT 0
+#endif
+
+/****************************************************************************
+ * Name: arm_registerdump
+ ****************************************************************************/
+
+static void arm64_registerdump(struct regs_context * regs)
+{
+ _alert("stack = %p\n", regs);
+ _alert("x0: 0x%-16"PRIx64" x1: 0x%"PRIx64"\n",
+ regs->regs[REG_X0], regs->regs[REG_X1]);
+ _alert("x2: 0x%-16"PRIx64" x3: 0x%"PRIx64"\n",
+ regs->regs[REG_X2], regs->regs[REG_X3]);
+ _alert("x4: 0x%-16"PRIx64" x5: 0x%"PRIx64"\n",
+ regs->regs[REG_X4], regs->regs[REG_X5]);
+ _alert("x6: 0x%-16"PRIx64" x7: 0x%"PRIx64"\n",
+ regs->regs[REG_X6], regs->regs[REG_X7]);
+ _alert("x8: 0x%-16"PRIx64" x9: 0x%"PRIx64"\n",
+ regs->regs[REG_X8], regs->regs[REG_X9]);
+ _alert("x10: 0x%-16"PRIx64" x11: 0x%"PRIx64"\n",
+ regs->regs[REG_X10], regs->regs[REG_X11]);
+ _alert("x12: 0x%-16"PRIx64" x13: 0x%"PRIx64"\n",
+ regs->regs[REG_X12], regs->regs[REG_X13]);
+ _alert("x14: 0x%-16"PRIx64" x15: 0x%"PRIx64"\n",
+ regs->regs[REG_X14], regs->regs[REG_X15]);
+ _alert("x16: 0x%-16"PRIx64" x17: 0x%"PRIx64"\n",
+ regs->regs[REG_X16], regs->regs[REG_X17]);
+ _alert("x18: 0x%-16"PRIx64" x19: 0x%"PRIx64"\n",
+ regs->regs[REG_X18], regs->regs[REG_X19]);
+ _alert("x20: 0x%-16"PRIx64" x21: 0x%"PRIx64"\n",
+ regs->regs[REG_X20], regs->regs[REG_X21]);
+ _alert("x22: 0x%-16"PRIx64" x23: 0x%"PRIx64"\n",
+ regs->regs[REG_X22], regs->regs[REG_X23]);
+ _alert("x24: 0x%-16"PRIx64" x25: 0x%"PRIx64"\n",
+ regs->regs[REG_X24], regs->regs[REG_X25]);
+ _alert("x26: 0x%-16"PRIx64" x27: 0x%"PRIx64"\n",
+ regs->regs[REG_X26], regs->regs[REG_X27]);
+ _alert("x28: 0x%-16"PRIx64" x29: 0x%"PRIx64"\n",
+ regs->regs[REG_X28], regs->regs[REG_X29]);
+ _alert("x30: 0x%-16"PRIx64"\n", regs->regs[REG_X30]);
+
+ _alert("\n");
+ _alert("STATUS Registers:\n");
+ _alert("SPSR: 0x%-16"PRIx64"\n", regs->spsr);
+ _alert("ELR: 0x%-16"PRIx64"\n", regs->elr);
+ _alert("SP_EL0: 0x%-16"PRIx64"\n", regs->sp_el0);
+ _alert("SP_ELX: 0x%-16"PRIx64"\n", regs->sp_elx);
+ _alert("TPIDR_EL0: 0x%-16"PRIx64"\n", regs->tpidr_el0);
+ _alert("TPIDR_EL1: 0x%-16"PRIx64"\n", regs->tpidr_el1);
+ _alert("EXE_DEPTH: 0x%-16"PRIx64"\n", regs->exe_depth);
+}
+
+#ifdef CONFIG_ARCH_STACKDUMP
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_stackdump
+ ****************************************************************************/
+
+static void arm64_stackdump(uint64_t sp, uint64_t stack_top)
+{
+ uint64_t stack;
+
+ /* Flush any buffered SYSLOG data to avoid overwrite */
+
+ syslog_flush();
+
+ for (stack = sp & ~0x1f; stack < (stack_top & ~0x1f); stack += 64)
+ {
+ uint64_t *ptr = (uint64_t *)stack;
+ _alert("%08" PRIx64 ": %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 " %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 "\n",
+ stack, ptr[0], ptr[1], ptr[2], ptr[3],
+ ptr[4], ptr[5], ptr[6], ptr[7]);
+ }
+}
+
+/****************************************************************************
+ * Name: arm_dump_task
+ ****************************************************************************/
+
+static void arm64_dump_task(struct tcb_s *tcb, void *arg)
+{
+ char args[64] = "";
+#ifdef CONFIG_STACK_COLORATION
+ uint64_t stack_filled = 0;
+ uint64_t stack_used;
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ struct cpuload_s cpuload;
+ uint64_t fracpart;
+ uint64_t intpart;
+ uint64_t tmp;
+
+ clock_cpuload(tcb->pid, &cpuload);
+
+ if (cpuload.total > 0)
+ {
+ tmp = (1000 * cpuload.active) / cpuload.total;
+ intpart = tmp / 10;
+ fracpart = tmp - 10 * intpart;
+ }
+ else
+ {
+ intpart = 0;
+ fracpart = 0;
+ }
+#endif
+
+#ifdef CONFIG_STACK_COLORATION
+ stack_used = up_check_tcbstack(tcb);
+ if (tcb->adj_stack_size > 0 && stack_used > 0)
+ {
+ /* Use fixed-point math with one decimal place */
+
+ stack_filled = 10 * 100 * stack_used / tcb->adj_stack_size;
+ }
+#endif
+
+#ifndef CONFIG_DISABLE_PTHREAD
+ if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD)
+ {
+ struct pthread_tcb_s *ptcb = (struct pthread_tcb_s *)tcb;
+
+ snprintf(args, sizeof(args), "%p ", ptcb->arg);
+ }
+ else
+#endif
+ {
+ FAR char **argv = tcb->group->tg_info->argv + 1;
+ size_t npos = 0;
+
+ while (*argv != NULL && npos < sizeof(args))
+ {
+ npos += snprintf(args + npos, sizeof(args) - npos, " %s", *argv++);
+ }
+ }
+
+ /* Dump interesting properties of this task */
+
+ _alert(" %4d %4d"
+#ifdef CONFIG_SMP
+ " %4d"
+#endif
+#ifdef CONFIG_STACK_COLORATION
+ " %7lu"
+#endif
+ " %7lu"
+#ifdef CONFIG_STACK_COLORATION
+ " %3" PRId64 ".%1" PRId64 "%%%c"
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ " %3" PRId64 ".%01" PRId64 "%%"
+#endif
+#if CONFIG_TASK_NAME_SIZE > 0
+ " %s %s\n",
+#else
+ " %s\n",
+#endif
+ tcb->pid, tcb->sched_priority,
+#ifdef CONFIG_SMP
+ tcb->cpu,
+#endif
+#ifdef CONFIG_STACK_COLORATION
+ (unsigned long)up_check_tcbstack(tcb),
+#endif
+ (unsigned long)tcb->adj_stack_size
+#ifdef CONFIG_STACK_COLORATION
+ , stack_filled / 10, stack_filled % 10,
+ (stack_filled >= 10 * 80 ? '!' : ' ')
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ , intpart, fracpart
+#endif
+#if CONFIG_TASK_NAME_SIZE > 0
Review Comment:
I will rework arm64 stackdump when i update the arm64 porting at next version
I cannot following armv7 completely since armv8-a have more mechanism about crash analyse
these code is keep there only for reference propose
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906688242
##########
arch/arm64/src/common/arm64_boot.c:
##########
@@ -0,0 +1,185 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/init.h>
+
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+
+extern void *_vector_table[];
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_boot_el3_init(void)
+{
+ uint64_t reg;
+
+ /* Setup vector table */
+
+ write_sysreg((uint64_t)_vector_table, vbar_el3);
+ __ISB();
+
+ reg = 0U; /* Mostly RES0 */
+ reg &= ~(CPTR_TTA_BIT | /* Do not trap sysreg accesses */
+ CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
+ CPTR_TCPAC_BIT); /* Do not trap CPTR_EL2 / CPACR_EL1 accesses
+ */
+
+ /* CPTR_EL3, Architectural Feature Trap Register (EL3) */
+
+ write_sysreg(reg, cptr_el3);
+
+ reg = 0U; /* Reset */
+ reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */
+ reg |= (SCR_RES1 | /* RES1 */
+ SCR_RW_BIT | /* EL2 execution state is AArch64 */
+ SCR_ST_BIT | /* Do not trap EL1 accesses to timer */
+ SCR_HCE_BIT | /* Do not trap HVC */
+ SCR_SMD_BIT); /* Do not trap SMC */
+ write_sysreg(reg, scr_el3);
+
+ reg = read_sysreg(ICC_SRE_EL3);
+ reg |= (ICC_SRE_ELX_DFB_BIT | /* Disable FIQ bypass */
+ ICC_SRE_ELX_DIB_BIT | /* Disable IRQ bypass */
+ ICC_SRE_ELX_SRE_BIT | /* System register interface is used */
+ ICC_SRE_EL3_EN_BIT); /* Enables lower Exception level access to
+ * ICC_SRE_EL1 */
+ write_sysreg(reg, ICC_SRE_EL3);
+
+ __ISB();
+}
+
+void arm64_boot_el3_get_next_el(uint64_t switch_addr)
+{
+ uint64_t spsr;
+
+ write_sysreg(switch_addr, elr_el3);
+
+ /* Mask the DAIF */
+
+ spsr = SPSR_DAIF_MASK;
+ spsr |= SPSR_MODE_EL2T;
+
+ write_sysreg(spsr, spsr_el3);
+}
+
+void arm64_boot_el2_init(void)
+{
+ uint64_t reg;
+
+ reg = read_sysreg(sctlr_el2);
+ reg |= (SCTLR_EL2_RES1 | /* RES1 */
+ SCTLR_I_BIT | /* Enable i-cache */
+ SCTLR_SA_BIT); /* Enable SP alignment check */
+ write_sysreg(reg, sctlr_el2);
+
+ reg = read_sysreg(hcr_el2);
+ reg |= HCR_RW_BIT; /* EL1 Execution state is AArch64 */
+ write_sysreg(reg, hcr_el2);
+
+ reg = 0U; /* RES0 */
+ reg |= CPTR_EL2_RES1; /* RES1 */
+ reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
+ CPTR_TCPAC_BIT); /* Do not trap CPACR_EL1 accesses */
+ write_sysreg(reg, cptr_el2);
+
+ /* Enable EL1 access to timers */
+
+ reg = read_sysreg(cnthctl_el2);
+ reg |= (CNTHCTL_EL2_EL1PCEN_EN | CNTHCTL_EL2_EL1PCTEN_EN);
+ write_sysreg(reg, cnthctl_el2);
+
+ zero_sysreg(cntvoff_el2); /* Set 64-bit virtual timer offset to 0 */
+
+#ifdef CONFIG_ARCH_ARMV8R
+ zero_sysreg(cnthps_ctl_el2);
+#else
+ zero_sysreg(cnthp_ctl_el2);
+#endif
+
+ /* Enable this if/when we use the hypervisor timer.
+ * write_cnthp_cval_el2(~(uint64_t)0);
+ */
+
+ __ISB();
+}
+
+void arm64_boot_el1_init(void)
+{
+ uint64_t reg;
+
+ /* Setup vector table */
+
+ write_sysreg((uint64_t)_vector_table, vbar_el1);
+ __ISB();
+
+ reg = 0U; /* RES0 */
+ reg |= CPACR_EL1_FPEN_NOTRAP; /* Do not trap NEON/SIMD/FP initially */
+
+ /* TODO: CONFIG_FLOAT_*_FORBIDDEN */
+
+ write_sysreg(reg, cpacr_el1);
+
+ reg = read_sysreg(sctlr_el1);
+ reg |= (SCTLR_EL1_RES1 | /* RES1 */
+ SCTLR_I_BIT | /* Enable i-cache */
+ SCTLR_SA_BIT); /* Enable SP alignment check */
+ write_sysreg(reg, sctlr_el1);
+
+ write_sysreg((~(uint64_t)0), cntv_cval_el0);
+
+ /* Enable these if/when we use the corresponding timers.
+ * write_cntp_cval_el0(~(uint64_t)0);
+ * write_cntps_cval_el1(~(uint64_t)0);
+ */
+
+ __ISB();
+}
+
+/* These simple memset alternatives are necessary
+ * as the function at libc is depend on the MMU
+ * to be active.
+ */
+
+static void boot_early_memset(void *dst, int c, size_t n)
+{
+ uint8_t *d = dst;
+
+ while (n--)
+ {
+ *d++ = c;
+ }
+}
+
+void arm64_boot_primary_c_routine(void)
+{
+ boot_early_memset(_sbss, 0, _ebss - _sbss);
Review Comment:
Ok. Usually BSS section should be machine word aligned, but I'm fine with what we are having now.
The other platforms use
```
# define _START_BSS &_sbss
# define _END_BSS &_ebss
```
and
```
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = _START_BSS; dest < _END_BSS; )
{
*dest++ = 0;
}
```
in `__start`. Or do BSS clear in assembly code like `arm_data_initialize:` in `arch/arm/src/armv7-a/arm_head.S`.
This is optional just to keep similar style.
I'm fine to keep code as is and just pointing possible variants
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r917705706
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
Review Comment:
Ok
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915013451
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
Should be:
`static int arm64_arch_timer_compare_isr(int irq, void *context, void *arg)`
At top of function, add:
`regs = (uint64_t) context;`
At end of function, add:
`return OK;`
(Edit: Remove FAR. Not needed for arm64.)
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
Should be:
`static int arm64_arch_timer_compare_isr(int irq, void *context, void *arg)`
At top of function, add:
`regs = (uint64_t) context;`
At end of function, add:
`return OK;`
(Edit: Removed FAR. Not needed for arm64.)
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1179476789
> FYI when applying patch:
>
> ```
> $ wget https://github.com/apache/incubator-nuttx/pull/6478.patch
> $ git checkout master
> $ git apply 6478.patch
> 6478.patch:9014: trailing whitespace.
> #else
> 6478.patch:10141: trailing whitespace.
> *
> 6478.patch:16238: trailing whitespace.
> 1. Cotex-a53 single core support: With the supporting of GICv3,
> 6478.patch:16241: trailing whitespace.
> 2. qemu-a53 board configuration support: qemu-a53 board can been
> 6478.patch:16242: trailing whitespace.
> configuring and compiling, And runing with qemu-system-aarch64
> warning: squelched 30 whitespace errors
> warning: 35 lines add whitespace errors.
> ```
I will checking this issue
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916004637
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
Review Comment:
but for following code, it's used, and arm is samed code
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916056943
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
Review Comment:
i think it's better not do this
for every soc, it have many base address, i feel just keep they in header will keep the things simple
arm32 not this configuring option, too
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[GitHub] [incubator-nuttx] pkarashchenko commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1182454319
I think many comments have been addressed. I will not be able to do a review till Friday and I'm fine to address any leftovers with the next PR after this PR is merged. I will most probably post some comments to this PR after it is merged
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1182784597
let's merge the comment path into the master one too. it doesn't make sense to use two patch.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1164385121
In first commit log, s/Cotex-a53/Cortex-a53/
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1184365051
> Please squash into a single commit
Done
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1184472953
I would like to say Congratulations on this HUGE PR!
In the Single Core case, `ostest` is running successfully for me.
In the SMP case, it seems that `ostest` fails or hangs in different places, but my system is ancient and I am running QEMU 3.1.0 (!!!), so it is possible that I am seeing old bugs in QEMU. I would need to upgrade my system and try the latest QEMU before I could draw any conclusions.
Anyway, this PR is a very good starting point for NuttX on Arm64 and I look forward to seeing NuttX on real Arm64 hardware!
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1182835467
> @xiaoxiang781216, @hartmannathan @pkarashchenko
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r920155183
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,254 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ UNUSED(regs);
+ UNUSED(arg);
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#else
+
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+ uint64_t next_cycle;
+
+ UNUSED(irq);
+ UNUSED(regs);
+ UNUSED(arg);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ next_cycle = last_cycle + cycle_per_tick;
+
+ if ((uint64_t)(next_cycle - curr_cycle) < MIN_DELAY)
+ {
+ next_cycle += cycle_per_tick;
+ }
+
+ arm64_arch_timer_set_compare(next_cycle);
+ arm64_arch_timer_set_irq_mask(false);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+/* Notes:
+ *
+ * The origin design for ARMv8-A timer is assigned private timer to
+ * every PE(CPU core), the ARM_ARCH_TIMER_IRQ is a PPI so it's
+ * should be enable at every core.
+ *
+ * But for NuttX, it's design only for primary core to handle timer
+ * interrupt and call nxsched_process_timer at timer tick mode.
+ * So we need only enable timer for primary core
+ *
+ * IMX6 use GPT which is a SPI rather than generic timer to handle
+ * timer interrupt
+ */
+
+void arm64_smp_timer_init(void)
+{
+ uint64_t curr_cycle;
+
+ /* set the initial status of timer0 of each secondary core */
+
+ curr_cycle = arm64_arch_timer_count();
+
+ arm64_arch_timer_set_compare(curr_cycle + cycle_per_tick);
+ arm64_arch_timer_enable(true);
+ up_enable_irq(ARM_ARCH_TIMER_IRQ);
+ arm64_arch_timer_set_irq_mask(false);
+}
+
+#endif
+
+uint64_t arm64_counter_read(void)
+{
+ return arm64_arch_timer_count();
+}
+
+void arm64_timer_delay(long mini_sec)
+{
+ unsigned int timeout;
+ volatile unsigned int new_counter;
Review Comment:
Actually, I wonder if this may be subject to edge case if roll-over occurs.
Would this be better:
```
start_time = arm64_counter_read();
do
{
arch_nop();
}
while ((arm64_counter_read() - start_time) < clock);
```
???
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902654904
##########
arch/arm64/include/spinlock.h:
##########
@@ -0,0 +1,90 @@
+/****************************************************************************
+ * arch/arm64/include/spinlock.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_SPINLOCK_H
+#define __ARCH_ARM64_INCLUDE_SPINLOCK_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Spinlock states */
+
+#define SP_UNLOCKED 0 /* The Un-locked state */
+#define SP_LOCKED 1 /* The Locked state */
+
+/* Memory barriers for use with NuttX spinlock logic
+ *
+ * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
+ * explicit memory accesses that appear in program order before the DMB
+ * instruction are observed before any explicit memory accesses that appear
+ * in program order after the DMB instruction. It does not affect the
+ * ordering of any other instructions executing on the processor
+ *
+ * dmb st - Data memory barrier. Wait for stores to complete.
+ *
+ * Data Synchronization Barrier (DSB) acts as a special kind of memory
+ * barrier. No instruction in program order after this instruction executes
+ * until this instruction completes. This instruction completes when: (1) All
+ * explicit memory accesses before this instruction complete, and (2) all
+ * Cache, Branch predictor and TLB maintenance operations before this
+ * instruction complete.
+ *
+ * dsb sy - Data syncrhonization barrier. Assures that the CPU waits until
Review Comment:
s/syncrhonization/synchronization/
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915847144
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
Review Comment:
done
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915845856
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
Review Comment:
FPSR and FPCR are 32-bit register, I define here only for readable
it's not any meaning for access propose
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1179483127
@xiaoxiang781216 @hartmannathan @pkarashchenko
all review issue was fixed or replied, please check again
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915437115
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#define BIT(n) (1UL << (n))
Review Comment:
> @qinwei2004 you can fix only critical items like `assert(1)` and `psci_fn` and other style issues can be fixed in the next PR
I have fix all issue you give, thanks for your careful check
Please check again
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915859107
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
Review Comment:
I move the define into arch/arm64/src/common/arm64_arch.h, which is a private header file
i define these struct for 2 propose
1. in C level, it's more readable and convenient to access by struct, since the register context is included 128bit, 64bit and 32bit register
2. for GDB debug propose, when I p *val, it's convenient to show register
thanks
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916802696
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
Review Comment:
the size is used at the struct mmu_nxrt_regions of arm64_mmu.c
the structure is defined as const and put it into rodata section.
I want set the rodata as RO attribute to avoid illegal access to the section. it will be done when I used the MMU/MPU completely
but if i use _exxxx - _sxxxx, it will trigger compile error
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902417367
##########
arch/arm64/src/common/arm64_fatal.h:
##########
@@ -0,0 +1,77 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__
+
+/**
+ * @defgroup fatal_apis Fatal error APIs
+ * @ingroup kernel_apis
+ * @{
+ */
+
+#define K_ERR_CPU_EXCEPTION (0)
+#define K_ERR_CPU_MODE32 (1)
+#define K_ERR_SPURIOUS_IRQ (2)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_fatal_error
+ *
+ * Description:
+ * fatal error handle for arm64
+ * Input Parameters:
+ * reason: error reason
+ * reg: exception stack reg context
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+void arm64_fatal_error(unsigned int reason, struct regs_context * reg);
+void arm64_dump_fatal(struct regs_context * reg);
+
+#define __builtin_unreachable() \
+ do { \
+ sinfo("Unreachable code\n"); \
+ PANIC(); \
+ } while (true)
+
+#endif //__ASSEMBLY__
+
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H__ */
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
+
+ /* for statistic propose */
+
+ int save_count;
+ int restore_count;
+ int switch_count;
+ int exe_depth_count;
+};
+
+static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/***************************************************************************
+ * Public Functions
+ ***************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb)
+{
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ memset(&g_cpu_fpu_ctx[this_cpu()], 0,
+ sizeof(struct arm64_cpu_fpu_context));
+ g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb;
+
+ tcb->xcp.fpu_regs = &g_idle_thread_fpu[this_cpu()];
+ }
+
+ memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg));
+ tcb->xcp.fpu_regs->fpu_trap = 0;
+}
+
+void arm64_destory_fpu(struct tcb_s * tcb)
+{
+ struct tcb_s * owner;
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner == tcb)
+ {
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+}
+
+/* enable FPU access trap */
+
+static void arm64_fpu_access_trap_enable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+ cpacr &= ~CPACR_EL1_FPEN_NOTRAP;
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/* disable FPU access trap */
+
+static void arm64_fpu_access_trap_disable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+
+ cpacr |= CPACR_EL1_FPEN_NOTRAP;
+
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/***************************************************************************
+ * Name: arm64_fpu_enter_exception
+ *
+ * Description:
+ * called at every time get into a exception
+ *
+ ***************************************************************************/
+
+void arm64_fpu_enter_exception(void)
+{
+}
+
+void arm64_fpu_exit_exception(void)
+{
+}
+
+void arm64_fpu_trap(struct esf_reg * regs)
+{
+ struct tcb_s * owner;
+
+ /* disable fpu trap access */
+
+ arm64_fpu_access_trap_disable();
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner != NULL)
+ {
+ arm64_fpu_save(owner->xcp.fpu_regs);
+ __DSB();
+ g_cpu_fpu_ctx[this_cpu()].save_count++;
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+
+ if (arch_get_exception_depth() > 1)
+ {
+ /* if get_exception_depth > 1
+ * it means FPU access exception occurred in exception context
+ * switch FPU owner to idle thread
+ */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].idle_thread;
+ }
+ else
+ {
+ owner = (struct tcb_s *)arch_get_current_tcb();
+ }
+
+ /* restore our content */
+
+ arm64_fpu_restore(owner->xcp.fpu_regs);
+ g_cpu_fpu_ctx[this_cpu()].restore_count++;
+
+ /* become new owner */
+
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = owner;
+ owner->xcp.fpu_regs->fpu_trap = 1;
+}
+
+void arm64_fpu_context_restore(void)
+{
+ struct tcb_s *new_tcb = (struct tcb_s *)arch_get_current_tcb();
+
+ arm64_fpu_access_trap_enable();
+
+ if (new_tcb->xcp.fpu_regs->fpu_trap == 0)
+ {
+ /* FPU trap hasn't happened at this task */
+
+ arm64_fpu_access_trap_enable();
+ }
+ else
+ {
+ /* FPU trap has happened at this task */
+
+ if (new_tcb == g_cpu_fpu_ctx[this_cpu()].fpu_owner)
+ {
+ arm64_fpu_access_trap_disable();
+ }
+ else
+ {
+ arm64_fpu_access_trap_enable();
+ }
+ }
+
+ g_cpu_fpu_ctx[this_cpu()].switch_count++;
+}
+
+void arm64_fpu_enable(void)
+{
+ irqstate_t flags = up_irq_save();
+
+ arm64_fpu_access_trap_enable();
+ up_irq_restore(flags);
+}
+
+void arm64_fpu_disable(void)
+{
+ irqstate_t flags = up_irq_save();
+
+ arm64_fpu_access_trap_disable();
+ up_irq_restore(flags);
+}
+
+/***************************************************************************
+ * Name: up_fpucmp
+ *
+ * Description:
+ * compare FPU areas from thread context
+ *
+ ***************************************************************************/
+
+bool up_fpucmp(const void *saveregs1, const void *saveregs2)
+{
+ const uint64_t *regs1 = saveregs1 + XCPTCONTEXT_GP_SIZE;
+ const uint64_t *regs2 = saveregs2 + XCPTCONTEXT_GP_SIZE;
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902414789
##########
arch/arm64/src/common/arm64_copystate.c:
##########
@@ -0,0 +1,120 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_copystate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <sched.h>
+#include <debug.h>
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <arch/syscall.h>
+#include <arch/irq.h>
+
+#include "arm64_internal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+int arch_save_fpucontext(void *saveregs)
+{
+ irqstate_t flags;
+ uint64_t * p_save;
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r903724638
##########
arch/arm64/src/common/arm64_cpuidlestack.c:
##########
@@ -0,0 +1,112 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpuidlestack.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+
+#include "arm64_smp.h"
+#include "arm64_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Stack alignment macros */
+
+#define STACK_ISALIGNED(a) ((uintptr_t)(a) & ~STACK_ALIGN_MASK)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_idlestack
+ *
+ * Description:
+ * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and
+ * setup up stack-related information in the IDLE task's TCB. This
+ * function is always called before up_cpu_start(). This function is
+ * only called for the CPU's initial IDLE task; up_create_task is used for
+ * all normal tasks, pthreads, and kernel threads for all CPUs.
+ *
+ * The initial IDLE task is a special case because the CPUs can be started
+ * in different wans in different environments:
Review Comment:
s/wans/ways/
##########
arch/arm64/src/common/arm64_cache.c:
##########
@@ -0,0 +1,449 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cache.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* Common operations for the caches
+ *
+ * WB means write-back and intends to transfer dirty cache lines to memory in
+ * a copy-back cache policy. May be a no-op in write-back cache policy.
+ *
+ * INVD means invalidate and will mark cache lines as not valid. A future
+ * access to the associated address is guaranteed to generate a memory fetch.
+ *
+ * armv8 data cahce instruction:
Review Comment:
s/cahce/cache/
##########
arch/arm64/src/common/arm64_checkstack.c:
##########
@@ -0,0 +1,239 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_checkstack.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <sched.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#include "sched/sched.h"
+#include "arm64_internal.h"
+
+#ifdef CONFIG_STACK_COLORATION
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static size_t do_stackcheck(void *stackbase, size_t nbytes);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: do_stackcheck
+ *
+ * Description:
+ * Determine (approximately) how much stack has been used by searching the
+ * stack memory for a high water mark. That is, the deepest level of the
+ * stack that clobbered some recognizable marker in the stack memory.
+ *
+ * Input Parameters:
+ * alloc - Allocation base address of the stack
+ * size - The size of the stack in bytes
+ *
+ * Returned Value:
+ * The estimated amount of stack space used.
+ *
+ ****************************************************************************/
+
+static size_t do_stackcheck(void *stackbase, size_t nbytes)
+{
+ uintptr_t start;
+ uintptr_t end;
+ uint64_t *ptr;
+ size_t mark;
+
+ if (nbytes == 0)
+ {
+ return 0;
+ }
+
+ /* Take extra care that we do not check outside the stack boundaries */
+
+ start = STACK_ALIGN_UP((uintptr_t)stackbase);
+ end = STACK_ALIGN_DOWN((uintptr_t)stackbase + nbytes);
+
+ /* Get the adjusted size based on the top and bottom of the stack */
+
+ nbytes = end - start;
+
+ /* The ARM uses a push-down stack: the stack grows toward lower addresses
+ * in memory. We need to start at the lowest address in the stack memory
+ * allocation and search to higher addresses. The first word we encounter
+ * that does not have the magic value is the high water mark.
+ */
+
+ for (ptr = (uint64_t *)start, mark = (nbytes >> 2);
+ *ptr == STACK_COLOR && mark > 0;
+ ptr++, mark--);
+
+ /* If the stack is completely used, then this might mean that the stack
+ * overflowed from above (meaning that the stack is too small), or may
+ * have been overwritten from below meaning that some other stack or data
+ * structure overflowed.
+ *
+ * If you see returned values saying that the entire stack is being used
+ * then enable the following logic to see it there are unused areas in the
+ * middle of the stack.
+ */
+
+#if 0
+ if (mark + 16 > nwords)
+ {
+ int i;
+ int j;
+
+ ptr = (uint32_t *)start;
+ for (i = 0; i < nbytes; i += 4 * 64)
+ {
+ for (j = 0; j < 64; j++)
+ {
+ int ch;
+ if (*ptr++ == STACK_COLOR)
+ {
+ ch = '.';
+ }
+ else
+ {
+ ch = 'X';
+ }
+
+ up_putc(ch);
+ }
+
+ up_putc('\n');
+ }
+ }
+#endif
+
+ /* Return our guess about how much stack space was used */
+
+ return mark << 2;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_stack_color
+ *
+ * Description:
+ * Write a well know value into the stack
+ *
+ ****************************************************************************/
+
+void arm64_stack_color(void *stackbase, size_t nbytes)
+{
+ uintptr_t start;
+ uintptr_t end;
+ size_t nwords;
+ uint32_t *ptr;
+
+ /* Take extra care that we do not write outside the stack boundaries */
+
+ start = STACK_ALIGN_UP((uintptr_t)stackbase);
+ end = nbytes ? STACK_ALIGN_DOWN((uintptr_t)stackbase + nbytes) :
+ up_getsp(); /* 0: colorize the running stack */
+
+ /* Get the adjusted size based on the top and bottom of the stack */
+
+ nwords = (end - start) >> 2;
+ ptr = (uint32_t *)start;
+
+ /* Set the entire stack to the coloration value */
+
+ while (nwords-- > 0)
+ {
+ *ptr++ = STACK_COLOR;
+ }
+}
+
+/****************************************************************************
+ * Name: up_check_stack and friends
+ *
+ * Description:
+ * Determine (approximately) how much stack has been used be searching the
Review Comment:
s/be searching/by searching/
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
+
+ /* for statistic propose */
+
+ int save_count;
+ int restore_count;
+ int switch_count;
+ int exe_depth_count;
+};
+
+static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/***************************************************************************
+ * Public Functions
+ ***************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb)
+{
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ memset(&g_cpu_fpu_ctx[this_cpu()], 0,
+ sizeof(struct arm64_cpu_fpu_context));
+ g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb;
+
+ tcb->xcp.fpu_regs = &g_idle_thread_fpu[this_cpu()];
+ }
+
+ memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg));
+ tcb->xcp.fpu_regs->fpu_trap = 0;
+}
+
+void arm64_destory_fpu(struct tcb_s * tcb)
+{
+ struct tcb_s * owner;
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner == tcb)
+ {
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+}
+
+/* enable FPU access trap */
+
+static void arm64_fpu_access_trap_enable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+ cpacr &= ~CPACR_EL1_FPEN_NOTRAP;
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/* disable FPU access trap */
+
+static void arm64_fpu_access_trap_disable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+
+ cpacr |= CPACR_EL1_FPEN_NOTRAP;
+
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/***************************************************************************
+ * Name: arm64_fpu_enter_exception
+ *
+ * Description:
+ * called at every time get into a exception
+ *
+ ***************************************************************************/
+
+void arm64_fpu_enter_exception(void)
+{
+}
+
+void arm64_fpu_exit_exception(void)
+{
+}
+
+void arm64_fpu_trap(struct esf_reg * regs)
+{
+ struct tcb_s * owner;
+
+ /* disable fpu trap access */
+
+ arm64_fpu_access_trap_disable();
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner != NULL)
+ {
+ arm64_fpu_save(owner->xcp.fpu_regs);
+ __DSB();
+ g_cpu_fpu_ctx[this_cpu()].save_count++;
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+
+ if (arch_get_exception_depth() > 1)
+ {
+ /* if get_exception_depth > 1
+ * it means FPU access exception occurred in exception context
+ * switch FPU owner to idle thread
+ */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].idle_thread;
+ }
+ else
+ {
+ owner = (struct tcb_s *)arch_get_current_tcb();
+ }
+
+ /* restore our content */
Review Comment:
Should this be:
`/* restore our context */`
(s/content/context/)
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1162690839
@qinwei2004 please rebase your patch to the latest mainline and squash the temp change to the master one.
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906779165
##########
arch/arm64/src/common/arm64_cache.c:
##########
@@ -0,0 +1,458 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cache.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* Common operations for the caches
+ *
+ * WB means write-back and intends to transfer dirty cache lines to memory in
+ * a copy-back cache policy. May be a no-op in write-back cache policy.
+ *
+ * INVD means invalidate and will mark cache lines as not valid. A future
+ * access to the associated address is guaranteed to generate a memory fetch.
+ *
+ * armv8 data cache instruction:
+ *
+ * DC CIVAC (WB+INVD):
+ * Data or unified Cache line Clean and Invalidate by VA to PoC
+ * Clean and Invalidate data cache by address to Point of Coherency.
+ *
+ * DC CVAC (WB):
+ * Data or unified Cache line Clean by VA to PoC
+ * Clean data cache by address to Point of Coherency.
+ *
+ * DC IVAC (INVD):
+ * Data or unified Cache line Invalidate by VA to PoC
+ * Invalidate data cache by address to Point of Coherency
+ */
+
+#define CACHE_OP_WB BIT(0)
+#define CACHE_OP_INVD BIT(1)
+#define CACHE_OP_WB_INVD (CACHE_OP_WB | CACHE_OP_INVD)
+
+#define LINE_MASK(line) ((line) - 1)
+#define LINE_ALIGN_DOWN(a, line) ((a) & ~LINE_MASK(line))
+#define LINE_ALIGN_UP(a, line) \
+ (((a) + LINE_MASK(line)) & ~LINE_MASK(line))
+
+#define dc_ops(op, val) \
+ ({ \
+ __asm__ volatile ("dc " op ", %0" : : "r" (val) : "memory"); \
+ })
+
+/* IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
+ * Purpose
+ * Invalidate all instruction caches in the Inner Shareable domain of
+ * the PE executing the instruction to the Point of Unification.
+ */
+
+static inline void __ic_iallu(void)
+{
+ __asm__ volatile ("ic iallu" : : : "memory");
+}
+
+/* IC IALLU, Instruction Cache Invalidate All to PoU
+ * Purpose
+ * Invalidate all instruction caches of the PE executing
+ * the instruction to the Point of Unification.
+ */
+
+static inline void __ic_ialluis(void)
+{
+ __asm__ volatile ("ic ialluis" : : : "memory");
+}
+
+size_t dcache_line_size;
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* operation for data cache by virtual address to PoC */
+
+static inline int arm64_dcache_range(uintptr_t start_addr,
+ uintptr_t end_addr, int op)
+{
+ /* Align address to line size */
+
+ start_addr = LINE_ALIGN_DOWN(start_addr, dcache_line_size);
+
+ while (start_addr < end_addr)
+ {
+ switch (op)
+ {
+ case CACHE_OP_WB:
+ {
+ dc_ops("cvac", start_addr);
+ break;
+ }
+
+ case CACHE_OP_INVD:
+ {
+ dc_ops("ivac", start_addr);
+ break;
+ }
+
+ case CACHE_OP_WB_INVD:
+ {
+ dc_ops("civac", start_addr);
+ break;
+ }
+
+ default:
+ {
+ assert(1);
Review Comment:
```suggestion
DEBUGASSERT(0);
```
##########
arch/arm64/src/common/arm64_cpu_psci.c:
##########
@@ -0,0 +1,187 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arch/syscall.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+
+#include "arm64_cpu_psci.h"
+
+static struct psci_interface psci_data;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int psci_to_dev_err(int ret)
+{
+ switch (ret)
+ {
+ case PSCI_RET_SUCCESS:
+ {
+ return 0;
+ }
+
+ case PSCI_RET_NOT_SUPPORTED:
+ {
+ return -ENOTSUP;
+ }
+
+ case PSCI_RET_INVALID_PARAMS:
+ case PSCI_RET_INVALID_ADDRESS:
+ {
+ return -EINVAL;
+ }
+
+ case PSCI_RET_DENIED:
+ {
+ return -EPERM;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static unsigned long __invoke_psci_fn_hvc(unsigned long function_id,
+ unsigned long arg0,
+ unsigned long arg1,
+ unsigned long arg2)
+{
+ struct arm64_smccc_res res;
+
+ arm64_smccc_hvc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
+ return res.a0;
+}
+
+static unsigned long __invoke_psci_fn_smc(unsigned long function_id,
+ unsigned long arg0,
+ unsigned long arg1,
+ unsigned long arg2)
+{
+ struct arm64_smccc_res res;
+
+ arm64_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
+ return res.a0;
+}
+
+static uint32_t psci_get_version(void)
+{
+ return psci_data.invoke_psci_fn(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0);
+}
+
+static int set_conduit_method(const char *method)
+{
+ if (!strcmp("hvc", method))
+ {
+ psci_data.conduit = SMCCC_CONDUIT_HVC;
+ psci_data.invoke_psci_fn = __invoke_psci_fn_hvc;
+ }
+ else if (!strcmp("smc", method))
+ {
+ psci_data.conduit = SMCCC_CONDUIT_SMC;
+ psci_data.invoke_psci_fn = __invoke_psci_fn_smc;
+ }
+ else
+ {
+ serr("Invalid conduit method");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int psci_detect(void)
+{
+ uint32_t ver = psci_get_version();
+
+ sinfo("Detected PSCI v%d.%d\n", PSCI_VERSION_MAJOR(ver),
+ PSCI_VERSION_MINOR(ver));
Review Comment:
```suggestion
sinfo("Detected PSCI v%d.%d\n",
PSCI_VERSION_MAJOR(ver), PSCI_VERSION_MINOR(ver));
```
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
+#define GIC_DIST_IGROUPR 0x0080
+#define GIC_DIST_ISENABLER 0x0100
+#define GIC_DIST_ICENABLER 0x0180
+#define GIC_DIST_ISPENDR 0x0200
+#define GIC_DIST_ICPENDR 0x0280
+#define GIC_DIST_ISACTIVER 0x0300
+#define GIC_DIST_ICACTIVER 0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR 0x0800
+#define GIC_DIST_ICFGR 0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR 0x0f00
+
+/* GICD GICR common access macros */
+
+#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD_PIDR2 : Peripheral ID2 Register
+ * bit assignments
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+#define GICD_PIDR2_ARCH_MASK 0xf0
+#define GICD_PIDR2_ARCH_GICV3 0x30
+#define GICD_PIDR2_ARCH_GICV4 0x40
+
+/* GICD_TYPER : Interrupt Controller Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+#define GICD_TYPER_RSS (1U << 26)
+#define GICD_TYPER_LPIS (1U << 17)
+#define GICD_TYPER_MBIS (1U << 16)
+#define GICD_TYPER_ESPI (1U << 8)
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
+#define GICD_TYPER_ESPIS(typer) \
+ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
+
+/* Common Helper Constants */
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
+ ((intid) < GIC_PPI_INT_BASE))
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_NUM_INTR_PER_REG 32
+#define GIC_NUM_CFG_PER_REG 16
+#define GIC_NUM_PRI_PER_REG 4
+
+/* GIC idle priority : value '0xff' will allow all interrupts */
+
+#define GIC_IDLE_PRIO 0xff
+
+/* Priority levels 0:255 */
+
+#define GIC_PRI_MASK 0xff
+
+/* '0xa0'is used to initialize each interrtupt default priority.
+ * This is an arbitrary value in current context.
+ * Any value '0x80' to '0xff' will work for both NS and S state.
+ * The values of individual interrupt and default has to be chosen
+ * carefully if PMR and BPR based nesting and preemption has to be done.
+ */
+
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
+
+/* Register bit definitions */
+
+/* GICD_CTLR Interrupt group definitions */
+#define GICD_CTLR_ENABLE_G0 0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S 2
+#define GICD_CTRL_ARE_S 4
+#define GICD_CTRL_ARE_NS 5
+#define GICD_CTRL_NS 6
+#define GICD_CGRL_E1NWF 7
+
+/* GICD_CTLR Register write progress bit */
+#define GICD_CTLR_RWP 31
+
+/* GICR_CTLR */
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP 3
+
+/* GICD_TYPER.ITLinesNumber 0:4 */
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICR： Re-Distributor registers, offsets from RD_base(n) */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00A0
+#define GICR_INVALLR 0x00B0
+#define GICR_SYNCR 0x00C0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+#define GICR_IDREGS 0xFFD0
+#define GICR_PIDR2 0xFFE8
+
+/* GICR_PIDR2 : Peripheral ID2 Register
+ * bit assignments are the same as those for GICD_PIDR2)
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+
+#define GICR_PIDR2_ARCH_MASK 0xf0
+#define GICR_PIDR2_ARCH_GICV3 0x30
+#define GICR_PIDR2_ARCH_GICV4 0x40
+
+/* GICR_TYPER : Redistributor Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ * chapter 9.11.35 for detail descriptions
+ */
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_DIRECTLPIS (1U << 3)
+#define GICR_TYPER_LAST (1U << 4)
Review Comment:
```suggestion
#define GICR_TYPER_PLPIS BIT(0)
#define GICR_TYPER_VLPIS BIT(1)
#define GICR_TYPER_DIRECTLPIS BIT(3)
#define GICR_TYPER_LAST BIT(4)
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static inline unsigned long gic_get_rdist(void)
+{
+ return gic_rdists[this_cpu()];
+}
+
+static inline uint32_t read_gicd_wait_rwp(void)
+{
+ uint32_t value;
+
+ value = getreg32(GICD_CTLR);
+
+ while (value & BIT(GICD_CTLR_RWP))
+ {
+ value = getreg32(GICD_CTLR);
+ }
+
+ return value;
+}
+
+/* Wait for register write pending
+ * TODO: add timed wait
+ */
+
+static int gic_wait_rwp(uint32_t intid)
+{
+ uint32_t rwp_mask;
+ unsigned long base;
+
+ if (intid < GIC_SPI_INT_BASE)
+ {
+ base = (gic_get_rdist() + GICR_CTLR);
+ rwp_mask = BIT(GICR_CTLR_RWP);
+ }
+ else
+ {
+ base = GICD_CTLR;
+ rwp_mask = BIT(GICD_CTLR_RWP);
+ }
+
+ while (getreg32(base) & rwp_mask)
+ {
+ }
+
+ return 0;
+}
+
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t shift;
+ uint32_t val;
+ unsigned long base = GET_DIST_BASE(intid);
+
+ /* Disable the interrupt */
+
+ putreg32(mask, ICENABLER(base, idx));
+ gic_wait_rwp(intid);
+
+ /* PRIORITYR registers provide byte access */
+
+ putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+
+ /* Interrupt type config */
+
+ if (!GIC_IS_SGI(intid))
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+
+ val = getreg32(ICFGR(base, idx));
+ val &= ~(GICD_ICFGR_MASK << shift);
+ if (flags & IRQ_TYPE_EDGE)
+ {
+ val |= (GICD_ICFGR_TYPE << shift);
+ }
+
+ putreg32(val, ICFGR(base, idx));
+ }
+}
+
+void arm64_gic_irq_enable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+
+ /* Affinity routing is enabled for Non-secure state (GICD_CTLR.ARE_NS
+ * is set to '1' when GIC distributor is initialized) ,so need to set
+ * SPI's affinity, now set it to be the PE on which it is enabled.
+ */
+
+ if (GIC_IS_SPI(intid))
+ {
+ putreg64(MPIDR_TO_CORE(GET_MPIDR()),
+ IROUTER(GET_DIST_BASE(intid), intid));
+ }
+}
+
+void arm64_gic_irq_disable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
+
+ /* poll to ensure write is complete */
+
+ gic_wait_rwp(intid);
+}
+
+bool arm64_gic_irq_is_enabled(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t val;
+
+ val = getreg32(ISENABLER(GET_DIST_BASE(intid), idx));
+
+ return (val & mask) != 0;
+}
+
+unsigned int arm64_gic_get_active(void)
+{
+ int intid;
+
+ /* (Pending -> Active / AP) or (AP -> AP) */
+
+ intid = read_sysreg(ICC_IAR1_EL1);
+
+ return intid;
+}
+
+void arm64_gic_eoi(unsigned int intid)
+{
+ /* Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+
+ __DSB();
+
+ /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
+
+ write_sysreg(intid, ICC_EOIR1_EL1);
+}
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list)
+{
+ uint32_t aff3;
+ uint32_t aff2;
+ uint32_t aff1;
+ uint64_t sgi_val;
+
+ assert(GIC_IS_SGI(sgi_id));
+
+ /* Extract affinity fields from target */
+
+ aff1 = MPIDR_AFFLVL(target_aff, 1);
+ aff2 = MPIDR_AFFLVL(target_aff, 2);
+ aff3 = MPIDR_AFFLVL(target_aff, 3);
+
+ sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF,
+ target_list);
+
+ __DSB();
+ write_sysreg(sgi_val, ICC_SGI1R);
+ __ISB();
+
+ return 0;
+}
+
+/* Wake up GIC redistributor.
+ * clear ProcessorSleep and wait till ChildAsleep is cleared.
+ * ProcessSleep to be cleared only when ChildAsleep is set
+ * Check if redistributor is not powered already.
+ */
+
+static void gicv3_rdist_enable(unsigned long rdist)
+{
+ if (!(getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)))
+ {
+ return;
+ }
+
+ sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
+ while (getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))
+ {
+ }
+}
+
+/* Initialize the cpu interface. This should be called by each core. */
+
+static void gicv3_cpuif_init(void)
+{
+ uint32_t icc_sre;
+ uint32_t intid;
+
+ unsigned long base = gic_get_rdist() + GICR_SGI_BASE_OFF;
+
+ /* Disable all sgi ppi */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0));
+
+ /* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */
+
+ gic_wait_rwp(0);
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, 0));
+
+ /* Configure all SGIs/PPIs as G1S or G1NS depending on Zephyr
+ * is run in EL1S or EL1NS respectively.
+ * All interrupts will be delivered as irq
+ */
+
+ putreg32(IGROUPR_VAL, IGROUPR(base, 0));
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, 0));
+
+ /* Configure default priorities for SGI 0:15 and PPI 0:15. */
+
+ for (intid = 0; intid < GIC_SPI_INT_BASE;
+ intid += GIC_NUM_PRI_PER_REG)
+ {
+ putreg32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
+ }
+
+ /* Configure PPIs as level triggered */
+
+ putreg32(0, ICFGR(base, 1));
+
+ /* Check if system interface can be enabled.
+ * 'icc_sre_el3' needs to be configured at 'EL3'
+ * to allow access to 'icc_sre_el1' at 'EL1'
+ * eg: z_arch_el3_plat_init can be used by platform.
+ */
+
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ if (!(icc_sre & ICC_SRE_ELX_SRE_BIT))
+ {
+ icc_sre =
+ (icc_sre | ICC_SRE_ELX_SRE_BIT | ICC_SRE_ELX_DIB_BIT |
+ ICC_SRE_ELX_DFB_BIT);
+ write_sysreg(icc_sre, ICC_SRE_EL1);
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ assert(icc_sre & ICC_SRE_ELX_SRE_BIT);
+ }
+
+ write_sysreg(GIC_IDLE_PRIO, ICC_PMR_EL1);
+
+ /* Allow group1 interrupts */
+
+ write_sysreg(1, ICC_IGRPEN1_EL1);
+}
+
+static void gicv3_dist_init(void)
+{
+ unsigned int num_ints;
+ unsigned int intid;
+ unsigned int idx;
+ unsigned long base = GIC_DIST_BASE;
+
+ num_ints = getreg32(GICD_TYPER);
+ num_ints &= GICD_TYPER_ITLINESNUM_MASK;
+ num_ints = (num_ints + 1) << 5;
+
+ /* Disable the distributor */
+
+ putreg32(0, GICD_CTLR);
+ gic_wait_rwp(GIC_SPI_INT_BASE);
+
+#if 0
+
+ /* Before configuration, we need to check whether
+ * the GIC single security state mode is supported.
+ * Make sure GICD_CTRL_NS is 1.
+ */
+
+ sys_set_bit(GICD_CTLR, GICD_CTRL_NS);
+ __ASSERT(sys_test_bit(GICD_CTLR,
+ GICD_CTRL_NS),
+ "Current GIC does not support single security state");
+#endif
+
+ /* Default configuration of all SPIs */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_INTR_PER_REG)
+ {
+ idx = intid / GIC_NUM_INTR_PER_REG;
+
+ /* Disable interrupt */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICENABLER(base, idx));
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICPENDR(base, idx));
+ putreg32(IGROUPR_VAL, IGROUPR(base, idx));
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ IGROUPMODR(base, idx));
Review Comment:
```suggestion
putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
IGROUPMODR(base, idx));
```
##########
arch/arm64/src/common/arm64_initialstate.c:
##########
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialstate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tcb)
+{
+ char * stack_ptr = tcb->stack_base_ptr + tcb->adj_stack_size;
+ struct regs_context * pinitctx;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * pfpuctx;
+ pfpuctx = STACK_PTR_TO_FRAME(struct fpu_reg, stack_ptr);
+ tcb->xcp.fpu_regs = pfpuctx;
+
+ /* set fpu context */
+
+ arm64_init_fpu(tcb);
+ stack_ptr = (char *)pfpuctx;
+#endif
+
+ pinitctx = STACK_PTR_TO_FRAME(struct regs_context, stack_ptr);
+ memset(pinitctx, 0, sizeof(struct regs_context));
+ pinitctx->elr = (uint64_t)tcb->start;
+
+ /* Keep using SP_EL1 */
+
+ pinitctx->spsr = SPSR_MODE_EL1H;
+
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ pinitctx->spsr |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT);
+#endif /* CONFIG_SUPPRESS_INTERRUPTS */
+
+ pinitctx->sp_elx = (uint64_t)pinitctx;
+ pinitctx->sp_el0 = (uint64_t)pinitctx;
+ pinitctx->exe_depth = 0;
+ pinitctx->tpidr_el0 = (uint64_t)tcb;
+ pinitctx->tpidr_el1 = (uint64_t)tcb;
+
+ tcb->xcp.regs = (uint64_t *)pinitctx;
Review Comment:
```suggestion
pinitctx->tpidr_el1 = (uint64_t)tcb;
tcb->xcp.regs = (uint64_t *)pinitctx;
```
##########
arch/arm64/src/common/arm64_cache.c:
##########
@@ -0,0 +1,458 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cache.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* Common operations for the caches
+ *
+ * WB means write-back and intends to transfer dirty cache lines to memory in
+ * a copy-back cache policy. May be a no-op in write-back cache policy.
+ *
+ * INVD means invalidate and will mark cache lines as not valid. A future
+ * access to the associated address is guaranteed to generate a memory fetch.
+ *
+ * armv8 data cache instruction:
+ *
+ * DC CIVAC (WB+INVD):
+ * Data or unified Cache line Clean and Invalidate by VA to PoC
+ * Clean and Invalidate data cache by address to Point of Coherency.
+ *
+ * DC CVAC (WB):
+ * Data or unified Cache line Clean by VA to PoC
+ * Clean data cache by address to Point of Coherency.
+ *
+ * DC IVAC (INVD):
+ * Data or unified Cache line Invalidate by VA to PoC
+ * Invalidate data cache by address to Point of Coherency
+ */
+
+#define CACHE_OP_WB BIT(0)
+#define CACHE_OP_INVD BIT(1)
+#define CACHE_OP_WB_INVD (CACHE_OP_WB | CACHE_OP_INVD)
+
+#define LINE_MASK(line) ((line) - 1)
+#define LINE_ALIGN_DOWN(a, line) ((a) & ~LINE_MASK(line))
+#define LINE_ALIGN_UP(a, line) \
+ (((a) + LINE_MASK(line)) & ~LINE_MASK(line))
+
+#define dc_ops(op, val) \
+ ({ \
+ __asm__ volatile ("dc " op ", %0" : : "r" (val) : "memory"); \
+ })
+
+/* IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
+ * Purpose
+ * Invalidate all instruction caches in the Inner Shareable domain of
+ * the PE executing the instruction to the Point of Unification.
+ */
+
+static inline void __ic_iallu(void)
+{
+ __asm__ volatile ("ic iallu" : : : "memory");
+}
+
+/* IC IALLU, Instruction Cache Invalidate All to PoU
+ * Purpose
+ * Invalidate all instruction caches of the PE executing
+ * the instruction to the Point of Unification.
+ */
+
+static inline void __ic_ialluis(void)
+{
+ __asm__ volatile ("ic ialluis" : : : "memory");
+}
+
+size_t dcache_line_size;
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* operation for data cache by virtual address to PoC */
+
+static inline int arm64_dcache_range(uintptr_t start_addr,
+ uintptr_t end_addr, int op)
+{
+ /* Align address to line size */
+
+ start_addr = LINE_ALIGN_DOWN(start_addr, dcache_line_size);
+
+ while (start_addr < end_addr)
+ {
+ switch (op)
+ {
+ case CACHE_OP_WB:
+ {
+ dc_ops("cvac", start_addr);
+ break;
+ }
+
+ case CACHE_OP_INVD:
+ {
+ dc_ops("ivac", start_addr);
+ break;
+ }
+
+ case CACHE_OP_WB_INVD:
+ {
+ dc_ops("civac", start_addr);
+ break;
+ }
+
+ default:
+ {
+ assert(1);
+ }
+ }
+ start_addr += dcache_line_size;
+ }
+
+ __DSB();
+
+ return 0;
+}
+
+/* operation for all data cache */
+
+static inline int arm64_dcache_all(int op)
+{
+ uint32_t clidr_el1;
+ uint32_t csselr_el1;
+ uint32_t ccsidr_el1;
+ uint8_t loc;
+ uint8_t ctype;
+ uint8_t cache_level;
+ uint8_t line_size;
+ uint8_t way_pos;
+ uint32_t max_ways;
+ uint32_t max_sets;
+ uint32_t dc_val;
+ uint32_t set;
+ uint32_t way;
+
+ /* Data barrier before start */
+
+ __DSB();
+
+ clidr_el1 = read_sysreg(clidr_el1);
+
+ loc = (clidr_el1 >> CLIDR_EL1_LOC_SHIFT) & CLIDR_EL1_LOC_MASK;
+ if (!loc)
+ {
+ return 0;
+ }
+
+ for (cache_level = 0; cache_level < loc; cache_level++)
+ {
+ ctype =
+ (clidr_el1 >>
+ CLIDR_EL1_CTYPE_SHIFT(cache_level)) & CLIDR_EL1_CTYPE_MASK;
+
+ /* No data cache, continue */
+
+ if (ctype < 2)
+ {
+ continue;
+ }
+
+ /* select cache level */
+
+ csselr_el1 = cache_level << 1;
+ write_sysreg(csselr_el1, csselr_el1);
+ __ISB();
+
+ ccsidr_el1 = read_sysreg(ccsidr_el1);
+ line_size =
+ (ccsidr_el1 >> CCSIDR_EL1_LN_SZ_SHIFT & CCSIDR_EL1_LN_SZ_MASK) + 4;
+ max_ways =
+ (ccsidr_el1 >> CCSIDR_EL1_WAYS_SHIFT) & CCSIDR_EL1_WAYS_MASK;
+ max_sets =
+ (ccsidr_el1 >> CCSIDR_EL1_SETS_SHIFT) & CCSIDR_EL1_SETS_MASK;
+
+ /* 32-log2(ways), bit position of way in DC operand */
+
+ way_pos = __builtin_clz(max_ways);
+
+ for (set = 0; set <= max_sets; set++)
+ {
+ for (way = 0; way <= max_ways; way++)
+ {
+ /* way number, aligned to pos in DC operand */
+
+ dc_val = way << way_pos;
+
+ /* cache level, aligned to pos in DC operand */
+
+ dc_val |= csselr_el1;
+
+ /* set number, aligned to pos in DC operand */
+
+ dc_val |= set << line_size;
+ switch (op)
+ {
+ case CACHE_OP_WB:
+ {
+ dc_ops("csw", dc_val);
+ break;
+ }
+
+ case CACHE_OP_INVD:
+ {
+ dc_ops("isw", dc_val);
+ break;
+ }
+
+ case CACHE_OP_WB_INVD:
+ {
+ dc_ops("cisw", dc_val);
+ break;
+ }
+ default:
+ {
+ assert(1);
Review Comment:
```suggestion
DEBUGASSERT(0);
```
##########
arch/arm64/src/common/arm64_cpu_psci.c:
##########
@@ -0,0 +1,187 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arch/syscall.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+
+#include "arm64_cpu_psci.h"
+
+static struct psci_interface psci_data;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int psci_to_dev_err(int ret)
+{
+ switch (ret)
+ {
+ case PSCI_RET_SUCCESS:
+ {
+ return 0;
+ }
+
+ case PSCI_RET_NOT_SUPPORTED:
+ {
+ return -ENOTSUP;
+ }
+
+ case PSCI_RET_INVALID_PARAMS:
+ case PSCI_RET_INVALID_ADDRESS:
+ {
+ return -EINVAL;
+ }
+
+ case PSCI_RET_DENIED:
+ {
+ return -EPERM;
+ }
Review Comment:
add 2 more spaces for this block
##########
arch/arm64/src/common/arm64_cpustart.c:
##########
@@ -0,0 +1,266 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpustart.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/sched_note.h>
+#include <sched/sched.h>
+#include <nuttx/cache.h>
+#include <arch/spinlock.h>
+#include <nuttx/init.h>
+
+#include "init/init.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+#include "arm64_smp.h"
+#include "arm64_cpu_psci.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+typedef void (*arm64_cpustart_t)(void *data);
+
+struct arm64_boot_params
+{
+ uint64_t mpid;
+ char *boot_sp;
+ arm64_cpustart_t func;
+ void *arg;
+ int cpu_num;
+};
Review Comment:
Please add Types section
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <arch/syscall.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+#define PSCI_RET_INVALID_ADDRESS -9
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+uint32_t psci_version(void);
+
+typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long,
Review Comment:
Please re-order this to sections: Types, Public Functions, etc.
##########
arch/arm64/src/common/arm64_cpustart.c:
##########
@@ -0,0 +1,266 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpustart.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/sched_note.h>
+#include <sched/sched.h>
+#include <nuttx/cache.h>
+#include <arch/spinlock.h>
+#include <nuttx/init.h>
+
+#include "init/init.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+#include "arm64_smp.h"
+#include "arm64_cpu_psci.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+typedef void (*arm64_cpustart_t)(void *data);
+
+struct arm64_boot_params
+{
+ uint64_t mpid;
+ char *boot_sp;
+ arm64_cpustart_t func;
+ void *arg;
+ int cpu_num;
+};
+
+volatile struct arm64_boot_params aligned_data(L1_CACHE_BYTES)
+cpu_boot_params =
+{
+ .mpid = -1,
+ .boot_sp = (char *)g_cpu_idlestackalloc[0],
+};
+
+volatile uint64_t *g_cpu_int_stacktop[CONFIG_SMP_NCPUS] =
+{
+ (uint64_t *)(g_interrupt_stacks[0] + INTSTACK_SIZE),
+};
+
+/****************************************************************************
+ * Private data
+ ****************************************************************************/
+
+volatile static long cpu_ready_flag;
Review Comment:
```suggestion
static volatile long cpu_ready_flag;
```
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
+
+ /* for statistic propose */
+
+ int save_count;
+ int restore_count;
+ int switch_count;
+ int exe_depth_count;
+};
+
+static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS];
Review Comment:
Please move to Private Data
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
Review Comment:
Please move to Private Data
##########
arch/arm64/src/common/arm64_fatal.c:
##########
@@ -0,0 +1,360 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <debug.h>
+#include <assert.h>
+#include <sched.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/tls.h>
+#include <nuttx/board.h>
+#include <arch/chip/chip.h>
+#include <nuttx/syslog/syslog.h>
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+#include "arm64_fatal.h"
+#include "arm64_arch_timer.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: print_ec_cause
+ ****************************************************************************/
+
+static void print_ec_cause(uint64_t esr)
+{
+ uint32_t ec = (uint32_t)esr >> 26;
+
+ switch (ec)
+ {
+ case 0b000000:
+ {
+ sinfo("Unknown reason\n");
+ break;
+ }
+
+ case 0b000001:
+ {
+ sinfo("Trapped WFI or WFE instruction execution\n");
+ break;
+ }
+
+ case 0b000011:
+ {
+ sinfo(
+ "Trapped MCR or MRC access with (coproc==0b1111) that "
+ "is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000100:
+ {
+ sinfo(
+ "Trapped MCRR or MRRC access with (coproc==0b1111) "
+ "that is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000101:
+ {
+ sinfo("Trapped MCR or MRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b000110:
+ {
+ sinfo("Trapped LDC or STC access\n");
+ break;
Review Comment:
Please add 2 spaces more to this block
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+
+struct arm64_cpu_fpu_context
Review Comment:
Please move to Types
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
+
+ /* for statistic propose */
+
+ int save_count;
+ int restore_count;
+ int switch_count;
+ int exe_depth_count;
+};
+
+static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/***************************************************************************
+ * Public Functions
+ ***************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb)
+{
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ memset(&g_cpu_fpu_ctx[this_cpu()], 0,
+ sizeof(struct arm64_cpu_fpu_context));
+ g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb;
+
+ tcb->xcp.fpu_regs = &g_idle_thread_fpu[this_cpu()];
+ }
+
+ memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg));
+ tcb->xcp.fpu_regs->fpu_trap = 0;
+}
+
+void arm64_destory_fpu(struct tcb_s * tcb)
+{
+ struct tcb_s * owner;
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner == tcb)
+ {
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+}
+
+/* enable FPU access trap */
+
+static void arm64_fpu_access_trap_enable(void)
Review Comment:
Please add prototype to Private Functions Prototypes and re-order to separate Private Functions from Public Functions
##########
arch/arm64/src/common/arm64_fatal.c:
##########
@@ -0,0 +1,360 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <debug.h>
+#include <assert.h>
+#include <sched.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/tls.h>
+#include <nuttx/board.h>
+#include <arch/chip/chip.h>
+#include <nuttx/syslog/syslog.h>
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+#include "arm64_fatal.h"
+#include "arm64_arch_timer.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: print_ec_cause
+ ****************************************************************************/
+
+static void print_ec_cause(uint64_t esr)
+{
+ uint32_t ec = (uint32_t)esr >> 26;
+
+ switch (ec)
+ {
+ case 0b000000:
+ {
+ sinfo("Unknown reason\n");
+ break;
+ }
+
+ case 0b000001:
+ {
+ sinfo("Trapped WFI or WFE instruction execution\n");
+ break;
+ }
+
+ case 0b000011:
+ {
+ sinfo(
+ "Trapped MCR or MRC access with (coproc==0b1111) that "
+ "is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000100:
+ {
+ sinfo(
+ "Trapped MCRR or MRRC access with (coproc==0b1111) "
+ "that is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000101:
+ {
+ sinfo("Trapped MCR or MRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b000110:
+ {
+ sinfo("Trapped LDC or STC access\n");
+ break;
+ }
+
+ case 0b000111:
+ {
+ sinfo(
+ "Trapped access to SVE, Advanced SIMD, or "
+ "floating-point functionality\n");
+ break;
+ }
+
+ case 0b001100:
+ {
+ sinfo("Trapped MRRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b001101:
+ {
+ sinfo("Branch Target Exception\n");
+ break;
+ }
+
+ case 0b001110:
+ {
+ sinfo("Illegal Execution state\n");
+ break;
+ }
+
+ case 0b010001:
+ {
+ sinfo("SVC instruction execution in AArch32 state\n");
+ break;
+ }
+
+ case 0b011000:
+ {
+ sinfo(
+ "Trapped MSR, MRS or System instruction execution in "
+ "AArch64 state, that is not reported using EC "
+ "0b000000, 0b000001 or 0b000111\n");
+ break;
+ }
+
+ case 0b011001:
+ {
+ sinfo("Trapped access to SVE functionality\n");
+ break;
+ }
+
+ case 0b100000:
+ {
+ sinfo(
+ "Instruction Abort from a lower Exception level, that "
+ "might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b100001:
+ {
+ sinfo(
+ "Instruction Abort taken without a change in Exception level.\n");
+ break;
+ }
+
+ case 0b100010:
+ {
+ sinfo("PC alignment fault exception.\n");
+ break;
+ }
+
+ case 0b100100:
+ {
+ sinfo(
+ "Data Abort from a lower Exception level, that might "
+ "be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b100101:
+ {
+ sinfo("Data Abort taken without a change in Exception level\n");
+ break;
+ }
+
+ case 0b100110:
+ {
+ sinfo("SP alignment fault exception\n");
+ break;
+ }
+
+ case 0b101000:
+ {
+ sinfo("Trapped floating-point exception taken from AArch32 state\n");
+ break;
+ }
+
+ case 0b101100:
+ {
+ sinfo("Trapped floating-point exception taken from AArch64 state.\n");
+ break;
+ }
+
+ case 0b101111:
+ {
+ sinfo("SError interrupt\n");
+ break;
+ }
+
+ case 0b110000:
+ {
+ sinfo(
+ "Breakpoint exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110001:
+ {
+ sinfo(
+ "Breakpoint exception taken without a change in "
+ "Exception level\n");
+ break;
+ }
+
+ case 0b110010:
+ {
+ sinfo(
+ "Software Step exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110011:
+ {
+ sinfo(
+ "Software Step exception taken without a change in "
+ "Exception level\n");
+ break;
+ }
+
+ case 0b110100:
+ {
+ sinfo(
+ "Watchpoint exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110101:
+ {
+ sinfo(
+ "Watchpoint exception taken without a change in "
+ "Exception level.\n");
+ break;
+ }
+
+ case 0b111000:
+ {
+ sinfo("BKPT instruction execution in AArch32 state\n");
+ break;
+ }
+
+ case 0b111100:
+ {
+ sinfo("BRK instruction execution in AArch64 state.\n");
+ break;
+ }
+
+ default:
+ break;
+ }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_fatal_error
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void arm64_fatal_error(unsigned int reason, struct regs_context * reg)
+{
+ uint64_t el, esr, elr, far;
+ int cpu = up_cpu_index();
+
+ sinfo("reason = %d\n", reason);
+ sinfo("arm64_fatal_error: CPU%d task: %s\n", cpu, running_task()->name);
+
+ if (reason != K_ERR_SPURIOUS_IRQ)
+ {
+ __asm__ volatile ("mrs %0, CurrentEL" : "=r" (el));
+
+ switch (GET_EL(el))
+ {
+ case MODE_EL1:
+ {
+ sinfo("CurrentEL: MODE_EL1\n");
+ __asm__ volatile ("mrs %0, esr_el1" : "=r" (esr));
+ __asm__ volatile ("mrs %0, far_el1" : "=r" (far));
+ __asm__ volatile ("mrs %0, elr_el1" : "=r" (elr));
+ break;
+ }
+
+ case MODE_EL2:
+ {
+ sinfo("CurrentEL: MODE_EL2\n");
+ __asm__ volatile ("mrs %0, esr_el2" : "=r" (esr));
+ __asm__ volatile ("mrs %0, far_el2" : "=r" (far));
+ __asm__ volatile ("mrs %0, elr_el2" : "=r" (elr));
+ break;
+ }
+
+ case MODE_EL3:
+ {
+ sinfo("CurrentEL: MODE_EL3\n");
+ __asm__ volatile ("mrs %0, esr_el3" : "=r" (esr));
+ __asm__ volatile ("mrs %0, far_el3" : "=r" (far));
+ __asm__ volatile ("mrs %0, elr_el3" : "=r" (elr));
+ break;
+ }
+
+ default:
+ {
+ sinfo("CurrentEL: unknown\n");
+
Review Comment:
Please add 2 more spaces to this block
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,606 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#include "arm64_trace_printf.h"
+
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one
+ * complete table */
+#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX 3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+ (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+
+#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT \
+ (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT \
+ (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT \
+ (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+ (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+ (XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+ ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21) - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \
+ ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \
+ ? 0U \
+ : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \
+ ? 1U \
+ : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \
+ ? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \
+ (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
+ CONFIG_ARM64_VA_BITS)
+
+static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
+ NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
+
+static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+
+#if (CONFIG_ARM64_PA_BITS == 48)
+#define TCR_PS_BITS TCR_PS_BITS_256TB
+#elif (CONFIG_ARM64_PA_BITS == 44)
+#define TCR_PS_BITS TCR_PS_BITS_16TB
+#elif (CONFIG_ARM64_PA_BITS == 42)
+#define TCR_PS_BITS TCR_PS_BITS_4TB
+#elif (CONFIG_ARM64_PA_BITS == 40)
+#define TCR_PS_BITS TCR_PS_BITS_1TB
+#elif (CONFIG_ARM64_PA_BITS == 36)
+#define TCR_PS_BITS TCR_PS_BITS_64GB
+#else
+#define TCR_PS_BITS TCR_PS_BITS_4GB
+#endif
+
+/* Translation table control register settings */
+
+static uint64_t get_tcr(int el)
+{
+ uint64_t tcr;
+ uint64_t va_bits = CONFIG_ARM64_VA_BITS;
+ uint64_t tcr_ps_bits;
+
+ tcr_ps_bits = TCR_PS_BITS;
+
+ if (el == 1)
+ {
+ tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+
+ /* TCR_EL1.EPD1: Disable translation table walk for addresses
+ * that are translated using TTBR1_EL1.
+ */
+
+ tcr |= TCR_EPD1_DISABLE;
+ }
+ else
+ {
+ tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+ }
+
+ tcr |= TCR_T0SZ(va_bits);
+
+ /* Translation table walk is cacheable, inner/outer WBWA and
+ * inner shareable
+ */
+
+ tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+ return tcr;
+}
+
+static int pte_desc_type(uint64_t *pte)
+{
+ return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static uint64_t *calculate_pte_index(uint64_t addr, int level)
+{
+ int base_level = XLAT_TABLE_BASE_LEVEL;
+ uint64_t *pte;
+ uint64_t idx;
+ unsigned int i;
+
+ /* Walk through all translation tables to find pte index */
+
+ pte = (uint64_t *)base_xlat_table;
+ for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++)
+ {
+ idx = XLAT_TABLE_VA_IDX(addr, i);
+ pte += idx;
+
+ /* Found pte index */
+
+ if (i == level)
+ {
+ return pte;
+ }
+
+ /* if PTE is not table desc, can't traverse */
+
+ if (pte_desc_type(pte) != PTE_TABLE_DESC)
+ {
+ return NULL;
+ }
+
+ /* Move to the next translation table level */
+
+ pte = (uint64_t *)(*pte & 0x0000fffffffff000);
+ }
+
+ return NULL;
+}
+
+static void set_pte_table_desc(uint64_t *pte, uint64_t *table,
+ unsigned int level)
+{
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: [Table] %p\n", pte, table);
+#endif
+
+ /* Point pte to new table */
+
+ *pte = PTE_TABLE_DESC | (uint64_t)table;
+}
+
+static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
+ unsigned int attrs, unsigned int level)
+{
+ uint64_t desc = addr_pa;
+ unsigned int mem_type;
+
+ desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+ /* NS bit for security memory access from secure state */
+
+ desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+ /* AP bits for Data access permission */
+
+ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+ /* the access flag */
+
+ desc |= PTE_BLOCK_DESC_AF;
+
+ /* memory attribute index field */
+
+ mem_type = MT_TYPE(attrs);
+ desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+ switch (mem_type)
+ {
+ case MT_DEVICE_NGNRNE:
+ case MT_DEVICE_NGNRE:
+ case MT_DEVICE_GRE:
+ {
+ /* Access to Device memory and non-cacheable memory are coherent
+ * for all observers in the system and are treated as
+ * Outer shareable, so, for these 2 types of memory,
+ * it is not strictly needed to set shareability field
+ */
+
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+
+ /* Map device memory as execute-never */
+
+ desc |= PTE_BLOCK_DESC_PXN;
+ desc |= PTE_BLOCK_DESC_UXN;
+ break;
+ }
+
+ case MT_NORMAL_NC:
+ case MT_NORMAL:
+ {
+ /* Make Normal RW memory as execute never */
+
+ if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+ {
+ desc |= PTE_BLOCK_DESC_PXN;
+ }
+ if (mem_type == MT_NORMAL)
+ {
+ desc |= PTE_BLOCK_DESC_INNER_SHARE;
+ }
+ else
+ {
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+ }
+ }
+ }
+
+#if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE)
+ sinfo("%s ", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: ", pte);
+ sinfo("%s ",
+ (mem_type ==
+ MT_NORMAL) ? "MEM" :((mem_type == MT_NORMAL_NC) ? "NC" : "DEV"));
+ sinfo("%s ", (attrs & MT_RW) ? "-RW" : "-RO");
+ sinfo("%s ", (attrs & MT_NS) ? "-NS" : "-S");
+ sinfo("%s ", (attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC");
+ sinfo("\n");
+#endif
+
+ *pte = desc;
+}
+
+/* Returns a new reallocated table */
+
+static uint64_t *new_prealloc_table(void)
+{
+ static unsigned int table_idx;
+
+ __MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
+ "Enough xlat tables not allocated");
+
+ return (uint64_t *)(xlat_tables[table_idx++]);
+}
+
+/* Splits a block into table with entries spanning the old block */
+
+static void split_pte_block_desc(uint64_t *pte, int level)
+{
+ uint64_t old_block_desc = *pte;
+ uint64_t *new_table;
+ unsigned int i = 0;
+
+ /* get address size shift bits for next level */
+
+ int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1);
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("Splitting existing PTE %p(L%d)\n", pte, level);
+#endif
+
+ new_table = new_prealloc_table();
+
+ for (i = 0; i < XLAT_TABLE_ENTRIES; i++)
+ {
+ new_table[i] = old_block_desc | (i << levelshift);
+
+ if ((level + 1) == 3)
+ {
+ new_table[i] |= PTE_PAGE_DESC;
+ }
+ }
+
+ /* Overwrite existing PTE set the new table into effect */
+
+ set_pte_table_desc(pte, new_table, level);
+}
+
+/* Create/Populate translation table(s) for given region */
+
+static void init_xlat_tables(const struct arm_mmu_region *region)
+{
+ uint64_t *pte;
+ uint64_t virt = region->base_va;
+ uint64_t phys = region->base_pa;
+ uint64_t size = region->size;
+ uint64_t attrs = region->attrs;
+ uint64_t level_size;
+ uint64_t *new_table;
+ unsigned int level = XLAT_TABLE_BASE_LEVEL;
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("mmap: virt %llx phys %llx size %llx\n", virt, phys, size);
+#endif
+
+ /* check minimum alignment requirement for given mmap region */
+
+ __MMU_ASSERT(((virt & (PAGE_SIZE - 1)) == 0) &&
+ ((size & (PAGE_SIZE - 1)) == 0),
+ "address/size are not page aligned\n");
+
+ while (size)
+ {
+ __MMU_ASSERT(level <= XLAT_TABLE_LEVEL_MAX,
+ "max translation table level exceeded\n");
+
Review Comment:
```suggestion
__MMU_ASSERT(level <= XLAT_TABLE_LEVEL_MAX,
"max translation table level exceeded\n");
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
Review Comment:
It's good to add `{}` for the `if`
##########
arch/arm64/src/common/arm64_schedulesigaction.c:
##########
@@ -0,0 +1,361 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_schedulesigaction.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "sched/sched.h"
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+#include "irq/irq.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_init_signal_process(struct tcb_s *tcb)
+{
+ struct regs_context * pctx = (struct regs_context *)tcb->xcp.regs;
+ struct regs_context * psigctx;
+ char * stack_ptr = (char *)pctx->sp_elx;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * pfpuctx;
Review Comment:
```suggestion
struct regs_context *pctx = (struct regs_context *)tcb->xcp.regs;
struct regs_context *psigctx;
char *stack_ptr = (char *)pctx->sp_elx;
#ifdef CONFIG_ARCH_FPU
struct fpu_reg *pfpuctx;
```
##########
arch/arm64/src/common/arm64_mmu.h:
##########
@@ -0,0 +1,246 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+#define __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Following Memory types supported through MAIR encodings can be passed
+ * by user through "attrs"(attributes) field of specified memory region.
+ * As MAIR supports such 8 encodings, we will reserve attrs[2:0];
+ * so that we can provide encodings upto 7 if needed in future.
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a, B2.7.2
+ */
+#define MT_TYPE_MASK 0x7U
+#define MT_TYPE(attr) (attr & MT_TYPE_MASK)
+#define MT_DEVICE_NGNRNE 0U
+#define MT_DEVICE_NGNRE 1U
+#define MT_DEVICE_GRE 2U
+#define MT_NORMAL_NC 3U
+#define MT_NORMAL 4U
+
+#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
+ (0x04 << (MT_DEVICE_NGNRE * 8)) | \
+ (0x0c << (MT_DEVICE_GRE * 8)) | \
+ (0x44 << (MT_NORMAL_NC * 8)) | \
+ (0xffUL << (MT_NORMAL * 8)))
+
+/* More flags from user's perpective are supported using remaining bits
+ * of "attrs" field, i.e. attrs[31:3], underlying code will take care
+ * of setting PTE fields correctly.
+ *
+ * current usage of attrs[31:3] is:
+ * attrs[3] : Access Permissions
+ * attrs[4] : Memory access from secure/ns state
+ * attrs[5] : Execute Permissions
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a
+ */
+
+#define MT_PERM_SHIFT 3U
+#define MT_SEC_SHIFT 4U
+#define MT_EXECUTE_SHIFT 5U
+
+#define MT_RO (0U << MT_PERM_SHIFT)
+#define MT_RW (1U << MT_PERM_SHIFT)
+
+#define MT_SECURE (0U << MT_SEC_SHIFT)
+#define MT_NS (1U << MT_SEC_SHIFT)
+
+#define MT_EXECUTE (0U << MT_EXECUTE_SHIFT)
+#define MT_EXECUTE_NEVER (1U << MT_EXECUTE_SHIFT)
+
+/* Some compound attributes for most common usages */
+
+#define MT_CODE (MT_NORMAL | MT_RO | MT_EXECUTE)
+#define MT_RODATA (MT_NORMAL | MT_RO | MT_EXECUTE_NEVER)
+
+/* PTE descriptor can be Block descriptor or Table descriptor
+ * or Page descriptor.
+ */
+
+#define PTE_DESC_TYPE_MASK 3U
+#define PTE_BLOCK_DESC 1U
+#define PTE_TABLE_DESC 3U
+#define PTE_PAGE_DESC 3U
+#define PTE_INVALID_DESC 0U
+
+/* Block and Page descriptor attributes fields */
+
+#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2)
Review Comment:
```suggestion
#define PTE_BLOCK_DESC_MEMTYPE(x) ((x) << 2)
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp & ~(1 << bit);
Review Comment:
Optional
```suggestion
*(volatile uint32_t *)addr = temp & ~BIT(bit);
```
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
+#define GIC_DIST_IGROUPR 0x0080
+#define GIC_DIST_ISENABLER 0x0100
+#define GIC_DIST_ICENABLER 0x0180
+#define GIC_DIST_ISPENDR 0x0200
+#define GIC_DIST_ICPENDR 0x0280
+#define GIC_DIST_ISACTIVER 0x0300
+#define GIC_DIST_ICACTIVER 0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR 0x0800
+#define GIC_DIST_ICFGR 0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR 0x0f00
+
+/* GICD GICR common access macros */
+
+#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD_PIDR2 : Peripheral ID2 Register
+ * bit assignments
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+#define GICD_PIDR2_ARCH_MASK 0xf0
+#define GICD_PIDR2_ARCH_GICV3 0x30
+#define GICD_PIDR2_ARCH_GICV4 0x40
+
+/* GICD_TYPER : Interrupt Controller Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+#define GICD_TYPER_RSS (1U << 26)
+#define GICD_TYPER_LPIS (1U << 17)
+#define GICD_TYPER_MBIS (1U << 16)
+#define GICD_TYPER_ESPI (1U << 8)
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
+#define GICD_TYPER_ESPIS(typer) \
+ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
+
+/* Common Helper Constants */
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
+ ((intid) < GIC_PPI_INT_BASE))
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_NUM_INTR_PER_REG 32
+#define GIC_NUM_CFG_PER_REG 16
+#define GIC_NUM_PRI_PER_REG 4
+
+/* GIC idle priority : value '0xff' will allow all interrupts */
+
+#define GIC_IDLE_PRIO 0xff
+
+/* Priority levels 0:255 */
+
+#define GIC_PRI_MASK 0xff
+
+/* '0xa0'is used to initialize each interrtupt default priority.
+ * This is an arbitrary value in current context.
+ * Any value '0x80' to '0xff' will work for both NS and S state.
+ * The values of individual interrupt and default has to be chosen
+ * carefully if PMR and BPR based nesting and preemption has to be done.
+ */
+
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
+
+/* Register bit definitions */
+
+/* GICD_CTLR Interrupt group definitions */
+#define GICD_CTLR_ENABLE_G0 0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S 2
+#define GICD_CTRL_ARE_S 4
+#define GICD_CTRL_ARE_NS 5
+#define GICD_CTRL_NS 6
+#define GICD_CGRL_E1NWF 7
+
+/* GICD_CTLR Register write progress bit */
+#define GICD_CTLR_RWP 31
+
+/* GICR_CTLR */
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP 3
+
+/* GICD_TYPER.ITLinesNumber 0:4 */
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICR： Re-Distributor registers, offsets from RD_base(n) */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00A0
+#define GICR_INVALLR 0x00B0
+#define GICR_SYNCR 0x00C0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+#define GICR_IDREGS 0xFFD0
+#define GICR_PIDR2 0xFFE8
+
+/* GICR_PIDR2 : Peripheral ID2 Register
+ * bit assignments are the same as those for GICD_PIDR2)
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+
+#define GICR_PIDR2_ARCH_MASK 0xf0
+#define GICR_PIDR2_ARCH_GICV3 0x30
+#define GICR_PIDR2_ARCH_GICV4 0x40
+
+/* GICR_TYPER : Redistributor Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ * chapter 9.11.35 for detail descriptions
+ */
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_DIRECTLPIS (1U << 3)
+#define GICR_TYPER_LAST (1U << 4)
+
+/* GICR_WAKER */
+#define GICR_WAKER_PS 1
+#define GICR_WAKER_CA 2
+
+/* SGI base is at 64K offset from Redistributor */
+#define GICR_SGI_BASE_OFF 0x10000
+
+/* GICD_ICFGR */
+#define GICD_ICFGR_MASK BIT_MASK(2)
+#define GICD_ICFGR_TYPE BIT(1)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_SPI_MAX_INTID 1019
+#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \
+ ((intid) <= GIC_SPI_MAX_INTID))
+
+/* GITCD_IROUTER */
+#define GIC_DIST_IROUTER 0x6000
+#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define IRQ_DEFAULT_PRIORITY 0xa0
+
+#define GIC_IRQ_SGI0 0
+#define GIC_IRQ_SGI1 1
+#define GIC_IRQ_SGI2 2
+#define GIC_IRQ_SGI3 3
+#define GIC_IRQ_SGI4 4
+#define GIC_IRQ_SGI5 5
+#define GIC_IRQ_SGI6 6
+#define GIC_IRQ_SGI7 7
+#define GIC_IRQ_SGI8 8
+#define GIC_IRQ_SGI9 9
+#define GIC_IRQ_SGI10 10
+#define GIC_IRQ_SGI11 11
+#define GIC_IRQ_SGI12 12
+#define GIC_IRQ_SGI13 13
+#define GIC_IRQ_SGI14 14
+#define GIC_IRQ_SGI15 15
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+bool arm64_gic_irq_is_enabled(unsigned int intid);
+int arm64_gic_initialize(void);
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags);
+
+/****************************************************************************
+ * Name: arm64_decodeirq
+ *
+ * Description:
+ * This function is called from the IRQ vector handler in arm_vectors.S.
+ * At this point, the interrupt has been taken and the registers have
+ * been saved on the stack. This function simply needs to determine the
+ * the irq number of the interrupt and then to call arm_doirq to dispatch
+ * the interrupt.
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area on the stack.
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_decodeirq(uint64_t * regs);
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list);
+
+#ifdef CONFIG_SMP
+
+#define SGI_CPU_PAUSE GIC_IRQ_SGI0
+
+/****************************************************************************
+ * Name: arm64_pause_handler
+ *
+ * Description:
+ * This is the handler for SGI2. It performs the following operations:
+ *
+ * 1. It saves the current task state at the head of the current assigned
+ * task list.
+ * 2. It waits on a spinlock, then
+ * 3. Returns from interrupt, restoring the state of the new task at the
+ * head of the ready to run list.
+ *
+ * Input Parameters:
+ * Standard interrupt handling
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int arm64_pause_handler(int irq, void *context, void *arg);
+
+void arm64_gic_secondary_init(void);
+
+int arm64_smp_sgi_init(void);
+
+#endif
+
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H */
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
Review Comment:
```suggestion
#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
(gic_get_rdist() + GICR_SGI_BASE_OFF) \
: GIC_DIST_BASE)
```
##########
arch/arm64/src/common/arm64_mmu.h:
##########
@@ -0,0 +1,246 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+#define __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H
```
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,606 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#include "arm64_trace_printf.h"
+
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one
+ * complete table */
+#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX 3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+ (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+
+#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT \
+ (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT \
+ (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT \
+ (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+ (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+ (XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+ ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21) - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \
+ ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \
+ ? 0U \
+ : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \
+ ? 1U \
+ : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \
+ ? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \
+ (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
+ CONFIG_ARM64_VA_BITS)
+
+static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
+ NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
+
+static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+
+#if (CONFIG_ARM64_PA_BITS == 48)
+#define TCR_PS_BITS TCR_PS_BITS_256TB
+#elif (CONFIG_ARM64_PA_BITS == 44)
+#define TCR_PS_BITS TCR_PS_BITS_16TB
+#elif (CONFIG_ARM64_PA_BITS == 42)
+#define TCR_PS_BITS TCR_PS_BITS_4TB
+#elif (CONFIG_ARM64_PA_BITS == 40)
+#define TCR_PS_BITS TCR_PS_BITS_1TB
+#elif (CONFIG_ARM64_PA_BITS == 36)
+#define TCR_PS_BITS TCR_PS_BITS_64GB
+#else
+#define TCR_PS_BITS TCR_PS_BITS_4GB
+#endif
+
+/* Translation table control register settings */
+
+static uint64_t get_tcr(int el)
+{
+ uint64_t tcr;
+ uint64_t va_bits = CONFIG_ARM64_VA_BITS;
+ uint64_t tcr_ps_bits;
+
+ tcr_ps_bits = TCR_PS_BITS;
+
+ if (el == 1)
+ {
+ tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+
+ /* TCR_EL1.EPD1: Disable translation table walk for addresses
+ * that are translated using TTBR1_EL1.
+ */
+
+ tcr |= TCR_EPD1_DISABLE;
+ }
+ else
+ {
+ tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+ }
+
+ tcr |= TCR_T0SZ(va_bits);
+
+ /* Translation table walk is cacheable, inner/outer WBWA and
+ * inner shareable
+ */
+
+ tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+ return tcr;
+}
+
+static int pte_desc_type(uint64_t *pte)
+{
+ return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static uint64_t *calculate_pte_index(uint64_t addr, int level)
+{
+ int base_level = XLAT_TABLE_BASE_LEVEL;
+ uint64_t *pte;
+ uint64_t idx;
+ unsigned int i;
+
+ /* Walk through all translation tables to find pte index */
+
+ pte = (uint64_t *)base_xlat_table;
+ for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++)
+ {
+ idx = XLAT_TABLE_VA_IDX(addr, i);
+ pte += idx;
+
+ /* Found pte index */
+
+ if (i == level)
+ {
+ return pte;
+ }
+
+ /* if PTE is not table desc, can't traverse */
+
+ if (pte_desc_type(pte) != PTE_TABLE_DESC)
+ {
+ return NULL;
+ }
+
+ /* Move to the next translation table level */
+
+ pte = (uint64_t *)(*pte & 0x0000fffffffff000);
+ }
+
+ return NULL;
+}
+
+static void set_pte_table_desc(uint64_t *pte, uint64_t *table,
+ unsigned int level)
+{
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: [Table] %p\n", pte, table);
+#endif
+
+ /* Point pte to new table */
+
+ *pte = PTE_TABLE_DESC | (uint64_t)table;
+}
+
+static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
+ unsigned int attrs, unsigned int level)
+{
+ uint64_t desc = addr_pa;
+ unsigned int mem_type;
+
+ desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+ /* NS bit for security memory access from secure state */
+
+ desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+ /* AP bits for Data access permission */
+
+ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+ /* the access flag */
+
+ desc |= PTE_BLOCK_DESC_AF;
+
+ /* memory attribute index field */
+
+ mem_type = MT_TYPE(attrs);
+ desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+ switch (mem_type)
+ {
+ case MT_DEVICE_NGNRNE:
+ case MT_DEVICE_NGNRE:
+ case MT_DEVICE_GRE:
+ {
+ /* Access to Device memory and non-cacheable memory are coherent
+ * for all observers in the system and are treated as
+ * Outer shareable, so, for these 2 types of memory,
+ * it is not strictly needed to set shareability field
+ */
+
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+
+ /* Map device memory as execute-never */
+
+ desc |= PTE_BLOCK_DESC_PXN;
+ desc |= PTE_BLOCK_DESC_UXN;
+ break;
+ }
+
+ case MT_NORMAL_NC:
+ case MT_NORMAL:
+ {
+ /* Make Normal RW memory as execute never */
+
+ if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+ {
+ desc |= PTE_BLOCK_DESC_PXN;
+ }
+ if (mem_type == MT_NORMAL)
+ {
+ desc |= PTE_BLOCK_DESC_INNER_SHARE;
+ }
+ else
+ {
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+ }
+ }
+ }
+
+#if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE)
+ sinfo("%s ", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: ", pte);
+ sinfo("%s ",
+ (mem_type ==
+ MT_NORMAL) ? "MEM" :((mem_type == MT_NORMAL_NC) ? "NC" : "DEV"));
+ sinfo("%s ", (attrs & MT_RW) ? "-RW" : "-RO");
+ sinfo("%s ", (attrs & MT_NS) ? "-NS" : "-S");
+ sinfo("%s ", (attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC");
+ sinfo("\n");
+#endif
+
+ *pte = desc;
+}
+
+/* Returns a new reallocated table */
+
+static uint64_t *new_prealloc_table(void)
+{
+ static unsigned int table_idx;
+
+ __MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
+ "Enough xlat tables not allocated");
+
+ return (uint64_t *)(xlat_tables[table_idx++]);
+}
+
+/* Splits a block into table with entries spanning the old block */
+
+static void split_pte_block_desc(uint64_t *pte, int level)
+{
+ uint64_t old_block_desc = *pte;
+ uint64_t *new_table;
+ unsigned int i = 0;
+
+ /* get address size shift bits for next level */
+
+ int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1);
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("Splitting existing PTE %p(L%d)\n", pte, level);
+#endif
+
+ new_table = new_prealloc_table();
+
+ for (i = 0; i < XLAT_TABLE_ENTRIES; i++)
+ {
+ new_table[i] = old_block_desc | (i << levelshift);
+
+ if ((level + 1) == 3)
+ {
+ new_table[i] |= PTE_PAGE_DESC;
+ }
+ }
+
+ /* Overwrite existing PTE set the new table into effect */
+
+ set_pte_table_desc(pte, new_table, level);
+}
+
+/* Create/Populate translation table(s) for given region */
+
+static void init_xlat_tables(const struct arm_mmu_region *region)
+{
+ uint64_t *pte;
+ uint64_t virt = region->base_va;
+ uint64_t phys = region->base_pa;
+ uint64_t size = region->size;
+ uint64_t attrs = region->attrs;
+ uint64_t level_size;
+ uint64_t *new_table;
+ unsigned int level = XLAT_TABLE_BASE_LEVEL;
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("mmap: virt %llx phys %llx size %llx\n", virt, phys, size);
+#endif
+
+ /* check minimum alignment requirement for given mmap region */
+
+ __MMU_ASSERT(((virt & (PAGE_SIZE - 1)) == 0) &&
+ ((size & (PAGE_SIZE - 1)) == 0),
+ "address/size are not page aligned\n");
+
+ while (size)
+ {
+ __MMU_ASSERT(level <= XLAT_TABLE_LEVEL_MAX,
+ "max translation table level exceeded\n");
+
+ /* Locate PTE for given virtual address and page table level */
+
+ pte = calculate_pte_index(virt, level);
+ __MMU_ASSERT(pte != NULL, "pte not found\n");
+
+ level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level);
+
+ if (size >= level_size && !(virt & (level_size - 1)))
+ {
+ /* Given range fits into level size,
+ * create block/page descriptor
+ */
+
+ set_pte_block_desc(pte, phys, attrs, level);
+ virt += level_size;
+ phys += level_size;
+ size -= level_size;
+
+ /* Range is mapped, start again for next range */
+
+ level = XLAT_TABLE_BASE_LEVEL;
+ }
+ else if (pte_desc_type(pte) == PTE_INVALID_DESC)
+ {
+ /* Range doesn't fit, create subtable */
+
+ new_table = new_prealloc_table();
+ set_pte_table_desc(pte, new_table, level);
+ level++;
+ }
+ else if (pte_desc_type(pte) == PTE_BLOCK_DESC)
+ {
+ split_pte_block_desc(pte, level);
+ level++;
+ }
+ else if (pte_desc_type(pte) == PTE_TABLE_DESC)
+ {
+ level++;
+ }
+ }
+}
+
+/* NuttX RTOS execution regions with appropriate attributes */
+
+static const struct arm_mmu_region mmu_nxrt_regions[] =
+{
+ /* Mark text segment cacheable,read only and executable */
+
+ MMU_REGION_FLAT_ENTRY("nx_code",
+ (uint64_t)_stext,
+ (uint64_t)_sztext,
+ MT_CODE | MT_SECURE),
+
+ /* Mark rodata segment cacheable, read only and execute-never */
+
+ MMU_REGION_FLAT_ENTRY("nx_rodata",
+ (uint64_t)_srodata,
+ (uint64_t)_szrodata,
+ MT_RODATA | MT_SECURE),
+
+ /* Mark rest of the mirtos execution regions (data, bss, noinit, etc.)
+ * cacheable, read-write
+ * Note: read-write region is marked execute-ever internally
+ */
+
+ MMU_REGION_FLAT_ENTRY("nx_data",
+ (uint64_t)_sdata,
+ (uint64_t)_szdata,
+ MT_NORMAL | MT_RW | MT_SECURE),
+};
+
+static void setup_page_tables(void)
+{
+ unsigned int index;
+ const struct arm_mmu_region *region;
+ uint64_t max_va = 0, max_pa = 0;
+
+ for (index = 0; index < mmu_config.num_regions; index++)
+ {
+ region = &mmu_config.mmu_regions[index];
+ max_va = MAX(max_va, region->base_va + region->size);
+ max_pa = MAX(max_pa, region->base_pa + region->size);
+ }
+
+ __MMU_ASSERT(max_va <= (1ULL << CONFIG_ARM64_VA_BITS),
+ "Maximum VA not supported\n");
+ __MMU_ASSERT(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS),
+ "Maximum PA not supported\n");
Review Comment:
```suggestion
__MMU_ASSERT(max_va <= (1ULL << CONFIG_ARM64_VA_BITS),
"Maximum VA not supported\n");
__MMU_ASSERT(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS),
"Maximum PA not supported\n");
```
##########
arch/arm64/src/common/arm64_fpu.c:
##########
@@ -0,0 +1,249 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_fpu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "sched/sched.h"
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_fpu.h"
+
+static struct fpu_reg g_idle_thread_fpu[CONFIG_SMP_NCPUS];
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
+
+ /* for statistic propose */
+
+ int save_count;
+ int restore_count;
+ int switch_count;
+ int exe_depth_count;
+};
+
+static struct arm64_cpu_fpu_context g_cpu_fpu_ctx[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/***************************************************************************
+ * Public Functions
+ ***************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb)
+{
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ memset(&g_cpu_fpu_ctx[this_cpu()], 0,
+ sizeof(struct arm64_cpu_fpu_context));
+ g_cpu_fpu_ctx[this_cpu()].idle_thread = tcb;
+
+ tcb->xcp.fpu_regs = &g_idle_thread_fpu[this_cpu()];
+ }
+
+ memset(tcb->xcp.fpu_regs, 0, sizeof(struct fpu_reg));
+ tcb->xcp.fpu_regs->fpu_trap = 0;
+}
+
+void arm64_destory_fpu(struct tcb_s * tcb)
+{
+ struct tcb_s * owner;
+
+ /* save current fpu owner's context */
+
+ owner = g_cpu_fpu_ctx[this_cpu()].fpu_owner;
+
+ if (owner == tcb)
+ {
+ g_cpu_fpu_ctx[this_cpu()].fpu_owner = NULL;
+ }
+}
+
+/* enable FPU access trap */
+
+static void arm64_fpu_access_trap_enable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+ cpacr &= ~CPACR_EL1_FPEN_NOTRAP;
+ write_sysreg(cpacr, cpacr_el1);
+
+ __ISB();
+}
+
+/* disable FPU access trap */
+
+static void arm64_fpu_access_trap_disable(void)
+{
+ uint64_t cpacr;
+
+ cpacr = read_sysreg(cpacr_el1);
+
+ cpacr |= CPACR_EL1_FPEN_NOTRAP;
+
Review Comment:
```suggestion
cpacr |= CPACR_EL1_FPEN_NOTRAP;
```
##########
arch/arm64/src/common/arm64_mmu.h:
##########
@@ -0,0 +1,246 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+#define __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Following Memory types supported through MAIR encodings can be passed
+ * by user through "attrs"(attributes) field of specified memory region.
+ * As MAIR supports such 8 encodings, we will reserve attrs[2:0];
+ * so that we can provide encodings upto 7 if needed in future.
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a, B2.7.2
+ */
+#define MT_TYPE_MASK 0x7U
+#define MT_TYPE(attr) (attr & MT_TYPE_MASK)
Review Comment:
```suggestion
#define MT_TYPE(attr) ((attr) & MT_TYPE_MASK)
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
Review Comment:
Optional
```suggestion
*(volatile uint32_t *)addr = temp | BIT(bit);
```
##########
arch/arm64/src/common/arm64_mmu.h:
##########
@@ -0,0 +1,246 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+#define __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Following Memory types supported through MAIR encodings can be passed
+ * by user through "attrs"(attributes) field of specified memory region.
+ * As MAIR supports such 8 encodings, we will reserve attrs[2:0];
+ * so that we can provide encodings upto 7 if needed in future.
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a, B2.7.2
+ */
+#define MT_TYPE_MASK 0x7U
+#define MT_TYPE(attr) (attr & MT_TYPE_MASK)
+#define MT_DEVICE_NGNRNE 0U
+#define MT_DEVICE_NGNRE 1U
+#define MT_DEVICE_GRE 2U
+#define MT_NORMAL_NC 3U
+#define MT_NORMAL 4U
+
+#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
+ (0x04 << (MT_DEVICE_NGNRE * 8)) | \
+ (0x0c << (MT_DEVICE_GRE * 8)) | \
+ (0x44 << (MT_NORMAL_NC * 8)) | \
+ (0xffUL << (MT_NORMAL * 8)))
+
+/* More flags from user's perpective are supported using remaining bits
+ * of "attrs" field, i.e. attrs[31:3], underlying code will take care
+ * of setting PTE fields correctly.
+ *
+ * current usage of attrs[31:3] is:
+ * attrs[3] : Access Permissions
+ * attrs[4] : Memory access from secure/ns state
+ * attrs[5] : Execute Permissions
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a
+ */
+
+#define MT_PERM_SHIFT 3U
+#define MT_SEC_SHIFT 4U
+#define MT_EXECUTE_SHIFT 5U
+
+#define MT_RO (0U << MT_PERM_SHIFT)
+#define MT_RW (1U << MT_PERM_SHIFT)
+
+#define MT_SECURE (0U << MT_SEC_SHIFT)
+#define MT_NS (1U << MT_SEC_SHIFT)
+
+#define MT_EXECUTE (0U << MT_EXECUTE_SHIFT)
+#define MT_EXECUTE_NEVER (1U << MT_EXECUTE_SHIFT)
+
+/* Some compound attributes for most common usages */
+
+#define MT_CODE (MT_NORMAL | MT_RO | MT_EXECUTE)
+#define MT_RODATA (MT_NORMAL | MT_RO | MT_EXECUTE_NEVER)
+
+/* PTE descriptor can be Block descriptor or Table descriptor
+ * or Page descriptor.
+ */
+
+#define PTE_DESC_TYPE_MASK 3U
+#define PTE_BLOCK_DESC 1U
+#define PTE_TABLE_DESC 3U
+#define PTE_PAGE_DESC 3U
+#define PTE_INVALID_DESC 0U
+
+/* Block and Page descriptor attributes fields */
+
+#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2)
+#define PTE_BLOCK_DESC_NS (1ULL << 5)
+#define PTE_BLOCK_DESC_AP_RO (1ULL << 7)
+#define PTE_BLOCK_DESC_AP_RW (0ULL << 7)
+#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8)
+#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8)
+#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8)
+#define PTE_BLOCK_DESC_AF (1ULL << 10)
+#define PTE_BLOCK_DESC_NG (1ULL << 11)
+#define PTE_BLOCK_DESC_PXN (1ULL << 53)
+#define PTE_BLOCK_DESC_UXN (1ULL << 54)
+
+/* TCR definitions.
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a D13.2.112~114
+ *
+ */
+
+#define TCR_EL1_IPS_SHIFT 32U
+#define TCR_EL2_PS_SHIFT 16U
+#define TCR_EL3_PS_SHIFT 16U
+
+#define TCR_T0SZ_SHIFT 0U
+#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT)
+
+#define TCR_IRGN_NC (0ULL << 8)
+#define TCR_IRGN_WBWA (1ULL << 8)
+#define TCR_IRGN_WT (2ULL << 8)
+#define TCR_IRGN_WBNWA (3ULL << 8)
+#define TCR_IRGN_MASK (3ULL << 8)
+#define TCR_ORGN_NC (0ULL << 10)
+#define TCR_ORGN_WBWA (1ULL << 10)
+#define TCR_ORGN_WT (2ULL << 10)
+#define TCR_ORGN_WBNWA (3ULL << 10)
+#define TCR_ORGN_MASK (3ULL << 10)
+#define TCR_SHARED_NON (0ULL << 12)
+#define TCR_SHARED_OUTER (2ULL << 12)
+#define TCR_SHARED_INNER (3ULL << 12)
+#define TCR_TG0_4K (0ULL << 14)
+#define TCR_TG0_64K (1ULL << 14)
+#define TCR_TG0_16K (2ULL << 14)
+#define TCR_EPD1_DISABLE (1ULL << 23)
+
+#define TCR_PS_BITS_4GB 0x0ULL
+#define TCR_PS_BITS_64GB 0x1ULL
+#define TCR_PS_BITS_1TB 0x2ULL
+#define TCR_PS_BITS_4TB 0x3ULL
+#define TCR_PS_BITS_16TB 0x4ULL
+#define TCR_PS_BITS_256TB 0x5ULL
+
+#define CTR_EL0_DMINLINE_SHIFT 16
+#define CTR_EL0_DMINLINE_MASK BIT_MASK(4)
+#define CTR_EL0_CWG_SHIFT 24
+#define CTR_EL0_CWG_MASK BIT_MASK(4)
+
+/* clidr_el1 */
+
+#define CLIDR_EL1_LOC_SHIFT 24
+#define CLIDR_EL1_LOC_MASK BIT_MASK(3)
+#define CLIDR_EL1_CTYPE_SHIFT(level) ((level) * 3)
+#define CLIDR_EL1_CTYPE_MASK BIT_MASK(3)
+
+/* ccsidr_el1 */
+
+#define CCSIDR_EL1_LN_SZ_SHIFT 0
+#define CCSIDR_EL1_LN_SZ_MASK BIT_MASK(3)
+#define CCSIDR_EL1_WAYS_SHIFT 3
+#define CCSIDR_EL1_WAYS_MASK BIT_MASK(10)
+#define CCSIDR_EL1_SETS_SHIFT 13
+#define CCSIDR_EL1_SETS_MASK BIT_MASK(15)
+
+#ifndef __ASSEMBLY__
+
+/* Region definition data structure */
+
+struct arm_mmu_region
Review Comment:
Please arrange Types section
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,606 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#include "arm64_trace_printf.h"
+
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one
+ * complete table */
+#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX 3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+ (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+
+#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT \
+ (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT \
+ (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT \
+ (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+ (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+ (XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+ ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21) - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \
+ ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \
+ ? 0U \
+ : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \
+ ? 1U \
+ : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \
+ ? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \
+ (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
+ CONFIG_ARM64_VA_BITS)
+
+static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
+ NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
+
+static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+
+#if (CONFIG_ARM64_PA_BITS == 48)
+#define TCR_PS_BITS TCR_PS_BITS_256TB
+#elif (CONFIG_ARM64_PA_BITS == 44)
+#define TCR_PS_BITS TCR_PS_BITS_16TB
+#elif (CONFIG_ARM64_PA_BITS == 42)
+#define TCR_PS_BITS TCR_PS_BITS_4TB
+#elif (CONFIG_ARM64_PA_BITS == 40)
+#define TCR_PS_BITS TCR_PS_BITS_1TB
+#elif (CONFIG_ARM64_PA_BITS == 36)
+#define TCR_PS_BITS TCR_PS_BITS_64GB
+#else
+#define TCR_PS_BITS TCR_PS_BITS_4GB
+#endif
+
+/* Translation table control register settings */
+
+static uint64_t get_tcr(int el)
+{
+ uint64_t tcr;
+ uint64_t va_bits = CONFIG_ARM64_VA_BITS;
+ uint64_t tcr_ps_bits;
+
+ tcr_ps_bits = TCR_PS_BITS;
+
+ if (el == 1)
+ {
+ tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+
+ /* TCR_EL1.EPD1: Disable translation table walk for addresses
+ * that are translated using TTBR1_EL1.
+ */
+
+ tcr |= TCR_EPD1_DISABLE;
+ }
+ else
+ {
+ tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+ }
+
+ tcr |= TCR_T0SZ(va_bits);
+
+ /* Translation table walk is cacheable, inner/outer WBWA and
+ * inner shareable
+ */
+
+ tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+ return tcr;
+}
+
+static int pte_desc_type(uint64_t *pte)
+{
+ return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static uint64_t *calculate_pte_index(uint64_t addr, int level)
+{
+ int base_level = XLAT_TABLE_BASE_LEVEL;
+ uint64_t *pte;
+ uint64_t idx;
+ unsigned int i;
+
+ /* Walk through all translation tables to find pte index */
+
+ pte = (uint64_t *)base_xlat_table;
+ for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++)
+ {
+ idx = XLAT_TABLE_VA_IDX(addr, i);
+ pte += idx;
+
+ /* Found pte index */
+
+ if (i == level)
+ {
+ return pte;
+ }
+
+ /* if PTE is not table desc, can't traverse */
+
+ if (pte_desc_type(pte) != PTE_TABLE_DESC)
+ {
+ return NULL;
+ }
+
+ /* Move to the next translation table level */
+
+ pte = (uint64_t *)(*pte & 0x0000fffffffff000);
+ }
+
+ return NULL;
+}
+
+static void set_pte_table_desc(uint64_t *pte, uint64_t *table,
+ unsigned int level)
+{
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: [Table] %p\n", pte, table);
+#endif
+
+ /* Point pte to new table */
+
+ *pte = PTE_TABLE_DESC | (uint64_t)table;
+}
+
+static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
+ unsigned int attrs, unsigned int level)
+{
+ uint64_t desc = addr_pa;
+ unsigned int mem_type;
+
+ desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+ /* NS bit for security memory access from secure state */
+
+ desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+ /* AP bits for Data access permission */
+
+ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+ /* the access flag */
+
+ desc |= PTE_BLOCK_DESC_AF;
+
+ /* memory attribute index field */
+
+ mem_type = MT_TYPE(attrs);
+ desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+ switch (mem_type)
+ {
+ case MT_DEVICE_NGNRNE:
+ case MT_DEVICE_NGNRE:
+ case MT_DEVICE_GRE:
+ {
+ /* Access to Device memory and non-cacheable memory are coherent
+ * for all observers in the system and are treated as
+ * Outer shareable, so, for these 2 types of memory,
+ * it is not strictly needed to set shareability field
+ */
+
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+
+ /* Map device memory as execute-never */
+
+ desc |= PTE_BLOCK_DESC_PXN;
+ desc |= PTE_BLOCK_DESC_UXN;
+ break;
+ }
+
+ case MT_NORMAL_NC:
+ case MT_NORMAL:
+ {
+ /* Make Normal RW memory as execute never */
+
+ if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+ {
+ desc |= PTE_BLOCK_DESC_PXN;
+ }
+ if (mem_type == MT_NORMAL)
+ {
+ desc |= PTE_BLOCK_DESC_INNER_SHARE;
+ }
+ else
+ {
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+ }
+ }
+ }
+
+#if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE)
+ sinfo("%s ", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: ", pte);
+ sinfo("%s ",
+ (mem_type ==
+ MT_NORMAL) ? "MEM" :((mem_type == MT_NORMAL_NC) ? "NC" : "DEV"));
+ sinfo("%s ", (attrs & MT_RW) ? "-RW" : "-RO");
+ sinfo("%s ", (attrs & MT_NS) ? "-NS" : "-S");
+ sinfo("%s ", (attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC");
+ sinfo("\n");
+#endif
+
+ *pte = desc;
+}
+
+/* Returns a new reallocated table */
+
+static uint64_t *new_prealloc_table(void)
+{
+ static unsigned int table_idx;
+
+ __MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
+ "Enough xlat tables not allocated");
+
+ return (uint64_t *)(xlat_tables[table_idx++]);
+}
+
+/* Splits a block into table with entries spanning the old block */
+
+static void split_pte_block_desc(uint64_t *pte, int level)
+{
+ uint64_t old_block_desc = *pte;
+ uint64_t *new_table;
+ unsigned int i = 0;
+
+ /* get address size shift bits for next level */
+
+ int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1);
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("Splitting existing PTE %p(L%d)\n", pte, level);
+#endif
+
+ new_table = new_prealloc_table();
+
+ for (i = 0; i < XLAT_TABLE_ENTRIES; i++)
+ {
+ new_table[i] = old_block_desc | (i << levelshift);
+
+ if ((level + 1) == 3)
+ {
+ new_table[i] |= PTE_PAGE_DESC;
+ }
+ }
+
+ /* Overwrite existing PTE set the new table into effect */
+
+ set_pte_table_desc(pte, new_table, level);
+}
+
+/* Create/Populate translation table(s) for given region */
+
+static void init_xlat_tables(const struct arm_mmu_region *region)
+{
+ uint64_t *pte;
+ uint64_t virt = region->base_va;
+ uint64_t phys = region->base_pa;
+ uint64_t size = region->size;
+ uint64_t attrs = region->attrs;
+ uint64_t level_size;
+ uint64_t *new_table;
+ unsigned int level = XLAT_TABLE_BASE_LEVEL;
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("mmap: virt %llx phys %llx size %llx\n", virt, phys, size);
+#endif
+
+ /* check minimum alignment requirement for given mmap region */
+
+ __MMU_ASSERT(((virt & (PAGE_SIZE - 1)) == 0) &&
+ ((size & (PAGE_SIZE - 1)) == 0),
+ "address/size are not page aligned\n");
+
+ while (size)
+ {
+ __MMU_ASSERT(level <= XLAT_TABLE_LEVEL_MAX,
+ "max translation table level exceeded\n");
+
+ /* Locate PTE for given virtual address and page table level */
+
+ pte = calculate_pte_index(virt, level);
+ __MMU_ASSERT(pte != NULL, "pte not found\n");
+
+ level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level);
+
+ if (size >= level_size && !(virt & (level_size - 1)))
+ {
+ /* Given range fits into level size,
+ * create block/page descriptor
+ */
+
+ set_pte_block_desc(pte, phys, attrs, level);
+ virt += level_size;
+ phys += level_size;
+ size -= level_size;
+
+ /* Range is mapped, start again for next range */
+
+ level = XLAT_TABLE_BASE_LEVEL;
+ }
+ else if (pte_desc_type(pte) == PTE_INVALID_DESC)
+ {
+ /* Range doesn't fit, create subtable */
+
+ new_table = new_prealloc_table();
+ set_pte_table_desc(pte, new_table, level);
+ level++;
+ }
+ else if (pte_desc_type(pte) == PTE_BLOCK_DESC)
+ {
+ split_pte_block_desc(pte, level);
+ level++;
+ }
+ else if (pte_desc_type(pte) == PTE_TABLE_DESC)
+ {
+ level++;
+ }
+ }
+}
+
+/* NuttX RTOS execution regions with appropriate attributes */
+
+static const struct arm_mmu_region mmu_nxrt_regions[] =
+{
+ /* Mark text segment cacheable,read only and executable */
+
+ MMU_REGION_FLAT_ENTRY("nx_code",
+ (uint64_t)_stext,
+ (uint64_t)_sztext,
+ MT_CODE | MT_SECURE),
+
+ /* Mark rodata segment cacheable, read only and execute-never */
+
+ MMU_REGION_FLAT_ENTRY("nx_rodata",
+ (uint64_t)_srodata,
+ (uint64_t)_szrodata,
+ MT_RODATA | MT_SECURE),
+
+ /* Mark rest of the mirtos execution regions (data, bss, noinit, etc.)
+ * cacheable, read-write
+ * Note: read-write region is marked execute-ever internally
+ */
+
+ MMU_REGION_FLAT_ENTRY("nx_data",
+ (uint64_t)_sdata,
+ (uint64_t)_szdata,
+ MT_NORMAL | MT_RW | MT_SECURE),
+};
+
+static void setup_page_tables(void)
+{
+ unsigned int index;
+ const struct arm_mmu_region *region;
+ uint64_t max_va = 0, max_pa = 0;
+
+ for (index = 0; index < mmu_config.num_regions; index++)
+ {
+ region = &mmu_config.mmu_regions[index];
+ max_va = MAX(max_va, region->base_va + region->size);
+ max_pa = MAX(max_pa, region->base_pa + region->size);
+ }
+
+ __MMU_ASSERT(max_va <= (1ULL << CONFIG_ARM64_VA_BITS),
+ "Maximum VA not supported\n");
+ __MMU_ASSERT(max_pa <= (1ULL << CONFIG_ARM64_PA_BITS),
+ "Maximum PA not supported\n");
+
+ /* create translation tables for user provided platform regions */
+
+ for (index = 0; index < mmu_config.num_regions; index++)
+ {
+ region = &mmu_config.mmu_regions[index];
+ if (region->size || region->attrs)
+ {
+ init_xlat_tables(region);
+ }
+ }
+
+ /* setup translation table for mirtos execution regions */
+
+ for (index = 0; index < ARRAY_SIZE(mmu_nxrt_regions); index++)
+ {
+ region = &mmu_nxrt_regions[index];
+ if (region->size || region->attrs)
+ {
+ init_xlat_tables(region);
+ }
+ }
+}
+
+static void enable_mmu_el1(unsigned int flags)
+{
+ uint64_t value;
+
+ /* Set MAIR, TCR and TBBR registers */
+
+ write_sysreg(MEMORY_ATTRIBUTES, mair_el1);
+ write_sysreg(get_tcr(1), tcr_el1);
+ write_sysreg(((uint64_t)base_xlat_table), ttbr0_el1);
+
+ /* Ensure these changes are seen before MMU is enabled */
+
+ __ISB();
+
+ /* Enable the MMU and data cache */
+
+ value = read_sysreg(sctlr_el1);
+ write_sysreg((value | SCTLR_M_BIT | SCTLR_C_BIT), sctlr_el1);
+
+ /* Ensure the MMU enable takes effect immediately */
+
+ __ISB();
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("MMU enabled with dcache\n");
+#endif
+}
+
+int arm_mmu_set_memregion(const struct arm_mmu_region *region)
+{
+ uint64_t virt = region->base_va;
+ uint64_t size = region->size;
+
+ if (((virt & (PAGE_SIZE - 1)) == 0) &&
+ ((size & (PAGE_SIZE - 1)) == 0))
+ {
+ init_xlat_tables(region);
+ }
+ else
+ {
+ sinfo("address/size are not page aligned\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/***************************************************************************
+ * Public Functions
+ ***************************************************************************/
+
+/* @brief MMU default configuration
+ *
+ * This function provides the default configuration mechanism for the Memory
+ * Management Unit (MMU).
+ */
+
+int arm64_mmu_init(bool is_primary_core)
+{
+ uint64_t val;
+ unsigned flags = 0;
+ uint64_t ctr_el0;
+ uint32_t dminline;
+
+ /* Current MMU code supports only EL1 */
+
+ __asm__ volatile ("mrs %0, CurrentEL" : "=r" (val));
+
+ __MMU_ASSERT(GET_EL(val) == MODE_EL1,
+ "Exception level not EL1, MMU not enabled!\n");
Review Comment:
```suggestion
__MMU_ASSERT(GET_EL(val) == MODE_EL1,
"Exception level not EL1, MMU not enabled!\n");
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static inline unsigned long gic_get_rdist(void)
+{
+ return gic_rdists[this_cpu()];
+}
+
+static inline uint32_t read_gicd_wait_rwp(void)
+{
+ uint32_t value;
+
+ value = getreg32(GICD_CTLR);
+
+ while (value & BIT(GICD_CTLR_RWP))
+ {
+ value = getreg32(GICD_CTLR);
+ }
+
+ return value;
+}
+
+/* Wait for register write pending
+ * TODO: add timed wait
+ */
+
+static int gic_wait_rwp(uint32_t intid)
+{
+ uint32_t rwp_mask;
+ unsigned long base;
+
+ if (intid < GIC_SPI_INT_BASE)
+ {
+ base = (gic_get_rdist() + GICR_CTLR);
+ rwp_mask = BIT(GICR_CTLR_RWP);
+ }
+ else
+ {
+ base = GICD_CTLR;
+ rwp_mask = BIT(GICD_CTLR_RWP);
+ }
+
+ while (getreg32(base) & rwp_mask)
+ {
+ }
+
+ return 0;
+}
+
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t shift;
+ uint32_t val;
+ unsigned long base = GET_DIST_BASE(intid);
+
+ /* Disable the interrupt */
+
+ putreg32(mask, ICENABLER(base, idx));
+ gic_wait_rwp(intid);
+
+ /* PRIORITYR registers provide byte access */
+
+ putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+
+ /* Interrupt type config */
+
+ if (!GIC_IS_SGI(intid))
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+
+ val = getreg32(ICFGR(base, idx));
+ val &= ~(GICD_ICFGR_MASK << shift);
+ if (flags & IRQ_TYPE_EDGE)
+ {
+ val |= (GICD_ICFGR_TYPE << shift);
+ }
+
+ putreg32(val, ICFGR(base, idx));
+ }
+}
+
+void arm64_gic_irq_enable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+
+ /* Affinity routing is enabled for Non-secure state (GICD_CTLR.ARE_NS
+ * is set to '1' when GIC distributor is initialized) ,so need to set
+ * SPI's affinity, now set it to be the PE on which it is enabled.
+ */
+
+ if (GIC_IS_SPI(intid))
+ {
+ putreg64(MPIDR_TO_CORE(GET_MPIDR()),
+ IROUTER(GET_DIST_BASE(intid), intid));
+ }
+}
+
+void arm64_gic_irq_disable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
+
+ /* poll to ensure write is complete */
+
+ gic_wait_rwp(intid);
+}
+
+bool arm64_gic_irq_is_enabled(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t val;
+
+ val = getreg32(ISENABLER(GET_DIST_BASE(intid), idx));
+
+ return (val & mask) != 0;
+}
+
+unsigned int arm64_gic_get_active(void)
+{
+ int intid;
+
+ /* (Pending -> Active / AP) or (AP -> AP) */
+
+ intid = read_sysreg(ICC_IAR1_EL1);
+
+ return intid;
+}
+
+void arm64_gic_eoi(unsigned int intid)
+{
+ /* Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+
+ __DSB();
+
+ /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
+
+ write_sysreg(intid, ICC_EOIR1_EL1);
+}
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list)
+{
+ uint32_t aff3;
+ uint32_t aff2;
+ uint32_t aff1;
+ uint64_t sgi_val;
+
+ assert(GIC_IS_SGI(sgi_id));
+
+ /* Extract affinity fields from target */
+
+ aff1 = MPIDR_AFFLVL(target_aff, 1);
+ aff2 = MPIDR_AFFLVL(target_aff, 2);
+ aff3 = MPIDR_AFFLVL(target_aff, 3);
+
+ sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF,
+ target_list);
+
+ __DSB();
+ write_sysreg(sgi_val, ICC_SGI1R);
+ __ISB();
+
+ return 0;
+}
+
+/* Wake up GIC redistributor.
+ * clear ProcessorSleep and wait till ChildAsleep is cleared.
+ * ProcessSleep to be cleared only when ChildAsleep is set
+ * Check if redistributor is not powered already.
+ */
+
+static void gicv3_rdist_enable(unsigned long rdist)
+{
+ if (!(getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)))
+ {
+ return;
+ }
+
+ sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
+ while (getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))
+ {
+ }
+}
+
+/* Initialize the cpu interface. This should be called by each core. */
+
+static void gicv3_cpuif_init(void)
+{
+ uint32_t icc_sre;
+ uint32_t intid;
+
+ unsigned long base = gic_get_rdist() + GICR_SGI_BASE_OFF;
+
+ /* Disable all sgi ppi */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0));
+
+ /* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */
+
+ gic_wait_rwp(0);
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, 0));
+
+ /* Configure all SGIs/PPIs as G1S or G1NS depending on Zephyr
+ * is run in EL1S or EL1NS respectively.
+ * All interrupts will be delivered as irq
+ */
+
+ putreg32(IGROUPR_VAL, IGROUPR(base, 0));
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, 0));
+
+ /* Configure default priorities for SGI 0:15 and PPI 0:15. */
+
+ for (intid = 0; intid < GIC_SPI_INT_BASE;
+ intid += GIC_NUM_PRI_PER_REG)
+ {
+ putreg32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
+ }
+
+ /* Configure PPIs as level triggered */
+
+ putreg32(0, ICFGR(base, 1));
+
+ /* Check if system interface can be enabled.
+ * 'icc_sre_el3' needs to be configured at 'EL3'
+ * to allow access to 'icc_sre_el1' at 'EL1'
+ * eg: z_arch_el3_plat_init can be used by platform.
+ */
+
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ if (!(icc_sre & ICC_SRE_ELX_SRE_BIT))
+ {
+ icc_sre =
+ (icc_sre | ICC_SRE_ELX_SRE_BIT | ICC_SRE_ELX_DIB_BIT |
+ ICC_SRE_ELX_DFB_BIT);
+ write_sysreg(icc_sre, ICC_SRE_EL1);
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ assert(icc_sre & ICC_SRE_ELX_SRE_BIT);
+ }
+
+ write_sysreg(GIC_IDLE_PRIO, ICC_PMR_EL1);
+
+ /* Allow group1 interrupts */
+
+ write_sysreg(1, ICC_IGRPEN1_EL1);
+}
+
+static void gicv3_dist_init(void)
+{
+ unsigned int num_ints;
+ unsigned int intid;
+ unsigned int idx;
+ unsigned long base = GIC_DIST_BASE;
+
+ num_ints = getreg32(GICD_TYPER);
+ num_ints &= GICD_TYPER_ITLINESNUM_MASK;
+ num_ints = (num_ints + 1) << 5;
+
+ /* Disable the distributor */
+
+ putreg32(0, GICD_CTLR);
+ gic_wait_rwp(GIC_SPI_INT_BASE);
+
+#if 0
+
+ /* Before configuration, we need to check whether
+ * the GIC single security state mode is supported.
+ * Make sure GICD_CTRL_NS is 1.
+ */
+
+ sys_set_bit(GICD_CTLR, GICD_CTRL_NS);
+ __ASSERT(sys_test_bit(GICD_CTLR,
+ GICD_CTRL_NS),
+ "Current GIC does not support single security state");
+#endif
+
+ /* Default configuration of all SPIs */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_INTR_PER_REG)
+ {
+ idx = intid / GIC_NUM_INTR_PER_REG;
+
+ /* Disable interrupt */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICENABLER(base, idx));
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICPENDR(base, idx));
Review Comment:
```suggestion
putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
ICPENDR(base, idx));
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static inline unsigned long gic_get_rdist(void)
+{
+ return gic_rdists[this_cpu()];
+}
+
+static inline uint32_t read_gicd_wait_rwp(void)
+{
+ uint32_t value;
+
+ value = getreg32(GICD_CTLR);
+
+ while (value & BIT(GICD_CTLR_RWP))
+ {
+ value = getreg32(GICD_CTLR);
+ }
+
+ return value;
+}
+
+/* Wait for register write pending
+ * TODO: add timed wait
+ */
+
+static int gic_wait_rwp(uint32_t intid)
+{
+ uint32_t rwp_mask;
+ unsigned long base;
+
+ if (intid < GIC_SPI_INT_BASE)
+ {
+ base = (gic_get_rdist() + GICR_CTLR);
+ rwp_mask = BIT(GICR_CTLR_RWP);
+ }
+ else
+ {
+ base = GICD_CTLR;
+ rwp_mask = BIT(GICD_CTLR_RWP);
+ }
+
+ while (getreg32(base) & rwp_mask)
+ {
+ }
+
+ return 0;
+}
+
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t shift;
+ uint32_t val;
+ unsigned long base = GET_DIST_BASE(intid);
+
+ /* Disable the interrupt */
+
+ putreg32(mask, ICENABLER(base, idx));
+ gic_wait_rwp(intid);
+
+ /* PRIORITYR registers provide byte access */
+
+ putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+
+ /* Interrupt type config */
+
+ if (!GIC_IS_SGI(intid))
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+
+ val = getreg32(ICFGR(base, idx));
+ val &= ~(GICD_ICFGR_MASK << shift);
+ if (flags & IRQ_TYPE_EDGE)
+ {
+ val |= (GICD_ICFGR_TYPE << shift);
+ }
+
+ putreg32(val, ICFGR(base, idx));
+ }
+}
+
+void arm64_gic_irq_enable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+
+ /* Affinity routing is enabled for Non-secure state (GICD_CTLR.ARE_NS
+ * is set to '1' when GIC distributor is initialized) ,so need to set
+ * SPI's affinity, now set it to be the PE on which it is enabled.
+ */
+
+ if (GIC_IS_SPI(intid))
+ {
+ putreg64(MPIDR_TO_CORE(GET_MPIDR()),
+ IROUTER(GET_DIST_BASE(intid), intid));
+ }
+}
+
+void arm64_gic_irq_disable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
+
+ /* poll to ensure write is complete */
+
+ gic_wait_rwp(intid);
+}
+
+bool arm64_gic_irq_is_enabled(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t val;
+
+ val = getreg32(ISENABLER(GET_DIST_BASE(intid), idx));
+
+ return (val & mask) != 0;
+}
+
+unsigned int arm64_gic_get_active(void)
+{
+ int intid;
+
+ /* (Pending -> Active / AP) or (AP -> AP) */
+
+ intid = read_sysreg(ICC_IAR1_EL1);
+
+ return intid;
+}
+
+void arm64_gic_eoi(unsigned int intid)
+{
+ /* Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+
+ __DSB();
+
+ /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
+
+ write_sysreg(intid, ICC_EOIR1_EL1);
+}
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list)
Review Comment:
```suggestion
int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
uint16_t target_list)
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static inline unsigned long gic_get_rdist(void)
+{
+ return gic_rdists[this_cpu()];
+}
+
+static inline uint32_t read_gicd_wait_rwp(void)
+{
+ uint32_t value;
+
+ value = getreg32(GICD_CTLR);
+
+ while (value & BIT(GICD_CTLR_RWP))
+ {
+ value = getreg32(GICD_CTLR);
+ }
+
+ return value;
+}
+
+/* Wait for register write pending
+ * TODO: add timed wait
+ */
+
+static int gic_wait_rwp(uint32_t intid)
+{
+ uint32_t rwp_mask;
+ unsigned long base;
+
+ if (intid < GIC_SPI_INT_BASE)
+ {
+ base = (gic_get_rdist() + GICR_CTLR);
+ rwp_mask = BIT(GICR_CTLR_RWP);
+ }
+ else
+ {
+ base = GICD_CTLR;
+ rwp_mask = BIT(GICD_CTLR_RWP);
+ }
+
+ while (getreg32(base) & rwp_mask)
+ {
+ }
+
+ return 0;
+}
+
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t shift;
+ uint32_t val;
+ unsigned long base = GET_DIST_BASE(intid);
+
+ /* Disable the interrupt */
+
+ putreg32(mask, ICENABLER(base, idx));
+ gic_wait_rwp(intid);
+
+ /* PRIORITYR registers provide byte access */
+
+ putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+
+ /* Interrupt type config */
+
+ if (!GIC_IS_SGI(intid))
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+
+ val = getreg32(ICFGR(base, idx));
+ val &= ~(GICD_ICFGR_MASK << shift);
+ if (flags & IRQ_TYPE_EDGE)
+ {
+ val |= (GICD_ICFGR_TYPE << shift);
+ }
+
+ putreg32(val, ICFGR(base, idx));
+ }
+}
+
+void arm64_gic_irq_enable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+
+ /* Affinity routing is enabled for Non-secure state (GICD_CTLR.ARE_NS
+ * is set to '1' when GIC distributor is initialized) ,so need to set
+ * SPI's affinity, now set it to be the PE on which it is enabled.
+ */
+
+ if (GIC_IS_SPI(intid))
+ {
+ putreg64(MPIDR_TO_CORE(GET_MPIDR()),
+ IROUTER(GET_DIST_BASE(intid), intid));
+ }
+}
+
+void arm64_gic_irq_disable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
+
+ /* poll to ensure write is complete */
+
+ gic_wait_rwp(intid);
+}
+
+bool arm64_gic_irq_is_enabled(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t val;
+
+ val = getreg32(ISENABLER(GET_DIST_BASE(intid), idx));
+
+ return (val & mask) != 0;
+}
+
+unsigned int arm64_gic_get_active(void)
+{
+ int intid;
+
+ /* (Pending -> Active / AP) or (AP -> AP) */
+
+ intid = read_sysreg(ICC_IAR1_EL1);
+
+ return intid;
+}
+
+void arm64_gic_eoi(unsigned int intid)
+{
+ /* Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+
+ __DSB();
+
+ /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
+
+ write_sysreg(intid, ICC_EOIR1_EL1);
+}
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list)
+{
+ uint32_t aff3;
+ uint32_t aff2;
+ uint32_t aff1;
+ uint64_t sgi_val;
+
+ assert(GIC_IS_SGI(sgi_id));
+
+ /* Extract affinity fields from target */
+
+ aff1 = MPIDR_AFFLVL(target_aff, 1);
+ aff2 = MPIDR_AFFLVL(target_aff, 2);
+ aff3 = MPIDR_AFFLVL(target_aff, 3);
+
+ sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF,
+ target_list);
+
+ __DSB();
+ write_sysreg(sgi_val, ICC_SGI1R);
+ __ISB();
+
+ return 0;
+}
+
+/* Wake up GIC redistributor.
+ * clear ProcessorSleep and wait till ChildAsleep is cleared.
+ * ProcessSleep to be cleared only when ChildAsleep is set
+ * Check if redistributor is not powered already.
+ */
+
+static void gicv3_rdist_enable(unsigned long rdist)
+{
+ if (!(getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)))
+ {
+ return;
+ }
+
+ sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
+ while (getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))
+ {
+ }
+}
+
+/* Initialize the cpu interface. This should be called by each core. */
+
+static void gicv3_cpuif_init(void)
+{
+ uint32_t icc_sre;
+ uint32_t intid;
+
+ unsigned long base = gic_get_rdist() + GICR_SGI_BASE_OFF;
+
+ /* Disable all sgi ppi */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0));
+
+ /* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */
+
+ gic_wait_rwp(0);
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, 0));
+
+ /* Configure all SGIs/PPIs as G1S or G1NS depending on Zephyr
+ * is run in EL1S or EL1NS respectively.
+ * All interrupts will be delivered as irq
+ */
+
+ putreg32(IGROUPR_VAL, IGROUPR(base, 0));
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, 0));
+
+ /* Configure default priorities for SGI 0:15 and PPI 0:15. */
+
+ for (intid = 0; intid < GIC_SPI_INT_BASE;
+ intid += GIC_NUM_PRI_PER_REG)
+ {
+ putreg32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
+ }
+
+ /* Configure PPIs as level triggered */
+
+ putreg32(0, ICFGR(base, 1));
+
+ /* Check if system interface can be enabled.
+ * 'icc_sre_el3' needs to be configured at 'EL3'
+ * to allow access to 'icc_sre_el1' at 'EL1'
+ * eg: z_arch_el3_plat_init can be used by platform.
+ */
+
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ if (!(icc_sre & ICC_SRE_ELX_SRE_BIT))
+ {
+ icc_sre =
+ (icc_sre | ICC_SRE_ELX_SRE_BIT | ICC_SRE_ELX_DIB_BIT |
+ ICC_SRE_ELX_DFB_BIT);
+ write_sysreg(icc_sre, ICC_SRE_EL1);
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ assert(icc_sre & ICC_SRE_ELX_SRE_BIT);
+ }
+
+ write_sysreg(GIC_IDLE_PRIO, ICC_PMR_EL1);
+
+ /* Allow group1 interrupts */
+
+ write_sysreg(1, ICC_IGRPEN1_EL1);
+}
+
+static void gicv3_dist_init(void)
+{
+ unsigned int num_ints;
+ unsigned int intid;
+ unsigned int idx;
+ unsigned long base = GIC_DIST_BASE;
+
+ num_ints = getreg32(GICD_TYPER);
+ num_ints &= GICD_TYPER_ITLINESNUM_MASK;
+ num_ints = (num_ints + 1) << 5;
+
+ /* Disable the distributor */
+
+ putreg32(0, GICD_CTLR);
+ gic_wait_rwp(GIC_SPI_INT_BASE);
+
+#if 0
+
+ /* Before configuration, we need to check whether
+ * the GIC single security state mode is supported.
+ * Make sure GICD_CTRL_NS is 1.
+ */
+
+ sys_set_bit(GICD_CTLR, GICD_CTRL_NS);
+ __ASSERT(sys_test_bit(GICD_CTLR,
+ GICD_CTRL_NS),
+ "Current GIC does not support single security state");
+#endif
+
+ /* Default configuration of all SPIs */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_INTR_PER_REG)
+ {
+ idx = intid / GIC_NUM_INTR_PER_REG;
+
+ /* Disable interrupt */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICENABLER(base, idx));
Review Comment:
```suggestion
putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
ICENABLER(base, idx));
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static inline unsigned long gic_get_rdist(void)
+{
+ return gic_rdists[this_cpu()];
+}
+
+static inline uint32_t read_gicd_wait_rwp(void)
+{
+ uint32_t value;
+
+ value = getreg32(GICD_CTLR);
+
+ while (value & BIT(GICD_CTLR_RWP))
+ {
+ value = getreg32(GICD_CTLR);
+ }
+
+ return value;
+}
+
+/* Wait for register write pending
+ * TODO: add timed wait
+ */
+
+static int gic_wait_rwp(uint32_t intid)
+{
+ uint32_t rwp_mask;
+ unsigned long base;
+
+ if (intid < GIC_SPI_INT_BASE)
+ {
+ base = (gic_get_rdist() + GICR_CTLR);
+ rwp_mask = BIT(GICR_CTLR_RWP);
+ }
+ else
+ {
+ base = GICD_CTLR;
+ rwp_mask = BIT(GICD_CTLR_RWP);
+ }
+
+ while (getreg32(base) & rwp_mask)
+ {
+ }
+
+ return 0;
+}
+
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t shift;
+ uint32_t val;
+ unsigned long base = GET_DIST_BASE(intid);
+
+ /* Disable the interrupt */
+
+ putreg32(mask, ICENABLER(base, idx));
+ gic_wait_rwp(intid);
+
+ /* PRIORITYR registers provide byte access */
+
+ putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+
+ /* Interrupt type config */
+
+ if (!GIC_IS_SGI(intid))
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+
+ val = getreg32(ICFGR(base, idx));
+ val &= ~(GICD_ICFGR_MASK << shift);
+ if (flags & IRQ_TYPE_EDGE)
+ {
+ val |= (GICD_ICFGR_TYPE << shift);
+ }
+
+ putreg32(val, ICFGR(base, idx));
+ }
+}
+
+void arm64_gic_irq_enable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+
+ /* Affinity routing is enabled for Non-secure state (GICD_CTLR.ARE_NS
+ * is set to '1' when GIC distributor is initialized) ,so need to set
+ * SPI's affinity, now set it to be the PE on which it is enabled.
+ */
+
+ if (GIC_IS_SPI(intid))
+ {
+ putreg64(MPIDR_TO_CORE(GET_MPIDR()),
+ IROUTER(GET_DIST_BASE(intid), intid));
Review Comment:
```suggestion
putreg64(MPIDR_TO_CORE(GET_MPIDR()),
IROUTER(GET_DIST_BASE(intid), intid));
```
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static inline unsigned long gic_get_rdist(void)
+{
+ return gic_rdists[this_cpu()];
+}
+
+static inline uint32_t read_gicd_wait_rwp(void)
+{
+ uint32_t value;
+
+ value = getreg32(GICD_CTLR);
+
+ while (value & BIT(GICD_CTLR_RWP))
+ {
+ value = getreg32(GICD_CTLR);
+ }
+
+ return value;
+}
+
+/* Wait for register write pending
+ * TODO: add timed wait
+ */
+
+static int gic_wait_rwp(uint32_t intid)
+{
+ uint32_t rwp_mask;
+ unsigned long base;
+
+ if (intid < GIC_SPI_INT_BASE)
+ {
+ base = (gic_get_rdist() + GICR_CTLR);
+ rwp_mask = BIT(GICR_CTLR_RWP);
+ }
+ else
+ {
+ base = GICD_CTLR;
+ rwp_mask = BIT(GICD_CTLR_RWP);
+ }
+
+ while (getreg32(base) & rwp_mask)
+ {
+ }
+
+ return 0;
+}
+
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t shift;
+ uint32_t val;
+ unsigned long base = GET_DIST_BASE(intid);
+
+ /* Disable the interrupt */
+
+ putreg32(mask, ICENABLER(base, idx));
+ gic_wait_rwp(intid);
+
+ /* PRIORITYR registers provide byte access */
+
+ putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+
+ /* Interrupt type config */
+
+ if (!GIC_IS_SGI(intid))
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+
+ val = getreg32(ICFGR(base, idx));
+ val &= ~(GICD_ICFGR_MASK << shift);
+ if (flags & IRQ_TYPE_EDGE)
+ {
+ val |= (GICD_ICFGR_TYPE << shift);
+ }
+
+ putreg32(val, ICFGR(base, idx));
+ }
+}
+
+void arm64_gic_irq_enable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+
+ /* Affinity routing is enabled for Non-secure state (GICD_CTLR.ARE_NS
+ * is set to '1' when GIC distributor is initialized) ,so need to set
+ * SPI's affinity, now set it to be the PE on which it is enabled.
+ */
+
+ if (GIC_IS_SPI(intid))
+ {
+ putreg64(MPIDR_TO_CORE(GET_MPIDR()),
+ IROUTER(GET_DIST_BASE(intid), intid));
+ }
+}
+
+void arm64_gic_irq_disable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
+
+ /* poll to ensure write is complete */
+
+ gic_wait_rwp(intid);
+}
+
+bool arm64_gic_irq_is_enabled(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t val;
+
+ val = getreg32(ISENABLER(GET_DIST_BASE(intid), idx));
+
+ return (val & mask) != 0;
+}
+
+unsigned int arm64_gic_get_active(void)
+{
+ int intid;
+
+ /* (Pending -> Active / AP) or (AP -> AP) */
+
+ intid = read_sysreg(ICC_IAR1_EL1);
+
+ return intid;
+}
+
+void arm64_gic_eoi(unsigned int intid)
+{
+ /* Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+
+ __DSB();
+
+ /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
+
+ write_sysreg(intid, ICC_EOIR1_EL1);
+}
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list)
+{
+ uint32_t aff3;
+ uint32_t aff2;
+ uint32_t aff1;
+ uint64_t sgi_val;
+
+ assert(GIC_IS_SGI(sgi_id));
+
+ /* Extract affinity fields from target */
+
+ aff1 = MPIDR_AFFLVL(target_aff, 1);
+ aff2 = MPIDR_AFFLVL(target_aff, 2);
+ aff3 = MPIDR_AFFLVL(target_aff, 3);
+
+ sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF,
+ target_list);
+
+ __DSB();
+ write_sysreg(sgi_val, ICC_SGI1R);
+ __ISB();
+
+ return 0;
+}
+
+/* Wake up GIC redistributor.
+ * clear ProcessorSleep and wait till ChildAsleep is cleared.
+ * ProcessSleep to be cleared only when ChildAsleep is set
+ * Check if redistributor is not powered already.
+ */
+
+static void gicv3_rdist_enable(unsigned long rdist)
+{
+ if (!(getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)))
+ {
+ return;
+ }
+
+ sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
+ while (getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))
+ {
+ }
+}
+
+/* Initialize the cpu interface. This should be called by each core. */
+
+static void gicv3_cpuif_init(void)
+{
+ uint32_t icc_sre;
+ uint32_t intid;
+
+ unsigned long base = gic_get_rdist() + GICR_SGI_BASE_OFF;
+
+ /* Disable all sgi ppi */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0));
+
+ /* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */
+
+ gic_wait_rwp(0);
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, 0));
+
+ /* Configure all SGIs/PPIs as G1S or G1NS depending on Zephyr
+ * is run in EL1S or EL1NS respectively.
+ * All interrupts will be delivered as irq
+ */
+
+ putreg32(IGROUPR_VAL, IGROUPR(base, 0));
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, 0));
+
+ /* Configure default priorities for SGI 0:15 and PPI 0:15. */
+
+ for (intid = 0; intid < GIC_SPI_INT_BASE;
+ intid += GIC_NUM_PRI_PER_REG)
+ {
+ putreg32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
+ }
+
+ /* Configure PPIs as level triggered */
+
+ putreg32(0, ICFGR(base, 1));
+
+ /* Check if system interface can be enabled.
+ * 'icc_sre_el3' needs to be configured at 'EL3'
+ * to allow access to 'icc_sre_el1' at 'EL1'
+ * eg: z_arch_el3_plat_init can be used by platform.
+ */
+
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ if (!(icc_sre & ICC_SRE_ELX_SRE_BIT))
+ {
+ icc_sre =
+ (icc_sre | ICC_SRE_ELX_SRE_BIT | ICC_SRE_ELX_DIB_BIT |
+ ICC_SRE_ELX_DFB_BIT);
+ write_sysreg(icc_sre, ICC_SRE_EL1);
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ assert(icc_sre & ICC_SRE_ELX_SRE_BIT);
+ }
+
+ write_sysreg(GIC_IDLE_PRIO, ICC_PMR_EL1);
+
+ /* Allow group1 interrupts */
+
+ write_sysreg(1, ICC_IGRPEN1_EL1);
+}
+
+static void gicv3_dist_init(void)
+{
+ unsigned int num_ints;
+ unsigned int intid;
+ unsigned int idx;
+ unsigned long base = GIC_DIST_BASE;
+
+ num_ints = getreg32(GICD_TYPER);
+ num_ints &= GICD_TYPER_ITLINESNUM_MASK;
+ num_ints = (num_ints + 1) << 5;
+
+ /* Disable the distributor */
+
+ putreg32(0, GICD_CTLR);
+ gic_wait_rwp(GIC_SPI_INT_BASE);
+
+#if 0
+
+ /* Before configuration, we need to check whether
+ * the GIC single security state mode is supported.
+ * Make sure GICD_CTRL_NS is 1.
+ */
+
+ sys_set_bit(GICD_CTLR, GICD_CTRL_NS);
+ __ASSERT(sys_test_bit(GICD_CTLR,
+ GICD_CTRL_NS),
+ "Current GIC does not support single security state");
+#endif
+
+ /* Default configuration of all SPIs */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_INTR_PER_REG)
+ {
+ idx = intid / GIC_NUM_INTR_PER_REG;
+
+ /* Disable interrupt */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICENABLER(base, idx));
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICPENDR(base, idx));
+ putreg32(IGROUPR_VAL, IGROUPR(base, idx));
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ IGROUPMODR(base, idx));
+ }
+
+ /* wait for rwp on GICD */
+
+ gic_wait_rwp(GIC_SPI_INT_BASE);
+
+ /* Configure default priorities for all SPIs. */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_PRI_PER_REG)
+ {
+ putreg32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
+ }
+
+ /* Configure all SPIs as active low, level triggered by default */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_CFG_PER_REG)
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ putreg32(0, ICFGR(base, idx));
+ }
+
+ /* Enable distributor with ARE */
+
+ putreg32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS),
+ GICD_CTLR);
Review Comment:
```suggestion
putreg32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS),
GICD_CTLR);
```
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ extern struct thread_stack_element locate_data(".initstack") \
Review Comment:
```suggestion
EXTERN struct thread_stack_element locate_data(".initstack") \
```
##########
arch/arm64/src/common/arm64_initialize.c:
##########
@@ -0,0 +1,181 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialize.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+#ifdef CONFIG_SMP
+THREAD_STACK_ARRAY_DEFINE(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/****************************************************************************
+ * Name: arm64_intstack_alloc
+ *
+ * Description:
+ * Return a pointer to the "alloc" the correct interrupt stack allocation
+ * for the current CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+uintptr_t arm64_intstack_alloc(void)
+{
+ return (uintptr_t)(g_interrupt_stacks[up_cpu_index()]);
+}
+
+/****************************************************************************
+ * Name: arm64_intstack_top
+ *
+ * Description:
+ * Return a pointer to the top the correct interrupt stack allocation
+ * for the current CPU.
+ *
+ ****************************************************************************/
+
+uintptr_t arm64_intstack_top(void)
+{
+ return (uintptr_t)(g_interrupt_stacks[up_cpu_index()] + INTSTACK_SIZE);
+}
+
+#endif
+
+/****************************************************************************
+ * Name: up_color_intstack
+ *
+ * Description:
+ * Set the interrupt stack to a value so that later we can determine how
+ * much stack space was used by interrupt handling logic
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
+static void up_color_intstack(void)
+{
+#ifdef CONFIG_SMP
+ void * ptr = (void *)g_interrupt_stacks[up_cpu_index()];
+#else
+ void * ptr = (void *)g_interrupt_stack;
Review Comment:
```suggestion
void *ptr = (void *)g_interrupt_stacks[up_cpu_index()];
#else
void *ptr = (void *)g_interrupt_stack;
```
##########
arch/arm64/src/common/arm64_macro.inc:
##########
@@ -0,0 +1,83 @@
+/****************************************************************************
+ *
+ * arch/arm64/src/common/macro.inc
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************
+ * DESCRIPTION
+ * macro define for arm64 assembler
+ *
+ ***************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC_
+#define __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC_
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC
#define __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC
```
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ extern struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ extern struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+extern char _stext[]; /* Start of .text */
+extern char _etext[]; /* End of .text */
+extern char _sztext[]; /* Size of .text */
+extern char _srodata[]; /* Start of .rodata */
+extern char _erodata[]; /* End+1 of .rodata */
+extern char _szrodata[]; /* Size of .rodata */
+extern const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
+extern char _sdata[]; /* Start of .data */
+extern char _edata[]; /* End+1 of .data */
+extern char _sbss[]; /* Start of .bss */
+extern char _ebss[]; /* End+1 of .bss */
+extern char _szdata[]; /* Size of data(.data + .bss) */
+extern char _e_initstack[]; /* End+1 of .initstack */
Review Comment:
```suggestion
EXTERN char _stext[]; /* Start of .text */
EXTERN char _etext[]; /* End of .text */
EXTERN char _sztext[]; /* Size of .text */
EXTERN char _srodata[]; /* Start of .rodata */
EXTERN char _erodata[]; /* End+1 of .rodata */
EXTERN char _szrodata[]; /* Size of .rodata */
EXTERN const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
EXTERN char _sdata[]; /* Start of .data */
EXTERN char _edata[]; /* End+1 of .data */
EXTERN char _sbss[]; /* Start of .bss */
EXTERN char _ebss[]; /* End+1 of .bss */
EXTERN char _szdata[]; /* Size of data(.data + .bss) */
EXTERN char _e_initstack[]; /* End+1 of .initstack */
```
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ extern struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ extern struct thread_stack_element locate_data(".initstack") \
Review Comment:
```suggestion
EXTERN struct thread_stack_element locate_data(".initstack") \
```
##########
arch/arm64/src/common/arm64_macro.inc:
##########
@@ -0,0 +1,83 @@
+/****************************************************************************
+ *
+ * arch/arm64/src/common/macro.inc
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************
+ * DESCRIPTION
+ * macro define for arm64 assembler
+ *
+ ***************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC_
+#define __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC_
+
+/*
+ * Get CPU id
+ */
+
+.macro get_cpu_id xreg0
+ mrs \xreg0, mpidr_el1
+ /* FIMXME: aff3 not taken into consideration */
+ ubfx \xreg0, \xreg0, #0, #24
+.endm
+
+.macro switch_el, xreg, el3_label, el2_label, el1_label
+ mrs \xreg, CurrentEL
+ cmp \xreg, 0xc
+ beq \el3_label
+ cmp \xreg, 0x8
+ beq \el2_label
+ cmp \xreg, 0x4
+ beq \el1_label
+.endm
+
+/*
+ * macro to support mov of immediate constant to 64 bit register
+ * It will generate instruction sequence of 'mov'/ 'movz' and one
+ * to three 'movk' depending on the immediate value.
+ */
+.macro mov_imm, xreg, imm
+ .if ((\imm) == 0)
+ mov \xreg, \imm
+ .else
+ .if (((\imm) >> 31) == 0 || ((\imm) >> 31) == 0x1ffffffff)
+ movz \xreg, (\imm >> 16) & 0xffff, lsl 16
+ .else
+ .if (((\imm) >> 47) == 0 || ((\imm) >> 47) == 0x1ffff)
+ movz \xreg, (\imm >> 32) & 0xffff, lsl 32
+ .else
+ movz \xreg, (\imm >> 48) & 0xffff, lsl 48
+ movk \xreg, (\imm >> 32) & 0xffff, lsl 32
+ .endif
+ movk \xreg, (\imm >> 16) & 0xffff, lsl 16
+ .endif
+ movk \xreg, (\imm) & 0xffff, lsl 0
+ .endif
+.endm
+
+#define GTEXT(sym) .global sym; .type sym, %function
+#define PERFOPT_ALIGN .balign 4
+
+#define SECTION_FUNC(sect, sym) \
+ .section .sect.sym, "ax"; \
+ PERFOPT_ALIGN; sym :
+
+#define SECTION_SUBSEC_FUNC(sect, subsec, sym) \
+ .section .sect.subsec, "ax"; PERFOPT_ALIGN; sym :
+
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC_ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC */
```
##########
arch/arm64/src/common/arm64_initialstate.c:
##########
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialstate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tcb)
+{
+ char * stack_ptr = tcb->stack_base_ptr + tcb->adj_stack_size;
Review Comment:
```suggestion
char *stack_ptr = tcb->stack_base_ptr + tcb->adj_stack_size;
```
##########
arch/arm64/src/common/arm64_macro.inc:
##########
@@ -0,0 +1,83 @@
+/****************************************************************************
+ *
+ * arch/arm64/src/common/macro.inc
+ *
Review Comment:
```suggestion
* arch/arm64/src/common/arm64_macro.inc
*
```
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,606 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#include "arm64_trace_printf.h"
+
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one
+ * complete table */
+#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX 3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+ (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+
+#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT \
+ (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT \
+ (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT \
+ (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+ (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+ (XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+ ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21) - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \
+ ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \
+ ? 0U \
+ : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \
+ ? 1U \
+ : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \
+ ? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \
+ (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
+ CONFIG_ARM64_VA_BITS)
+
+static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
+ NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
+
+static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+
+#if (CONFIG_ARM64_PA_BITS == 48)
+#define TCR_PS_BITS TCR_PS_BITS_256TB
+#elif (CONFIG_ARM64_PA_BITS == 44)
+#define TCR_PS_BITS TCR_PS_BITS_16TB
+#elif (CONFIG_ARM64_PA_BITS == 42)
+#define TCR_PS_BITS TCR_PS_BITS_4TB
+#elif (CONFIG_ARM64_PA_BITS == 40)
+#define TCR_PS_BITS TCR_PS_BITS_1TB
+#elif (CONFIG_ARM64_PA_BITS == 36)
+#define TCR_PS_BITS TCR_PS_BITS_64GB
+#else
+#define TCR_PS_BITS TCR_PS_BITS_4GB
+#endif
+
+/* Translation table control register settings */
+
+static uint64_t get_tcr(int el)
+{
+ uint64_t tcr;
+ uint64_t va_bits = CONFIG_ARM64_VA_BITS;
+ uint64_t tcr_ps_bits;
+
+ tcr_ps_bits = TCR_PS_BITS;
+
+ if (el == 1)
+ {
+ tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+
+ /* TCR_EL1.EPD1: Disable translation table walk for addresses
+ * that are translated using TTBR1_EL1.
+ */
+
+ tcr |= TCR_EPD1_DISABLE;
+ }
+ else
+ {
+ tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+ }
+
+ tcr |= TCR_T0SZ(va_bits);
+
+ /* Translation table walk is cacheable, inner/outer WBWA and
+ * inner shareable
+ */
+
+ tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+ return tcr;
+}
+
+static int pte_desc_type(uint64_t *pte)
+{
+ return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static uint64_t *calculate_pte_index(uint64_t addr, int level)
+{
+ int base_level = XLAT_TABLE_BASE_LEVEL;
+ uint64_t *pte;
+ uint64_t idx;
+ unsigned int i;
+
+ /* Walk through all translation tables to find pte index */
+
+ pte = (uint64_t *)base_xlat_table;
+ for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++)
+ {
+ idx = XLAT_TABLE_VA_IDX(addr, i);
+ pte += idx;
+
+ /* Found pte index */
+
+ if (i == level)
+ {
+ return pte;
+ }
+
+ /* if PTE is not table desc, can't traverse */
+
+ if (pte_desc_type(pte) != PTE_TABLE_DESC)
+ {
+ return NULL;
+ }
+
+ /* Move to the next translation table level */
+
+ pte = (uint64_t *)(*pte & 0x0000fffffffff000);
+ }
+
+ return NULL;
+}
+
+static void set_pte_table_desc(uint64_t *pte, uint64_t *table,
+ unsigned int level)
+{
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: [Table] %p\n", pte, table);
+#endif
+
+ /* Point pte to new table */
+
+ *pte = PTE_TABLE_DESC | (uint64_t)table;
+}
+
+static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
+ unsigned int attrs, unsigned int level)
+{
+ uint64_t desc = addr_pa;
+ unsigned int mem_type;
+
+ desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+ /* NS bit for security memory access from secure state */
+
+ desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+ /* AP bits for Data access permission */
+
+ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+ /* the access flag */
+
+ desc |= PTE_BLOCK_DESC_AF;
+
+ /* memory attribute index field */
+
+ mem_type = MT_TYPE(attrs);
+ desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+ switch (mem_type)
+ {
+ case MT_DEVICE_NGNRNE:
+ case MT_DEVICE_NGNRE:
+ case MT_DEVICE_GRE:
+ {
+ /* Access to Device memory and non-cacheable memory are coherent
+ * for all observers in the system and are treated as
+ * Outer shareable, so, for these 2 types of memory,
+ * it is not strictly needed to set shareability field
+ */
+
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+
+ /* Map device memory as execute-never */
+
+ desc |= PTE_BLOCK_DESC_PXN;
+ desc |= PTE_BLOCK_DESC_UXN;
+ break;
+ }
+
+ case MT_NORMAL_NC:
+ case MT_NORMAL:
+ {
+ /* Make Normal RW memory as execute never */
+
+ if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+ {
+ desc |= PTE_BLOCK_DESC_PXN;
+ }
+ if (mem_type == MT_NORMAL)
+ {
+ desc |= PTE_BLOCK_DESC_INNER_SHARE;
+ }
+ else
+ {
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+ }
+ }
+ }
+
+#if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE)
+ sinfo("%s ", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: ", pte);
+ sinfo("%s ",
+ (mem_type ==
+ MT_NORMAL) ? "MEM" :((mem_type == MT_NORMAL_NC) ? "NC" : "DEV"));
+ sinfo("%s ", (attrs & MT_RW) ? "-RW" : "-RO");
+ sinfo("%s ", (attrs & MT_NS) ? "-NS" : "-S");
+ sinfo("%s ", (attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC");
+ sinfo("\n");
+#endif
+
+ *pte = desc;
+}
+
+/* Returns a new reallocated table */
+
+static uint64_t *new_prealloc_table(void)
+{
+ static unsigned int table_idx;
+
+ __MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
+ "Enough xlat tables not allocated");
+
+ return (uint64_t *)(xlat_tables[table_idx++]);
+}
+
+/* Splits a block into table with entries spanning the old block */
+
+static void split_pte_block_desc(uint64_t *pte, int level)
+{
+ uint64_t old_block_desc = *pte;
+ uint64_t *new_table;
+ unsigned int i = 0;
+
+ /* get address size shift bits for next level */
+
+ int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1);
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("Splitting existing PTE %p(L%d)\n", pte, level);
+#endif
+
+ new_table = new_prealloc_table();
+
+ for (i = 0; i < XLAT_TABLE_ENTRIES; i++)
+ {
+ new_table[i] = old_block_desc | (i << levelshift);
+
+ if ((level + 1) == 3)
+ {
+ new_table[i] |= PTE_PAGE_DESC;
+ }
+ }
+
+ /* Overwrite existing PTE set the new table into effect */
+
+ set_pte_table_desc(pte, new_table, level);
+}
+
+/* Create/Populate translation table(s) for given region */
+
+static void init_xlat_tables(const struct arm_mmu_region *region)
+{
+ uint64_t *pte;
+ uint64_t virt = region->base_va;
+ uint64_t phys = region->base_pa;
+ uint64_t size = region->size;
+ uint64_t attrs = region->attrs;
+ uint64_t level_size;
+ uint64_t *new_table;
+ unsigned int level = XLAT_TABLE_BASE_LEVEL;
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("mmap: virt %llx phys %llx size %llx\n", virt, phys, size);
+#endif
+
+ /* check minimum alignment requirement for given mmap region */
+
+ __MMU_ASSERT(((virt & (PAGE_SIZE - 1)) == 0) &&
+ ((size & (PAGE_SIZE - 1)) == 0),
+ "address/size are not page aligned\n");
Review Comment:
```suggestion
__MMU_ASSERT(((virt & (PAGE_SIZE - 1)) == 0) &&
((size & (PAGE_SIZE - 1)) == 0),
"address/size are not page aligned\n");
```
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,606 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#include "arm64_trace_printf.h"
+
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one
+ * complete table */
+#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX 3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+ (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+
+#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT \
+ (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT \
+ (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT \
+ (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+ (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+ (XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+ ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21) - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \
+ ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \
+ ? 0U \
+ : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \
+ ? 1U \
+ : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \
+ ? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \
+ (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
+ CONFIG_ARM64_VA_BITS)
+
+static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
+ NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
+
+static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+
+#if (CONFIG_ARM64_PA_BITS == 48)
+#define TCR_PS_BITS TCR_PS_BITS_256TB
+#elif (CONFIG_ARM64_PA_BITS == 44)
+#define TCR_PS_BITS TCR_PS_BITS_16TB
+#elif (CONFIG_ARM64_PA_BITS == 42)
+#define TCR_PS_BITS TCR_PS_BITS_4TB
+#elif (CONFIG_ARM64_PA_BITS == 40)
+#define TCR_PS_BITS TCR_PS_BITS_1TB
+#elif (CONFIG_ARM64_PA_BITS == 36)
+#define TCR_PS_BITS TCR_PS_BITS_64GB
+#else
+#define TCR_PS_BITS TCR_PS_BITS_4GB
+#endif
+
+/* Translation table control register settings */
+
+static uint64_t get_tcr(int el)
+{
+ uint64_t tcr;
+ uint64_t va_bits = CONFIG_ARM64_VA_BITS;
+ uint64_t tcr_ps_bits;
+
+ tcr_ps_bits = TCR_PS_BITS;
+
+ if (el == 1)
+ {
+ tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+
+ /* TCR_EL1.EPD1: Disable translation table walk for addresses
+ * that are translated using TTBR1_EL1.
+ */
+
+ tcr |= TCR_EPD1_DISABLE;
+ }
+ else
+ {
+ tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+ }
+
+ tcr |= TCR_T0SZ(va_bits);
+
+ /* Translation table walk is cacheable, inner/outer WBWA and
+ * inner shareable
+ */
+
+ tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+ return tcr;
+}
+
+static int pte_desc_type(uint64_t *pte)
+{
+ return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static uint64_t *calculate_pte_index(uint64_t addr, int level)
+{
+ int base_level = XLAT_TABLE_BASE_LEVEL;
+ uint64_t *pte;
+ uint64_t idx;
+ unsigned int i;
+
+ /* Walk through all translation tables to find pte index */
+
+ pte = (uint64_t *)base_xlat_table;
+ for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++)
+ {
+ idx = XLAT_TABLE_VA_IDX(addr, i);
+ pte += idx;
+
+ /* Found pte index */
+
+ if (i == level)
+ {
+ return pte;
+ }
+
+ /* if PTE is not table desc, can't traverse */
+
+ if (pte_desc_type(pte) != PTE_TABLE_DESC)
+ {
+ return NULL;
+ }
+
+ /* Move to the next translation table level */
+
+ pte = (uint64_t *)(*pte & 0x0000fffffffff000);
+ }
+
+ return NULL;
+}
+
+static void set_pte_table_desc(uint64_t *pte, uint64_t *table,
+ unsigned int level)
+{
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: [Table] %p\n", pte, table);
+#endif
+
+ /* Point pte to new table */
+
+ *pte = PTE_TABLE_DESC | (uint64_t)table;
+}
+
+static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
+ unsigned int attrs, unsigned int level)
+{
+ uint64_t desc = addr_pa;
+ unsigned int mem_type;
+
+ desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+ /* NS bit for security memory access from secure state */
+
+ desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+ /* AP bits for Data access permission */
+
+ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+ /* the access flag */
+
+ desc |= PTE_BLOCK_DESC_AF;
+
+ /* memory attribute index field */
+
+ mem_type = MT_TYPE(attrs);
+ desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+ switch (mem_type)
+ {
+ case MT_DEVICE_NGNRNE:
+ case MT_DEVICE_NGNRE:
+ case MT_DEVICE_GRE:
+ {
+ /* Access to Device memory and non-cacheable memory are coherent
+ * for all observers in the system and are treated as
+ * Outer shareable, so, for these 2 types of memory,
+ * it is not strictly needed to set shareability field
+ */
+
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+
+ /* Map device memory as execute-never */
+
+ desc |= PTE_BLOCK_DESC_PXN;
+ desc |= PTE_BLOCK_DESC_UXN;
+ break;
+ }
+
+ case MT_NORMAL_NC:
+ case MT_NORMAL:
+ {
+ /* Make Normal RW memory as execute never */
+
+ if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+ {
+ desc |= PTE_BLOCK_DESC_PXN;
+ }
+ if (mem_type == MT_NORMAL)
+ {
Review Comment:
pease add 2 spaces for this block
##########
arch/arm64/src/common/arm64_mmu.h:
##########
@@ -0,0 +1,246 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+#define __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Following Memory types supported through MAIR encodings can be passed
+ * by user through "attrs"(attributes) field of specified memory region.
+ * As MAIR supports such 8 encodings, we will reserve attrs[2:0];
+ * so that we can provide encodings upto 7 if needed in future.
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a, B2.7.2
+ */
+#define MT_TYPE_MASK 0x7U
+#define MT_TYPE(attr) (attr & MT_TYPE_MASK)
+#define MT_DEVICE_NGNRNE 0U
+#define MT_DEVICE_NGNRE 1U
+#define MT_DEVICE_GRE 2U
+#define MT_NORMAL_NC 3U
+#define MT_NORMAL 4U
+
+#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
+ (0x04 << (MT_DEVICE_NGNRE * 8)) | \
+ (0x0c << (MT_DEVICE_GRE * 8)) | \
+ (0x44 << (MT_NORMAL_NC * 8)) | \
+ (0xffUL << (MT_NORMAL * 8)))
+
+/* More flags from user's perpective are supported using remaining bits
+ * of "attrs" field, i.e. attrs[31:3], underlying code will take care
+ * of setting PTE fields correctly.
+ *
+ * current usage of attrs[31:3] is:
+ * attrs[3] : Access Permissions
+ * attrs[4] : Memory access from secure/ns state
+ * attrs[5] : Execute Permissions
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a
+ */
+
+#define MT_PERM_SHIFT 3U
+#define MT_SEC_SHIFT 4U
+#define MT_EXECUTE_SHIFT 5U
+
+#define MT_RO (0U << MT_PERM_SHIFT)
+#define MT_RW (1U << MT_PERM_SHIFT)
+
+#define MT_SECURE (0U << MT_SEC_SHIFT)
+#define MT_NS (1U << MT_SEC_SHIFT)
+
+#define MT_EXECUTE (0U << MT_EXECUTE_SHIFT)
+#define MT_EXECUTE_NEVER (1U << MT_EXECUTE_SHIFT)
+
+/* Some compound attributes for most common usages */
+
+#define MT_CODE (MT_NORMAL | MT_RO | MT_EXECUTE)
+#define MT_RODATA (MT_NORMAL | MT_RO | MT_EXECUTE_NEVER)
+
+/* PTE descriptor can be Block descriptor or Table descriptor
+ * or Page descriptor.
+ */
+
+#define PTE_DESC_TYPE_MASK 3U
+#define PTE_BLOCK_DESC 1U
+#define PTE_TABLE_DESC 3U
+#define PTE_PAGE_DESC 3U
+#define PTE_INVALID_DESC 0U
+
+/* Block and Page descriptor attributes fields */
+
+#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2)
+#define PTE_BLOCK_DESC_NS (1ULL << 5)
+#define PTE_BLOCK_DESC_AP_RO (1ULL << 7)
+#define PTE_BLOCK_DESC_AP_RW (0ULL << 7)
+#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8)
+#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8)
+#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8)
+#define PTE_BLOCK_DESC_AF (1ULL << 10)
+#define PTE_BLOCK_DESC_NG (1ULL << 11)
+#define PTE_BLOCK_DESC_PXN (1ULL << 53)
+#define PTE_BLOCK_DESC_UXN (1ULL << 54)
+
+/* TCR definitions.
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a D13.2.112~114
+ *
+ */
+
+#define TCR_EL1_IPS_SHIFT 32U
+#define TCR_EL2_PS_SHIFT 16U
+#define TCR_EL3_PS_SHIFT 16U
+
+#define TCR_T0SZ_SHIFT 0U
+#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT)
+
+#define TCR_IRGN_NC (0ULL << 8)
+#define TCR_IRGN_WBWA (1ULL << 8)
+#define TCR_IRGN_WT (2ULL << 8)
+#define TCR_IRGN_WBNWA (3ULL << 8)
+#define TCR_IRGN_MASK (3ULL << 8)
+#define TCR_ORGN_NC (0ULL << 10)
+#define TCR_ORGN_WBWA (1ULL << 10)
+#define TCR_ORGN_WT (2ULL << 10)
+#define TCR_ORGN_WBNWA (3ULL << 10)
+#define TCR_ORGN_MASK (3ULL << 10)
+#define TCR_SHARED_NON (0ULL << 12)
+#define TCR_SHARED_OUTER (2ULL << 12)
+#define TCR_SHARED_INNER (3ULL << 12)
+#define TCR_TG0_4K (0ULL << 14)
+#define TCR_TG0_64K (1ULL << 14)
+#define TCR_TG0_16K (2ULL << 14)
+#define TCR_EPD1_DISABLE (1ULL << 23)
+
+#define TCR_PS_BITS_4GB 0x0ULL
+#define TCR_PS_BITS_64GB 0x1ULL
+#define TCR_PS_BITS_1TB 0x2ULL
+#define TCR_PS_BITS_4TB 0x3ULL
+#define TCR_PS_BITS_16TB 0x4ULL
+#define TCR_PS_BITS_256TB 0x5ULL
+
+#define CTR_EL0_DMINLINE_SHIFT 16
+#define CTR_EL0_DMINLINE_MASK BIT_MASK(4)
+#define CTR_EL0_CWG_SHIFT 24
+#define CTR_EL0_CWG_MASK BIT_MASK(4)
+
+/* clidr_el1 */
+
+#define CLIDR_EL1_LOC_SHIFT 24
+#define CLIDR_EL1_LOC_MASK BIT_MASK(3)
+#define CLIDR_EL1_CTYPE_SHIFT(level) ((level) * 3)
+#define CLIDR_EL1_CTYPE_MASK BIT_MASK(3)
+
+/* ccsidr_el1 */
+
+#define CCSIDR_EL1_LN_SZ_SHIFT 0
+#define CCSIDR_EL1_LN_SZ_MASK BIT_MASK(3)
+#define CCSIDR_EL1_WAYS_SHIFT 3
+#define CCSIDR_EL1_WAYS_MASK BIT_MASK(10)
+#define CCSIDR_EL1_SETS_SHIFT 13
+#define CCSIDR_EL1_SETS_MASK BIT_MASK(15)
+
+#ifndef __ASSEMBLY__
+
+/* Region definition data structure */
+
+struct arm_mmu_region
+{
+ /* Region Base Physical Address */
+
+ uint64_t base_pa;
+
+ /* Region Base Virtual Address */
+
+ uint64_t base_va;
+
+ /* Region size */
+
+ uint64_t size;
+
+ /* Region Name */
+
+ const char *name;
+
+ /* Region Attributes */
+
+ unsigned int attrs;
+};
+
+/* MMU configuration data structure */
+
+struct arm_mmu_config
+{
+ /* Number of regions */
+
+ uint32_t num_regions;
+
+ /* Regions */
+
+ const struct arm_mmu_region *mmu_regions;
+};
+
+struct arm_mmu_ptables
+{
+ uint64_t *base_xlat_table;
+};
+
+/* Convenience macros to represent the ARMv8-A-specific
+ * configuration for memory access permission and
+ * cache-ability attribution.
+ */
+
+#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \
+ { \
+ .name = _name, \
+ .base_pa = _base_pa, \
+ .base_va = _base_va, \
+ .size = _size, \
+ .attrs = _attrs, \
+ }
+
+#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \
+ MMU_REGION_ENTRY(name, adr, adr, sz, attrs)
+
+/* Reference to the MMU configuration.
+ *
+ * This struct is defined and populated for each SoC,
+ * and holds the build-time configuration information for the fixed MMU
+ * regions enabled during kernel initialization.
+ */
+
+extern const struct arm_mmu_config mmu_config;
+extern size_t dcache_line_size;
Review Comment:
```suggestion
EXTERN const struct arm_mmu_config mmu_config;
EXTERN size_t dcache_line_size;
```
##########
arch/arm64/src/common/arm64_sigdeliver.c:
##########
@@ -0,0 +1,155 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_sigdeliver.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "sched/sched.h"
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+#include "irq/irq.h"
+#include "arm64_fatal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_sigdeliver
+ *
+ * Description:
+ * This is the a signal handling trampoline. When a signal action was
+ * posted. The task context was mucked with and forced to branch to this
+ * location with interrupts disabled.
+ *
+ ****************************************************************************/
+
+void arm64_sigdeliver(void)
+{
+ struct tcb_s *rtcb = this_task();
+
+#ifdef CONFIG_SMP
+ /* In the SMP case, we must terminate the critical section while the signal
+ * handler executes, but we also need to restore the irqcount when the
+ * we resume the main thread of the task.
+ */
+
+ irqstate_t flags;
+ int16_t saved_irqcount;
+ struct regs_context * pctx =
Review Comment:
```suggestion
struct regs_context *pctx =
```
##########
arch/arm64/src/common/arm64_mmu.h:
##########
@@ -0,0 +1,246 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_mmu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+#define __ARCH_ARM64_SRC_COMMON_ARM64_MMU_H_
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Following Memory types supported through MAIR encodings can be passed
+ * by user through "attrs"(attributes) field of specified memory region.
+ * As MAIR supports such 8 encodings, we will reserve attrs[2:0];
+ * so that we can provide encodings upto 7 if needed in future.
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a, B2.7.2
+ */
+#define MT_TYPE_MASK 0x7U
+#define MT_TYPE(attr) (attr & MT_TYPE_MASK)
+#define MT_DEVICE_NGNRNE 0U
+#define MT_DEVICE_NGNRE 1U
+#define MT_DEVICE_GRE 2U
+#define MT_NORMAL_NC 3U
+#define MT_NORMAL 4U
+
+#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
+ (0x04 << (MT_DEVICE_NGNRE * 8)) | \
+ (0x0c << (MT_DEVICE_GRE * 8)) | \
+ (0x44 << (MT_NORMAL_NC * 8)) | \
+ (0xffUL << (MT_NORMAL * 8)))
+
+/* More flags from user's perpective are supported using remaining bits
+ * of "attrs" field, i.e. attrs[31:3], underlying code will take care
+ * of setting PTE fields correctly.
+ *
+ * current usage of attrs[31:3] is:
+ * attrs[3] : Access Permissions
+ * attrs[4] : Memory access from secure/ns state
+ * attrs[5] : Execute Permissions
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a
+ */
+
+#define MT_PERM_SHIFT 3U
+#define MT_SEC_SHIFT 4U
+#define MT_EXECUTE_SHIFT 5U
+
+#define MT_RO (0U << MT_PERM_SHIFT)
+#define MT_RW (1U << MT_PERM_SHIFT)
+
+#define MT_SECURE (0U << MT_SEC_SHIFT)
+#define MT_NS (1U << MT_SEC_SHIFT)
+
+#define MT_EXECUTE (0U << MT_EXECUTE_SHIFT)
+#define MT_EXECUTE_NEVER (1U << MT_EXECUTE_SHIFT)
+
+/* Some compound attributes for most common usages */
+
+#define MT_CODE (MT_NORMAL | MT_RO | MT_EXECUTE)
+#define MT_RODATA (MT_NORMAL | MT_RO | MT_EXECUTE_NEVER)
+
+/* PTE descriptor can be Block descriptor or Table descriptor
+ * or Page descriptor.
+ */
+
+#define PTE_DESC_TYPE_MASK 3U
+#define PTE_BLOCK_DESC 1U
+#define PTE_TABLE_DESC 3U
+#define PTE_PAGE_DESC 3U
+#define PTE_INVALID_DESC 0U
+
+/* Block and Page descriptor attributes fields */
+
+#define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2)
+#define PTE_BLOCK_DESC_NS (1ULL << 5)
+#define PTE_BLOCK_DESC_AP_RO (1ULL << 7)
+#define PTE_BLOCK_DESC_AP_RW (0ULL << 7)
+#define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8)
+#define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8)
+#define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8)
+#define PTE_BLOCK_DESC_AF (1ULL << 10)
+#define PTE_BLOCK_DESC_NG (1ULL << 11)
+#define PTE_BLOCK_DESC_PXN (1ULL << 53)
+#define PTE_BLOCK_DESC_UXN (1ULL << 54)
+
+/* TCR definitions.
+ *
+ * See Arm® Architecture Reference Manual, ARM DDI 0487E.a D13.2.112~114
+ *
+ */
+
+#define TCR_EL1_IPS_SHIFT 32U
+#define TCR_EL2_PS_SHIFT 16U
+#define TCR_EL3_PS_SHIFT 16U
+
+#define TCR_T0SZ_SHIFT 0U
+#define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT)
+
+#define TCR_IRGN_NC (0ULL << 8)
+#define TCR_IRGN_WBWA (1ULL << 8)
+#define TCR_IRGN_WT (2ULL << 8)
+#define TCR_IRGN_WBNWA (3ULL << 8)
+#define TCR_IRGN_MASK (3ULL << 8)
+#define TCR_ORGN_NC (0ULL << 10)
+#define TCR_ORGN_WBWA (1ULL << 10)
+#define TCR_ORGN_WT (2ULL << 10)
+#define TCR_ORGN_WBNWA (3ULL << 10)
+#define TCR_ORGN_MASK (3ULL << 10)
+#define TCR_SHARED_NON (0ULL << 12)
+#define TCR_SHARED_OUTER (2ULL << 12)
+#define TCR_SHARED_INNER (3ULL << 12)
+#define TCR_TG0_4K (0ULL << 14)
+#define TCR_TG0_64K (1ULL << 14)
+#define TCR_TG0_16K (2ULL << 14)
+#define TCR_EPD1_DISABLE (1ULL << 23)
+
+#define TCR_PS_BITS_4GB 0x0ULL
+#define TCR_PS_BITS_64GB 0x1ULL
+#define TCR_PS_BITS_1TB 0x2ULL
+#define TCR_PS_BITS_4TB 0x3ULL
+#define TCR_PS_BITS_16TB 0x4ULL
+#define TCR_PS_BITS_256TB 0x5ULL
+
+#define CTR_EL0_DMINLINE_SHIFT 16
+#define CTR_EL0_DMINLINE_MASK BIT_MASK(4)
+#define CTR_EL0_CWG_SHIFT 24
+#define CTR_EL0_CWG_MASK BIT_MASK(4)
+
+/* clidr_el1 */
+
+#define CLIDR_EL1_LOC_SHIFT 24
+#define CLIDR_EL1_LOC_MASK BIT_MASK(3)
+#define CLIDR_EL1_CTYPE_SHIFT(level) ((level) * 3)
+#define CLIDR_EL1_CTYPE_MASK BIT_MASK(3)
+
+/* ccsidr_el1 */
+
+#define CCSIDR_EL1_LN_SZ_SHIFT 0
+#define CCSIDR_EL1_LN_SZ_MASK BIT_MASK(3)
+#define CCSIDR_EL1_WAYS_SHIFT 3
+#define CCSIDR_EL1_WAYS_MASK BIT_MASK(10)
+#define CCSIDR_EL1_SETS_SHIFT 13
+#define CCSIDR_EL1_SETS_MASK BIT_MASK(15)
+
+#ifndef __ASSEMBLY__
+
+/* Region definition data structure */
+
+struct arm_mmu_region
+{
+ /* Region Base Physical Address */
+
+ uint64_t base_pa;
+
+ /* Region Base Virtual Address */
+
+ uint64_t base_va;
+
+ /* Region size */
+
+ uint64_t size;
+
+ /* Region Name */
+
+ const char *name;
+
+ /* Region Attributes */
+
+ unsigned int attrs;
+};
+
+/* MMU configuration data structure */
+
+struct arm_mmu_config
+{
+ /* Number of regions */
+
+ uint32_t num_regions;
+
+ /* Regions */
+
+ const struct arm_mmu_region *mmu_regions;
+};
+
+struct arm_mmu_ptables
+{
+ uint64_t *base_xlat_table;
+};
+
+/* Convenience macros to represent the ARMv8-A-specific
+ * configuration for memory access permission and
+ * cache-ability attribution.
+ */
+
+#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \
+ { \
+ .name = _name, \
+ .base_pa = _base_pa, \
+ .base_va = _base_va, \
+ .size = _size, \
+ .attrs = _attrs, \
+ }
+
+#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \
+ MMU_REGION_ENTRY(name, adr, adr, sz, attrs)
Review Comment:
let's move to Defines section
```suggestion
/* Convenience macros to represent the ARMv8-A-specific
* configuration for memory access permission and
* cache-ability attribution.
*/
#define MMU_REGION_ENTRY(_name, _base_pa, _base_va, _size, _attrs) \
{ \
.name = (_name), \
.base_pa = (_base_pa), \
.base_va = (_base_va), \
.size = (_size), \
.attrs = (_attrs), \
}
#define MMU_REGION_FLAT_ENTRY(name, adr, sz, attrs) \
MMU_REGION_ENTRY(name, adr, adr, sz, attrs)
```
##########
arch/arm64/src/common/arm64_smp.h:
##########
@@ -0,0 +1,144 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_smp.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "arm64_internal.h"
+
+#ifdef CONFIG_SMP
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* AArch64 requires at least a 8-byte stack alignment. For use with EABI and
+ * floating point, the stack must be aligned to 16-byte addresses. We will
+ * always use the EABI stack alignment
+ */
+
+#if 0
+#define SMP_STACK_ALIGNMENT STACK_ALIGNMENT
+#define SMP_STACK_MASK (SMP_STACK_ALIGNMENT - 1)
+#define SMP_STACK_ALIGN_DOWN(a) ((a) & ~SMP_STACK_MASK)
+#define SMP_STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#if 0
+#if CONFIG_SMP_NCPUS > 1
+extern uint64_t g_cpu1_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 2
+extern uint64_t g_cpu2_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 3
+extern uint64_t g_cpu3_idlestack[SMP_STACK_WORDS];
+#if CONFIG_SMP_NCPUS > 4
+# error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+#endif /* CONFIG_SMP_NCPUS > 4 */
+#endif /* CONFIG_SMP_NCPUS > 3 */
+#endif /* CONFIG_SMP_NCPUS > 2 */
+#endif /* CONFIG_SMP_NCPUS > 1 */
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: __cpu[n]_start
+ *
+ * Description:
+ * Boot functions for each CPU (other than CPU0). These functions set up
+ * the ARM operating mode, the initial stack, and configure co-processor
+ * registers. At the end of the boot, arm_cpu_boot() is called.
+ *
+ * These functions are provided by the common ARMv7-A logic.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Do not return.
+ *
+ ****************************************************************************/
+
+#if CONFIG_SMP_NCPUS > 1
+void __cpu1_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 2
+void __cpu2_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 3
+void __cpu3_start(void);
+#endif
+
+#if CONFIG_SMP_NCPUS > 4
+# error This logic needs to extended for CONFIG_SMP_NCPUS > 4
+#endif
+#endif
+
+/****************************************************************************
+ * Name: arm_cpu_boot
+ *
+ * Description:
+ * Continues the C-level initialization started by the assembly language
+ * __cpu[n]_start function. At a minimum, this function needs to
+ * initialize interrupt handling and, perhaps, wait on WFI for
+ * arm_cpu_start() to issue an SGI.
+ *
+ * This function must be provided by the each ARMv7-A MCU and implement
+ * MCU-specific initialization logic.
+ *
+ * Input Parameters:
+ * cpu - The CPU index. This is the same value that would be obtained by
+ * calling up_cpu_index();
+ *
+ * Returned Value:
+ * Does not return.
+ *
+ ****************************************************************************/
+
+void arm64_cpu_boot(int cpu);
+
+/****************************************************************************
+ * Name: arm64_enable_smp
+ *
+ * Description:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+void arm64_enable_smp(int cpu);
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_SMP */
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H */
```
##########
arch/arm64/src/common/arm64_syscall.c:
##########
@@ -0,0 +1,541 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_syscall.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+#include <syscall.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/addrenv.h>
+
+#include "arch/irq.h"
+#include "signal/signal.h"
+#include "addrenv.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dispatch_syscall
+ *
+ * Description:
+ * Call the stub function corresponding to the system call. NOTE the non-
+ * standard parameter passing:
+ *
+ * x0 = SYS_ call number
+ * x1 = parm0
+ * x2 = parm1
+ * x3 = parm2
+ * x4 = parm3
+ * x5 = parm4
+ * x6 = parm5
+ *
+ * The values of X4-X5 may be preserved in the proxy called by the user
+ * code if they are used (but otherwise will not be).
+ *
+ * WARNING: There are hard-coded values in this logic!
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LIB_SYSCALL
+static void dispatch_syscall(void) naked_function;
+static void dispatch_syscall(void)
+{
+ __asm__ __volatile__
+ (
+ " sub sp, sp, #16\n" /* Create a stack frame to hold 3 parms + lr */
+ " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */
+ " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */
+ " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */
+ " str lr, [sp, #12]\n" /* Save lr in the stack frame */
+ " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
+ " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */
+ " blx ip\n" /* Call the stub (modifies lr) */
+ " ldr lr, [sp, #12]\n" /* Restore lr */
+ " add sp, sp, #16\n" /* Destroy the stack frame */
+ " mov r2, r0\n" /* R2=Save return value in R2 */
+ " mov r0, %0\n" /* R0=SYS_syscall_return */
+ " svc %1\n"::"i"(SYS_syscall_return),
+ "i"(SYS_syscall) /* Return from the SYSCALL */
+ );
+}
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void arm64_dump_syscall(const char *tag, uint64_t cmd,
+ const struct regs_context * f_regs)
Review Comment:
```suggestion
static void arm64_dump_syscall(const char *tag, uint64_t cmd,
const struct regs_context * f_regs)
```
##########
arch/arm64/src/common/arm64_smp.h:
##########
@@ -0,0 +1,144 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_smp.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H
#define __ARCH_ARM64_SRC_COMMON_ARM64_SMP_H
```
##########
arch/arm64/src/common/arm64_syscall.c:
##########
@@ -0,0 +1,541 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_syscall.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+#include <syscall.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/addrenv.h>
+
+#include "arch/irq.h"
+#include "signal/signal.h"
+#include "addrenv.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dispatch_syscall
+ *
+ * Description:
+ * Call the stub function corresponding to the system call. NOTE the non-
+ * standard parameter passing:
+ *
+ * x0 = SYS_ call number
+ * x1 = parm0
+ * x2 = parm1
+ * x3 = parm2
+ * x4 = parm3
+ * x5 = parm4
+ * x6 = parm5
+ *
+ * The values of X4-X5 may be preserved in the proxy called by the user
+ * code if they are used (but otherwise will not be).
+ *
+ * WARNING: There are hard-coded values in this logic!
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LIB_SYSCALL
+static void dispatch_syscall(void) naked_function;
+static void dispatch_syscall(void)
+{
+ __asm__ __volatile__
+ (
+ " sub sp, sp, #16\n" /* Create a stack frame to hold 3 parms + lr */
+ " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */
+ " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */
+ " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */
+ " str lr, [sp, #12]\n" /* Save lr in the stack frame */
+ " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
+ " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */
+ " blx ip\n" /* Call the stub (modifies lr) */
+ " ldr lr, [sp, #12]\n" /* Restore lr */
+ " add sp, sp, #16\n" /* Destroy the stack frame */
+ " mov r2, r0\n" /* R2=Save return value in R2 */
+ " mov r0, %0\n" /* R0=SYS_syscall_return */
+ " svc %1\n"::"i"(SYS_syscall_return),
+ "i"(SYS_syscall) /* Return from the SYSCALL */
+ );
+}
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void arm64_dump_syscall(const char *tag, uint64_t cmd,
+ const struct regs_context * f_regs)
+{
+ svcinfo("SYSCALL %s: regs: %p cmd: %" PRId64 "\n", tag, f_regs, cmd);
+
+ svcinfo("x0: 0x%-16lx x1: 0x%lx\n",
+ f_regs->regs[REG_X0], f_regs->regs[REG_X1]);
+ svcinfo("x2: 0x%-16lx x3: 0x%lx\n",
+ f_regs->regs[REG_X2], f_regs->regs[REG_X3]);
+ svcinfo("x4: 0x%-16lx x5: 0x%lx\n",
+ f_regs->regs[REG_X4], f_regs->regs[REG_X5]);
+ svcinfo("x6: 0x%-16lx x7: 0x%lx\n",
+ f_regs->regs[REG_X6], f_regs->regs[REG_X7]);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_syscall_switch
+ *
+ * Description:
+ * task switch syscall
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_syscall_switch(uint64_t * regs)
+{
+ uint64_t cmd;
+ struct regs_context * f_regs;
+ uint64_t * ret_regs;
+
+ /* Nested interrupts are not supported */
+
+ DEBUGASSERT(regs);
+
+ f_regs = (struct regs_context *)regs;
+
+ /* The SYSCALL command is in x0 on entry. Parameters follow in x1..x7 */
+
+ cmd = f_regs->regs[REG_X0];
+
+ arm64_dump_syscall(__func__, cmd, f_regs);
+
+ switch (cmd)
+ {
+ /* x0 = SYS_restore_context: Restore task context
+ *
+ * void arm64_fullcontextrestore(uint64_t *restoreregs)
+ * noreturn_function;
+ *
+ * At this point, the following values are saved in context:
+ *
+ * x0 = SYS_restore_context
+ * x1 = restoreregs( xcp->regs, callee saved register save area)
+ */
+
+ case SYS_restore_context:
+ {
+ /* Replace 'regs' with the pointer to the register set in
+ * regs[REG_R1]. On return from the system call, that register
+ * set will determine the restored context.
+ */
+
+ ret_regs = (uint64_t *)f_regs->regs[REG_X1];
+ f_regs->regs[REG_X1] = 0; /* set the saveregs = 0 */
+
+ DEBUGASSERT(ret_regs);
+ }
+ break;
+
+ /* x0 = SYS_switch_context: This a switch context command:
+ *
+ * void arm64_switchcontext(uint64_t *saveregs, uint64_t *restoreregs);
+ *
+ * At this point, the following values are saved in context:
+ *
+ * x0 = SYS_switch_context
+ * x1 = saveregs (xcp->regs, callee saved register save area)
+ * x2 = restoreregs (xcp->regs, callee saved register save area)
+ *
+ * In this case, we do both: We save the context registers to the save
+ * register area reference by the saved contents of x1 and then set
+ * regs to the save register area referenced by the saved
+ * contents of x2.
+ */
+
+ case SYS_switch_context:
+ {
+ DEBUGASSERT(f_regs->regs[REG_X1] != 0 &&
+ f_regs->regs[REG_X2] != 0);
+ *(uint64_t **)f_regs->regs[REG_X1] = regs;
+
+ ret_regs = (uint64_t *) f_regs->regs[REG_X2];
+ }
+ break;
+
+ default:
+ {
+ svcerr("ERROR: Bad SYS call: 0x%" PRIx64 "\n", cmd);
+ ret_regs = 0;
+ return 0;
+ }
+ break;
+ }
+
+ return ret_regs;
+}
+
+/****************************************************************************
+ * Name: arm64_syscall
+ *
+ * Description:
+ * SVC interrupts will vector here with insn=the SVC instruction and
+ * xcp=the interrupt context
+ *
+ * The handler may get the SVC number be de-referencing the return
+ * address saved in the xcp and decoding the SVC instruction
+ *
+ ****************************************************************************/
+
+int arm64_syscall(uint64_t * regs)
+{
+ uint64_t cmd;
+ struct regs_context * f_regs;
Review Comment:
```suggestion
int arm64_syscall(uint64_t *regs)
{
uint64_t cmd;
struct regs_context *f_regs;
```
##########
arch/arm64/src/common/arm64_stackframe.c:
##########
@@ -0,0 +1,100 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_stackframe.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/tls.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_stack_frame
+ *
+ * Description:
+ * Allocate a stack frame in the TCB's stack to hold thread-specific data.
+ * This function may be called anytime after up_create_stack() or
+ * up_use_stack() have been called but before the task has been started.
+ *
+ * Thread data may be kept in the stack (instead of in the TCB) if it is
+ * accessed by the user code directly. This includes such things as
+ * argv[]. The stack memory is guaranteed to be in the same protection
+ * domain as the thread.
+ *
+ * The following TCB fields will be re-initialized:
+ *
+ * - adj_stack_size: Stack size after removal of the stack frame from
+ * the stack
+ * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and
+ * Arguments has been removed from the stack allocation.
+ *
+ * Input Parameters:
+ * - tcb: The TCB of new task
+ * - frame_size: The size of the stack frame to allocate.
+ *
+ * Returned Value:
+ * - A pointer to bottom of the allocated stack frame. NULL will be
+ * returned on any failures. The alignment of the returned value is
+ * the same as the alignment of the stack itself.
+ *
+ ****************************************************************************/
+
+void *up_stack_frame(struct tcb_s *tcb, size_t frame_size)
+{
+ void *ret;
+
+ /* Align the frame_size */
+
+ frame_size = STACK_ALIGN_UP(frame_size);
+
+ /* Is there already a stack allocated? Is it big enough? */
+
+ if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size)
+ {
+ return NULL;
+ }
+
+ ret = tcb->stack_base_ptr;
+ memset(ret, 0, frame_size);
+
+ /* Save the adjusted stack values in the struct tcb_s */
+
+ tcb->stack_base_ptr = (uint8_t *)tcb->stack_base_ptr + frame_size;
Review Comment:
```suggestion
tcb->stack_base_ptr = (uint8_t *)tcb->stack_base_ptr + frame_size;
```
##########
arch/arm64/src/common/arm64_syscall.c:
##########
@@ -0,0 +1,541 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_syscall.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+#include <syscall.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/addrenv.h>
+
+#include "arch/irq.h"
+#include "signal/signal.h"
+#include "addrenv.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dispatch_syscall
+ *
+ * Description:
+ * Call the stub function corresponding to the system call. NOTE the non-
+ * standard parameter passing:
+ *
+ * x0 = SYS_ call number
+ * x1 = parm0
+ * x2 = parm1
+ * x3 = parm2
+ * x4 = parm3
+ * x5 = parm4
+ * x6 = parm5
+ *
+ * The values of X4-X5 may be preserved in the proxy called by the user
+ * code if they are used (but otherwise will not be).
+ *
+ * WARNING: There are hard-coded values in this logic!
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LIB_SYSCALL
+static void dispatch_syscall(void) naked_function;
+static void dispatch_syscall(void)
+{
+ __asm__ __volatile__
+ (
+ " sub sp, sp, #16\n" /* Create a stack frame to hold 3 parms + lr */
+ " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */
+ " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */
+ " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */
+ " str lr, [sp, #12]\n" /* Save lr in the stack frame */
+ " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
+ " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */
+ " blx ip\n" /* Call the stub (modifies lr) */
+ " ldr lr, [sp, #12]\n" /* Restore lr */
+ " add sp, sp, #16\n" /* Destroy the stack frame */
+ " mov r2, r0\n" /* R2=Save return value in R2 */
+ " mov r0, %0\n" /* R0=SYS_syscall_return */
+ " svc %1\n"::"i"(SYS_syscall_return),
+ "i"(SYS_syscall) /* Return from the SYSCALL */
+ );
+}
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void arm64_dump_syscall(const char *tag, uint64_t cmd,
+ const struct regs_context * f_regs)
+{
+ svcinfo("SYSCALL %s: regs: %p cmd: %" PRId64 "\n", tag, f_regs, cmd);
+
+ svcinfo("x0: 0x%-16lx x1: 0x%lx\n",
+ f_regs->regs[REG_X0], f_regs->regs[REG_X1]);
+ svcinfo("x2: 0x%-16lx x3: 0x%lx\n",
+ f_regs->regs[REG_X2], f_regs->regs[REG_X3]);
+ svcinfo("x4: 0x%-16lx x5: 0x%lx\n",
+ f_regs->regs[REG_X4], f_regs->regs[REG_X5]);
+ svcinfo("x6: 0x%-16lx x7: 0x%lx\n",
+ f_regs->regs[REG_X6], f_regs->regs[REG_X7]);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_syscall_switch
+ *
+ * Description:
+ * task switch syscall
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_syscall_switch(uint64_t * regs)
+{
+ uint64_t cmd;
+ struct regs_context * f_regs;
+ uint64_t * ret_regs;
Review Comment:
```suggestion
uint64_t *arm64_syscall_switch(uint64_t *regs)
{
uint64_t cmd;
struct regs_context *f_regs;
uint64_t *ret_regs;
```
##########
arch/arm64/src/common/arm64_task_sched.c:
##########
@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_task_sched.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <sched.h>
+#include <debug.h>
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <arch/syscall.h>
+
+#include "sched/sched.h"
+#include "group/group.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_saveusercontext
+ *
+ * Description:
+ * Save the current thread context. Full prototype is:
+ *
+ * int up_saveusercontext(void *saveregs);
+ *
+ * Returned Value:
+ * 0: Normal return
+ * 1: Context switch return
+ *
+ ****************************************************************************/
+#ifdef CONFIG_BUILD_FLAT
+
+int up_saveusercontext(void * saveregs)
Review Comment:
```suggestion
int up_saveusercontext(void *saveregs)
```
##########
arch/arm64/src/common/arm64_task_sched.c:
##########
@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_task_sched.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <sched.h>
+#include <debug.h>
+#include <assert.h>
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <arch/syscall.h>
+
+#include "sched/sched.h"
+#include "group/group.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_saveusercontext
+ *
+ * Description:
+ * Save the current thread context. Full prototype is:
+ *
+ * int up_saveusercontext(void *saveregs);
+ *
+ * Returned Value:
+ * 0: Normal return
+ * 1: Context switch return
+ *
+ ****************************************************************************/
+#ifdef CONFIG_BUILD_FLAT
+
+int up_saveusercontext(void * saveregs)
+{
+ irqstate_t flags;
+
+ /* Take a snapshot of the thread context right now */
+
+ flags = enter_critical_section();
+
+ arm64_context_snapshot(saveregs);
+
+ leave_critical_section(flags);
+ return 0;
+}
+
+#else
+
+int up_saveusercontext(void *saveregs)
+{
+ return sys_call1(SYS_save_context, (uintptr_t)saveregs);
+}
+
+#endif
+
+/****************************************************************************
+ * Name: arm64_fullcontextrestore
+ *
+ * Description:
+ * Restore the current thread context. Full prototype is:
+ *
+ * void arm64_fullcontextrestore(uint64_t *restoreregs) noreturn_function;
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void arm64_fullcontextrestore(uint64_t *restoreregs)
+{
+ sys_call1(SYS_restore_context, (uintptr_t)restoreregs);
+
+ __builtin_unreachable();
+}
+
+/****************************************************************************
+ * Name: arm64_switchcontext
+ *
+ * Description:
+ * Save the current thread context and restore the specified context.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void arm64_switchcontext(uint64_t ** saveregs, uint64_t * restoreregs)
Review Comment:
```suggestion
void arm64_switchcontext(uint64_t **saveregs, uint64_t *restoreregs)
```
##########
arch/arm64/src/common/arm64_syscall.c:
##########
@@ -0,0 +1,541 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_syscall.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+#include <syscall.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/addrenv.h>
+
+#include "arch/irq.h"
+#include "signal/signal.h"
+#include "addrenv.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dispatch_syscall
+ *
+ * Description:
+ * Call the stub function corresponding to the system call. NOTE the non-
+ * standard parameter passing:
+ *
+ * x0 = SYS_ call number
+ * x1 = parm0
+ * x2 = parm1
+ * x3 = parm2
+ * x4 = parm3
+ * x5 = parm4
+ * x6 = parm5
+ *
+ * The values of X4-X5 may be preserved in the proxy called by the user
+ * code if they are used (but otherwise will not be).
+ *
+ * WARNING: There are hard-coded values in this logic!
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LIB_SYSCALL
+static void dispatch_syscall(void) naked_function;
+static void dispatch_syscall(void)
+{
+ __asm__ __volatile__
+ (
+ " sub sp, sp, #16\n" /* Create a stack frame to hold 3 parms + lr */
+ " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */
+ " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */
+ " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */
+ " str lr, [sp, #12]\n" /* Save lr in the stack frame */
+ " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
+ " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */
+ " blx ip\n" /* Call the stub (modifies lr) */
+ " ldr lr, [sp, #12]\n" /* Restore lr */
+ " add sp, sp, #16\n" /* Destroy the stack frame */
+ " mov r2, r0\n" /* R2=Save return value in R2 */
+ " mov r0, %0\n" /* R0=SYS_syscall_return */
+ " svc %1\n"::"i"(SYS_syscall_return),
+ "i"(SYS_syscall) /* Return from the SYSCALL */
+ );
+}
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void arm64_dump_syscall(const char *tag, uint64_t cmd,
+ const struct regs_context * f_regs)
+{
+ svcinfo("SYSCALL %s: regs: %p cmd: %" PRId64 "\n", tag, f_regs, cmd);
+
+ svcinfo("x0: 0x%-16lx x1: 0x%lx\n",
+ f_regs->regs[REG_X0], f_regs->regs[REG_X1]);
+ svcinfo("x2: 0x%-16lx x3: 0x%lx\n",
+ f_regs->regs[REG_X2], f_regs->regs[REG_X3]);
+ svcinfo("x4: 0x%-16lx x5: 0x%lx\n",
+ f_regs->regs[REG_X4], f_regs->regs[REG_X5]);
+ svcinfo("x6: 0x%-16lx x7: 0x%lx\n",
+ f_regs->regs[REG_X6], f_regs->regs[REG_X7]);
Review Comment:
```suggestion
svcinfo("x0: 0x%-16lx x1: 0x%lx\n",
f_regs->regs[REG_X0], f_regs->regs[REG_X1]);
svcinfo("x2: 0x%-16lx x3: 0x%lx\n",
f_regs->regs[REG_X2], f_regs->regs[REG_X3]);
svcinfo("x4: 0x%-16lx x5: 0x%lx\n",
f_regs->regs[REG_X4], f_regs->regs[REG_X5]);
svcinfo("x6: 0x%-16lx x7: 0x%lx\n",
f_regs->regs[REG_X6], f_regs->regs[REG_X7]);
```
##########
arch/arm64/src/qemu/chip.h:
##########
@@ -0,0 +1,42 @@
+/****************************************************************************
+ * arch/arm64/src/qemu/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_QEMU_CHIP_H__
+#define __ARCH_ARM64_SRC_QEMU_CHIP_H__
Review Comment:
```suggestion
#ifndef __ARCH_ARM64_SRC_QEMU_CHIP_H
#define __ARCH_ARM64_SRC_QEMU_CHIP_H
```
##########
arch/arm64/src/common/arm64_vfork.c:
##########
@@ -0,0 +1,248 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_vfork.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/sched.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include "sched/sched.h"
+
+#include "arm64_arch.h"
+#include "arm64_vfork.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+
+void arm64_vfork_fpureg_save(struct vfork_s *context)
+{
+ irqstate_t flags;
+
+ arm64_fpu_disable();
+
+ /* Take a snapshot of the thread fpu reg context right now */
+
+ flags = enter_critical_section();
+
+ arm64_fpu_save(&context->fpu);
+ __DSB();
+
+ leave_critical_section(flags);
+ arm64_fpu_enable();
+}
+
+#endif
+
+/****************************************************************************
+ * Name: vfork
+ *
+ * Description:
+ * The vfork() function has the same effect as fork(), except that the
+ * behavior is undefined if the process created by vfork() either modifies
+ * any data other than a variable of type pid_t used to store the return
+ * value from vfork(), or returns from the function in which vfork() was
+ * called, or calls any other function before successfully calling _exit()
+ * or one of the exec family of functions.
+ *
+ * The overall sequence is:
+ *
+ * 1) User code calls vfork(). vfork() collects context information and
+ * transfers control up up_vfork().
+ * 2) up_vfork() and calls nxtask_setup_vfork().
+ * 3) nxtask_setup_vfork() allocates and configures the child task's TCB.
+ * This consists of:
+ * - Allocation of the child task's TCB.
+ * - Initialization of file descriptors and streams
+ * - Configuration of environment variables
+ * - Allocate and initialize the stack
+ * - Setup the input parameters for the task.
+ * - Initialization of the TCB (including call to up_initial_state())
+ * 4) up_vfork() provides any additional operating context. up_vfork must:
+ * - Initialize special values in any CPU registers that were not
+ * already configured by up_initial_state()
+ * 5) up_vfork() then calls nxtask_start_vfork()
+ * 6) nxtask_start_vfork() then executes the child thread.
+ *
+ * nxtask_abort_vfork() may be called if an error occurs between steps 3 and
+ * 6.
+ *
+ * Input Parameters:
+ * context - Caller context information saved by vfork()
+ *
+ * Returned Value:
+ * Upon successful completion, vfork() returns 0 to the child process and
+ * returns the process ID of the child process to the parent process.
+ * Otherwise, -1 is returned to the parent, no child process is created,
+ * and errno is set to indicate the error.
+ *
+ ****************************************************************************/
+
+pid_t up_vfork(const struct vfork_s *context)
+{
+ struct tcb_s *parent = this_task();
+ struct task_tcb_s *child;
+ uint64_t newsp;
+ uint64_t newfp;
+ uint64_t newtop;
+ uint64_t stacktop;
+ uint64_t stackutil;
+ char * stack_ptr;
+ struct regs_context * pvforkctx;
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * pfpuctx;
Review Comment:
```suggestion
char *stack_ptr;
struct regs_context *pvforkctx;
#ifdef CONFIG_ARCH_FPU
struct fpu_reg *pfpuctx;
```
##########
arch/arm64/src/common/arm64_testset.S:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_testset.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/spinlock.h>
+
+#include "arch/syscall.h"
+#include "arm64_macro.inc"
+
+
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
+.text
Review Comment:
duplicates line 46
##########
arch/arm64/src/common/arm64_syscall.c:
##########
@@ -0,0 +1,541 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_syscall.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+#include <syscall.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/sched.h>
+#include <nuttx/addrenv.h>
+
+#include "arch/irq.h"
+#include "signal/signal.h"
+#include "addrenv.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dispatch_syscall
+ *
+ * Description:
+ * Call the stub function corresponding to the system call. NOTE the non-
+ * standard parameter passing:
+ *
+ * x0 = SYS_ call number
+ * x1 = parm0
+ * x2 = parm1
+ * x3 = parm2
+ * x4 = parm3
+ * x5 = parm4
+ * x6 = parm5
+ *
+ * The values of X4-X5 may be preserved in the proxy called by the user
+ * code if they are used (but otherwise will not be).
+ *
+ * WARNING: There are hard-coded values in this logic!
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LIB_SYSCALL
+static void dispatch_syscall(void) naked_function;
+static void dispatch_syscall(void)
+{
+ __asm__ __volatile__
+ (
+ " sub sp, sp, #16\n" /* Create a stack frame to hold 3 parms + lr */
+ " str r4, [sp, #0]\n" /* Move parameter 4 (if any) into position */
+ " str r5, [sp, #4]\n" /* Move parameter 5 (if any) into position */
+ " str r6, [sp, #8]\n" /* Move parameter 6 (if any) into position */
+ " str lr, [sp, #12]\n" /* Save lr in the stack frame */
+ " ldr ip, =g_stublookup\n" /* R12=The base of the stub lookup table */
+ " ldr ip, [ip, r0, lsl #2]\n" /* R12=The address of the stub for this SYSCALL */
+ " blx ip\n" /* Call the stub (modifies lr) */
+ " ldr lr, [sp, #12]\n" /* Restore lr */
+ " add sp, sp, #16\n" /* Destroy the stack frame */
+ " mov r2, r0\n" /* R2=Save return value in R2 */
+ " mov r0, %0\n" /* R0=SYS_syscall_return */
+ " svc %1\n"::"i"(SYS_syscall_return),
+ "i"(SYS_syscall) /* Return from the SYSCALL */
+ );
+}
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void arm64_dump_syscall(const char *tag, uint64_t cmd,
+ const struct regs_context * f_regs)
+{
+ svcinfo("SYSCALL %s: regs: %p cmd: %" PRId64 "\n", tag, f_regs, cmd);
+
+ svcinfo("x0: 0x%-16lx x1: 0x%lx\n",
+ f_regs->regs[REG_X0], f_regs->regs[REG_X1]);
+ svcinfo("x2: 0x%-16lx x3: 0x%lx\n",
+ f_regs->regs[REG_X2], f_regs->regs[REG_X3]);
+ svcinfo("x4: 0x%-16lx x5: 0x%lx\n",
+ f_regs->regs[REG_X4], f_regs->regs[REG_X5]);
+ svcinfo("x6: 0x%-16lx x7: 0x%lx\n",
+ f_regs->regs[REG_X6], f_regs->regs[REG_X7]);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_syscall_switch
+ *
+ * Description:
+ * task switch syscall
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_syscall_switch(uint64_t * regs)
+{
+ uint64_t cmd;
+ struct regs_context * f_regs;
+ uint64_t * ret_regs;
+
+ /* Nested interrupts are not supported */
+
+ DEBUGASSERT(regs);
+
+ f_regs = (struct regs_context *)regs;
+
+ /* The SYSCALL command is in x0 on entry. Parameters follow in x1..x7 */
+
+ cmd = f_regs->regs[REG_X0];
+
+ arm64_dump_syscall(__func__, cmd, f_regs);
+
+ switch (cmd)
+ {
+ /* x0 = SYS_restore_context: Restore task context
+ *
+ * void arm64_fullcontextrestore(uint64_t *restoreregs)
+ * noreturn_function;
+ *
+ * At this point, the following values are saved in context:
+ *
+ * x0 = SYS_restore_context
+ * x1 = restoreregs( xcp->regs, callee saved register save area)
+ */
+
+ case SYS_restore_context:
+ {
+ /* Replace 'regs' with the pointer to the register set in
+ * regs[REG_R1]. On return from the system call, that register
+ * set will determine the restored context.
+ */
+
+ ret_regs = (uint64_t *)f_regs->regs[REG_X1];
+ f_regs->regs[REG_X1] = 0; /* set the saveregs = 0 */
+
+ DEBUGASSERT(ret_regs);
+ }
+ break;
+
+ /* x0 = SYS_switch_context: This a switch context command:
+ *
+ * void arm64_switchcontext(uint64_t *saveregs, uint64_t *restoreregs);
+ *
+ * At this point, the following values are saved in context:
+ *
+ * x0 = SYS_switch_context
+ * x1 = saveregs (xcp->regs, callee saved register save area)
+ * x2 = restoreregs (xcp->regs, callee saved register save area)
+ *
+ * In this case, we do both: We save the context registers to the save
+ * register area reference by the saved contents of x1 and then set
+ * regs to the save register area referenced by the saved
+ * contents of x2.
+ */
+
+ case SYS_switch_context:
+ {
+ DEBUGASSERT(f_regs->regs[REG_X1] != 0 &&
+ f_regs->regs[REG_X2] != 0);
+ *(uint64_t **)f_regs->regs[REG_X1] = regs;
+
+ ret_regs = (uint64_t *) f_regs->regs[REG_X2];
+ }
+ break;
+
+ default:
+ {
+ svcerr("ERROR: Bad SYS call: 0x%" PRIx64 "\n", cmd);
+ ret_regs = 0;
+ return 0;
+ }
+ break;
+ }
+
+ return ret_regs;
+}
+
+/****************************************************************************
+ * Name: arm64_syscall
+ *
+ * Description:
+ * SVC interrupts will vector here with insn=the SVC instruction and
+ * xcp=the interrupt context
+ *
+ * The handler may get the SVC number be de-referencing the return
+ * address saved in the xcp and decoding the SVC instruction
+ *
+ ****************************************************************************/
+
+int arm64_syscall(uint64_t * regs)
+{
+ uint64_t cmd;
+ struct regs_context * f_regs;
+
+ /* Nested interrupts are not supported */
+
+ DEBUGASSERT(regs);
+
+ f_regs = (struct regs_context *)regs;
+
+ /* The SYSCALL command is in x0 on entry. Parameters follow in x1..x7 */
+
+ cmd = f_regs->regs[REG_X0];
+
+ arm64_dump_syscall(__func__, cmd, f_regs);
+
+ switch (cmd)
+ {
+ /* R0=SYS_syscall_return: This a SYSCALL return command:
+ *
+ * void arm_syscall_return(void);
+ *
+ * At this point, the following values are saved in context:
+ *
+ * R0 = SYS_syscall_return
+ *
+ * We need to restore the saved return address and return in
+ * unprivileged thread mode.
+ */
+
+#ifdef CONFIG_LIB_SYSCALL
+ case SYS_syscall_return:
+ {
+ struct tcb_s *rtcb = nxsched_self();
+ int index = (int)rtcb->xcp.nsyscalls - 1;
+
+ /* Make sure that there is a saved SYSCALL return address. */
+
+ DEBUGASSERT(index >= 0);
+
+ /* Setup to return to the saved SYSCALL return address in
+ * the original mode.
+ */
+
+ regs[REG_PC] = rtcb->xcp.syscall[index].sysreturn;
+#ifdef CONFIG_BUILD_KERNEL
+ regs[REG_CPSR] = rtcb->xcp.syscall[index].cpsr;
+#endif
+ /* The return value must be in R0-R1. dispatch_syscall()
+ * temporarily moved the value for R0 into R2.
+ */
+
+ regs[REG_R0] = regs[REG_R2];
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* If this is the outermost SYSCALL and if there is a saved user
+ * stack pointer, then restore the user stack pointer on this
+ * final return to user code.
+ */
+
+ if (index == 0 && rtcb->xcp.ustkptr != NULL)
+ {
+ regs[REG_SP] = (uint32_t)rtcb->xcp.ustkptr;
+ rtcb->xcp.ustkptr = NULL;
+ }
+#endif
+
+ /* Save the new SYSCALL nesting level */
+
+ rtcb->xcp.nsyscalls = index;
+
+ /* Handle any signal actions that were deferred while processing
+ * the system call.
+ */
+
+ rtcb->flags &= ~TCB_FLAG_SYSCALL;
+ (void)nxsig_unmask_pendingsignal();
+ }
+ break;
+#endif
+
+ /* R0=SYS_task_start: This a user task start
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ *
+ * At this point, the following values are saved in context:
+ *
+ * R0 = SYS_task_start
+ * R1 = taskentry
+ * R2 = argc
+ * R3 = argv
+ */
+
+#ifdef CONFIG_BUILD_KERNEL
+ case SYS_task_start:
+ {
+ /* Set up to return to the user-space _start function in
+ * unprivileged mode. We need:
+ *
+ * R0 = argc
+ * R1 = argv
+ * PC = taskentry
+ * CSPR = user mode
+ */
+
+ regs[REG_PC] = regs[REG_R1];
+ regs[REG_R0] = regs[REG_R2];
+ regs[REG_R1] = regs[REG_R3];
+
+ cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
+ regs[REG_CPSR] = cpsr | PSR_MODE_USR;
+ }
+ break;
+#endif
+
+ /* R0=SYS_pthread_start: This a user pthread start
+ *
+ * void up_pthread_start(pthread_startroutine_t entrypt,
+ * pthread_addr_t arg) noreturn_function;
+ *
+ * At this point, the following values are saved in context:
+ *
+ * R0 = SYS_pthread_start
+ * R1 = entrypt
+ * R2 = arg
+ */
+
+#if !defined(CONFIG_BUILD_FLAT) && !defined(CONFIG_DISABLE_PTHREAD)
+ case SYS_pthread_start:
+ {
+ /* Set up to enter the user-space pthread start-up function in
+ * unprivileged mode. We need:
+ *
+ * R0 = entrypt
+ * R1 = arg
+ * PC = startup
+ * CSPR = user mode
+ */
+
+ regs[REG_PC] = regs[REG_R1];
+ regs[REG_R0] = regs[REG_R2];
+ regs[REG_R1] = regs[REG_R3];
+
+ cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
+ regs[REG_CPSR] = cpsr | PSR_MODE_USR;
+ }
+ break;
+#endif
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* R0=SYS_signal_handler: This a user signal handler callback
+ *
+ * void signal_handler(_sa_sigaction_t sighand, int signo,
+ * siginfo_t *info, void *ucontext);
+ *
+ * At this point, the following values are saved in context:
+ *
+ * R0 = SYS_signal_handler
+ * R1 = sighand
+ * R2 = signo
+ * R3 = info
+ * ucontext (on the stack)
+ */
+
+ case SYS_signal_handler:
+ {
+ struct tcb_s *rtcb = nxsched_self();
+
+ /* Remember the caller's return address */
+
+ DEBUGASSERT(rtcb->xcp.sigreturn == 0);
+ rtcb->xcp.sigreturn = regs[REG_PC];
+
+ /* Set up to return to the user-space trampoline function in
+ * unprivileged mode.
+ */
+
+ regs[REG_PC] = (uint32_t)ARCH_DATA_RESERVE->ar_sigtramp;
+ cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
+ regs[REG_CPSR] = cpsr | PSR_MODE_USR;
+
+ /* Change the parameter ordering to match the expectation of struct
+ * userpace_s signal_handler.
+ */
+
+ regs[REG_R0] = regs[REG_R1]; /* sighand */
+ regs[REG_R1] = regs[REG_R2]; /* signal */
+ regs[REG_R2] = regs[REG_R3]; /* info */
+ regs[REG_R3] = regs[REG_R4]; /* ucontext */
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* If we are signalling a user process, then we must be operating
+ * on the kernel stack now. We need to switch back to the user
+ * stack before dispatching the signal handler to the user code.
+ * The existence of an allocated kernel stack is sufficient
+ * information to make this decision.
+ */
+
+ if (rtcb->xcp.kstack != NULL)
+ {
+ DEBUGASSERT(rtcb->xcp.kstkptr == NULL &&
+ rtcb->xcp.ustkptr != NULL);
+
+ rtcb->xcp.kstkptr = (uint32_t *)regs[REG_SP];
+ regs[REG_SP] = (uint32_t)rtcb->xcp.ustkptr;
+ }
+#endif
+ }
+ break;
+#endif
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* R0=SYS_signal_handler_return: This a user signal handler callback
+ *
+ * void signal_handler_return(void);
+ *
+ * At this point, the following values are saved in context:
+ *
+ * R0 = SYS_signal_handler_return
+ */
+
+ case SYS_signal_handler_return:
+ {
+ struct tcb_s *rtcb = nxsched_self();
+
+ /* Set up to return to the kernel-mode signal dispatching logic. */
+
+ DEBUGASSERT(rtcb->xcp.sigreturn != 0);
+
+ regs[REG_PC] = rtcb->xcp.sigreturn;
+ cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
+ regs[REG_CPSR] = cpsr | PSR_MODE_SVC;
+ rtcb->xcp.sigreturn = 0;
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* We must enter here be using the user stack. We need to switch
+ * to back to the kernel user stack before returning to the kernel
+ * mode signal trampoline.
+ */
+
+ if (rtcb->xcp.kstack != NULL)
+ {
+ DEBUGASSERT(rtcb->xcp.kstkptr != NULL &&
+ (uint32_t)rtcb->xcp.ustkptr == regs[REG_SP]);
+
+ regs[REG_SP] = (uint32_t)rtcb->xcp.kstkptr;
+ rtcb->xcp.kstkptr = NULL;
+ }
+#endif
+ }
+ break;
+#endif
+
+ /* This is not an architecture-specific system call. If NuttX is built
+ * as a standalone kernel with a system call interface, then all of the
+ * additional system calls must be handled as in the default case.
+ */
+
+ default:
+ {
+#ifdef CONFIG_LIB_SYSCALL
+ struct tcb_s *rtcb = nxsched_self();
+ int index = rtcb->xcp.nsyscalls;
+
+ /* Verify that the SYS call number is within range */
+
+ DEBUGASSERT(cmd >= CONFIG_SYS_RESERVED && cmd < SYS_maxsyscall);
+
+ /* Make sure that there is a no saved SYSCALL return address. We
+ * cannot yet handle nested system calls.
+ */
+
+ DEBUGASSERT(index < CONFIG_SYS_NNEST);
+
+ /* Setup to return to dispatch_syscall in privileged mode. */
+
+ rtcb->xcp.syscall[index].sysreturn = regs[REG_PC];
+#ifdef CONFIG_BUILD_KERNEL
+ rtcb->xcp.syscall[index].cpsr = regs[REG_CPSR];
+#endif
+
+ regs[REG_PC] = (uint32_t)dispatch_syscall;
+#ifdef CONFIG_BUILD_KERNEL
+ cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
+ regs[REG_CPSR] = cpsr | PSR_MODE_SVC;
+#endif
+ /* Offset R0 to account for the reserved values */
+
+ regs[REG_R0] -= CONFIG_SYS_RESERVED;
+
+ /* Indicate that we are in a syscall handler. */
+
+ rtcb->flags |= TCB_FLAG_SYSCALL;
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* If this is the first SYSCALL and if there is an allocated
+ * kernel stack, then switch to the kernel stack.
+ */
+
+ if (index == 0 && rtcb->xcp.kstack != NULL)
+ {
+ rtcb->xcp.ustkptr = (uint32_t *)regs[REG_SP];
+ regs[REG_SP] = (uint32_t)rtcb->xcp.kstack +
+ ARCH_KERNEL_STACKSIZE;
+ }
+#endif
+
+ /* Save the new SYSCALL nesting level */
+
+ rtcb->xcp.nsyscalls = index + 1;
+#else
+ svcerr("ERROR: Bad SYS call: 0x%" PRIx64 "\n", cmd);
+ return 0;
Review Comment:
```suggestion
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
Review Comment:
```suggestion
# define CONSOLE_DEV g_uart1port /* UART1 is console */
# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
# define UART1_ASSIGNED 1
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
Review Comment:
```suggestion
config->uart->cr |= PL011_CR_UARTEN;
```
##########
arch/arm64/src/qemu/qemu_boot.c:
##########
@@ -0,0 +1,108 @@
+/****************************************************************************
+ * arch/arm64/src/qemu/qemu_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/cache.h>
+#ifdef CONFIG_PAGING
+# include <nuttx/page.h>
+#endif
+
+#include <arch/chip/chip.h>
+
+#ifdef CONFIG_SMP
+#include "arm64_smp.h"
+#endif
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+#include "qemu_boot.h"
+#include "qemu_serial.h"
+
+static const struct arm_mmu_region mmu_regions[] =
+{
+ MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
+ CONFIG_DEVICEIO_BASEADDR, MB(512),
+ MT_DEVICE_NGNRNE | MT_RW | MT_SECURE),
+
+ MMU_REGION_FLAT_ENTRY("DRAM0_S0",
+ CONFIG_RAMBANK1_ADDR, MB(512),
+ MT_NORMAL | MT_RW | MT_SECURE),
Review Comment:
```suggestion
MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
CONFIG_DEVICEIO_BASEADDR, MB(512),
MT_DEVICE_NGNRNE | MT_RW | MT_SECURE),
MMU_REGION_FLAT_ENTRY("DRAM0_S0",
CONFIG_RAMBANK1_ADDR, MB(512),
MT_NORMAL | MT_RW | MT_SECURE),
```
##########
arch/arm64/src/qemu/chip.h:
##########
@@ -0,0 +1,42 @@
+/****************************************************************************
+ * arch/arm64/src/qemu/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_QEMU_CHIP_H__
+#define __ARCH_ARM64_SRC_QEMU_CHIP_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/arch.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Macro Definitions
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM64_SRC_QEMU_CHIP_H__ */
Review Comment:
```suggestion
#endif /* __ARCH_ARM64_SRC_QEMU_CHIP_H */
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
Review Comment:
```suggestion
#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5)
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
Review Comment:
```suggestion
#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y))
```
##########
arch/arm64/src/qemu/qemu_boot.c:
##########
@@ -0,0 +1,108 @@
+/****************************************************************************
+ * arch/arm64/src/qemu/qemu_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/cache.h>
+#ifdef CONFIG_PAGING
+# include <nuttx/page.h>
+#endif
+
+#include <arch/chip/chip.h>
+
+#ifdef CONFIG_SMP
+#include "arm64_smp.h"
+#endif
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+#include "qemu_boot.h"
+#include "qemu_serial.h"
+
+static const struct arm_mmu_region mmu_regions[] =
+{
+ MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
+ CONFIG_DEVICEIO_BASEADDR, MB(512),
+ MT_DEVICE_NGNRNE | MT_RW | MT_SECURE),
+
+ MMU_REGION_FLAT_ENTRY("DRAM0_S0",
+ CONFIG_RAMBANK1_ADDR, MB(512),
+ MT_NORMAL | MT_RW | MT_SECURE),
+};
+
+const struct arm_mmu_config mmu_config =
+{
+ .num_regions = ARRAY_SIZE(mmu_regions),
+ .mmu_regions = mmu_regions,
Review Comment:
```suggestion
.num_regions = ARRAY_SIZE(mmu_regions),
.mmu_regions = mmu_regions,
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
Review Comment:
Could you please use either `u` or `U`, but not the mix in a single file?
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
Review Comment:
Could you please add Defines, Types, Public/Private Functions sections? Here and in other files
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
Review Comment:
```suggestion
bool is_console;
```
##########
arch/arm64/src/common/arm64_vfork_func.S:
##########
@@ -0,0 +1,131 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_vfork_func.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "arch/syscall.h"
+#include "arm64_macro.inc"
+#include "arm64_vfork.h"
+
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
+.text
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: vfork
+ *
+ * Description:
+ * The vfork() function has the same effect as fork(), except that the
+ * behavior is undefined if the process created by vfork() either modifies
+ * any data other than a variable of type pid_t used to store the return
+ * value from vfork(), or returns from the function in which vfork() was
+ * called, or calls any other function before successfully calling _exit()
+ * or one of the exec family of functions.
+ *
+ * This thin layer implements vfork by simply calling up_vfork() with the
+ * vfork() context as an argument. The overall sequence is:
+ *
+ * 1) User code calls vfork(). vfork() collects context information and
+ * transfers control up up_vfork().
+ * 2) up_vfork() and calls nxtask_setup_vfork().
+ * 3) nxtask_setup_vfork() allocates and configures the child task's TCB.
+ * This consists of:
+ * - Allocation of the child task's TCB.
+ * - Initialization of file descriptors and streams
+ * - Configuration of environment variables
+ * - Allocate and initialize the stack
+ * - Setup the input parameters for the task.
+ * - Initialization of the TCB (including call to up_initial_state())
+ * 4) up_vfork() provides any additional operating context. up_vfork must:
+ * - Initialize special values in any CPU registers that were not
+ * already configured by up_initial_state()
+ * 5) up_vfork() then calls nxtask_start_vfork()
+ * 6) nxtask_start_vfork() then executes the child thread.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Upon successful completion, vfork() returns 0 to the child process and
+ * returns the process ID of the child process to the parent process.
+ * Otherwise, -1 is returned to the parent, no child process is created,
+ * and errno is set to indicate the error.
+ *
+ ****************************************************************************/
+
+GTEXT(vfork)
+SECTION_FUNC(TEXT, vfork)
+ /* Create a stack frame */
+
+ mov x0, sp /* Save the value of the stack on entry */
+ stp x29, x30, [sp]
+ sub sp, sp, #8 * VFORK_REGS_SIZE /* Allocate the structure on the stack */
+
+ /* CPU registers, save all register*/
+
+ stp x0, x1, [sp, #8 * VFORK_REG_X0]
+ stp x2, x3, [sp, #8 * VFORK_REG_X2]
+ stp x4, x5, [sp, #8 * VFORK_REG_X4]
+ stp x6, x7, [sp, #8 * VFORK_REG_X6]
+ stp x8, x9, [sp, #8 * VFORK_REG_X8]
+ stp x10, x11, [sp, #8 * VFORK_REG_X10]
+ stp x12, x13, [sp, #8 * VFORK_REG_X12]
+ stp x14, x15, [sp, #8 * VFORK_REG_X14]
+ stp x16, x17, [sp, #8 * VFORK_REG_X16]
+ stp x18, x19, [sp, #8 * VFORK_REG_X18]
+ stp x20, x21, [sp, #8 * VFORK_REG_X20]
+ stp x22, x23, [sp, #8 * VFORK_REG_X22]
+ stp x24, x25, [sp, #8 * VFORK_REG_X24]
+ stp x26, x27, [sp, #8 * VFORK_REG_X26]
+ stp x28, x29, [sp, #8 * VFORK_REG_X28]
+
+ /* Save the LR, stack pointer */
+
+ stp x30, x0, [sp, #8 * VFORK_REG_LR]
+
+ /* Floating point registers */
+#ifdef CONFIG_ARCH_FPU
+ mov x0, sp
+ stp x0, x30, [sp, #-16]!
+ bl arm64_vfork_fpureg_save
+ ldp x0, x30, [sp], #16
+#endif
+
+ /* Then, call up_vfork(), passing it a pointer to the stack structure */
+
+ mov x0, sp
+ bl up_vfork
+
+ /* Release the stack data and return the value returned by up_vfork */
+
+ add sp, sp, #8 * VFORK_REGS_SIZE
+ ldp x29, x30, [sp]
+
+ ret
Review Comment:
```suggestion
ret
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
Review Comment:
Please add 2 spaces for this block
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport;
+ struct pl011_data * data;
+ int ret;
+
+ sport = (struct pl011_uart_port_s *)dev->priv;
+ data = &sport->data;
+
+ ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev);
+ arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0);
+
+ if (ret == OK)
+ {
+ up_enable_irq(sport->irq_num);
+ }
+ else
+ {
+ sinfo("error ret=%d\n", ret);
+ }
+
+ if (!data->sbsa)
+ {
+ pl011_enable(sport);
+ }
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_shutdown(struct uart_dev_s *dev)
+{
+ sinfo("%s: call unexpected\n", __func__);
+}
+
+static int qemu_pl011_setup(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+ int ret;
+ uint32_t lcrh;
+ irqstate_t i_flags;
+
+ i_flags = up_irq_save();
Review Comment:
```suggestion
i_flags = up_irq_save();
```
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <arch/syscall.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+#define PSCI_RET_INVALID_ADDRESS -9
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+uint32_t psci_version(void);
+
+typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long,
Review Comment:
```suggestion
typedef unsigned long (*psci_fn)(unsigned long, unsigned long, unsigned long,
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport;
+ struct pl011_data * data;
+ int ret;
+
+ sport = (struct pl011_uart_port_s *)dev->priv;
+ data = &sport->data;
+
+ ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev);
+ arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0);
+
+ if (ret == OK)
+ {
+ up_enable_irq(sport->irq_num);
+ }
+ else
+ {
+ sinfo("error ret=%d\n", ret);
+ }
+
+ if (!data->sbsa)
+ {
+ pl011_enable(sport);
+ }
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_shutdown(struct uart_dev_s *dev)
+{
+ sinfo("%s: call unexpected\n", __func__);
+}
+
+static int qemu_pl011_setup(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+ int ret;
+ uint32_t lcrh;
+ irqstate_t i_flags;
+
+ i_flags = up_irq_save();
+
+ /* If working in SBSA mode, we assume that UART is already configured,
+ * or does not require configuration at all (if UART is emulated by
+ * virtualization software).
+ */
+
+ if (!data->sbsa)
+ {
+ /* disable the uart */
+
+ pl011_disable(sport);
+ pl011_disable_fifo(sport);
+
+ /* Set baud rate */
+
+ ret = pl011_set_baudrate(sport, config->sys_clk_freq,
+ data->baud_rate);
+ if (ret != 0)
+ {
+ up_irq_restore(i_flags);
+ return ret;
+ }
+
+ /* Setting the default character format */
+
+ lcrh = config->uart->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
+ lcrh &= ~(BIT(0) | BIT(7));
+ lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
+ config->uart->lcr_h = lcrh;
+
+ /* Enabling the FIFOs */
+
+ pl011_enable_fifo(sport);
+ }
+
+ /* initialize all IRQs as masked */
+
+ config->uart->imsc = 0U;
+ config->uart->icr = PL011_IMSC_MASK_ALL;
+
+ if (!data->sbsa)
+ {
+ config->uart->dmacr = 0U;
+ __ISB();
+ config->uart->cr &= ~(BIT(14) | BIT(15) | BIT(1));
+ config->uart->cr |= PL011_CR_RXE | PL011_CR_TXE;
+ __ISB();
+ }
+
+ up_irq_restore(i_flags);
+
+ return 0;
+}
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/* Serial driver UART operations */
+
+static const struct uart_ops_s g_uart_ops =
+{
+ .setup = qemu_pl011_setup,
+ .shutdown = qemu_pl011_shutdown,
+ .attach = qemu_pl011_attach,
+ .detach = qemu_pl011_detach,
+ .ioctl = qemu_pl011_ioctl,
+ .receive = qemu_pl011_receive,
+ .rxint = qemu_pl011_rxint,
+ .rxavailable = qemu_pl011_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = NULL,
+#endif
+ .send = qemu_pl011_send,
+ .txint = qemu_pl011_txint,
+ .txready = qemu_pl011_txready,
+ .txempty = qemu_pl011_txempty,
+};
+
+/* This describes the state of the uart1 port. */
+
+static struct pl011_uart_port_s g_uart1priv =
+{
+ .data =
+ {
+ .baud_rate = CONFIG_UART1_BAUD, .sbsa = false,
Review Comment:
```suggestion
.baud_rate = CONFIG_UART1_BAUD,
.sbsa = false,
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport;
+ struct pl011_data * data;
+ int ret;
+
+ sport = (struct pl011_uart_port_s *)dev->priv;
+ data = &sport->data;
+
+ ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev);
+ arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0);
+
+ if (ret == OK)
+ {
+ up_enable_irq(sport->irq_num);
+ }
+ else
+ {
+ sinfo("error ret=%d\n", ret);
+ }
+
+ if (!data->sbsa)
+ {
+ pl011_enable(sport);
+ }
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_shutdown(struct uart_dev_s *dev)
+{
+ sinfo("%s: call unexpected\n", __func__);
+}
+
+static int qemu_pl011_setup(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+ int ret;
+ uint32_t lcrh;
+ irqstate_t i_flags;
+
+ i_flags = up_irq_save();
+
+ /* If working in SBSA mode, we assume that UART is already configured,
+ * or does not require configuration at all (if UART is emulated by
+ * virtualization software).
+ */
+
+ if (!data->sbsa)
+ {
+ /* disable the uart */
+
+ pl011_disable(sport);
+ pl011_disable_fifo(sport);
+
+ /* Set baud rate */
+
+ ret = pl011_set_baudrate(sport, config->sys_clk_freq,
+ data->baud_rate);
+ if (ret != 0)
+ {
+ up_irq_restore(i_flags);
+ return ret;
+ }
+
+ /* Setting the default character format */
+
+ lcrh = config->uart->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
+ lcrh &= ~(BIT(0) | BIT(7));
+ lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
+ config->uart->lcr_h = lcrh;
+
+ /* Enabling the FIFOs */
+
+ pl011_enable_fifo(sport);
+ }
+
+ /* initialize all IRQs as masked */
+
+ config->uart->imsc = 0U;
+ config->uart->icr = PL011_IMSC_MASK_ALL;
+
+ if (!data->sbsa)
+ {
+ config->uart->dmacr = 0U;
+ __ISB();
+ config->uart->cr &= ~(BIT(14) | BIT(15) | BIT(1));
+ config->uart->cr |= PL011_CR_RXE | PL011_CR_TXE;
+ __ISB();
+ }
+
+ up_irq_restore(i_flags);
+
+ return 0;
+}
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/* Serial driver UART operations */
+
+static const struct uart_ops_s g_uart_ops =
+{
+ .setup = qemu_pl011_setup,
+ .shutdown = qemu_pl011_shutdown,
+ .attach = qemu_pl011_attach,
+ .detach = qemu_pl011_detach,
+ .ioctl = qemu_pl011_ioctl,
+ .receive = qemu_pl011_receive,
+ .rxint = qemu_pl011_rxint,
+ .rxavailable = qemu_pl011_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = NULL,
+#endif
+ .send = qemu_pl011_send,
+ .txint = qemu_pl011_txint,
+ .txready = qemu_pl011_txready,
+ .txempty = qemu_pl011_txempty,
+};
+
+/* This describes the state of the uart1 port. */
+
+static struct pl011_uart_port_s g_uart1priv =
+{
+ .data =
+ {
+ .baud_rate = CONFIG_UART1_BAUD, .sbsa = false,
+ }, .config =
+ {
+ .uart = (volatile struct pl011_regs *)CONFIG_QEMU_UART_BASE,
+ .sys_clk_freq = 24000000,
+ }, .irq_num = CONFIG_QEMU_UART_IRQ, .is_console = 1,
Review Comment:
```suggestion
},
.irq_num = CONFIG_QEMU_UART_IRQ,
.is_console = 1,
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
Review Comment:
```suggestion
struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport;
+ struct pl011_data * data;
Review Comment:
```suggestion
struct pl011_uart_port_s *sport;
struct pl011_data *data;
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport;
+ struct pl011_data * data;
+ int ret;
+
+ sport = (struct pl011_uart_port_s *)dev->priv;
+ data = &sport->data;
+
+ ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev);
+ arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0);
+
+ if (ret == OK)
+ {
+ up_enable_irq(sport->irq_num);
+ }
+ else
+ {
+ sinfo("error ret=%d\n", ret);
+ }
+
+ if (!data->sbsa)
+ {
+ pl011_enable(sport);
+ }
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_shutdown(struct uart_dev_s *dev)
+{
+ sinfo("%s: call unexpected\n", __func__);
+}
+
+static int qemu_pl011_setup(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+ int ret;
+ uint32_t lcrh;
+ irqstate_t i_flags;
+
+ i_flags = up_irq_save();
+
+ /* If working in SBSA mode, we assume that UART is already configured,
+ * or does not require configuration at all (if UART is emulated by
+ * virtualization software).
+ */
+
+ if (!data->sbsa)
+ {
+ /* disable the uart */
+
+ pl011_disable(sport);
+ pl011_disable_fifo(sport);
+
+ /* Set baud rate */
+
+ ret = pl011_set_baudrate(sport, config->sys_clk_freq,
+ data->baud_rate);
+ if (ret != 0)
+ {
+ up_irq_restore(i_flags);
+ return ret;
+ }
+
+ /* Setting the default character format */
+
+ lcrh = config->uart->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
+ lcrh &= ~(BIT(0) | BIT(7));
+ lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
+ config->uart->lcr_h = lcrh;
+
+ /* Enabling the FIFOs */
+
+ pl011_enable_fifo(sport);
+ }
+
+ /* initialize all IRQs as masked */
+
+ config->uart->imsc = 0U;
+ config->uart->icr = PL011_IMSC_MASK_ALL;
+
+ if (!data->sbsa)
+ {
+ config->uart->dmacr = 0U;
+ __ISB();
+ config->uart->cr &= ~(BIT(14) | BIT(15) | BIT(1));
+ config->uart->cr |= PL011_CR_RXE | PL011_CR_TXE;
+ __ISB();
+ }
+
+ up_irq_restore(i_flags);
+
+ return 0;
+}
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/* Serial driver UART operations */
+
+static const struct uart_ops_s g_uart_ops =
+{
+ .setup = qemu_pl011_setup,
+ .shutdown = qemu_pl011_shutdown,
+ .attach = qemu_pl011_attach,
+ .detach = qemu_pl011_detach,
+ .ioctl = qemu_pl011_ioctl,
+ .receive = qemu_pl011_receive,
+ .rxint = qemu_pl011_rxint,
+ .rxavailable = qemu_pl011_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = NULL,
+#endif
+ .send = qemu_pl011_send,
+ .txint = qemu_pl011_txint,
+ .txready = qemu_pl011_txready,
+ .txempty = qemu_pl011_txempty,
+};
+
+/* This describes the state of the uart1 port. */
+
+static struct pl011_uart_port_s g_uart1priv =
+{
+ .data =
+ {
+ .baud_rate = CONFIG_UART1_BAUD, .sbsa = false,
+ }, .config =
+ {
+ .uart = (volatile struct pl011_regs *)CONFIG_QEMU_UART_BASE,
+ .sys_clk_freq = 24000000,
+ }, .irq_num = CONFIG_QEMU_UART_IRQ, .is_console = 1,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_QEMU_UART_PL011
+
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+static struct uart_dev_s g_uart1port =
+{
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE, .buffer = g_uart1rxbuffer,
+ },
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE, .buffer = g_uart1txbuffer,
+ }, .ops = &g_uart_ops, .priv = &g_uart1priv,
Review Comment:
```suggestion
.recv =
{
.size = CONFIG_UART1_RXBUFSIZE, .buffer = g_uart1rxbuffer,
},
.xmit =
{
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
.ops = &g_uart_ops,
.priv = &g_uart1priv,
```
##########
arch/arm64/src/qemu/qemu_serial.h:
##########
@@ -0,0 +1,76 @@
+/****************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_QEMU_QEMU_SERIAL_H
+#define __ARCH_ARM64_SRC_QEMU_QEMU_SERIAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_CHIP_QEMU_A53
+#define CONFIG_QEMU_UART_BASE 0x9000000
+#define CONFIG_QEMU_UART_IRQ (GIC_SPI_INT_BASE + 1)
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: qemu_earlyserialinit
+ *
+ * Description:
+ * Performs the low level UART initialization early in debug so that the
+ * serial console will be available during bootup. This must be called
+ * before arm_serialinit.
+ *
+ ****************************************************************************/
+
+#ifdef USE_EARLYSERIALINIT
+void qemu_earlyserialinit(void);
+
Review Comment:
```suggestion
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport;
+ struct pl011_data * data;
+ int ret;
+
+ sport = (struct pl011_uart_port_s *)dev->priv;
+ data = &sport->data;
+
+ ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev);
+ arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0);
+
+ if (ret == OK)
+ {
+ up_enable_irq(sport->irq_num);
+ }
+ else
+ {
+ sinfo("error ret=%d\n", ret);
+ }
+
+ if (!data->sbsa)
+ {
+ pl011_enable(sport);
+ }
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_shutdown(struct uart_dev_s *dev)
+{
+ sinfo("%s: call unexpected\n", __func__);
+}
+
+static int qemu_pl011_setup(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+ int ret;
+ uint32_t lcrh;
+ irqstate_t i_flags;
+
+ i_flags = up_irq_save();
+
+ /* If working in SBSA mode, we assume that UART is already configured,
+ * or does not require configuration at all (if UART is emulated by
+ * virtualization software).
+ */
+
+ if (!data->sbsa)
+ {
+ /* disable the uart */
+
+ pl011_disable(sport);
+ pl011_disable_fifo(sport);
+
+ /* Set baud rate */
+
+ ret = pl011_set_baudrate(sport, config->sys_clk_freq,
+ data->baud_rate);
Review Comment:
```suggestion
ret = pl011_set_baudrate(sport, config->sys_clk_freq,
data->baud_rate);
```
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport;
+ struct pl011_data * data;
+ int ret;
+
+ sport = (struct pl011_uart_port_s *)dev->priv;
+ data = &sport->data;
+
+ ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev);
+ arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0);
+
+ if (ret == OK)
+ {
+ up_enable_irq(sport->irq_num);
+ }
+ else
+ {
+ sinfo("error ret=%d\n", ret);
+ }
+
+ if (!data->sbsa)
+ {
+ pl011_enable(sport);
+ }
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_shutdown(struct uart_dev_s *dev)
+{
+ sinfo("%s: call unexpected\n", __func__);
+}
+
+static int qemu_pl011_setup(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+ int ret;
+ uint32_t lcrh;
+ irqstate_t i_flags;
+
+ i_flags = up_irq_save();
+
+ /* If working in SBSA mode, we assume that UART is already configured,
+ * or does not require configuration at all (if UART is emulated by
+ * virtualization software).
+ */
+
+ if (!data->sbsa)
+ {
+ /* disable the uart */
+
+ pl011_disable(sport);
+ pl011_disable_fifo(sport);
+
+ /* Set baud rate */
+
+ ret = pl011_set_baudrate(sport, config->sys_clk_freq,
+ data->baud_rate);
+ if (ret != 0)
+ {
+ up_irq_restore(i_flags);
+ return ret;
+ }
+
+ /* Setting the default character format */
+
+ lcrh = config->uart->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
+ lcrh &= ~(BIT(0) | BIT(7));
+ lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
+ config->uart->lcr_h = lcrh;
+
+ /* Enabling the FIFOs */
+
+ pl011_enable_fifo(sport);
+ }
+
+ /* initialize all IRQs as masked */
+
+ config->uart->imsc = 0U;
+ config->uart->icr = PL011_IMSC_MASK_ALL;
+
+ if (!data->sbsa)
+ {
+ config->uart->dmacr = 0U;
+ __ISB();
+ config->uart->cr &= ~(BIT(14) | BIT(15) | BIT(1));
+ config->uart->cr |= PL011_CR_RXE | PL011_CR_TXE;
+ __ISB();
+ }
+
+ up_irq_restore(i_flags);
+
+ return 0;
+}
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/* Serial driver UART operations */
+
+static const struct uart_ops_s g_uart_ops =
+{
+ .setup = qemu_pl011_setup,
+ .shutdown = qemu_pl011_shutdown,
+ .attach = qemu_pl011_attach,
+ .detach = qemu_pl011_detach,
+ .ioctl = qemu_pl011_ioctl,
+ .receive = qemu_pl011_receive,
+ .rxint = qemu_pl011_rxint,
+ .rxavailable = qemu_pl011_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = NULL,
+#endif
+ .send = qemu_pl011_send,
+ .txint = qemu_pl011_txint,
+ .txready = qemu_pl011_txready,
+ .txempty = qemu_pl011_txempty,
+};
+
+/* This describes the state of the uart1 port. */
+
+static struct pl011_uart_port_s g_uart1priv =
+{
+ .data =
+ {
+ .baud_rate = CONFIG_UART1_BAUD, .sbsa = false,
+ }, .config =
Review Comment:
```suggestion
},
.config =
```
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906673001
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,531 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MIN
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/* Number of bytes in @p x kibibytes/mebibytes/gibibytes */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#define BIT(n) (1UL << (n))
+#define BIT64(_n) (1ULL << (_n))
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
Review Comment:
I perfer to keep previous code which is look more readable
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906687639
##########
arch/arm64/src/common/arm64_assert.c:
##########
@@ -0,0 +1,582 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_assert.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/board.h>
+#include <nuttx/syslog/syslog.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* USB trace dumping */
+
+#ifndef CONFIG_USBDEV_TRACE
+# undef CONFIG_ARCH_USBDUMP
+#endif
+
+#ifndef CONFIG_BOARD_RESET_ON_ASSERT
+# define CONFIG_BOARD_RESET_ON_ASSERT 0
+#endif
+
+/****************************************************************************
+ * Name: arm_registerdump
+ ****************************************************************************/
+
+static void arm64_registerdump(struct regs_context * regs)
+{
+ _alert("stack = %p\n", regs);
+ _alert("x0: 0x%-16"PRIx64" x1: 0x%"PRIx64"\n",
+ regs->regs[REG_X0], regs->regs[REG_X1]);
+ _alert("x2: 0x%-16"PRIx64" x3: 0x%"PRIx64"\n",
+ regs->regs[REG_X2], regs->regs[REG_X3]);
+ _alert("x4: 0x%-16"PRIx64" x5: 0x%"PRIx64"\n",
+ regs->regs[REG_X4], regs->regs[REG_X5]);
+ _alert("x6: 0x%-16"PRIx64" x7: 0x%"PRIx64"\n",
+ regs->regs[REG_X6], regs->regs[REG_X7]);
+ _alert("x8: 0x%-16"PRIx64" x9: 0x%"PRIx64"\n",
+ regs->regs[REG_X8], regs->regs[REG_X9]);
+ _alert("x10: 0x%-16"PRIx64" x11: 0x%"PRIx64"\n",
+ regs->regs[REG_X10], regs->regs[REG_X11]);
+ _alert("x12: 0x%-16"PRIx64" x13: 0x%"PRIx64"\n",
+ regs->regs[REG_X12], regs->regs[REG_X13]);
+ _alert("x14: 0x%-16"PRIx64" x15: 0x%"PRIx64"\n",
+ regs->regs[REG_X14], regs->regs[REG_X15]);
+ _alert("x16: 0x%-16"PRIx64" x17: 0x%"PRIx64"\n",
+ regs->regs[REG_X16], regs->regs[REG_X17]);
+ _alert("x18: 0x%-16"PRIx64" x19: 0x%"PRIx64"\n",
+ regs->regs[REG_X18], regs->regs[REG_X19]);
+ _alert("x20: 0x%-16"PRIx64" x21: 0x%"PRIx64"\n",
+ regs->regs[REG_X20], regs->regs[REG_X21]);
+ _alert("x22: 0x%-16"PRIx64" x23: 0x%"PRIx64"\n",
+ regs->regs[REG_X22], regs->regs[REG_X23]);
+ _alert("x24: 0x%-16"PRIx64" x25: 0x%"PRIx64"\n",
+ regs->regs[REG_X24], regs->regs[REG_X25]);
+ _alert("x26: 0x%-16"PRIx64" x27: 0x%"PRIx64"\n",
+ regs->regs[REG_X26], regs->regs[REG_X27]);
+ _alert("x28: 0x%-16"PRIx64" x29: 0x%"PRIx64"\n",
+ regs->regs[REG_X28], regs->regs[REG_X29]);
+ _alert("x30: 0x%-16"PRIx64"\n", regs->regs[REG_X30]);
+
+ _alert("\n");
+ _alert("STATUS Registers:\n");
+ _alert("SPSR: 0x%-16"PRIx64"\n", regs->spsr);
+ _alert("ELR: 0x%-16"PRIx64"\n", regs->elr);
+ _alert("SP_EL0: 0x%-16"PRIx64"\n", regs->sp_el0);
+ _alert("SP_ELX: 0x%-16"PRIx64"\n", regs->sp_elx);
+ _alert("TPIDR_EL0: 0x%-16"PRIx64"\n", regs->tpidr_el0);
+ _alert("TPIDR_EL1: 0x%-16"PRIx64"\n", regs->tpidr_el1);
+ _alert("EXE_DEPTH: 0x%-16"PRIx64"\n", regs->exe_depth);
+}
+
+#ifdef CONFIG_ARCH_STACKDUMP
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_stackdump
+ ****************************************************************************/
+
+static void arm64_stackdump(uint64_t sp, uint64_t stack_top)
+{
+ uint64_t stack;
+
+ /* Flush any buffered SYSLOG data to avoid overwrite */
+
+ syslog_flush();
+
+ for (stack = sp & ~0x1f; stack < (stack_top & ~0x1f); stack += 64)
+ {
+ uint64_t *ptr = (uint64_t *)stack;
+ _alert("%08" PRIx64 ": %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 " %08" PRIx64 " %08" PRIx64 " %08" PRIx64
+ " %08" PRIx64 "\n",
+ stack, ptr[0], ptr[1], ptr[2], ptr[3],
+ ptr[4], ptr[5], ptr[6], ptr[7]);
+ }
+}
+
+/****************************************************************************
+ * Name: arm_dump_task
+ ****************************************************************************/
+
+static void arm64_dump_task(struct tcb_s *tcb, void *arg)
+{
+ char args[64] = "";
+#ifdef CONFIG_STACK_COLORATION
+ uint64_t stack_filled = 0;
+ uint64_t stack_used;
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ struct cpuload_s cpuload;
+ uint64_t fracpart;
+ uint64_t intpart;
+ uint64_t tmp;
+
+ clock_cpuload(tcb->pid, &cpuload);
+
+ if (cpuload.total > 0)
+ {
+ tmp = (1000 * cpuload.active) / cpuload.total;
+ intpart = tmp / 10;
+ fracpart = tmp - 10 * intpart;
+ }
+ else
+ {
+ intpart = 0;
+ fracpart = 0;
+ }
+#endif
+
+#ifdef CONFIG_STACK_COLORATION
+ stack_used = up_check_tcbstack(tcb);
+ if (tcb->adj_stack_size > 0 && stack_used > 0)
+ {
+ /* Use fixed-point math with one decimal place */
+
+ stack_filled = 10 * 100 * stack_used / tcb->adj_stack_size;
+ }
+#endif
+
+#ifndef CONFIG_DISABLE_PTHREAD
+ if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD)
+ {
+ struct pthread_tcb_s *ptcb = (struct pthread_tcb_s *)tcb;
+
+ snprintf(args, sizeof(args), "%p ", ptcb->arg);
+ }
+ else
+#endif
+ {
+ FAR char **argv = tcb->group->tg_info->argv + 1;
+ size_t npos = 0;
+
+ while (*argv != NULL && npos < sizeof(args))
+ {
+ npos += snprintf(args + npos, sizeof(args) - npos, " %s", *argv++);
+ }
+ }
+
+ /* Dump interesting properties of this task */
+
+ _alert(" %4d %4d"
+#ifdef CONFIG_SMP
+ " %4d"
+#endif
+#ifdef CONFIG_STACK_COLORATION
+ " %7lu"
+#endif
+ " %7lu"
+#ifdef CONFIG_STACK_COLORATION
+ " %3" PRId64 ".%1" PRId64 "%%%c"
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ " %3" PRId64 ".%01" PRId64 "%%"
+#endif
+#if CONFIG_TASK_NAME_SIZE > 0
+ " %s %s\n",
+#else
+ " %s\n",
+#endif
+ tcb->pid, tcb->sched_priority,
+#ifdef CONFIG_SMP
+ tcb->cpu,
+#endif
+#ifdef CONFIG_STACK_COLORATION
+ (unsigned long)up_check_tcbstack(tcb),
+#endif
+ (unsigned long)tcb->adj_stack_size
+#ifdef CONFIG_STACK_COLORATION
+ , stack_filled / 10, stack_filled % 10,
+ (stack_filled >= 10 * 80 ? '!' : ' ')
+#endif
+#ifdef CONFIG_SCHED_CPULOAD
+ , intpart, fracpart
+#endif
+#if CONFIG_TASK_NAME_SIZE > 0
Review Comment:
Yes. I understand that. I mean that at least part with task name printing
```
#ifdef CONFIG_SCHED_CPULOAD
, intpart, fracpart
#endif
#if CONFIG_TASK_NAME_SIZE > 0
, tcb->name
#else
, "<noname>"
#endif
, args
);
}
```
Maybe some other parts are missing similar
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1168372765
Fix some issue when develop with qemu, please checking again
@xiaoxiang781216 @hartmannathan @pkarashchenko
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r913316157
##########
arch/arm64/include/arch.h:
##########
@@ -0,0 +1,145 @@
+/****************************************************************************
+ * arch/arm64/include/arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_ARCH_H
+#define __ARCH_ARM64_INCLUDE_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <nuttx/pgalloc.h>
+# include <nuttx/addrenv.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+#if CONFIG_MM_PGSIZE != 4096
+# error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
+#endif
+
+#endif /* CONFIG_ARCH_ADDRENV */
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsp
+ ****************************************************************************/
+
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
Review Comment:
done
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r917705536
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
Review Comment:
Ok
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[GitHub] [incubator-nuttx] lupyuen commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
lupyuen commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1226612789
Hi @qinwei2004 thank you so much for implementing Arm64 support! I have written an article that's based on your work, I hope to run it on PinePhone soon :-)
["Apache NuttX RTOS on Arm Cortex-A53: How it might run on PinePhone"](https://lupyuen.github.io/articles/arm)
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r913315387
##########
arch/arm64/Kconfig:
##########
@@ -0,0 +1,76 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_ARM64
+comment "ARM64 Options"
+
+choice
+ prompt "ARM64 chip selection"
+ default ARCH_CHIP_QEMU
+
+config ARCH_CHIP_QEMU
+ bool "QEMU virt platform (cortex-a53)"
+ select ARCH_CORTEX_A53
+ select ARCH_HAVE_ADDRENV
+ select ARCH_NEED_ADDRENV_MAPPING
+ ---help---
+ QEMU virt platform (cortex-a53)
+
+endchoice
+
+config ARCH_ARMV8A
+ bool
+ default n
+
+config ARCH_ARMV8R
+ bool
+ default n
+
+config ARCH_CORTEX_A53
+ bool
+ default n
+ select ARCH_ARMV8A
+ select ARCH_DCACHE
+ select ARCH_ICACHE
+ select ARCH_HAVE_MMU
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_TESTSET
+
+config ARCH_CORTEX_R82
+ bool
+ default n
+ select ARCH_ARMV8R
+ select ARCH_DCACHE
+ select ARCH_ICACHE
+ select ARCH_HAVE_MPU
+ select ARCH_HAVE_TESTSET
+
+config ARCH_FAMILY
+ string
+ default "armv8-a" if ARCH_ARMV8A
+ default "armv8-r" if ARCH_ARMV8R
+
+config ARCH_CHIP
+ string
+ default "qemu" if ARCH_CHIP_QEMU
+
+config ARCH_HAVE_TRUSTZONE
+ bool
+ default n
+ ---help---
+ Automatically selected to indicate that the ARM CPU supports
+ TrustZone.
+
+config ARM_HAVE_NEON
Review Comment:
done
##########
arch/arm64/Kconfig:
##########
@@ -0,0 +1,76 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_ARM64
+comment "ARM64 Options"
+
+choice
+ prompt "ARM64 chip selection"
+ default ARCH_CHIP_QEMU
+
+config ARCH_CHIP_QEMU
+ bool "QEMU virt platform (cortex-a53)"
+ select ARCH_CORTEX_A53
+ select ARCH_HAVE_ADDRENV
+ select ARCH_NEED_ADDRENV_MAPPING
+ ---help---
+ QEMU virt platform (cortex-a53)
+
+endchoice
+
+config ARCH_ARMV8A
+ bool
+ default n
+
+config ARCH_ARMV8R
+ bool
+ default n
+
+config ARCH_CORTEX_A53
+ bool
+ default n
+ select ARCH_ARMV8A
+ select ARCH_DCACHE
+ select ARCH_ICACHE
+ select ARCH_HAVE_MMU
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_TESTSET
+
+config ARCH_CORTEX_R82
+ bool
+ default n
+ select ARCH_ARMV8R
+ select ARCH_DCACHE
+ select ARCH_ICACHE
+ select ARCH_HAVE_MPU
+ select ARCH_HAVE_TESTSET
+
+config ARCH_FAMILY
+ string
+ default "armv8-a" if ARCH_ARMV8A
+ default "armv8-r" if ARCH_ARMV8R
+
+config ARCH_CHIP
+ string
+ default "qemu" if ARCH_CHIP_QEMU
+
+config ARCH_HAVE_TRUSTZONE
Review Comment:
done
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916018027
##########
arch/arm64/src/Toolchain.defs:
##########
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm64/src/Toolchain.defs
Review Comment:
what about Just keep this for now? i don't see any good or bad reason to make this change
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r917212831
##########
arch/arm64/src/common/arm64_initialstate.c:
##########
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialstate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tcb)
+{
+ char * stack_ptr = tcb->stack_base_ptr + tcb->adj_stack_size;
+ struct regs_context * pinitctx;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * pfpuctx;
+ pfpuctx = STACK_PTR_TO_FRAME(struct fpu_reg, stack_ptr);
+ tcb->xcp.fpu_regs = pfpuctx;
+
+ /* set fpu context */
+
+ arm64_init_fpu(tcb);
+ stack_ptr = (char *)pfpuctx;
+#endif
+
+ pinitctx = STACK_PTR_TO_FRAME(struct regs_context, stack_ptr);
+ memset(pinitctx, 0, sizeof(struct regs_context));
+ pinitctx->elr = (uint64_t)tcb->start;
+
+ /* Keep using SP_EL1 */
+
+ pinitctx->spsr = SPSR_MODE_EL1H;
+
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ pinitctx->spsr |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT);
+#endif /* CONFIG_SUPPRESS_INTERRUPTS */
+
+ pinitctx->sp_elx = (uint64_t)pinitctx;
+ pinitctx->sp_el0 = (uint64_t)pinitctx;
+ pinitctx->exe_depth = 0;
+ pinitctx->tpidr_el0 = (uint64_t)tcb;
+ pinitctx->tpidr_el1 = (uint64_t)tcb;
+
+ tcb->xcp.regs = (uint64_t *)pinitctx;
+}
+
+/****************************************************************************
+ * Name: up_initial_state
+ *
+ * Description:
+ * A new thread is being started and a new TCB has been created. This
+ * function is called to initialize the processor specific portions of
+ * the new TCB.
+ *
+ * This function must setup the initial architecture registers and/or
+ * stack so that execution will begin at tcb->start on the next context
+ * switch.
+ *
+ ****************************************************************************/
+
+void up_initial_state(struct tcb_s *tcb)
+{
+ struct xcptcontext *xcp = &tcb->xcp;
+
+ memset(xcp, 0, sizeof(struct xcptcontext));
+
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ /* Initialize the idle thread stack */
+#ifdef CONFIG_SMP
+ tcb->stack_alloc_ptr = (void *)(g_cpu_idlestackalloc[0]);
Review Comment:
fix it
the second idle thread can be init with normal routine
thanks
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915952512
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
Review Comment:
these macros is used at arch/arm64/src/common/arm64_smccc.S
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r911603135
##########
arch/arm64/Kconfig:
##########
@@ -0,0 +1,76 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_ARM64
+comment "ARM64 Options"
+
+choice
+ prompt "ARM64 chip selection"
+ default ARCH_CHIP_QEMU
+
+config ARCH_CHIP_QEMU
+ bool "QEMU virt platform (cortex-a53)"
+ select ARCH_CORTEX_A53
+ select ARCH_HAVE_ADDRENV
+ select ARCH_NEED_ADDRENV_MAPPING
+ ---help---
+ QEMU virt platform (cortex-a53)
+
+endchoice
+
+config ARCH_ARMV8A
+ bool
+ default n
+
+config ARCH_ARMV8R
+ bool
+ default n
+
+config ARCH_CORTEX_A53
+ bool
+ default n
+ select ARCH_ARMV8A
+ select ARCH_DCACHE
+ select ARCH_ICACHE
+ select ARCH_HAVE_MMU
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_TESTSET
+
+config ARCH_CORTEX_R82
+ bool
+ default n
+ select ARCH_ARMV8R
+ select ARCH_DCACHE
+ select ARCH_ICACHE
+ select ARCH_HAVE_MPU
+ select ARCH_HAVE_TESTSET
+
+config ARCH_FAMILY
+ string
+ default "armv8-a" if ARCH_ARMV8A
+ default "armv8-r" if ARCH_ARMV8R
+
+config ARCH_CHIP
+ string
+ default "qemu" if ARCH_CHIP_QEMU
+
+config ARCH_HAVE_TRUSTZONE
+ bool
+ default n
+ ---help---
+ Automatically selected to indicate that the ARM CPU supports
+ TrustZone.
+
+config ARM_HAVE_NEON
Review Comment:
should we select NEON in ARCH_CHIP_QEMU or even ARCH_CORTEX_A53/ARCH_ARMV8A
##########
arch/arm64/Kconfig:
##########
@@ -0,0 +1,76 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_ARM64
+comment "ARM64 Options"
+
+choice
+ prompt "ARM64 chip selection"
+ default ARCH_CHIP_QEMU
+
+config ARCH_CHIP_QEMU
+ bool "QEMU virt platform (cortex-a53)"
+ select ARCH_CORTEX_A53
+ select ARCH_HAVE_ADDRENV
+ select ARCH_NEED_ADDRENV_MAPPING
+ ---help---
+ QEMU virt platform (cortex-a53)
+
+endchoice
+
+config ARCH_ARMV8A
+ bool
+ default n
+
+config ARCH_ARMV8R
+ bool
+ default n
+
+config ARCH_CORTEX_A53
+ bool
+ default n
+ select ARCH_ARMV8A
+ select ARCH_DCACHE
+ select ARCH_ICACHE
+ select ARCH_HAVE_MMU
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_TESTSET
+
+config ARCH_CORTEX_R82
+ bool
+ default n
+ select ARCH_ARMV8R
+ select ARCH_DCACHE
+ select ARCH_ICACHE
+ select ARCH_HAVE_MPU
+ select ARCH_HAVE_TESTSET
+
+config ARCH_FAMILY
+ string
+ default "armv8-a" if ARCH_ARMV8A
+ default "armv8-r" if ARCH_ARMV8R
+
+config ARCH_CHIP
+ string
+ default "qemu" if ARCH_CHIP_QEMU
+
+config ARCH_HAVE_TRUSTZONE
Review Comment:
should we select ARCH_HAVE_TRUSTZONE in ARCH_CORTEX_A53
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
Review Comment:
remove, let's access general register through REG_X0
##########
arch/arm64/include/types.h:
##########
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm64/include/types.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_TYPES_H
+#define __ARCH_ARM64_INCLUDE_TYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types. NOTE that these type
+ * names have a leading underscore character. This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character. This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char _int8_t;
+typedef unsigned char _uint8_t;
+
+typedef signed short _int16_t;
+typedef unsigned short _uint16_t;
+
+typedef signed int _int32_t;
+typedef unsigned int _uint32_t;
+
+typedef signed long _int64_t;
+typedef unsigned long _uint64_t;
+#define __INT64_DEFINED
+
+typedef _int64_t _intmax_t;
+typedef _uint64_t _uintmax_t;
+
+#if defined(__WCHAR_TYPE__)
+typedef __WCHAR_TYPE__ _wchar_t;
+#else
+typedef int _wchar_t;
+#endif
+
+#if defined(__SIZE_TYPE__)
+/* If __SIZE_TYPE__ is defined we define ssize_t based on size_t.
+ * We simply change "unsigned" to "signed" for this single definition
+ * to make sure ssize_t and size_t only differ by their signedness.
+ */
+
+#define unsigned signed
+typedef __SIZE_TYPE__ _ssize_t;
+#undef unsigned
+typedef __SIZE_TYPE__ _size_t;
+
+#elif defined(CONFIG_ARCH_SIZET_LONG)
+
+typedef signed long _ssize_t;
+typedef unsigned long _size_t;
+
+#else
+
+typedef signed int _ssize_t;
+typedef unsigned int _size_t;
Review Comment:
int-> long long?
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
Review Comment:
```suggestion
static inline long smh_call(unsigned int nbr, void *parm)
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
Review Comment:
remove #include <arch/arch.h>
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
Review Comment:
move before line 32
##########
arch/arm64/include/arch.h:
##########
@@ -0,0 +1,145 @@
+/****************************************************************************
+ * arch/arm64/include/arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_ARCH_H
+#define __ARCH_ARM64_INCLUDE_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <nuttx/pgalloc.h>
+# include <nuttx/addrenv.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+#if CONFIG_MM_PGSIZE != 4096
+# error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
+#endif
+
+#endif /* CONFIG_ARCH_ADDRENV */
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsp
+ ****************************************************************************/
+
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
Review Comment:
move to irq.h like patch: https://github.com/apache/incubator-nuttx/pull/6550
##########
arch/arm64/include/inttypes.h:
##########
@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/arm64/include/inttypes.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_INTTYPES_H
+#define __ARCH_ARM64_INCLUDE_INTTYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PRId8 "d"
+#define PRId16 "d"
+#define PRId32 "d"
+#define PRId64 "ld"
+
+#define PRIdPTR "ld"
+
+#define PRIi8 "i"
+#define PRIi16 "i"
+#define PRIi32 "i"
+#define PRIi64 "li"
+
+#define PRIiPTR "li"
+
+#define PRIo8 "o"
+#define PRIo16 "o"
+#define PRIo32 "o"
+#define PRIo64 "lo"
+
+#define PRIoPTR "lo"
+
+#define PRIu8 "u"
+#define PRIu16 "u"
+#define PRIu32 "u"
+#define PRIu64 "lu"
+
+#define PRIuPTR "lu"
+
+#define PRIx8 "x"
+#define PRIx16 "x"
+#define PRIx32 "x"
+#define PRIx64 "lx"
+
+#define PRIxPTR "lx"
+
+#define PRIX8 "X"
+#define PRIX16 "X"
+#define PRIX32 "X"
+#define PRIX64 "lX"
+
+#define PRIXPTR "lX"
+
+#define SCNd8 "hhd"
+#define SCNd16 "hd"
+#define SCNd32 "d"
+#define SCNd64 "ld"
+
+#define SCNdPTR "ld"
+
+#define SCNi8 "hhi"
+#define SCNi16 "hi"
+#define SCNi32 "i"
+#define SCNi64 "li"
+
+#define SCNiPTR "li"
+
+#define SCNo8 "hho"
+#define SCNo16 "ho"
+#define SCNo32 "o"
+#define SCNo64 "lo"
+
+#define SCNoPTR "lo"
+
+#define SCNu8 "hhu"
+#define SCNu16 "hu"
+#define SCNu32 "u"
+#define SCNu64 "lu"
+
+#define SCNuPTR "u"
Review Comment:
```suggestion
#define SCNuPTR "lu"
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
Review Comment:
let's continue number FPSR and FPCR after FPU_REG_Q31
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
Review Comment:
add blank line after the comment.
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
Review Comment:
```suggestion
uint64_t *regs;
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
Review Comment:
remove, let' access through `regs`
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
Review Comment:
it's better number Q1 to 2, please reference how REG_Dx define on arm arch.
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
Review Comment:
```suggestion
uint64_t *saved_regs;
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
Review Comment:
regs[REG_R15]->ELR?
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
Review Comment:
```suggestion
#define XCPTCONTEXT_FPU_REGS (66)
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
Review Comment:
remove, let' access the fpu register through FPU_REG_Q1
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
Review Comment:
```suggestion
#define XCPTCONTEXT_FPU_SIZE (8 * ARM64_FPU_REGS)
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
Review Comment:
where you define `struct xcpt_syscall_s`?
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
Review Comment:
why not make FPU_REG_Q0 stat from XCPTCONTEXT_GP_REGS? and remove:
```
#ifdef CONFIG_ARCH_FPU
struct fpu_reg * fpu_regs;
struct fpu_reg * sig_save_fpu_regs;
#endif
```
##########
arch/arm64/include/limits.h:
##########
@@ -0,0 +1,84 @@
+/****************************************************************************
+ * arch/arm64/include/limits.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H
+#define __ARCH_ARM64_INCLUDE_LIMITS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <limits.h>
Review Comment:
remove all above header files inclusion
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+#ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+#endif
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* In this configuration, all syscalls execute from an internal kernel
+ * stack. Why? Because when we instantiate and initialize the address
+ * environment of the new user process, we will temporarily lose the
+ * address environment of the old user process, including its stack
+ * contents. The kernel C logic will crash immediately with no valid
+ * stack in place.
+ */
+
+ uint64_t *ustkptr; /* Saved user stack pointer */
+ uint64_t *kstack; /* Allocate base of the (aligned) kernel stack */
+ uint64_t *kstkptr; /* Saved kernel stack pointer */
+#endif
Review Comment:
```suggestion
# endif
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+#ifdef CONFIG_ARCH_STACK_DYNAMIC
Review Comment:
```suggestion
# ifdef CONFIG_ARCH_STACK_DYNAMIC
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+#ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+#endif
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
Review Comment:
```suggestion
# ifdef CONFIG_ARCH_KERNEL_STACK
```
##########
arch/arm64/include/types.h:
##########
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm64/include/types.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_TYPES_H
+#define __ARCH_ARM64_INCLUDE_TYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types. NOTE that these type
+ * names have a leading underscore character. This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character. This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char _int8_t;
+typedef unsigned char _uint8_t;
+
+typedef signed short _int16_t;
+typedef unsigned short _uint16_t;
+
+typedef signed int _int32_t;
+typedef unsigned int _uint32_t;
+
+typedef signed long _int64_t;
+typedef unsigned long _uint64_t;
+#define __INT64_DEFINED
+
+typedef _int64_t _intmax_t;
+typedef _uint64_t _uintmax_t;
+
+#if defined(__WCHAR_TYPE__)
+typedef __WCHAR_TYPE__ _wchar_t;
+#else
+typedef int _wchar_t;
+#endif
+
+#if defined(__SIZE_TYPE__)
+/* If __SIZE_TYPE__ is defined we define ssize_t based on size_t.
+ * We simply change "unsigned" to "signed" for this single definition
+ * to make sure ssize_t and size_t only differ by their signedness.
+ */
+
+#define unsigned signed
+typedef __SIZE_TYPE__ _ssize_t;
+#undef unsigned
+typedef __SIZE_TYPE__ _size_t;
+
+#elif defined(CONFIG_ARCH_SIZET_LONG)
+
+typedef signed long _ssize_t;
+typedef unsigned long _size_t;
+
+#else
+
+typedef signed int _ssize_t;
+typedef unsigned int _size_t;
+
+#endif
+
+/* This is the size of the interrupt state save returned by
+ * up_irq_save()
+ */
+
+typedef unsigned int irqstate_t;
Review Comment:
should we use long here?
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+#ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+#endif
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* In this configuration, all syscalls execute from an internal kernel
+ * stack. Why? Because when we instantiate and initialize the address
+ * environment of the new user process, we will temporarily lose the
+ * address environment of the old user process, including its stack
+ * contents. The kernel C logic will crash immediately with no valid
+ * stack in place.
+ */
+
+ uint64_t *ustkptr; /* Saved user stack pointer */
+ uint64_t *kstack; /* Allocate base of the (aligned) kernel stack */
+ uint64_t *kstkptr; /* Saved kernel stack pointer */
+#endif
+#endif
+};
+
+/* Name: up_irq_save, up_irq_restore, and friends.
+ *
+ * NOTE: This function should never be called from application code and,
+ * as a general rule unless you really know what you are doing, this
+ * function should not be called directly from operation system code either:
+ * Typically, the wrapper functions, enter_critical_section() and
+ * leave_critical section(), are probably what you really want.
+ */
+
+/* Return the current IRQ state */
+
+static inline irqstate_t irqstate(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__("mrs %0, daif" : "=r" (flags):: "memory");
+
+ return flags;
+}
+
+/* Disable IRQs and return the previous IRQ state */
+
+static inline irqstate_t up_irq_save(void)
+{
+ irqstate_t flags;
+ __asm__ __volatile__
+ (
+ "mrs %0, daif \n"
Review Comment:
```suggestion
"mrs %0, daif\n"
```
##########
arch/arm64/include/limits.h:
##########
@@ -0,0 +1,84 @@
+/****************************************************************************
+ * arch/arm64/include/limits.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H
+#define __ARCH_ARM64_INCLUDE_LIMITS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <limits.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT 8
+#define SCHAR_MIN (-SCHAR_MAX - 1)
+#define SCHAR_MAX 127
+#define UCHAR_MAX 255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
+#define CHAR_MIN 0
+#define CHAR_MAX UCHAR_MAX
+#else
+#define CHAR_MIN SCHAR_MIN
+#define CHAR_MAX SCHAR_MAX
+#endif
+
+#define SHRT_MIN (-SHRT_MAX - 1)
+#define SHRT_MAX 32767
+#define USHRT_MAX 65535U
+
+#define INT_MIN (-INT_MAX - 1)
+#define INT_MAX 2147483647
+#define UINT_MAX 4294967295U
+
+/* For 64-bit arm64 with Linux ABI, long is identical to long long */
+
+#define LONG_MIN LLONG_MIN
+#define LONG_MAX LLONG_MAX
+#define ULONG_MAX ULLONG_MAX
+
+#define LLONG_MIN (-LLONG_MAX - 1)
+#define LLONG_MAX 9223372036854775807ll
Review Comment:
```suggestion
#define LLONG_MAX 9223372036854775807LL
```
##########
arch/arm64/include/limits.h:
##########
@@ -0,0 +1,84 @@
+/****************************************************************************
+ * arch/arm64/include/limits.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H
+#define __ARCH_ARM64_INCLUDE_LIMITS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <limits.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT 8
+#define SCHAR_MIN (-SCHAR_MAX - 1)
+#define SCHAR_MAX 127
+#define UCHAR_MAX 255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
+#define CHAR_MIN 0
+#define CHAR_MAX UCHAR_MAX
+#else
+#define CHAR_MIN SCHAR_MIN
+#define CHAR_MAX SCHAR_MAX
+#endif
+
+#define SHRT_MIN (-SHRT_MAX - 1)
+#define SHRT_MAX 32767
+#define USHRT_MAX 65535U
+
+#define INT_MIN (-INT_MAX - 1)
+#define INT_MAX 2147483647
+#define UINT_MAX 4294967295U
+
+/* For 64-bit arm64 with Linux ABI, long is identical to long long */
Review Comment:
Linux ABI->LP64
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
Review Comment:
```suggestion
#define SYS_smhcall 0xf000
```
Please reference:
https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst#the-semihosting-interface
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+#ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+#endif
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+ /* In this configuration, all syscalls execute from an internal kernel
+ * stack. Why? Because when we instantiate and initialize the address
+ * environment of the new user process, we will temporarily lose the
+ * address environment of the old user process, including its stack
+ * contents. The kernel C logic will crash immediately with no valid
+ * stack in place.
+ */
+
+ uint64_t *ustkptr; /* Saved user stack pointer */
+ uint64_t *kstack; /* Allocate base of the (aligned) kernel stack */
+ uint64_t *kstkptr; /* Saved kernel stack pointer */
+#endif
+#endif
+};
+
+/* Name: up_irq_save, up_irq_restore, and friends.
+ *
+ * NOTE: This function should never be called from application code and,
+ * as a general rule unless you really know what you are doing, this
+ * function should not be called directly from operation system code either:
+ * Typically, the wrapper functions, enter_critical_section() and
+ * leave_critical section(), are probably what you really want.
+ */
+
+/* Return the current IRQ state */
+
+static inline irqstate_t irqstate(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__("mrs %0, daif" : "=r" (flags):: "memory");
+
+ return flags;
+}
+
+/* Disable IRQs and return the previous IRQ state */
+
+static inline irqstate_t up_irq_save(void)
+{
+ irqstate_t flags;
+ __asm__ __volatile__
+ (
+ "mrs %0, daif \n"
+ "msr daifset, #2\n"
+ : "=r" (flags)
+ :
+ : "memory"
+ );
+
+ return flags;
+}
+
+/* Enable IRQs and return the previous IRQ state */
+
+static inline irqstate_t up_irq_enable(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__
+ (
+ "mrs %0, daif \n"
Review Comment:
```suggestion
"mrs %0, daif\n"
```
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
Review Comment:
```suggestion
* void arm64_switchcontext(void **saveregs, void *restoreregs);
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,435 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * ARM64_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + ARM64_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t * regs;
+
+ /* task context, for signal process */
+
+ uint64_t * sig_save_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * fpu_regs;
+ struct fpu_reg * sig_save_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_R15];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+#ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+#endif
Review Comment:
```suggestion
# endif
```
##########
arch/arm64/include/limits.h:
##########
@@ -0,0 +1,84 @@
+/****************************************************************************
+ * arch/arm64/include/limits.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H
+#define __ARCH_ARM64_INCLUDE_LIMITS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <limits.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT 8
+#define SCHAR_MIN (-SCHAR_MAX - 1)
+#define SCHAR_MAX 127
+#define UCHAR_MAX 255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
+#define CHAR_MIN 0
+#define CHAR_MAX UCHAR_MAX
+#else
+#define CHAR_MIN SCHAR_MIN
+#define CHAR_MAX SCHAR_MAX
+#endif
+
+#define SHRT_MIN (-SHRT_MAX - 1)
+#define SHRT_MAX 32767
+#define USHRT_MAX 65535U
+
+#define INT_MIN (-INT_MAX - 1)
+#define INT_MAX 2147483647
+#define UINT_MAX 4294967295U
+
+/* For 64-bit arm64 with Linux ABI, long is identical to long long */
+
+#define LONG_MIN LLONG_MIN
+#define LONG_MAX LLONG_MAX
+#define ULONG_MAX ULLONG_MAX
+
+#define LLONG_MIN (-LLONG_MAX - 1)
+#define LLONG_MAX 9223372036854775807ll
+#define ULLONG_MAX 18446744073709551615ull
Review Comment:
```suggestion
#define ULLONG_MAX 18446744073709551615ULL
```
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
Review Comment:
remove all macros which isn't really used
##########
arch/arm64/include/qemu/chip.h:
##########
@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/arm64/include/qemu/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
+#define __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_QEMU_A53)
+
+#define CONFIG_GICD_BASE 0x8000000
+#define CONFIG_GICR_BASE 0x80a0000
+
+#define CONFIG_RAMBANK1_ADDR 0x40000000
+#define CONFIG_RAMBANK1_SIZE MB(128)
Review Comment:
where MB define?
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
Review Comment:
move ` "r"(reg3), ` to the next line
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm);
+
+ __asm__ __volatile__
+ (
+ "hlt %1"
+ : "=r"(reg0)
+ : "i"(SYS_smhcall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* Result from SMC/HVC call
+ * a0-a7 result values from registers 0 to 7
+ */
+
+struct arm64_smccc_res
Review Comment:
move to public type section
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm);
+
+ __asm__ __volatile__
+ (
+ "hlt %1"
+ : "=r"(reg0)
+ : "i"(SYS_smhcall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* Result from SMC/HVC call
+ * a0-a7 result values from registers 0 to 7
+ */
+
+struct arm64_smccc_res
+{
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+};
+
+typedef struct arm64_smccc_res arm64_smccc_res_t;
+
+enum arm64_smccc_conduit
Review Comment:
should we move to arm64_cpu_psci.h/c
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r920723985
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,619 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
Review Comment:
i perfer to keep, it's not a bit operation actually and a little weird to change to BIT defined
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1159613577
@xiaoxiang781216 , please review
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902414586
##########
arch/arm64/src/common/arm64_backtrace.c:
##########
@@ -0,0 +1,184 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+
+#include "sched/sched.h"
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_FRAME_POINTER)
+
+/****************************************************************************
+ * Name: backtrace
+ *
+ * Description:
+ * backtrace() parsing the return address through frame pointer
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int backtrace(uintptr_t *base, uintptr_t *limit,
+ uintptr_t *fp, uintptr_t *pc,
+ void **buffer, int size, int *skip)
+{
+ int i = 0;
+
+ if (pc)
+ {
+ i++;
+ if (*skip-- <= 0)
+ {
+ *buffer++ = pc;
+ }
+ }
+
+ for (; i < size; fp = (uintptr_t *)*(fp - 1), i++)
+ {
+ if (fp > limit || fp < base || *fp == 0)
+ {
+ break;
+ }
+
+ if (*skip-- <= 0)
+ {
+ *buffer++ = (void *)*fp;
+ }
+ }
+
+ return i;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_backtrace
+ *
+ * Description:
+ * up_backtrace() returns a backtrace for the TCB, in the array
+ * pointed to by buffer. A backtrace is the series of currently active
+ * function calls for the program. Each item in the array pointed to by
+ * buffer is of type void *, and is the return address from the
+ * corresponding stack frame. The size argument specifies the maximum
+ * number of addresses that can be stored in buffer. If the backtrace is
+ * larger than size, then the addresses corresponding to the size most
+ * recent function calls are returned; to obtain the complete backtrace,
+ * make sure that buffer and size are large enough.
+ *
+ * Input Parameters:
+ * tcb - Address of the task's TCB
+ * buffer - Return address from the corresponding stack frame
+ * size - Maximum number of addresses that can be stored in buffer
+ * skip - number of addresses to be skipped
+ *
+ * Returned Value:
+ * up_backtrace() returns the number of addresses returned in buffer
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+int up_backtrace(struct tcb_s *tcb,
+ void **buffer, int size, int skip)
+{
+ struct tcb_s *rtcb = (struct tcb_s *)arch_get_current_tcb();
+ struct regs_context * p_regs;
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
+ void *istacklimit;
+#endif
+ irqstate_t flags;
+ int ret;
+
+ if (size <= 0 || !buffer)
+ {
+ return 0;
+ }
+
+ if (tcb == NULL || tcb == rtcb)
+ {
+ if (up_interrupt_context())
+ {
+#if CONFIG_ARCH_INTERRUPTSTACK > 7
+# ifdef CONFIG_SMP
+ istacklimit = (void *)arm64_intstack_top();
+# else
+ istacklimit = g_interrupt_stack + INTSTACK_SIZE;
+# endif /* CONFIG_SMP */
+ ret = backtrace(istacklimit - (CONFIG_ARCH_INTERRUPTSTACK & ~15),
+ istacklimit,
+ (void *)__builtin_frame_address(0),
+ NULL, buffer, size, &skip);
+#else
+ ret = backtrace(rtcb->stack_base_ptr,
+ rtcb->stack_base_ptr + rtcb->adj_stack_size,
+ (void *)__builtin_frame_address(0),
+ NULL, buffer, size, &skip);
+#endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */
+ if (ret < size)
+ {
+ p_regs = (struct regs_context *)CURRENT_REGS;
+ ret += backtrace(rtcb->stack_base_ptr,
+ rtcb->stack_base_ptr + rtcb->adj_stack_size,
+ (void *)p_regs->regs[REG_X29],
+ (void *)p_regs->elr,
+ &buffer[ret], size - ret, &skip);
+ }
+ }
+ else
+ {
+ ret = backtrace(rtcb->stack_base_ptr,
+ rtcb->stack_base_ptr + rtcb->adj_stack_size,
+ (void *)__builtin_frame_address(0),
+ NULL, buffer, size, &skip);
+ }
+ }
+ else
+ {
+ flags = enter_critical_section();
+ p_regs = (struct regs_context *)CURRENT_REGS;
+
+ ret = backtrace(tcb->stack_base_ptr,
+ tcb->stack_base_ptr + tcb->adj_stack_size,
+ (void *)p_regs->regs[REG_X29],
+ (void *)p_regs->elr,
+ buffer, size, &skip);
+
+ leave_critical_section(flags);
+ }
+
+ return ret;
+}
+#endif /* CONFIG_FRAME_POINTER && !CONFIG_ARM_THUMB */
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/src/common/arm64_cache.c:
##########
@@ -0,0 +1,449 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cache.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_mmu.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* Common operations for the caches
+ *
+ * WB means write-back and intends to transfer dirty cache lines to memory in
+ * a copy-back cache policy. May be a no-op in write-back cache policy.
+ *
+ * INVD means invalidate and will mark cache lines as not valid. A future
+ * access to the associated address is guaranteed to generate a memory fetch.
+ *
+ * armv8 data cahce instruction:
+ *
+ * DC CIVAC (WB+INVD):
+ * Data or unified Cache line Clean and Invalidate by VA to PoC
+ * Clean and Invalidate data cache by address to Point of Coherency.
+ *
+ * DC CVAC (WB):
+ * Data or unified Cache line Clean by VA to PoC
+ * Clean data cache by address to Point of Coherency.
+ *
+ * DC IVAC (INVD):
+ * Data or unified Cache line Invalidate by VA to PoC
+ * Invalidate data cache by address to Point of Coherency
+ */
+
+#define CACHE_OP_WB BIT(0)
+#define CACHE_OP_INVD BIT(1)
+#define CACHE_OP_WB_INVD (CACHE_OP_WB | CACHE_OP_INVD)
+
+#define LINE_MASK(line) (line - 1)
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902415007
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <arch/syscall.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+#define PSCI_RET_INVALID_ADDRESS -9
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+uint32_t psci_version(void);
+
+typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long,
+ unsigned long);
+
+struct psci_interface
+{
+ enum arm64_smccc_conduit conduit;
+ psci_fn *invoke_psci_fn;
+ uint32_t version;
+};
+
+int pcsi_cpu_off(void);
+int pcsi_cpu_on(unsigned long cpuid, uintptr_t entry_point);
+
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__ */
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <arch/syscall.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+#define PSCI_RET_INVALID_ADDRESS -9
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+uint32_t psci_version(void);
+
+typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long,
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902417992
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
+#define GIC_DIST_IGROUPR 0x0080
+#define GIC_DIST_ISENABLER 0x0100
+#define GIC_DIST_ICENABLER 0x0180
+#define GIC_DIST_ISPENDR 0x0200
+#define GIC_DIST_ICPENDR 0x0280
+#define GIC_DIST_ISACTIVER 0x0300
+#define GIC_DIST_ICACTIVER 0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR 0x0800
+#define GIC_DIST_ICFGR 0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR 0x0f00
+
+/* GICD GICR common access macros */
+
+#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD_PIDR2 : Peripheral ID2 Register
+ * bit assignments
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+#define GICD_PIDR2_ARCH_MASK 0xf0
+#define GICD_PIDR2_ARCH_GICV3 0x30
+#define GICD_PIDR2_ARCH_GICV4 0x40
+
+/* GICD_TYPER : Interrupt Controller Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+#define GICD_TYPER_RSS (1U << 26)
+#define GICD_TYPER_LPIS (1U << 17)
+#define GICD_TYPER_MBIS (1U << 16)
+#define GICD_TYPER_ESPI (1U << 8)
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
+#define GICD_TYPER_ESPIS(typer) \
+ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
+
+/* Common Helper Constants */
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
+ ((intid) < GIC_PPI_INT_BASE))
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_NUM_INTR_PER_REG 32
+#define GIC_NUM_CFG_PER_REG 16
+#define GIC_NUM_PRI_PER_REG 4
+
+/* GIC idle priority : value '0xff' will allow all interrupts */
+
+#define GIC_IDLE_PRIO 0xff
+
+/* Priority levels 0:255 */
+
+#define GIC_PRI_MASK 0xff
+
+/* '0xa0'is used to initialize each interrtupt default priority.
+ * This is an arbitrary value in current context.
+ * Any value '0x80' to '0xff' will work for both NS and S state.
+ * The values of individual interrupt and default has to be chosen
+ * carefully if PMR and BPR based nesting and preemption has to be done.
+ */
+
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
+
+/* Register bit definitions */
+
+/* GICD_CTLR Interrupt group definitions */
+#define GICD_CTLR_ENABLE_G0 0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S 2
+#define GICD_CTRL_ARE_S 4
+#define GICD_CTRL_ARE_NS 5
+#define GICD_CTRL_NS 6
+#define GICD_CGRL_E1NWF 7
+
+/* GICD_CTLR Register write progress bit */
+#define GICD_CTLR_RWP 31
+
+/* GICR_CTLR */
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP 3
+
+/* GICD_TYPER.ITLinesNumber 0:4 */
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICR： Re-Distributor registers, offsets from RD_base(n) */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00A0
+#define GICR_INVALLR 0x00B0
+#define GICR_SYNCR 0x00C0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+#define GICR_IDREGS 0xFFD0
+#define GICR_PIDR2 0xFFE8
+
+/* GICR_PIDR2 : Peripheral ID2 Register
+ * bit assignments are the same as those for GICD_PIDR2)
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+
+#define GICR_PIDR2_ARCH_MASK 0xf0
+#define GICR_PIDR2_ARCH_GICV3 0x30
+#define GICR_PIDR2_ARCH_GICV4 0x40
+
+/* GICR_TYPER : Redistributor Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ * chapter 9.11.35 for detail descriptions
+ */
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_DIRECTLPIS (1U << 3)
+#define GICR_TYPER_LAST (1U << 4)
+
+/* GICR_WAKER */
+#define GICR_WAKER_PS 1
+#define GICR_WAKER_CA 2
+
+/* SGI base is at 64K offset from Redistributor */
+#define GICR_SGI_BASE_OFF 0x10000
+
+/* GICD_ICFGR */
+#define GICD_ICFGR_MASK BIT_MASK(2)
+#define GICD_ICFGR_TYPE BIT(1)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_SPI_MAX_INTID 1019
+#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \
+ ((intid) <= GIC_SPI_MAX_INTID))
+
+/* GITCD_IROUTER */
+#define GIC_DIST_IROUTER 0x6000
+#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define IRQ_DEFAULT_PRIORITY 0xa0
+
+#define GIC_IRQ_SGI0 0
+#define GIC_IRQ_SGI1 1
+#define GIC_IRQ_SGI2 2
+#define GIC_IRQ_SGI3 3
+#define GIC_IRQ_SGI4 4
+#define GIC_IRQ_SGI5 5
+#define GIC_IRQ_SGI6 6
+#define GIC_IRQ_SGI7 7
+#define GIC_IRQ_SGI8 8
+#define GIC_IRQ_SGI9 9
+#define GIC_IRQ_SGI10 10
+#define GIC_IRQ_SGI11 11
+#define GIC_IRQ_SGI12 12
+#define GIC_IRQ_SGI13 13
+#define GIC_IRQ_SGI14 14
+#define GIC_IRQ_SGI15 15
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+bool arm64_gic_irq_is_enabled(unsigned int intid);
+int arm64_gic_initialize(void);
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags);
+
+/****************************************************************************
+ * Name: arm64_decodeirq
+ *
+ * Description:
+ * This function is called from the IRQ vector handler in arm_vectors.S.
+ * At this point, the interrupt has been taken and the registers have
+ * been saved on the stack. This function simply needs to determine the
+ * the irq number of the interrupt and then to call arm_doirq to dispatch
+ * the interrupt.
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area on the stack.
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_decodeirq(uint64_t * regs);
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list);
+
+#ifdef CONFIG_SMP
+
+#define SGI_CPU_PAUSE GIC_IRQ_SGI0
+
+/****************************************************************************
+ * Name: arm64_pause_handler
+ *
+ * Description:
+ * This is the handler for SGI2. It performs the following operations:
+ *
+ * 1. It saves the current task state at the head of the current assigned
+ * task list.
+ * 2. It waits on a spinlock, then
+ * 3. Returns from interrupt, restoring the state of the new task at the
+ * head of the ready to run list.
+ *
+ * Input Parameters:
+ * Standard interrupt handling
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int arm64_pause_handler(int irq, void *context, void *arg);
+
+void arm64_gic_secondary_init(void);
+
+int arm64_smp_sgi_init(void);
+
+#endif
+
+#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__ */
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r919707297
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,404 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <sys/types.h>
+#ifndef __ASSEMBLY__
+# include <stdbool.h>
+#endif
+
+#include <nuttx/config.h>
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define XCPTCONTEXT_FPU_REGS (66)
+#else
+#define XCPTCONTEXT_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * XCPTCONTEXT_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + XCPTCONTEXT_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
Review Comment:
```suggestion
uintptr_t sigreturn;
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,569 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#ifndef __ASSEMBLY__
+ #include <stdint.h>
+ #include <inttypes.h>
+ #define BIT(n) (UINT32_C(1) << (n))
+ #define BIT64(n) (UINT64_C(1) << (n))
+#else
+ #define BIT(n) ((1UL) << (n))
+ #define BIT64(n) ((1ULL) << (n))
Review Comment:
why
```
#include <inttypes.h>
#define BIT(n) (UINT32_C(1) << (n))
#define BIT64(n) (UINT64_C(1) << (n))
```
can't be used for all the cases? I think that only `#include <stdint.h>` should be wrapped with `#ifndef __ASSEMBLY__`. Or assembly preprocessor does not understand `##`? If it does not understand `##` then lets use `((1UL) << (n))` and `((1ULL) << (n))` in both cases.
BTW no need for `()` around `1UL` and `1ULL`.
Also strange that `#define UINT64_C(x) x ## ul`, but for assembly you use `1ULL` for 64 bit and `1UL` for 32.
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,404 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <sys/types.h>
+#ifndef __ASSEMBLY__
+# include <stdbool.h>
+#endif
+
+#include <nuttx/config.h>
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define XCPTCONTEXT_FPU_REGS (66)
+#else
+#define XCPTCONTEXT_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * XCPTCONTEXT_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + XCPTCONTEXT_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t *regs;
+
+ /* task context, for signal process */
+
+ uint64_t *saved_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ uint64_t *fpu_regs;
+ uint64_t *saved_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_ELR];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+# ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+# endif
+
+# ifdef CONFIG_ARCH_KERNEL_STACK
+ /* In this configuration, all syscalls execute from an internal kernel
+ * stack. Why? Because when we instantiate and initialize the address
+ * environment of the new user process, we will temporarily lose the
+ * address environment of the old user process, including its stack
+ * contents. The kernel C logic will crash immediately with no valid
+ * stack in place.
+ */
+
+ uint64_t *ustkptr; /* Saved user stack pointer */
+ uint64_t *kstack; /* Allocate base of the (aligned) kernel stack */
+ uint64_t *kstkptr; /* Saved kernel stack pointer */
Review Comment:
```suggestion
uintptr_t *ustkptr; /* Saved user stack pointer */
uintptr_t *kstack; /* Allocate base of the (aligned) kernel stack */
uintptr_t *kstkptr; /* Saved kernel stack pointer */
```
since `ustack` is `uintptr_t *ustack[ARCH_STACK_NSECTS];`
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,569 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#ifndef __ASSEMBLY__
+ #include <stdint.h>
+ #include <inttypes.h>
+ #define BIT(n) (UINT32_C(1) << (n))
+ #define BIT64(n) (UINT64_C(1) << (n))
+#else
+ #define BIT(n) ((1UL) << (n))
+ #define BIT64(n) ((1ULL) << (n))
+#endif
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+#define DAIFSET_FIQ_BIT BIT(0)
+#define DAIFSET_IRQ_BIT BIT(1)
+#define DAIFSET_ABT_BIT BIT(2)
+#define DAIFSET_DBG_BIT BIT(3)
+
+#define DAIFCLR_FIQ_BIT BIT(0)
+#define DAIFCLR_IRQ_BIT BIT(1)
+#define DAIFCLR_ABT_BIT BIT(2)
+#define DAIFCLR_DBG_BIT BIT(3)
+
+#define DAIF_FIQ_BIT BIT(6)
+#define DAIF_IRQ_BIT BIT(7)
+#define DAIF_ABT_BIT BIT(8)
+#define DAIF_DBG_BIT BIT(9)
+
+#define DAIF_MASK (0xf << 6)
+
+/* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ *
+ * SCTLR_EL1: System Control Register (EL1)
+ * SCTLR_EL2: System Control Register (EL2)
+ * SCTLR_EL3: System Control Register (EL3)
+ *
+ */
+
+#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(20) | BIT(11))
+
+#define SCTLR_M_BIT BIT(0)
+#define SCTLR_A_BIT BIT(1)
+#define SCTLR_C_BIT BIT(2)
+#define SCTLR_SA_BIT BIT(3)
+#define SCTLR_I_BIT BIT(12)
+
+/* SPSR M[3:0] define
+ *
+ * Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ * SPSR_EL1: Saved Program Status Register (EL1)
+ * SPSR_EL2: Saved Program Status Register (EL2)
+ * SPSR_EL3: Saved Program Status Register (EL3)
+ *
+ * reference to Programmer’s Guide for ARMv8-A
+ * (ARM DEN0024A, ID050815 ), 4.1.2 Stack pointer
+ *
+ * The T suffix, indicates use of the SP_EL0 stack pointer.
+ * The H suffix, indicates use of the SP_ELx stack pointer.
+ *
+ */
+
+#define SPSR_DAIF_SHIFT (6)
+#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE_EL0T (0x0)
+#define SPSR_MODE_EL1T (0x4)
+#define SPSR_MODE_EL1H (0x5)
+#define SPSR_MODE_EL2T (0x8)
+#define SPSR_MODE_EL2H (0x9)
+#define SPSR_MODE_MASK (0xf)
+
+/* CurrentEL: Current Exception Level */
+
+#define MODE_EL_SHIFT (0x2)
+#define MODE_EL_MASK (0x3)
+
+#define MODE_EL3 (0x3)
+#define MODE_EL2 (0x2)
+#define MODE_EL1 (0x1)
+#define MODE_EL0 (0x0)
+
+/* struct arm64_boot_params member offset for assembly code
+ * struct is defined at arm64_cpustart.c
+ */
+
+#define BOOT_PARAM_MPID 0
+#define BOOT_PARAM_SP 8
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MAX
+# define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+# define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
+
+/* MPIDR_EL1, Multiprocessor Affinity Register */
+
+#define MPIDR_AFFLVL_MASK (0xff)
+
+#define MPIDR_AFF0_SHIFT (0)
+#define MPIDR_AFF1_SHIFT (8)
+#define MPIDR_AFF2_SHIFT (16)
+#define MPIDR_AFF3_SHIFT (32)
+
+#define MPIDR_AFFLVL(mpidr, aff_level) \
+ (((mpidr) >> MPIDR_AFF ## aff_level ## _SHIFT) & MPIDR_AFFLVL_MASK)
+
+#define GET_MPIDR() read_sysreg(mpidr_el1)
+#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL((mpidr), 0)
+#define IS_PRIMARY_CORE() (!MPIDR_TO_CORE(GET_MPIDR()))
+
+/* System register interface to GICv3 */
+
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
+#define ICC_SGI1R S3_0_C12_C11_5
+#define ICC_SRE_EL1 S3_0_C12_C12_5
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_RPR_EL1 S3_0_C12_C11_3
+#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
+#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
+#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
+#define ICC_IAR0_EL1 S3_0_C12_C8_0
+#define ICC_IAR1_EL1 S3_0_C12_C12_0
+#define ICC_EOIR0_EL1 S3_0_C12_C8_1
+#define ICC_EOIR1_EL1 S3_0_C12_C12_1
+#define ICC_SGI0R_EL1 S3_0_C12_C11_7
+
+/* register constants */
+#define ICC_SRE_ELX_SRE_BIT BIT(0)
+#define ICC_SRE_ELX_DFB_BIT BIT(1)
+#define ICC_SRE_ELX_DIB_BIT BIT(2)
+#define ICC_SRE_EL3_EN_BIT BIT(3)
+
+/* ICC SGI macros */
+#define SGIR_TGT_MASK (0xffff)
+#define SGIR_AFF1_SHIFT (16)
+#define SGIR_AFF2_SHIFT (32)
+#define SGIR_AFF3_SHIFT (48)
+#define SGIR_AFF_MASK (0xf)
+#define SGIR_INTID_SHIFT (24)
+#define SGIR_INTID_MASK (0xf)
+#define SGIR_IRM_SHIFT (40)
+#define SGIR_IRM_MASK (0x1)
+#define SGIR_IRM_TO_AFF (0)
+#define SGIR_IRM_TO_ALL (1)
+
+#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
+ ((((uint64_t)(_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
+ (((uint64_t)(_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
+ (((uint64_t)(_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
+ (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
+ (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
+ ((_tgt) & SGIR_TGT_MASK))
+
+/* CPTR_EL2, Architectural Feature Trap Register (EL2) */
+
+#define CPTR_EZ_BIT BIT(8)
+#define CPTR_TFP_BIT BIT(10)
+#define CPTR_TTA_BIT BIT(20)
+#define CPTR_TCPAC_BIT BIT(31)
+#define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
+
+/* CPACR_EL1, Architectural Feature Access Control Register */
+#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
+
+/* SCR_EL3, Secure Configuration Register */
+#define SCR_NS_BIT BIT(0)
+#define SCR_IRQ_BIT BIT(1)
+#define SCR_FIQ_BIT BIT(2)
+#define SCR_EA_BIT BIT(3)
+#define SCR_SMD_BIT BIT(7)
+#define SCR_HCE_BIT BIT(8)
+#define SCR_RW_BIT BIT(10)
+#define SCR_ST_BIT BIT(11)
+#define SCR_RES1 (BIT(4) | BIT(5))
+
+/* HCR_EL2, Hypervisor Configuration Register */
+
+#define HCR_FMO_BIT BIT(3)
+#define HCR_IMO_BIT BIT(4)
+#define HCR_AMO_BIT BIT(5)
+#define HCR_RW_BIT BIT(31)
+
+/* CNTHCTL_EL2 bits definitions */
+
+#define CNTHCTL_EL2_EL1PCEN_EN BIT(1)
+#define CNTHCTL_EL2_EL1PCTEN_EN BIT(0)
+
+/* CNTV_CVAL, Counter-timer Virtual Timer CompareValue register
+ * CNTV_CTL, Counter-timer Virtual Timer Control register
+ */
+
+#define CNTV_CTL_ENABLE_BIT BIT(0)
+#define CNTV_CTL_IMASK_BIT BIT(1)
+
+/* Maximum numbers of translation tables
+ * This option specifies the maximum numbers of translation tables
+ * excluding the base translation table. Based on this, translation
+ * tables are allocated at compile time and used at runtime as needed.
+ * If the runtime need exceeds preallocated numbers of translation
+ * tables, it will result in assert. Number of translation tables
+ * required is decided based on how many discrete memory regions
+ * (both normal and device memory) are present on given platform and
+ * how much granularity is required while assigning attributes
+ * to these memory regions.
+ */
+
+#define CONFIG_MAX_XLAT_TABLES 7
+
+/* Virtual address space size
+ * Allows choosing one of multiple possible virtual address
+ * space sizes. The level of translation table is determined by
+ * a combination of page size and virtual address space size.
+ *
+ * The choice could be: 32, 36, 42, 48
+ */
+
+#define CONFIG_ARM64_VA_BITS 36
+
+/* Physical address space size
+ * Choose the maximum physical address range that the kernel will support.
+ *
+ * The choice could be: 32, 36, 42, 48
+ */
+
+#define CONFIG_ARM64_PA_BITS 36
+
+#define L1_CACHE_SHIFT (6)
+#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/* See Arm® Architecture Reference Manual
+ * ARM DDI 0487E.a C6.2.81
+ */
+
+static inline void __DSB(void)
+{
+ __asm__ volatile ("dsb sy" : : : "memory");
+}
+
+/* See Arm® Architecture Reference Manual
+ * ARM DDI 0487E.a C6.2.79
+ */
+
+static inline void __DMB(void)
+{
+ __asm__ volatile ("dmb sy" : : : "memory");
+}
+
+/* See Arm® Architecture Reference Manual
+ * ARM DDI 0487E.a C6.2.96
+ */
+
+static inline void __ISB(void)
+{
+ __asm__ volatile ("isb" : : : "memory");
+}
Review Comment:
let's create `barriers.h` same as for ARM32 and rename to `ARM_DSB`, `ARM_DMB` and `ARM_ISB` and use it as defines
##########
arch/arm64/src/common/arm64_fatal.c:
##########
@@ -0,0 +1,364 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <debug.h>
+#include <assert.h>
+#include <sched.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/tls.h>
+#include <nuttx/board.h>
+#include <arch/chip/chip.h>
+#include <nuttx/syslog/syslog.h>
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+#include "arm64_fatal.h"
+#include "arm64_arch_timer.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: print_ec_cause
+ ****************************************************************************/
+
+static void print_ec_cause(uint64_t esr)
+{
+ uint32_t ec = (uint32_t)esr >> 26;
+
+ switch (ec)
+ {
+ case 0b000000:
+ {
+ sinfo("Unknown reason\n");
+ break;
+ }
+
+ case 0b000001:
+ {
+ sinfo("Trapped WFI or WFE instruction execution\n");
+ break;
+ }
+
+ case 0b000011:
+ {
+ sinfo(
+ "Trapped MCR or MRC access with (coproc==0b1111) that "
+ "is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000100:
+ {
+ sinfo(
+ "Trapped MCRR or MRRC access with (coproc==0b1111) "
+ "that is not reported using EC 0b000000\n");
Review Comment:
add 2 spaces for case block
##########
arch/arm64/src/common/arm64_fatal.c:
##########
@@ -0,0 +1,364 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <debug.h>
+#include <assert.h>
+#include <sched.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/tls.h>
+#include <nuttx/board.h>
+#include <arch/chip/chip.h>
+#include <nuttx/syslog/syslog.h>
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+#include "arm64_fatal.h"
+#include "arm64_arch_timer.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: print_ec_cause
+ ****************************************************************************/
+
+static void print_ec_cause(uint64_t esr)
+{
+ uint32_t ec = (uint32_t)esr >> 26;
+
+ switch (ec)
+ {
+ case 0b000000:
+ {
+ sinfo("Unknown reason\n");
+ break;
+ }
+
+ case 0b000001:
+ {
+ sinfo("Trapped WFI or WFE instruction execution\n");
+ break;
+ }
+
+ case 0b000011:
+ {
+ sinfo(
+ "Trapped MCR or MRC access with (coproc==0b1111) that "
+ "is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000100:
+ {
+ sinfo(
+ "Trapped MCRR or MRRC access with (coproc==0b1111) "
+ "that is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000101:
+ {
+ sinfo("Trapped MCR or MRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b000110:
+ {
+ sinfo("Trapped LDC or STC access\n");
+ break;
+ }
+
+ case 0b000111:
+ {
+ sinfo(
+ "Trapped access to SVE, Advanced SIMD, or "
+ "floating-point functionality\n");
+ break;
+ }
+
+ case 0b001100:
+ {
+ sinfo("Trapped MRRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b001101:
+ {
+ sinfo("Branch Target Exception\n");
+ break;
+ }
+
+ case 0b001110:
+ {
+ sinfo("Illegal Execution state\n");
+ break;
+ }
+
+ case 0b010001:
+ {
+ sinfo("SVC instruction execution in AArch32 state\n");
+ break;
+ }
+
+ case 0b011000:
+ {
+ sinfo(
+ "Trapped MSR, MRS or System instruction execution in "
+ "AArch64 state, that is not reported using EC "
+ "0b000000, 0b000001 or 0b000111\n");
+ break;
+ }
+
+ case 0b011001:
+ {
+ sinfo("Trapped access to SVE functionality\n");
+ break;
+ }
+
+ case 0b100000:
+ {
+ sinfo(
+ "Instruction Abort from a lower Exception level, that "
+ "might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b100001:
+ {
+ sinfo(
+ "Instruction Abort taken without a change in Exception level.\n");
+ break;
+ }
+
+ case 0b100010:
+ {
+ sinfo("PC alignment fault exception.\n");
+ break;
+ }
+
+ case 0b100100:
+ {
+ sinfo(
+ "Data Abort from a lower Exception level, that might "
+ "be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b100101:
+ {
+ sinfo("Data Abort taken without a change in Exception level\n");
+ break;
+ }
+
+ case 0b100110:
+ {
+ sinfo("SP alignment fault exception\n");
+ break;
+ }
+
+ case 0b101000:
+ {
+ sinfo(
+ "Trapped floating-point exception "
+ "taken from AArch32 state\n");
+ break;
+ }
+
+ case 0b101100:
+ {
+ sinfo(
+ "Trapped floating-point exception "
+ "taken from AArch64 state.\n");
+ break;
+ }
+
+ case 0b101111:
+ {
+ sinfo("SError interrupt\n");
+ break;
+ }
+
+ case 0b110000:
+ {
+ sinfo(
+ "Breakpoint exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110001:
+ {
+ sinfo(
+ "Breakpoint exception taken without a change in "
+ "Exception level\n");
+ break;
+ }
+
+ case 0b110010:
+ {
+ sinfo(
+ "Software Step exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110011:
+ {
+ sinfo(
+ "Software Step exception taken without a change in "
+ "Exception level\n");
+ break;
+ }
+
+ case 0b110100:
+ {
+ sinfo(
+ "Watchpoint exception from a lower Exception level, "
+ "that might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b110101:
+ {
+ sinfo(
+ "Watchpoint exception taken without a change in "
+ "Exception level.\n");
+ break;
+ }
+
+ case 0b111000:
+ {
+ sinfo("BKPT instruction execution in AArch32 state\n");
+ break;
+ }
+
+ case 0b111100:
+ {
+ sinfo("BRK instruction execution in AArch64 state.\n");
+ break;
+ }
+
+ default:
+ break;
+ }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_fatal_error
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void arm64_fatal_error(unsigned int reason, struct regs_context * reg)
+{
+ uint64_t el, esr, elr, far;
+ int cpu = up_cpu_index();
+
+ sinfo("reason = %d\n", reason);
+ sinfo("arm64_fatal_error: CPU%d task: %s\n", cpu, running_task()->name);
+
+ if (reason != K_ERR_SPURIOUS_IRQ)
+ {
+ __asm__ volatile ("mrs %0, CurrentEL" : "=r" (el));
+
+ switch (GET_EL(el))
+ {
+ case MODE_EL1:
+ {
+ sinfo("CurrentEL: MODE_EL1\n");
+ __asm__ volatile ("mrs %0, esr_el1" : "=r" (esr));
+ __asm__ volatile ("mrs %0, far_el1" : "=r" (far));
+ __asm__ volatile ("mrs %0, elr_el1" : "=r" (elr));
+ break;
+ }
+
+ case MODE_EL2:
+ {
+ sinfo("CurrentEL: MODE_EL2\n");
+ __asm__ volatile ("mrs %0, esr_el2" : "=r" (esr));
+ __asm__ volatile ("mrs %0, far_el2" : "=r" (far));
+ __asm__ volatile ("mrs %0, elr_el2" : "=r" (elr));
Review Comment:
add 2 spaces for case block
##########
arch/arm64/src/common/arm64_fatal.h:
##########
@@ -0,0 +1,78 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
+
+/**
+ * @defgroup fatal_apis Fatal error APIs
+ * @ingroup kernel_apis
+ * @{
+ */
+
+#define K_ERR_CPU_EXCEPTION (0)
+#define K_ERR_CPU_MODE32 (1)
+#define K_ERR_SPURIOUS_IRQ (2)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm64_fatal_error
+ *
+ * Description:
+ * fatal error handle for arm64
+ * Input Parameters:
+ * reason: error reason
+ * reg: exception stack reg context
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+void arm64_fatal_error(unsigned int reason, struct regs_context * reg);
+void arm64_dump_fatal(struct regs_context * reg);
+
+#define __builtin_unreachable() \
+ do { \
Review Comment:
```suggestion
do { \
```
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,319 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
+
+#define GIC_DIST_IGROUPR 0x0080
+#define GIC_DIST_ISENABLER 0x0100
+#define GIC_DIST_ICENABLER 0x0180
+#define GIC_DIST_ISPENDR 0x0200
+#define GIC_DIST_ICPENDR 0x0280
+#define GIC_DIST_ISACTIVER 0x0300
+#define GIC_DIST_ICACTIVER 0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR 0x0800
+#define GIC_DIST_ICFGR 0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR 0x0f00
+
+/* GICD GICR common access macros */
+
+#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD_PIDR2 : Peripheral ID2 Register
+ * bit assignments
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+#define GICD_PIDR2_ARCH_MASK 0xf0
+#define GICD_PIDR2_ARCH_GICV3 0x30
+#define GICD_PIDR2_ARCH_GICV4 0x40
+
+/* GICD_TYPER : Interrupt Controller Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+#define GICD_TYPER_RSS BIT(26)
+#define GICD_TYPER_LPIS BIT(17)
+#define GICD_TYPER_MBIS BIT(16)
+#define GICD_TYPER_ESPI BIT(8)
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
+#define GICD_TYPER_ESPIS(typer) \
+ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
+
+/* Common Helper Constants */
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
+ ((intid) < GIC_PPI_INT_BASE))
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_NUM_INTR_PER_REG 32
+#define GIC_NUM_CFG_PER_REG 16
+#define GIC_NUM_PRI_PER_REG 4
+
+/* GIC idle priority : value '0xff' will allow all interrupts */
+
+#define GIC_IDLE_PRIO 0xff
+
+/* Priority levels 0:255 */
+
+#define GIC_PRI_MASK 0xff
+
+/* '0xa0'is used to initialize each interrtupt default priority.
+ * This is an arbitrary value in current context.
+ * Any value '0x80' to '0xff' will work for both NS and S state.
+ * The values of individual interrupt and default has to be chosen
+ * carefully if PMR and BPR based nesting and preemption has to be done.
+ */
+
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
+
+/* Register bit definitions */
+
+/* GICD_CTLR Interrupt group definitions */
+#define GICD_CTLR_ENABLE_G0 0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S 2
+#define GICD_CTRL_ARE_S 4
+#define GICD_CTRL_ARE_NS 5
+#define GICD_CTRL_NS 6
+#define GICD_CGRL_E1NWF 7
+
+/* GICD_CTLR Register write progress bit */
+#define GICD_CTLR_RWP 31
+
+/* GICR_CTLR */
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP 3
+
+/* GICD_TYPER.ITLinesNumber 0:4 */
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICR： Re-Distributor registers, offsets from RD_base(n) */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00A0
+#define GICR_INVALLR 0x00B0
+#define GICR_SYNCR 0x00C0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+#define GICR_IDREGS 0xFFD0
+#define GICR_PIDR2 0xFFE8
+
+/* GICR_PIDR2 : Peripheral ID2 Register
+ * bit assignments are the same as those for GICD_PIDR2)
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+
+#define GICR_PIDR2_ARCH_MASK 0xf0
+#define GICR_PIDR2_ARCH_GICV3 0x30
+#define GICR_PIDR2_ARCH_GICV4 0x40
+
+/* GICR_TYPER : Redistributor Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ * chapter 9.11.35 for detail descriptions
+ */
+
+#define GICR_TYPER_PLPIS BIT(0)
+#define GICR_TYPER_VLPIS BIT(1)
+#define GICR_TYPER_DIRECTLPIS BIT(3)
+#define GICR_TYPER_LAST BIT(4)
+
+/* GICR_WAKER */
+#define GICR_WAKER_PS 1
+#define GICR_WAKER_CA 2
+
+/* SGI base is at 64K offset from Redistributor */
+#define GICR_SGI_BASE_OFF 0x10000
+
+/* GICD_ICFGR */
+#define GICD_ICFGR_MASK BIT_MASK(2)
+#define GICD_ICFGR_TYPE BIT(1)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_SPI_MAX_INTID 1019
+#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \
+ ((intid) <= GIC_SPI_MAX_INTID))
+
+/* GITCD_IROUTER */
+#define GIC_DIST_IROUTER 0x6000
+#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define IRQ_DEFAULT_PRIORITY 0xa0
+
+#define GIC_IRQ_SGI0 0
+#define GIC_IRQ_SGI1 1
+#define GIC_IRQ_SGI2 2
+#define GIC_IRQ_SGI3 3
+#define GIC_IRQ_SGI4 4
+#define GIC_IRQ_SGI5 5
+#define GIC_IRQ_SGI6 6
+#define GIC_IRQ_SGI7 7
+#define GIC_IRQ_SGI8 8
+#define GIC_IRQ_SGI9 9
+#define GIC_IRQ_SGI10 10
+#define GIC_IRQ_SGI11 11
+#define GIC_IRQ_SGI12 12
+#define GIC_IRQ_SGI13 13
+#define GIC_IRQ_SGI14 14
+#define GIC_IRQ_SGI15 15
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+bool arm64_gic_irq_is_enabled(unsigned int intid);
+int arm64_gic_initialize(void);
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags);
+
+/****************************************************************************
+ * Name: arm64_decodeirq
+ *
+ * Description:
+ * This function is called from the IRQ vector handler in arm_vectors.S.
+ * At this point, the interrupt has been taken and the registers have
+ * been saved on the stack. This function simply needs to determine the
+ * the irq number of the interrupt and then to call arm_doirq to dispatch
+ * the interrupt.
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area on the stack.
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_decodeirq(uint64_t *regs);
+
+int arm64_gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list);
Review Comment:
```suggestion
int arm64_gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
uint16_t target_list);
```
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,366 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
Review Comment:
```suggestion
#define STACK_ALIGN_MASK (STACK_ALIGNMENT - 1)
```
##########
arch/arm64/src/common/arm64_usestack.c:
##########
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_usestack.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
Review Comment:
```suggestion
****************************************************************************/
#include <nuttx/config.h>
```
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,619 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one
+ * complete table */
+#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX 3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+ (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+
+#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT \
+ (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT \
+ (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT \
+ (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+ (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+ (XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+ ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21) - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \
+ ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \
+ ? 0U \
+ : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \
+ ? 1U \
+ : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \
+ ? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \
+ (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
+ CONFIG_ARM64_VA_BITS)
+
+static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
+ NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
+
+static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+
+#if (CONFIG_ARM64_PA_BITS == 48)
+#define TCR_PS_BITS TCR_PS_BITS_256TB
+#elif (CONFIG_ARM64_PA_BITS == 44)
+#define TCR_PS_BITS TCR_PS_BITS_16TB
+#elif (CONFIG_ARM64_PA_BITS == 42)
+#define TCR_PS_BITS TCR_PS_BITS_4TB
+#elif (CONFIG_ARM64_PA_BITS == 40)
+#define TCR_PS_BITS TCR_PS_BITS_1TB
+#elif (CONFIG_ARM64_PA_BITS == 36)
+#define TCR_PS_BITS TCR_PS_BITS_64GB
+#else
+#define TCR_PS_BITS TCR_PS_BITS_4GB
+#endif
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/* NuttX RTOS execution regions with appropriate attributes */
+
+static const struct arm_mmu_region mmu_nxrt_regions[] =
+{
+ /* Mark text segment cacheable,read only and executable */
+
+ MMU_REGION_FLAT_ENTRY("nx_code",
+ (uint64_t)_stext,
+ (uint64_t)_sztext,
+ MT_CODE | MT_SECURE),
+
+ /* Mark rodata segment cacheable, read only and execute-never */
+
+ MMU_REGION_FLAT_ENTRY("nx_rodata",
+ (uint64_t)_srodata,
+ (uint64_t)_szrodata,
+ MT_RODATA | MT_SECURE),
+
+ /* Mark rest of the mirtos execution regions (data, bss, noinit, etc.)
+ * cacheable, read-write
+ * Note: read-write region is marked execute-ever internally
+ */
+
+ MMU_REGION_FLAT_ENTRY("nx_data",
+ (uint64_t)_sdata,
+ (uint64_t)_szdata,
+ MT_NORMAL | MT_RW | MT_SECURE),
+};
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Translation table control register settings */
+
+static uint64_t get_tcr(int el)
+{
+ uint64_t tcr;
+ uint64_t va_bits = CONFIG_ARM64_VA_BITS;
+ uint64_t tcr_ps_bits;
+
+ tcr_ps_bits = TCR_PS_BITS;
+
+ if (el == 1)
+ {
+ tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+
+ /* TCR_EL1.EPD1: Disable translation table walk for addresses
+ * that are translated using TTBR1_EL1.
+ */
+
+ tcr |= TCR_EPD1_DISABLE;
+ }
+ else
+ {
+ tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+ }
+
+ tcr |= TCR_T0SZ(va_bits);
+
+ /* Translation table walk is cacheable, inner/outer WBWA and
+ * inner shareable
+ */
+
+ tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+ return tcr;
+}
+
+static int pte_desc_type(uint64_t *pte)
+{
+ return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static uint64_t *calculate_pte_index(uint64_t addr, int level)
+{
+ int base_level = XLAT_TABLE_BASE_LEVEL;
+ uint64_t *pte;
+ uint64_t idx;
+ unsigned int i;
+
+ /* Walk through all translation tables to find pte index */
+
+ pte = (uint64_t *)base_xlat_table;
+ for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++)
+ {
+ idx = XLAT_TABLE_VA_IDX(addr, i);
+ pte += idx;
+
+ /* Found pte index */
+
+ if (i == level)
+ {
+ return pte;
+ }
+
+ /* if PTE is not table desc, can't traverse */
+
+ if (pte_desc_type(pte) != PTE_TABLE_DESC)
+ {
+ return NULL;
+ }
+
+ /* Move to the next translation table level */
+
+ pte = (uint64_t *)(*pte & 0x0000fffffffff000);
+ }
+
+ return NULL;
+}
+
+static void set_pte_table_desc(uint64_t *pte, uint64_t *table,
+ unsigned int level)
+{
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: [Table] %p\n", pte, table);
+#endif
+
+ /* Point pte to new table */
+
+ *pte = PTE_TABLE_DESC | (uint64_t)table;
+}
+
+static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
+ unsigned int attrs, unsigned int level)
+{
+ uint64_t desc = addr_pa;
+ unsigned int mem_type;
+
+ desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+ /* NS bit for security memory access from secure state */
+
+ desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+ /* AP bits for Data access permission */
+
+ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+ /* the access flag */
+
+ desc |= PTE_BLOCK_DESC_AF;
+
+ /* memory attribute index field */
+
+ mem_type = MT_TYPE(attrs);
+ desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+ switch (mem_type)
+ {
+ case MT_DEVICE_NGNRNE:
+ case MT_DEVICE_NGNRE:
+ case MT_DEVICE_GRE:
+ {
+ /* Access to Device memory and non-cacheable memory are coherent
+ * for all observers in the system and are treated as
+ * Outer shareable, so, for these 2 types of memory,
+ * it is not strictly needed to set shareability field
+ */
+
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+
+ /* Map device memory as execute-never */
+
+ desc |= PTE_BLOCK_DESC_PXN;
+ desc |= PTE_BLOCK_DESC_UXN;
+ break;
+ }
+
+ case MT_NORMAL_NC:
+ case MT_NORMAL:
+ {
+ /* Make Normal RW memory as execute never */
+
+ if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+ {
+ desc |= PTE_BLOCK_DESC_PXN;
+ }
+
+ if (mem_type == MT_NORMAL)
+ {
+ desc |= PTE_BLOCK_DESC_INNER_SHARE;
+ }
+ else
+ {
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+ }
+ }
+ }
+
+#if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE)
+ sinfo("%s ", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: ", pte);
+ sinfo("%s ",
+ (mem_type ==
+ MT_NORMAL) ? "MEM" :((mem_type == MT_NORMAL_NC) ? "NC" : "DEV"));
+ sinfo("%s ", (attrs & MT_RW) ? "-RW" : "-RO");
+ sinfo("%s ", (attrs & MT_NS) ? "-NS" : "-S");
+ sinfo("%s ", (attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC");
+ sinfo("\n");
+#endif
+
+ *pte = desc;
+}
+
+/* Returns a new reallocated table */
+
+static uint64_t *new_prealloc_table(void)
+{
+ static unsigned int table_idx;
+
+ __MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
+ "Enough xlat tables not allocated");
+
+ return (uint64_t *)(xlat_tables[table_idx++]);
+}
+
+/* Splits a block into table with entries spanning the old block */
+
+static void split_pte_block_desc(uint64_t *pte, int level)
+{
+ uint64_t old_block_desc = *pte;
+ uint64_t *new_table;
+ unsigned int i = 0;
+
+ /* get address size shift bits for next level */
+
+ int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1);
+
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("Splitting existing PTE %p(L%d)\n", pte, level);
+#endif
+
+ new_table = new_prealloc_table();
+
+ for (i = 0; i < XLAT_TABLE_ENTRIES; i++)
+ {
+ new_table[i] = old_block_desc | (i << levelshift);
+
+ if ((level + 1) == 3)
Review Comment:
```suggestion
if (level == 2)
```
##########
arch/arm64/src/common/arm64_releasestack.c:
##########
@@ -0,0 +1,113 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_releasestack.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/tls.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include "arm64_internal.h"
Review Comment:
```suggestion
#include <arch/irq.h>
#include "arm64_internal.h"
```
##########
arch/arm64/include/qemu/chip.h:
##########
@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/arm64/include/qemu/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
+#define __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_QEMU_A53)
+
+#define CONFIG_GICD_BASE 0x8000000
+#define CONFIG_GICR_BASE 0x80a0000
+
+#define CONFIG_RAMBANK1_ADDR 0x40000000
+#define CONFIG_RAMBANK1_SIZE MB(128)
Review Comment:
above at line 32 of this file
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
Review Comment:
The current macro is dangerous because `(ptr) - sizeof(type)` if using `ptr` size type for calculation. So if `ptr` is `uint8_t *` then it will jump back by `sizeof(type)` bytes, but if it is `uint64_t *` than by `sizeof(type) * 8` bytes
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,569 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#ifndef __ASSEMBLY__
+ #include <stdint.h>
+ #include <inttypes.h>
+ #define BIT(n) (UINT32_C(1) << (n))
+ #define BIT64(n) (UINT64_C(1) << (n))
+#else
+ #define BIT(n) ((1UL) << (n))
+ #define BIT64(n) ((1ULL) << (n))
+#endif
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+#define DAIFSET_FIQ_BIT BIT(0)
+#define DAIFSET_IRQ_BIT BIT(1)
+#define DAIFSET_ABT_BIT BIT(2)
+#define DAIFSET_DBG_BIT BIT(3)
+
+#define DAIFCLR_FIQ_BIT BIT(0)
+#define DAIFCLR_IRQ_BIT BIT(1)
+#define DAIFCLR_ABT_BIT BIT(2)
+#define DAIFCLR_DBG_BIT BIT(3)
+
+#define DAIF_FIQ_BIT BIT(6)
+#define DAIF_IRQ_BIT BIT(7)
+#define DAIF_ABT_BIT BIT(8)
+#define DAIF_DBG_BIT BIT(9)
+
+#define DAIF_MASK (0xf << 6)
+
+/* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ *
+ * SCTLR_EL1: System Control Register (EL1)
+ * SCTLR_EL2: System Control Register (EL2)
+ * SCTLR_EL3: System Control Register (EL3)
+ *
+ */
+
+#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(20) | BIT(11))
+
+#define SCTLR_M_BIT BIT(0)
+#define SCTLR_A_BIT BIT(1)
+#define SCTLR_C_BIT BIT(2)
+#define SCTLR_SA_BIT BIT(3)
+#define SCTLR_I_BIT BIT(12)
+
+/* SPSR M[3:0] define
+ *
+ * Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ * SPSR_EL1: Saved Program Status Register (EL1)
+ * SPSR_EL2: Saved Program Status Register (EL2)
+ * SPSR_EL3: Saved Program Status Register (EL3)
+ *
+ * reference to Programmer’s Guide for ARMv8-A
+ * (ARM DEN0024A, ID050815 ), 4.1.2 Stack pointer
+ *
+ * The T suffix, indicates use of the SP_EL0 stack pointer.
+ * The H suffix, indicates use of the SP_ELx stack pointer.
+ *
+ */
+
+#define SPSR_DAIF_SHIFT (6)
+#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE_EL0T (0x0)
+#define SPSR_MODE_EL1T (0x4)
+#define SPSR_MODE_EL1H (0x5)
+#define SPSR_MODE_EL2T (0x8)
+#define SPSR_MODE_EL2H (0x9)
+#define SPSR_MODE_MASK (0xf)
+
+/* CurrentEL: Current Exception Level */
+
+#define MODE_EL_SHIFT (0x2)
+#define MODE_EL_MASK (0x3)
+
+#define MODE_EL3 (0x3)
+#define MODE_EL2 (0x2)
+#define MODE_EL1 (0x1)
+#define MODE_EL0 (0x0)
+
+/* struct arm64_boot_params member offset for assembly code
+ * struct is defined at arm64_cpustart.c
+ */
+
+#define BOOT_PARAM_MPID 0
+#define BOOT_PARAM_SP 8
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MAX
+# define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+# define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
+
+/* MPIDR_EL1, Multiprocessor Affinity Register */
+
+#define MPIDR_AFFLVL_MASK (0xff)
+
+#define MPIDR_AFF0_SHIFT (0)
+#define MPIDR_AFF1_SHIFT (8)
+#define MPIDR_AFF2_SHIFT (16)
+#define MPIDR_AFF3_SHIFT (32)
+
+#define MPIDR_AFFLVL(mpidr, aff_level) \
+ (((mpidr) >> MPIDR_AFF ## aff_level ## _SHIFT) & MPIDR_AFFLVL_MASK)
+
+#define GET_MPIDR() read_sysreg(mpidr_el1)
+#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL((mpidr), 0)
+#define IS_PRIMARY_CORE() (!MPIDR_TO_CORE(GET_MPIDR()))
+
+/* System register interface to GICv3 */
+
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
+#define ICC_SGI1R S3_0_C12_C11_5
+#define ICC_SRE_EL1 S3_0_C12_C12_5
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_RPR_EL1 S3_0_C12_C11_3
+#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
+#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
+#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
+#define ICC_IAR0_EL1 S3_0_C12_C8_0
+#define ICC_IAR1_EL1 S3_0_C12_C12_0
+#define ICC_EOIR0_EL1 S3_0_C12_C8_1
+#define ICC_EOIR1_EL1 S3_0_C12_C12_1
+#define ICC_SGI0R_EL1 S3_0_C12_C11_7
+
+/* register constants */
+#define ICC_SRE_ELX_SRE_BIT BIT(0)
+#define ICC_SRE_ELX_DFB_BIT BIT(1)
+#define ICC_SRE_ELX_DIB_BIT BIT(2)
+#define ICC_SRE_EL3_EN_BIT BIT(3)
+
+/* ICC SGI macros */
+#define SGIR_TGT_MASK (0xffff)
+#define SGIR_AFF1_SHIFT (16)
+#define SGIR_AFF2_SHIFT (32)
+#define SGIR_AFF3_SHIFT (48)
+#define SGIR_AFF_MASK (0xf)
+#define SGIR_INTID_SHIFT (24)
+#define SGIR_INTID_MASK (0xf)
+#define SGIR_IRM_SHIFT (40)
+#define SGIR_IRM_MASK (0x1)
+#define SGIR_IRM_TO_AFF (0)
+#define SGIR_IRM_TO_ALL (1)
+
+#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
+ ((((uint64_t)(_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
+ (((uint64_t)(_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
+ (((uint64_t)(_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
+ (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
+ (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
+ ((_tgt) & SGIR_TGT_MASK))
+
+/* CPTR_EL2, Architectural Feature Trap Register (EL2) */
+
+#define CPTR_EZ_BIT BIT(8)
+#define CPTR_TFP_BIT BIT(10)
+#define CPTR_TTA_BIT BIT(20)
+#define CPTR_TCPAC_BIT BIT(31)
+#define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
+
+/* CPACR_EL1, Architectural Feature Access Control Register */
+#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
+
+/* SCR_EL3, Secure Configuration Register */
+#define SCR_NS_BIT BIT(0)
+#define SCR_IRQ_BIT BIT(1)
+#define SCR_FIQ_BIT BIT(2)
+#define SCR_EA_BIT BIT(3)
+#define SCR_SMD_BIT BIT(7)
+#define SCR_HCE_BIT BIT(8)
+#define SCR_RW_BIT BIT(10)
+#define SCR_ST_BIT BIT(11)
+#define SCR_RES1 (BIT(4) | BIT(5))
+
+/* HCR_EL2, Hypervisor Configuration Register */
+
+#define HCR_FMO_BIT BIT(3)
+#define HCR_IMO_BIT BIT(4)
+#define HCR_AMO_BIT BIT(5)
+#define HCR_RW_BIT BIT(31)
+
+/* CNTHCTL_EL2 bits definitions */
+
+#define CNTHCTL_EL2_EL1PCEN_EN BIT(1)
+#define CNTHCTL_EL2_EL1PCTEN_EN BIT(0)
+
+/* CNTV_CVAL, Counter-timer Virtual Timer CompareValue register
+ * CNTV_CTL, Counter-timer Virtual Timer Control register
+ */
+
+#define CNTV_CTL_ENABLE_BIT BIT(0)
+#define CNTV_CTL_IMASK_BIT BIT(1)
+
+/* Maximum numbers of translation tables
+ * This option specifies the maximum numbers of translation tables
+ * excluding the base translation table. Based on this, translation
+ * tables are allocated at compile time and used at runtime as needed.
+ * If the runtime need exceeds preallocated numbers of translation
+ * tables, it will result in assert. Number of translation tables
+ * required is decided based on how many discrete memory regions
+ * (both normal and device memory) are present on given platform and
+ * how much granularity is required while assigning attributes
+ * to these memory regions.
+ */
+
+#define CONFIG_MAX_XLAT_TABLES 7
+
+/* Virtual address space size
+ * Allows choosing one of multiple possible virtual address
+ * space sizes. The level of translation table is determined by
+ * a combination of page size and virtual address space size.
+ *
+ * The choice could be: 32, 36, 42, 48
+ */
+
+#define CONFIG_ARM64_VA_BITS 36
+
+/* Physical address space size
+ * Choose the maximum physical address range that the kernel will support.
+ *
+ * The choice could be: 32, 36, 42, 48
+ */
+
+#define CONFIG_ARM64_PA_BITS 36
+
+#define L1_CACHE_SHIFT (6)
+#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
Review Comment:
please add few spaces to align with defines above
##########
arch/arm64/src/common/arm64_cpu_psci.h:
##########
@@ -0,0 +1,104 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_CPU_PSCI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <arch/syscall.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+#define PSCI_RET_INVALID_ADDRESS -9
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+typedef unsigned long (*psci_fn)(unsigned long, unsigned long, unsigned long,
+ unsigned long);
Review Comment:
```suggestion
typedef unsigned long (*psci_fn)(unsigned long, unsigned long, unsigned long,
unsigned long);
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,569 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#ifndef __ASSEMBLY__
+ #include <stdint.h>
+ #include <inttypes.h>
+ #define BIT(n) (UINT32_C(1) << (n))
+ #define BIT64(n) (UINT64_C(1) << (n))
+#else
+ #define BIT(n) ((1UL) << (n))
+ #define BIT64(n) ((1ULL) << (n))
+#endif
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+#define DAIFSET_FIQ_BIT BIT(0)
+#define DAIFSET_IRQ_BIT BIT(1)
+#define DAIFSET_ABT_BIT BIT(2)
+#define DAIFSET_DBG_BIT BIT(3)
+
+#define DAIFCLR_FIQ_BIT BIT(0)
+#define DAIFCLR_IRQ_BIT BIT(1)
+#define DAIFCLR_ABT_BIT BIT(2)
+#define DAIFCLR_DBG_BIT BIT(3)
+
+#define DAIF_FIQ_BIT BIT(6)
+#define DAIF_IRQ_BIT BIT(7)
+#define DAIF_ABT_BIT BIT(8)
+#define DAIF_DBG_BIT BIT(9)
+
+#define DAIF_MASK (0xf << 6)
+
+/* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ *
+ * SCTLR_EL1: System Control Register (EL1)
+ * SCTLR_EL2: System Control Register (EL2)
+ * SCTLR_EL3: System Control Register (EL3)
+ *
+ */
+
+#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(20) | BIT(11))
+
+#define SCTLR_M_BIT BIT(0)
+#define SCTLR_A_BIT BIT(1)
+#define SCTLR_C_BIT BIT(2)
+#define SCTLR_SA_BIT BIT(3)
+#define SCTLR_I_BIT BIT(12)
+
+/* SPSR M[3:0] define
+ *
+ * Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ * SPSR_EL1: Saved Program Status Register (EL1)
+ * SPSR_EL2: Saved Program Status Register (EL2)
+ * SPSR_EL3: Saved Program Status Register (EL3)
+ *
+ * reference to Programmer’s Guide for ARMv8-A
+ * (ARM DEN0024A, ID050815 ), 4.1.2 Stack pointer
+ *
+ * The T suffix, indicates use of the SP_EL0 stack pointer.
+ * The H suffix, indicates use of the SP_ELx stack pointer.
+ *
+ */
+
+#define SPSR_DAIF_SHIFT (6)
+#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE_EL0T (0x0)
+#define SPSR_MODE_EL1T (0x4)
+#define SPSR_MODE_EL1H (0x5)
+#define SPSR_MODE_EL2T (0x8)
+#define SPSR_MODE_EL2H (0x9)
+#define SPSR_MODE_MASK (0xf)
+
+/* CurrentEL: Current Exception Level */
+
+#define MODE_EL_SHIFT (0x2)
+#define MODE_EL_MASK (0x3)
+
+#define MODE_EL3 (0x3)
+#define MODE_EL2 (0x2)
+#define MODE_EL1 (0x1)
+#define MODE_EL0 (0x0)
+
+/* struct arm64_boot_params member offset for assembly code
+ * struct is defined at arm64_cpustart.c
+ */
+
+#define BOOT_PARAM_MPID 0
+#define BOOT_PARAM_SP 8
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
Review Comment:
```suggestion
#ifndef ARRAY_SIZE
# define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
```
##########
arch/arm64/src/common/arm64_fpu.h:
##########
@@ -0,0 +1,74 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
Review Comment:
```suggestion
struct tcb_s *fpu_owner;
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,404 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <sys/types.h>
+#ifndef __ASSEMBLY__
+# include <stdbool.h>
+#endif
+
+#include <nuttx/config.h>
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define XCPTCONTEXT_FPU_REGS (66)
+#else
+#define XCPTCONTEXT_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * XCPTCONTEXT_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + XCPTCONTEXT_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t *regs;
+
+ /* task context, for signal process */
+
+ uint64_t *saved_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ uint64_t *fpu_regs;
+ uint64_t *saved_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_ELR];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+# ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+# endif
+
+# ifdef CONFIG_ARCH_KERNEL_STACK
+ /* In this configuration, all syscalls execute from an internal kernel
+ * stack. Why? Because when we instantiate and initialize the address
+ * environment of the new user process, we will temporarily lose the
+ * address environment of the old user process, including its stack
+ * contents. The kernel C logic will crash immediately with no valid
+ * stack in place.
+ */
+
+ uint64_t *ustkptr; /* Saved user stack pointer */
+ uint64_t *kstack; /* Allocate base of the (aligned) kernel stack */
+ uint64_t *kstkptr; /* Saved kernel stack pointer */
+# endif
+#endif
+};
+
+/* Name: up_irq_save, up_irq_restore, and friends.
+ *
+ * NOTE: This function should never be called from application code and,
+ * as a general rule unless you really know what you are doing, this
+ * function should not be called directly from operation system code either:
+ * Typically, the wrapper functions, enter_critical_section() and
+ * leave_critical section(), are probably what you really want.
+ */
+
+/* Return the current IRQ state */
+
+static inline irqstate_t irqstate(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__("mrs %0, daif" : "=r" (flags):: "memory");
+
+ return flags;
+}
+
+/* Disable IRQs and return the previous IRQ state */
+
+static inline irqstate_t up_irq_save(void)
+{
+ irqstate_t flags;
+ __asm__ __volatile__
+ (
+ "mrs %0, daif\n"
+ "msr daifset, #2\n"
+ : "=r" (flags)
+ :
+ : "memory"
+ );
+
+ return flags;
Review Comment:
Please use 2 spaces for this block
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,254 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ UNUSED(regs);
+ UNUSED(arg);
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#else
+
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+ uint64_t next_cycle;
+
+ UNUSED(irq);
+ UNUSED(regs);
+ UNUSED(arg);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ next_cycle = last_cycle + cycle_per_tick;
+
+ if ((uint64_t)(next_cycle - curr_cycle) < MIN_DELAY)
+ {
+ next_cycle += cycle_per_tick;
+ }
+
+ arm64_arch_timer_set_compare(next_cycle);
+ arm64_arch_timer_set_irq_mask(false);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+/* Notes:
+ *
+ * The origin design for ARMv8-A timer is assigned private timer to
+ * every PE(CPU core), the ARM_ARCH_TIMER_IRQ is a PPI so it's
+ * should be enable at every core.
+ *
+ * But for NuttX, it's design only for primary core to handle timer
+ * interrupt and call nxsched_process_timer at timer tick mode.
+ * So we need only enable timer for primary core
+ *
+ * IMX6 use GPT which is a SPI rather than generic timer to handle
+ * timer interrupt
+ */
+
+void arm64_smp_timer_init(void)
+{
+ uint64_t curr_cycle;
+
+ /* set the initial status of timer0 of each secondary core */
+
+ curr_cycle = arm64_arch_timer_count();
+
+ arm64_arch_timer_set_compare(curr_cycle + cycle_per_tick);
+ arm64_arch_timer_enable(true);
+ up_enable_irq(ARM_ARCH_TIMER_IRQ);
+ arm64_arch_timer_set_irq_mask(false);
+}
+
+#endif
+
+uint64_t arm64_counter_read(void)
+{
+ return arm64_arch_timer_count();
+}
+
+void arm64_timer_delay(long mini_sec)
+{
+ unsigned int timeout;
+ volatile unsigned int new_counter;
Review Comment:
why `volatile` is needed here?
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,404 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <sys/types.h>
+#ifndef __ASSEMBLY__
+# include <stdbool.h>
+#endif
+
+#include <nuttx/config.h>
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define XCPTCONTEXT_FPU_REGS (66)
+#else
+#define XCPTCONTEXT_FPU_REGS (0)
+#endif
+
+#define FPUCONTEXT_SIZE (8 * XCPTCONTEXT_FPU_REGS)
+
+#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + XCPTCONTEXT_FPU_REGS)
+#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
+
+#ifndef __ASSEMBLY__
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure. If is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there are pending signals
+ * to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+#ifdef CONFIG_BUILD_KERNEL
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint64_t sigreturn;
+
+#endif
+ /* task stack reg context */
+
+ uint64_t *regs;
+
+ /* task context, for signal process */
+
+ uint64_t *saved_reg;
+
+#ifdef CONFIG_ARCH_FPU
+ uint64_t *fpu_regs;
+ uint64_t *saved_fpu_regs;
+#endif
+
+ /* Extra fault address register saved for common paging logic. In the
+ * case of the pre-fetch abort, this value is the same as regs[REG_ELR];
+ * For the case of the data abort, this value is the value of the fault
+ * address register (FAR) at the time of data abort exception.
+ */
+
+#ifdef CONFIG_PAGING
+ uintptr_t far;
+#endif
+
+#ifdef CONFIG_ARCH_ADDRENV
+# ifdef CONFIG_ARCH_STACK_DYNAMIC
+ /* This array holds the physical address of the level 2 page table used
+ * to map the thread's stack memory. This array will be initially of
+ * zeroed and would be back-up up with pages during page fault exception
+ * handling to support dynamically sized stacks for each thread.
+ */
+
+ uintptr_t *ustack[ARCH_STACK_NSECTS];
+# endif
+
+# ifdef CONFIG_ARCH_KERNEL_STACK
+ /* In this configuration, all syscalls execute from an internal kernel
+ * stack. Why? Because when we instantiate and initialize the address
+ * environment of the new user process, we will temporarily lose the
+ * address environment of the old user process, including its stack
+ * contents. The kernel C logic will crash immediately with no valid
+ * stack in place.
+ */
+
+ uint64_t *ustkptr; /* Saved user stack pointer */
+ uint64_t *kstack; /* Allocate base of the (aligned) kernel stack */
+ uint64_t *kstkptr; /* Saved kernel stack pointer */
+# endif
+#endif
+};
+
+/* Name: up_irq_save, up_irq_restore, and friends.
+ *
+ * NOTE: This function should never be called from application code and,
+ * as a general rule unless you really know what you are doing, this
+ * function should not be called directly from operation system code either:
+ * Typically, the wrapper functions, enter_critical_section() and
+ * leave_critical section(), are probably what you really want.
+ */
+
+/* Return the current IRQ state */
+
+static inline irqstate_t irqstate(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__("mrs %0, daif" : "=r" (flags):: "memory");
+
+ return flags;
+}
+
+/* Disable IRQs and return the previous IRQ state */
+
+static inline irqstate_t up_irq_save(void)
+{
+ irqstate_t flags;
+ __asm__ __volatile__
+ (
+ "mrs %0, daif\n"
+ "msr daifset, #2\n"
+ : "=r" (flags)
+ :
+ : "memory"
+ );
+
+ return flags;
+}
+
+/* Enable IRQs and return the previous IRQ state */
+
+static inline irqstate_t up_irq_enable(void)
+{
+ irqstate_t flags;
+
+ __asm__ __volatile__
+ (
+ "mrs %0, daif\n"
+ "msr daifclr, #2\n"
+ : "=r" (flags)
+ :
+ : "memory"
+ );
+ return flags;
Review Comment:
Please use 2 spaces for this block
##########
arch/arm64/src/common/arm64_cpu_psci.c:
##########
@@ -0,0 +1,187 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_cpu_psci.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
Review Comment:
```suggestion
****************************************************************************/
#include <nuttx/config.h>
```
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,366 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+#define INIT_STACK_DEFINE(sym, size) \
+ char locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define INIT_STACK_ARRAY_DEFINE(sym, n, size) \
+ char locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define INIT_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN char locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define INIT_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN char locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
Review Comment:
```suggestion
#define INIT_STACK_DEFINE_EXTERN(sym, size) \
EXTERN char sym[size]
#define INIT_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
EXTERN char sym[n][size]
```
extern does not require location and alignment attributes. Maybe `INIT_STACK_DEFINE_EXTERN` and `INIT_STACK_ARRAY_DEFINE_EXTERN` can be removed at all.
##########
arch/arm64/src/common/arm64_fpu.h:
##########
@@ -0,0 +1,74 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
+
+ /* for statistic propose */
+
+ int save_count;
+ int restore_count;
+ int switch_count;
+ int exe_depth_count;
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb);
+void arm64_destory_fpu(struct tcb_s * tcb);
Review Comment:
```suggestion
void arm64_destory_fpu(struct tcb_s *tcb);
```
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,619 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
Review Comment:
Maybe use `BIT` macro here and other places in this file?
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,613 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ { __nr_ppis += __ppinum * 32; } \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+static inline unsigned long gic_get_rdist(void)
+{
+ return gic_rdists[this_cpu()];
+}
+
+static inline uint32_t read_gicd_wait_rwp(void)
+{
+ uint32_t value;
+
+ value = getreg32(GICD_CTLR);
+
+ while (value & BIT(GICD_CTLR_RWP))
+ {
+ value = getreg32(GICD_CTLR);
+ }
+
+ return value;
+}
+
+/* Wait for register write pending
+ * TODO: add timed wait
+ */
+
+static int gic_wait_rwp(uint32_t intid)
+{
+ uint32_t rwp_mask;
+ unsigned long base;
+
+ if (intid < GIC_SPI_INT_BASE)
+ {
+ base = (gic_get_rdist() + GICR_CTLR);
+ rwp_mask = BIT(GICR_CTLR_RWP);
+ }
+ else
+ {
+ base = GICD_CTLR;
+ rwp_mask = BIT(GICD_CTLR_RWP);
+ }
+
+ while (getreg32(base) & rwp_mask)
+ {
+ }
+
+ return 0;
+}
+
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t shift;
+ uint32_t val;
+ unsigned long base = GET_DIST_BASE(intid);
+
+ /* Disable the interrupt */
+
+ putreg32(mask, ICENABLER(base, idx));
+ gic_wait_rwp(intid);
+
+ /* PRIORITYR registers provide byte access */
+
+ putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+
+ /* Interrupt type config */
+
+ if (!GIC_IS_SGI(intid))
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+
+ val = getreg32(ICFGR(base, idx));
+ val &= ~(GICD_ICFGR_MASK << shift);
+ if (flags & IRQ_TYPE_EDGE)
+ {
+ val |= (GICD_ICFGR_TYPE << shift);
+ }
+
+ putreg32(val, ICFGR(base, idx));
+ }
+}
+
+void arm64_gic_irq_enable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+
+ /* Affinity routing is enabled for Non-secure state (GICD_CTLR.ARE_NS
+ * is set to '1' when GIC distributor is initialized) ,so need to set
+ * SPI's affinity, now set it to be the PE on which it is enabled.
+ */
+
+ if (GIC_IS_SPI(intid))
+ {
+ putreg64(MPIDR_TO_CORE(GET_MPIDR()),
+ IROUTER(GET_DIST_BASE(intid), intid));
+ }
+}
+
+void arm64_gic_irq_disable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
+
+ /* poll to ensure write is complete */
+
+ gic_wait_rwp(intid);
+}
+
+bool arm64_gic_irq_is_enabled(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t val;
+
+ val = getreg32(ISENABLER(GET_DIST_BASE(intid), idx));
+
+ return (val & mask) != 0;
+}
+
+unsigned int arm64_gic_get_active(void)
+{
+ int intid;
+
+ /* (Pending -> Active / AP) or (AP -> AP) */
+
+ intid = read_sysreg(ICC_IAR1_EL1);
+
+ return intid;
+}
+
+void arm64_gic_eoi(unsigned int intid)
+{
+ /* Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+
+ __DSB();
+
+ /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
+
+ write_sysreg(intid, ICC_EOIR1_EL1);
+}
+
+int arm64_gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list)
Review Comment:
```suggestion
int arm64_gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
uint16_t target_list)
```
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,619 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
Review Comment:
please use 2 spaces (not 4) and `if (!(__cond)){` should be
```
if (!(__cond)) \
{
```
##########
arch/arm64/src/common/arm64_fpu.h:
##########
@@ -0,0 +1,74 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+struct arm64_cpu_fpu_context
+{
+ /* owner of current CPU's FPU */
+
+ struct tcb_s * fpu_owner;
+
+ struct tcb_s * idle_thread;
Review Comment:
```suggestion
struct tcb_s *idle_thread;
```
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,619 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
+#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one
+ * complete table */
+#define XLAT_TABLE_SIZE (1U << XLAT_TABLE_SIZE_SHIFT)
+
+#define XLAT_TABLE_ENTRY_SIZE_SHIFT 3U /* Each table entry is 8 bytes */
+#define XLAT_TABLE_LEVEL_MAX 3U
+
+#define XLAT_TABLE_ENTRIES_SHIFT \
+ (XLAT_TABLE_SIZE_SHIFT - XLAT_TABLE_ENTRY_SIZE_SHIFT)
+#define XLAT_TABLE_ENTRIES (1U << XLAT_TABLE_ENTRIES_SHIFT)
+
+/* Address size covered by each entry at given translation table level */
+
+#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
+#define L2_XLAT_VA_SIZE_SHIFT \
+ (L3_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L1_XLAT_VA_SIZE_SHIFT \
+ (L2_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+#define L0_XLAT_VA_SIZE_SHIFT \
+ (L1_XLAT_VA_SIZE_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
+
+#define LEVEL_TO_VA_SIZE_SHIFT(level) \
+ (PAGE_SIZE_SHIFT + (XLAT_TABLE_ENTRIES_SHIFT * \
+ (XLAT_TABLE_LEVEL_MAX - (level))))
+
+/* Virtual Address Index within given translation table level */
+
+#define XLAT_TABLE_VA_IDX(va_addr, level) \
+ ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (XLAT_TABLE_ENTRIES - 1))
+
+/* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
+ * For a 4 KB page size,
+ * (va_bits <= 21) - base level 3
+ * (22 <= va_bits <= 30) - base level 2
+ * (31 <= va_bits <= 39) - base level 1
+ * (40 <= va_bits <= 48) - base level 0
+ */
+
+#define GET_XLAT_TABLE_BASE_LEVEL(va_bits) \
+ ((va_bits > L0_XLAT_VA_SIZE_SHIFT) \
+ ? 0U \
+ : (va_bits > L1_XLAT_VA_SIZE_SHIFT) \
+ ? 1U \
+ : (va_bits > L2_XLAT_VA_SIZE_SHIFT) \
+ ? 2U : 3U)
+
+#define XLAT_TABLE_BASE_LEVEL GET_XLAT_TABLE_BASE_LEVEL(CONFIG_ARM64_VA_BITS)
+
+#define GET_NUM_BASE_LEVEL_ENTRIES(va_bits) \
+ (1U << (va_bits - LEVEL_TO_VA_SIZE_SHIFT(XLAT_TABLE_BASE_LEVEL)))
+
+#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
+ CONFIG_ARM64_VA_BITS)
+
+static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
+ NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
+
+static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
+aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));
+
+#if (CONFIG_ARM64_PA_BITS == 48)
+#define TCR_PS_BITS TCR_PS_BITS_256TB
+#elif (CONFIG_ARM64_PA_BITS == 44)
+#define TCR_PS_BITS TCR_PS_BITS_16TB
+#elif (CONFIG_ARM64_PA_BITS == 42)
+#define TCR_PS_BITS TCR_PS_BITS_4TB
+#elif (CONFIG_ARM64_PA_BITS == 40)
+#define TCR_PS_BITS TCR_PS_BITS_1TB
+#elif (CONFIG_ARM64_PA_BITS == 36)
+#define TCR_PS_BITS TCR_PS_BITS_64GB
+#else
+#define TCR_PS_BITS TCR_PS_BITS_4GB
+#endif
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/* NuttX RTOS execution regions with appropriate attributes */
+
+static const struct arm_mmu_region mmu_nxrt_regions[] =
+{
+ /* Mark text segment cacheable,read only and executable */
+
+ MMU_REGION_FLAT_ENTRY("nx_code",
+ (uint64_t)_stext,
+ (uint64_t)_sztext,
+ MT_CODE | MT_SECURE),
+
+ /* Mark rodata segment cacheable, read only and execute-never */
+
+ MMU_REGION_FLAT_ENTRY("nx_rodata",
+ (uint64_t)_srodata,
+ (uint64_t)_szrodata,
+ MT_RODATA | MT_SECURE),
+
+ /* Mark rest of the mirtos execution regions (data, bss, noinit, etc.)
+ * cacheable, read-write
+ * Note: read-write region is marked execute-ever internally
+ */
+
+ MMU_REGION_FLAT_ENTRY("nx_data",
+ (uint64_t)_sdata,
+ (uint64_t)_szdata,
+ MT_NORMAL | MT_RW | MT_SECURE),
+};
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Translation table control register settings */
+
+static uint64_t get_tcr(int el)
+{
+ uint64_t tcr;
+ uint64_t va_bits = CONFIG_ARM64_VA_BITS;
+ uint64_t tcr_ps_bits;
+
+ tcr_ps_bits = TCR_PS_BITS;
+
+ if (el == 1)
+ {
+ tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
+
+ /* TCR_EL1.EPD1: Disable translation table walk for addresses
+ * that are translated using TTBR1_EL1.
+ */
+
+ tcr |= TCR_EPD1_DISABLE;
+ }
+ else
+ {
+ tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
+ }
+
+ tcr |= TCR_T0SZ(va_bits);
+
+ /* Translation table walk is cacheable, inner/outer WBWA and
+ * inner shareable
+ */
+
+ tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+
+ return tcr;
+}
+
+static int pte_desc_type(uint64_t *pte)
+{
+ return *pte & PTE_DESC_TYPE_MASK;
+}
+
+static uint64_t *calculate_pte_index(uint64_t addr, int level)
+{
+ int base_level = XLAT_TABLE_BASE_LEVEL;
+ uint64_t *pte;
+ uint64_t idx;
+ unsigned int i;
+
+ /* Walk through all translation tables to find pte index */
+
+ pte = (uint64_t *)base_xlat_table;
+ for (i = base_level; i <= XLAT_TABLE_LEVEL_MAX; i++)
+ {
+ idx = XLAT_TABLE_VA_IDX(addr, i);
+ pte += idx;
+
+ /* Found pte index */
+
+ if (i == level)
+ {
+ return pte;
+ }
+
+ /* if PTE is not table desc, can't traverse */
+
+ if (pte_desc_type(pte) != PTE_TABLE_DESC)
+ {
+ return NULL;
+ }
+
+ /* Move to the next translation table level */
+
+ pte = (uint64_t *)(*pte & 0x0000fffffffff000);
+ }
+
+ return NULL;
+}
+
+static void set_pte_table_desc(uint64_t *pte, uint64_t *table,
+ unsigned int level)
+{
+#ifdef CONFIG_MMU_DEBUG
+ sinfo("%s", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: [Table] %p\n", pte, table);
+#endif
+
+ /* Point pte to new table */
+
+ *pte = PTE_TABLE_DESC | (uint64_t)table;
+}
+
+static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
+ unsigned int attrs, unsigned int level)
+{
+ uint64_t desc = addr_pa;
+ unsigned int mem_type;
+
+ desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
+
+ /* NS bit for security memory access from secure state */
+
+ desc |= (attrs & MT_NS) ? PTE_BLOCK_DESC_NS : 0;
+
+ /* AP bits for Data access permission */
+
+ desc |= (attrs & MT_RW) ? PTE_BLOCK_DESC_AP_RW : PTE_BLOCK_DESC_AP_RO;
+
+ /* the access flag */
+
+ desc |= PTE_BLOCK_DESC_AF;
+
+ /* memory attribute index field */
+
+ mem_type = MT_TYPE(attrs);
+ desc |= PTE_BLOCK_DESC_MEMTYPE(mem_type);
+
+ switch (mem_type)
+ {
+ case MT_DEVICE_NGNRNE:
+ case MT_DEVICE_NGNRE:
+ case MT_DEVICE_GRE:
+ {
+ /* Access to Device memory and non-cacheable memory are coherent
+ * for all observers in the system and are treated as
+ * Outer shareable, so, for these 2 types of memory,
+ * it is not strictly needed to set shareability field
+ */
+
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+
+ /* Map device memory as execute-never */
+
+ desc |= PTE_BLOCK_DESC_PXN;
+ desc |= PTE_BLOCK_DESC_UXN;
+ break;
+ }
+
+ case MT_NORMAL_NC:
+ case MT_NORMAL:
+ {
+ /* Make Normal RW memory as execute never */
+
+ if ((attrs & MT_RW) || (attrs & MT_EXECUTE_NEVER))
+ {
+ desc |= PTE_BLOCK_DESC_PXN;
+ }
+
+ if (mem_type == MT_NORMAL)
+ {
+ desc |= PTE_BLOCK_DESC_INNER_SHARE;
+ }
+ else
+ {
+ desc |= PTE_BLOCK_DESC_OUTER_SHARE;
+ }
+ }
+ }
+
+#if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE)
+ sinfo("%s ", XLAT_TABLE_LEVEL_SPACE(level));
+ sinfo("%p: ", pte);
+ sinfo("%s ",
+ (mem_type ==
+ MT_NORMAL) ? "MEM" :((mem_type == MT_NORMAL_NC) ? "NC" : "DEV"));
+ sinfo("%s ", (attrs & MT_RW) ? "-RW" : "-RO");
+ sinfo("%s ", (attrs & MT_NS) ? "-NS" : "-S");
+ sinfo("%s ", (attrs & MT_EXECUTE_NEVER) ? "-XN" : "-EXEC");
+ sinfo("\n");
+#endif
+
+ *pte = desc;
+}
+
+/* Returns a new reallocated table */
+
+static uint64_t *new_prealloc_table(void)
+{
+ static unsigned int table_idx;
+
+ __MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
+ "Enough xlat tables not allocated");
Review Comment:
```suggestion
__MMU_ASSERT(table_idx < CONFIG_MAX_XLAT_TABLES,
"Enough xlat tables not allocated");
```
##########
arch/arm64/src/qemu/Kconfig:
##########
@@ -0,0 +1,30 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_CHIP_QEMU
+
+menu "Qemu Virt Chip Selection"
+
+choice
+ prompt "Qemu Core Configuration"
+ default ARCH_CHIP_QEMU_A53
+
+config ARCH_CHIP_QEMU_A53
+ bool "Qemu virtual Processor (cortex-a53)"
+ select ARCH_HAVE_MULTICPU
+ select ARMV8A_HAVE_GICv3
+
+endchoice # Qemu Chip Selection
+
+endmenu # "Qemu Chip Selection"
+
+menu "Qemu Peripheral Selection"
+config QEMU_UART_PL011
+ bool "UART"
+ default n
+ select UART1_SERIALDRIVER
+endmenu # iMX Peripheral Selection
Review Comment:
```suggestion
endmenu # Qemu Peripheral Selection
```
##########
arch/arm64/src/common/arm64_schedulesigaction.c:
##########
@@ -0,0 +1,361 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_schedulesigaction.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "sched/sched.h"
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+#include "irq/irq.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_init_signal_process(struct tcb_s *tcb)
+{
+ struct regs_context *pctx = (struct regs_context *)tcb->xcp.regs;
+ struct regs_context *psigctx;
+ char * stack_ptr = (char *)pctx->sp_elx;
Review Comment:
```suggestion
char *stack_ptr = (char *)pctx->sp_elx;
```
##########
arch/arm64/src/qemu/Kconfig:
##########
@@ -0,0 +1,30 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_CHIP_QEMU
+
+menu "Qemu Virt Chip Selection"
+
+choice
+ prompt "Qemu Core Configuration"
+ default ARCH_CHIP_QEMU_A53
+
+config ARCH_CHIP_QEMU_A53
+ bool "Qemu virtual Processor (cortex-a53)"
+ select ARCH_HAVE_MULTICPU
+ select ARMV8A_HAVE_GICv3
+
+endchoice # Qemu Chip Selection
+
+endmenu # "Qemu Chip Selection"
+
+menu "Qemu Peripheral Selection"
+config QEMU_UART_PL011
+ bool "UART"
+ default n
+ select UART1_SERIALDRIVER
+endmenu # iMX Peripheral Selection
+
+endif # ARCH_CHIP_IMX8
Review Comment:
```suggestion
endif # ARCH_CHIP_QEMU
```
--
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902413704
##########
tools/ci/testlist/other.dat:
##########
@@ -20,3 +20,7 @@
# Sparc-gaisler-elf toolchain doesn't provide macOS binaries
/sparc
-xx3823:nsh
+
+# macOS doesn't have arm64 toolchain
+/arm64
+-Darwin
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,438 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/* Include NuttX-specific IRQ definitions */
+
+#include <nuttx/irq.h>
+
+/* Include chip-specific IRQ definitions (including IRQ numbers) */
+
+#include <arch/chip/irq.h>
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <arch/arch.h>
+#endif
+
+/****************************************************************************
+ * Exception stack frame format:
+ *
+ * x0 ~ x18, x30 (lr), spsr and elr
+ * Corruptible Registers and exception context
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * need to be saved in all exception
+ *
+ * x19 ~ x29, sp_el0, sp_elx
+ * Callee-saved Registers and SP pointer
+ * reference to Armv8-A Instruction Set Architecture
+ * (ARM062-948681440-3280, Issue 1.1), chapter 11 PCS
+ * These registers frame is allocated on stack frame
+ * when a exception is occurred and saved at task switch
+ * or crash exception
+ * check arm64_vectors.S for detail
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Registers and exception context
+ * Note:
+ * REG_EXEC_DEPTH indicate the task's exception depth
+ *
+ ****************************************************************************/
+
+#define REG_X0 (0)
+#define REG_X1 (1)
+#define REG_X2 (2)
+#define REG_X3 (3)
+#define REG_X4 (4)
+#define REG_X5 (5)
+#define REG_X6 (6)
+#define REG_X7 (7)
+#define REG_X8 (8)
+#define REG_X9 (9)
+#define REG_X10 (10)
+#define REG_X11 (11)
+#define REG_X12 (12)
+#define REG_X13 (13)
+#define REG_X14 (14)
+#define REG_X15 (15)
+#define REG_X16 (16)
+#define REG_X17 (17)
+#define REG_X18 (18)
+#define REG_X19 (19)
+#define REG_X20 (20)
+#define REG_X21 (21)
+#define REG_X22 (22)
+#define REG_X23 (23)
+#define REG_X24 (24)
+#define REG_X25 (25)
+#define REG_X26 (26)
+#define REG_X27 (27)
+#define REG_X28 (28)
+#define REG_X29 (29)
+#define REG_X30 (30)
+#define REG_SP_ELX (31)
+#define REG_ELR (32)
+#define REG_SPSR (33)
+#define REG_SP_EL0 (34)
+#define REG_EXE_DEPTH (35)
+#define REG_TPIDR_EL0 (36)
+#define REG_TPIDR_EL1 (37)
+
+/* In Armv8-A Architecture, the stack must align with 16 byte */
+
+#define XCPTCONTEXT_GP_REGS (38)
+#define XCPTCONTEXT_GP_SIZE (8 * XCPTCONTEXT_GP_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * q0 ~ q31(128bit), fpsr, fpcr
+ * armv8 fpu registers and context
+ * With CONFIG_ARCH_FPU is enabled, armv8 fpu registers context
+ * is allocated on stack frame at exception and store/restore
+ * when switching FPU context
+ * check arm64_fpu.c for detail
+ *
+ ****************************************************************************/
+
+/* 128bit registers */
+
+#define FPU_REG_Q0 (0)
+#define FPU_REG_Q1 (1)
+#define FPU_REG_Q2 (2)
+#define FPU_REG_Q3 (3)
+#define FPU_REG_Q4 (4)
+#define FPU_REG_Q5 (5)
+#define FPU_REG_Q6 (6)
+#define FPU_REG_Q7 (7)
+#define FPU_REG_Q8 (8)
+#define FPU_REG_Q9 (9)
+#define FPU_REG_Q10 (10)
+#define FPU_REG_Q11 (11)
+#define FPU_REG_Q12 (12)
+#define FPU_REG_Q13 (13)
+#define FPU_REG_Q14 (14)
+#define FPU_REG_Q15 (15)
+#define FPU_REG_Q16 (16)
+#define FPU_REG_Q17 (17)
+#define FPU_REG_Q18 (18)
+#define FPU_REG_Q19 (19)
+#define FPU_REG_Q20 (20)
+#define FPU_REG_Q21 (21)
+#define FPU_REG_Q22 (22)
+#define FPU_REG_Q23 (23)
+#define FPU_REG_Q24 (24)
+#define FPU_REG_Q25 (25)
+#define FPU_REG_Q26 (26)
+#define FPU_REG_Q27 (27)
+#define FPU_REG_Q28 (28)
+#define FPU_REG_Q29 (29)
+#define FPU_REG_Q30 (30)
+#define FPU_REG_Q31 (31)
+
+/* 32 bit registers
+ */
+#define FPU_REG_FPSR (0)
+#define FPU_REG_FPCR (1)
+
+/* FPU registers(Q0~Q31, 128bit): 32x2 = 64
+ * FPU FPSR/SPSR(32 bit) : 1
+ * FPU TRAP: 1
+ * 64 + 1 + 1 = 66
+ */
+#define ARM64_FPU_REGS (66)
+#else
+#define ARM64_FPU_REGS (0)
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r903556019
##########
arch/arm64/include/spinlock.h:
##########
@@ -0,0 +1,90 @@
+/****************************************************************************
+ * arch/arm64/include/spinlock.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_SPINLOCK_H
+#define __ARCH_ARM64_INCLUDE_SPINLOCK_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Spinlock states */
+
+#define SP_UNLOCKED 0 /* The Un-locked state */
+#define SP_LOCKED 1 /* The Locked state */
+
+/* Memory barriers for use with NuttX spinlock logic
+ *
+ * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
+ * explicit memory accesses that appear in program order before the DMB
+ * instruction are observed before any explicit memory accesses that appear
+ * in program order after the DMB instruction. It does not affect the
+ * ordering of any other instructions executing on the processor
+ *
+ * dmb st - Data memory barrier. Wait for stores to complete.
+ *
+ * Data Synchronization Barrier (DSB) acts as a special kind of memory
+ * barrier. No instruction in program order after this instruction executes
+ * until this instruction completes. This instruction completes when: (1) All
+ * explicit memory accesses before this instruction complete, and (2) all
+ * Cache, Branch predictor and TLB maintenance operations before this
+ * instruction complete.
+ *
+ * dsb sy - Data syncrhonization barrier. Assures that the CPU waits until
Review Comment:
done
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[GitHub] [incubator-nuttx] pkarashchenko commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1166487810
@qinwei2004 you can fix only critical items like `assert(1)` and `psci_fn` and other style issues can be fixed in the next PR
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906924373
##########
arch/arm64/src/qemu/qemu_serial.c:
##########
@@ -0,0 +1,856 @@
+/***************************************************************************
+ * arch/arm64/src/qemu/qemu_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/spinlock.h>
+#include <nuttx/init.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/serial/serial.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "qemu_serial.h"
+#include "arm64_arch_timer.h"
+#include "qemu_boot.h"
+#include "arm64_gic.h"
+
+#ifdef USE_SERIALDRIVER
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Which UART with be tty0/console and which tty1-4? The console will
+ * always be ttyS0. If there is no console then will use the lowest
+ * numbered UART.
+ */
+
+/* First pick the console and ttys0. This could be any of UART1-5 */
+
+#if defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1port /* UART1 is console */
+# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+#endif
+
+/* UART PL011 register map structure */
+
+struct pl011_regs
+{
+ uint32_t dr; /* data register */
+ union
+ {
+ uint32_t rsr;
+ uint32_t ecr;
+ };
+
+ uint32_t reserved_0[4];
+ uint32_t fr; /* flags register */
+ uint32_t reserved_1;
+ uint32_t ilpr;
+ uint32_t ibrd;
+ uint32_t fbrd;
+ uint32_t lcr_h;
+ uint32_t cr;
+ uint32_t ifls;
+ uint32_t imsc;
+ uint32_t ris;
+ uint32_t mis;
+ uint32_t icr;
+ uint32_t dmacr;
+};
+
+struct pl011_config
+{
+ volatile struct pl011_regs *uart;
+ uint32_t sys_clk_freq;
+};
+
+/* Device data structure */
+
+struct pl011_data
+{
+ uint32_t baud_rate;
+ bool sbsa;
+};
+
+struct pl011_uart_port_s
+{
+ struct pl011_data data;
+ struct pl011_config config;
+ unsigned int irq_num;
+ int is_console;
+};
+
+#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
+
+/* PL011 Uart Flags Register */
+#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
+#define PL011_FR_DSR BIT(1) /* data set ready - inverted
+ */
+#define PL011_FR_DCD BIT(2) /* data carrier detect -
+ * inverted */
+#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
+#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
+#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
+#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
+#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
+#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
+
+/* PL011 Integer baud rate register */
+#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
+
+/* PL011 Fractional baud rate register */
+#define PL011_FBRD_BAUD_DIVFRAC 0x3f
+#define PL011_FBRD_WIDTH 6u
+
+/* PL011 Receive status register / error clear register */
+#define PL011_RSR_ECR_FE BIT(0) /* framing error */
+#define PL011_RSR_ECR_PE BIT(1) /* parity error */
+#define PL011_RSR_ECR_BE BIT(2) /* break error */
+#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
+
+#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
+ PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
+
+/* PL011 Line Control Register */
+#define PL011_LCRH_BRK BIT(0) /* send break */
+#define PL011_LCRH_PEN BIT(1) /* enable parity */
+#define PL011_LCRH_EPS BIT(2) /* select even parity */
+#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
+#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
+#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
+#define PL011_LCRH_WLEN_WIDTH 2
+#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
+
+#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
+
+#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
+ PL011_LCRH_SPS | \
+ PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \
+ PL011_LCRH_WLEN_SHIFT))
+
+#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
+#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
+#define PL011_LCRH_PARITY_NONE (0)
+
+/* PL011 Control Register */
+#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
+#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
+#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
+#define PL011_CR_LBE BIT(7) /* loop back enable */
+#define PL011_CR_TXE BIT(8) /* transmit enable */
+#define PL011_CR_RXE BIT(9) /* receive enable */
+#define PL011_CR_DTR BIT(10) /* data transmit ready */
+#define PL011_CR_RTS BIT(11) /* request to send */
+#define PL011_CR_Out1 BIT(12)
+#define PL011_CR_Out2 BIT(13)
+#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable
+ */
+#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable
+ */
+
+/* PL011 Interrupt Fifo Level Select Register */
+#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */
+#define PL011_IFLS_TXIFLSEL_WIDTH 3
+#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */
+#define PL011_IFLS_RXIFLSEL_WIDTH 3
+
+/* PL011 Interrupt Mask Set/Clear Register */
+#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
+#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
+#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
+#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
+#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
+#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
+#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt
+ * mask */
+#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt
+ * mask */
+#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask
+ */
+#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask
+ */
+#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt
+ * mask */
+
+#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_OEIM)
+
+#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
+ PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
+ PL011_IMSC_RIMIM | \
+ PL011_IMSC_CTSMIM | \
+ PL011_IMSC_DCDMIM | \
+ PL011_IMSC_DSRMIM | \
+ PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
+ PL011_IMSC_RTIM)
+
+static void pl011_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr |= PL011_CR_UARTEN;
+}
+
+static void pl011_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->cr &= ~PL011_CR_UARTEN;
+}
+
+static void pl011_enable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h |= PL011_LCRH_FEN;
+}
+
+static void pl011_disable_fifo(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->lcr_h &= ~PL011_LCRH_FEN;
+}
+
+static int pl011_set_baudrate(const struct pl011_uart_port_s *sport,
+ uint32_t clk, uint32_t baudrate)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* Avoiding float calculations, bauddiv is left shifted by 6 */
+
+ uint64_t bauddiv =
+ (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U);
+
+ /* Valid bauddiv value
+ * uart_clk (min) >= 16 x baud_rate (max)
+ * uart_clk (max) <= 16 x 65535 x baud_rate (min)
+ */
+
+ if ((bauddiv < (1u << PL011_FBRD_WIDTH)) ||
+ (bauddiv > (65535u << PL011_FBRD_WIDTH)))
+ {
+ return -EINVAL;
+ }
+
+ config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
+ config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
+
+ __DMB();
+
+ /* In order to internally update the contents of ibrd or fbrd, a
+ * lcr_h write must always be performed at the end
+ * ARM DDI 0183F, Pg 3-13
+ */
+
+ config->uart->lcr_h = config->uart->lcr_h;
+
+ return 0;
+}
+
+static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~PL011_IMSC_TXIM;
+}
+
+static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
+}
+
+static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
+}
+
+static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+
+ /* check for TX FIFO empty */
+
+ return config->uart->fr & PL011_FR_TXFE;
+}
+
+static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport)
+{
+ const struct pl011_config *config = &sport->config;
+ const struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_RXIM) &&
+ (!(config->uart->fr & PL011_FR_RXFE));
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txready
+ *
+ * Description:
+ * Return true if the tranmsit fifo is not full
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txready(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
+ {
+ return false;
+ }
+
+ return (config->uart->imsc & PL011_IMSC_TXIM) &&
+ pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txempty
+ *
+ * Description:
+ * Return true if the transmit fifo is empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_txempty(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport = (struct pl011_uart_port_s *)dev->priv;
+
+ return pl011_irq_tx_complete(sport);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_send
+ *
+ * Description:
+ * This method will send one byte on the UART
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_send(struct uart_dev_s *dev, int ch)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+
+ config->uart->dr = ch;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxavailable
+ *
+ * Description:
+ * Return true if the receive fifo is not empty
+ *
+ ***************************************************************************/
+
+static bool qemu_pl011_rxavailable(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+
+ if (!data->sbsa &&
+ (!(config->uart->cr & PL011_CR_UARTEN) ||
+ !(config->uart->cr & PL011_CR_RXE)))
+ {
+ return false;
+ }
+
+ return (config->uart->fr & PL011_FR_RXFE) == 0U;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_rx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_rx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (enable)
+ {
+ pl011_irq_tx_enable(sport);
+ }
+ else
+ {
+ pl011_irq_tx_disable(sport);
+ }
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ unsigned int rx;
+
+ rx = config->uart->dr;
+
+ *status = 0;
+
+ return rx;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ * for current qemu configure,
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ int ret = OK;
+
+ switch (cmd)
+ {
+ case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+ case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+ default:
+ {
+ ret = -ENOTTY;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/***************************************************************************
+ * Name: qemu_pl011_irq_handler (and front-ends)
+ *
+ * Description:
+ * This is the common UART interrupt handler. It should cal
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_irq_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct pl011_uart_port_s *sport;
+
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
+ sport = (struct pl011_uart_port_s *)dev->priv;
+
+ if (pl011_irq_rx_ready(sport))
+ {
+ uart_recvchars(dev);
+ }
+
+ if (qemu_pl011_txready(dev))
+ {
+ uart_xmitchars(dev);
+ }
+
+ return OK;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_detach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+
+ up_disable_irq(sport->irq_num);
+ irq_detach(sport->irq_num);
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode.
+ * This method is called when the serial port is opened.
+ * Normally, this is just after the setup() method is called,
+ * however, the serial console may operate in
+ * a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method
+ * (unless the hardware supports multiple levels of interrupt
+ * enabling). The RX and TX interrupts are not enabled until
+ * the txint() and rxint() methods are called.
+ *
+ ***************************************************************************/
+
+static int qemu_pl011_attach(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s * sport;
+ struct pl011_data * data;
+ int ret;
+
+ sport = (struct pl011_uart_port_s *)dev->priv;
+ data = &sport->data;
+
+ ret = irq_attach(sport->irq_num, qemu_pl011_irq_handler, dev);
+ arm64_gic_irq_set_priority(sport->irq_num, IRQ_TYPE_LEVEL, 0);
+
+ if (ret == OK)
+ {
+ up_enable_irq(sport->irq_num);
+ }
+ else
+ {
+ sinfo("error ret=%d\n", ret);
+ }
+
+ if (!data->sbsa)
+ {
+ pl011_enable(sport);
+ }
+ return ret;
+}
+
+/***************************************************************************
+ * Name: qemu_pl011_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ***************************************************************************/
+
+static void qemu_pl011_shutdown(struct uart_dev_s *dev)
+{
+ sinfo("%s: call unexpected\n", __func__);
+}
+
+static int qemu_pl011_setup(struct uart_dev_s *dev)
+{
+ struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv;
+ const struct pl011_config *config = &sport->config;
+ struct pl011_data *data = &sport->data;
+ int ret;
+ uint32_t lcrh;
+ irqstate_t i_flags;
+
+ i_flags = up_irq_save();
+
+ /* If working in SBSA mode, we assume that UART is already configured,
+ * or does not require configuration at all (if UART is emulated by
+ * virtualization software).
+ */
+
+ if (!data->sbsa)
+ {
+ /* disable the uart */
+
+ pl011_disable(sport);
+ pl011_disable_fifo(sport);
+
+ /* Set baud rate */
+
+ ret = pl011_set_baudrate(sport, config->sys_clk_freq,
+ data->baud_rate);
+ if (ret != 0)
+ {
+ up_irq_restore(i_flags);
+ return ret;
+ }
+
+ /* Setting the default character format */
+
+ lcrh = config->uart->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
+ lcrh &= ~(BIT(0) | BIT(7));
+ lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
+ config->uart->lcr_h = lcrh;
+
+ /* Enabling the FIFOs */
+
+ pl011_enable_fifo(sport);
+ }
+
+ /* initialize all IRQs as masked */
+
+ config->uart->imsc = 0U;
+ config->uart->icr = PL011_IMSC_MASK_ALL;
+
+ if (!data->sbsa)
+ {
+ config->uart->dmacr = 0U;
+ __ISB();
+ config->uart->cr &= ~(BIT(14) | BIT(15) | BIT(1));
+ config->uart->cr |= PL011_CR_RXE | PL011_CR_TXE;
+ __ISB();
+ }
+
+ up_irq_restore(i_flags);
+
+ return 0;
+}
+
+/***************************************************************************
+ * Private Data
+ ***************************************************************************/
+
+/* Serial driver UART operations */
+
+static const struct uart_ops_s g_uart_ops =
+{
+ .setup = qemu_pl011_setup,
+ .shutdown = qemu_pl011_shutdown,
+ .attach = qemu_pl011_attach,
+ .detach = qemu_pl011_detach,
+ .ioctl = qemu_pl011_ioctl,
+ .receive = qemu_pl011_receive,
+ .rxint = qemu_pl011_rxint,
+ .rxavailable = qemu_pl011_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = NULL,
+#endif
+ .send = qemu_pl011_send,
+ .txint = qemu_pl011_txint,
+ .txready = qemu_pl011_txready,
+ .txempty = qemu_pl011_txempty,
+};
+
+/* This describes the state of the uart1 port. */
+
+static struct pl011_uart_port_s g_uart1priv =
+{
+ .data =
+ {
+ .baud_rate = CONFIG_UART1_BAUD, .sbsa = false,
Review Comment:
Oh, I use /tools/uncrustify.cfg in VSCode with uncrustify extention,
but format like this ugly style
thanks
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902287077
##########
tools/ci/testlist/other.dat:
##########
@@ -20,3 +20,7 @@
# Sparc-gaisler-elf toolchain doesn't provide macOS binaries
/sparc
-xx3823:nsh
+
+# macOS doesn't have arm64 toolchain
+/arm64
+-Darwin
Review Comment:
```suggestion
-Darwin
```
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1170367631
@pkarashchenko @qinwei2004 I will give the feedback in the next couple days.
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1166193579
> In first commit log, s/Cotex-a53/Cortex-a53/
Done
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r903554794
##########
arch/arm64/include/arch.h:
##########
@@ -0,0 +1,145 @@
+/****************************************************************************
+ * arch/arm64/include/arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_ARCH_H
+#define __ARCH_ARM64_INCLUDE_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <nuttx/pgalloc.h>
+# include <nuttx/addrenv.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+#if CONFIG_MM_PGSIZE != 4096
+# error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
+#endif
+
+#endif /* CONFIG_ARCH_ADDRENV */
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsp
+ ****************************************************************************/
+
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+/* The task group resources are retained in a single structure, task_group_s
+ * that is defined in the header file nuttx/include/nuttx/sched.h. The type
+ * group_addrenv_t must be defined by platform specific logic in
+ * nuttx/arch/<architecture>/include/arch.h.
+ *
+ * These tables would hold the physical address of the level 2 page tables.
+ * All would be initially NULL and would not be backed up with physical
+ * memory until mappings in the level 2 page table are required.
+ */
+
+struct group_addrenv_s
+{
+ /* Level 1 page table entries for each group section */
+
+ uintptr_t *text[ARCH_TEXT_NSECTS];
+ uintptr_t *data[ARCH_DATA_NSECTS];
+#ifdef CONFIG_BUILD_KERNEL
+ uintptr_t *heap[ARCH_HEAP_NSECTS];
+#ifdef CONFIG_MM_SHM
+ uintptr_t *shm[ARCH_SHM_NSECTS];
+#endif
+
+ /* Initial heap allocation (in bytes). This exists only provide an
+ * indirect path for passing the size of the initial heap to the heap
+ * initialization logic. These operations are separated in time and
+ * architecture. REVISIT: I would like a better way to do this.
+ */
+
+ size_t heapsize;
+#endif
+};
+
+typedef struct group_addrenv_s group_addrenv_t;
+
+/* This type is used when the OS needs to temporarily instantiate a
+ * different address environment. Used in the implementation of
+ *
+ * int up_addrenv_select(group_addrenv_t addrenv, save_addrenv_t *oldenv);
+ * int up_addrenv_restore(save_addrenv_t oldenv);
+ *
+ * In this case, the saved valued in the L1 page table are returned
Review Comment:
done
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r903553735
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H
Review Comment:
done
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r920691903
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,569 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#ifndef __ASSEMBLY__
+ #include <stdint.h>
+ #include <inttypes.h>
+ #define BIT(n) (UINT32_C(1) << (n))
+ #define BIT64(n) (UINT64_C(1) << (n))
+#else
+ #define BIT(n) ((1UL) << (n))
+ #define BIT64(n) ((1ULL) << (n))
+#endif
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+#define DAIFSET_FIQ_BIT BIT(0)
+#define DAIFSET_IRQ_BIT BIT(1)
+#define DAIFSET_ABT_BIT BIT(2)
+#define DAIFSET_DBG_BIT BIT(3)
+
+#define DAIFCLR_FIQ_BIT BIT(0)
+#define DAIFCLR_IRQ_BIT BIT(1)
+#define DAIFCLR_ABT_BIT BIT(2)
+#define DAIFCLR_DBG_BIT BIT(3)
+
+#define DAIF_FIQ_BIT BIT(6)
+#define DAIF_IRQ_BIT BIT(7)
+#define DAIF_ABT_BIT BIT(8)
+#define DAIF_DBG_BIT BIT(9)
+
+#define DAIF_MASK (0xf << 6)
+
+/* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ *
+ * SCTLR_EL1: System Control Register (EL1)
+ * SCTLR_EL2: System Control Register (EL2)
+ * SCTLR_EL3: System Control Register (EL3)
+ *
+ */
+
+#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(20) | BIT(11))
+
+#define SCTLR_M_BIT BIT(0)
+#define SCTLR_A_BIT BIT(1)
+#define SCTLR_C_BIT BIT(2)
+#define SCTLR_SA_BIT BIT(3)
+#define SCTLR_I_BIT BIT(12)
+
+/* SPSR M[3:0] define
+ *
+ * Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ * SPSR_EL1: Saved Program Status Register (EL1)
+ * SPSR_EL2: Saved Program Status Register (EL2)
+ * SPSR_EL3: Saved Program Status Register (EL3)
+ *
+ * reference to Programmer’s Guide for ARMv8-A
+ * (ARM DEN0024A, ID050815 ), 4.1.2 Stack pointer
+ *
+ * The T suffix, indicates use of the SP_EL0 stack pointer.
+ * The H suffix, indicates use of the SP_ELx stack pointer.
+ *
+ */
+
+#define SPSR_DAIF_SHIFT (6)
+#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE_EL0T (0x0)
+#define SPSR_MODE_EL1T (0x4)
+#define SPSR_MODE_EL1H (0x5)
+#define SPSR_MODE_EL2T (0x8)
+#define SPSR_MODE_EL2H (0x9)
+#define SPSR_MODE_MASK (0xf)
+
+/* CurrentEL: Current Exception Level */
+
+#define MODE_EL_SHIFT (0x2)
+#define MODE_EL_MASK (0x3)
+
+#define MODE_EL3 (0x3)
+#define MODE_EL2 (0x2)
+#define MODE_EL1 (0x1)
+#define MODE_EL0 (0x0)
+
+/* struct arm64_boot_params member offset for assembly code
+ * struct is defined at arm64_cpustart.c
+ */
+
+#define BOOT_PARAM_MPID 0
+#define BOOT_PARAM_SP 8
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MAX
+# define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+# define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
+
+/* MPIDR_EL1, Multiprocessor Affinity Register */
+
+#define MPIDR_AFFLVL_MASK (0xff)
+
+#define MPIDR_AFF0_SHIFT (0)
+#define MPIDR_AFF1_SHIFT (8)
+#define MPIDR_AFF2_SHIFT (16)
+#define MPIDR_AFF3_SHIFT (32)
+
+#define MPIDR_AFFLVL(mpidr, aff_level) \
+ (((mpidr) >> MPIDR_AFF ## aff_level ## _SHIFT) & MPIDR_AFFLVL_MASK)
+
+#define GET_MPIDR() read_sysreg(mpidr_el1)
+#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL((mpidr), 0)
+#define IS_PRIMARY_CORE() (!MPIDR_TO_CORE(GET_MPIDR()))
+
+/* System register interface to GICv3 */
+
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
+#define ICC_SGI1R S3_0_C12_C11_5
+#define ICC_SRE_EL1 S3_0_C12_C12_5
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_RPR_EL1 S3_0_C12_C11_3
+#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
+#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
+#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
+#define ICC_IAR0_EL1 S3_0_C12_C8_0
+#define ICC_IAR1_EL1 S3_0_C12_C12_0
+#define ICC_EOIR0_EL1 S3_0_C12_C8_1
+#define ICC_EOIR1_EL1 S3_0_C12_C12_1
+#define ICC_SGI0R_EL1 S3_0_C12_C11_7
+
+/* register constants */
+#define ICC_SRE_ELX_SRE_BIT BIT(0)
+#define ICC_SRE_ELX_DFB_BIT BIT(1)
+#define ICC_SRE_ELX_DIB_BIT BIT(2)
+#define ICC_SRE_EL3_EN_BIT BIT(3)
+
+/* ICC SGI macros */
+#define SGIR_TGT_MASK (0xffff)
+#define SGIR_AFF1_SHIFT (16)
+#define SGIR_AFF2_SHIFT (32)
+#define SGIR_AFF3_SHIFT (48)
+#define SGIR_AFF_MASK (0xf)
+#define SGIR_INTID_SHIFT (24)
+#define SGIR_INTID_MASK (0xf)
+#define SGIR_IRM_SHIFT (40)
+#define SGIR_IRM_MASK (0x1)
+#define SGIR_IRM_TO_AFF (0)
+#define SGIR_IRM_TO_ALL (1)
+
+#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
+ ((((uint64_t)(_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
+ (((uint64_t)(_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
+ (((uint64_t)(_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
+ (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
+ (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
+ ((_tgt) & SGIR_TGT_MASK))
+
+/* CPTR_EL2, Architectural Feature Trap Register (EL2) */
+
+#define CPTR_EZ_BIT BIT(8)
+#define CPTR_TFP_BIT BIT(10)
+#define CPTR_TTA_BIT BIT(20)
+#define CPTR_TCPAC_BIT BIT(31)
+#define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
+
+/* CPACR_EL1, Architectural Feature Access Control Register */
+#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
+
+/* SCR_EL3, Secure Configuration Register */
+#define SCR_NS_BIT BIT(0)
+#define SCR_IRQ_BIT BIT(1)
+#define SCR_FIQ_BIT BIT(2)
+#define SCR_EA_BIT BIT(3)
+#define SCR_SMD_BIT BIT(7)
+#define SCR_HCE_BIT BIT(8)
+#define SCR_RW_BIT BIT(10)
+#define SCR_ST_BIT BIT(11)
+#define SCR_RES1 (BIT(4) | BIT(5))
+
+/* HCR_EL2, Hypervisor Configuration Register */
+
+#define HCR_FMO_BIT BIT(3)
+#define HCR_IMO_BIT BIT(4)
+#define HCR_AMO_BIT BIT(5)
+#define HCR_RW_BIT BIT(31)
+
+/* CNTHCTL_EL2 bits definitions */
+
+#define CNTHCTL_EL2_EL1PCEN_EN BIT(1)
+#define CNTHCTL_EL2_EL1PCTEN_EN BIT(0)
+
+/* CNTV_CVAL, Counter-timer Virtual Timer CompareValue register
+ * CNTV_CTL, Counter-timer Virtual Timer Control register
+ */
+
+#define CNTV_CTL_ENABLE_BIT BIT(0)
+#define CNTV_CTL_IMASK_BIT BIT(1)
+
+/* Maximum numbers of translation tables
+ * This option specifies the maximum numbers of translation tables
+ * excluding the base translation table. Based on this, translation
+ * tables are allocated at compile time and used at runtime as needed.
+ * If the runtime need exceeds preallocated numbers of translation
+ * tables, it will result in assert. Number of translation tables
+ * required is decided based on how many discrete memory regions
+ * (both normal and device memory) are present on given platform and
+ * how much granularity is required while assigning attributes
+ * to these memory regions.
+ */
+
+#define CONFIG_MAX_XLAT_TABLES 7
+
+/* Virtual address space size
+ * Allows choosing one of multiple possible virtual address
+ * space sizes. The level of translation table is determined by
+ * a combination of page size and virtual address space size.
+ *
+ * The choice could be: 32, 36, 42, 48
+ */
+
+#define CONFIG_ARM64_VA_BITS 36
+
+/* Physical address space size
+ * Choose the maximum physical address range that the kernel will support.
+ *
+ * The choice could be: 32, 36, 42, 48
+ */
+
+#define CONFIG_ARM64_PA_BITS 36
+
+#define L1_CACHE_SHIFT (6)
+#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+
+/****************************************************************************
+ * armv8 fpu registers and context
+ ****************************************************************************/
+
+struct fpu_reg
+{
+ __int128 q[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ uint64_t fpu_trap;
+};
+
+#endif
+
+/****************************************************************************
+ * Registers and exception context
+ ****************************************************************************/
+
+struct regs_context
+{
+ uint64_t regs[31]; /* x0~x30 */
+ uint64_t sp_elx;
+ uint64_t elr;
+ uint64_t spsr;
+ uint64_t sp_el0;
+ uint64_t exe_depth;
+ uint64_t tpidr_el0;
+ uint64_t tpidr_el1;
+};
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/* See Arm® Architecture Reference Manual
+ * ARM DDI 0487E.a C6.2.81
+ */
+
+static inline void __DSB(void)
+{
+ __asm__ volatile ("dsb sy" : : : "memory");
+}
+
+/* See Arm® Architecture Reference Manual
+ * ARM DDI 0487E.a C6.2.79
+ */
+
+static inline void __DMB(void)
+{
+ __asm__ volatile ("dmb sy" : : : "memory");
+}
+
+/* See Arm® Architecture Reference Manual
+ * ARM DDI 0487E.a C6.2.96
+ */
+
+static inline void __ISB(void)
+{
+ __asm__ volatile ("isb" : : : "memory");
+}
Review Comment:
I perfer to add prefix ARM64_ to define.
please check
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,254 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ UNUSED(regs);
+ UNUSED(arg);
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#else
+
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+ uint64_t next_cycle;
+
+ UNUSED(irq);
+ UNUSED(regs);
+ UNUSED(arg);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ next_cycle = last_cycle + cycle_per_tick;
+
+ if ((uint64_t)(next_cycle - curr_cycle) < MIN_DELAY)
+ {
+ next_cycle += cycle_per_tick;
+ }
+
+ arm64_arch_timer_set_compare(next_cycle);
+ arm64_arch_timer_set_irq_mask(false);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+/* Notes:
+ *
+ * The origin design for ARMv8-A timer is assigned private timer to
+ * every PE(CPU core), the ARM_ARCH_TIMER_IRQ is a PPI so it's
+ * should be enable at every core.
+ *
+ * But for NuttX, it's design only for primary core to handle timer
+ * interrupt and call nxsched_process_timer at timer tick mode.
+ * So we need only enable timer for primary core
+ *
+ * IMX6 use GPT which is a SPI rather than generic timer to handle
+ * timer interrupt
+ */
+
+void arm64_smp_timer_init(void)
+{
+ uint64_t curr_cycle;
+
+ /* set the initial status of timer0 of each secondary core */
+
+ curr_cycle = arm64_arch_timer_count();
+
+ arm64_arch_timer_set_compare(curr_cycle + cycle_per_tick);
+ arm64_arch_timer_enable(true);
+ up_enable_irq(ARM_ARCH_TIMER_IRQ);
+ arm64_arch_timer_set_irq_mask(false);
+}
+
+#endif
+
+uint64_t arm64_counter_read(void)
+{
+ return arm64_arch_timer_count();
+}
+
+void arm64_timer_delay(long mini_sec)
+{
+ unsigned int timeout;
+ volatile unsigned int new_counter;
Review Comment:
Oh, arm64_timer_delay is a very early version to used at arm64_assert.c, only for debug propose
I think I perfer to use up_mdelay instead
Thanks for check
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r906697466
##########
arch/arm64/src/common/arm64_boot.c:
##########
@@ -0,0 +1,185 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/init.h>
+
+#include "arm64_internal.h"
+#include "arm64_arch.h"
+
+extern void *_vector_table[];
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_boot_el3_init(void)
+{
+ uint64_t reg;
+
+ /* Setup vector table */
+
+ write_sysreg((uint64_t)_vector_table, vbar_el3);
+ __ISB();
+
+ reg = 0U; /* Mostly RES0 */
+ reg &= ~(CPTR_TTA_BIT | /* Do not trap sysreg accesses */
+ CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
+ CPTR_TCPAC_BIT); /* Do not trap CPTR_EL2 / CPACR_EL1 accesses
+ */
+
+ /* CPTR_EL3, Architectural Feature Trap Register (EL3) */
+
+ write_sysreg(reg, cptr_el3);
+
+ reg = 0U; /* Reset */
+ reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */
+ reg |= (SCR_RES1 | /* RES1 */
+ SCR_RW_BIT | /* EL2 execution state is AArch64 */
+ SCR_ST_BIT | /* Do not trap EL1 accesses to timer */
+ SCR_HCE_BIT | /* Do not trap HVC */
+ SCR_SMD_BIT); /* Do not trap SMC */
+ write_sysreg(reg, scr_el3);
+
+ reg = read_sysreg(ICC_SRE_EL3);
+ reg |= (ICC_SRE_ELX_DFB_BIT | /* Disable FIQ bypass */
+ ICC_SRE_ELX_DIB_BIT | /* Disable IRQ bypass */
+ ICC_SRE_ELX_SRE_BIT | /* System register interface is used */
+ ICC_SRE_EL3_EN_BIT); /* Enables lower Exception level access to
+ * ICC_SRE_EL1 */
+ write_sysreg(reg, ICC_SRE_EL3);
+
+ __ISB();
+}
+
+void arm64_boot_el3_get_next_el(uint64_t switch_addr)
+{
+ uint64_t spsr;
+
+ write_sysreg(switch_addr, elr_el3);
+
+ /* Mask the DAIF */
+
+ spsr = SPSR_DAIF_MASK;
+ spsr |= SPSR_MODE_EL2T;
+
+ write_sysreg(spsr, spsr_el3);
+}
+
+void arm64_boot_el2_init(void)
+{
+ uint64_t reg;
+
+ reg = read_sysreg(sctlr_el2);
+ reg |= (SCTLR_EL2_RES1 | /* RES1 */
+ SCTLR_I_BIT | /* Enable i-cache */
+ SCTLR_SA_BIT); /* Enable SP alignment check */
+ write_sysreg(reg, sctlr_el2);
+
+ reg = read_sysreg(hcr_el2);
+ reg |= HCR_RW_BIT; /* EL1 Execution state is AArch64 */
+ write_sysreg(reg, hcr_el2);
+
+ reg = 0U; /* RES0 */
+ reg |= CPTR_EL2_RES1; /* RES1 */
+ reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */
+ CPTR_TCPAC_BIT); /* Do not trap CPACR_EL1 accesses */
+ write_sysreg(reg, cptr_el2);
+
+ /* Enable EL1 access to timers */
+
+ reg = read_sysreg(cnthctl_el2);
+ reg |= (CNTHCTL_EL2_EL1PCEN_EN | CNTHCTL_EL2_EL1PCTEN_EN);
+ write_sysreg(reg, cnthctl_el2);
+
+ zero_sysreg(cntvoff_el2); /* Set 64-bit virtual timer offset to 0 */
+
+#ifdef CONFIG_ARCH_ARMV8R
+ zero_sysreg(cnthps_ctl_el2);
+#else
+ zero_sysreg(cnthp_ctl_el2);
+#endif
+
+ /* Enable this if/when we use the hypervisor timer.
+ * write_cnthp_cval_el2(~(uint64_t)0);
+ */
+
+ __ISB();
+}
+
+void arm64_boot_el1_init(void)
+{
+ uint64_t reg;
+
+ /* Setup vector table */
+
+ write_sysreg((uint64_t)_vector_table, vbar_el1);
+ __ISB();
+
+ reg = 0U; /* RES0 */
+ reg |= CPACR_EL1_FPEN_NOTRAP; /* Do not trap NEON/SIMD/FP initially */
+
+ /* TODO: CONFIG_FLOAT_*_FORBIDDEN */
+
+ write_sysreg(reg, cpacr_el1);
+
+ reg = read_sysreg(sctlr_el1);
+ reg |= (SCTLR_EL1_RES1 | /* RES1 */
+ SCTLR_I_BIT | /* Enable i-cache */
+ SCTLR_SA_BIT); /* Enable SP alignment check */
+ write_sysreg(reg, sctlr_el1);
+
+ write_sysreg((~(uint64_t)0), cntv_cval_el0);
+
+ /* Enable these if/when we use the corresponding timers.
+ * write_cntp_cval_el0(~(uint64_t)0);
+ * write_cntps_cval_el1(~(uint64_t)0);
+ */
+
+ __ISB();
+}
+
+/* These simple memset alternatives are necessary
+ * as the function at libc is depend on the MMU
+ * to be active.
+ */
+
+static void boot_early_memset(void *dst, int c, size_t n)
+{
+ uint8_t *d = dst;
+
+ while (n--)
+ {
+ *d++ = c;
+ }
+}
+
+void arm64_boot_primary_c_routine(void)
+{
+ boot_early_memset(_sbss, 0, _ebss - _sbss);
Review Comment:
add define _START_BSS and _END_BSS
in C level, we cannot make sure the operation will be alignment in any case or optimization level. So operating by byte is a very conservative but safety approach.
assembly code can make the guarantee. Actually at the early single core version, I clear BSS in arm64_head.S. but for SMP, the operation of clear BSS can only be done by primary core, it's a little complicated to clear BSS at arm64_head.S for SMP case, so I move the operation to C level
if have any need for booting performance requirement, maybe it's a optimizing point to move clear BSS to assembly code. i maybe rework it at future
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915024106
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
@xiaoxiang781216 Maybe we don't need FAR keyword here?
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r912773548
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
Review Comment:
remove the unused code
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
+#INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_INCDIR)$(DELIM)}
Review Comment:
remove
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
+#INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_INCDIR)$(DELIM)}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
+
+CPPFLAGS += $(INCLUDES)
+CFLAGS += $(INCLUDES)
+CXXFLAGS += $(INCLUDES)
+AFLAGS += $(INCLUDES)
+
+NUTTX = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx$(EXEEXT))
+NUTTXMAP = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx-all.map)
+NUTTXDIS = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx-all.dis)
+
+EXTRADELFILE += $(NUTTXMAP)
+EXTRADELFILE += $(NUTTXDIS)
+
+# Additional rules for system call wrapper
+
+ifeq ($(CONFIG_SCHED_INSTRUMENTATION_SYSCALL),y)
+ EXTRALINKCMDS += @$(TOPDIR)/syscall/syscall_wraps.ldcmd
+endif
+
+# The "head" object
+
+HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT))
+STARTUP_OBJS ?= $(HEAD_OBJ)
+
+# Flat build or kernel-mode objects
+
+ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS)
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+
+CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS)
+COBJS = $(CSRCS:.c=$(OBJEXT))
+
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)
+
+# User-mode objects
+
+UASRCS = $(CHIP_UASRCS) $(CMN_UASRCS)
+UAOBJS = $(UASRCS:.S=$(OBJEXT))
+
+UCSRCS = $(CHIP_UCSRCS) $(CMN_UCSRCS)
+UCOBJS = $(UCSRCS:.c=$(OBJEXT))
+
+USRCS = $(UASRCS) $(UCSRCS)
+UOBJS = $(UAOBJS) $(UCOBJS)
+
+KBIN = libkarch$(LIBEXT)
+BIN = libarch$(LIBEXT)
+
+LDFLAGS += $(addprefix -T,$(call CONVERT_PATH,$(ARCHSCRIPT))) $(EXTRALINKCMDS)
+
+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
Review Comment:
please follow the change from: https://github.com/apache/incubator-nuttx/pull/6123
##########
arch/arm64/src/Toolchain.defs:
##########
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm64/src/Toolchain.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+#
+# Supported toolchains
+#
+# Each toolchain definition should set:
+#
+# CROSSDEV The GNU toolchain triple (command prefix)
+# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
+# FPU options, etc.
+# ARCHOPTIMIZATION The optimization level that results in
+# reliable code generation.
+#
+
+ifeq ($(CONFIG_ARCH_ARMV8A),y)
+ARCHCPUFLAGS += -march=armv8-a
+endif
+
+ifeq ($(CONFIG_ARCH_CORTEX_A53),y)
+ARCHCPUFLAGS += -mtune=cortex-a53
+endif
+
+ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
+ ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL)
+else ifeq ($(CONFIG_DEBUG_FULLOPT),y)
+ ARCHOPTIMIZATION += -Os
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += -fno-strict-aliasing
+endif
+
+ifeq ($(CONFIG_FRAME_POINTER),y)
+ ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls
+else
+ ARCHOPTIMIZATION += -fomit-frame-pointer
+endif
+
+ifeq ($(CONFIG_STACK_CANARIES),y)
+ ARCHOPTIMIZATION += -fstack-protector-all
+endif
+
+ifeq ($(CONFIG_ARCH_COVERAGE),y)
+ ARCHOPTIMIZATION += -fprofile-generate -ftest-coverage
+endif
+ARCHCFLAGS += -fno-common
+ARCHCXXFLAGS += -fno-common -nostdinc++
+
+ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Werror
+ARCHCXXFLAGS += -Wall -Wshadow -Wundef
+
+ifneq ($(CONFIG_CXX_EXCEPTION),y)
+ ARCHCXXFLAGS += -fno-exceptions -fcheck-new
+endif
+
+ifneq ($(CONFIG_CXX_RTTI),y)
+ ARCHCXXFLAGS += -fno-rtti
+endif
+
+LDFLAGS += -nostdlib
+
+# Optimization of unused sections
+
+ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y)
+ LDFLAGS += --gc-sections
+ ARCHOPTIMIZATION += -ffunction-sections -fdata-sections
+endif
+
+# Debug link map
+
+ifeq ($(CONFIG_DEBUG_LINK_MAP),y)
+ LDFLAGS += --cref -Map=$(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx.map)
+endif
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+ ARCHOPTIMIZATION += -g
+endif
Review Comment:
add blank line before CROSSDEV
##########
arch/arm64/src/Toolchain.defs:
##########
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm64/src/Toolchain.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+#
+# Supported toolchains
+#
+# Each toolchain definition should set:
+#
+# CROSSDEV The GNU toolchain triple (command prefix)
+# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
+# FPU options, etc.
+# ARCHOPTIMIZATION The optimization level that results in
+# reliable code generation.
+#
+
+ifeq ($(CONFIG_ARCH_ARMV8A),y)
+ARCHCPUFLAGS += -march=armv8-a
+endif
+
+ifeq ($(CONFIG_ARCH_CORTEX_A53),y)
+ARCHCPUFLAGS += -mtune=cortex-a53
+endif
+
+ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
+ ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL)
+else ifeq ($(CONFIG_DEBUG_FULLOPT),y)
+ ARCHOPTIMIZATION += -Os
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += -fno-strict-aliasing
+endif
+
+ifeq ($(CONFIG_FRAME_POINTER),y)
+ ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls
+else
+ ARCHOPTIMIZATION += -fomit-frame-pointer
+endif
+
+ifeq ($(CONFIG_STACK_CANARIES),y)
+ ARCHOPTIMIZATION += -fstack-protector-all
+endif
+
+ifeq ($(CONFIG_ARCH_COVERAGE),y)
+ ARCHOPTIMIZATION += -fprofile-generate -ftest-coverage
+endif
Review Comment:
add blank line before ARCHCFLAGS
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
+#INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_INCDIR)$(DELIM)}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
+
+CPPFLAGS += $(INCLUDES)
+CFLAGS += $(INCLUDES)
+CXXFLAGS += $(INCLUDES)
+AFLAGS += $(INCLUDES)
+
+NUTTX = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx$(EXEEXT))
+NUTTXMAP = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx-all.map)
+NUTTXDIS = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx-all.dis)
Review Comment:
let's remove NUTTXDIS related test code
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
+#INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_INCDIR)$(DELIM)}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
+
+CPPFLAGS += $(INCLUDES)
+CFLAGS += $(INCLUDES)
+CXXFLAGS += $(INCLUDES)
+AFLAGS += $(INCLUDES)
+
+NUTTX = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx$(EXEEXT))
+NUTTXMAP = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx-all.map)
+NUTTXDIS = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx-all.dis)
+
+EXTRADELFILE += $(NUTTXMAP)
+EXTRADELFILE += $(NUTTXDIS)
+
+# Additional rules for system call wrapper
+
+ifeq ($(CONFIG_SCHED_INSTRUMENTATION_SYSCALL),y)
+ EXTRALINKCMDS += @$(TOPDIR)/syscall/syscall_wraps.ldcmd
+endif
+
+# The "head" object
+
+HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT))
+STARTUP_OBJS ?= $(HEAD_OBJ)
+
+# Flat build or kernel-mode objects
+
+ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS)
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+
+CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS)
+COBJS = $(CSRCS:.c=$(OBJEXT))
+
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)
+
+# User-mode objects
+
+UASRCS = $(CHIP_UASRCS) $(CMN_UASRCS)
+UAOBJS = $(UASRCS:.S=$(OBJEXT))
+
+UCSRCS = $(CHIP_UCSRCS) $(CMN_UCSRCS)
+UCOBJS = $(UCSRCS:.c=$(OBJEXT))
+
+USRCS = $(UASRCS) $(UCSRCS)
+UOBJS = $(UAOBJS) $(UCOBJS)
+
+KBIN = libkarch$(LIBEXT)
+BIN = libarch$(LIBEXT)
+
+LDFLAGS += $(addprefix -T,$(call CONVERT_PATH,$(ARCHSCRIPT))) $(EXTRALINKCMDS)
+
+# Override in Make.defs if linker is not 'ld'
+
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
+BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,)
+
+LIBPATHS += -L $(call CONVERT_PATH,$(TOPDIR)$(DELIM)staging)
+ifeq ($(BOARDMAKE),y)
+ LIBPATHS += -L $(call CONVERT_PATH,$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board)
+endif
+
+LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS)))
+ifeq ($(BOARDMAKE),y)
+ LDLIBS += -lboard
+endif
+
+VPATH += chip
+VPATH += common
+VPATH += $(ARCH_SUBDIR)
+
+ifeq ($(CONFIG_ARCH_TOOLCHAIN_IAR),y)
+ VPATH += $(ARCH_SUBDIR)$(DELIM)iar
+else # ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y)
+ VPATH += $(ARCH_SUBDIR)$(DELIM)gnu
+endif
Review Comment:
remove, the code doesn't support IAR at all.
##########
arch/arm64/src/Toolchain.defs:
##########
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm64/src/Toolchain.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+#
+# Supported toolchains
+#
+# Each toolchain definition should set:
+#
+# CROSSDEV The GNU toolchain triple (command prefix)
+# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
+# FPU options, etc.
+# ARCHOPTIMIZATION The optimization level that results in
+# reliable code generation.
+#
+
+ifeq ($(CONFIG_ARCH_ARMV8A),y)
+ARCHCPUFLAGS += -march=armv8-a
+endif
+
+ifeq ($(CONFIG_ARCH_CORTEX_A53),y)
+ARCHCPUFLAGS += -mtune=cortex-a53
+endif
+
+ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
+ ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL)
+else ifeq ($(CONFIG_DEBUG_FULLOPT),y)
+ ARCHOPTIMIZATION += -Os
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += -fno-strict-aliasing
+endif
+
+ifeq ($(CONFIG_FRAME_POINTER),y)
+ ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls
+else
+ ARCHOPTIMIZATION += -fomit-frame-pointer
+endif
+
+ifeq ($(CONFIG_STACK_CANARIES),y)
+ ARCHOPTIMIZATION += -fstack-protector-all
+endif
+
+ifeq ($(CONFIG_ARCH_COVERAGE),y)
+ ARCHOPTIMIZATION += -fprofile-generate -ftest-coverage
+endif
+ARCHCFLAGS += -fno-common
+ARCHCXXFLAGS += -fno-common -nostdinc++
+
+ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Werror
+ARCHCXXFLAGS += -Wall -Wshadow -Wundef
+
+ifneq ($(CONFIG_CXX_EXCEPTION),y)
+ ARCHCXXFLAGS += -fno-exceptions -fcheck-new
+endif
+
+ifneq ($(CONFIG_CXX_RTTI),y)
+ ARCHCXXFLAGS += -fno-rtti
+endif
+
+LDFLAGS += -nostdlib
+
+# Optimization of unused sections
+
+ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y)
+ LDFLAGS += --gc-sections
+ ARCHOPTIMIZATION += -ffunction-sections -fdata-sections
+endif
+
+# Debug link map
+
+ifeq ($(CONFIG_DEBUG_LINK_MAP),y)
+ LDFLAGS += --cref -Map=$(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx.map)
+endif
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+ ARCHOPTIMIZATION += -g
+endif
+CROSSDEV ?= aarch64-none-elf-
+
+# Default toolchain
+
+CC = $(CROSSDEV)gcc
Review Comment:
let's add clang support like this patch: https://github.com/apache/incubator-nuttx/pull/6105
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
+#INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_INCDIR)$(DELIM)}
+INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
+
+CPPFLAGS += $(INCLUDES)
+CFLAGS += $(INCLUDES)
+CXXFLAGS += $(INCLUDES)
+AFLAGS += $(INCLUDES)
+
+NUTTX = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx$(EXEEXT))
+NUTTXMAP = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx-all.map)
Review Comment:
please follow the change here: https://github.com/apache/incubator-nuttx/pull/6121
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
Review Comment:
remove all ARCH_SRCDIR which is not really used
##########
arch/arm64/src/Toolchain.defs:
##########
@@ -0,0 +1,126 @@
+############################################################################
+# arch/arm64/src/Toolchain.defs
Review Comment:
move to arch/arm64/src/common?
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r917711878
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
Review Comment:
But all people understand the meaning of container_of
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1182193785
Yes, I agree. @qinwei2004 please squash your change, thanks.
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r918865253
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
Review Comment:
Oh, I check container_of at nuttx.h, define is
#define container_of(ptr, type, member) \
((type *)((uintptr_t)(ptr) - offsetof(type, member)))
but for STACK_PTR_TO_FRAME, it's
#define STACK_PTR_TO_FRAME(type, ptr) \
(type *)((ptr) - **sizeof(type)**)
it's deference define
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r919663238
##########
arch/arm64/include/qemu/chip.h:
##########
@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/arm64/include/qemu/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
+#define __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_QEMU_A53)
+
+#define CONFIG_GICD_BASE 0x8000000
Review Comment:
you can put into src/chip.h instead
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[GitHub] [incubator-nuttx] qinwei2004 closed pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 closed pull request #6478: arch: arm64: ARMv8-A support for NuttX
URL: https://github.com/apache/incubator-nuttx/pull/6478
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915017817
##########
boards/arm64/qemu/qemu-a53/src/qemu_appinit.c:
##########
@@ -0,0 +1,75 @@
+/****************************************************************************
+ * boards/arm64/qemu/qemu-a53/src/qemu_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include <nuttx/board.h>
+
+#include "qemu-a53.h"
+
+#ifdef CONFIG_BOARDCTL
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value could be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
Review Comment:
Add:
`UNUSED(arg);`
##########
boards/arm64/qemu/qemu-a53/README.txt:
##########
@@ -0,0 +1,297 @@
+README.txt
+==========
+
+This board configuration will use QEMU to emulate a generic Cortex-A53
+hardware platform and provides support for these devices:
+
+ - GICv3 interrupt controller
+ - ARM Generic Timer
+ - PL011 UART controller
+
+Contents
+========
+ - Getting Started
+ - Status
+ - Platform Features
+ - Debugging with QEMU
+ - FPU Support and Performance
+ - SMP Support
+ - References
+
+Getting Started
+===============
+
+1. Compile Toolchain
+ 1.1 Host environment
+ GNU/Linux: Ubuntu 18.04 or greater
+ 1.2 Download and Install
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ xz -d gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar
+
+ Put gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin/ to your host PATH environment variable, like:
+ $ export PATH=$PATH:/opt/software/arm/linaro-toolchain/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin
+ check the toolchain:
+ $ aarch64-none-elf-gcc -v
+
+2. Install QEMU
+ In Ubuntu 18.04(or greater), install qemu:
+ $ sudo apt-get install qemu-system-arm qemu-efi-aarch64 qemu-utils
+ And make sure install is properly:
+ $ qemu-system-aarch64 --help
+
+3. Configuring and running
+ 3.1 Single Core
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ 3.2 SMP
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh_smp
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ Note:
+ 1. Make sure the aarch64-none-elf toolchain install PATH has been add to environment variable
+ 2. To quit QEMU, type Ctrl + X
+ 3. Nuttx default core number is 4, and Changing CONFIG_SMP_NCPUS > 4 and setting qemu command
+ option -smp will boot more core. for qemu, core limit is 32.
+
+Status
+======
+2022-06-12:
+
+1. SMP is supprt at QEMU. add psci interface, armv8 cache operation(data cache)
+ and smccc support. the system will run into nsh shell, SMP test is PASS, but
+ ostest crash at signal testing
+
+
+2022-05-22:
+ Arm64 support version for NuttX is Ready, These Features supported:
+
+1. Cotex-a53 single core support: With the supporting of GICv3,
+ Arch timer, PL101 UART, The system can run into nsh shell.
+ Running ostest seem PASSED.
+2. qemu-a53 board configuration support: qemu-a53 board can been
+ configuring and compiling, And runing with qemu-system-aarch64
+ at Ubuntu 18.04.
+3. FPU support for armv8-a: FPU context switching in NEON/floating-point
+ TRAP was supported. FPU registers saving at vfork and independent
+ FPU context for signal rountine was considered but more testing
+ need to be do.
Review Comment:
s/need to be do/needs to be done/
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
Should be:
`static int arm64_arch_timer_compare_isr(int irq, FAR void *context, FAR void *arg)`
At top of function, add:
`regs = (uint64_t) context;`
At end of function, add:
`return OK;`
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+}
+
+#else
+
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+ uint64_t next_cycle;
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ next_cycle = last_cycle + cycle_per_tick;
+
+ if ((uint64_t)(next_cycle - curr_cycle) < MIN_DELAY)
+ {
+ next_cycle += cycle_per_tick;
+ }
+
+ arm64_arch_timer_set_compare(next_cycle);
+ arm64_arch_timer_set_irq_mask(false);
+
+ nxsched_process_timer();
+}
+
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+/* Notes:
+ *
+ * The origin design for ARMv8-A timer is assigned private timer to
+ * every PE(CPU core), the ARM_ARCH_TIMER_IRQ is a PPI so it's
+ * should be enable at every core.
+ *
+ * But for NuttX, it's design only for primary core to handle timer
+ * interrupt and call nxsched_process_timer at timer tick mode.
+ * So we need only enable timer for primary core
+ *
+ * IMX6 use GPT which is a SPI rather than generic timer to handle
+ * timer interrupt
+ */
+
+void arm64_smp_timer_init(void)
+{
+ uint64_t curr_cycle;
+
+ /* set the initial status of timer0 of each secondary core */
+
+ curr_cycle = arm64_arch_timer_count();
+
+ arm64_arch_timer_set_compare(curr_cycle + cycle_per_tick);
+ arm64_arch_timer_enable(true);
+ up_enable_irq(ARM_ARCH_TIMER_IRQ);
+ arm64_arch_timer_set_irq_mask(false);
+}
+
+#endif
+
+uint64_t arch_counter_read(void)
+{
+ return arm64_arch_timer_count();
+}
+
+void arch_timer_delay(long mini_sec)
+{
+ unsigned int timeout;
+ volatile unsigned int new_counter;
+ unsigned int clock = mini_sec * arch_timer_rate / 1000;
+
+ if (mini_sec == 0 || mini_sec > 2000)
+ {
+ sinfo("delay must !=0 or < 2000ms \n");
+ return;
+ }
+
+ timeout = arch_counter_read() + clock;
+ do
+ {
+ new_counter = arch_counter_read();
+ arch_nop();
+ }
+ while (new_counter < timeout);
+}
+
+/****************************************************************************
+ * Name: up_timer_initialize
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+ uint64_t curr_cycle;
+
+ arch_timer_rate = arm64_arch_timer_get_cntfrq();
+ cycle_per_tick = ((uint64_t)arch_timer_rate / (uint64_t)TICK_PER_SEC);
+
+ sinfo("%s: cp15 timer(s) running at %lu.%02luMHz, cycle %ld\n", __func__,
+ (unsigned long)arch_timer_rate / 1000000,
+ (unsigned long)(arch_timer_rate / 10000) % 100, cycle_per_tick);
+
+ irq_attach(ARM_ARCH_TIMER_IRQ, (xcpt_t)arm64_arch_timer_compare_isr, 0);
Review Comment:
Will not need typecast to (xcpt_t) after above changes.
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+}
+
+#else
+
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
Same as tickless version of this function:
Should be:
`static int arm64_arch_timer_compare_isr(int irq, FAR void *context, FAR void *arg)`
At top of function, add:
`regs = (uint64_t) context;`
At end of function, add:
`return OK;`
##########
boards/arm64/qemu/qemu-a53/README.txt:
##########
@@ -0,0 +1,297 @@
+README.txt
+==========
+
+This board configuration will use QEMU to emulate a generic Cortex-A53
+hardware platform and provides support for these devices:
+
+ - GICv3 interrupt controller
+ - ARM Generic Timer
+ - PL011 UART controller
+
+Contents
+========
+ - Getting Started
+ - Status
+ - Platform Features
+ - Debugging with QEMU
+ - FPU Support and Performance
+ - SMP Support
+ - References
+
+Getting Started
+===============
+
+1. Compile Toolchain
+ 1.1 Host environment
+ GNU/Linux: Ubuntu 18.04 or greater
+ 1.2 Download and Install
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ xz -d gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar
+
+ Put gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin/ to your host PATH environment variable, like:
+ $ export PATH=$PATH:/opt/software/arm/linaro-toolchain/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin
+ check the toolchain:
+ $ aarch64-none-elf-gcc -v
+
+2. Install QEMU
+ In Ubuntu 18.04(or greater), install qemu:
+ $ sudo apt-get install qemu-system-arm qemu-efi-aarch64 qemu-utils
+ And make sure install is properly:
+ $ qemu-system-aarch64 --help
+
+3. Configuring and running
+ 3.1 Single Core
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ 3.2 SMP
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh_smp
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ Note:
+ 1. Make sure the aarch64-none-elf toolchain install PATH has been add to environment variable
+ 2. To quit QEMU, type Ctrl + X
+ 3. Nuttx default core number is 4, and Changing CONFIG_SMP_NCPUS > 4 and setting qemu command
+ option -smp will boot more core. for qemu, core limit is 32.
+
+Status
+======
+2022-06-12:
+
+1. SMP is supprt at QEMU. add psci interface, armv8 cache operation(data cache)
Review Comment:
s/supprt/support/
##########
boards/arm64/qemu/qemu-a53/README.txt:
##########
@@ -0,0 +1,297 @@
+README.txt
+==========
+
+This board configuration will use QEMU to emulate a generic Cortex-A53
+hardware platform and provides support for these devices:
+
+ - GICv3 interrupt controller
+ - ARM Generic Timer
+ - PL011 UART controller
+
+Contents
+========
+ - Getting Started
+ - Status
+ - Platform Features
+ - Debugging with QEMU
+ - FPU Support and Performance
+ - SMP Support
+ - References
+
+Getting Started
+===============
+
+1. Compile Toolchain
+ 1.1 Host environment
+ GNU/Linux: Ubuntu 18.04 or greater
+ 1.2 Download and Install
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ xz -d gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar
+
+ Put gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin/ to your host PATH environment variable, like:
+ $ export PATH=$PATH:/opt/software/arm/linaro-toolchain/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin
+ check the toolchain:
+ $ aarch64-none-elf-gcc -v
+
+2. Install QEMU
+ In Ubuntu 18.04(or greater), install qemu:
+ $ sudo apt-get install qemu-system-arm qemu-efi-aarch64 qemu-utils
+ And make sure install is properly:
+ $ qemu-system-aarch64 --help
+
+3. Configuring and running
+ 3.1 Single Core
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh
+ $ make
+ Runing with qemu
Review Comment:
s/Runing/Running/g
##########
boards/arm64/qemu/qemu-a53/README.txt:
##########
@@ -0,0 +1,297 @@
+README.txt
+==========
+
+This board configuration will use QEMU to emulate a generic Cortex-A53
+hardware platform and provides support for these devices:
+
+ - GICv3 interrupt controller
+ - ARM Generic Timer
+ - PL011 UART controller
+
+Contents
+========
+ - Getting Started
+ - Status
+ - Platform Features
+ - Debugging with QEMU
+ - FPU Support and Performance
+ - SMP Support
+ - References
+
+Getting Started
+===============
+
+1. Compile Toolchain
+ 1.1 Host environment
+ GNU/Linux: Ubuntu 18.04 or greater
+ 1.2 Download and Install
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ xz -d gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar
+
+ Put gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin/ to your host PATH environment variable, like:
+ $ export PATH=$PATH:/opt/software/arm/linaro-toolchain/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin
+ check the toolchain:
+ $ aarch64-none-elf-gcc -v
+
+2. Install QEMU
+ In Ubuntu 18.04(or greater), install qemu:
+ $ sudo apt-get install qemu-system-arm qemu-efi-aarch64 qemu-utils
+ And make sure install is properly:
+ $ qemu-system-aarch64 --help
+
+3. Configuring and running
+ 3.1 Single Core
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ 3.2 SMP
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh_smp
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ Note:
+ 1. Make sure the aarch64-none-elf toolchain install PATH has been add to environment variable
+ 2. To quit QEMU, type Ctrl + X
+ 3. Nuttx default core number is 4, and Changing CONFIG_SMP_NCPUS > 4 and setting qemu command
+ option -smp will boot more core. for qemu, core limit is 32.
+
+Status
+======
+2022-06-12:
+
+1. SMP is supprt at QEMU. add psci interface, armv8 cache operation(data cache)
+ and smccc support. the system will run into nsh shell, SMP test is PASS, but
+ ostest crash at signal testing
+
+
+2022-05-22:
+ Arm64 support version for NuttX is Ready, These Features supported:
+
+1. Cotex-a53 single core support: With the supporting of GICv3,
+ Arch timer, PL101 UART, The system can run into nsh shell.
+ Running ostest seem PASSED.
+2. qemu-a53 board configuration support: qemu-a53 board can been
+ configuring and compiling, And runing with qemu-system-aarch64
+ at Ubuntu 18.04.
+3. FPU support for armv8-a: FPU context switching in NEON/floating-point
+ TRAP was supported. FPU registers saving at vfork and independent
+ FPU context for signal rountine was considered but more testing
Review Comment:
s/rountine/routine/g
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r914024867
##########
arch/arm64/src/common/addrenv.h:
##########
@@ -0,0 +1,105 @@
+/****************************************************************************
+ * arch/arm64/src/common/addrenv.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ADDRENV_H
+#define __ARCH_ARM64_SRC_COMMON_ADDRENV_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
Review Comment:
add blank line
##########
arch/arm64/src/common/arm64_arch_timer.h:
##########
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
Review Comment:
add blank line
##########
arch/arm64/src/common/arm64_allocateheap.c:
##########
@@ -0,0 +1,163 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/userspace.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a
+ * single heap access with the standard allocations (malloc/free). This
+ * heap is referred to as the user heap. In the protected build
+ * (CONFIG_BUILD_PROTECTED=y) where an MPU is used to protect a region of
+ * otherwise flat memory, there will be two allocators: One that allocates
+ * protected (kernel) memory and one that allocates unprotected (user)
+ * memory. These are referred to as the kernel and user heaps,
+ * respectively.
+ *
+ * The ARMv7 has no MPU but does have an MMU. With this MMU, it can support
+ * the kernel build (CONFIG_BUILD_KERNEL=y). In this configuration, there
+ * is one kernel heap but multiple user heaps: One per task group. However,
+ * in this case, we need only be concerned about initializing the single
+ * kernel heap here.
+ */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap/up_allocate_kheap
+ *
+ * Description:
+ * This function will be called to dynamically set aside the heap region.
+ *
+ * - For the normal "flat" build, this function returns the size of the
+ * single heap.
+ * - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel-
+ * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function
+ * provides the size of the unprotected, user-space heap.
+ * - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides
+ * the size of the protected, kernel-space heap.
+ *
+ * If a protected kernel-space heap is provided, the kernel heap must be
+ * allocated by an analogous up_allocate_kheap(). A custom version of this
+ * file is needed if memory protection of the kernel heap is required.
+ *
+ * The following memory map is assumed for the flat build:
+ *
+ * .data region. Size determined at link time.
+ * .bss region Size determined at link time.
+ * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ * Heap. Extends to the end of SRAM.
+ *
+ * The following memory map is assumed for the kernel build:
+ *
+ * Kernel .data region. Size determined at link time.
+ * Kernel .bss region Size determined at link time.
+ * Kernel IDLE thread stack. Size determined by
+ * CONFIG_IDLETHREAD_STACKSIZE.
+ * Padding for alignment
+ * User .data region. Size determined at link time.
+ * User .bss region Size determined at link time.
+ * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
+ * User heap. Extends to the end of SRAM.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BUILD_KERNEL
+void up_allocate_kheap(void **heap_start, size_t *heap_size)
+#else
+void up_allocate_heap(void **heap_start, size_t *heap_size)
+#endif
+{
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+ /* Get the unaligned size and position of the user-space heap.
+ * This heap begins after the user-space .bss section at an offset
+ * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+ */
+
+ uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
+ CONFIG_MM_KERNEL_HEAPSIZE;
+ size_t usize = CONFIG_RAM_END - ubase;
+
+ /* Return the user-space heap settings */
+
+ board_autoled_on(LED_HEAPALLOCATE);
+ *heap_start = (void *)ubase;
+ *heap_size = usize;
+#else
+
+ /* Return the heap settings */
+
+ *heap_start = (void *)_e_initstack;
Review Comment:
change _e_initstack to g_idle_topstack, let's use the same symbol
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
Review Comment:
add blank line
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
Review Comment:
why not use modreg32
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
Review Comment:
ditto
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
+EXTERN char _srodata[]; /* Start of .rodata */
+EXTERN char _erodata[]; /* End+1 of .rodata */
+EXTERN char _szrodata[]; /* Size of .rodata */
+EXTERN const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
+EXTERN char _sdata[]; /* Start of .data */
+EXTERN char _edata[]; /* End+1 of .data */
+EXTERN char _sbss[]; /* Start of .bss */
+EXTERN char _ebss[]; /* End+1 of .bss */
+EXTERN char _szdata[]; /* Size of data(.data + .bss) */
+EXTERN char _e_initstack[]; /* End+1 of .initstack */
+
+# define _START_TEXT _stext
+# define _END_TEXT _etext
+# define _START_BSS _sbss
+# define _END_BSS _ebss
+# define _DATA_INIT _eronly
+# define _START_DATA _sdata
+# define _END_DATA _edata
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tak_new);
+
+/* Low level initialization provided by chip logic */
+
+void arm64_chip_boot(void);
+
+int arm64_psci_init(const char *method);
+
+void __start(void);
+void arm64_secondary_start(void);
+
+/* Context switching */
+
+void arm64_fullcontextrestore(uint64_t * restoreregs) noreturn_function;
+void arm64_switchcontext(uint64_t ** saveregs, uint64_t *restoreregs);
+void arm64_context_snapshot(void *savereg);
+
+/* Signal handling **********************************************************/
+
+void arm64_sigdeliver(void);
+
+/* Power management *********************************************************/
+
+#ifdef CONFIG_PM
+void arm64_pminitialize(void);
+#else
+# define arm64_pminitialize()
+#endif
+
+/* Interrupt handling */
+
+/* Exception handling logic unique to the Cortex-A and Cortex-R families
+ * (but should be back-ported to the ARM7 and ARM9 families).
+ */
+
+/* Interrupt acknowledge and dispatch */
+
+uint64_t *arm64_doirq(int irq, uint64_t * regs);
+
+/* Paging support */
+
+#ifdef CONFIG_PAGING
+void arm64_pginitialize(void);
+#else /* CONFIG_PAGING */
+# define arm64_pginitialize()
+#endif /* CONFIG_PAGING */
+
+uint64_t * arm64_syscall_switch(uint64_t * regs);
+int arm64_syscall(uint64_t * regs);
+
+#ifdef USE_SERIALDRIVER
+void arm64_serialinit(void);
+#endif
+
+#ifdef USE_EARLYSERIALINIT
+void arm64_earlyserialinit(void);
+#endif
+
+#ifdef CONFIG_RPMSG_UART
+void rpmsg_serialinit(void);
Review Comment:
remove
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
Review Comment:
why not directly use char
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
Review Comment:
change to THREAD_STACK_DECLARE
##########
arch/arm64/src/common/addrenv.h:
##########
@@ -0,0 +1,105 @@
+/****************************************************************************
+ * arch/arm64/src/common/addrenv.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ADDRENV_H
+#define __ARCH_ARM64_SRC_COMMON_ADDRENV_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include "arm64_internal.h"
+
+#ifdef CONFIG_ARCH_ADDRENV
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Aligned size of the kernel stack */
+
+#ifdef CONFIG_ARCH_KERNEL_STACK
+# define ARCH_KERNEL_STACKSIZE STACK_ALIGN_UP(CONFIG_ARCH_KERNEL_STACKSIZE)
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif /* __ASSEMBLY__ */
Review Comment:
remove the empty #ifndef/#endif?
##########
arch/arm64/src/common/arm64_allocateheap.c:
##########
@@ -0,0 +1,163 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
Review Comment:
add blank line
##########
arch/arm64/src/common/arm64_allocateheap.c:
##########
@@ -0,0 +1,163 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/userspace.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a
+ * single heap access with the standard allocations (malloc/free). This
+ * heap is referred to as the user heap. In the protected build
+ * (CONFIG_BUILD_PROTECTED=y) where an MPU is used to protect a region of
+ * otherwise flat memory, there will be two allocators: One that allocates
+ * protected (kernel) memory and one that allocates unprotected (user)
+ * memory. These are referred to as the kernel and user heaps,
+ * respectively.
+ *
+ * The ARMv7 has no MPU but does have an MMU. With this MMU, it can support
Review Comment:
ARMv8
##########
arch/arm64/src/common/arm64_arch_timer.h:
##########
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_ARCH_TIMER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_gic.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CONFIG_ARM_TIMER_SECURE_IRQ (GIC_PPI_INT_BASE + 13)
+#define CONFIG_ARM_TIMER_NON_SECURE_IRQ (GIC_PPI_INT_BASE + 14)
+#define CONFIG_ARM_TIMER_VIRTUAL_IRQ (GIC_PPI_INT_BASE + 11)
+#define CONFIG_ARM_TIMER_HYP_IRQ (GIC_PPI_INT_BASE + 10)
+
+#define ARM_ARCH_TIMER_IRQ CONFIG_ARM_TIMER_VIRTUAL_IRQ
+#define ARM_ARCH_TIMER_PRIO IRQ_DEFAULT_PRIORITY
+#define ARM_ARCH_TIMER_FLAGS IRQ_TYPE_LEVEL
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+extern uint64_t arch_counter_read(void);
Review Comment:
let's unify the prefix from arch_ to arm64_
##########
arch/arm64/include/qemu/chip.h:
##########
@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/arm64/include/qemu/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
+#define __ARCH_ARM64_INCLUDE_QEMU_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#if defined(CONFIG_ARCH_CHIP_QEMU_A53)
+
+#define CONFIG_GICD_BASE 0x8000000
Review Comment:
this is arm64 specific macro, don't need expose to the public interface
##########
arch/arm64/src/common/arm64_allocateheap.c:
##########
@@ -0,0 +1,163 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/userspace.h>
+
+#include "arm64_arch.h"
Review Comment:
remove, don't need
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
+#define GIC_DIST_IGROUPR 0x0080
+#define GIC_DIST_ISENABLER 0x0100
+#define GIC_DIST_ICENABLER 0x0180
+#define GIC_DIST_ISPENDR 0x0200
+#define GIC_DIST_ICPENDR 0x0280
+#define GIC_DIST_ISACTIVER 0x0300
+#define GIC_DIST_ICACTIVER 0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR 0x0800
+#define GIC_DIST_ICFGR 0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR 0x0f00
+
+/* GICD GICR common access macros */
+
+#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD_PIDR2 : Peripheral ID2 Register
+ * bit assignments
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+#define GICD_PIDR2_ARCH_MASK 0xf0
+#define GICD_PIDR2_ARCH_GICV3 0x30
+#define GICD_PIDR2_ARCH_GICV4 0x40
+
+/* GICD_TYPER : Interrupt Controller Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+#define GICD_TYPER_RSS (1U << 26)
+#define GICD_TYPER_LPIS (1U << 17)
+#define GICD_TYPER_MBIS (1U << 16)
+#define GICD_TYPER_ESPI (1U << 8)
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
+#define GICD_TYPER_ESPIS(typer) \
+ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
+
+/* Common Helper Constants */
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
+ ((intid) < GIC_PPI_INT_BASE))
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_NUM_INTR_PER_REG 32
+#define GIC_NUM_CFG_PER_REG 16
+#define GIC_NUM_PRI_PER_REG 4
+
+/* GIC idle priority : value '0xff' will allow all interrupts */
+
+#define GIC_IDLE_PRIO 0xff
+
+/* Priority levels 0:255 */
+
+#define GIC_PRI_MASK 0xff
+
+/* '0xa0'is used to initialize each interrtupt default priority.
+ * This is an arbitrary value in current context.
+ * Any value '0x80' to '0xff' will work for both NS and S state.
+ * The values of individual interrupt and default has to be chosen
+ * carefully if PMR and BPR based nesting and preemption has to be done.
+ */
+
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
+
+/* Register bit definitions */
+
+/* GICD_CTLR Interrupt group definitions */
+#define GICD_CTLR_ENABLE_G0 0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S 2
+#define GICD_CTRL_ARE_S 4
+#define GICD_CTRL_ARE_NS 5
+#define GICD_CTRL_NS 6
+#define GICD_CGRL_E1NWF 7
+
+/* GICD_CTLR Register write progress bit */
+#define GICD_CTLR_RWP 31
+
+/* GICR_CTLR */
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP 3
+
+/* GICD_TYPER.ITLinesNumber 0:4 */
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICR： Re-Distributor registers, offsets from RD_base(n) */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00A0
+#define GICR_INVALLR 0x00B0
+#define GICR_SYNCR 0x00C0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+#define GICR_IDREGS 0xFFD0
+#define GICR_PIDR2 0xFFE8
+
+/* GICR_PIDR2 : Peripheral ID2 Register
+ * bit assignments are the same as those for GICD_PIDR2)
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+
+#define GICR_PIDR2_ARCH_MASK 0xf0
+#define GICR_PIDR2_ARCH_GICV3 0x30
+#define GICR_PIDR2_ARCH_GICV4 0x40
+
+/* GICR_TYPER : Redistributor Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ * chapter 9.11.35 for detail descriptions
+ */
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_DIRECTLPIS (1U << 3)
+#define GICR_TYPER_LAST (1U << 4)
+
+/* GICR_WAKER */
+#define GICR_WAKER_PS 1
+#define GICR_WAKER_CA 2
+
+/* SGI base is at 64K offset from Redistributor */
+#define GICR_SGI_BASE_OFF 0x10000
+
+/* GICD_ICFGR */
+#define GICD_ICFGR_MASK BIT_MASK(2)
+#define GICD_ICFGR_TYPE BIT(1)
Review Comment:
please unify BIT/BIT_MASK usage, either:
1. replace all x << y with BIT/BIT_MASK
2. or remove BIT/BIT_MASK macro
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
Review Comment:
add blank line
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
Review Comment:
should we change CONFIG_GICD_BASE to Kconfig?
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
+#define GIC_DIST_IGROUPR 0x0080
+#define GIC_DIST_ISENABLER 0x0100
+#define GIC_DIST_ICENABLER 0x0180
+#define GIC_DIST_ISPENDR 0x0200
+#define GIC_DIST_ICPENDR 0x0280
+#define GIC_DIST_ISACTIVER 0x0300
+#define GIC_DIST_ICACTIVER 0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR 0x0800
+#define GIC_DIST_ICFGR 0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR 0x0f00
+
+/* GICD GICR common access macros */
+
+#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD_PIDR2 : Peripheral ID2 Register
+ * bit assignments
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+#define GICD_PIDR2_ARCH_MASK 0xf0
+#define GICD_PIDR2_ARCH_GICV3 0x30
+#define GICD_PIDR2_ARCH_GICV4 0x40
+
+/* GICD_TYPER : Interrupt Controller Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+#define GICD_TYPER_RSS (1U << 26)
+#define GICD_TYPER_LPIS (1U << 17)
+#define GICD_TYPER_MBIS (1U << 16)
+#define GICD_TYPER_ESPI (1U << 8)
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
+#define GICD_TYPER_ESPIS(typer) \
+ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
+
+/* Common Helper Constants */
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
+ ((intid) < GIC_PPI_INT_BASE))
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_NUM_INTR_PER_REG 32
+#define GIC_NUM_CFG_PER_REG 16
+#define GIC_NUM_PRI_PER_REG 4
+
+/* GIC idle priority : value '0xff' will allow all interrupts */
+
+#define GIC_IDLE_PRIO 0xff
+
+/* Priority levels 0:255 */
+
+#define GIC_PRI_MASK 0xff
+
+/* '0xa0'is used to initialize each interrtupt default priority.
+ * This is an arbitrary value in current context.
+ * Any value '0x80' to '0xff' will work for both NS and S state.
+ * The values of individual interrupt and default has to be chosen
+ * carefully if PMR and BPR based nesting and preemption has to be done.
+ */
+
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
+
+/* Register bit definitions */
+
+/* GICD_CTLR Interrupt group definitions */
+#define GICD_CTLR_ENABLE_G0 0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S 2
+#define GICD_CTRL_ARE_S 4
+#define GICD_CTRL_ARE_NS 5
+#define GICD_CTRL_NS 6
+#define GICD_CGRL_E1NWF 7
+
+/* GICD_CTLR Register write progress bit */
+#define GICD_CTLR_RWP 31
+
+/* GICR_CTLR */
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP 3
+
+/* GICD_TYPER.ITLinesNumber 0:4 */
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICR： Re-Distributor registers, offsets from RD_base(n) */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00A0
+#define GICR_INVALLR 0x00B0
+#define GICR_SYNCR 0x00C0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+#define GICR_IDREGS 0xFFD0
+#define GICR_PIDR2 0xFFE8
+
+/* GICR_PIDR2 : Peripheral ID2 Register
+ * bit assignments are the same as those for GICD_PIDR2)
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+
+#define GICR_PIDR2_ARCH_MASK 0xf0
+#define GICR_PIDR2_ARCH_GICV3 0x30
+#define GICR_PIDR2_ARCH_GICV4 0x40
+
+/* GICR_TYPER : Redistributor Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ * chapter 9.11.35 for detail descriptions
+ */
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_DIRECTLPIS (1U << 3)
+#define GICR_TYPER_LAST (1U << 4)
+
+/* GICR_WAKER */
+#define GICR_WAKER_PS 1
+#define GICR_WAKER_CA 2
+
+/* SGI base is at 64K offset from Redistributor */
+#define GICR_SGI_BASE_OFF 0x10000
+
+/* GICD_ICFGR */
+#define GICD_ICFGR_MASK BIT_MASK(2)
+#define GICD_ICFGR_TYPE BIT(1)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_SPI_MAX_INTID 1019
+#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \
+ ((intid) <= GIC_SPI_MAX_INTID))
+
+/* GITCD_IROUTER */
+#define GIC_DIST_IROUTER 0x6000
+#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define IRQ_DEFAULT_PRIORITY 0xa0
+
+#define GIC_IRQ_SGI0 0
+#define GIC_IRQ_SGI1 1
+#define GIC_IRQ_SGI2 2
+#define GIC_IRQ_SGI3 3
+#define GIC_IRQ_SGI4 4
+#define GIC_IRQ_SGI5 5
+#define GIC_IRQ_SGI6 6
+#define GIC_IRQ_SGI7 7
+#define GIC_IRQ_SGI8 8
+#define GIC_IRQ_SGI9 9
+#define GIC_IRQ_SGI10 10
+#define GIC_IRQ_SGI11 11
+#define GIC_IRQ_SGI12 12
+#define GIC_IRQ_SGI13 13
+#define GIC_IRQ_SGI14 14
+#define GIC_IRQ_SGI15 15
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+bool arm64_gic_irq_is_enabled(unsigned int intid);
+int arm64_gic_initialize(void);
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags);
+
+/****************************************************************************
+ * Name: arm64_decodeirq
+ *
+ * Description:
+ * This function is called from the IRQ vector handler in arm_vectors.S.
+ * At this point, the interrupt has been taken and the registers have
+ * been saved on the stack. This function simply needs to determine the
+ * the irq number of the interrupt and then to call arm_doirq to dispatch
+ * the interrupt.
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area on the stack.
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_decodeirq(uint64_t * regs);
Review Comment:
remove space after *
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GIC Distributor register Interface Base Addresses
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+
+#define GIC_DIST_BASE CONFIG_GICD_BASE
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
+#define GICD_STATUSR (GIC_DIST_BASE + 0x10)
+#define GICD_SETSPI_NSR (GIC_DIST_BASE + 0x40)
+#define GICD_CLRSPI_NSR (GIC_DIST_BASE + 0x48)
+#define GICD_SETSPI_SR (GIC_DIST_BASE + 0x50)
+#define GICD_CLRSPI_SR (GIC_DIST_BASE + 0x58)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
+#define GICD_IDREGS (GIC_DIST_BASE + 0xFFD0)
+#define GICD_PIDR2 (GIC_DIST_BASE + 0xFFE8)
+
+/* Offsets from GICD base or GICR(n) SGI_base */
+#define GIC_DIST_IGROUPR 0x0080
+#define GIC_DIST_ISENABLER 0x0100
+#define GIC_DIST_ICENABLER 0x0180
+#define GIC_DIST_ISPENDR 0x0200
+#define GIC_DIST_ICPENDR 0x0280
+#define GIC_DIST_ISACTIVER 0x0300
+#define GIC_DIST_ICACTIVER 0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR 0x0800
+#define GIC_DIST_ICFGR 0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR 0x0f00
+
+/* GICD GICR common access macros */
+
+#define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD_PIDR2 : Peripheral ID2 Register
+ * bit assignments
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+#define GICD_PIDR2_ARCH_MASK 0xf0
+#define GICD_PIDR2_ARCH_GICV3 0x30
+#define GICD_PIDR2_ARCH_GICV4 0x40
+
+/* GICD_TYPER : Interrupt Controller Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ */
+#define GICD_TYPER_RSS (1U << 26)
+#define GICD_TYPER_LPIS (1U << 17)
+#define GICD_TYPER_MBIS (1U << 16)
+#define GICD_TYPER_ESPI (1U << 8)
+#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
+#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
+#define GICD_TYPER_ESPIS(typer) \
+ (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
+
+/* Common Helper Constants */
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && \
+ ((intid) < GIC_PPI_INT_BASE))
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_NUM_INTR_PER_REG 32
+#define GIC_NUM_CFG_PER_REG 16
+#define GIC_NUM_PRI_PER_REG 4
+
+/* GIC idle priority : value '0xff' will allow all interrupts */
+
+#define GIC_IDLE_PRIO 0xff
+
+/* Priority levels 0:255 */
+
+#define GIC_PRI_MASK 0xff
+
+/* '0xa0'is used to initialize each interrtupt default priority.
+ * This is an arbitrary value in current context.
+ * Any value '0x80' to '0xff' will work for both NS and S state.
+ * The values of individual interrupt and default has to be chosen
+ * carefully if PMR and BPR based nesting and preemption has to be done.
+ */
+
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
+
+/* Register bit definitions */
+
+/* GICD_CTLR Interrupt group definitions */
+#define GICD_CTLR_ENABLE_G0 0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S 2
+#define GICD_CTRL_ARE_S 4
+#define GICD_CTRL_ARE_NS 5
+#define GICD_CTRL_NS 6
+#define GICD_CGRL_E1NWF 7
+
+/* GICD_CTLR Register write progress bit */
+#define GICD_CTLR_RWP 31
+
+/* GICR_CTLR */
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP 3
+
+/* GICD_TYPER.ITLinesNumber 0:4 */
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICR： Re-Distributor registers, offsets from RD_base(n) */
+#define GICR_CTLR 0x0000
+#define GICR_IIDR 0x0004
+#define GICR_TYPER 0x0008
+#define GICR_STATUSR 0x0010
+#define GICR_WAKER 0x0014
+#define GICR_SETLPIR 0x0040
+#define GICR_CLRLPIR 0x0048
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_INVLPIR 0x00A0
+#define GICR_INVALLR 0x00B0
+#define GICR_SYNCR 0x00C0
+#define GICR_MOVLPIR 0x0100
+#define GICR_MOVALLR 0x0110
+#define GICR_IDREGS 0xFFD0
+#define GICR_PIDR2 0xFFE8
+
+/* GICR_PIDR2 : Peripheral ID2 Register
+ * bit assignments are the same as those for GICD_PIDR2)
+ * [31:8] - IMPLEMENTATION DEFINED
+ * [7:4] ArchRev 0x1. GICv1.
+ * 0x2. GICv2.
+ * 0x3. GICv3.
+ * 0x4. GICv4.
+ * [3:0] - IMPLEMENTATION DEFINED.
+ */
+
+#define GICR_PIDR2_ARCH_MASK 0xf0
+#define GICR_PIDR2_ARCH_GICV3 0x30
+#define GICR_PIDR2_ARCH_GICV4 0x40
+
+/* GICR_TYPER : Redistributor Type Register
+ * Arm® Generic Interrupt Controller Architecture Specification
+ * GIC architecture version 3 and version 4
+ * chapter 9.11.35 for detail descriptions
+ */
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_DIRECTLPIS (1U << 3)
+#define GICR_TYPER_LAST (1U << 4)
+
+/* GICR_WAKER */
+#define GICR_WAKER_PS 1
+#define GICR_WAKER_CA 2
+
+/* SGI base is at 64K offset from Redistributor */
+#define GICR_SGI_BASE_OFF 0x10000
+
+/* GICD_ICFGR */
+#define GICD_ICFGR_MASK BIT_MASK(2)
+#define GICD_ICFGR_TYPE BIT(1)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define GIC_SPI_INT_BASE 32
+#define GIC_SPI_MAX_INTID 1019
+#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && \
+ ((intid) <= GIC_SPI_MAX_INTID))
+
+/* GITCD_IROUTER */
+#define GIC_DIST_IROUTER 0x6000
+#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
+
+/* BIT(0) reserved for IRQ_ZERO_LATENCY */
+#define IRQ_TYPE_LEVEL BIT(1)
+#define IRQ_TYPE_EDGE BIT(2)
+
+#define IRQ_DEFAULT_PRIORITY 0xa0
+
+#define GIC_IRQ_SGI0 0
+#define GIC_IRQ_SGI1 1
+#define GIC_IRQ_SGI2 2
+#define GIC_IRQ_SGI3 3
+#define GIC_IRQ_SGI4 4
+#define GIC_IRQ_SGI5 5
+#define GIC_IRQ_SGI6 6
+#define GIC_IRQ_SGI7 7
+#define GIC_IRQ_SGI8 8
+#define GIC_IRQ_SGI9 9
+#define GIC_IRQ_SGI10 10
+#define GIC_IRQ_SGI11 11
+#define GIC_IRQ_SGI12 12
+#define GIC_IRQ_SGI13 13
+#define GIC_IRQ_SGI14 14
+#define GIC_IRQ_SGI15 15
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+bool arm64_gic_irq_is_enabled(unsigned int intid);
+int arm64_gic_initialize(void);
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags);
+
+/****************************************************************************
+ * Name: arm64_decodeirq
+ *
+ * Description:
+ * This function is called from the IRQ vector handler in arm_vectors.S.
+ * At this point, the interrupt has been taken and the registers have
+ * been saved on the stack. This function simply needs to determine the
+ * the irq number of the interrupt and then to call arm_doirq to dispatch
+ * the interrupt.
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area on the stack.
+ *
+ ****************************************************************************/
+
+uint64_t * arm64_decodeirq(uint64_t * regs);
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
Review Comment:
add arm64_ preifx
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
Review Comment:
add blank line
##########
arch/arm64/src/common/arm64_interruptcontext.c:
##########
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_interruptcontext.c
Review Comment:
remove the file
##########
arch/arm64/src/common/arm64_initialize.c:
##########
@@ -0,0 +1,181 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialize.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
Review Comment:
add new line
##########
arch/arm64/src/common/arm64_initialize.c:
##########
@@ -0,0 +1,181 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialize.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+#ifdef CONFIG_SMP
+THREAD_STACK_ARRAY_DEFINE(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/****************************************************************************
+ * Name: arm64_intstack_alloc
Review Comment:
move to public section
##########
arch/arm64/src/common/arm64_initialize.c:
##########
@@ -0,0 +1,181 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialize.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
Review Comment:
remove the unused header file
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
+EXTERN char _srodata[]; /* Start of .rodata */
+EXTERN char _erodata[]; /* End+1 of .rodata */
+EXTERN char _szrodata[]; /* Size of .rodata */
+EXTERN const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
+EXTERN char _sdata[]; /* Start of .data */
+EXTERN char _edata[]; /* End+1 of .data */
+EXTERN char _sbss[]; /* Start of .bss */
+EXTERN char _ebss[]; /* End+1 of .bss */
+EXTERN char _szdata[]; /* Size of data(.data + .bss) */
+EXTERN char _e_initstack[]; /* End+1 of .initstack */
+
+# define _START_TEXT _stext
+# define _END_TEXT _etext
+# define _START_BSS _sbss
+# define _END_BSS _ebss
+# define _DATA_INIT _eronly
+# define _START_DATA _sdata
+# define _END_DATA _edata
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tak_new);
+
+/* Low level initialization provided by chip logic */
+
+void arm64_chip_boot(void);
+
+int arm64_psci_init(const char *method);
+
+void __start(void);
+void arm64_secondary_start(void);
+
+/* Context switching */
+
+void arm64_fullcontextrestore(uint64_t * restoreregs) noreturn_function;
+void arm64_switchcontext(uint64_t ** saveregs, uint64_t *restoreregs);
+void arm64_context_snapshot(void *savereg);
+
+/* Signal handling **********************************************************/
+
+void arm64_sigdeliver(void);
+
+/* Power management *********************************************************/
+
+#ifdef CONFIG_PM
+void arm64_pminitialize(void);
+#else
+# define arm64_pminitialize()
+#endif
+
+/* Interrupt handling */
+
+/* Exception handling logic unique to the Cortex-A and Cortex-R families
+ * (but should be back-ported to the ARM7 and ARM9 families).
+ */
+
+/* Interrupt acknowledge and dispatch */
+
+uint64_t *arm64_doirq(int irq, uint64_t * regs);
+
+/* Paging support */
+
+#ifdef CONFIG_PAGING
+void arm64_pginitialize(void);
+#else /* CONFIG_PAGING */
+# define arm64_pginitialize()
+#endif /* CONFIG_PAGING */
+
+uint64_t * arm64_syscall_switch(uint64_t * regs);
+int arm64_syscall(uint64_t * regs);
+
+#ifdef USE_SERIALDRIVER
+void arm64_serialinit(void);
+#endif
+
+#ifdef USE_EARLYSERIALINIT
+void arm64_earlyserialinit(void);
+#endif
+
+#ifdef CONFIG_RPMSG_UART
+void rpmsg_serialinit(void);
+#endif
+
+#ifdef CONFIG_LWL_CONSOLE
+void lwlconsole_init(void);
+#endif
+
+/* DMA */
+
+#ifdef CONFIG_ARCH_DMA
+void weak_function arm_dma_initialize(void);
+#endif
+
+/* Cache control */
+
+#ifdef CONFIG_ARCH_L2CACHE
+void arm64_l2ccinitialize(void);
+#else
+# define arm64_l2ccinitialize()
+#endif
+
+/* Memory management */
+
+#if CONFIG_MM_REGIONS > 1
+void arm64_addregion(void);
+#else
+# define arm64_addregion()
+#endif
+
+/* Networking */
+
+/* Defined in board/xyz_network.c for board-specific Ethernet
+ * implementations, or chip/xyx_ethernet.c for chip-specific Ethernet
+ * implementations, or common/arm_etherstub.c for a corner case where the
+ * network is enabled yet there is no Ethernet driver to be initialized.
+ *
+ * Use of common/arm_etherstub.c is deprecated. The preferred mechanism is
+ * to use CONFIG_NETDEV_LATEINIT=y to suppress the call to
+ * arm_netinitialize() in up_initialize(). Then this stub would not be
+ * needed.
+ */
+
+#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT)
+void arm64_netinitialize(void);
+#else
+# define arm64_netinitialize()
+#endif
+
+/* USB */
+
+#ifdef CONFIG_USBDEV
+void arm_usbinitialize(void);
Review Comment:
change all arm_ to arm64_
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
+EXTERN char _srodata[]; /* Start of .rodata */
+EXTERN char _erodata[]; /* End+1 of .rodata */
+EXTERN char _szrodata[]; /* Size of .rodata */
+EXTERN const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
+EXTERN char _sdata[]; /* Start of .data */
+EXTERN char _edata[]; /* End+1 of .data */
+EXTERN char _sbss[]; /* Start of .bss */
+EXTERN char _ebss[]; /* End+1 of .bss */
+EXTERN char _szdata[]; /* Size of data(.data + .bss) */
+EXTERN char _e_initstack[]; /* End+1 of .initstack */
+
+# define _START_TEXT _stext
+# define _END_TEXT _etext
+# define _START_BSS _sbss
+# define _END_BSS _ebss
+# define _DATA_INIT _eronly
+# define _START_DATA _sdata
+# define _END_DATA _edata
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tak_new);
+
+/* Low level initialization provided by chip logic */
+
+void arm64_chip_boot(void);
+
+int arm64_psci_init(const char *method);
+
+void __start(void);
+void arm64_secondary_start(void);
+
+/* Context switching */
+
+void arm64_fullcontextrestore(uint64_t * restoreregs) noreturn_function;
+void arm64_switchcontext(uint64_t ** saveregs, uint64_t *restoreregs);
+void arm64_context_snapshot(void *savereg);
+
+/* Signal handling **********************************************************/
+
+void arm64_sigdeliver(void);
+
+/* Power management *********************************************************/
+
+#ifdef CONFIG_PM
+void arm64_pminitialize(void);
+#else
+# define arm64_pminitialize()
+#endif
+
+/* Interrupt handling */
+
+/* Exception handling logic unique to the Cortex-A and Cortex-R families
+ * (but should be back-ported to the ARM7 and ARM9 families).
+ */
+
+/* Interrupt acknowledge and dispatch */
+
+uint64_t *arm64_doirq(int irq, uint64_t * regs);
+
+/* Paging support */
+
+#ifdef CONFIG_PAGING
+void arm64_pginitialize(void);
+#else /* CONFIG_PAGING */
+# define arm64_pginitialize()
+#endif /* CONFIG_PAGING */
+
+uint64_t * arm64_syscall_switch(uint64_t * regs);
+int arm64_syscall(uint64_t * regs);
+
+#ifdef USE_SERIALDRIVER
+void arm64_serialinit(void);
+#endif
+
+#ifdef USE_EARLYSERIALINIT
+void arm64_earlyserialinit(void);
+#endif
+
+#ifdef CONFIG_RPMSG_UART
+void rpmsg_serialinit(void);
+#endif
+
+#ifdef CONFIG_LWL_CONSOLE
+void lwlconsole_init(void);
+#endif
+
+/* DMA */
+
+#ifdef CONFIG_ARCH_DMA
+void weak_function arm_dma_initialize(void);
+#endif
+
+/* Cache control */
+
+#ifdef CONFIG_ARCH_L2CACHE
+void arm64_l2ccinitialize(void);
+#else
+# define arm64_l2ccinitialize()
+#endif
+
+/* Memory management */
+
+#if CONFIG_MM_REGIONS > 1
+void arm64_addregion(void);
+#else
+# define arm64_addregion()
+#endif
+
+/* Networking */
+
+/* Defined in board/xyz_network.c for board-specific Ethernet
+ * implementations, or chip/xyx_ethernet.c for chip-specific Ethernet
+ * implementations, or common/arm_etherstub.c for a corner case where the
+ * network is enabled yet there is no Ethernet driver to be initialized.
+ *
+ * Use of common/arm_etherstub.c is deprecated. The preferred mechanism is
+ * to use CONFIG_NETDEV_LATEINIT=y to suppress the call to
+ * arm_netinitialize() in up_initialize(). Then this stub would not be
+ * needed.
+ */
+
+#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT)
+void arm64_netinitialize(void);
+#else
+# define arm64_netinitialize()
+#endif
+
+/* USB */
+
+#ifdef CONFIG_USBDEV
+void arm_usbinitialize(void);
+void arm_usbuninitialize(void);
+#else
+# define arm_usbinitialize()
+# define arm_usbuninitialize()
+#endif
+
+/* Debug */
Review Comment:
please add blank after all comment
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
+EXTERN char _srodata[]; /* Start of .rodata */
+EXTERN char _erodata[]; /* End+1 of .rodata */
+EXTERN char _szrodata[]; /* Size of .rodata */
+EXTERN const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
+EXTERN char _sdata[]; /* Start of .data */
+EXTERN char _edata[]; /* End+1 of .data */
+EXTERN char _sbss[]; /* Start of .bss */
+EXTERN char _ebss[]; /* End+1 of .bss */
+EXTERN char _szdata[]; /* Size of data(.data + .bss) */
+EXTERN char _e_initstack[]; /* End+1 of .initstack */
+
+# define _START_TEXT _stext
+# define _END_TEXT _etext
+# define _START_BSS _sbss
+# define _END_BSS _ebss
+# define _DATA_INIT _eronly
+# define _START_DATA _sdata
+# define _END_DATA _edata
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tak_new);
+
+/* Low level initialization provided by chip logic */
+
+void arm64_chip_boot(void);
+
+int arm64_psci_init(const char *method);
+
+void __start(void);
+void arm64_secondary_start(void);
+
+/* Context switching */
+
+void arm64_fullcontextrestore(uint64_t * restoreregs) noreturn_function;
+void arm64_switchcontext(uint64_t ** saveregs, uint64_t *restoreregs);
+void arm64_context_snapshot(void *savereg);
+
+/* Signal handling **********************************************************/
+
+void arm64_sigdeliver(void);
+
+/* Power management *********************************************************/
+
+#ifdef CONFIG_PM
+void arm64_pminitialize(void);
+#else
+# define arm64_pminitialize()
+#endif
+
+/* Interrupt handling */
+
+/* Exception handling logic unique to the Cortex-A and Cortex-R families
+ * (but should be back-ported to the ARM7 and ARM9 families).
+ */
+
+/* Interrupt acknowledge and dispatch */
+
+uint64_t *arm64_doirq(int irq, uint64_t * regs);
+
+/* Paging support */
+
+#ifdef CONFIG_PAGING
+void arm64_pginitialize(void);
+#else /* CONFIG_PAGING */
+# define arm64_pginitialize()
+#endif /* CONFIG_PAGING */
+
+uint64_t * arm64_syscall_switch(uint64_t * regs);
+int arm64_syscall(uint64_t * regs);
+
+#ifdef USE_SERIALDRIVER
+void arm64_serialinit(void);
+#endif
+
+#ifdef USE_EARLYSERIALINIT
+void arm64_earlyserialinit(void);
+#endif
+
+#ifdef CONFIG_RPMSG_UART
+void rpmsg_serialinit(void);
+#endif
+
+#ifdef CONFIG_LWL_CONSOLE
+void lwlconsole_init(void);
Review Comment:
remove
##########
arch/arm64/src/common/arm64_gicv3.c:
##########
@@ -0,0 +1,623 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_gicv3.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <sched/sched.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_fatal.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+#define GICR_TYPER_NR_PPIS(r) \
+ ({ \
+ unsigned int __ppinum = ((r) >> 27) & 0x1f; \
+ unsigned int __nr_ppis = 16; \
+ if (__ppinum == 1 || __ppinum == 2) \
+ __nr_ppis += __ppinum * 32; \
+ __nr_ppis; \
+ })
+
+/* selects redistributor SGI_base for current core for PPI and SGI
+ * selects distributor base for SPI
+ * The macro translates to distributor base for GICv2 and GICv1
+ */
+#define GET_DIST_BASE(intid) ((intid < GIC_SPI_INT_BASE) ? \
+ (gic_get_rdist() + GICR_SGI_BASE_OFF) \
+ : GIC_DIST_BASE)
+
+#define IGROUPR_VAL 0xFFFFFFFFU
+
+/* Redistributor base addresses for each core */
+
+unsigned long gic_rdists[CONFIG_SMP_NCPUS];
+
+/***************************************************************************
+ * Private Functions
+ ***************************************************************************/
+
+/* Memory bit manipulation functions */
+
+static inline void sys_set_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static inline void sys_clear_bit(unsigned long addr, unsigned int bit)
+{
+ uint32_t temp = *(volatile uint32_t *)addr;
+
+ *(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static inline unsigned long gic_get_rdist(void)
+{
+ return gic_rdists[this_cpu()];
+}
+
+static inline uint32_t read_gicd_wait_rwp(void)
+{
+ uint32_t value;
+
+ value = getreg32(GICD_CTLR);
+
+ while (value & BIT(GICD_CTLR_RWP))
+ {
+ value = getreg32(GICD_CTLR);
+ }
+
+ return value;
+}
+
+/* Wait for register write pending
+ * TODO: add timed wait
+ */
+
+static int gic_wait_rwp(uint32_t intid)
+{
+ uint32_t rwp_mask;
+ unsigned long base;
+
+ if (intid < GIC_SPI_INT_BASE)
+ {
+ base = (gic_get_rdist() + GICR_CTLR);
+ rwp_mask = BIT(GICR_CTLR_RWP);
+ }
+ else
+ {
+ base = GICD_CTLR;
+ rwp_mask = BIT(GICD_CTLR_RWP);
+ }
+
+ while (getreg32(base) & rwp_mask)
+ {
+ }
+
+ return 0;
+}
+
+void arm64_gic_irq_set_priority(unsigned int intid, unsigned int prio,
+ uint32_t flags)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t shift;
+ uint32_t val;
+ unsigned long base = GET_DIST_BASE(intid);
+
+ /* Disable the interrupt */
+
+ putreg32(mask, ICENABLER(base, idx));
+ gic_wait_rwp(intid);
+
+ /* PRIORITYR registers provide byte access */
+
+ putreg8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+
+ /* Interrupt type config */
+
+ if (!GIC_IS_SGI(intid))
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
+
+ val = getreg32(ICFGR(base, idx));
+ val &= ~(GICD_ICFGR_MASK << shift);
+ if (flags & IRQ_TYPE_EDGE)
+ {
+ val |= (GICD_ICFGR_TYPE << shift);
+ }
+
+ putreg32(val, ICFGR(base, idx));
+ }
+}
+
+void arm64_gic_irq_enable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+
+ /* Affinity routing is enabled for Non-secure state (GICD_CTLR.ARE_NS
+ * is set to '1' when GIC distributor is initialized) ,so need to set
+ * SPI's affinity, now set it to be the PE on which it is enabled.
+ */
+
+ if (GIC_IS_SPI(intid))
+ {
+ putreg64(MPIDR_TO_CORE(GET_MPIDR()),
+ IROUTER(GET_DIST_BASE(intid), intid));
+ }
+}
+
+void arm64_gic_irq_disable(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+
+ putreg32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
+
+ /* poll to ensure write is complete */
+
+ gic_wait_rwp(intid);
+}
+
+bool arm64_gic_irq_is_enabled(unsigned int intid)
+{
+ uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
+ uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+ uint32_t val;
+
+ val = getreg32(ISENABLER(GET_DIST_BASE(intid), idx));
+
+ return (val & mask) != 0;
+}
+
+unsigned int arm64_gic_get_active(void)
+{
+ int intid;
+
+ /* (Pending -> Active / AP) or (AP -> AP) */
+
+ intid = read_sysreg(ICC_IAR1_EL1);
+
+ return intid;
+}
+
+void arm64_gic_eoi(unsigned int intid)
+{
+ /* Interrupt request deassertion from peripheral to GIC happens
+ * by clearing interrupt condition by a write to the peripheral
+ * register. It is desired that the write transfer is complete
+ * before the core tries to change GIC state from 'AP/Active' to
+ * a new state on seeing 'EOI write'.
+ * Since ICC interface writes are not ordered against Device
+ * memory writes, a barrier is required to ensure the ordering.
+ * The dsb will also ensure *completion* of previous writes with
+ * DEVICE nGnRnE attribute.
+ */
+
+ __DSB();
+
+ /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
+
+ write_sysreg(intid, ICC_EOIR1_EL1);
+}
+
+int gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
+ uint16_t target_list)
+{
+ uint32_t aff3;
+ uint32_t aff2;
+ uint32_t aff1;
+ uint64_t sgi_val;
+
+ assert(GIC_IS_SGI(sgi_id));
+
+ /* Extract affinity fields from target */
+
+ aff1 = MPIDR_AFFLVL(target_aff, 1);
+ aff2 = MPIDR_AFFLVL(target_aff, 2);
+ aff3 = MPIDR_AFFLVL(target_aff, 3);
+
+ sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF,
+ target_list);
+
+ __DSB();
+ write_sysreg(sgi_val, ICC_SGI1R);
+ __ISB();
+
+ return 0;
+}
+
+/* Wake up GIC redistributor.
+ * clear ProcessorSleep and wait till ChildAsleep is cleared.
+ * ProcessSleep to be cleared only when ChildAsleep is set
+ * Check if redistributor is not powered already.
+ */
+
+static void gicv3_rdist_enable(unsigned long rdist)
+{
+ if (!(getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)))
+ {
+ return;
+ }
+
+ sys_clear_bit(rdist + GICR_WAKER, GICR_WAKER_PS);
+ while (getreg32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))
+ {
+ }
+}
+
+/* Initialize the cpu interface. This should be called by each core. */
+
+static void gicv3_cpuif_init(void)
+{
+ uint32_t icc_sre;
+ uint32_t intid;
+
+ unsigned long base = gic_get_rdist() + GICR_SGI_BASE_OFF;
+
+ /* Disable all sgi ppi */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0));
+
+ /* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */
+
+ gic_wait_rwp(0);
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, 0));
+
+ /* Configure all SGIs/PPIs as G1S or G1NS depending on Zephyr
+ * is run in EL1S or EL1NS respectively.
+ * All interrupts will be delivered as irq
+ */
+
+ putreg32(IGROUPR_VAL, IGROUPR(base, 0));
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, 0));
+
+ /* Configure default priorities for SGI 0:15 and PPI 0:15. */
+
+ for (intid = 0; intid < GIC_SPI_INT_BASE;
+ intid += GIC_NUM_PRI_PER_REG)
+ {
+ putreg32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
+ }
+
+ /* Configure PPIs as level triggered */
+
+ putreg32(0, ICFGR(base, 1));
+
+ /* Check if system interface can be enabled.
+ * 'icc_sre_el3' needs to be configured at 'EL3'
+ * to allow access to 'icc_sre_el1' at 'EL1'
+ * eg: z_arch_el3_plat_init can be used by platform.
+ */
+
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ if (!(icc_sre & ICC_SRE_ELX_SRE_BIT))
+ {
+ icc_sre =
+ (icc_sre | ICC_SRE_ELX_SRE_BIT | ICC_SRE_ELX_DIB_BIT |
+ ICC_SRE_ELX_DFB_BIT);
+ write_sysreg(icc_sre, ICC_SRE_EL1);
+ icc_sre = read_sysreg(ICC_SRE_EL1);
+
+ assert(icc_sre & ICC_SRE_ELX_SRE_BIT);
+ }
+
+ write_sysreg(GIC_IDLE_PRIO, ICC_PMR_EL1);
+
+ /* Allow group1 interrupts */
+
+ write_sysreg(1, ICC_IGRPEN1_EL1);
+}
+
+static void gicv3_dist_init(void)
+{
+ unsigned int num_ints;
+ unsigned int intid;
+ unsigned int idx;
+ unsigned long base = GIC_DIST_BASE;
+
+ num_ints = getreg32(GICD_TYPER);
+ num_ints &= GICD_TYPER_ITLINESNUM_MASK;
+ num_ints = (num_ints + 1) << 5;
+
+ /* Disable the distributor */
+
+ putreg32(0, GICD_CTLR);
+ gic_wait_rwp(GIC_SPI_INT_BASE);
+
+#if 0
+
+ /* Before configuration, we need to check whether
+ * the GIC single security state mode is supported.
+ * Make sure GICD_CTRL_NS is 1.
+ */
+
+ sys_set_bit(GICD_CTLR, GICD_CTRL_NS);
+ __ASSERT(sys_test_bit(GICD_CTLR,
+ GICD_CTRL_NS),
+ "Current GIC does not support single security state");
+#endif
+
+ /* Default configuration of all SPIs */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_INTR_PER_REG)
+ {
+ idx = intid / GIC_NUM_INTR_PER_REG;
+
+ /* Disable interrupt */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICENABLER(base, idx));
+
+ /* Clear pending */
+
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ ICPENDR(base, idx));
+ putreg32(IGROUPR_VAL, IGROUPR(base, idx));
+ putreg32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
+ IGROUPMODR(base, idx));
+ }
+
+ /* wait for rwp on GICD */
+
+ gic_wait_rwp(GIC_SPI_INT_BASE);
+
+ /* Configure default priorities for all SPIs. */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_PRI_PER_REG)
+ {
+ putreg32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
+ }
+
+ /* Configure all SPIs as active low, level triggered by default */
+
+ for (intid = GIC_SPI_INT_BASE; intid < num_ints;
+ intid += GIC_NUM_CFG_PER_REG)
+ {
+ idx = intid / GIC_NUM_CFG_PER_REG;
+ putreg32(0, ICFGR(base, idx));
+ }
+
+ /* Enable distributor with ARE */
+
+ putreg32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS),
+ GICD_CTLR);
+#if 0
+
+ /* TODO: ARMv8-R support
+ *
+ * For GIC single security state(ARMv8-R), the config means
+ * the GIC is under single security state which has
+ * only two groups:
+ * group 0 and group 1.
+ * Then set GICD_CTLR_ARE and GICD_CTLR_ENABLE_G1 to enable Group 1
+ * interrupt.
+ * Since the GICD_CTLR_ARE and GICD_CTRL_ARE_S share BIT(4), and
+ * similarly the GICD_CTLR_ENABLE_G1 and GICD_CTLR_ENABLE_G1NS share
+ * BIT(1), we can reuse them.
+ */
+
+ putreg32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS),
+ GICD_CTLR);
+#endif
+}
+
+void up_enable_irq(int irq)
+{
+ arm64_gic_irq_enable(irq);
+}
+
+void up_disable_irq(int irq)
+{
+ arm64_gic_irq_disable(irq);
+}
+
+/***************************************************************************
+ * Name: arm64_decodeirq
+ *
+ * Description:
+ * This function is called from the IRQ vector handler in arm64_vectors.S.
+ * At this point, the interrupt has been taken and the registers have
+ * been saved on the stack. This function simply needs to determine the
+ * the irq number of the interrupt and then to call arm_doirq to dispatch
+ * the interrupt.
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area on the stack.
+ ***************************************************************************/
+
+uint64_t * arm64_decodeirq(uint64_t * regs)
+{
+ int irq;
+
+ /* Read the interrupt acknowledge register and get the interrupt ID */
+
+ irq = arm64_gic_get_active();
+
+ /* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending
+ * interrupt.
+ */
+
+ DEBUGASSERT(irq < NR_IRQS || irq == 1023);
+ if (irq < NR_IRQS)
+ {
+ /* Dispatch the interrupt */
+
+ regs = arm64_doirq(irq, regs);
+ }
+
+ /* Write to the end-of-interrupt register */
+
+ arm64_gic_eoi(irq);
+
+ return regs;
+}
+
+static int gic_validate_dist_version(void)
+{
+ uint32_t typer;
+ bool has_rss;
+ uint32_t reg = getreg32(GICD_PIDR2) & GICD_PIDR2_ARCH_MASK;
+ int spis;
+ int espis;
+
+ if (reg == GICD_PIDR2_ARCH_GICV3)
+ {
+ sinfo("GICv3 version detect\n");
+ }
+ else if (reg == GICD_PIDR2_ARCH_GICV4)
+ {
+ sinfo("GICv4 version detect\n");
+ }
+ else
+ {
+ sinfo("No GIC version detect\n");
+ return -ENODEV;
+ }
+
+ /* Find out how many interrupts are supported. */
+
+ typer = getreg32(GICD_TYPER);
+ spis = MIN(GICD_TYPER_SPIS(typer), 1020U) - 32;
+ espis = GICD_TYPER_ESPIS(typer);
+
+ sinfo("GICD_TYPER = 0x%x\n", typer);
+ sinfo("%d SPIs implemented\n", spis);
+ sinfo("%d Extended SPIs implemented\n", espis);
+
+ has_rss = !!(typer & GICD_TYPER_RSS);
+ sinfo("Distributor has %sRange Selector support\n", has_rss ? "" : "no ");
+
+ if (typer & GICD_TYPER_MBIS)
+ {
+ sinfo("MBIs is present, But No support\n");
+ }
+
+ return 0;
+}
+
+static int gic_validate_redist_version(void)
+{
+ uint64_t typer;
+ unsigned int ppi_nr;
+ bool has_vlpis = true;
+ bool has_direct_lpi = true;
+ uint32_t reg;
+ unsigned long redist_base = gic_get_rdist();
+
+ ppi_nr = (~0U);
+ reg = getreg32(redist_base +
+ GICR_PIDR2) & GICR_PIDR2_ARCH_MASK;
+ if (reg != GICR_PIDR2_ARCH_GICV3 &&
+ reg != GICR_PIDR2_ARCH_GICV4)
+ {
+ sinfo("No redistributor present 0x%lx\n", redist_base);
+ return -ENODEV;
+ }
+
+ typer = getreg64(redist_base + GICR_TYPER);
+ has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
+ has_direct_lpi &= !!(typer & GICR_TYPER_DIRECTLPIS);
+ ppi_nr = MIN(GICR_TYPER_NR_PPIS(typer), ppi_nr);
+
+ if (ppi_nr == (~0U))
+ {
+ ppi_nr = 0;
+ }
+
+ sinfo("GICD_TYPER = 0x%"PRIx64"\n", typer);
+ sinfo("%d PPIs implemented\n", ppi_nr);
+ sinfo("%sVLPI support, %sdirect LPI support\n", !has_vlpis ? "no " : "",
+ !has_direct_lpi ? "no " : "");
+
+ return 0;
+}
+
+static void __arm64_gic_init(void)
Review Comment:
remove __ prefix
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
+EXTERN char _srodata[]; /* Start of .rodata */
+EXTERN char _erodata[]; /* End+1 of .rodata */
+EXTERN char _szrodata[]; /* Size of .rodata */
+EXTERN const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
+EXTERN char _sdata[]; /* Start of .data */
+EXTERN char _edata[]; /* End+1 of .data */
+EXTERN char _sbss[]; /* Start of .bss */
+EXTERN char _ebss[]; /* End+1 of .bss */
+EXTERN char _szdata[]; /* Size of data(.data + .bss) */
+EXTERN char _e_initstack[]; /* End+1 of .initstack */
+
+# define _START_TEXT _stext
+# define _END_TEXT _etext
+# define _START_BSS _sbss
+# define _END_BSS _ebss
+# define _DATA_INIT _eronly
+# define _START_DATA _sdata
+# define _END_DATA _edata
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tak_new);
+
+/* Low level initialization provided by chip logic */
+
+void arm64_chip_boot(void);
+
+int arm64_psci_init(const char *method);
+
+void __start(void);
+void arm64_secondary_start(void);
+
+/* Context switching */
+
+void arm64_fullcontextrestore(uint64_t * restoreregs) noreturn_function;
+void arm64_switchcontext(uint64_t ** saveregs, uint64_t *restoreregs);
+void arm64_context_snapshot(void *savereg);
+
+/* Signal handling **********************************************************/
+
+void arm64_sigdeliver(void);
+
+/* Power management *********************************************************/
+
+#ifdef CONFIG_PM
+void arm64_pminitialize(void);
+#else
+# define arm64_pminitialize()
+#endif
+
+/* Interrupt handling */
+
+/* Exception handling logic unique to the Cortex-A and Cortex-R families
+ * (but should be back-ported to the ARM7 and ARM9 families).
+ */
+
+/* Interrupt acknowledge and dispatch */
+
+uint64_t *arm64_doirq(int irq, uint64_t * regs);
+
+/* Paging support */
+
+#ifdef CONFIG_PAGING
+void arm64_pginitialize(void);
+#else /* CONFIG_PAGING */
+# define arm64_pginitialize()
+#endif /* CONFIG_PAGING */
+
+uint64_t * arm64_syscall_switch(uint64_t * regs);
+int arm64_syscall(uint64_t * regs);
+
+#ifdef USE_SERIALDRIVER
+void arm64_serialinit(void);
+#endif
+
+#ifdef USE_EARLYSERIALINIT
+void arm64_earlyserialinit(void);
+#endif
+
+#ifdef CONFIG_RPMSG_UART
+void rpmsg_serialinit(void);
+#endif
+
+#ifdef CONFIG_LWL_CONSOLE
+void lwlconsole_init(void);
+#endif
+
+/* DMA */
+
+#ifdef CONFIG_ARCH_DMA
+void weak_function arm_dma_initialize(void);
Review Comment:
arm_ -> arm64_
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
Review Comment:
why not use container_of directly
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
Review Comment:
where is ROUND_DOWN defined
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
+EXTERN char _srodata[]; /* Start of .rodata */
+EXTERN char _erodata[]; /* End+1 of .rodata */
+EXTERN char _szrodata[]; /* Size of .rodata */
+EXTERN const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
+EXTERN char _sdata[]; /* Start of .data */
+EXTERN char _edata[]; /* End+1 of .data */
+EXTERN char _sbss[]; /* Start of .bss */
+EXTERN char _ebss[]; /* End+1 of .bss */
+EXTERN char _szdata[]; /* Size of data(.data + .bss) */
+EXTERN char _e_initstack[]; /* End+1 of .initstack */
+
+# define _START_TEXT _stext
+# define _END_TEXT _etext
+# define _START_BSS _sbss
+# define _END_BSS _ebss
+# define _DATA_INIT _eronly
+# define _START_DATA _sdata
+# define _END_DATA _edata
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tak_new);
+
+/* Low level initialization provided by chip logic */
+
+void arm64_chip_boot(void);
+
+int arm64_psci_init(const char *method);
+
+void __start(void);
+void arm64_secondary_start(void);
+
+/* Context switching */
+
+void arm64_fullcontextrestore(uint64_t * restoreregs) noreturn_function;
+void arm64_switchcontext(uint64_t ** saveregs, uint64_t *restoreregs);
+void arm64_context_snapshot(void *savereg);
+
+/* Signal handling **********************************************************/
+
+void arm64_sigdeliver(void);
+
+/* Power management *********************************************************/
+
+#ifdef CONFIG_PM
+void arm64_pminitialize(void);
+#else
+# define arm64_pminitialize()
+#endif
+
+/* Interrupt handling */
+
+/* Exception handling logic unique to the Cortex-A and Cortex-R families
+ * (but should be back-ported to the ARM7 and ARM9 families).
+ */
+
+/* Interrupt acknowledge and dispatch */
+
+uint64_t *arm64_doirq(int irq, uint64_t * regs);
+
+/* Paging support */
+
+#ifdef CONFIG_PAGING
+void arm64_pginitialize(void);
+#else /* CONFIG_PAGING */
+# define arm64_pginitialize()
+#endif /* CONFIG_PAGING */
+
+uint64_t * arm64_syscall_switch(uint64_t * regs);
+int arm64_syscall(uint64_t * regs);
Review Comment:
please remove space after all *
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
Review Comment:
interrupt stack isn't thread stack, let remove THREAD_ prefix from STACK_ARRAY_DEFINE_EXTERN
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
+EXTERN char _srodata[]; /* Start of .rodata */
+EXTERN char _erodata[]; /* End+1 of .rodata */
+EXTERN char _szrodata[]; /* Size of .rodata */
+EXTERN const uint64_t _eronly; /* End+1 of read only section (.text + .rodata) */
Review Comment:
why not _eronly[]
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
Review Comment:
remove, let's call THREAD_STACK_ARRAY_DEFINE with 1
##########
arch/arm64/src/common/arm64_internal.h:
##########
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_internal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <nuttx/arch.h>
+# include <sys/types.h>
+# include <stdint.h>
+#endif
+
+#include "arm64_arch.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine which (if any) console driver to use. If a console is enabled
+ * and no other console device is specified, then a serial console is
+ * assumed.
+ */
+
+#ifndef CONFIG_DEV_CONSOLE
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+#else
+# if defined(CONFIG_LWL_CONSOLE)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# elif defined(CONFIG_CONSOLE_SYSLOG)
+# undef USE_SERIALDRIVER
+# undef USE_EARLYSERIALINIT
+# else
+# define USE_SERIALDRIVER 1
+# define USE_EARLYSERIALINIT 1
+# endif
+#endif
+
+/* If some other device is used as the console, then the serial driver may
+ * still be needed. Let's assume that if the upper half serial driver is
+ * built, then the lower half will also be needed. There is no need for
+ * the early serial initialization in this case.
+ */
+
+#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL)
+# define USE_SERIALDRIVER 1
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/* If the floating point unit is present and enabled, then save the
+ * floating point registers as well as normal ARM registers.
+ */
+
+#define arm64_savestate(regs) (regs = (uint64_t *)CURRENT_REGS)
+#define arm64_restorestate(regs) (CURRENT_REGS = regs)
+
+/* This is the value used to mark the stack for subsequent stack monitoring
+ * logic.
+ */
+
+#define STACK_COLOR 0xdeaddead
+#define HEAP_COLOR 'h'
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* AArch64 the stack-pointer must be 128-bit aligned */
+
+#define STACK_ALIGNMENT 16
+
+/* Stack alignment macros */
+
+#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1)
+#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK)
+#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
+
+struct __attribute__((__packed__)) thread_stack_element
+{
+ char data;
+};
+
+#define STACK_PTR_ALIGN(ptr) ROUND_DOWN((ptr), STACK_ALIGNMENT)
+
+#define THREAD_STACK_DEFINE(sym, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE(sym, n, size) \
+ struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define THREAD_STACK_DEFINE_EXTERN(sym, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[size]
+
+#define THREAD_STACK_ARRAY_DEFINE_EXTERN(sym, n, size) \
+ EXTERN struct thread_stack_element locate_data(".initstack") \
+ aligned_data(STACK_ALIGNMENT) sym[n][size]
+
+#define STACK_PTR_TO_FRAME(type, ptr) \
+ (type *)((ptr) - sizeof(type))
+
+#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK)
+
+#ifdef CONFIG_SMP
+
+/* The size of interrupt and idle stack. This is the configured
+ * value aligned the 8-bytes as required by the ARM EABI.
+ */
+
+#define SMP_STACK_SIZE STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE)
+
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_cpu_idlestackalloc, CONFIG_SMP_NCPUS,
+ SMP_STACK_SIZE);
+THREAD_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS,
+ INTSTACK_SIZE);
+uintptr_t arm64_intstack_alloc(void);
+uintptr_t arm64_intstack_top(void);
+#else
+/* idle thread stack for primary core */
+
+THREAD_STACK_DEFINE_EXTERN(g_idle_stack, CONFIG_IDLETHREAD_STACKSIZE);
+THREAD_STACK_DEFINE_EXTERN(g_interrupt_stack, INTSTACK_SIZE);
+#endif
+
+/* This is the beginning of heap as provided from arm64_head.S.
+ * This is the first address in DRAM after the loaded
+ * program + bss + idle stack. The end of the heap is
+ * CONFIG_RAM_END
+ */
+
+/* Address of the saved user stack pointer */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+EXTERN uint64_t g_intstackalloc; /* Allocated stack base */
+EXTERN uint64_t g_intstacktop; /* Initial top of interrupt stack */
+#else
+# error CONFIG_ARCH_INTERRUPTSTACK must be defined (4096 at least) at arm64
+#endif
+
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint64_t storage locations! They are only used
+ * meaningfully in the following way:
+ *
+ * - The linker script defines, for example, the symbol_sdata.
+ * - The declaration extern uint64_t _sdata; makes C happy. C will believe
+ * that the value _sdata is the address of a uint64_t variable _data
+ * (it is not!).
+ * - We can recover the linker value then by simply taking the address of
+ * of _data. like: uint64_t *pdata = &_sdata;
+ *
+ * Memory layout for Nuttx at arm64 for FLAT Build
+ *
+ * +-------------------------+ <- RAM BASE
+ * | |
+ * |<<<<<<<<<<<<<<<<<<<<<<<<<| <- LOAD_BASE
+ * | text(code) section |
+ * | vector table |
+ * +-------------------------+-- page align(4096)
+ * | rodata section |
+ * +-------------------------+-- page align(4096)
+ * | data/bss section |
+ * +-------------------------+-- page align(4096)
+ * | initstack section |
+ * +-------------------------+-- page align(4096)
+ * | heap alloc area |
+ * | |
+ * | |
+ * | |
+ * +-------------------------+
+ *
+ * Note:
+ * 1. initstack is for idle_thread and interrupt stack,
+ * it has dedicated stack for IRQ handler in arm64
+ * 2. Every section with different memory attribute,
+ * please check mmu_nxrt_regions at arm64_mmu.c
+ *
+ * please check dramboot.ld at specified platform for more detail
+ */
+
+EXTERN char _stext[]; /* Start of .text */
+EXTERN char _etext[]; /* End of .text */
+EXTERN char _sztext[]; /* Size of .text */
Review Comment:
let's remove all _szxxx? since we can compute them from _exxxx - _sxxxx
##########
arch/arm64/src/common/arm64_initialstate.c:
##########
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_initialstate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <arch/limits.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/drivers/drivers.h>
+#include <nuttx/fs/loop.h>
+#include <nuttx/net/loopback.h>
+#include <nuttx/net/tun.h>
+#include <nuttx/net/telnet.h>
+#include <nuttx/note/note_driver.h>
+#include <nuttx/syslog/syslog_console.h>
+#include <nuttx/serial/pty.h>
+#include <nuttx/crypto/crypto.h>
+#include <nuttx/power/pm.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "chip.h"
+#include "arm64_fatal.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void arm64_new_task(struct tcb_s * tcb)
+{
+ char * stack_ptr = tcb->stack_base_ptr + tcb->adj_stack_size;
+ struct regs_context * pinitctx;
+
+#ifdef CONFIG_ARCH_FPU
+ struct fpu_reg * pfpuctx;
+ pfpuctx = STACK_PTR_TO_FRAME(struct fpu_reg, stack_ptr);
+ tcb->xcp.fpu_regs = pfpuctx;
+
+ /* set fpu context */
+
+ arm64_init_fpu(tcb);
+ stack_ptr = (char *)pfpuctx;
+#endif
+
+ pinitctx = STACK_PTR_TO_FRAME(struct regs_context, stack_ptr);
+ memset(pinitctx, 0, sizeof(struct regs_context));
+ pinitctx->elr = (uint64_t)tcb->start;
+
+ /* Keep using SP_EL1 */
+
+ pinitctx->spsr = SPSR_MODE_EL1H;
+
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ pinitctx->spsr |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT);
+#endif /* CONFIG_SUPPRESS_INTERRUPTS */
+
+ pinitctx->sp_elx = (uint64_t)pinitctx;
+ pinitctx->sp_el0 = (uint64_t)pinitctx;
+ pinitctx->exe_depth = 0;
+ pinitctx->tpidr_el0 = (uint64_t)tcb;
+ pinitctx->tpidr_el1 = (uint64_t)tcb;
+
+ tcb->xcp.regs = (uint64_t *)pinitctx;
+}
+
+/****************************************************************************
+ * Name: up_initial_state
+ *
+ * Description:
+ * A new thread is being started and a new TCB has been created. This
+ * function is called to initialize the processor specific portions of
+ * the new TCB.
+ *
+ * This function must setup the initial architecture registers and/or
+ * stack so that execution will begin at tcb->start on the next context
+ * switch.
+ *
+ ****************************************************************************/
+
+void up_initial_state(struct tcb_s *tcb)
+{
+ struct xcptcontext *xcp = &tcb->xcp;
+
+ memset(xcp, 0, sizeof(struct xcptcontext));
+
+ if (tcb->pid < CONFIG_SMP_NCPUS)
+ {
+ /* Initialize the idle thread stack */
+#ifdef CONFIG_SMP
+ tcb->stack_alloc_ptr = (void *)(g_cpu_idlestackalloc[0]);
Review Comment:
so the second idle thread point to the same buffer as the first idle thread
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915936543
##########
arch/arm64/include/types.h:
##########
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm64/include/types.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through sys/types.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_TYPES_H
+#define __ARCH_ARM64_INCLUDE_TYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Type Declarations
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* These are the sizes of the standard integer types. NOTE that these type
+ * names have a leading underscore character. This file will be included
+ * (indirectly) by include/stdint.h and typedef'ed to the final name without
+ * the underscore character. This roundabout way of doings things allows
+ * the stdint.h to be removed from the include/ directory in the event that
+ * the user prefers to use the definitions provided by their toolchain header
+ * files
+ */
+
+typedef signed char _int8_t;
+typedef unsigned char _uint8_t;
+
+typedef signed short _int16_t;
+typedef unsigned short _uint16_t;
+
+typedef signed int _int32_t;
+typedef unsigned int _uint32_t;
+
+typedef signed long _int64_t;
+typedef unsigned long _uint64_t;
+#define __INT64_DEFINED
+
+typedef _int64_t _intmax_t;
+typedef _uint64_t _uintmax_t;
+
+#if defined(__WCHAR_TYPE__)
+typedef __WCHAR_TYPE__ _wchar_t;
+#else
+typedef int _wchar_t;
+#endif
+
+#if defined(__SIZE_TYPE__)
+/* If __SIZE_TYPE__ is defined we define ssize_t based on size_t.
+ * We simply change "unsigned" to "signed" for this single definition
+ * to make sure ssize_t and size_t only differ by their signedness.
+ */
+
+#define unsigned signed
+typedef __SIZE_TYPE__ _ssize_t;
+#undef unsigned
+typedef __SIZE_TYPE__ _size_t;
+
+#elif defined(CONFIG_ARCH_SIZET_LONG)
+
+typedef signed long _ssize_t;
+typedef unsigned long _size_t;
+
+#else
+
+typedef signed int _ssize_t;
+typedef unsigned int _size_t;
+
+#endif
+
+/* This is the size of the interrupt state save returned by
+ * up_irq_save()
+ */
+
+typedef unsigned int irqstate_t;
Review Comment:
https://developer.arm.com/documentation/ddi0595/2021-12/AArch64-Registers/DAIF--Interrupt-Mask-Bits
the daif register is only use lower 32bit, high 32bit is Reserved
at present, most OS kernel only access the lower 32bit.
but if it necessary to change to long, i will change
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r916004637
##########
arch/arm64/src/Makefile:
##########
@@ -0,0 +1,213 @@
+############################################################################
+# arch/arm64/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+include chip/Make.defs
+
+#ARCH_SUBDIR = arm64
+#ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
Review Comment:
but for following code, it's used, and arm is samed code:
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
INCLUDES += ${shell $(INCDIR) "$(CC)" $(**ARCH_SRCDIR**)$(DELIM)chip}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(**ARCH_SRCDIR**)$(DELIM)common}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
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[GitHub] [incubator-nuttx] qinwei2004 commented on pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#issuecomment-1184029998
@xiaoxiang781216 @pkarashchenko @hartmannathan
please check again
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r920149689
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,254 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ UNUSED(regs);
+ UNUSED(arg);
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#else
+
+static int arm64_arch_timer_compare_isr(int irq, void *regs, void *arg)
+{
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+ uint64_t next_cycle;
+
+ UNUSED(irq);
+ UNUSED(regs);
+ UNUSED(arg);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ next_cycle = last_cycle + cycle_per_tick;
+
+ if ((uint64_t)(next_cycle - curr_cycle) < MIN_DELAY)
+ {
+ next_cycle += cycle_per_tick;
+ }
+
+ arm64_arch_timer_set_compare(next_cycle);
+ arm64_arch_timer_set_irq_mask(false);
+
+ nxsched_process_timer();
+ return OK;
+}
+
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+/* Notes:
+ *
+ * The origin design for ARMv8-A timer is assigned private timer to
+ * every PE(CPU core), the ARM_ARCH_TIMER_IRQ is a PPI so it's
+ * should be enable at every core.
+ *
+ * But for NuttX, it's design only for primary core to handle timer
+ * interrupt and call nxsched_process_timer at timer tick mode.
+ * So we need only enable timer for primary core
+ *
+ * IMX6 use GPT which is a SPI rather than generic timer to handle
+ * timer interrupt
+ */
+
+void arm64_smp_timer_init(void)
+{
+ uint64_t curr_cycle;
+
+ /* set the initial status of timer0 of each secondary core */
+
+ curr_cycle = arm64_arch_timer_count();
+
+ arm64_arch_timer_set_compare(curr_cycle + cycle_per_tick);
+ arm64_arch_timer_enable(true);
+ up_enable_irq(ARM_ARCH_TIMER_IRQ);
+ arm64_arch_timer_set_irq_mask(false);
+}
+
+#endif
+
+uint64_t arm64_counter_read(void)
+{
+ return arm64_arch_timer_count();
+}
+
+void arm64_timer_delay(long mini_sec)
+{
+ unsigned int timeout;
+ volatile unsigned int new_counter;
Review Comment:
Else perhaps (current or future) compiler could optimize away `new_counter = arm64_counter_read();` in do..while()?
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r920857869
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,619 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do { \
+ if (!(__cond)){ \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
+#else
+#define __MMU_ASSERT(test, fmt, ...)
+#endif
+
+/* We support only 4kB translation granule */
+
+#define PAGE_SIZE_SHIFT 12U
+#define PAGE_SIZE (1U << PAGE_SIZE_SHIFT)
Review Comment:
I was just a bit confused with `#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)`
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r920859238
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,405 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <sys/types.h>
Review Comment:
```suggestion
****************************************************************************/
#include <sys/types.h>
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,405 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <sys/types.h>
+#ifndef __ASSEMBLY__
+# include <stdbool.h>
+#endif
+
+#include <nuttx/config.h>
Review Comment:
Please move before `#include <sys/types.h>`
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,548 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#ifndef __ASSEMBLY__
+ #include <stdint.h>
+#endif
+
+#include "barriers.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BIT(n) ((1UL) << (n))
+#define BIT64(n) ((1ULL) << (n))
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+#define DAIFSET_FIQ_BIT BIT(0)
+#define DAIFSET_IRQ_BIT BIT(1)
+#define DAIFSET_ABT_BIT BIT(2)
+#define DAIFSET_DBG_BIT BIT(3)
+
+#define DAIFCLR_FIQ_BIT BIT(0)
+#define DAIFCLR_IRQ_BIT BIT(1)
+#define DAIFCLR_ABT_BIT BIT(2)
+#define DAIFCLR_DBG_BIT BIT(3)
+
+#define DAIF_FIQ_BIT BIT(6)
+#define DAIF_IRQ_BIT BIT(7)
+#define DAIF_ABT_BIT BIT(8)
+#define DAIF_DBG_BIT BIT(9)
+
+#define DAIF_MASK (0xf << 6)
+
+/* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ *
+ * SCTLR_EL1: System Control Register (EL1)
+ * SCTLR_EL2: System Control Register (EL2)
+ * SCTLR_EL3: System Control Register (EL3)
+ *
+ */
+
+#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(20) | BIT(11))
+
+#define SCTLR_M_BIT BIT(0)
+#define SCTLR_A_BIT BIT(1)
+#define SCTLR_C_BIT BIT(2)
+#define SCTLR_SA_BIT BIT(3)
+#define SCTLR_I_BIT BIT(12)
+
+/* SPSR M[3:0] define
+ *
+ * Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ * SPSR_EL1: Saved Program Status Register (EL1)
+ * SPSR_EL2: Saved Program Status Register (EL2)
+ * SPSR_EL3: Saved Program Status Register (EL3)
+ *
+ * reference to Programmer’s Guide for ARMv8-A
+ * (ARM DEN0024A, ID050815 ), 4.1.2 Stack pointer
+ *
+ * The T suffix, indicates use of the SP_EL0 stack pointer.
+ * The H suffix, indicates use of the SP_ELx stack pointer.
+ *
+ */
+
+#define SPSR_DAIF_SHIFT (6)
+#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE_EL0T (0x0)
+#define SPSR_MODE_EL1T (0x4)
+#define SPSR_MODE_EL1H (0x5)
+#define SPSR_MODE_EL2T (0x8)
+#define SPSR_MODE_EL2H (0x9)
+#define SPSR_MODE_MASK (0xf)
+
+/* CurrentEL: Current Exception Level */
+
+#define MODE_EL_SHIFT (0x2)
+#define MODE_EL_MASK (0x3)
+
+#define MODE_EL3 (0x3)
+#define MODE_EL2 (0x2)
+#define MODE_EL1 (0x1)
+#define MODE_EL0 (0x0)
+
+/* struct arm64_boot_params member offset for assembly code
+ * struct is defined at arm64_cpustart.c
+ */
+
+#define BOOT_PARAM_MPID 0
+#define BOOT_PARAM_SP 8
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
Review Comment:
```suggestion
# define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
```
##########
arch/arm64/include/irq.h:
##########
@@ -0,0 +1,405 @@
+/****************************************************************************
+ * arch/arm64/include/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_IRQ_H
+#define __ARCH_ARM64_INCLUDE_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <sys/types.h>
+#ifndef __ASSEMBLY__
+# include <stdbool.h>
Review Comment:
Please group with `# include <stdint.h>`
##########
arch/arm64/src/common/arm64_fatal.h:
##########
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FATAL_H
+
+/**
+ * @defgroup fatal_apis Fatal error APIs
+ * @ingroup kernel_apis
+ * @{
+ */
+
+#define K_ERR_CPU_EXCEPTION (0)
+#define K_ERR_CPU_MODE32 (1)
+#define K_ERR_SPURIOUS_IRQ (2)
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define __builtin_unreachable() \
+ do { \
+ sinfo("Unreachable code\n"); \
+ PANIC(); \
+ } while (true)
Review Comment:
```suggestion
do \
{ \
sinfo("Unreachable code\n"); \
PANIC(); \
} \
while (true)
```
##########
arch/arm64/src/common/arm64_fatal.c:
##########
@@ -0,0 +1,365 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fatal.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <debug.h>
+#include <assert.h>
+#include <sched.h>
+#include <nuttx/arch.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/tls.h>
+#include <nuttx/board.h>
+#include <arch/chip/chip.h>
+#include <nuttx/syslog/syslog.h>
+#include "sched/sched.h"
+#include "irq/irq.h"
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+#include "arm64_fatal.h"
+#include "arm64_arch_timer.h"
+
+#ifdef CONFIG_ARCH_FPU
+#include "arm64_fpu.h"
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: print_ec_cause
+ ****************************************************************************/
+
+static void print_ec_cause(uint64_t esr)
+{
+ uint32_t ec = (uint32_t)esr >> 26;
+
+ switch (ec)
+ {
+ case 0b000000:
+ {
+ sinfo("Unknown reason\n");
+ break;
+ }
+
+ case 0b000001:
+ {
+ sinfo("Trapped WFI or WFE instruction execution\n");
+ break;
+ }
+
+ case 0b000011:
+ {
+ sinfo(
+ "Trapped MCR or MRC access with (coproc==0b1111) that "
+ "is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000100:
+ {
+ sinfo(
+ "Trapped MCRR or MRRC access with (coproc==0b1111) "
+ "that is not reported using EC 0b000000\n");
+ break;
+ }
+
+ case 0b000101:
+ {
+ sinfo("Trapped MCR or MRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b000110:
+ {
+ sinfo("Trapped LDC or STC access\n");
+ break;
+ }
+
+ case 0b000111:
+ {
+ sinfo(
+ "Trapped access to SVE, Advanced SIMD, or "
+ "floating-point functionality\n");
+ break;
+ }
+
+ case 0b001100:
+ {
+ sinfo("Trapped MRRC access with (coproc==0b1110)\n");
+ break;
+ }
+
+ case 0b001101:
+ {
+ sinfo("Branch Target Exception\n");
+ break;
+ }
+
+ case 0b001110:
+ {
+ sinfo("Illegal Execution state\n");
+ break;
+ }
+
+ case 0b010001:
+ {
+ sinfo("SVC instruction execution in AArch32 state\n");
+ break;
+ }
+
+ case 0b011000:
+ {
+ sinfo(
+ "Trapped MSR, MRS or System instruction execution in "
+ "AArch64 state, that is not reported using EC "
+ "0b000000, 0b000001 or 0b000111\n");
+ break;
+ }
+
+ case 0b011001:
+ {
+ sinfo("Trapped access to SVE functionality\n");
+ break;
+ }
+
+ case 0b100000:
+ {
+ sinfo(
+ "Instruction Abort from a lower Exception level, that "
+ "might be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b100001:
+ {
+ sinfo(
+ "Instruction Abort taken without a change "
+ "in Exception level.\n");
+ break;
+ }
+
+ case 0b100010:
+ {
+ sinfo("PC alignment fault exception.\n");
+ break;
+ }
+
+ case 0b100100:
+ {
+ sinfo(
+ "Data Abort from a lower Exception level, that might "
+ "be using AArch32 or AArch64\n");
+ break;
+ }
+
+ case 0b100101:
+ {
+ sinfo("Data Abort taken without a change in Exception level\n");
+ break;
+ }
+
+ case 0b100110:
+ {
+ sinfo("SP alignment fault exception\n");
+ break;
+ }
+
+ case 0b101000:
+ {
+ sinfo(
+ "Trapped floating-point exception "
+ "taken from AArch32 state\n");
+ break;
+ }
Review Comment:
```suggestion
break;
}
```
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -0,0 +1,548 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+#define ___ARCH_ARM64_SRC_COMMON_ARM64_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Unsigned integer with bit position n set (signed in
+ * assembly language).
+ */
+#ifndef __ASSEMBLY__
+ #include <stdint.h>
+#endif
+
+#include "barriers.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BIT(n) ((1UL) << (n))
+#define BIT64(n) ((1ULL) << (n))
+
+/* Bit mask with bits 0 through n-1 (inclusive) set,
+ * or 0 if n is 0.
+ */
+#define BIT_MASK(n) (BIT(n) - 1)
+#define BIT64_MASK(n) (BIT64(n) - 1ULL)
+
+#define DAIFSET_FIQ_BIT BIT(0)
+#define DAIFSET_IRQ_BIT BIT(1)
+#define DAIFSET_ABT_BIT BIT(2)
+#define DAIFSET_DBG_BIT BIT(3)
+
+#define DAIFCLR_FIQ_BIT BIT(0)
+#define DAIFCLR_IRQ_BIT BIT(1)
+#define DAIFCLR_ABT_BIT BIT(2)
+#define DAIFCLR_DBG_BIT BIT(3)
+
+#define DAIF_FIQ_BIT BIT(6)
+#define DAIF_IRQ_BIT BIT(7)
+#define DAIF_ABT_BIT BIT(8)
+#define DAIF_DBG_BIT BIT(9)
+
+#define DAIF_MASK (0xf << 6)
+
+/* Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ *
+ * SCTLR_EL1: System Control Register (EL1)
+ * SCTLR_EL2: System Control Register (EL2)
+ * SCTLR_EL3: System Control Register (EL3)
+ *
+ */
+
+#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(18) | BIT(16) | \
+ BIT(11) | BIT(5) | BIT(4))
+
+#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
+ BIT(22) | BIT(20) | BIT(11))
+
+#define SCTLR_M_BIT BIT(0)
+#define SCTLR_A_BIT BIT(1)
+#define SCTLR_C_BIT BIT(2)
+#define SCTLR_SA_BIT BIT(3)
+#define SCTLR_I_BIT BIT(12)
+
+/* SPSR M[3:0] define
+ *
+ * Arm® Architecture Registers Armv8, for Armv8-A architecture profile
+ * ( DDI 0595, ID121321 ), defined:
+ * SPSR_EL1: Saved Program Status Register (EL1)
+ * SPSR_EL2: Saved Program Status Register (EL2)
+ * SPSR_EL3: Saved Program Status Register (EL3)
+ *
+ * reference to Programmer’s Guide for ARMv8-A
+ * (ARM DEN0024A, ID050815 ), 4.1.2 Stack pointer
+ *
+ * The T suffix, indicates use of the SP_EL0 stack pointer.
+ * The H suffix, indicates use of the SP_ELx stack pointer.
+ *
+ */
+
+#define SPSR_DAIF_SHIFT (6)
+#define SPSR_DAIF_MASK (0xf << SPSR_DAIF_SHIFT)
+
+#define SPSR_MODE_EL0T (0x0)
+#define SPSR_MODE_EL1T (0x4)
+#define SPSR_MODE_EL1H (0x5)
+#define SPSR_MODE_EL2T (0x8)
+#define SPSR_MODE_EL2H (0x9)
+#define SPSR_MODE_MASK (0xf)
+
+/* CurrentEL: Current Exception Level */
+
+#define MODE_EL_SHIFT (0x2)
+#define MODE_EL_MASK (0x3)
+
+#define MODE_EL3 (0x3)
+#define MODE_EL2 (0x2)
+#define MODE_EL1 (0x1)
+#define MODE_EL0 (0x0)
+
+/* struct arm64_boot_params member offset for assembly code
+ * struct is defined at arm64_cpustart.c
+ */
+
+#define BOOT_PARAM_MPID 0
+#define BOOT_PARAM_SP 8
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define STRINGIFY(x) #x
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/* define MAX(a, b)/MIN(a, b)
+ * The larger/smaller value between a and b.
+ * Arguments are evaluated twice.
+ */
+#ifndef MAX
+# define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef MIN
+# define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
+
+/* MPIDR_EL1, Multiprocessor Affinity Register */
+
+#define MPIDR_AFFLVL_MASK (0xff)
+
+#define MPIDR_AFF0_SHIFT (0)
+#define MPIDR_AFF1_SHIFT (8)
+#define MPIDR_AFF2_SHIFT (16)
+#define MPIDR_AFF3_SHIFT (32)
+
+#define MPIDR_AFFLVL(mpidr, aff_level) \
+ (((mpidr) >> MPIDR_AFF ## aff_level ## _SHIFT) & MPIDR_AFFLVL_MASK)
+
+#define GET_MPIDR() read_sysreg(mpidr_el1)
+#define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL((mpidr), 0)
+#define IS_PRIMARY_CORE() (!MPIDR_TO_CORE(GET_MPIDR()))
+
+/* System register interface to GICv3 */
+
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
+#define ICC_SGI1R S3_0_C12_C11_5
+#define ICC_SRE_EL1 S3_0_C12_C12_5
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_RPR_EL1 S3_0_C12_C11_3
+#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
+#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
+#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
+#define ICC_IAR0_EL1 S3_0_C12_C8_0
+#define ICC_IAR1_EL1 S3_0_C12_C12_0
+#define ICC_EOIR0_EL1 S3_0_C12_C8_1
+#define ICC_EOIR1_EL1 S3_0_C12_C12_1
+#define ICC_SGI0R_EL1 S3_0_C12_C11_7
+
+/* register constants */
+#define ICC_SRE_ELX_SRE_BIT BIT(0)
+#define ICC_SRE_ELX_DFB_BIT BIT(1)
+#define ICC_SRE_ELX_DIB_BIT BIT(2)
+#define ICC_SRE_EL3_EN_BIT BIT(3)
+
+/* ICC SGI macros */
+#define SGIR_TGT_MASK (0xffff)
+#define SGIR_AFF1_SHIFT (16)
+#define SGIR_AFF2_SHIFT (32)
+#define SGIR_AFF3_SHIFT (48)
+#define SGIR_AFF_MASK (0xf)
+#define SGIR_INTID_SHIFT (24)
+#define SGIR_INTID_MASK (0xf)
+#define SGIR_IRM_SHIFT (40)
+#define SGIR_IRM_MASK (0x1)
+#define SGIR_IRM_TO_AFF (0)
+#define SGIR_IRM_TO_ALL (1)
+
+#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
+ ((((uint64_t)(_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
+ (((uint64_t)(_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
+ (((uint64_t)(_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
+ (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
+ (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
+ ((_tgt) & SGIR_TGT_MASK))
+
+/* CPTR_EL2, Architectural Feature Trap Register (EL2) */
+
+#define CPTR_EZ_BIT BIT(8)
+#define CPTR_TFP_BIT BIT(10)
+#define CPTR_TTA_BIT BIT(20)
+#define CPTR_TCPAC_BIT BIT(31)
+#define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
+
+/* CPACR_EL1, Architectural Feature Access Control Register */
+#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
+
+/* SCR_EL3, Secure Configuration Register */
+#define SCR_NS_BIT BIT(0)
+#define SCR_IRQ_BIT BIT(1)
+#define SCR_FIQ_BIT BIT(2)
+#define SCR_EA_BIT BIT(3)
+#define SCR_SMD_BIT BIT(7)
+#define SCR_HCE_BIT BIT(8)
+#define SCR_RW_BIT BIT(10)
+#define SCR_ST_BIT BIT(11)
+#define SCR_RES1 (BIT(4) | BIT(5))
+
+/* HCR_EL2, Hypervisor Configuration Register */
+
+#define HCR_FMO_BIT BIT(3)
+#define HCR_IMO_BIT BIT(4)
+#define HCR_AMO_BIT BIT(5)
+#define HCR_RW_BIT BIT(31)
+
+/* CNTHCTL_EL2 bits definitions */
+
+#define CNTHCTL_EL2_EL1PCEN_EN BIT(1)
+#define CNTHCTL_EL2_EL1PCTEN_EN BIT(0)
+
+/* CNTV_CVAL, Counter-timer Virtual Timer CompareValue register
+ * CNTV_CTL, Counter-timer Virtual Timer Control register
+ */
+
+#define CNTV_CTL_ENABLE_BIT BIT(0)
+#define CNTV_CTL_IMASK_BIT BIT(1)
+
+/* Maximum numbers of translation tables
+ * This option specifies the maximum numbers of translation tables
+ * excluding the base translation table. Based on this, translation
+ * tables are allocated at compile time and used at runtime as needed.
+ * If the runtime need exceeds preallocated numbers of translation
+ * tables, it will result in assert. Number of translation tables
+ * required is decided based on how many discrete memory regions
+ * (both normal and device memory) are present on given platform and
+ * how much granularity is required while assigning attributes
+ * to these memory regions.
+ */
+
+#define CONFIG_MAX_XLAT_TABLES 7
+
+/* Virtual address space size
+ * Allows choosing one of multiple possible virtual address
+ * space sizes. The level of translation table is determined by
+ * a combination of page size and virtual address space size.
+ *
+ * The choice could be: 32, 36, 42, 48
+ */
+
+#define CONFIG_ARM64_VA_BITS 36
+
+/* Physical address space size
+ * Choose the maximum physical address range that the kernel will support.
+ *
+ * The choice could be: 32, 36, 42, 48
+ */
+
+#define CONFIG_ARM64_PA_BITS 36
+
+#define L1_CACHE_SHIFT (6)
+#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
Review Comment:
```suggestion
#define CONFIG_ARM64_PA_BITS 36
#define L1_CACHE_SHIFT (6)
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
```
##########
arch/arm64/src/common/arm64_mmu.c:
##########
@@ -0,0 +1,621 @@
+/***************************************************************************
+ * arch/arm64/src/common/arm64_mmu.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ***************************************************************************/
+
+/***************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_fatal.h"
+#include "arm64_mmu.h"
+
+/***************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* MMU debug option
+ * #define CONFIG_MMU_ASSERT 1
+ * #define CONFIG_MMU_DEBUG 1
+ * #define CONFIG_MMU_DUMP_PTE 1
+ */
+
+#ifdef CONFIG_MMU_DEBUG
+
+#define L0_SPACE ""
+#define L1_SPACE " "
+#define L2_SPACE " "
+#define L3_SPACE " "
+#define XLAT_TABLE_LEVEL_SPACE(level) \
+ (((level) == 0) ? L0_SPACE : \
+ ((level) == 1) ? L1_SPACE : \
+ ((level) == 2) ? L2_SPACE : L3_SPACE)
+#endif
+
+#ifdef CONFIG_MMU_ASSERT
+#define __MMU_ASSERT(__cond, fmt, ...) \
+ do \
+ { \
+ if (!(__cond)) \
+ { \
+ trace_printf(fmt, ## __VA_ARGS__); \
+ PANIC(); \
+ } \
+ } while (false)
Review Comment:
```suggestion
} \
} \
while (false)
```
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902550606
##########
arch/arm64/src/common/arm64_fatal.h:
##########
@@ -72,6 +72,6 @@ void arm64_dump_fatal(struct regs_context * reg);
PANIC(); \
} while (true)
-#endif /*__ASSEMBLY__ */
+#endif // __ASSEMBLY__
Review Comment:
why changed to C++ comments here?
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[GitHub] [incubator-nuttx] qinwei2004 closed pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 closed pull request #6478: arch: arm64: ARMv8-A support for NuttX
URL: https://github.com/apache/incubator-nuttx/pull/6478
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902096217
##########
arch/arm64/include/limits.h:
##########
@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/arm64/include/limits.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_INCLUDE_LIMITS_H__
+#define __ARCH_ARM64_INCLUDE_LIMITS_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <limits.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CHAR_BIT 8
+#define SCHAR_MIN (-SCHAR_MAX - 1)
+#define SCHAR_MAX 127
+#define UCHAR_MAX 255
+
+/* These could be different on machines where char is unsigned */
+
+#ifdef __CHAR_UNSIGNED__
Review Comment:
I have add WCHAR define,
compile and test with qemu
Thanks
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902552374
##########
boards/Kconfig:
##########
@@ -1575,6 +1575,15 @@ config ARCH_BOARD_SABRE_6QUAD
This options selects support for NuttX on the NXP/Freescale Sabre
board featuring the iMX 6Quad CPU.
+
+config ARCH_BOARD_QEMU_A53
Review Comment:
Please revert file permissions
##########
boards/arm64/qemu/qemu-a53/scripts/Make.defs:
##########
@@ -0,0 +1,51 @@
+############################################################################
+# boards/arm64/qemu/qemu-a53/scripts/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/arch/arm64/src/Toolchain.defs
+
+LDSCRIPT = dramboot.ld
+
+ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
+
+
+
+
Review Comment:
I think some of the newlines can be removed
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H
Review Comment:
Please either rename file to `arm64_gicv3.h` or change the macro
##########
tools/ci/testlist/other.dat:
##########
@@ -20,3 +20,7 @@
# Sparc-gaisler-elf toolchain doesn't provide macOS binaries
/sparc
-xx3823:nsh
+
Review Comment:
Please revert file permissions
##########
arch/Kconfig:
##########
@@ -22,6 +22,20 @@ config ARCH_ARM
---help---
The ARM architectures
+config ARCH_ARM64
Review Comment:
Please revert file permissions
##########
tools/ci/docker/linux/Dockerfile:
##########
@@ -87,6 +87,15 @@ RUN mkdir gcc-arm-none-eabi && \
curl -s -L "https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2" \
| tar -C gcc-arm-none-eabi --strip-components 1 -xj
+###############################################################################
Review Comment:
Please revert file permissions
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[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902653872
##########
arch/arm64/include/arch.h:
##########
@@ -0,0 +1,145 @@
+/****************************************************************************
+ * arch/arm64/include/arch.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/arch.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_ARCH_H
+#define __ARCH_ARM64_INCLUDE_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <nuttx/pgalloc.h>
+# include <nuttx/addrenv.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+#if CONFIG_MM_PGSIZE != 4096
+# error Only pages sizes of 4096 are currently supported (CONFIG_ARCH_ADDRENV)
+#endif
+
+#endif /* CONFIG_ARCH_ADDRENV */
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsp
+ ****************************************************************************/
+
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ADDRENV
+/* The task group resources are retained in a single structure, task_group_s
+ * that is defined in the header file nuttx/include/nuttx/sched.h. The type
+ * group_addrenv_t must be defined by platform specific logic in
+ * nuttx/arch/<architecture>/include/arch.h.
+ *
+ * These tables would hold the physical address of the level 2 page tables.
+ * All would be initially NULL and would not be backed up with physical
+ * memory until mappings in the level 2 page table are required.
+ */
+
+struct group_addrenv_s
+{
+ /* Level 1 page table entries for each group section */
+
+ uintptr_t *text[ARCH_TEXT_NSECTS];
+ uintptr_t *data[ARCH_DATA_NSECTS];
+#ifdef CONFIG_BUILD_KERNEL
+ uintptr_t *heap[ARCH_HEAP_NSECTS];
+#ifdef CONFIG_MM_SHM
+ uintptr_t *shm[ARCH_SHM_NSECTS];
+#endif
+
+ /* Initial heap allocation (in bytes). This exists only provide an
+ * indirect path for passing the size of the initial heap to the heap
+ * initialization logic. These operations are separated in time and
+ * architecture. REVISIT: I would like a better way to do this.
+ */
+
+ size_t heapsize;
+#endif
+};
+
+typedef struct group_addrenv_s group_addrenv_t;
+
+/* This type is used when the OS needs to temporarily instantiate a
+ * different address environment. Used in the implementation of
+ *
+ * int up_addrenv_select(group_addrenv_t addrenv, save_addrenv_t *oldenv);
+ * int up_addrenv_restore(save_addrenv_t oldenv);
+ *
+ * In this case, the saved valued in the L1 page table are returned
Review Comment:
s/valued/values/
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902414083
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm);
+
+ __asm__ __volatile__
+ (
+ "hlt %1"
+ : "=r"(reg0)
+ : "i"(SYS_smhcall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* Result from SMC/HVC call
+ * a0-a7 result values from registers 0 to 7
+ */
+
+struct arm64_smccc_res
+{
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+};
+
+typedef struct arm64_smccc_res arm64_smccc_res_t;
+
+enum arm64_smccc_conduit
+{
+ SMCCC_CONDUIT_NONE,
+ SMCCC_CONDUIT_SMC,
+ SMCCC_CONDUIT_HVC,
+};
+
+/* Make HVC calls
+ *
+ * param a0 function identifier
+ * param a1-a7 parameters registers
+ * param res results
+ */
+
+void arm64_smccc_hvc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm64_smccc_res *res);
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/include/syscall.h:
##########
@@ -0,0 +1,390 @@
+/****************************************************************************
+ * arch/arm64/include/syscall.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through include/syscall.h or include/sys/sycall.h
+ */
+
+#ifndef __ARCH_ARM64_INCLUDE_SYSCALL_H
+#define __ARCH_ARM64_INCLUDE_SYSCALL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define SYS_syscall 0x00
+#define SYS_smhcall 0x123456
+
+/* Configuration ************************************************************/
+
+/* This logic uses three system calls {0,1,2} for context switching and one
+ * for the syscall return.
+ * So a minimum of four syscall values must be reserved.
+ * If CONFIG_BUILD_PROTECTED is defined, then four more syscall values must
+ * be reserved.
+ */
+
+#ifndef CONFIG_BUILD_FLAT
+# define CONFIG_SYS_RESERVED 8
+#else
+# define CONFIG_SYS_RESERVED 4
+#endif
+
+/* system calls */
+
+/* SYS call 0:
+ *
+ * int arm64_saveusercontext(void *saveregs);
+ */
+
+#define SYS_save_context (0)
+
+/* SYS call 1:
+ *
+ * void arm64_fullcontextrestore(void *restoreregs) noreturn_function;
+ */
+
+#define SYS_restore_context (1)
+
+/* SYS call 2:
+ *
+ * void arm64_switchcontext(void *saveregs, void *restoreregs);
+ */
+
+#define SYS_switch_context (2)
+
+#ifdef CONFIG_LIB_SYSCALL
+/* SYS call 3:
+ *
+ * void arm_syscall_return(void);
+ */
+
+#define SYS_syscall_return (3)
+#endif /* CONFIG_LIB_SYSCALL */
+
+#ifndef CONFIG_BUILD_FLAT
+/* SYS call 4:
+ *
+ * void up_task_start(main_t taskentry, int argc, char *argv[])
+ * noreturn_function;
+ */
+
+#define SYS_task_start (4)
+
+/* SYS call 5:
+ *
+ * void up_pthread_start((pthread_startroutine_t startup,
+ * pthread_startroutine_t entrypt, pthread_addr_t arg)
+ * noreturn_function
+ */
+
+#define SYS_pthread_start (5)
+
+/* SYS call 6:
+ *
+ * void signal_handler(_sa_sigaction_t sighand,
+ * int signo, siginfo_t *info,
+ * void *ucontext);
+ */
+
+#define SYS_signal_handler (6)
+
+/* SYS call 7:
+ *
+ * void signal_handler_return(void);
+ */
+
+#define SYS_signal_handler_return (7)
+#endif /* !CONFIG_BUILD_FLAT */
+
+#define ARM_SMCC_RES_A0 (0)
+#define ARM_SMCC_RES_A1 (1)
+#define ARM_SMCC_RES_A2 (2)
+#define ARM_SMCC_RES_A3 (3)
+#define ARM_SMCC_RES_A4 (4)
+#define ARM_SMCC_RES_A5 (5)
+#define ARM_SMCC_RES_A6 (6)
+#define ARM_SMCC_RES_A7 (7)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* SVC with SYS_ call number and no parameters */
+
+static inline uintptr_t sys_call0(unsigned int nbr)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and one parameter */
+
+static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and two parameters */
+
+static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and three parameters */
+
+static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and four parameters */
+
+static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and five parameters */
+
+static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* SVC with SYS_ call number and six parameters */
+
+static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
+ uintptr_t parm2, uintptr_t parm3,
+ uintptr_t parm4, uintptr_t parm5,
+ uintptr_t parm6)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg6 __asm__("x6") = (uint64_t)(parm6);
+ register uint64_t reg5 __asm__("x5") = (uint64_t)(parm5);
+ register uint64_t reg4 __asm__("x4") = (uint64_t)(parm4);
+ register uint64_t reg3 __asm__("x3") = (uint64_t)(parm3);
+ register uint64_t reg2 __asm__("x2") = (uint64_t)(parm2);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm1);
+
+ __asm__ __volatile__
+ (
+ "svc %1"
+ : "=r"(reg0)
+ : "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
+ "r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* semihosting(SMH) call with call number and one parameter */
+
+static inline long smh_call(unsigned int nbr, uintptr_t *parm)
+{
+ register uint64_t reg0 __asm__("x0") = (uint64_t)(nbr);
+ register uint64_t reg1 __asm__("x1") = (uint64_t)(parm);
+
+ __asm__ __volatile__
+ (
+ "hlt %1"
+ : "=r"(reg0)
+ : "i"(SYS_smhcall), "r"(reg0), "r"(reg1)
+ : "memory", "x30"
+ );
+
+ return reg0;
+}
+
+/* Result from SMC/HVC call
+ * a0-a7 result values from registers 0 to 7
+ */
+
+struct arm64_smccc_res
+{
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long a4;
+ unsigned long a5;
+ unsigned long a6;
+ unsigned long a7;
+};
+
+typedef struct arm64_smccc_res arm64_smccc_res_t;
+
+enum arm64_smccc_conduit
+{
+ SMCCC_CONDUIT_NONE,
+ SMCCC_CONDUIT_SMC,
+ SMCCC_CONDUIT_HVC,
+};
+
+/* Make HVC calls
+ *
+ * param a0 function identifier
+ * param a1-a7 parameters registers
+ * param res results
+ */
+
+void arm64_smccc_hvc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm64_smccc_res *res);
+
+/* Make SMC calls
+ *
+ * param a0 function identifier
+ * param a1-a7 parameters registers
+ * param res results
+ */
+
+void arm64_smccc_smc(unsigned long a0, unsigned long a1,
+ unsigned long a2, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm64_smccc_res *res);
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
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[GitHub] [incubator-nuttx] qinwei2004 commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
Posted by GitBox <gi...@apache.org>.
qinwei2004 commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r902417630
##########
arch/arm64/src/common/arm64_fpu.h:
##########
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/src/common/arm64_fpu.h:
##########
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_fpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_FPU_H__
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <debug.h>
+#include <assert.h>
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void arm64_init_fpu(struct tcb_s *tcb);
+void arm64_destory_fpu(struct tcb_s * tcb);
+
+void arm64_fpu_disable(void);
+void arm64_fpu_enable(void);
+
+void arm64_fpu_save(struct fpu_reg *saved_fp_context);
+void arm64_fpu_restore(struct fpu_reg *saved_fp_context);
+
+#endif //__ASSEMBLY__
+
+#endif /* __ARCH_ARM_SRC_ARMV7_A_ARM_H */
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
##########
arch/arm64/src/common/arm64_gic.h:
##########
@@ -0,0 +1,317 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_gic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__
+#define __ARCH_ARM64_SRC_COMMON_ARM64_GICV3_H__
Review Comment:
fix at [48faa78](https://github.com/apache/incubator-nuttx/pull/6478/commits/48faa78d9898c978116903e3d2860b1f2593196a)
please check
--
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