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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/03/12 03:53:23 UTC
[incubator-nuttx] branch master updated (023b1a5 -> 86b18bd)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 023b1a5 boards: sabre-6quad: Add CONFIG_DEBUG_FULLOPT=y to knsh/defconfig
new a4db403 xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled
new 86b18bd xtensa/esp32s3: Move code documentation to the correct place
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Summary of changes:
arch/xtensa/src/esp32s3/esp32s3_tickless.c | 3 +++
arch/xtensa/src/esp32s3/esp32s3_timerisr.c | 9 ++++++---
2 files changed, 9 insertions(+), 3 deletions(-)
[incubator-nuttx] 02/02: xtensa/esp32s3: Move code documentation to the correct place
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 86b18bd6e9d8e3034c3685ac99b76ba11d79f099
Author: Gustavo Henrique Nihei <gu...@espressif.com>
AuthorDate: Fri Mar 11 09:32:19 2022 -0300
xtensa/esp32s3: Move code documentation to the correct place
Signed-off-by: Gustavo Henrique Nihei <gu...@espressif.com>
---
arch/xtensa/src/esp32s3/esp32s3_timerisr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
index e2d4b23..960c614 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
@@ -119,7 +119,7 @@ void up_timer_initialize(void)
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_SYSTIMER_RST, 0);
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_CLK_EN);
- /* Configure alarm0 (Comparator 0) */
+ /* Configure alarm 0 (Comparator 0) */
regval = SYSTIMER_TARGET0_PERIOD_MODE |
((ESP32S3_SYSTIMER_TICKS_PER_SEC / CLOCKS_PER_SEC) <<
@@ -138,9 +138,9 @@ void up_timer_initialize(void)
modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET0_INT_CLR);
modifyreg32(SYSTIMER_INT_ENA_REG, 0, SYSTIMER_TARGET0_INT_ENA);
- modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TARGET0_WORK_EN);
- /* Start alarm0 counter0 */
+ /* Start alarm 0 and counter 0 */
+ modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TARGET0_WORK_EN);
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_WORK_EN);
}
[incubator-nuttx] 01/02: xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a4db4031c9c804a771c97ce95edf2ce2a1181d9a
Author: Gustavo Henrique Nihei <gu...@espressif.com>
AuthorDate: Fri Mar 11 09:30:52 2022 -0300
xtensa/esp32s3: Stall Systimer when core 1 is temporarily stalled
Signed-off-by: Gustavo Henrique Nihei <gu...@espressif.com>
---
arch/xtensa/src/esp32s3/esp32s3_tickless.c | 3 +++
arch/xtensa/src/esp32s3/esp32s3_timerisr.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/xtensa/src/esp32s3/esp32s3_tickless.c b/arch/xtensa/src/esp32s3/esp32s3_tickless.c
index 7e188b3..e379c48 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_tickless.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_tickless.c
@@ -479,6 +479,9 @@ void up_timer_initialize(void)
/* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
+#ifdef CONFIG_SMP
+ modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN);
+#endif
}
#endif /* CONFIG_SCHED_TICKLESS */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
index 30896f0..e2d4b23 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
@@ -130,6 +130,9 @@ void up_timer_initialize(void)
/* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
+#ifdef CONFIG_SMP
+ modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN);
+#endif
/* Enable interrupt */