[drlvm] design issues re: merging SableVM's GC write barrier code

[Weldon Washburn <we...@gmail.com>]

All,

Please take a look and tell me if the following seems correct:

drlvm/trunk/vm/vmcore/src/util/ia32/base/jit_runtime_support_ia32.cpp,
line 507 contains the entry point for the runtime helper that the JIT
uses for generating write barrier calls. (For simplicity, we will not
do any inlining at this point.)    This JIT runtime helper is created
during boot and is called, getaddress__gc_write_barrier_fastcall() and
is in the same ...support_ia32.cpp file.  Its basically a very short
asm language stub that turns around and calls, gc_write_barrier()
which is located in, drlvm/trunk/vm/gc/src/gc_for_vm.cpp, line 572.
gc_write_barrier() is currently an empty stub.  This is where DRLVM
intends write barriers for GCs written in "C" to go.  And, by the way,
gc_for_vm.cpp in DRLVM mentions that the JIT should call the write
barrier *after* doing the write.  Two observations.  a) DRLVM did not
originally have the concept of substituting write barrier and b) its
probably best to observe the write followed by write barrier ordering
lest we trip upon some obscure bugs.  The lack of substituting write
barrier is not a biggie.  It should be simple to add this to the VM/GC
API when we neeed to do so.

Now let's talk about what goes in the empty stub called
gc_write_barrier() to support SableVM's generational GC.

At sableVM/sablevm-sdk-1.13/sablevm/src/libsablevm/gc_gencopy.h, line #35 is:

_svmf_write_barrier (_svmt_JNIEnv *env, _svmt_object_instance **ref)

This C routine is a very thin wrapper that does an indirect call of:

_svmf_remember_set_add()

Which is located at
sableVM/sablevm-sdk-1.13/sablevm/src/libsablevm/gc_gencopy.c, line
643.  This is a basic, simple open hash.  It looks like there are a
few #defines plus one typdef struct that have to be pulled into the
DRLVM code base to get the SableVM GC write barrier to build.

Does the above make sense?  Is there anything missing?  My next step
will be to turn in JIRA patches that merge SableVM GC write barriers
into DRLVM.

    Thanks





-- 
Weldon Washburn
Intel Middleware Products Division

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