[orc] branch main updated: ORC-1447: [C++] Fix a bug in CpuInfoUtil.cc to support ARM platform

[ga...@apache.org]

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gangwu pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/orc.git


The following commit(s) were added to refs/heads/main by this push:
     new ee5e072f7 ORC-1447: [C++] Fix a bug in CpuInfoUtil.cc to support ARM platform
ee5e072f7 is described below

commit ee5e072f70eba0f813d9cb6dfabaee2423d63683
Author: wpleonardo <wp...@163.com>
AuthorDate: Thu Jun 22 00:05:42 2023 +0800

    ORC-1447: [C++] Fix a bug in CpuInfoUtil.cc to support ARM platform
    
    ### What changes were proposed in this pull request?
    To fix a bug reported in #1534
    The bug is that some CpuInfoUtil.cc functions don't support the ARM platform. In this PR, try to fix this bug.
    
    ### Why are the changes needed?
    Currently, ORC can't build success on the ARM platform without this PR.
    
    ### How was this patch tested?
    We can build ORC on the ARM platform directly to check if it can succeed.
    If user enabled -DBUILD_ENABLE_AVX512=ON in the cmake process, it will get the below warning message, and BUILD_ENABLE_AVX512 will be changed back to OFF.
    CMake Warning at CMakeLists.txt:183 (message):
    Only X86 platform support AVX512
    
    This closes #1542
---
 CMakeLists.txt         |  6 ++++++
 c++/src/CpuInfoUtil.cc | 47 ++++++++++++++++++++++++++++++++++++++++++++++-
 c++/src/CpuInfoUtil.hh |  3 +++
 3 files changed, 55 insertions(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 28841f3a2..1fd27c9dd 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -178,6 +178,12 @@ enable_testing()
 
 INCLUDE(CheckSourceCompiles)
 INCLUDE(ThirdpartyToolchain)
+
+if (BUILD_ENABLE_AVX512 AND NOT (CMAKE_SYSTEM_PROCESSOR MATCHES "AMD64|X86|x86|i[3456]86|x64"))
+  message(WARNING "Only X86 platform support AVX512")
+  set (BUILD_ENABLE_AVX512 "OFF")
+endif ()
+
 message(STATUS "BUILD_ENABLE_AVX512: ${BUILD_ENABLE_AVX512}")
 #
 # macOS doesn't fully support AVX512, it has a different way dealing with AVX512 than Windows and Linux.
diff --git a/c++/src/CpuInfoUtil.cc b/c++/src/CpuInfoUtil.cc
index bf32617c4..482187f3d 100644
--- a/c++/src/CpuInfoUtil.cc
+++ b/c++/src/CpuInfoUtil.cc
@@ -50,9 +50,15 @@
 #include "orc/Exceptions.hh"
 
 #undef CPUINFO_ARCH_X86
+#undef CPUINFO_ARCH_ARM
+#undef CPUINFO_ARCH_PPC
 
 #if defined(__i386) || defined(_M_IX86) || defined(__x86_64__) || defined(_M_X64)
 #define CPUINFO_ARCH_X86
+#elif defined(_M_ARM64) || defined(__aarch64__) || defined(__arm64__)
+#define CPUINFO_ARCH_ARM
+#elif defined(__PPC64__) || defined(__PPC64LE__) || defined(__ppc64__) || defined(__powerpc64__)
+#define CPUINFO_ARCH_PPC
 #endif
 
 #ifndef ORC_HAVE_RUNTIME_AVX512
@@ -203,6 +209,14 @@ namespace orc {
         }
       }
     }
+
+#elif defined(CPUINFO_ARCH_ARM)
+    // Windows on Arm
+    void OsRetrieveCpuInfo(int64_t* hardware_flags, CpuInfo::Vendor* vendor,
+                           std::string* model_name) {
+      *hardware_flags |= CpuInfo::ASIMD;
+      // TODO: vendor, model_name
+    }
 #endif
 
 #elif defined(__APPLE__)
@@ -259,6 +273,9 @@ namespace orc {
         {"hw.optional.avx512dq", CpuInfo::AVX512DQ},
         {"hw.optional.avx512bw", CpuInfo::AVX512BW},
         {"hw.optional.avx512vl", CpuInfo::AVX512VL},
+#elif defined(CPUINFO_ARCH_ARM)
+        // ARM64 (note that this is exposed under Rosetta as well)
+        {"hw.optional.neon", CpuInfo::ASIMD},
 #endif
       };
       for (const auto& feature : features) {
@@ -344,6 +361,8 @@ namespace orc {
         {"avx512bw", CpuInfo::AVX512BW},
         {"bmi1", CpuInfo::BMI1},
         {"bmi2", CpuInfo::BMI2},
+#elif defined(CPUINFO_ARCH_ARM)
+        {"asimd", CpuInfo::ASIMD},
 #endif
       };
       const int64_t num_flags = sizeof(flag_mappings) / sizeof(flag_mappings[0]);
@@ -449,7 +468,31 @@ namespace orc {
 #endif
     }
 
-#endif  // X86
+#elif defined(CPUINFO_ARCH_ARM)
+    //------------------------------ AARCH64 ------------------------------//
+    bool ArchParseUserSimdLevel(const std::string& simd_level, int64_t* hardware_flags) {
+      if (simd_level == "NONE") {
+        *hardware_flags &= ~CpuInfo::ASIMD;
+        return true;
+      }
+      return false;
+    }
+
+    void ArchVerifyCpuRequirements(const CpuInfo* ci) {
+      if (!ci->isDetected(CpuInfo::ASIMD)) {
+        throw ParseError("CPU does not support the Armv8 Neon instruction set");
+      }
+    }
+
+#else
+    //------------------------------ PPC, ... ------------------------------//
+    bool ArchParseUserSimdLevel(const std::string& simd_level, int64_t* hardware_flags) {
+      return true;
+    }
+
+    void ArchVerifyCpuRequirements(const CpuInfo* ci) {}
+
+#endif  // X86, ARM, PPC
 
   }  // namespace
 
@@ -543,3 +586,5 @@ namespace orc {
 }  // namespace orc
 
 #undef CPUINFO_ARCH_X86
+#undef CPUINFO_ARCH_ARM
+#undef CPUINFO_ARCH_PPC
diff --git a/c++/src/CpuInfoUtil.hh b/c++/src/CpuInfoUtil.hh
index ad7df6a82..5637053e6 100644
--- a/c++/src/CpuInfoUtil.hh
+++ b/c++/src/CpuInfoUtil.hh
@@ -55,6 +55,9 @@ namespace orc {
     static constexpr int64_t BMI1 = (1LL << 11);
     static constexpr int64_t BMI2 = (1LL << 12);
 
+    /// Arm features
+    static constexpr int64_t ASIMD = (1LL << 32);
+
     // Cache enums for L1 (data), L2 and L3
     enum class CacheLevel { L1 = 0, L2, L3, Last = L3 };