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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/01/27 01:14:06 UTC
[GitHub] [incubator-nuttx] gustavonihei opened a new pull request #5352: xtensa: Add initial support for ESP32-S3
gustavonihei opened a new pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352
## Summary
This PR intends to add basic support for **ESP32-S3**, a dual-core Xtensa LX7 MCU from Espressif Systems.\
https://www.espressif.com/en/products/socs/esp32-s3
The new `esp32s3-devkit` target considers a generic development board whose characteristics are common to [ESP32-S3-DevKitC-1](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html) and [ESP32-S3-DevKitM-1](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html) official development kits.
This initial support consists of the following features:
- Basic clock control (APB clock defaults to 80MHz)
- Peripheral and CPU interrupts management
- Heap management
- Board reset support
- Serial driver
## Impact
Support for new chip.
## Testing
`esp32s3-devkit:nsh` and successful execution of `ostest` application.
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[GitHub] [incubator-nuttx] gustavonihei commented on pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#issuecomment-1023119322
> Do we need `boards/xtensa/esp32s3/.gitignore`? It is empty
No need, added for creating the initial tree and forgot to remove it later. Thanks.
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[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793473193
##########
File path: arch/xtensa/include/esp32s3/core-isa.h
##########
@@ -0,0 +1,695 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/core-isa.h
+ * Xtensa processor core configuration information.
+ *
+ * Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
Review comment:
Yes, we need to keep the original header here. In all of the Xtensa folder we have some files that come from Tensilica and we can't change the headers to the ASF one.
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[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793484799
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
Review comment:
ESP32-S3 is a dual core chip, so yes we do expect an index other than `0`. However, for this initial support all SMP features are now ignored. These will be dealt with later.
Regarding `volatile uint32_t *g_current_regs[1];` this will change to the usual:
```
#ifdef CONFIG_SMP
/* For the case of architectures with multiple CPUs, then there must be one
* such value for each processor that can receive an interrupt.
*/
volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
#else
volatile uint32_t *g_current_regs[1];
#endif
```
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[GitHub] [incubator-nuttx] gustavonihei commented on pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#issuecomment-1023124424
@pkarashchenko I've updated the PR addressing your comments.
Also, I've moved the change to the Dockerfile to another PR. If that gets merged first, then the `esp32s3-devkit:nsh` may be built by the CI on this PR.
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[GitHub] [incubator-nuttx] gustavonihei commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793635825
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
Review comment:
Done.
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[GitHub] [incubator-nuttx] gustavonihei commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793626150
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
Review comment:
Actually the correct would be `user == NULL`. Thanks!
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793675606
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h
##########
@@ -0,0 +1,1961 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_UART_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_UART_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* UART_FIFO_REG register
+ * FIFO data register
+ */
+
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+
+/* UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ * UART $n accesses FIFO via this register.
+ */
+
+#define UART_RXFIFO_RD_BYTE 0x000000ff
+#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V 0x000000ff
+#define UART_RXFIFO_RD_BYTE_S 0
+
+/* UART_INT_RAW_REG register
+ * Raw interrupt status
+ */
+
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+
+/* UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ * This interrupt raw bit turns to high level when input rxd edge changes
+ * more times than what reg_active_threshold specifies in light sleeping
+ * mode.
+ */
+
+#define UART_WAKEUP_INT_RAW (BIT(19))
Review comment:
minor
```suggestion
#define UART_WAKEUP_INT_RAW BIT(19)
```
here and in other places
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_systimer.h
##########
@@ -0,0 +1,808 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_systimer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTIMER_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTIMER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* SYSTIMER_CONF_REG register
+ * Configure system timer clock
+ */
+
+#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
+
+/* SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ * register file clk gating
+ */
+
+#define SYSTIMER_CLK_EN (BIT(31))
Review comment:
minor
```suggestion
#define SYSTIMER_CLK_EN BIT(31)
```
here and in other places
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h
##########
@@ -0,0 +1,2761 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* EXTMEM_DCACHE_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0)
+
+/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W; bitpos: [4:3]; default: 0;
+ * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2:
+ * 64 bytes
+ */
+
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE 0x00000003
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M (EXTMEM_DCACHE_BLOCKSIZE_MODE_V << EXTMEM_DCACHE_BLOCKSIZE_MODE_S)
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x00000003
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3
+
+/* EXTMEM_DCACHE_SIZE_MODE : R/W; bitpos: [2]; default: 0;
+ * The bit is used to configure cache memory size.0: 32KB, 1: 64KB
+ */
+
+#define EXTMEM_DCACHE_SIZE_MODE (BIT(2))
Review comment:
minor
```suggestion
#define EXTMEM_DCACHE_SIZE_MODE BIT(2)
```
here and in other places
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_iomux.h
##########
@@ -0,0 +1,467 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_iomux.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_IOMUX_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_IOMUX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-preprocessor Definitions
+ ****************************************************************************/
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+
+/* Output enable in sleep mode */
+
+#define SLP_OE (BIT(0))
Review comment:
minor
```suggestion
#define SLP_OE BIT(0)
```
here and in other places
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
##########
@@ -0,0 +1,5795 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to
+ * write-enable the wdt registers
+ */
+
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1
+
+/* RTC_CNTL_RTC_OPTIONS0_REG register
+ * RTC common configure register
+ */
+
+#define RTC_CNTL_RTC_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
+
+/* RTC_CNTL_SW_SYS_RST : WO; bitpos: [31]; default: 0;
+ * SW system reset
+ */
+
+#define RTC_CNTL_SW_SYS_RST (BIT(31))
Review comment:
minor
```suggestion
#define RTC_CNTL_SW_SYS_RST BIT(31)
```
here and in other places
##########
File path: boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.ld
##########
@@ -0,0 +1,269 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_flash.ld
+ ****************************************************************************/
+
+/* Default entry point: */
+
+ENTRY(__start);
+
+_diram_i_start = 0x40378000;
+
+SECTIONS
+{
+ /* Send .iram0 code to iram */
+
+ .iram0.vectors :
+ {
+ _iram_start = ABSOLUTE(.);
+
+ /* Vectors go to IRAM. */
+
+ _init_start = ABSOLUTE(.);
+
+ /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+
+ . = 0x0;
+ KEEP (*(.window_vectors.text));
+ . = 0x180;
+ KEEP (*(.xtensa_level2_vector.text));
+ . = 0x1c0;
+ KEEP (*(.xtensa_level3_vector.text));
+ . = 0x200;
+ KEEP (*(.xtensa_level4_vector.text));
+ . = 0x240;
+ KEEP (*(.xtensa_level5_vector.text));
+ . = 0x280;
+ KEEP (*(.debug_exception_vector.text));
+ . = 0x2c0;
+ KEEP (*(.nmi_vector.text));
+ . = 0x300;
+ KEEP (*(.kernel_exception_vector.text));
+ . = 0x340;
+ KEEP (*(.user_exception_vector.text));
+ . = 0x3c0;
+ KEEP (*(.double_exception_vector.text));
+ . = 0x400;
+ *(.*_vector.literal)
+
+ . = ALIGN (16);
+
+ *(.entry.text)
+ *(.init.literal)
+ *(.init)
+ } > iram0_0_seg
+
+ .iram0.text :
+ {
+ /* Code marked as running out of IRAM */
+
+ *(.iram1 .iram1.*)
+
+ /* align + add 16B for CPU dummy speculative instr. fetch */
+
+ . = ALIGN(4) + 16;
+
+ _iram_text = ABSOLUTE(.);
+ } > iram0_0_seg
+
+ .dram0.dummy (NOLOAD) :
+ {
+ /* This section is required to skip .iram0.text area because iram0_0_seg
+ * and dram0_0_seg reflect the same address space on different buses.
+ */
+
+ . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
+ } > dram0_0_seg
+
+ /* Shared RAM */
+
+ .dram0.bss (NOLOAD) :
+ {
+ /* .bss initialized on power-up */
+
+ . = ALIGN (8);
+ _sbss = ABSOLUTE(.);
+
+ *(.bss .bss.*)
+ *(COMMON)
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ *(.dynbss)
+ *(.share.mem)
+ *(.gnu.linkonce.b.*)
+
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .noinit (NOLOAD) :
+ {
+ /* This section contains data that is not initialized during load,
+ * or during the application's initialization sequence.
+ */
+
+ . = ALIGN(4);
+
+ *(.noinit .noinit.*)
+
+ . = ALIGN(4);
+ } > dram0_0_seg
+
+ .dram0.data :
+ {
+ /* .data initialized on power-up in ROMed configurations. */
+
+ _sdata = ABSOLUTE(.);
+ KEEP (*(.data))
+ KEEP (*(.data.*))
+ KEEP (*(.gnu.linkonce.d.*))
+ KEEP (*(.data1))
+ KEEP (*(.sdata))
+ KEEP (*(.sdata.*))
+ KEEP (*(.gnu.linkonce.s.*))
+ KEEP (*(.sdata2))
+ KEEP (*(.sdata2.*))
+ KEEP (*(.gnu.linkonce.s2.*))
+ KEEP (*(.jcr))
+ *(.dram1 .dram1.*)
+
+ _edata = ABSOLUTE(.);
+ . = ALIGN(4);
+
+ /* Heap starts at the end of .data */
+
+ _sheap = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .flash.text :
+ {
+ _stext = .;
+ *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.fini.literal)
+ *(.fini)
+ *(.gnu.version)
+
+ /* CPU will try to prefetch up to 16 bytes of instructions.
+ * This means that any configuration (e.g. MMU, PMS) must allow
+ * safe access to up to 16 bytes after the last real instruction, add
+ * dummy bytes to ensure this
+ */
+
+ . += 16;
+
+ _etext = .;
+ } > default_code_seg
+
+ .flash_rodata_dummy (NOLOAD) :
+ {
+ /* This dummy section represents the .flash.text section but in default_rodata_seg.
+ * Thus, it must have its alignment and (at least) its size.
+ */
+
+ /* Start at the same alignment constraint than .flash.text */
+
+ . = ALIGN(ALIGNOF(.flash.text));
+
+ /* Create an empty gap as big as .flash.text section */
+
+ . = SIZEOF(.flash.text);
+
+ /* Prepare the alignment of the section above. Few bytes (0x20) must be
+ * added for the mapping header.
+ */
+
+ . = ALIGN(0x10000) + 0x20;
+ _rodata_reserved_start = .;
+ } > default_rodata_seg
+
+ .flash.rodata : ALIGN(0x10)
+ {
+ _srodata = ABSOLUTE(.);
+
+ *(.rodata)
+ *(.rodata.*)
+ *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.gnu.linkonce.r.*)
+ *(.rodata1)
+ __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+ *(.xt_except_table)
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.gnu.linkonce.e.*)
+ *(.gnu.version_r)
+ *(.eh_frame)
+
+ . = (. + 3) & ~ 3;
Review comment:
Maybe just `. = ALIGN(4);`?
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_system.h
##########
@@ -0,0 +1,1757 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_system.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTEM_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTEM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* SYSTEM_CORE_1_CONTROL_0_REG register
+ * Core0 control regiter 0
+ */
+
+#define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x0)
+
+/* SYSTEM_CONTROL_CORE_1_RESETING : R/W; bitpos: [2]; default: 1;
+ * Set 1 to let core1 reset
+ */
+
+#define SYSTEM_CONTROL_CORE_1_RESETING (BIT(2))
Review comment:
minor
```suggestion
#define SYSTEM_CONTROL_CORE_1_RESETING BIT(2)
```
here and in other places
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.h
##########
@@ -0,0 +1,485 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_gpio_sigmap.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+enum uart_sclk
+{
+ APB_CLK = 1, /* 80 MHz */
+ CLK_8, /* 8 MHz */
+ XTAL_CLK
+};
+
+enum uart_parity
+{
+ UART_PARITY_DISABLE,
+ UART_PARITY_ODD,
+ UART_PARITY_EVEN
+};
+
+enum uart_data_length
+{
+ UART_DATA_5_BITS,
+ UART_DATA_6_BITS,
+ UART_DATA_7_BITS,
+ UART_DATA_8_BITS
+};
+
+enum uart_stop_length
+{
+ UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */
+ UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */
Review comment:
@gustavonihei could you please fix this?
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[GitHub] [incubator-nuttx] gustavonihei commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793709230
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h
##########
@@ -0,0 +1,1961 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_UART_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_UART_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* UART_FIFO_REG register
+ * FIFO data register
+ */
+
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+
+/* UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ * UART $n accesses FIFO via this register.
+ */
+
+#define UART_RXFIFO_RD_BYTE 0x000000ff
+#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V 0x000000ff
+#define UART_RXFIFO_RD_BYTE_S 0
+
+/* UART_INT_RAW_REG register
+ * Raw interrupt status
+ */
+
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+
+/* UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ * This interrupt raw bit turns to high level when input rxd edge changes
+ * more times than what reg_active_threshold specifies in light sleeping
+ * mode.
+ */
+
+#define UART_WAKEUP_INT_RAW (BIT(19))
Review comment:
@pkarashchenko These are auto-generated, so I prefer to leave these as-is to avoid additional work for every other future header.
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793509344
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
Review comment:
Recently we had https://github.com/apache/incubator-nuttx/pull/5264 so we can go with `volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];` even right now. But this is minor comment. It is fine to go with `volatile uint32_t *g_current_regs[1];` for now and rework later
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[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793479132
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
Review comment:
There are situations where `cpuint` is tested to verify the validity of an operation, any error code would work for this, however, the function that allocates a CPU interrupt returns `ENOMEM` in case of failure, "Out of Memory" here means "Out of CPU Interrupts".
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[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793510891
##########
File path: arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
##########
@@ -0,0 +1,312 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define DEFAULT_CPU_FREQ 80
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum cpu_freq_e
+{
+ CPU_80M = 0,
+ CPU_160M = 1,
+ CPU_240M = 2,
+};
+
+enum cpu_clksrc_e
+{
+ XTAL_CLK,
+ PLL_CLK,
+ FOSC_CLK
+};
+
+enum pll_freq_e
+{
+ PLL_320,
+ PLL_480
+};
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us will be
+ * accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
Review comment:
The API is defined in the linker scripts at `boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld` (they are in the `common` directory for ESP32.). The thing is there are a lot of functions there and we just use a few of them, so each source file just adds the prototypes of those it uses.
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[GitHub] [incubator-nuttx] gustavonihei commented on pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#issuecomment-1023328110
> @gustavonihei could you please fix this?
Sorry, I overlooked this comment. Fixed.
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793565707
##########
File path: arch/xtensa/include/esp32s3/tie.h
##########
@@ -0,0 +1,209 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie.h
+ * Compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality. It is customized to this
+ * Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+
+#define XCHAL_CP_NUM 2 /* number of coprocessors */
+#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
+
+/* Basic parameters of each coprocessor: */
+#define XCHAL_CP0_NAME "FPU"
Review comment:
```suggestion
#define XCHAL_CP0_NAME "FPU"
```
##########
File path: arch/xtensa/src/esp32s3/chip_macros.h
##########
@@ -0,0 +1,95 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/chip_macros.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_CHIP_MACROS_H
+#define __ARCH_XTENSA_SRC_ESP32S3_CHIP_MACROS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* This is the name of the section containing the Xtensa low level handlers
+ * that is used by the board linker scripts.
+ */
+
+#define HANDLER_SECTION .iram1
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __ASSEMBLY__
+
+#endif /* __ASSEMBLY__ */
Review comment:
```suggestion
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
+ freeints = &g_cpu0_freeints;
+
+ intset = *freeints & intmask;
+ if (intset != 0)
+ {
+ /* Skip over initial unavailable CPU interrupts quickly in groups
+ * of 8 interrupt.
+ */
+
+ for (cpuint = 0, bitmask = 0xff;
+ cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0;
+ cpuint += 8, bitmask <<= 8);
+
+ /* Search for an unallocated CPU interrupt number in the remaining
+ * intset.
+ */
+
+ for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++)
+ {
+ /* If the bit corresponding to the CPU interrupt is '1', then
+ * that CPU interrupt is available.
+ */
+
+ bitmask = (1ul << cpuint);
+ if ((intset & bitmask) != 0)
+ {
+ /* Got it! */
+
+ *freeints &= ~bitmask;
+ ret = cpuint;
+ break;
+ }
+ }
+ }
+
+ /* Enable the CPU interrupt now. The interrupt is still not attached
+ * to any peripheral and thus has no effect.
+ */
+
+ if (ret >= 0)
+ {
+ xtensa_enable_cpuint(&g_intenable[cpu], (1ul << ret));
Review comment:
```suggestion
xtensa_enable_cpuint(&g_intenable[cpu], 1ul << ret);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,846 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART1 */
+#endif /* HAVE_UART_DEVICE */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable)
+{
+ uint32_t mask;
+ if (enable)
+ {
+ /* Enable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
+
+ /* Configure the threshold */
+
+ mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
+ }
+ else
+ {
+ /* Disable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable)
+{
+ if (enable)
+ {
+ /* Enable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
+ }
+ else
+ {
+ /* Disable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RST_CORE_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
+ 1 << UART_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
+ 1 << UART_RX_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
+ 1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source)
+{
+ uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
+{
+ uint32_t clk_conf_reg;
+ uint32_t ret = -ENODATA;
+ clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
+ clk_conf_reg &= UART_SCLK_SEL_M;
+ clk_conf_reg >>= UART_SCLK_SEL_S;
+ switch (clk_conf_reg)
+ {
+ case 1:
+ ret = esp_clk_apb_freq();
+ break;
+ case 2:
+ ret = RTC_CLK_FREQ;
+ break;
+ case 3:
+ ret = XTAL_CLK_FREQ;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_baud
+ *
+ * Description:
+ * Set the baud rate according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_baud(const struct esp32s3_uart_s * priv)
+{
+ int sclk_div;
+ uint32_t sclk_freq;
+ uint32_t clk_div;
+ uint32_t int_part;
+ uint32_t frag_part;
+
+ /* Get serial clock */
+
+ sclk_freq = esp32s3_lowputc_get_sclk(priv);
+
+ /* Calculate integral part of the frequency divider factor.
+ * For low baud rates, the sclk must be less than half.
+ * For high baud rates, the sclk must be the higher.
+ */
+
+ sclk_div = DIV_UP(sclk_freq, MAX_UART_CLKDIV * priv->baud);
+
+ /* Calculate the clock divisor to achieve the baud rate.
+ * baud = f/clk_div
+ * f = sclk_freq/sclk_div
+ * clk_div = 16*int_part + frag_part
+ * 16*int_part + frag_part = 16*(sclk_freq/sclk_div)/baud
+ */
+
+ clk_div = ((sclk_freq) << 4) / (priv->baud * sclk_div);
Review comment:
```suggestion
clk_div = (sclk_freq << 4) / (priv->baud * sclk_div);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
Review comment:
```suggestion
priv->cpuint = -ENOMEM;
```
???
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev->priv, sizeof(struct esp32s3_uart_s));
+ }
+ }
+ break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+
+ /* Fill a termios structure with the required information. */
+
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */
+
+ termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
+ ((priv->parity == 1) ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0;
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ termiosp->c_cflag |= (priv->oflow) ? CCTS_OFLOW : 0;
Review comment:
```suggestion
termiosp->c_cflag |= priv->oflow ? CCTS_OFLOW : 0;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_timerisr.c
##########
@@ -0,0 +1,143 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_timerisr.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <time.h>
+
+#include <arch/board/board.h>
+#include <arch/irq.h>
+#include <nuttx/arch.h>
+
+#include "chip.h"
+#include "esp32s3_irq.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_systimer.h"
+#include "xtensa.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP32S3_SYSTIMER_TICKS_PER_SEC (16 * 1000 * 1000)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: systimer_isr
+ *
+ * Description:
+ * The timer ISR will perform a variety of services for various portions
+ * of the systems.
+ *
+ * Input Parameters:
+ * irq - CPU interrupt index.
+ * context - Context data from the ISR.
+ * arg - Opaque pointer to the internal driver state structure.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned on
+ * failure.
+ *
+ ****************************************************************************/
+
+static int systimer_isr(int irq, void *context, void *arg)
+{
+ modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET0_INT_CLR);
+
+ /* Process timer interrupt */
+
+ nxsched_process_timer();
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_timer_initialize
+ *
+ * Description:
+ * This function is called during start-up to initialize the timer
+ * interrupt.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+ uint32_t regval;
+ int cpuint;
+
+ cpuint = esp32s3_setup_irq(0, ESP32S3_PERIPH_SYSTIMER_TARGET0, 1,
+ ESP32S3_CPUINT_LEVEL);
+ DEBUGASSERT(cpuint >= 0);
+
+ /* Attach the timer interrupt. */
+
+ irq_attach(ESP32S3_IRQ_SYSTIMER_TARGET0, (xcpt_t)systimer_isr, NULL);
Review comment:
Maybe we can remove `(xcpt_t)` so compiler will generate warning in case if something is wrong?
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
+ freeints = &g_cpu0_freeints;
+
+ intset = *freeints & intmask;
+ if (intset != 0)
+ {
+ /* Skip over initial unavailable CPU interrupts quickly in groups
+ * of 8 interrupt.
+ */
+
+ for (cpuint = 0, bitmask = 0xff;
+ cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0;
+ cpuint += 8, bitmask <<= 8);
+
+ /* Search for an unallocated CPU interrupt number in the remaining
+ * intset.
+ */
+
+ for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++)
+ {
+ /* If the bit corresponding to the CPU interrupt is '1', then
+ * that CPU interrupt is available.
+ */
+
+ bitmask = (1ul << cpuint);
+ if ((intset & bitmask) != 0)
+ {
+ /* Got it! */
+
+ *freeints &= ~bitmask;
+ ret = cpuint;
+ break;
+ }
+ }
+ }
+
+ /* Enable the CPU interrupt now. The interrupt is still not attached
+ * to any peripheral and thus has no effect.
+ */
+
+ if (ret >= 0)
+ {
+ xtensa_enable_cpuint(&g_intenable[cpu], (1ul << ret));
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_alloc_cpuint
+ *
+ * Description:
+ * Allocate a level CPU interrupt
+ *
+ * Input Parameters:
+ * priority - Priority of the CPU interrupt (1-5)
+ * type - Interrupt type (level or edge).
+ *
+ * Returned Value:
+ * On success, the allocated CPU interrupt number is returned.
+ * A negated errno is returned on failure. The only possible failure
+ * is that all CPU interrupts of the requested type have already been
+ * allocated.
+ *
+ ****************************************************************************/
+
+static int esp32s3_alloc_cpuint(int priority, int type)
+{
+ uint32_t mask;
+
+ DEBUGASSERT(priority >= ESP32S3_MIN_PRIORITY &&
+ priority <= ESP32S3_MAX_PRIORITY);
+ DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL ||
+ type == ESP32S3_CPUINT_EDGE);
+
+ if (type == ESP32S3_CPUINT_LEVEL)
+ {
+ /* Check if there are any level CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_LEVELSET;
+ }
+ else
+ {
+ /* Check if there are any edge CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_EDGESET;
+ }
+
+ return esp32s3_getcpuint(mask);
+}
+
+/****************************************************************************
+ * Name: esp32s3_free_cpuint
+ *
+ * Description:
+ * Free a previously allocated CPU interrupt
+ *
+ * Input Parameters:
+ * The CPU interrupt number to be freed
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32s3_free_cpuint(int cpuint)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+
+ /* Mark the CPU interrupt as available */
+
+ bitmask = (1ul << cpuint);
Review comment:
```suggestion
bitmask = 1ul << cpuint;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_gpio.c
##########
@@ -0,0 +1,205 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <arch/irq.h>
+#include <arch/esp32s3/chip.h>
+
+#include "xtensa.h"
+#include "esp32s3_irq.h"
+#include "hardware/esp32s3_iomux.h"
+#include "hardware/esp32s3_gpio.h"
+
+#include "esp32s3_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on encoded pin attributes.
+ *
+ ****************************************************************************/
+
+int esp32s3_configgpio(int pin, gpio_pinattr_t attr)
+{
+ uintptr_t regaddr;
+ uint32_t func;
+ uint32_t cntrl;
+ uint32_t pin2func;
+
+ DEBUGASSERT(pin >= 0 && pin <= ESP32S3_NGPIOS);
+
+ func = 0;
+ cntrl = 0;
+
+ /* Handle input pins */
+
+ if ((attr & INPUT) != 0)
+ {
+ putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG);
+
+ /* Input enable */
+
+ func |= FUN_IE;
+
+ if ((attr & PULLUP) != 0)
+ {
+ func |= FUN_PU;
+ }
+ else if ((attr & PULLDOWN) != 0)
+ {
+ func |= FUN_PD;
+ }
+ }
+
+ /* Handle output pins */
+
+ if ((attr & OUTPUT) != 0)
+ {
+ putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG);
+ }
+
+ /* Add drivers */
+
+ func |= (uint32_t)(2ul << FUN_DRV_S);
+
+ /* Select the pad's function. If no function was given, consider it a
+ * normal input or output (i.e. function1).
+ */
+
+ if ((attr & FUNCTION_MASK) != 0)
+ {
+ func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S);
+ }
+ else
+ {
+ func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S);
+ }
+
+ if ((attr & OPEN_DRAIN) != 0)
+ {
+ cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S);
+ }
+
+ /* Set the pin function to its register */
+
+ pin2func = (pin + 1) * 4;
+ regaddr = REG_IO_MUX_BASE + pin2func;
+ putreg32(func, regaddr);
+
+ regaddr = GPIO_REG(pin);
+ putreg32(cntrl, regaddr);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_gpio_matrix_in
+ *
+ * Description:
+ * Set gpio input to a signal
+ * NOTE: one gpio can input to several signals
+ * If gpio == 0x3c, cancel input to the signal, input 0 to signal.
+ * If gpio == 0x3a, input nothing to signal.
+ * If gpio == 0x38, cancel input to the signal, input 1 to signal.
+ *
+ ****************************************************************************/
+
+void esp32s3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv)
+{
+ uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4);
+ uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S);
+
+ if (inv)
+ {
+ regval |= GPIO_FUNC0_IN_INV_SEL;
+ }
+
+ if (gpio != 0x3a)
+ {
+ regval |= GPIO_SIG0_IN_SEL;
+ }
+
+ putreg32(regval, regaddr);
+}
+
+/****************************************************************************
+ * Name: esp32s3_gpio_matrix_out
+ *
+ * Description:
+ * Set signal output to gpio
+ * NOTE: one signal can output to several gpios
+ * If signal_idx == 0x100, cancel output put to the gpio
+ *
+ ****************************************************************************/
+
+void esp32s3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
+ bool out_inv, bool oen_inv)
+{
+ uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4);
+ uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S;
+
+ if (gpio >= ESP32S3_NGPIOS)
+ {
+ return;
+ }
+
+ putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG);
Review comment:
```suggestion
putreg32(1ul << gpio, GPIO_ENABLE_W1TS_REG);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
+ freeints = &g_cpu0_freeints;
+
+ intset = *freeints & intmask;
+ if (intset != 0)
+ {
+ /* Skip over initial unavailable CPU interrupts quickly in groups
+ * of 8 interrupt.
+ */
+
+ for (cpuint = 0, bitmask = 0xff;
+ cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0;
+ cpuint += 8, bitmask <<= 8);
+
+ /* Search for an unallocated CPU interrupt number in the remaining
+ * intset.
+ */
+
+ for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++)
+ {
+ /* If the bit corresponding to the CPU interrupt is '1', then
+ * that CPU interrupt is available.
+ */
+
+ bitmask = (1ul << cpuint);
Review comment:
```suggestion
bitmask = 1ul << cpuint;
```
##########
File path: arch/xtensa/include/esp32s3/tie.h
##########
@@ -0,0 +1,209 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie.h
+ * Compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality. It is customized to this
+ * Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+
+#define XCHAL_CP_NUM 2 /* number of coprocessors */
+#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
+
+/* Basic parameters of each coprocessor: */
+#define XCHAL_CP0_NAME "FPU"
+#define XCHAL_CP0_IDENT FPU
+#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
+#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
+#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
+#define XCHAL_CP3_NAME "cop_ai"
Review comment:
```suggestion
#define XCHAL_CP3_NAME "cop_ai"
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
##########
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <nuttx/mm/mm.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "hardware/esp32s3_rom_layout.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ * This function will be called to dynamically set aside the heap region.
+ *
+ * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
+ * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ * size of the unprotected, user-space heap.
+ *
+ * If a protected kernel-space heap is provided, the kernel heap must be
+ * allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(void **heap_start, size_t *heap_size)
+{
+ /* These values come from the linker scripts (esp32s3.ld and
+ * esp32s3.template.ld.) Check boards/xtensa/esp32s3.
+ */
+
+ extern uint8_t *_sheap;
+ extern const struct esp32s3_rom_layout_s *ets_rom_layout_p;
Review comment:
should we move this outside of the function?
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,846 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART1 */
+#endif /* HAVE_UART_DEVICE */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable)
+{
+ uint32_t mask;
+ if (enable)
+ {
+ /* Enable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
+
+ /* Configure the threshold */
+
+ mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
+ }
+ else
+ {
+ /* Disable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable)
+{
+ if (enable)
+ {
+ /* Enable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
+ }
+ else
+ {
+ /* Disable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RST_CORE_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
+ 1 << UART_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
+ 1 << UART_RX_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
+ 1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source)
+{
+ uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
+{
+ uint32_t clk_conf_reg;
+ uint32_t ret = -ENODATA;
+ clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
+ clk_conf_reg &= UART_SCLK_SEL_M;
+ clk_conf_reg >>= UART_SCLK_SEL_S;
+ switch (clk_conf_reg)
+ {
+ case 1:
+ ret = esp_clk_apb_freq();
+ break;
+ case 2:
+ ret = RTC_CLK_FREQ;
+ break;
+ case 3:
+ ret = XTAL_CLK_FREQ;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_baud
+ *
+ * Description:
+ * Set the baud rate according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_baud(const struct esp32s3_uart_s * priv)
+{
+ int sclk_div;
+ uint32_t sclk_freq;
+ uint32_t clk_div;
+ uint32_t int_part;
+ uint32_t frag_part;
+
+ /* Get serial clock */
+
+ sclk_freq = esp32s3_lowputc_get_sclk(priv);
+
+ /* Calculate integral part of the frequency divider factor.
+ * For low baud rates, the sclk must be less than half.
+ * For high baud rates, the sclk must be the higher.
+ */
+
+ sclk_div = DIV_UP(sclk_freq, MAX_UART_CLKDIV * priv->baud);
+
+ /* Calculate the clock divisor to achieve the baud rate.
+ * baud = f/clk_div
+ * f = sclk_freq/sclk_div
+ * clk_div = 16*int_part + frag_part
+ * 16*int_part + frag_part = 16*(sclk_freq/sclk_div)/baud
+ */
+
+ clk_div = ((sclk_freq) << 4) / (priv->baud * sclk_div);
+
+ /* Get the integer part of it. */
+
+ int_part = clk_div >> 4;
+
+ /* Get the frag part of it. */
+
+ frag_part = clk_div & 0xf;
+
+ /* Set integer part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part);
+
+ /* Set decimal part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M,
+ (frag_part & UART_CLKDIV_FRAG_V) << UART_CLKDIV_FRAG_S);
+
+ /* Set the the integral part of the frequency divider factor. */
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_DIV_NUM_M,
+ (sclk_div - 1) << UART_SCLK_DIV_NUM_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_normal_mode
+ *
+ * Description:
+ * Set the UART to operate in normal mode, i.e., disable the RS485 mode and
+ * IRDA mode.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s * priv)
+{
+ /* Disable RS485 mode */
+
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0);
+
+ /* Disable IRDA mode */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_parity
+ *
+ * Description:
+ * Set the parity, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_parity(const struct esp32s3_uart_s * priv)
+{
+ if (priv->parity == UART_PARITY_DISABLE)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0);
+ }
+ else
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M,
+ ((priv->parity & 0x1) << UART_PARITY_S));
Review comment:
```suggestion
(priv->parity & 0x1) << UART_PARITY_S);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
##########
@@ -0,0 +1,312 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+ #define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define DEFAULT_CPU_FREQ 80
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum cpu_freq_e
+{
+ CPU_80M = 0,
+ CPU_160M = 1,
+ CPU_240M = 2,
+};
+
+enum cpu_clksrc_e
+{
+ XTAL_CLK,
+ PLL_CLK,
+ FOSC_CLK
+};
+
+enum pll_freq_e
+{
+ PLL_320,
+ PLL_480
+};
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us will be
+ * accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
+
+/****************************************************************************
+ * Name: ets_get_cpu_frequency
+ *
+ * Description:
+ * Get the real CPU ticks per us to the ets.
+ * This function do not return real CPU ticks per us, just the record in
+ * ets. It can be used to check with the real CPU frequency.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * CPU ticks per us record in ets.
+ *
+ ****************************************************************************/
+
+extern uint32_t ets_get_cpu_frequency(void);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_cpuclksrc
+ *
+ * Description:
+ * Select a clock source for CPU clock.
+ *
+ * Input Parameters:
+ * src - Any source from cpu_clksrc_e.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static inline void esp32s3_cpuclksrc(enum cpu_clksrc_e src)
+{
+ uint32_t value;
+ value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL);
+ modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value);
+}
+
+/****************************************************************************
+ * Name: esp32s3_cpudiv
+ *
+ * Description:
+ * Select a divider for the CPU clk.
+ * NOTE: The divider is not necessarily the real divisor. See TRM for the
+ * equivalences.
+ *
+ * Input Parameters:
+ * divider - A value between 0 to 2.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static inline void esp32s3_cpudiv(uint8_t divider)
+{
+ uint32_t value;
+ value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL);
+ modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value);
+}
+
+/****************************************************************************
+ * Name: esp32s3_pllfreqsel
+ *
+ * Description:
+ * Select the PLL frequency.
+ *
+ * Input Parameters:
+ * freq - Any clock from enum pll_freq_e
+ *
+ * Returned Value:
+ * None
+ ****************************************************************************/
+
+static inline void esp32s3_pllfreqsel(enum pll_freq_e freq)
+{
+ uint32_t value;
+ value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL);
+ modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_update_cpu_freq
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us
+ * will be accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp32s3_update_cpu_freq(uint32_t ticks_per_us)
+{
+ /* Update scale factors used by esp_rom_delay_us */
+
+ ets_update_cpu_frequency(ticks_per_us);
+}
+
+/****************************************************************************
+ * Name: esp32s3_set_cpu_freq
+ *
+ * Description:
+ * Switch to one of PLL-based frequencies.
+ *
+ * Input Parameters:
+ * cpu_freq_mhz - Target CPU frequency
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp32s3_set_cpu_freq(int cpu_freq_mhz)
+{
+ switch (cpu_freq_mhz)
+ {
+ case 80:
+ /* 80 MHz is obtained from the 480 MHz PLL.
+ * In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz
+ * with a 6 divider and set the source clock as PLL_CLK.
+ */
+
+ esp32s3_cpudiv(0);
+ break;
+
+ case 160:
+ /* 160 MHz is obtained from the 480 MHz PLL.
+ * In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz
+ * with a 3 divider and set the source clock as PLL_CLK.
+ */
+
+ esp32s3_cpudiv(1);
+ break;
+
+ case 240:
+ /* 240 MHz is obtained from the 480 MHz PLL.
+ * In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz
+ * with a 2 divider and set the source clock as PLL_CLK.
+ */
+
+ esp32s3_cpudiv(2);
+ break;
+
+ default:
+
+ /* Unsupported clock config. */
+
+ return;
+ }
+
+ esp32s3_pllfreqsel(PLL_480);
+ esp32s3_cpuclksrc(PLL_CLK);
+ esp32s3_update_cpu_freq(cpu_freq_mhz);
+}
+
+/****************************************************************************
+ * Name: esp32s3_clockconfig
+ *
+ * Description:
+ * Called to initialize the ESP32-S3. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void esp32s3_clockconfig(void)
+{
+ /* Configure the CPU frequency */
+
+ esp32s3_set_cpu_freq(CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ);
+}
+
+/****************************************************************************
+ * Name: esp_clk_cpu_freq
+ *
+ * Description:
+ * Get CPU frequency
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * CPU frequency
+ *
+ ****************************************************************************/
+
+int IRAM_ATTR esp_clk_cpu_freq(void)
+{
+ return ((int) ets_get_cpu_frequency()) * MHZ;
Review comment:
```suggestion
return (int)ets_get_cpu_frequency() * MHZ;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
Review comment:
I think 2 spaces alignment should be used
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
+ freeints = &g_cpu0_freeints;
+
+ intset = *freeints & intmask;
+ if (intset != 0)
+ {
+ /* Skip over initial unavailable CPU interrupts quickly in groups
+ * of 8 interrupt.
+ */
+
+ for (cpuint = 0, bitmask = 0xff;
+ cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0;
+ cpuint += 8, bitmask <<= 8);
+
+ /* Search for an unallocated CPU interrupt number in the remaining
+ * intset.
+ */
+
+ for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++)
+ {
+ /* If the bit corresponding to the CPU interrupt is '1', then
+ * that CPU interrupt is available.
+ */
+
+ bitmask = (1ul << cpuint);
+ if ((intset & bitmask) != 0)
+ {
+ /* Got it! */
+
+ *freeints &= ~bitmask;
+ ret = cpuint;
+ break;
+ }
+ }
+ }
+
+ /* Enable the CPU interrupt now. The interrupt is still not attached
+ * to any peripheral and thus has no effect.
+ */
+
+ if (ret >= 0)
+ {
+ xtensa_enable_cpuint(&g_intenable[cpu], (1ul << ret));
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_alloc_cpuint
+ *
+ * Description:
+ * Allocate a level CPU interrupt
+ *
+ * Input Parameters:
+ * priority - Priority of the CPU interrupt (1-5)
+ * type - Interrupt type (level or edge).
+ *
+ * Returned Value:
+ * On success, the allocated CPU interrupt number is returned.
+ * A negated errno is returned on failure. The only possible failure
+ * is that all CPU interrupts of the requested type have already been
+ * allocated.
+ *
+ ****************************************************************************/
+
+static int esp32s3_alloc_cpuint(int priority, int type)
+{
+ uint32_t mask;
+
+ DEBUGASSERT(priority >= ESP32S3_MIN_PRIORITY &&
+ priority <= ESP32S3_MAX_PRIORITY);
+ DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL ||
+ type == ESP32S3_CPUINT_EDGE);
+
+ if (type == ESP32S3_CPUINT_LEVEL)
+ {
+ /* Check if there are any level CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_LEVELSET;
+ }
+ else
+ {
+ /* Check if there are any edge CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_EDGESET;
+ }
+
+ return esp32s3_getcpuint(mask);
+}
+
+/****************************************************************************
+ * Name: esp32s3_free_cpuint
+ *
+ * Description:
+ * Free a previously allocated CPU interrupt
+ *
+ * Input Parameters:
+ * The CPU interrupt number to be freed
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32s3_free_cpuint(int cpuint)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+
+ /* Mark the CPU interrupt as available */
+
+ bitmask = (1ul << cpuint);
+
+ freeints = &g_cpu0_freeints;
+
+ DEBUGASSERT((*freeints & bitmask) == 0);
+ *freeints |= bitmask;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+ int i;
+ for (i = 0; i < NR_IRQS; i++)
+ {
+ g_irqmap[i] = IRQ_UNMAPPED;
+ }
+
+ /* Hard code special cases. */
+
+ g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0);
+
+ /* Initialize CPU interrupts */
+
+ esp32s3_cpuint_initialize();
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+ /* And finally, enable interrupts. Also clears PS.EXCM */
+
+ up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ int cpu = IRQ_GETCPU(g_irqmap[irq]);
+ int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
+
+ if (g_irqmap[irq] == IRQ_UNMAPPED)
+ {
+ /* This interrupt is already disabled. */
+
+ return;
+ }
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+ DEBUGASSERT(cpu == 0);
+
+ if (irq < XTENSA_NIRQ_INTERNAL)
+ {
+ /* This is an internal CPU interrupt, it cannot be disabled using
+ * the Interrupt Matrix.
+ */
+
+ xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint));
Review comment:
```suggestion
xtensa_disable_cpuint(&g_intenable[cpu], 1ul << cpuint);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
Review comment:
I think 2 spaces alignment should be used
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
+ freeints = &g_cpu0_freeints;
+
+ intset = *freeints & intmask;
+ if (intset != 0)
+ {
+ /* Skip over initial unavailable CPU interrupts quickly in groups
+ * of 8 interrupt.
+ */
+
+ for (cpuint = 0, bitmask = 0xff;
+ cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0;
+ cpuint += 8, bitmask <<= 8);
+
+ /* Search for an unallocated CPU interrupt number in the remaining
+ * intset.
+ */
+
+ for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++)
+ {
+ /* If the bit corresponding to the CPU interrupt is '1', then
+ * that CPU interrupt is available.
+ */
+
+ bitmask = (1ul << cpuint);
+ if ((intset & bitmask) != 0)
+ {
+ /* Got it! */
+
+ *freeints &= ~bitmask;
+ ret = cpuint;
+ break;
+ }
+ }
+ }
+
+ /* Enable the CPU interrupt now. The interrupt is still not attached
+ * to any peripheral and thus has no effect.
+ */
+
+ if (ret >= 0)
+ {
+ xtensa_enable_cpuint(&g_intenable[cpu], (1ul << ret));
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_alloc_cpuint
+ *
+ * Description:
+ * Allocate a level CPU interrupt
+ *
+ * Input Parameters:
+ * priority - Priority of the CPU interrupt (1-5)
+ * type - Interrupt type (level or edge).
+ *
+ * Returned Value:
+ * On success, the allocated CPU interrupt number is returned.
+ * A negated errno is returned on failure. The only possible failure
+ * is that all CPU interrupts of the requested type have already been
+ * allocated.
+ *
+ ****************************************************************************/
+
+static int esp32s3_alloc_cpuint(int priority, int type)
+{
+ uint32_t mask;
+
+ DEBUGASSERT(priority >= ESP32S3_MIN_PRIORITY &&
+ priority <= ESP32S3_MAX_PRIORITY);
+ DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL ||
+ type == ESP32S3_CPUINT_EDGE);
+
+ if (type == ESP32S3_CPUINT_LEVEL)
+ {
+ /* Check if there are any level CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_LEVELSET;
+ }
+ else
+ {
+ /* Check if there are any edge CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_EDGESET;
+ }
+
+ return esp32s3_getcpuint(mask);
+}
+
+/****************************************************************************
+ * Name: esp32s3_free_cpuint
+ *
+ * Description:
+ * Free a previously allocated CPU interrupt
+ *
+ * Input Parameters:
+ * The CPU interrupt number to be freed
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32s3_free_cpuint(int cpuint)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+
+ /* Mark the CPU interrupt as available */
+
+ bitmask = (1ul << cpuint);
+
+ freeints = &g_cpu0_freeints;
+
+ DEBUGASSERT((*freeints & bitmask) == 0);
+ *freeints |= bitmask;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+ int i;
+ for (i = 0; i < NR_IRQS; i++)
+ {
+ g_irqmap[i] = IRQ_UNMAPPED;
+ }
+
+ /* Hard code special cases. */
+
+ g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0);
+
+ /* Initialize CPU interrupts */
+
+ esp32s3_cpuint_initialize();
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+ /* And finally, enable interrupts. Also clears PS.EXCM */
+
+ up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ int cpu = IRQ_GETCPU(g_irqmap[irq]);
+ int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
+
+ if (g_irqmap[irq] == IRQ_UNMAPPED)
+ {
+ /* This interrupt is already disabled. */
+
+ return;
+ }
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+ DEBUGASSERT(cpu == 0);
+
+ if (irq < XTENSA_NIRQ_INTERNAL)
+ {
+ /* This is an internal CPU interrupt, it cannot be disabled using
+ * the Interrupt Matrix.
+ */
+
+ xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint));
+ }
+ else
+ {
+ /* A peripheral interrupt, use the Interrupt Matrix to disable it. */
+
+ int periph = ESP32S3_IRQ2PERIPH(irq);
+ uintptr_t regaddr;
+ uint8_t *intmap;
+
+ DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS);
+ esp32s3_intinfo(cpu, periph, ®addr, &intmap);
+
+ intmap[cpuint] = CPUINT_DISABLE(intmap[cpuint]);
+ putreg32(NO_CPUINT, regaddr);
+ }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ int cpu = IRQ_GETCPU(g_irqmap[irq]);
+ int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+ DEBUGASSERT(cpu == 0);
+
+ if (irq < XTENSA_NIRQ_INTERNAL)
+ {
+ /* Enable the CPU interrupt now for internal CPU. */
+
+ xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint));
+ }
+ else
+ {
+ /* For peripheral interrupts, attach the interrupt to the peripheral;
+ * the CPU interrupt was already enabled when allocated.
+ */
+
+ int periph = ESP32S3_IRQ2PERIPH(irq);
+ uintptr_t regaddr;
+ uint8_t *intmap;
+
+ DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS);
+
+ esp32s3_intinfo(cpu, periph, ®addr, &intmap);
+
+ intmap[cpuint] = CPUINT_ENABLE(intmap[cpuint]);
+ putreg32(cpuint, regaddr);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_cpuint_initialize
+ *
+ * Description:
+ * Initialize CPU interrupts
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned on
+ * any failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_cpuint_initialize(void)
+{
+ uintptr_t regaddr;
+ uint8_t *intmap;
+ int i;
+
+ /* Disable all CPU interrupts on this CPU */
+
+ xtensa_disable_all();
+
+ /* Detach all peripheral sources PRO CPU interrupts */
+
+ for (i = 0; i < ESP32S3_NPERIPHERALS; i++)
+ {
+ regaddr = CORE0_MAP_REGADDR(i);
+
+ putreg32(NO_CPUINT, regaddr);
+ }
+
+ /* Initialize CPU interrupt-to-IRQ mapping table */
+
+ intmap = g_cpu0_intmap;
+
+ /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
+
+ memset(intmap, CPUINT_UNASSIGNED, ESP32S3_NCPUINTS);
+
+ /* Special case the 6 internal interrupts.
+ *
+ * CPU interrupt bit IRQ number
+ * --------------------------- ---------------------
+ * ESP32S3_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0
+ * ESP32S3_CPUINT_SOFTWARE0 7 Not yet defined
+ * ESP32S3_CPUINT_PROFILING 11 Not yet defined
+ * ESP32S3_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1
+ * ESP32S3_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2
+ * ESP32S3_CPUINT_SOFTWARE1 29 Not yet defined
+ */
+
+ intmap[ESP32S3_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0);
+ intmap[ESP32S3_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1);
+ intmap[ESP32S3_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup_irq
+ *
+ * Description:
+ * This function sets up the IRQ. It allocates a CPU interrupt of the given
+ * priority and type and attaches it to the given peripheral.
+ *
+ * Input Parameters:
+ * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ * periphid - The peripheral number from irq.h to be assigned to
+ * a CPU interrupt.
+ * priority - Interrupt's priority (1 - 5).
+ * type - Interrupt's type (level or edge).
+ *
+ * Returned Value:
+ * The allocated CPU interrupt on success, a negated errno value on
+ * failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_setup_irq(int cpu, int periphid, int priority, int type)
+{
+ irqstate_t irqstate;
+ uintptr_t regaddr;
+ uint8_t *intmap;
+ int irq;
+ int cpuint;
+
+ irqstate = enter_critical_section();
+
+ /* Setting up an IRQ includes the following steps:
+ * 1. Allocate a CPU interrupt.
+ * 2. Attach that CPU interrupt to the peripheral.
+ * 3. Map the CPU interrupt to the IRQ to ease searching later.
+ */
+
+ cpuint = esp32s3_alloc_cpuint(priority, type);
+ if (cpuint < 0)
+ {
+ irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d",
+ priority, type);
+ leave_critical_section(irqstate);
+
+ return cpuint;
+ }
+
+ irq = ESP32S3_PERIPH2IRQ(periphid);
+
+ DEBUGASSERT(periphid >= 0 && periphid < ESP32S3_NPERIPHERALS);
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+
+ esp32s3_intinfo(cpu, periphid, ®addr, &intmap);
+
+ DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED);
+
+ intmap[cpuint] = CPUINT_ASSIGN(periphid + XTENSA_IRQ_FIRSTPERIPH);
+ g_irqmap[irq] = IRQ_MKMAP(cpu, cpuint);
+
+ putreg32(cpuint, regaddr);
+
+ leave_critical_section(irqstate);
+
+ return cpuint;
+}
+
+/****************************************************************************
+ * Name: esp32s3_teardown_irq
+ *
+ * Description:
+ * This function undoes the operations done by esp32s3_setup_irq.
+ * It detaches a peripheral interrupt from a CPU interrupt and frees the
+ * CPU interrupt.
+ *
+ * Input Parameters:
+ * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ * periphid - The peripheral number from irq.h to be detached from the
+ * CPU interrupt.
+ * cpuint - The CPU interrupt from which the peripheral interrupt will
+ * be detached.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_teardown_irq(int cpu, int periphid, int cpuint)
+{
+ irqstate_t irqstate;
+ uintptr_t regaddr;
+ uint8_t *intmap;
+ int irq;
+
+ irqstate = enter_critical_section();
+
+ /* Tearing down an IRQ includes the following steps:
+ * 1. Free the previously allocated CPU interrupt.
+ * 2. Detach the interrupt from the peripheral.
+ * 3. Unmap the IRQ from the IRQ-to-cpuint map.
+ */
+
+ esp32s3_free_cpuint(cpuint);
+
+ irq = ESP32S3_PERIPH2IRQ(periphid);
+
+ DEBUGASSERT(periphid >= 0 && periphid < ESP32S3_NPERIPHERALS);
+
+ esp32s3_intinfo(cpu, periphid, ®addr, &intmap);
+
+ DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED);
+ intmap[cpuint] = CPUINT_UNASSIGNED;
+ g_irqmap[irq] = IRQ_UNMAPPED;
+
+ putreg32(NO_CPUINT, regaddr);
+
+ leave_critical_section(irqstate);
+}
+
+/****************************************************************************
+ * Name: xtensa_int_decode
+ *
+ * Description:
+ * Determine the peripheral that generated the interrupt and dispatch
+ * handling to the registered interrupt handler via xtensa_irq_dispatch().
+ *
+ * Input Parameters:
+ * cpuints - Set of pending interrupts valid for this level
+ * regs - Saves processor state on the stack
+ *
+ * Returned Value:
+ * Normally the same value as regs is returned. But, in the event of an
+ * interrupt level context switch, the returned value will, instead point
+ * to the saved processor state in the TCB of the newly started task.
+ *
+ ****************************************************************************/
+
+uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
+{
+ uint8_t *intmap;
+ uint32_t mask;
+ int bit;
+
+#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY
+ board_autoled_on(LED_CPU);
+#endif
+
+ intmap = g_cpu0_intmap;
+
+ /* Skip over zero bits, eight at a time */
+
+ for (bit = 0, mask = 0xff;
+ bit < ESP32S3_NCPUINTS && (cpuints & mask) == 0;
+ bit += 8, mask <<= 8);
+
+ /* Process each pending CPU interrupt */
+
+ for (; bit < ESP32S3_NCPUINTS && cpuints != 0; bit++)
+ {
+ mask = (1 << bit);
Review comment:
```suggestion
mask = 1 << bit;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
Review comment:
I think 2 spaces alignment should be used
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev->priv, sizeof(struct esp32s3_uart_s));
+ }
+ }
+ break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+
+ /* Fill a termios structure with the required information. */
+
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */
+
+ termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
+ ((priv->parity == 1) ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0;
Review comment:
```suggestion
termiosp->c_cflag |= (priv->stop_b2 != 0) ? CSTOPB : 0;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev->priv, sizeof(struct esp32s3_uart_s));
+ }
+ }
+ break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+
+ /* Fill a termios structure with the required information. */
+
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ if (!termiosp)
Review comment:
```suggestion
if (termiosp != NULL)
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev->priv, sizeof(struct esp32s3_uart_s));
+ }
+ }
+ break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+
+ /* Fill a termios structure with the required information. */
+
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */
+
+ termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
+ ((priv->parity == 1) ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0;
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ termiosp->c_cflag |= (priv->oflow) ? CCTS_OFLOW : 0;
+#endif
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ termiosp->c_cflag |= (priv->iflow) ? CRTS_IFLOW : 0;
+#endif
+
+ /* Set the baud rate in ther termiosp using the
+ * cfsetispeed interface.
+ */
+
+ cfsetispeed(termiosp, priv->baud);
+
+ /* Return number of bits. */
+
+ switch (priv->bits)
+ {
+ case 5:
+ termiosp->c_cflag |= CS5;
+ break;
+
+ case 6:
+ termiosp->c_cflag |= CS6;
+ break;
+
+ case 7:
+ termiosp->c_cflag |= CS7;
+ break;
+
+ default:
+ case 8:
+ termiosp->c_cflag |= CS8;
+ break;
+ }
+ }
+ break;
+
+ case TCSETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ uint32_t baud;
+ uint32_t current_int_sts;
+ uint8_t parity;
+ uint8_t bits;
+ uint8_t stop2;
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ bool iflow;
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ bool oflow;
+#endif
+
+ if (!termiosp)
Review comment:
```suggestion
if (termiosp != NULL)
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev->priv, sizeof(struct esp32s3_uart_s));
+ }
+ }
+ break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+
+ /* Fill a termios structure with the required information. */
+
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */
+
+ termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
+ ((priv->parity == 1) ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0;
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ termiosp->c_cflag |= (priv->oflow) ? CCTS_OFLOW : 0;
+#endif
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ termiosp->c_cflag |= (priv->iflow) ? CRTS_IFLOW : 0;
Review comment:
```suggestion
termiosp->c_cflag |= priv->iflow ? CRTS_IFLOW : 0;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.h
##########
@@ -0,0 +1,485 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_gpio_sigmap.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+enum uart_sclk
+{
+ APB_CLK = 1, /* 80 MHz */
+ CLK_8, /* 8 MHz */
+ XTAL_CLK
+};
+
+enum uart_parity
+{
+ UART_PARITY_DISABLE,
+ UART_PARITY_ODD,
+ UART_PARITY_EVEN
+};
+
+enum uart_data_length
+{
+ UART_DATA_5_BITS,
+ UART_DATA_6_BITS,
+ UART_DATA_7_BITS,
+ UART_DATA_8_BITS
+};
+
+enum uart_stop_length
+{
+ UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */
+ UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */
Review comment:
Still is here. Please address
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev->priv, sizeof(struct esp32s3_uart_s));
+ }
+ }
+ break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+
+ /* Fill a termios structure with the required information. */
+
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */
+
+ termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
+ ((priv->parity == 1) ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0;
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ termiosp->c_cflag |= (priv->oflow) ? CCTS_OFLOW : 0;
+#endif
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ termiosp->c_cflag |= (priv->iflow) ? CRTS_IFLOW : 0;
+#endif
+
+ /* Set the baud rate in ther termiosp using the
+ * cfsetispeed interface.
+ */
+
+ cfsetispeed(termiosp, priv->baud);
+
+ /* Return number of bits. */
+
+ switch (priv->bits)
+ {
+ case 5:
+ termiosp->c_cflag |= CS5;
+ break;
+
+ case 6:
+ termiosp->c_cflag |= CS6;
+ break;
+
+ case 7:
+ termiosp->c_cflag |= CS7;
+ break;
+
+ default:
+ case 8:
+ termiosp->c_cflag |= CS8;
+ break;
+ }
+ }
+ break;
+
+ case TCSETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ uint32_t baud;
+ uint32_t current_int_sts;
+ uint8_t parity;
+ uint8_t bits;
+ uint8_t stop2;
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ bool iflow;
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ bool oflow;
+#endif
+
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Get the target baud rate to change. */
+
+ baud = cfgetispeed(termiosp);
+
+ /* Decode number of bits. */
+
+ switch (termiosp->c_cflag & CSIZE)
+ {
+ case CS5:
+ bits = 5;
+ break;
+
+ case CS6:
+ bits = 6;
+ break;
+
+ case CS7:
+ bits = 7;
+ break;
+
+ case CS8:
+ bits = 8;
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Decode parity. */
+
+ if ((termiosp->c_cflag & PARENB) != 0)
+ {
+ parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
Review comment:
```suggestion
parity = (termiosp->c_cflag & PARODD) != 0 ? 1 : 2;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev->priv, sizeof(struct esp32s3_uart_s));
+ }
+ }
+ break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+
+ /* Fill a termios structure with the required information. */
+
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */
+
+ termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
+ ((priv->parity == 1) ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0;
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ termiosp->c_cflag |= (priv->oflow) ? CCTS_OFLOW : 0;
+#endif
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ termiosp->c_cflag |= (priv->iflow) ? CRTS_IFLOW : 0;
+#endif
+
+ /* Set the baud rate in ther termiosp using the
+ * cfsetispeed interface.
+ */
+
+ cfsetispeed(termiosp, priv->baud);
+
+ /* Return number of bits. */
+
+ switch (priv->bits)
+ {
+ case 5:
+ termiosp->c_cflag |= CS5;
+ break;
+
+ case 6:
+ termiosp->c_cflag |= CS6;
+ break;
+
+ case 7:
+ termiosp->c_cflag |= CS7;
+ break;
+
+ default:
+ case 8:
+ termiosp->c_cflag |= CS8;
+ break;
+ }
+ }
+ break;
+
+ case TCSETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ uint32_t baud;
+ uint32_t current_int_sts;
+ uint8_t parity;
+ uint8_t bits;
+ uint8_t stop2;
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ bool iflow;
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ bool oflow;
+#endif
+
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Get the target baud rate to change. */
+
+ baud = cfgetispeed(termiosp);
+
+ /* Decode number of bits. */
+
+ switch (termiosp->c_cflag & CSIZE)
+ {
+ case CS5:
+ bits = 5;
+ break;
+
+ case CS6:
+ bits = 6;
+ break;
+
+ case CS7:
+ bits = 7;
+ break;
+
+ case CS8:
+ bits = 8;
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Decode parity. */
+
+ if ((termiosp->c_cflag & PARENB) != 0)
+ {
+ parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
+ }
+ else
+ {
+ parity = 0;
+ }
+
+ /* Decode stop bits. */
+
+ stop2 = (termiosp->c_cflag & CSTOPB) ? 1 : 0;
Review comment:
```suggestion
stop2 = (termiosp->c_cflag & CSTOPB) != 0 ? 1 : 0;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (!user)
Review comment:
```suggestion
if (user != NULL)
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
+ freeints = &g_cpu0_freeints;
+
+ intset = *freeints & intmask;
+ if (intset != 0)
+ {
+ /* Skip over initial unavailable CPU interrupts quickly in groups
+ * of 8 interrupt.
+ */
+
+ for (cpuint = 0, bitmask = 0xff;
+ cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0;
+ cpuint += 8, bitmask <<= 8);
+
+ /* Search for an unallocated CPU interrupt number in the remaining
+ * intset.
+ */
+
+ for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++)
+ {
+ /* If the bit corresponding to the CPU interrupt is '1', then
+ * that CPU interrupt is available.
+ */
+
+ bitmask = (1ul << cpuint);
+ if ((intset & bitmask) != 0)
+ {
+ /* Got it! */
+
+ *freeints &= ~bitmask;
+ ret = cpuint;
+ break;
+ }
+ }
+ }
+
+ /* Enable the CPU interrupt now. The interrupt is still not attached
+ * to any peripheral and thus has no effect.
+ */
+
+ if (ret >= 0)
+ {
+ xtensa_enable_cpuint(&g_intenable[cpu], (1ul << ret));
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_alloc_cpuint
+ *
+ * Description:
+ * Allocate a level CPU interrupt
+ *
+ * Input Parameters:
+ * priority - Priority of the CPU interrupt (1-5)
+ * type - Interrupt type (level or edge).
+ *
+ * Returned Value:
+ * On success, the allocated CPU interrupt number is returned.
+ * A negated errno is returned on failure. The only possible failure
+ * is that all CPU interrupts of the requested type have already been
+ * allocated.
+ *
+ ****************************************************************************/
+
+static int esp32s3_alloc_cpuint(int priority, int type)
+{
+ uint32_t mask;
+
+ DEBUGASSERT(priority >= ESP32S3_MIN_PRIORITY &&
+ priority <= ESP32S3_MAX_PRIORITY);
+ DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL ||
+ type == ESP32S3_CPUINT_EDGE);
+
+ if (type == ESP32S3_CPUINT_LEVEL)
+ {
+ /* Check if there are any level CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_LEVELSET;
+ }
+ else
+ {
+ /* Check if there are any edge CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_EDGESET;
+ }
+
+ return esp32s3_getcpuint(mask);
+}
+
+/****************************************************************************
+ * Name: esp32s3_free_cpuint
+ *
+ * Description:
+ * Free a previously allocated CPU interrupt
+ *
+ * Input Parameters:
+ * The CPU interrupt number to be freed
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32s3_free_cpuint(int cpuint)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+
+ /* Mark the CPU interrupt as available */
+
+ bitmask = (1ul << cpuint);
+
+ freeints = &g_cpu0_freeints;
+
+ DEBUGASSERT((*freeints & bitmask) == 0);
+ *freeints |= bitmask;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+ int i;
+ for (i = 0; i < NR_IRQS; i++)
+ {
+ g_irqmap[i] = IRQ_UNMAPPED;
+ }
+
+ /* Hard code special cases. */
+
+ g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0);
+
+ /* Initialize CPU interrupts */
+
+ esp32s3_cpuint_initialize();
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+ /* And finally, enable interrupts. Also clears PS.EXCM */
+
+ up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ int cpu = IRQ_GETCPU(g_irqmap[irq]);
+ int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
+
+ if (g_irqmap[irq] == IRQ_UNMAPPED)
+ {
+ /* This interrupt is already disabled. */
+
+ return;
+ }
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+ DEBUGASSERT(cpu == 0);
+
+ if (irq < XTENSA_NIRQ_INTERNAL)
+ {
+ /* This is an internal CPU interrupt, it cannot be disabled using
+ * the Interrupt Matrix.
+ */
+
+ xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint));
+ }
+ else
+ {
+ /* A peripheral interrupt, use the Interrupt Matrix to disable it. */
+
+ int periph = ESP32S3_IRQ2PERIPH(irq);
+ uintptr_t regaddr;
+ uint8_t *intmap;
+
+ DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS);
+ esp32s3_intinfo(cpu, periph, ®addr, &intmap);
+
+ intmap[cpuint] = CPUINT_DISABLE(intmap[cpuint]);
+ putreg32(NO_CPUINT, regaddr);
+ }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ int cpu = IRQ_GETCPU(g_irqmap[irq]);
+ int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+ DEBUGASSERT(cpu == 0);
+
+ if (irq < XTENSA_NIRQ_INTERNAL)
+ {
+ /* Enable the CPU interrupt now for internal CPU. */
+
+ xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint));
Review comment:
```suggestion
xtensa_enable_cpuint(&g_intenable[cpu], 1ul << cpuint);
```
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793507594
##########
File path: arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
##########
@@ -0,0 +1,312 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define DEFAULT_CPU_FREQ 80
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum cpu_freq_e
+{
+ CPU_80M = 0,
+ CPU_160M = 1,
+ CPU_240M = 2,
+};
+
+enum cpu_clksrc_e
+{
+ XTAL_CLK,
+ PLL_CLK,
+ FOSC_CLK
+};
+
+enum pll_freq_e
+{
+ PLL_320,
+ PLL_480
+};
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us will be
+ * accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
Review comment:
Is there an option to create `esp32s3_romapi.h` to list all needed APIs or this is too big effort?
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[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793474529
##########
File path: arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
##########
@@ -0,0 +1,312 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define DEFAULT_CPU_FREQ 80
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum cpu_freq_e
+{
+ CPU_80M = 0,
+ CPU_160M = 1,
+ CPU_240M = 2,
+};
+
+enum cpu_clksrc_e
+{
+ XTAL_CLK,
+ PLL_CLK,
+ FOSC_CLK
+};
+
+enum pll_freq_e
+{
+ PLL_320,
+ PLL_480
+};
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us will be
+ * accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
Review comment:
These functions come from the ROM ELF file. The prototypes are just declared to avoid warnings.
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793509519
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
Review comment:
Thank you for explanation
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[GitHub] [incubator-nuttx] pkarashchenko commented on pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#issuecomment-1023339719
LGTM!
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793425600
##########
File path: arch/xtensa/include/esp32s3/core-isa.h
##########
@@ -0,0 +1,695 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/core-isa.h
+ * Xtensa processor core configuration information.
+ *
+ * Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
Review comment:
Is this a correct copyright header?
##########
File path: arch/xtensa/include/esp32s3/core-isa.h
##########
@@ -0,0 +1,695 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/core-isa.h
+ * Xtensa processor core configuration information.
+ *
+ * Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option
+ * is configured, and a value of 0 otherwise. These macros are always
+ * defined.
+ */
+
+/****************************************************************************
+ * ISA
+ ****************************************************************************/
+
+#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
+#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE 4 /* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG 1 /* debug option */
+#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
+#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
+#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
+#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R 1 /* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
+#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
+#define XCHAL_HAVE_ABS 1 /* ABS instruction */
+
+/* #define XCHAL_HAVE_POPC 0 */ /* POPC instruction */
+
+/* #define XCHAL_HAVE_CRC 0 */ /* CRC instruction */
+
+#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION 0 /* speculation */
+#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS 1 /* */
+#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID 1 /* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
+#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
+#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
+#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
+#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
+#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
+#define XCHAL_HAVE_FUSION 0 /* Fusion*/
+#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
+#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
+#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
+#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
+#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
+#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI 0
+#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
+#define XCHAL_HAVE_FP 1 /* single prec floating point */
+#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
+
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
+#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
+#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
+#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
+#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
+#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
+#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
+#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
+#define XCHAL_HAVE_PDX 0 /* PDX */
+#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
+#define XCHAL_HAVE_PDX4 0 /* PDX4 */
+#define XCHAL_HAVE_PDX8 0 /* PDX8 */
+#define XCHAL_HAVE_PDX16 0 /* PDX16 */
+#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
+#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 Dual LoadStore Flix */
+#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 despread */
+#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
+#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 transpose32x32 */
+#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 viterbi */
+#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
+#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
+#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
+#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
+#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
+#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
+#define XCHAL_HAVE_VISIONC 0 /* Vision C */
+
+/****************************************************************************
+ * MISC
+ ****************************************************************************/
+
+#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */
+#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
+#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
+ /* In T1050, applies to selected core load
+ * and store instructions (see ISA)
+ */
+
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
+#define XCHAL_SW_VERSION 1200012 /* sw version of this header */
+#define XCHAL_CORE_ID "LX7_ESP32_S3_MP" /* alphanum core name
+ * (CoreID) set in the Xtensa
+ * Processor Generator
+ */
+
+#define XCHAL_BUILD_UNIQUE_ID 0x00090F1F /* 22-bit sw build ID */
+
+/* These definitions describe the hardware targeted by this software. */
+
+#define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1 0x23090F1F /* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */
+#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION 270012 /* major*100+minor */
+#define XCHAL_HW_REL_LX7 1
+#define XCHAL_HW_REL_LX7_0 1
+#define XCHAL_HW_REL_LX7_0_12 1
+#define XCHAL_HW_CONFIGID_RELIABLE 1
+
+/* If software targets a range of hardware versions, these are the bounds: */
+
+#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR 12 /* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION 270012 /* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR 12 /* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION 270012 /* latest targeted hw */
+
+/****************************************************************************
+ * CACHE
+ ****************************************************************************/
+
+#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
+#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
+#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
+#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
+#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
+#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
+#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
+#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
+
+/****************************************************************************
+ * Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/****************************************************************************
+ * CACHE
+ ****************************************************************************/
+
+#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
+
+#define XCHAL_HAVE_AXI 0 /* AXI bus */
+#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
+#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
+
+#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
+#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */
+
+/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
+
+/* Number of cache sets in log2(lines per way): */
+
+#define XCHAL_ICACHE_SETWIDTH 0
+#define XCHAL_DCACHE_SETWIDTH 0
+
+/* Cache set associativity (number of ways): */
+
+#define XCHAL_ICACHE_WAYS 1
+#define XCHAL_DCACHE_WAYS 1
+
+/* Cache features: */
+
+#define XCHAL_ICACHE_LINE_LOCKABLE 0
+#define XCHAL_DCACHE_LINE_LOCKABLE 0
+#define XCHAL_ICACHE_ECC_PARITY 0
+#define XCHAL_DCACHE_ECC_PARITY 0
+#define XCHAL_ICACHE_ECC_WIDTH 1
+#define XCHAL_DCACHE_ECC_WIDTH 1
+
+/* Cache access size in bytes (affects operation of SICW instruction): */
+
+#define XCHAL_ICACHE_ACCESS_SIZE 1
+#define XCHAL_DCACHE_ACCESS_SIZE 1
+
+#define XCHAL_DCACHE_BANKS 0 /* number of banks */
+
+/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits) */
+
+#define XCHAL_CA_BITS 4
+
+/****************************************************************************
+ * INTERNAL I/D RAM/ROMs and XLMI
+ ****************************************************************************/
+
+#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
+#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
+#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
+
+/* Instruction RAM 0: */
+
+#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
+#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
+#define XCHAL_INSTRAM0_SIZE 67108864 /* size in bytes */
+#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_HAVE_INSTRAM0 1
+#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
+
+/* Data RAM 0: */
+
+#define XCHAL_DATARAM0_VADDR 0x3C000000 /* virtual address */
+#define XCHAL_DATARAM0_PADDR 0x3C000000 /* physical address */
+#define XCHAL_DATARAM0_SIZE 67108864 /* size in bytes */
+#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
+#define XCHAL_HAVE_DATARAM0 1
+#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
+
+#define XCHAL_HAVE_IDMA 0
+#define XCHAL_HAVE_IDMA_TRANSPOSE 0
+
+#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM */
+
+/****************************************************************************
+ * INTERRUPTS and TIMERS
+ ****************************************************************************/
+
+#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
+ * (not including level zero)
+ */
+
+#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
+
+/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/* Masks of interrupts at each interrupt level: */
+
+#define XCHAL_INTLEVEL1_MASK 0x000637FF
+#define XCHAL_INTLEVEL2_MASK 0x00380000
+#define XCHAL_INTLEVEL3_MASK 0x28C08800
+#define XCHAL_INTLEVEL4_MASK 0x53000000
+#define XCHAL_INTLEVEL5_MASK 0x84010000
+#define XCHAL_INTLEVEL6_MASK 0x00000000
+#define XCHAL_INTLEVEL7_MASK 0x00004000
+
+/* Masks of interrupts at each range 1..n of interrupt levels: */
+
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
+
+/* Level of each interrupt: */
+
+#define XCHAL_INT0_LEVEL 1
+#define XCHAL_INT1_LEVEL 1
+#define XCHAL_INT2_LEVEL 1
+#define XCHAL_INT3_LEVEL 1
+#define XCHAL_INT4_LEVEL 1
+#define XCHAL_INT5_LEVEL 1
+#define XCHAL_INT6_LEVEL 1
+#define XCHAL_INT7_LEVEL 1
+#define XCHAL_INT8_LEVEL 1
+#define XCHAL_INT9_LEVEL 1
+#define XCHAL_INT10_LEVEL 1
+#define XCHAL_INT11_LEVEL 3
+#define XCHAL_INT12_LEVEL 1
+#define XCHAL_INT13_LEVEL 1
+#define XCHAL_INT14_LEVEL 7
+#define XCHAL_INT15_LEVEL 3
+#define XCHAL_INT16_LEVEL 5
+#define XCHAL_INT17_LEVEL 1
+#define XCHAL_INT18_LEVEL 1
+#define XCHAL_INT19_LEVEL 2
+#define XCHAL_INT20_LEVEL 2
+#define XCHAL_INT21_LEVEL 2
+#define XCHAL_INT22_LEVEL 3
+#define XCHAL_INT23_LEVEL 3
+#define XCHAL_INT24_LEVEL 4
+#define XCHAL_INT25_LEVEL 4
+#define XCHAL_INT26_LEVEL 5
+#define XCHAL_INT27_LEVEL 3
+#define XCHAL_INT28_LEVEL 4
+#define XCHAL_INT29_LEVEL 3
+#define XCHAL_INT30_LEVEL 4
+#define XCHAL_INT31_LEVEL 5
+#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
+#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
+ * EXCSAVE/EPS/EPC_n, RFI n)
+ */
+
+/* Type of each interrupt: */
+
+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+
+/* Masks of interrupts for each type of interrupt: */
+
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
+#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
+#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
+#define XCHAL_INTTYPE_MASK_NMI 0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
+#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
+#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
+
+/* Interrupt numbers assigned to specific interrupt sources: */
+
+#define XTHAL_TIMER_UNCONFIGURED -1
+#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
+#define XCHAL_PROFILING_INTERRUPT 11
+
+/* Interrupt numbers for levels at which only one interrupt is configured: */
+
+#define XCHAL_INTLEVEL7_NUM 14
+
+/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
+
+/* External interrupt mapping.
+ * These macros describe how Xtensa processor interrupt numbers
+ * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ * map to external BInterrupt<n> pins, for those interrupts
+ * configured as external (level-triggered, edge-triggered, or NMI).
+ * See the Xtensa processor databook for more details.
+ */
+
+/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
+
+#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
+#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
+#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
+#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
+#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
+#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
+#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
+#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
+#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
+#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
+#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
+#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
+#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
+#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
+#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
+#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
+#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
+
+/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
+
+#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
+#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
+#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
+#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
+#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
+#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
+#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
+#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
+#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
+#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
+#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
+#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
+#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
+#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
+#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
+#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
+#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
+#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
+#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
+#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
+#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
+
+/****************************************************************************
+ * EXCEPTIONS and VECTORS
+ ****************************************************************************/
+
+#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
+ * number: 1 == XEA1 (old)
+ * 2 == XEA2 (new)
+ * 0 == XEAX (extern) or TX
+ */
+
+#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
+#define XCHAL_HAVE_HALT 0 /* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
+#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR 0x40000000
+#define XCHAL_RESET_VECBASE_OVERLAP 0
+
+#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
+#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
+#define XCHAL_RESET_VECTOR_VADDR 0x40000400
+#define XCHAL_RESET_VECTOR_PADDR 0x40000400
+#define XCHAL_USER_VECOFS 0x00000340
+#define XCHAL_USER_VECTOR_VADDR 0x40000340
+#define XCHAL_USER_VECTOR_PADDR 0x40000340
+#define XCHAL_KERNEL_VECOFS 0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
+#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
+#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
+#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
+#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
+#define XCHAL_INTLEVEL2_VECOFS 0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
+#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
+#define XCHAL_INTLEVEL4_VECOFS 0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
+#define XCHAL_INTLEVEL5_VECOFS 0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
+#define XCHAL_INTLEVEL6_VECOFS 0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
+#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS 0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
+#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
+#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
+
+/****************************************************************************
+ * DEBUG MODULE
+ ****************************************************************************/
+
+/* Misc */
+
+#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
+
+/* On-Chip Debug (OCD) */
+
+#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
+#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
+
+/* TRAX (in core) */
+#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
+
+/* Perf counters */
+
+#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
+
+/****************************************************************************
+ * MMU
+ ****************************************************************************/
+
+/* See core-matmap.h header file for more details. */
+
+#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
+ * [autorefill] and protection)
+ * usable for an MMU-based OS
+ */
+
+/* If none of the above last 5 are set, it's a custom TLB configuration. */
+
+#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
+
+/****************************************************************************
+ * MPU
+ ****************************************************************************/
+
+#define XCHAL_HAVE_MPU 0
+#define XCHAL_MPU_ENTRIES 0
+
+#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
+#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
+#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
+
+#define XCHAL_MPU_ALIGN_BITS 0
+#define XCHAL_MPU_ALIGN 0
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
Review comment:
```suggestion
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H */
```
##########
File path: arch/xtensa/include/esp32s3/tie.h
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie.h
+ * Compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality. It is customized to this
+ * Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
Review comment:
Is this a correct copyright header?
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
Review comment:
```suggestion
.iflow = true, /* input flow control (RTS) enabled */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
Review comment:
```suggestion
.iflow = false, /* input flow control (RTS) disabled */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
Review comment:
```suggestion
.oflow = true, /* output flow control (CTS) enabled */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART1 */
+#endif /* HAVE_UART_DEVICE */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable)
+{
+ uint32_t mask;
+ if (enable)
+ {
+ /* Enable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
+
+ /* Configure the threshold */
+
+ mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
+ }
+ else
+ {
+ /* Disable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable)
+{
+ if (enable)
+ {
+ /* Enable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
+ }
+ else
+ {
+ /* Disable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RST_CORE_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
+ 1 << UART_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
+ 1 << UART_RX_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
+ 1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source)
+{
+ uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
+{
+ uint32_t clk_conf_reg;
+ uint32_t ret = -ENODATA;
+ clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
+ clk_conf_reg &= UART_SCLK_SEL_M;
+ clk_conf_reg >>= UART_SCLK_SEL_S;
Review comment:
```suggestion
uint32_t ret = -ENODATA;
clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
clk_conf_reg &= UART_SCLK_SEL_M;
clk_conf_reg >>= UART_SCLK_SEL_S;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if (int_status & tx_mask)
Review comment:
```suggestion
if ((int_status & tx_mask) != 0)
```
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
##########
@@ -0,0 +1,118 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H_
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H_
Review comment:
```suggestion
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H
```
##########
File path: arch/xtensa/include/esp32s3/tie.h
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie.h
+ * Compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality. It is customized to this
+ * Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+
+#define XCHAL_CP_NUM 2 /* number of coprocessors */
+#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
Review comment:
The effort to fix it seems to be not so big
##########
File path: arch/xtensa/include/esp32s3/tie.h
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie.h
+ * Compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality. It is customized to this
+ * Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+
+#define XCHAL_CP_NUM 2 /* number of coprocessors */
+#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
+
+/* Basic parameters of each coprocessor: */
+#define XCHAL_CP0_NAME "FPU"
+#define XCHAL_CP0_IDENT FPU
+#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
+#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
+#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
+#define XCHAL_CP3_NAME "cop_ai"
+#define XCHAL_CP3_IDENT cop_ai
+#define XCHAL_CP3_SA_SIZE 208 /* size of state save area */
+#define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */
+#define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0..7) */
+
+/* Filler info for unassigned coprocessors, to simplify arrays etc: */
+#define XCHAL_CP1_SA_SIZE 0
+#define XCHAL_CP1_SA_ALIGN 1
+#define XCHAL_CP2_SA_SIZE 0
+#define XCHAL_CP2_SA_ALIGN 1
+#define XCHAL_CP4_SA_SIZE 0
+#define XCHAL_CP4_SA_ALIGN 1
+#define XCHAL_CP5_SA_SIZE 0
+#define XCHAL_CP5_SA_ALIGN 1
+#define XCHAL_CP6_SA_SIZE 0
+#define XCHAL_CP6_SA_ALIGN 1
+#define XCHAL_CP7_SA_SIZE 0
+#define XCHAL_CP7_SA_ALIGN 1
+
+/* Save area for non-coprocessor optional and custom (TIE) state: */
+#define XCHAL_NCP_SA_SIZE 36
+#define XCHAL_NCP_SA_ALIGN 4
+
+/* Total save area for optional and custom state (NCP + CPn): */
+#define XCHAL_TOTAL_SA_SIZE 336 /* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
+
+/*
+ * Detailed contents of save areas.
+ * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ * dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ * ccused = set if used by compiler without special options or code
+ * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ * name = lowercase reg name (no quotes)
+ * galign = group byte alignment (power of 2) (galign >= align)
+ * align = register byte alignment (power of 2)
+ * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ * (not including any pad bytes required to galign this or next reg)
+ * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ * regnum = reg index in regfile, or special/TIE-user reg number
+ * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ * gapsz = intervening bits, if bitsz bits not stored contiguously
+ * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ * reset = register reset value (or 0 if undefined at reset)
+ * x = reserved for future use (0 until then)
+ *
+ * To filter out certain registers, e.g. to expand only the non-global
+ * registers used by the compiler, you can do something like this:
+ *
+ * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
+ * #define SELCC0(p...)
+ * #define SELCC1(abikind,p...) SELAK##abikind(p)
+ * #define SELAK0(p...) REG(p)
+ * #define SELAK1(p...) REG(p)
+ * #define SELAK2(p...)
+ * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ * ...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM 9
+#define XCHAL_NCP_SA_LIST(s) \
+ XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
+
+#define XCHAL_CP0_SA_NUM 18
+#define XCHAL_CP0_SA_LIST(s) \
+ XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
+
+#define XCHAL_CP1_SA_NUM 0
+#define XCHAL_CP1_SA_LIST(s) /* empty */
+
+#define XCHAL_CP2_SA_NUM 0
+#define XCHAL_CP2_SA_LIST(s) /* empty */
+
+#define XCHAL_CP3_SA_NUM 26
+#define XCHAL_CP3_SA_LIST(s) \
+ XCHAL_SA_REG(s,0,0,1,0, accx_0,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, accx_1, 4, 4, 4,0x0301, ur,1 , 8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_0, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_1, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_2, 4, 4, 4,0x0304, ur,4 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_3, 4, 4, 4,0x0305, ur,5 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_4, 4, 4, 4,0x0306, ur,6 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_0, 4, 4, 4,0x0307, ur,7 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_1, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_2, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_3, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_4, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 4,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, fft_bit_width, 4, 4, 4,0x030E, ur,14 , 4,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, ua_state_0, 4, 4, 4,0x030F, ur,15 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, ua_state_1, 4, 4, 4,0x0310, ur,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, ua_state_2, 4, 4, 4,0x0311, ur,17 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, ua_state_3, 4, 4, 4,0x0312, ur,18 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q0,16,16,16,0x1008, q,0 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q1,16,16,16,0x1009, q,1 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q2,16,16,16,0x100A, q,2 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q3,16,16,16,0x100B, q,3 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q4,16,16,16,0x100C, q,4 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q6,16,16,16,0x100E, q,6 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q7,16,16,16,0x100F, q,7 ,128,0,0,0)
+
+#define XCHAL_CP4_SA_NUM 0
+#define XCHAL_CP4_SA_LIST(s) /* empty */
+
+#define XCHAL_CP5_SA_NUM 0
+#define XCHAL_CP5_SA_LIST(s) /* empty */
+
+#define XCHAL_CP6_SA_NUM 0
+#define XCHAL_CP6_SA_LIST(s) /* empty */
+
+#define XCHAL_CP7_SA_NUM 0
+#define XCHAL_CP7_SA_LIST(s) /* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
+#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
+/* Byte length of instruction from its first byte, per FLIX. */
+#define XCHAL_BYTE0_FORMAT_LENGTHS \
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
+
+#endif /*_XTENSA_CORE_TIE_H*/
Review comment:
```suggestion
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H */
```
##########
File path: arch/xtensa/include/esp32s3/tie-asm.h
##########
@@ -0,0 +1,433 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie-asm.h
+ * Compile-time HAL assembler definitions dependent on CORE & TIE
+ * configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file contains assembly-language definitions (assembly
+ * macros, etc.) for this specific Xtensa processor's TIE extensions
+ * and options. It is customized to this Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H
+
+/* Selection parameter values for save-area save/restore macros: */
+/* Option vs. TIE: */
+#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
+#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
+#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
+/* Whether used automatically by compiler: */
+#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
+#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
+/* ABI handling across function calls: */
+#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
+#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
+#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
+#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
+/* Misc */
+#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
+#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
+ | ((ccuse) & XTHAL_SAS_ANYCC) \
+ | ((abi) & XTHAL_SAS_ANYABI) )
+
+
+ /*
+ * Macro to store all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 4 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters:
+ * continue If macro invoked as part of a larger store sequence, set to 1
+ * if this is not the first in the sequence. Defaults to 0.
+ * ofs Offset from start of larger sequence (from value of first ptr
+ * in sequence) at which to store. Defaults to next available space
+ * (or 0 if <continue> is 0).
+ * select Select what category(ies) of registers to store, as a bitmask
+ * (see XTHAL_SAS_xxx constants). Defaults to all registers.
+ * alloc Select what category(ies) of registers to allocate; if any
+ * category is selected here that is not in <select>, space for
+ * the corresponding registers is skipped without doing any store.
+ */
+ .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Optional global registers used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+ xchal_sa_align \ptr, 0, 1016, 4, 4
+ rur.THREADPTR \at1 // threadptr option
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 1016, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
+ .endif
+ // Optional caller-saved registers used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 1012, 4, 4
+ rsr.ACCLO \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ rsr.ACCHI \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 1012, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
+ .endif
+ // Optional caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 996, 4, 4
+ rsr.BR \at1 // boolean option
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ rsr.SCOMPARE1 \at1 // conditional store option
+ s32i \at1, \ptr, .Lxchal_ofs_+4
+ rsr.M0 \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+8
+ rsr.M1 \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+12
+ rsr.M2 \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+16
+ rsr.M3 \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+20
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 996, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
+ .endif
+ .endm // xchal_ncp_store
+
+ /*
+ * Macro to load all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 4 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters:
+ * continue If macro invoked as part of a larger load sequence, set to 1
+ * if this is not the first in the sequence. Defaults to 0.
+ * ofs Offset from start of larger sequence (from value of first ptr
+ * in sequence) at which to load. Defaults to next available space
+ * (or 0 if <continue> is 0).
+ * select Select what category(ies) of registers to load, as a bitmask
+ * (see XTHAL_SAS_xxx constants). Defaults to all registers.
+ * alloc Select what category(ies) of registers to allocate; if any
+ * category is selected here that is not in <select>, space for
+ * the corresponding registers is skipped without doing any load.
+ */
+ .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Optional global registers used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+ xchal_sa_align \ptr, 0, 1016, 4, 4
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wur.THREADPTR \at1 // threadptr option
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 1016, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
+ .endif
+ // Optional caller-saved registers used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 1012, 4, 4
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wsr.ACCLO \at1 // MAC16 option
+ l32i \at1, \ptr, .Lxchal_ofs_+4
+ wsr.ACCHI \at1 // MAC16 option
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 1012, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
+ .endif
+ // Optional caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 996, 4, 4
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wsr.BR \at1 // boolean option
+ l32i \at1, \ptr, .Lxchal_ofs_+4
+ wsr.SCOMPARE1 \at1 // conditional store option
+ l32i \at1, \ptr, .Lxchal_ofs_+8
+ wsr.M0 \at1 // MAC16 option
+ l32i \at1, \ptr, .Lxchal_ofs_+12
+ wsr.M1 \at1 // MAC16 option
+ l32i \at1, \ptr, .Lxchal_ofs_+16
+ wsr.M2 \at1 // MAC16 option
+ l32i \at1, \ptr, .Lxchal_ofs_+20
+ wsr.M3 \at1 // MAC16 option
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 996, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
+ .endif
+ .endm // xchal_ncp_load
+
+
+#define XCHAL_NCP_NUM_ATMPS 1
+
+ /*
+ * Macro to store the state of TIE coprocessor FPU.
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 4 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters are the same as for xchal_ncp_store.
+ */
+#define xchal_cp_FPU_store xchal_cp0_store
+ .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Custom caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 948, 4, 4
+ rur.FCR \at1 // ureg 232
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ rur.FSR \at1 // ureg 233
+ s32i \at1, \ptr, .Lxchal_ofs_+4
+ ssi f0, \ptr, .Lxchal_ofs_+8
+ ssi f1, \ptr, .Lxchal_ofs_+12
+ ssi f2, \ptr, .Lxchal_ofs_+16
+ ssi f3, \ptr, .Lxchal_ofs_+20
+ ssi f4, \ptr, .Lxchal_ofs_+24
+ ssi f5, \ptr, .Lxchal_ofs_+28
+ ssi f6, \ptr, .Lxchal_ofs_+32
+ ssi f7, \ptr, .Lxchal_ofs_+36
+ ssi f8, \ptr, .Lxchal_ofs_+40
+ ssi f9, \ptr, .Lxchal_ofs_+44
+ ssi f10, \ptr, .Lxchal_ofs_+48
+ ssi f11, \ptr, .Lxchal_ofs_+52
+ ssi f12, \ptr, .Lxchal_ofs_+56
+ ssi f13, \ptr, .Lxchal_ofs_+60
+ ssi f14, \ptr, .Lxchal_ofs_+64
+ ssi f15, \ptr, .Lxchal_ofs_+68
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
+ .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 948, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
+ .endif
+ .endm // xchal_cp0_store
+
+ /*
+ * Macro to load the state of TIE coprocessor FPU.
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 4 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters are the same as for xchal_ncp_load.
+ */
+#define xchal_cp_FPU_load xchal_cp0_load
+ .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Custom caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 948, 4, 4
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wur.FCR \at1 // ureg 232
+ l32i \at1, \ptr, .Lxchal_ofs_+4
+ wur.FSR \at1 // ureg 233
+ lsi f0, \ptr, .Lxchal_ofs_+8
+ lsi f1, \ptr, .Lxchal_ofs_+12
+ lsi f2, \ptr, .Lxchal_ofs_+16
+ lsi f3, \ptr, .Lxchal_ofs_+20
+ lsi f4, \ptr, .Lxchal_ofs_+24
+ lsi f5, \ptr, .Lxchal_ofs_+28
+ lsi f6, \ptr, .Lxchal_ofs_+32
+ lsi f7, \ptr, .Lxchal_ofs_+36
+ lsi f8, \ptr, .Lxchal_ofs_+40
+ lsi f9, \ptr, .Lxchal_ofs_+44
+ lsi f10, \ptr, .Lxchal_ofs_+48
+ lsi f11, \ptr, .Lxchal_ofs_+52
+ lsi f12, \ptr, .Lxchal_ofs_+56
+ lsi f13, \ptr, .Lxchal_ofs_+60
+ lsi f14, \ptr, .Lxchal_ofs_+64
+ lsi f15, \ptr, .Lxchal_ofs_+68
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
+ .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 948, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
+ .endif
+ .endm // xchal_cp0_load
+
+#define XCHAL_CP0_NUM_ATMPS 1
+ /*
+ * Macro to store the state of TIE coprocessor cop_ai.
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 16 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters are the same as for xchal_ncp_store.
+ */
+#define xchal_cp_cop_ai_store xchal_cp3_store
+ .macro xchal_cp3_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Custom caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 0, 16, 16
+ rur.ACCX_0 \at1 // ureg 0
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ rur.ACCX_1 \at1 // ureg 1
+ s32i \at1, \ptr, .Lxchal_ofs_+4
+ rur.QACC_H_0 \at1 // ureg 2
+ s32i \at1, \ptr, .Lxchal_ofs_+8
+ rur.QACC_H_1 \at1 // ureg 3
+ s32i \at1, \ptr, .Lxchal_ofs_+12
+ rur.QACC_H_2 \at1 // ureg 4
+ s32i \at1, \ptr, .Lxchal_ofs_+16
+ rur.QACC_H_3 \at1 // ureg 5
+ s32i \at1, \ptr, .Lxchal_ofs_+20
+ rur.QACC_H_4 \at1 // ureg 6
+ s32i \at1, \ptr, .Lxchal_ofs_+24
+ rur.QACC_L_0 \at1 // ureg 7
+ s32i \at1, \ptr, .Lxchal_ofs_+28
+ rur.QACC_L_1 \at1 // ureg 8
+ s32i \at1, \ptr, .Lxchal_ofs_+32
+ rur.QACC_L_2 \at1 // ureg 9
+ s32i \at1, \ptr, .Lxchal_ofs_+36
+ rur.QACC_L_3 \at1 // ureg 10
+ s32i \at1, \ptr, .Lxchal_ofs_+40
+ rur.QACC_L_4 \at1 // ureg 11
+ s32i \at1, \ptr, .Lxchal_ofs_+44
+ rur.SAR_BYTE \at1 // ureg 13
+ s32i \at1, \ptr, .Lxchal_ofs_+48
+ rur.FFT_BIT_WIDTH \at1 // ureg 14
+ s32i \at1, \ptr, .Lxchal_ofs_+52
+ rur.UA_STATE_0 \at1 // ureg 15
+ s32i \at1, \ptr, .Lxchal_ofs_+56
+ rur.UA_STATE_1 \at1 // ureg 16
+ s32i \at1, \ptr, .Lxchal_ofs_+60
+ rur.UA_STATE_2 \at1 // ureg 17
+ s32i \at1, \ptr, .Lxchal_ofs_+64
+ rur.UA_STATE_3 \at1 // ureg 18
+ s32i \at1, \ptr, .Lxchal_ofs_+68
+ st.qr q0, \ptr, .Lxchal_ofs_+80
+ st.qr q1, \ptr, .Lxchal_ofs_+96
+ st.qr q2, \ptr, .Lxchal_ofs_+112
+ addi \ptr, \ptr, 128
+ st.qr q3, \ptr, .Lxchal_ofs_+0
+ st.qr q4, \ptr, .Lxchal_ofs_+16
+ st.qr q5, \ptr, .Lxchal_ofs_+32
+ st.qr q6, \ptr, .Lxchal_ofs_+48
+ st.qr q7, \ptr, .Lxchal_ofs_+64
+ .set .Lxchal_pofs_, .Lxchal_pofs_ + 128
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 80
+ .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 0, 16, 16
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 208
+ .endif
+ .endm // xchal_cp3_store
+
+ /*
+ * Macro to load the state of TIE coprocessor cop_ai.
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 16 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters are the same as for xchal_ncp_load.
+ */
+#define xchal_cp_cop_ai_load xchal_cp3_load
+ .macro xchal_cp3_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Custom caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 0, 16, 16
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wur.ACCX_0 \at1 // ureg 0
+ l32i \at1, \ptr, .Lxchal_ofs_+4
+ wur.ACCX_1 \at1 // ureg 1
+ l32i \at1, \ptr, .Lxchal_ofs_+8
+ wur.QACC_H_0 \at1 // ureg 2
+ l32i \at1, \ptr, .Lxchal_ofs_+12
+ wur.QACC_H_1 \at1 // ureg 3
+ l32i \at1, \ptr, .Lxchal_ofs_+16
+ wur.QACC_H_2 \at1 // ureg 4
+ l32i \at1, \ptr, .Lxchal_ofs_+20
+ wur.QACC_H_3 \at1 // ureg 5
+ l32i \at1, \ptr, .Lxchal_ofs_+24
+ wur.QACC_H_4 \at1 // ureg 6
+ l32i \at1, \ptr, .Lxchal_ofs_+28
+ wur.QACC_L_0 \at1 // ureg 7
+ l32i \at1, \ptr, .Lxchal_ofs_+32
+ wur.QACC_L_1 \at1 // ureg 8
+ l32i \at1, \ptr, .Lxchal_ofs_+36
+ wur.QACC_L_2 \at1 // ureg 9
+ l32i \at1, \ptr, .Lxchal_ofs_+40
+ wur.QACC_L_3 \at1 // ureg 10
+ l32i \at1, \ptr, .Lxchal_ofs_+44
+ wur.QACC_L_4 \at1 // ureg 11
+ l32i \at1, \ptr, .Lxchal_ofs_+48
+ wur.SAR_BYTE \at1 // ureg 13
+ l32i \at1, \ptr, .Lxchal_ofs_+52
+ wur.FFT_BIT_WIDTH \at1 // ureg 14
+ l32i \at1, \ptr, .Lxchal_ofs_+56
+ wur.UA_STATE_0 \at1 // ureg 15
+ l32i \at1, \ptr, .Lxchal_ofs_+60
+ wur.UA_STATE_1 \at1 // ureg 16
+ l32i \at1, \ptr, .Lxchal_ofs_+64
+ wur.UA_STATE_2 \at1 // ureg 17
+ l32i \at1, \ptr, .Lxchal_ofs_+68
+ wur.UA_STATE_3 \at1 // ureg 18
+ ld.qr q0, \ptr, .Lxchal_ofs_+80
+ ld.qr q1, \ptr, .Lxchal_ofs_+96
+ ld.qr q2, \ptr, .Lxchal_ofs_+112
+ addi \ptr, \ptr, 128
+ ld.qr q3, \ptr, .Lxchal_ofs_+0
+ ld.qr q4, \ptr, .Lxchal_ofs_+16
+ ld.qr q5, \ptr, .Lxchal_ofs_+32
+ ld.qr q6, \ptr, .Lxchal_ofs_+48
+ ld.qr q7, \ptr, .Lxchal_ofs_+64
+ .set .Lxchal_pofs_, .Lxchal_pofs_ + 128
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 80
+ .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 0, 16, 16
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 208
+ .endif
+ .endm // xchal_cp3_load
+
+#define XCHAL_CP3_NUM_ATMPS 1
+#define XCHAL_SA_NUM_ATMPS 1
+
+ /* Empty macros for unconfigured coprocessors: */
+ .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+
+#endif /*_XTENSA_CORE_TIE_ASM_H*/
Review comment:
```suggestion
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H */
```
##########
File path: arch/xtensa/include/esp32s3/tie-asm.h
##########
@@ -0,0 +1,433 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie-asm.h
+ * Compile-time HAL assembler definitions dependent on CORE & TIE
+ * configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file contains assembly-language definitions (assembly
+ * macros, etc.) for this specific Xtensa processor's TIE extensions
+ * and options. It is customized to this Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
Review comment:
Id this a correct copyright header?
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
Review comment:
Why this is inited to `-ENOMEM`?
##########
File path: arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
##########
@@ -0,0 +1,312 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define DEFAULT_CPU_FREQ 80
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum cpu_freq_e
+{
+ CPU_80M = 0,
+ CPU_160M = 1,
+ CPU_240M = 2,
+};
+
+enum cpu_clksrc_e
+{
+ XTAL_CLK,
+ PLL_CLK,
+ FOSC_CLK
+};
+
+enum pll_freq_e
+{
+ PLL_320,
+ PLL_480
+};
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us will be
+ * accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
Review comment:
So this can't be included from any internal header right?
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
Review comment:
```suggestion
.oflow = true, /* output flow control (CTS) enabled */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.c
##########
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
Review comment:
Do we expect other index than `0`? If yes, then `volatile uint32_t *g_current_regs[1];` is not appropriate. If no, then I do not understand why cpu index code is needed here and in other files.
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
Review comment:
```suggestion
.stop_b2 = CONFIG_UART0_2STOP,
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
##########
@@ -0,0 +1,312 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
Review comment:
```suggestion
# define MIN(a, b) (((a) < (b)) ? (a) : (b))
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
##########
@@ -0,0 +1,312 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define DEFAULT_CPU_FREQ 80
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum cpu_freq_e
+{
+ CPU_80M = 0,
+ CPU_160M = 1,
+ CPU_240M = 2,
+};
+
+enum cpu_clksrc_e
+{
+ XTAL_CLK,
+ PLL_CLK,
+ FOSC_CLK
+};
+
+enum pll_freq_e
+{
+ PLL_320,
+ PLL_480
+};
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us will be
+ * accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
Review comment:
```suggestion
* Name: ets_get_cpu_frequency
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
Review comment:
```suggestion
.iflow = false, /* input flow control (RTS) disabled */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
Review comment:
```suggestion
.oflow = false, /* output flow control (CTS) disabled */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
Review comment:
```suggestion
.stop_b2 = CONFIG_UART1_2STOP,
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_irq.h
##########
@@ -0,0 +1,123 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
Review comment:
I think we can swap this with `Pre-processor Definitions` section
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
Review comment:
```suggestion
.iflow = true, /* input flow control (RTS) enabled */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
Review comment:
```suggestion
.oflow = false, /* output flow control (CTS) disabled */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART1 */
+#endif /* HAVE_UART_DEVICE */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable)
+{
+ uint32_t mask;
+ if (enable)
+ {
+ /* Enable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
+
+ /* Configure the threshold */
+
+ mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
+ }
+ else
+ {
+ /* Disable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable)
+{
+ if (enable)
+ {
+ /* Enable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
+ }
+ else
+ {
+ /* Disable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RST_CORE_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
+ 1 << UART_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
+ 1 << UART_RX_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
+ 1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source)
+{
+ uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
+{
+ uint32_t clk_conf_reg;
+ uint32_t ret = -ENODATA;
+ clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
+ clk_conf_reg &= UART_SCLK_SEL_M;
+ clk_conf_reg >>= UART_SCLK_SEL_S;
+ switch (clk_conf_reg)
+ {
+ case 1:
+ ret = esp_clk_apb_freq();
+ break;
+ case 2:
+ ret = RTC_CLK_FREQ;
+ break;
+ case 3:
+ ret = XTAL_CLK_FREQ;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_baud
+ *
+ * Description:
+ * Set the baud rate according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_baud(const struct esp32s3_uart_s * priv)
+{
+ int sclk_div;
+ uint32_t sclk_freq;
+ uint32_t clk_div;
+ uint32_t int_part;
+ uint32_t frag_part;
+
+ /* Get serial clock */
+
+ sclk_freq = esp32s3_lowputc_get_sclk(priv);
+
+ /* Calculate integral part of the frequency divider factor.
+ * For low baud rates, the sclk must be less than half.
+ * For high baud rates, the sclk must be the higher.
+ */
+
+ sclk_div = DIV_UP(sclk_freq, MAX_UART_CLKDIV * priv->baud);
+
+ /* Calculate the clock divisor to achieve the baud rate.
+ * baud = f/clk_div
+ * f = sclk_freq/sclk_div
+ * clk_div = 16*int_part + frag_part
+ * 16*int_part + frag_part = 16*(sclk_freq/sclk_div)/baud
+ */
+
+ clk_div = ((sclk_freq) << 4) / (priv->baud * sclk_div);
+
+ /* Get the integer part of it. */
+
+ int_part = clk_div >> 4;
+
+ /* Get the frag part of it. */
+
+ frag_part = clk_div & 0xf;
+
+ /* Set integer part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part);
+
+ /* Set decimal part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M,
+ (frag_part & UART_CLKDIV_FRAG_V) << UART_CLKDIV_FRAG_S);
+
+ /* Set the the integral part of the frequency divider factor. */
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_DIV_NUM_M,
+ (sclk_div - 1) << UART_SCLK_DIV_NUM_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_normal_mode
+ *
+ * Description:
+ * Set the UART to operate in normal mode, i.e., disable the RS485 mode and
+ * IRDA mode.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s * priv)
+{
+ /* Disable RS485 mode */
+
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0);
+
+ /* Disable IRDA mode */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_parity
+ *
+ * Description:
+ * Set the parity, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_parity(const struct esp32s3_uart_s * priv)
+{
+ if (priv->parity == UART_PARITY_DISABLE)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0);
+ }
+ else
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M,
+ ((priv->parity & 0x1) << UART_PARITY_S));
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M,
+ 1 << UART_PARITY_EN_S);
Review comment:
```suggestion
modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M,
1 << UART_PARITY_EN_S);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART1 */
+#endif /* HAVE_UART_DEVICE */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable)
+{
+ uint32_t mask;
+ if (enable)
+ {
+ /* Enable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
+
+ /* Configure the threshold */
+
+ mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
+ }
+ else
+ {
+ /* Disable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable)
+{
+ if (enable)
+ {
+ /* Enable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
+ }
+ else
+ {
+ /* Disable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RST_CORE_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
+ 1 << UART_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
+ 1 << UART_RX_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
+ 1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source)
+{
+ uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
+{
+ uint32_t clk_conf_reg;
+ uint32_t ret = -ENODATA;
+ clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
+ clk_conf_reg &= UART_SCLK_SEL_M;
+ clk_conf_reg >>= UART_SCLK_SEL_S;
+ switch (clk_conf_reg)
+ {
+ case 1:
+ ret = esp_clk_apb_freq();
+ break;
+ case 2:
+ ret = RTC_CLK_FREQ;
+ break;
+ case 3:
+ ret = XTAL_CLK_FREQ;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_baud
+ *
+ * Description:
+ * Set the baud rate according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_baud(const struct esp32s3_uart_s * priv)
+{
+ int sclk_div;
+ uint32_t sclk_freq;
+ uint32_t clk_div;
+ uint32_t int_part;
+ uint32_t frag_part;
+
+ /* Get serial clock */
+
+ sclk_freq = esp32s3_lowputc_get_sclk(priv);
+
+ /* Calculate integral part of the frequency divider factor.
+ * For low baud rates, the sclk must be less than half.
+ * For high baud rates, the sclk must be the higher.
+ */
+
+ sclk_div = DIV_UP(sclk_freq, MAX_UART_CLKDIV * priv->baud);
+
+ /* Calculate the clock divisor to achieve the baud rate.
+ * baud = f/clk_div
+ * f = sclk_freq/sclk_div
+ * clk_div = 16*int_part + frag_part
+ * 16*int_part + frag_part = 16*(sclk_freq/sclk_div)/baud
+ */
+
+ clk_div = ((sclk_freq) << 4) / (priv->baud * sclk_div);
+
+ /* Get the integer part of it. */
+
+ int_part = clk_div >> 4;
+
+ /* Get the frag part of it. */
+
+ frag_part = clk_div & 0xf;
+
+ /* Set integer part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part);
+
+ /* Set decimal part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M,
+ (frag_part & UART_CLKDIV_FRAG_V) << UART_CLKDIV_FRAG_S);
+
+ /* Set the the integral part of the frequency divider factor. */
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_DIV_NUM_M,
+ (sclk_div - 1) << UART_SCLK_DIV_NUM_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_normal_mode
+ *
+ * Description:
+ * Set the UART to operate in normal mode, i.e., disable the RS485 mode and
+ * IRDA mode.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s * priv)
+{
+ /* Disable RS485 mode */
+
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0);
+
+ /* Disable IRDA mode */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_parity
+ *
+ * Description:
+ * Set the parity, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_parity(const struct esp32s3_uart_s * priv)
+{
+ if (priv->parity == UART_PARITY_DISABLE)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0);
+ }
+ else
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M,
+ ((priv->parity & 0x1) << UART_PARITY_S));
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M,
+ 1 << UART_PARITY_EN_S);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_data_length
+ *
+ * Description:
+ * Set the data bits length, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+int esp32s3_lowputc_data_length(const struct esp32s3_uart_s * priv)
+{
+ int ret = OK;
+ uint32_t length = (priv->bits - 5);
+
+ /* If it is the allowed range */
+
+ if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_BIT_NUM_M,
+ length << UART_BIT_NUM_S);
Review comment:
```suggestion
modifyreg32(UART_CONF0_REG(priv->id), UART_BIT_NUM_M,
length << UART_BIT_NUM_S);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.h
##########
@@ -0,0 +1,485 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_gpio_sigmap.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+enum uart_sclk
+{
+ APB_CLK = 1, /* 80 MHz */
+ CLK_8, /* 8 MHz */
+ XTAL_CLK
+};
+
+enum uart_parity
+{
+ UART_PARITY_DISABLE,
+ UART_PARITY_ODD,
+ UART_PARITY_EVEN
+};
+
+enum uart_data_length
+{
+ UART_DATA_5_BITS,
+ UART_DATA_6_BITS,
+ UART_DATA_7_BITS,
+ UART_DATA_8_BITS
+};
+
+enum uart_stop_length
+{
+ UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */
+ UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */
Review comment:
```suggestion
UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */
UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART1 */
+#endif /* HAVE_UART_DEVICE */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable)
+{
+ uint32_t mask;
+ if (enable)
+ {
+ /* Enable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
+
+ /* Configure the threshold */
+
+ mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
+ }
+ else
+ {
+ /* Disable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable)
+{
+ if (enable)
+ {
+ /* Enable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
+ }
+ else
+ {
+ /* Disable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RST_CORE_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
+ 1 << UART_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
+ 1 << UART_RX_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
+ 1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source)
+{
+ uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
+{
+ uint32_t clk_conf_reg;
+ uint32_t ret = -ENODATA;
+ clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
+ clk_conf_reg &= UART_SCLK_SEL_M;
+ clk_conf_reg >>= UART_SCLK_SEL_S;
+ switch (clk_conf_reg)
+ {
+ case 1:
+ ret = esp_clk_apb_freq();
+ break;
+ case 2:
+ ret = RTC_CLK_FREQ;
+ break;
+ case 3:
+ ret = XTAL_CLK_FREQ;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_baud
+ *
+ * Description:
+ * Set the baud rate according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_baud(const struct esp32s3_uart_s * priv)
+{
+ int sclk_div;
+ uint32_t sclk_freq;
+ uint32_t clk_div;
+ uint32_t int_part;
+ uint32_t frag_part;
+
+ /* Get serial clock */
+
+ sclk_freq = esp32s3_lowputc_get_sclk(priv);
+
+ /* Calculate integral part of the frequency divider factor.
+ * For low baud rates, the sclk must be less than half.
+ * For high baud rates, the sclk must be the higher.
+ */
+
+ sclk_div = DIV_UP(sclk_freq, MAX_UART_CLKDIV * priv->baud);
+
+ /* Calculate the clock divisor to achieve the baud rate.
+ * baud = f/clk_div
+ * f = sclk_freq/sclk_div
+ * clk_div = 16*int_part + frag_part
+ * 16*int_part + frag_part = 16*(sclk_freq/sclk_div)/baud
+ */
+
+ clk_div = ((sclk_freq) << 4) / (priv->baud * sclk_div);
+
+ /* Get the integer part of it. */
+
+ int_part = clk_div >> 4;
+
+ /* Get the frag part of it. */
+
+ frag_part = clk_div & 0xf;
+
+ /* Set integer part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part);
+
+ /* Set decimal part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M,
+ (frag_part & UART_CLKDIV_FRAG_V) << UART_CLKDIV_FRAG_S);
+
+ /* Set the the integral part of the frequency divider factor. */
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_DIV_NUM_M,
+ (sclk_div - 1) << UART_SCLK_DIV_NUM_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_normal_mode
+ *
+ * Description:
+ * Set the UART to operate in normal mode, i.e., disable the RS485 mode and
+ * IRDA mode.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s * priv)
+{
+ /* Disable RS485 mode */
+
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0);
+
+ /* Disable IRDA mode */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_parity
+ *
+ * Description:
+ * Set the parity, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_parity(const struct esp32s3_uart_s * priv)
+{
+ if (priv->parity == UART_PARITY_DISABLE)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0);
+ }
+ else
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M,
+ ((priv->parity & 0x1) << UART_PARITY_S));
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M,
+ 1 << UART_PARITY_EN_S);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_data_length
+ *
+ * Description:
+ * Set the data bits length, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+int esp32s3_lowputc_data_length(const struct esp32s3_uart_s * priv)
+{
+ int ret = OK;
+ uint32_t length = (priv->bits - 5);
Review comment:
```suggestion
uint32_t length = priv->bits - 5;
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART1 */
+#endif /* HAVE_UART_DEVICE */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable)
+{
+ uint32_t mask;
+ if (enable)
+ {
+ /* Enable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
+
+ /* Configure the threshold */
+
+ mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
+ }
+ else
+ {
+ /* Disable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable)
+{
+ if (enable)
+ {
+ /* Enable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
+ }
+ else
+ {
+ /* Disable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RST_CORE_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
+ 1 << UART_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
+ 1 << UART_RX_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
+ 1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source)
+{
+ uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
+{
+ uint32_t clk_conf_reg;
+ uint32_t ret = -ENODATA;
+ clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
+ clk_conf_reg &= UART_SCLK_SEL_M;
+ clk_conf_reg >>= UART_SCLK_SEL_S;
+ switch (clk_conf_reg)
+ {
+ case 1:
+ ret = esp_clk_apb_freq();
+ break;
+ case 2:
+ ret = RTC_CLK_FREQ;
+ break;
+ case 3:
+ ret = XTAL_CLK_FREQ;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_baud
+ *
+ * Description:
+ * Set the baud rate according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_baud(const struct esp32s3_uart_s * priv)
+{
+ int sclk_div;
+ uint32_t sclk_freq;
+ uint32_t clk_div;
+ uint32_t int_part;
+ uint32_t frag_part;
+
+ /* Get serial clock */
+
+ sclk_freq = esp32s3_lowputc_get_sclk(priv);
+
+ /* Calculate integral part of the frequency divider factor.
+ * For low baud rates, the sclk must be less than half.
+ * For high baud rates, the sclk must be the higher.
+ */
+
+ sclk_div = DIV_UP(sclk_freq, MAX_UART_CLKDIV * priv->baud);
+
+ /* Calculate the clock divisor to achieve the baud rate.
+ * baud = f/clk_div
+ * f = sclk_freq/sclk_div
+ * clk_div = 16*int_part + frag_part
+ * 16*int_part + frag_part = 16*(sclk_freq/sclk_div)/baud
+ */
+
+ clk_div = ((sclk_freq) << 4) / (priv->baud * sclk_div);
+
+ /* Get the integer part of it. */
+
+ int_part = clk_div >> 4;
+
+ /* Get the frag part of it. */
+
+ frag_part = clk_div & 0xf;
+
+ /* Set integer part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part);
+
+ /* Set decimal part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M,
+ (frag_part & UART_CLKDIV_FRAG_V) << UART_CLKDIV_FRAG_S);
+
+ /* Set the the integral part of the frequency divider factor. */
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_DIV_NUM_M,
+ (sclk_div - 1) << UART_SCLK_DIV_NUM_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_normal_mode
+ *
+ * Description:
+ * Set the UART to operate in normal mode, i.e., disable the RS485 mode and
+ * IRDA mode.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s * priv)
+{
+ /* Disable RS485 mode */
+
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0);
+
+ /* Disable IRDA mode */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_parity
+ *
+ * Description:
+ * Set the parity, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_parity(const struct esp32s3_uart_s * priv)
+{
+ if (priv->parity == UART_PARITY_DISABLE)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0);
+ }
+ else
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M,
+ ((priv->parity & 0x1) << UART_PARITY_S));
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M,
+ 1 << UART_PARITY_EN_S);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_data_length
+ *
+ * Description:
+ * Set the data bits length, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+int esp32s3_lowputc_data_length(const struct esp32s3_uart_s * priv)
+{
+ int ret = OK;
+ uint32_t length = (priv->bits - 5);
+
+ /* If it is the allowed range */
+
+ if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_BIT_NUM_M,
+ length << UART_BIT_NUM_S);
+ }
+ else
+ {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_stop_length
+ *
+ * Description:
+ * Set the stop bits length, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_stop_length(const struct esp32s3_uart_s *priv)
+{
+ if (priv->stop_b2 == 0)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M,
+ UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S);
+ }
+ else
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M,
+ UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_tx_idle_time
+ *
+ * Description:
+ * Set the idle time between transfers.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * time - Desired time interval between the transfers.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_tx_idle_time(const struct esp32s3_uart_s *priv,
+ uint32_t time)
+{
+ time = time << UART_TX_IDLE_NUM_S;
+ time = time & UART_TX_IDLE_NUM_M; /* Just in case value overloads */
+ modifyreg32(UART_IDLE_CONF_REG(priv->id), UART_TX_IDLE_NUM_M,
+ time);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_send_byte
+ *
+ * Description:
+ * Send one byte.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * byte - Byte to be sent.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_send_byte(const struct esp32s3_uart_s * priv,
+ char byte)
+{
+ putreg32((uint32_t) byte, UART_FIFO_REG(priv->id));
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_is_tx_fifo_full
+ *
+ * Description:
+ * Verify if TX FIFO is full.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * True if it is full, otherwise false.
+ *
+ ****************************************************************************/
+
+bool esp32s3_lowputc_is_tx_fifo_full(const struct esp32s3_uart_s *priv)
+{
+ uint32_t reg;
+ reg = getreg32(UART_STATUS_REG(priv->id));
+ reg = reg >> UART_TXFIFO_CNT_S;
+ reg = reg & UART_TXFIFO_CNT_V;
+ if (reg < (UART_TX_FIFO_SIZE -1))
+ {
+ return false;
+ }
+ else
+ {
+ return true;
+ }
Review comment:
```suggestion
return !(reg < (UART_TX_FIFO_SIZE - 1));
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if (int_status & tx_mask)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if (int_status & rx_mask)
Review comment:
```suggestion
if ((int_status & rx_mask) != 0)
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
Review comment:
```suggestion
# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
# define UART0_ASSIGNED 1
```
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
##########
@@ -0,0 +1,118 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H_
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H_
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRAM0 is connected with Cache IBUS0 */
+
+#define IRAM0_ADDRESS_LOW 0x40000000
+#define IRAM0_ADDRESS_HIGH 0x44000000
+#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
+#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
+
+/* DRAM0 is connected with Cache DBUS0 */
+
+#define DRAM0_ADDRESS_LOW 0x3c000000
+#define DRAM0_ADDRESS_HIGH 0x40000000
+#define DRAM0_CACHE_ADDRESS_LOW 0x3c000000
+#define DRAM0_CACHE_ADDRESS_HIGH 0x3e000000
+#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
+#define ESP_CACHE_TEMP_ADDR 0x3c800000
+
+#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - \
+ bus_name##_ADDRESS_LOW)
+#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW \
+ && (vaddr) < \
+ bus_name##_ADDRESS_HIGH)
+
+#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
+#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
+#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+
+#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
+
+#define CACHE_IBUS 0
+#define CACHE_IBUS_MMU_START 0
+#define CACHE_IBUS_MMU_END 0x800
+
+#define CACHE_DBUS 1
+#define CACHE_DBUS_MMU_START 0
+#define CACHE_DBUS_MMU_END 0x800
+
+#define CACHE_IROM_MMU_START 0
+#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END 0x400
+
+#define ICACHE_MMU_SIZE 0x800
+#define DCACHE_MMU_SIZE 0x800
+
+#define MMU_BUS_START(i) 0
+#define MMU_BUS_SIZE(i) 0x800
+
+#define MMU_INVALID BIT(14)
+#define MMU_TYPE BIT(15)
+#define MMU_ACCESS_FLASH 0
+#define MMU_ACCESS_SPIRAM BIT(15)
+
+#define CACHE_MAX_SYNC_NUM 0x400000
+#define CACHE_MAX_LOCK_NUM 0x8000
+
+#define FLASH_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE)
+#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE / sizeof(uint32_t))
+
+#define MMU_TABLE_INVALID_VAL 0x4000
+#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
+#define MMU_ADDRESS_MASK 0x3fff
+#define MMU_PAGE_SIZE 0x10000
+#define INVALID_PHY_PAGE 0xffff
+
+#define BUS_ADDR_SIZE 0x200000
+#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
+
+#define CACHE_ICACHE_LOW_SHIFT 0
+#define CACHE_ICACHE_HIGH_SHIFT 2
+#define CACHE_DCACHE_LOW_SHIFT 4
+#define CACHE_DCACHE_HIGH_SHIFT 6
+
+#define CACHE_MEMORY_IBANK0_ADDR 0x40370000
+#define CACHE_MEMORY_IBANK1_ADDR 0x40374000
+
+#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000
+#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H_ */
Review comment:
```suggestion
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H */
```
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
##########
@@ -0,0 +1,5795 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTC_CNTL_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTC_CNTL_H
Review comment:
```suggestion
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if (int_status & tx_mask)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if (int_status & rx_mask)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0) ? true : false;
Review comment:
```suggestion
return (bytes > 0);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if (int_status & tx_mask)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if (int_status & rx_mask)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0) ? true : false;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return (esp32s3_lowputc_is_tx_fifo_full(dev->priv)) ? false : true;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0) ? true : false;
Review comment:
```suggestion
return (reg > 0);
```
##########
File path: arch/xtensa/src/esp32s3/esp32s3_serial.c
##########
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if (int_status & tx_mask)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if (int_status & rx_mask)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -1;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0) ? true : false;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return (esp32s3_lowputc_is_tx_fifo_full(dev->priv)) ? false : true;
Review comment:
```suggestion
return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
```
##########
File path: arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
##########
@@ -0,0 +1,5795 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTC_CNTL_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTC_CNTL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to
+ * write-enable the wdt registers
+ */
+
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1
+
+/* RTC_CNTL_RTC_OPTIONS0_REG register
+ * RTC common configure register
+ */
+
+#define RTC_CNTL_RTC_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
+
+/* RTC_CNTL_SW_SYS_RST : WO; bitpos: [31]; default: 0;
+ * SW system reset
+ */
+
+#define RTC_CNTL_SW_SYS_RST (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_M (RTC_CNTL_SW_SYS_RST_V << RTC_CNTL_SW_SYS_RST_S)
+#define RTC_CNTL_SW_SYS_RST_V 0x00000001
+#define RTC_CNTL_SW_SYS_RST_S 31
+
+/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W; bitpos: [30]; default: 0;
+ * digital core force no reset in deep sleep
+ */
+
+#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (RTC_CNTL_DG_WRAP_FORCE_NORST_V << RTC_CNTL_DG_WRAP_FORCE_NORST_S)
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x00000001
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30
+
+/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W; bitpos: [29]; default: 0;
+ * digital wrap force reset in deep sleep
+ */
+
+#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_M (RTC_CNTL_DG_WRAP_FORCE_RST_V << RTC_CNTL_DG_WRAP_FORCE_RST_S)
+#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x00000001
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29
+
+/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W; bitpos: [28]; default: 1;
+ * No public
+ */
+
+#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_M (RTC_CNTL_ANALOG_FORCE_NOISO_V << RTC_CNTL_ANALOG_FORCE_NOISO_S)
+#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28
+
+/* RTC_CNTL_PLL_FORCE_NOISO : R/W; bitpos: [27]; default: 1;
+ * No public
+ */
+
+#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_M (RTC_CNTL_PLL_FORCE_NOISO_V << RTC_CNTL_PLL_FORCE_NOISO_S)
+#define RTC_CNTL_PLL_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_PLL_FORCE_NOISO_S 27
+
+/* RTC_CNTL_XTL_FORCE_NOISO : R/W; bitpos: [26]; default: 1;
+ * No public
+ */
+
+#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_M (RTC_CNTL_XTL_FORCE_NOISO_V << RTC_CNTL_XTL_FORCE_NOISO_S)
+#define RTC_CNTL_XTL_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_XTL_FORCE_NOISO_S 26
+
+/* RTC_CNTL_ANALOG_FORCE_ISO : R/W; bitpos: [25]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_M (RTC_CNTL_ANALOG_FORCE_ISO_V << RTC_CNTL_ANALOG_FORCE_ISO_S)
+#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_ANALOG_FORCE_ISO_S 25
+
+/* RTC_CNTL_PLL_FORCE_ISO : R/W; bitpos: [24]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_PLL_FORCE_ISO (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_M (RTC_CNTL_PLL_FORCE_ISO_V << RTC_CNTL_PLL_FORCE_ISO_S)
+#define RTC_CNTL_PLL_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_PLL_FORCE_ISO_S 24
+
+/* RTC_CNTL_XTL_FORCE_ISO : R/W; bitpos: [23]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_XTL_FORCE_ISO (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_M (RTC_CNTL_XTL_FORCE_ISO_V << RTC_CNTL_XTL_FORCE_ISO_S)
+#define RTC_CNTL_XTL_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_XTL_FORCE_ISO_S 23
+
+/* RTC_CNTL_XTL_EN_WAIT : R/W; bitpos: [17:14]; default: 2;
+ * wait bias_sleep and current source wakeup
+ */
+
+#define RTC_CNTL_XTL_EN_WAIT 0x0000000f
+#define RTC_CNTL_XTL_EN_WAIT_M (RTC_CNTL_XTL_EN_WAIT_V << RTC_CNTL_XTL_EN_WAIT_S)
+#define RTC_CNTL_XTL_EN_WAIT_V 0x0000000f
+#define RTC_CNTL_XTL_EN_WAIT_S 14
+
+/* RTC_CNTL_XTL_FORCE_PU : R/W; bitpos: [13]; default: 1;
+ * crystall force power up
+ */
+
+#define RTC_CNTL_XTL_FORCE_PU (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_M (RTC_CNTL_XTL_FORCE_PU_V << RTC_CNTL_XTL_FORCE_PU_S)
+#define RTC_CNTL_XTL_FORCE_PU_V 0x00000001
+#define RTC_CNTL_XTL_FORCE_PU_S 13
+
+/* RTC_CNTL_XTL_FORCE_PD : R/W; bitpos: [12]; default: 0;
+ * crystall force power down
+ */
+
+#define RTC_CNTL_XTL_FORCE_PD (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_M (RTC_CNTL_XTL_FORCE_PD_V << RTC_CNTL_XTL_FORCE_PD_S)
+#define RTC_CNTL_XTL_FORCE_PD_V 0x00000001
+#define RTC_CNTL_XTL_FORCE_PD_S 12
+
+/* RTC_CNTL_BBPLL_FORCE_PU : R/W; bitpos: [11]; default: 0;
+ * BB_PLL force power up
+ */
+
+#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_M (RTC_CNTL_BBPLL_FORCE_PU_V << RTC_CNTL_BBPLL_FORCE_PU_S)
+#define RTC_CNTL_BBPLL_FORCE_PU_V 0x00000001
+#define RTC_CNTL_BBPLL_FORCE_PU_S 11
+
+/* RTC_CNTL_BBPLL_FORCE_PD : R/W; bitpos: [10]; default: 0;
+ * BB_PLL force power down
+ */
+
+#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_M (RTC_CNTL_BBPLL_FORCE_PD_V << RTC_CNTL_BBPLL_FORCE_PD_S)
+#define RTC_CNTL_BBPLL_FORCE_PD_V 0x00000001
+#define RTC_CNTL_BBPLL_FORCE_PD_S 10
+
+/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W; bitpos: [9]; default: 0;
+ * BB_PLL_I2C force power up
+ */
+
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (RTC_CNTL_BBPLL_I2C_FORCE_PU_V << RTC_CNTL_BBPLL_I2C_FORCE_PU_S)
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x00000001
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9
+
+/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W; bitpos: [8]; default: 0;
+ * BB_PLL _I2C force power down
+ */
+
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (RTC_CNTL_BBPLL_I2C_FORCE_PD_V << RTC_CNTL_BBPLL_I2C_FORCE_PD_S)
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x00000001
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8
+
+/* RTC_CNTL_BB_I2C_FORCE_PU : R/W; bitpos: [7]; default: 0;
+ * BB_I2C force power up
+ */
+
+#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_M (RTC_CNTL_BB_I2C_FORCE_PU_V << RTC_CNTL_BB_I2C_FORCE_PU_S)
+#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x00000001
+#define RTC_CNTL_BB_I2C_FORCE_PU_S 7
+
+/* RTC_CNTL_BB_I2C_FORCE_PD : R/W; bitpos: [6]; default: 0;
+ * BB_I2C force power down
+ */
+
+#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_M (RTC_CNTL_BB_I2C_FORCE_PD_V << RTC_CNTL_BB_I2C_FORCE_PD_S)
+#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x00000001
+#define RTC_CNTL_BB_I2C_FORCE_PD_S 6
+
+/* RTC_CNTL_SW_PROCPU_RST : WO; bitpos: [5]; default: 0;
+ * PRO CPU SW reset
+ */
+
+#define RTC_CNTL_SW_PROCPU_RST (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_M (RTC_CNTL_SW_PROCPU_RST_V << RTC_CNTL_SW_PROCPU_RST_S)
+#define RTC_CNTL_SW_PROCPU_RST_V 0x00000001
+#define RTC_CNTL_SW_PROCPU_RST_S 5
+
+/* RTC_CNTL_SW_APPCPU_RST : WO; bitpos: [4]; default: 0;
+ * APP CPU SW reset
+ */
+
+#define RTC_CNTL_SW_APPCPU_RST (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_M (RTC_CNTL_SW_APPCPU_RST_V << RTC_CNTL_SW_APPCPU_RST_S)
+#define RTC_CNTL_SW_APPCPU_RST_V 0x00000001
+#define RTC_CNTL_SW_APPCPU_RST_S 4
+
+/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W; bitpos: [3:2]; default: 0;
+ * {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will
+ * stall PRO CPU
+ */
+
+#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_M (RTC_CNTL_SW_STALL_PROCPU_C0_V << RTC_CNTL_SW_STALL_PROCPU_C0_S)
+#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2
+
+/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W; bitpos: [1:0]; default: 0;
+ * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will
+ * stall APP CPU
+ */
+
+#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003
+#define RTC_CNTL_SW_STALL_APPCPU_C0_M (RTC_CNTL_SW_STALL_APPCPU_C0_V << RTC_CNTL_SW_STALL_APPCPU_C0_S)
+#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x00000003
+#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0
+
+/* RTC_CNTL_RTC_SLP_TIMER0_REG register
+ * configure min sleep time
+ */
+
+#define RTC_CNTL_RTC_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4)
+
+/* RTC_CNTL_SLP_VAL_LO : R/W; bitpos: [31:0]; default: 0;
+ * RTC sleep timer low 32 bits
+ */
+
+#define RTC_CNTL_SLP_VAL_LO 0xffffffff
+#define RTC_CNTL_SLP_VAL_LO_M (RTC_CNTL_SLP_VAL_LO_V << RTC_CNTL_SLP_VAL_LO_S)
+#define RTC_CNTL_SLP_VAL_LO_V 0xffffffff
+#define RTC_CNTL_SLP_VAL_LO_S 0
+
+/* RTC_CNTL_RTC_SLP_TIMER1_REG register
+ * configure sleep time hi
+ */
+
+#define RTC_CNTL_RTC_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8)
+
+/* RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN : WO; bitpos: [16]; default: 0;
+ * timer alarm enable bit
+ */
+
+#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN (BIT(16))
+#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_M (RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_V << RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_S)
+#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_S 16
+
+/* RTC_CNTL_SLP_VAL_HI : R/W; bitpos: [15:0]; default: 0;
+ * RTC sleep timer high 16 bits
+ */
+
+#define RTC_CNTL_SLP_VAL_HI 0x0000ffff
+#define RTC_CNTL_SLP_VAL_HI_M (RTC_CNTL_SLP_VAL_HI_V << RTC_CNTL_SLP_VAL_HI_S)
+#define RTC_CNTL_SLP_VAL_HI_V 0x0000ffff
+#define RTC_CNTL_SLP_VAL_HI_S 0
+
+/* RTC_CNTL_RTC_TIME_UPDATE_REG register
+ * update rtc main timer
+ */
+
+#define RTC_CNTL_RTC_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc)
+
+/* RTC_CNTL_RTC_TIME_UPDATE : WO; bitpos: [31]; default: 0;
+ * Set 1: to update register with RTC timer
+ */
+
+#define RTC_CNTL_RTC_TIME_UPDATE (BIT(31))
+#define RTC_CNTL_RTC_TIME_UPDATE_M (RTC_CNTL_RTC_TIME_UPDATE_V << RTC_CNTL_RTC_TIME_UPDATE_S)
+#define RTC_CNTL_RTC_TIME_UPDATE_V 0x00000001
+#define RTC_CNTL_RTC_TIME_UPDATE_S 31
+
+/* RTC_CNTL_TIMER_SYS_RST : R/W; bitpos: [29]; default: 0;
+ * enable to record system reset time
+ */
+
+#define RTC_CNTL_TIMER_SYS_RST (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_M (RTC_CNTL_TIMER_SYS_RST_V << RTC_CNTL_TIMER_SYS_RST_S)
+#define RTC_CNTL_TIMER_SYS_RST_V 0x00000001
+#define RTC_CNTL_TIMER_SYS_RST_S 29
+
+/* RTC_CNTL_TIMER_XTL_OFF : R/W; bitpos: [28]; default: 0;
+ * Enable to record 40M XTAL OFF time
+ */
+
+#define RTC_CNTL_TIMER_XTL_OFF (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_M (RTC_CNTL_TIMER_XTL_OFF_V << RTC_CNTL_TIMER_XTL_OFF_S)
+#define RTC_CNTL_TIMER_XTL_OFF_V 0x00000001
+#define RTC_CNTL_TIMER_XTL_OFF_S 28
+
+/* RTC_CNTL_TIMER_SYS_STALL : R/W; bitpos: [27]; default: 0;
+ * Enable to record system stall time
+ */
+
+#define RTC_CNTL_TIMER_SYS_STALL (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_M (RTC_CNTL_TIMER_SYS_STALL_V << RTC_CNTL_TIMER_SYS_STALL_S)
+#define RTC_CNTL_TIMER_SYS_STALL_V 0x00000001
+#define RTC_CNTL_TIMER_SYS_STALL_S 27
+
+/* RTC_CNTL_RTC_TIME_LOW0_REG register
+ * read rtc_main timer low bits
+ */
+
+#define RTC_CNTL_RTC_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10)
+
+/* RTC_CNTL_RTC_TIMER_VALUE0_LOW : RO; bitpos: [31:0]; default: 0;
+ * RTC timer low 32 bits
+ */
+
+#define RTC_CNTL_RTC_TIMER_VALUE0_LOW 0xffffffff
+#define RTC_CNTL_RTC_TIMER_VALUE0_LOW_M (RTC_CNTL_RTC_TIMER_VALUE0_LOW_V << RTC_CNTL_RTC_TIMER_VALUE0_LOW_S)
+#define RTC_CNTL_RTC_TIMER_VALUE0_LOW_V 0xffffffff
+#define RTC_CNTL_RTC_TIMER_VALUE0_LOW_S 0
+
+/* RTC_CNTL_RTC_TIME_HIGH0_REG register
+ * read rtc_main timer high bits
+ */
+
+#define RTC_CNTL_RTC_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14)
+
+/* RTC_CNTL_RTC_TIMER_VALUE0_HIGH : RO; bitpos: [15:0]; default: 0;
+ * RTC timer high 16 bits
+ */
+
+#define RTC_CNTL_RTC_TIMER_VALUE0_HIGH 0x0000ffff
+#define RTC_CNTL_RTC_TIMER_VALUE0_HIGH_M (RTC_CNTL_RTC_TIMER_VALUE0_HIGH_V << RTC_CNTL_RTC_TIMER_VALUE0_HIGH_S)
+#define RTC_CNTL_RTC_TIMER_VALUE0_HIGH_V 0x0000ffff
+#define RTC_CNTL_RTC_TIMER_VALUE0_HIGH_S 0
+
+/* RTC_CNTL_RTC_STATE0_REG register
+ * configure chip sleep
+ */
+
+#define RTC_CNTL_RTC_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18)
+
+/* RTC_CNTL_SLEEP_EN : R/W; bitpos: [31]; default: 0;
+ * sleep enable bit
+ */
+
+#define RTC_CNTL_SLEEP_EN (BIT(31))
+#define RTC_CNTL_SLEEP_EN_M (RTC_CNTL_SLEEP_EN_V << RTC_CNTL_SLEEP_EN_S)
+#define RTC_CNTL_SLEEP_EN_V 0x00000001
+#define RTC_CNTL_SLEEP_EN_S 31
+
+/* RTC_CNTL_SLP_REJECT : R/W; bitpos: [30]; default: 0;
+ * leep reject bit
+ */
+
+#define RTC_CNTL_SLP_REJECT (BIT(30))
+#define RTC_CNTL_SLP_REJECT_M (RTC_CNTL_SLP_REJECT_V << RTC_CNTL_SLP_REJECT_S)
+#define RTC_CNTL_SLP_REJECT_V 0x00000001
+#define RTC_CNTL_SLP_REJECT_S 30
+
+/* RTC_CNTL_SLP_WAKEUP : R/W; bitpos: [29]; default: 0;
+ * leep wakeup bit
+ */
+
+#define RTC_CNTL_SLP_WAKEUP (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_M (RTC_CNTL_SLP_WAKEUP_V << RTC_CNTL_SLP_WAKEUP_S)
+#define RTC_CNTL_SLP_WAKEUP_V 0x00000001
+#define RTC_CNTL_SLP_WAKEUP_S 29
+
+/* RTC_CNTL_SDIO_ACTIVE_IND : RO; bitpos: [28]; default: 0;
+ * SDIO active indication
+ */
+
+#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_M (RTC_CNTL_SDIO_ACTIVE_IND_V << RTC_CNTL_SDIO_ACTIVE_IND_S)
+#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x00000001
+#define RTC_CNTL_SDIO_ACTIVE_IND_S 28
+
+/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W; bitpos: [22]; default: 0;
+ * 1: APB to RTC using bridge, 0: APB to RTC using sync
+ */
+
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (RTC_CNTL_APB2RTC_BRIDGE_SEL_V << RTC_CNTL_APB2RTC_BRIDGE_SEL_S)
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x00000001
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22
+
+/* RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR : WO; bitpos: [1]; default: 0;
+ * clear rtc sleep reject cause
+ */
+
+#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR (BIT(1))
+#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_M (RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_V << RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_S)
+#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_V 0x00000001
+#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_S 1
+
+/* RTC_CNTL_RTC_SW_CPU_INT : WO; bitpos: [0]; default: 0;
+ * rtc software interrupt to main cpu
+ */
+
+#define RTC_CNTL_RTC_SW_CPU_INT (BIT(0))
+#define RTC_CNTL_RTC_SW_CPU_INT_M (RTC_CNTL_RTC_SW_CPU_INT_V << RTC_CNTL_RTC_SW_CPU_INT_S)
+#define RTC_CNTL_RTC_SW_CPU_INT_V 0x00000001
+#define RTC_CNTL_RTC_SW_CPU_INT_S 0
+
+/* RTC_CNTL_RTC_TIMER1_REG register
+ * rtc state wait time
+ */
+
+#define RTC_CNTL_RTC_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c)
+
+/* RTC_CNTL_PLL_BUF_WAIT : R/W; bitpos: [31:24]; default: 40;
+ * PLL wait cycles in slow_clk_rtc
+ */
+
+#define RTC_CNTL_PLL_BUF_WAIT 0x000000ff
+#define RTC_CNTL_PLL_BUF_WAIT_M (RTC_CNTL_PLL_BUF_WAIT_V << RTC_CNTL_PLL_BUF_WAIT_S)
+#define RTC_CNTL_PLL_BUF_WAIT_V 0x000000ff
+#define RTC_CNTL_PLL_BUF_WAIT_S 24
+
+/* RTC_CNTL_XTL_BUF_WAIT : R/W; bitpos: [23:14]; default: 80;
+ * XTAL wait cycles in slow_clk_rtc
+ */
+
+#define RTC_CNTL_XTL_BUF_WAIT 0x000003ff
+#define RTC_CNTL_XTL_BUF_WAIT_M (RTC_CNTL_XTL_BUF_WAIT_V << RTC_CNTL_XTL_BUF_WAIT_S)
+#define RTC_CNTL_XTL_BUF_WAIT_V 0x000003ff
+#define RTC_CNTL_XTL_BUF_WAIT_S 14
+
+/* RTC_CNTL_CK8M_WAIT : R/W; bitpos: [13:6]; default: 16;
+ * CK8M wait cycles in slow_clk_rtc
+ */
+
+#define RTC_CNTL_CK8M_WAIT 0x000000ff
+#define RTC_CNTL_CK8M_WAIT_M (RTC_CNTL_CK8M_WAIT_V << RTC_CNTL_CK8M_WAIT_S)
+#define RTC_CNTL_CK8M_WAIT_V 0x000000ff
+#define RTC_CNTL_CK8M_WAIT_S 6
+
+/* RTC_CNTL_CPU_STALL_WAIT : R/W; bitpos: [5:1]; default: 1;
+ * CPU stall wait cycles in fast_clk_rtc
+ */
+
+#define RTC_CNTL_CPU_STALL_WAIT 0x0000001f
+#define RTC_CNTL_CPU_STALL_WAIT_M (RTC_CNTL_CPU_STALL_WAIT_V << RTC_CNTL_CPU_STALL_WAIT_S)
+#define RTC_CNTL_CPU_STALL_WAIT_V 0x0000001f
+#define RTC_CNTL_CPU_STALL_WAIT_S 1
+
+/* RTC_CNTL_CPU_STALL_EN : R/W; bitpos: [0]; default: 1;
+ * CPU stall enable bit
+ */
+
+#define RTC_CNTL_CPU_STALL_EN (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_M (RTC_CNTL_CPU_STALL_EN_V << RTC_CNTL_CPU_STALL_EN_S)
+#define RTC_CNTL_CPU_STALL_EN_V 0x00000001
+#define RTC_CNTL_CPU_STALL_EN_S 0
+
+/* RTC_CNTL_RTC_TIMER2_REG register
+ * rtc monitor state delay time
+ */
+
+#define RTC_CNTL_RTC_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20)
+
+/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W; bitpos: [31:24]; default: 1;
+ * minimal cycles in slow_clk_rtc for CK8M in power down state
+ */
+
+#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000ff
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_M (RTC_CNTL_MIN_TIME_CK8M_OFF_V << RTC_CNTL_MIN_TIME_CK8M_OFF_S)
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0x000000ff
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24
+
+/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W; bitpos: [23:15]; default: 16;
+ * wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller
+ * start to work
+ */
+
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001ff
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M (RTC_CNTL_ULPCP_TOUCH_START_WAIT_V << RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x000001ff
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15
+
+/* RTC_CNTL_RTC_TIMER3_REG register
+ * No public
+ */
+
+#define RTC_CNTL_RTC_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24)
+
+/* RTC_CNTL_BT_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 10;
+ * No public
+ */
+
+#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007f
+#define RTC_CNTL_BT_POWERUP_TIMER_M (RTC_CNTL_BT_POWERUP_TIMER_V << RTC_CNTL_BT_POWERUP_TIMER_S)
+#define RTC_CNTL_BT_POWERUP_TIMER_V 0x0000007f
+#define RTC_CNTL_BT_POWERUP_TIMER_S 25
+
+/* RTC_CNTL_BT_WAIT_TIMER : R/W; bitpos: [24:16]; default: 22;
+ * No public
+ */
+
+#define RTC_CNTL_BT_WAIT_TIMER 0x000001ff
+#define RTC_CNTL_BT_WAIT_TIMER_M (RTC_CNTL_BT_WAIT_TIMER_V << RTC_CNTL_BT_WAIT_TIMER_S)
+#define RTC_CNTL_BT_WAIT_TIMER_V 0x000001ff
+#define RTC_CNTL_BT_WAIT_TIMER_S 16
+
+/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5;
+ * No public
+ */
+
+#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007f
+#define RTC_CNTL_WIFI_POWERUP_TIMER_M (RTC_CNTL_WIFI_POWERUP_TIMER_V << RTC_CNTL_WIFI_POWERUP_TIMER_S)
+#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x0000007f
+#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9
+
+/* RTC_CNTL_WIFI_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8;
+ * No public
+ */
+
+#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001ff
+#define RTC_CNTL_WIFI_WAIT_TIMER_M (RTC_CNTL_WIFI_WAIT_TIMER_V << RTC_CNTL_WIFI_WAIT_TIMER_S)
+#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x000001ff
+#define RTC_CNTL_WIFI_WAIT_TIMER_S 0
+
+/* RTC_CNTL_RTC_TIMER4_REG register
+ * No public
+ */
+
+#define RTC_CNTL_RTC_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28)
+
+/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8;
+ * No public
+ */
+
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007f
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M (RTC_CNTL_DG_WRAP_POWERUP_TIMER_V << RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x0000007f
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25
+
+/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32;
+ * No public
+ */
+
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001ff
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M (RTC_CNTL_DG_WRAP_WAIT_TIMER_V << RTC_CNTL_DG_WRAP_WAIT_TIMER_S)
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x000001ff
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16
+
+/* RTC_CNTL_RTC_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5;
+ * No public
+ */
+
+#define RTC_CNTL_RTC_POWERUP_TIMER 0x0000007f
+#define RTC_CNTL_RTC_POWERUP_TIMER_M (RTC_CNTL_RTC_POWERUP_TIMER_V << RTC_CNTL_RTC_POWERUP_TIMER_S)
+#define RTC_CNTL_RTC_POWERUP_TIMER_V 0x0000007f
+#define RTC_CNTL_RTC_POWERUP_TIMER_S 9
+
+/* RTC_CNTL_RTC_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8;
+ * No public
+ */
+
+#define RTC_CNTL_RTC_WAIT_TIMER 0x000001ff
+#define RTC_CNTL_RTC_WAIT_TIMER_M (RTC_CNTL_RTC_WAIT_TIMER_V << RTC_CNTL_RTC_WAIT_TIMER_S)
+#define RTC_CNTL_RTC_WAIT_TIMER_V 0x000001ff
+#define RTC_CNTL_RTC_WAIT_TIMER_S 0
+
+/* RTC_CNTL_RTC_TIMER5_REG register
+ * configure min sleep time
+ */
+
+#define RTC_CNTL_RTC_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c)
+
+/* RTC_CNTL_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 128;
+ * minimal sleep cycles in slow_clk_rtc
+ */
+
+#define RTC_CNTL_MIN_SLP_VAL 0x000000ff
+#define RTC_CNTL_MIN_SLP_VAL_M (RTC_CNTL_MIN_SLP_VAL_V << RTC_CNTL_MIN_SLP_VAL_S)
+#define RTC_CNTL_MIN_SLP_VAL_V 0x000000ff
+#define RTC_CNTL_MIN_SLP_VAL_S 8
+
+/* RTC_CNTL_RTC_TIMER6_REG register
+ * No public
+ */
+
+#define RTC_CNTL_RTC_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30)
+
+/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8;
+ * No public
+ */
+
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007f
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M (RTC_CNTL_DG_PERI_POWERUP_TIMER_V << RTC_CNTL_DG_PERI_POWERUP_TIMER_S)
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x0000007f
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25
+
+/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32;
+ * No public
+ */
+
+#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001ff
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_M (RTC_CNTL_DG_PERI_WAIT_TIMER_V << RTC_CNTL_DG_PERI_WAIT_TIMER_S)
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x000001ff
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16
+
+/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5;
+ * No public
+ */
+
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007f
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M (RTC_CNTL_CPU_TOP_POWERUP_TIMER_V << RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x0000007f
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9
+
+/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8;
+ * No public
+ */
+
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001ff
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M (RTC_CNTL_CPU_TOP_WAIT_TIMER_V << RTC_CNTL_CPU_TOP_WAIT_TIMER_S)
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x000001ff
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0
+
+/* RTC_CNTL_RTC_ANA_CONF_REG register
+ * analog configure register
+ */
+
+#define RTC_CNTL_RTC_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34)
+
+/* RTC_CNTL_PLL_I2C_PU : R/W; bitpos: [31]; default: 0;
+ * power on pll i2c
+ */
+
+#define RTC_CNTL_PLL_I2C_PU (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_M (RTC_CNTL_PLL_I2C_PU_V << RTC_CNTL_PLL_I2C_PU_S)
+#define RTC_CNTL_PLL_I2C_PU_V 0x00000001
+#define RTC_CNTL_PLL_I2C_PU_S 31
+
+/* RTC_CNTL_CKGEN_I2C_PU : R/W; bitpos: [30]; default: 0;
+ * 1: CKGEN_I2C power up, otherwise power down
+ */
+
+#define RTC_CNTL_CKGEN_I2C_PU (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_M (RTC_CNTL_CKGEN_I2C_PU_V << RTC_CNTL_CKGEN_I2C_PU_S)
+#define RTC_CNTL_CKGEN_I2C_PU_V 0x00000001
+#define RTC_CNTL_CKGEN_I2C_PU_S 30
+
+/* RTC_CNTL_RFRX_PBUS_PU : R/W; bitpos: [28]; default: 0;
+ * 1: RFRX_PBUS power up, otherwise power down
+ */
+
+#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_M (RTC_CNTL_RFRX_PBUS_PU_V << RTC_CNTL_RFRX_PBUS_PU_S)
+#define RTC_CNTL_RFRX_PBUS_PU_V 0x00000001
+#define RTC_CNTL_RFRX_PBUS_PU_S 28
+
+/* RTC_CNTL_TXRF_I2C_PU : R/W; bitpos: [27]; default: 0;
+ * 1: TXRF_I2C power up, otherwise power down
+ */
+
+#define RTC_CNTL_TXRF_I2C_PU (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_M (RTC_CNTL_TXRF_I2C_PU_V << RTC_CNTL_TXRF_I2C_PU_S)
+#define RTC_CNTL_TXRF_I2C_PU_V 0x00000001
+#define RTC_CNTL_TXRF_I2C_PU_S 27
+
+/* RTC_CNTL_PVTMON_PU : R/W; bitpos: [26]; default: 0;
+ * 1: PVTMON power up, otherwise power down
+ */
+
+#define RTC_CNTL_PVTMON_PU (BIT(26))
+#define RTC_CNTL_PVTMON_PU_M (RTC_CNTL_PVTMON_PU_V << RTC_CNTL_PVTMON_PU_S)
+#define RTC_CNTL_PVTMON_PU_V 0x00000001
+#define RTC_CNTL_PVTMON_PU_S 26
+
+/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W; bitpos: [25]; default: 0;
+ * start BBPLL calibration during sleep
+ */
+
+#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_M (RTC_CNTL_BBPLL_CAL_SLP_START_V << RTC_CNTL_BBPLL_CAL_SLP_START_S)
+#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x00000001
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25
+
+/* RTC_CNTL_ANALOG_TOP_ISO_MONITOR : R/W; bitpos: [24]; default: 0;
+ * PLLA force power up
+ */
+
+#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR (BIT(24))
+#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_M (RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V << RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S)
+#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V 0x00000001
+#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S 24
+
+/* RTC_CNTL_ANALOG_TOP_ISO_SLEEP : R/W; bitpos: [23]; default: 0;
+ * PLLA force power down
+ */
+
+#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP (BIT(23))
+#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_M (RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V << RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S)
+#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V 0x00000001
+#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S 23
+
+/* RTC_CNTL_SAR_I2C_PU : R/W; bitpos: [22]; default: 1;
+ * PLLA force power up
+ */
+
+#define RTC_CNTL_SAR_I2C_PU (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_M (RTC_CNTL_SAR_I2C_PU_V << RTC_CNTL_SAR_I2C_PU_S)
+#define RTC_CNTL_SAR_I2C_PU_V 0x00000001
+#define RTC_CNTL_SAR_I2C_PU_S 22
+
+/* RTC_CNTL_GLITCH_RST_EN : R/W; bitpos: [20]; default: 0;
+ * enable clk glitch
+ */
+
+#define RTC_CNTL_GLITCH_RST_EN (BIT(20))
+#define RTC_CNTL_GLITCH_RST_EN_M (RTC_CNTL_GLITCH_RST_EN_V << RTC_CNTL_GLITCH_RST_EN_S)
+#define RTC_CNTL_GLITCH_RST_EN_V 0x00000001
+#define RTC_CNTL_GLITCH_RST_EN_S 20
+
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W; bitpos: [19]; default: 0;
+ * force on I2C_RESET_POR
+ */
+
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (RTC_CNTL_I2C_RESET_POR_FORCE_PU_V << RTC_CNTL_I2C_RESET_POR_FORCE_PU_S)
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x00000001
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19
+
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W; bitpos: [18]; default: 1;
+ * force down I2C_RESET_POR
+ */
+
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (RTC_CNTL_I2C_RESET_POR_FORCE_PD_V << RTC_CNTL_I2C_RESET_POR_FORCE_PD_S)
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x00000001
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18
+
+/* RTC_CNTL_RTC_RESET_STATE_REG register
+ * get reset state
+ */
+
+#define RTC_CNTL_RTC_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38)
+
+/* RTC_CNTL_RTC_PRO_DRESET_MASK : R/W; bitpos: [25]; default: 0;
+ * bypass cpu0 dreset
+ */
+
+#define RTC_CNTL_RTC_PRO_DRESET_MASK (BIT(25))
+#define RTC_CNTL_RTC_PRO_DRESET_MASK_M (RTC_CNTL_RTC_PRO_DRESET_MASK_V << RTC_CNTL_RTC_PRO_DRESET_MASK_S)
+#define RTC_CNTL_RTC_PRO_DRESET_MASK_V 0x00000001
+#define RTC_CNTL_RTC_PRO_DRESET_MASK_S 25
+
+/* RTC_CNTL_RTC_APP_DRESET_MASK : R/W; bitpos: [24]; default: 0;
+ * bypass cpu1 dreset
+ */
+
+#define RTC_CNTL_RTC_APP_DRESET_MASK (BIT(24))
+#define RTC_CNTL_RTC_APP_DRESET_MASK_M (RTC_CNTL_RTC_APP_DRESET_MASK_V << RTC_CNTL_RTC_APP_DRESET_MASK_S)
+#define RTC_CNTL_RTC_APP_DRESET_MASK_V 0x00000001
+#define RTC_CNTL_RTC_APP_DRESET_MASK_S 24
+
+/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO; bitpos: [23]; default: 0;
+ * clear jtag reset flag
+ */
+
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23))
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V << RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S)
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x00000001
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23
+
+/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO; bitpos: [22]; default: 0;
+ * clear jtag reset flag
+ */
+
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22))
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V << RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S)
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x00000001
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22
+
+/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO; bitpos: [21]; default: 0;
+ * jtag reset flag
+ */
+
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21))
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V << RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S)
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x00000001
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21
+
+/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO; bitpos: [20]; default: 0;
+ * jtag reset flag
+ */
+
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20))
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V << RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S)
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x00000001
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20
+
+/* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W; bitpos: [19]; default: 0;
+ * PROCPU OcdHaltOnReset
+ */
+
+#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19))
+#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V << RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S)
+#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x00000001
+#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19
+
+/* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W; bitpos: [18]; default: 0;
+ * APPCPU OcdHaltOnReset
+ */
+
+#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18))
+#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V << RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S)
+#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x00000001
+#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18
+
+/* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO; bitpos: [17]; default: 0;
+ * clear APP CPU reset flag
+ */
+
+#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17))
+#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (RTC_CNTL_RESET_FLAG_APPCPU_CLR_V << RTC_CNTL_RESET_FLAG_APPCPU_CLR_S)
+#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x00000001
+#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17
+
+/* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO; bitpos: [16]; default: 0;
+ * clear PRO CPU reset_flag
+ */
+
+#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16))
+#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (RTC_CNTL_RESET_FLAG_PROCPU_CLR_V << RTC_CNTL_RESET_FLAG_PROCPU_CLR_S)
+#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x00000001
+#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16
+
+/* RTC_CNTL_RESET_FLAG_APPCPU : RO; bitpos: [15]; default: 0;
+ * APP CPU reset flag
+ */
+
+#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15))
+#define RTC_CNTL_RESET_FLAG_APPCPU_M (RTC_CNTL_RESET_FLAG_APPCPU_V << RTC_CNTL_RESET_FLAG_APPCPU_S)
+#define RTC_CNTL_RESET_FLAG_APPCPU_V 0x00000001
+#define RTC_CNTL_RESET_FLAG_APPCPU_S 15
+
+/* RTC_CNTL_RESET_FLAG_PROCPU : RO; bitpos: [14]; default: 0;
+ * PRO CPU reset_flag
+ */
+
+#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14))
+#define RTC_CNTL_RESET_FLAG_PROCPU_M (RTC_CNTL_RESET_FLAG_PROCPU_V << RTC_CNTL_RESET_FLAG_PROCPU_S)
+#define RTC_CNTL_RESET_FLAG_PROCPU_V 0x00000001
+#define RTC_CNTL_RESET_FLAG_PROCPU_S 14
+
+/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W; bitpos: [13]; default: 1;
+ * PRO CPU state vector sel
+ */
+
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13))
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V << RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S)
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x00000001
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13
+
+/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W; bitpos: [12]; default: 1;
+ * APP CPU state vector sel
+ */
+
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12))
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V << RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S)
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x00000001
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12
+
+/* RTC_CNTL_RESET_CAUSE_APPCPU : RO; bitpos: [11:6]; default: 0;
+ * reset cause of APP CPU
+ */
+
+#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003f
+#define RTC_CNTL_RESET_CAUSE_APPCPU_M (RTC_CNTL_RESET_CAUSE_APPCPU_V << RTC_CNTL_RESET_CAUSE_APPCPU_S)
+#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x0000003f
+#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6
+
+/* RTC_CNTL_RESET_CAUSE_PROCPU : RO; bitpos: [5:0]; default: 0;
+ * reset cause of PRO CPU
+ */
+
+#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003f
+#define RTC_CNTL_RESET_CAUSE_PROCPU_M (RTC_CNTL_RESET_CAUSE_PROCPU_V << RTC_CNTL_RESET_CAUSE_PROCPU_S)
+#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x0000003f
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0
+
+/* RTC_CNTL_RTC_WAKEUP_STATE_REG register
+ * configure wakeup state
+ */
+
+#define RTC_CNTL_RTC_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3c)
+
+/* RTC_CNTL_RTC_WAKEUP_ENA : R/W; bitpos: [31:15]; default: 12;
+ * wakeup enable bitmap
+ */
+
+#define RTC_CNTL_RTC_WAKEUP_ENA 0x0001ffff
+#define RTC_CNTL_RTC_WAKEUP_ENA_M (RTC_CNTL_RTC_WAKEUP_ENA_V << RTC_CNTL_RTC_WAKEUP_ENA_S)
+#define RTC_CNTL_RTC_WAKEUP_ENA_V 0x0001ffff
+#define RTC_CNTL_RTC_WAKEUP_ENA_S 15
+
+/* RTC_CNTL_INT_ENA_RTC_REG register
+ * configure rtc interrupt register
+ */
+
+#define RTC_CNTL_INT_ENA_RTC_REG (DR_REG_RTCCNTL_BASE + 0x40)
+
+/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W; bitpos: [20];
+ * default: 0;
+ * touch approach mode loop interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20))
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S)
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20
+
+/* RTC_CNTL_RTC_GLITCH_DET_INT_ENA : R/W; bitpos: [19]; default: 0;
+ * enbale gitch det interrupt
+ */
+
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA (BIT(19))
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_M (RTC_CNTL_RTC_GLITCH_DET_INT_ENA_V << RTC_CNTL_RTC_GLITCH_DET_INT_ENA_S)
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_S 19
+
+/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [18]; default: 0;
+ * enable touch timeout interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA (BIT(18))
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_S)
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_S 18
+
+/* RTC_CNTL_RTC_COCPU_TRAP_INT_ENA : R/W; bitpos: [17]; default: 0;
+ * enable cocpu trap interrupt
+ */
+
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA (BIT(17))
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_M (RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_V << RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_S)
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_S 17
+
+/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA : R/W; bitpos: [16]; default: 0;
+ * enable xtal32k_dead interrupt
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA (BIT(16))
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_S)
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_S 16
+
+/* RTC_CNTL_RTC_SWD_INT_ENA : R/W; bitpos: [15]; default: 0;
+ * enable super watch dog interrupt
+ */
+
+#define RTC_CNTL_RTC_SWD_INT_ENA (BIT(15))
+#define RTC_CNTL_RTC_SWD_INT_ENA_M (RTC_CNTL_RTC_SWD_INT_ENA_V << RTC_CNTL_RTC_SWD_INT_ENA_S)
+#define RTC_CNTL_RTC_SWD_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_SWD_INT_ENA_S 15
+
+/* RTC_CNTL_RTC_SARADC2_INT_ENA : R/W; bitpos: [14]; default: 0;
+ * enable saradc2 interrupt
+ */
+
+#define RTC_CNTL_RTC_SARADC2_INT_ENA (BIT(14))
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_M (RTC_CNTL_RTC_SARADC2_INT_ENA_V << RTC_CNTL_RTC_SARADC2_INT_ENA_S)
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_S 14
+
+/* RTC_CNTL_RTC_COCPU_INT_ENA : R/W; bitpos: [13]; default: 0;
+ * enable riscV cocpu interrupt
+ */
+
+#define RTC_CNTL_RTC_COCPU_INT_ENA (BIT(13))
+#define RTC_CNTL_RTC_COCPU_INT_ENA_M (RTC_CNTL_RTC_COCPU_INT_ENA_V << RTC_CNTL_RTC_COCPU_INT_ENA_S)
+#define RTC_CNTL_RTC_COCPU_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_INT_ENA_S 13
+
+/* RTC_CNTL_RTC_TSENS_INT_ENA : R/W; bitpos: [12]; default: 0;
+ * enable tsens interrupt
+ */
+
+#define RTC_CNTL_RTC_TSENS_INT_ENA (BIT(12))
+#define RTC_CNTL_RTC_TSENS_INT_ENA_M (RTC_CNTL_RTC_TSENS_INT_ENA_V << RTC_CNTL_RTC_TSENS_INT_ENA_S)
+#define RTC_CNTL_RTC_TSENS_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_TSENS_INT_ENA_S 12
+
+/* RTC_CNTL_RTC_SARADC1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ * enable saradc1 interrupt
+ */
+
+#define RTC_CNTL_RTC_SARADC1_INT_ENA (BIT(11))
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_M (RTC_CNTL_RTC_SARADC1_INT_ENA_V << RTC_CNTL_RTC_SARADC1_INT_ENA_S)
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_S 11
+
+/* RTC_CNTL_RTC_MAIN_TIMER_INT_ENA : R/W; bitpos: [10]; default: 0;
+ * enable RTC main timer interrupt
+ */
+
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA (BIT(10))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_M (RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_V << RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_S)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_S 10
+
+/* RTC_CNTL_RTC_BROWN_OUT_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * enable brown out interrupt
+ */
+
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA (BIT(9))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_M (RTC_CNTL_RTC_BROWN_OUT_INT_ENA_V << RTC_CNTL_RTC_BROWN_OUT_INT_ENA_S)
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_S 9
+
+/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [8]; default: 0;
+ * enable touch inactive interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA (BIT(8))
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_S)
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_S 8
+
+/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * enable touch active interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA (BIT(7))
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_S)
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_S 7
+
+/* RTC_CNTL_RTC_TOUCH_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * enable touch done interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_S)
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_S 6
+
+/* RTC_CNTL_RTC_ULP_CP_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * enable ULP-coprocessor interrupt
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA (BIT(5))
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_M (RTC_CNTL_RTC_ULP_CP_INT_ENA_V << RTC_CNTL_RTC_ULP_CP_INT_ENA_S)
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_S 5
+
+/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * enable touch scan done interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA (BIT(4))
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_S)
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_S 4
+
+/* RTC_CNTL_RTC_WDT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * enable RTC WDT interrupt
+ */
+
+#define RTC_CNTL_RTC_WDT_INT_ENA (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_ENA_M (RTC_CNTL_RTC_WDT_INT_ENA_V << RTC_CNTL_RTC_WDT_INT_ENA_S)
+#define RTC_CNTL_RTC_WDT_INT_ENA_V 0x00000001
+#define RTC_CNTL_RTC_WDT_INT_ENA_S 3
+
+/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * enable SDIO idle interrupt
+ */
+
+#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (RTC_CNTL_SDIO_IDLE_INT_ENA_V << RTC_CNTL_SDIO_IDLE_INT_ENA_S)
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x00000001
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2
+
+/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * enable sleep reject interrupt
+ */
+
+#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_M (RTC_CNTL_SLP_REJECT_INT_ENA_V << RTC_CNTL_SLP_REJECT_INT_ENA_S)
+#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x00000001
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1
+
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * enable sleep wakeup interrupt
+ */
+
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_S)
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x00000001
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0
+
+/* RTC_CNTL_INT_RAW_RTC_REG register
+ * rtc interrupt register
+ */
+
+#define RTC_CNTL_INT_RAW_RTC_REG (DR_REG_RTCCNTL_BASE + 0x44)
+
+/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W; bitpos: [20];
+ * default: 0;
+ * touch approach mode loop interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20))
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S)
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20
+
+/* RTC_CNTL_RTC_GLITCH_DET_INT_RAW : RO; bitpos: [19]; default: 0;
+ * glitch_det_interrupt_raw
+ */
+
+#define RTC_CNTL_RTC_GLITCH_DET_INT_RAW (BIT(19))
+#define RTC_CNTL_RTC_GLITCH_DET_INT_RAW_M (RTC_CNTL_RTC_GLITCH_DET_INT_RAW_V << RTC_CNTL_RTC_GLITCH_DET_INT_RAW_S)
+#define RTC_CNTL_RTC_GLITCH_DET_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_GLITCH_DET_INT_RAW_S 19
+
+/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW : RO; bitpos: [18]; default: 0;
+ * touch timeout interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW (BIT(18))
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_S)
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_S 18
+
+/* RTC_CNTL_RTC_COCPU_TRAP_INT_RAW : RO; bitpos: [17]; default: 0;
+ * cocpu trap interrupt raw
+ */
+
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_RAW (BIT(17))
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_M (RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_V << RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_S)
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_S 17
+
+/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW : RO; bitpos: [16]; default: 0;
+ * xtal32k dead detection interrupt raw
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW (BIT(16))
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_S)
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_S 16
+
+/* RTC_CNTL_RTC_SWD_INT_RAW : RO; bitpos: [15]; default: 0;
+ * super watch dog interrupt raw
+ */
+
+#define RTC_CNTL_RTC_SWD_INT_RAW (BIT(15))
+#define RTC_CNTL_RTC_SWD_INT_RAW_M (RTC_CNTL_RTC_SWD_INT_RAW_V << RTC_CNTL_RTC_SWD_INT_RAW_S)
+#define RTC_CNTL_RTC_SWD_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_SWD_INT_RAW_S 15
+
+/* RTC_CNTL_RTC_SARADC2_INT_RAW : RO; bitpos: [14]; default: 0;
+ * saradc2 interrupt raw
+ */
+
+#define RTC_CNTL_RTC_SARADC2_INT_RAW (BIT(14))
+#define RTC_CNTL_RTC_SARADC2_INT_RAW_M (RTC_CNTL_RTC_SARADC2_INT_RAW_V << RTC_CNTL_RTC_SARADC2_INT_RAW_S)
+#define RTC_CNTL_RTC_SARADC2_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_SARADC2_INT_RAW_S 14
+
+/* RTC_CNTL_RTC_COCPU_INT_RAW : RO; bitpos: [13]; default: 0;
+ * riscV cocpu interrupt raw
+ */
+
+#define RTC_CNTL_RTC_COCPU_INT_RAW (BIT(13))
+#define RTC_CNTL_RTC_COCPU_INT_RAW_M (RTC_CNTL_RTC_COCPU_INT_RAW_V << RTC_CNTL_RTC_COCPU_INT_RAW_S)
+#define RTC_CNTL_RTC_COCPU_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_INT_RAW_S 13
+
+/* RTC_CNTL_RTC_TSENS_INT_RAW : RO; bitpos: [12]; default: 0;
+ * tsens interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TSENS_INT_RAW (BIT(12))
+#define RTC_CNTL_RTC_TSENS_INT_RAW_M (RTC_CNTL_RTC_TSENS_INT_RAW_V << RTC_CNTL_RTC_TSENS_INT_RAW_S)
+#define RTC_CNTL_RTC_TSENS_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_TSENS_INT_RAW_S 12
+
+/* RTC_CNTL_RTC_SARADC1_INT_RAW : RO; bitpos: [11]; default: 0;
+ * saradc1 interrupt raw
+ */
+
+#define RTC_CNTL_RTC_SARADC1_INT_RAW (BIT(11))
+#define RTC_CNTL_RTC_SARADC1_INT_RAW_M (RTC_CNTL_RTC_SARADC1_INT_RAW_V << RTC_CNTL_RTC_SARADC1_INT_RAW_S)
+#define RTC_CNTL_RTC_SARADC1_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_SARADC1_INT_RAW_S 11
+
+/* RTC_CNTL_RTC_MAIN_TIMER_INT_RAW : RO; bitpos: [10]; default: 0;
+ * RTC main timer interrupt raw
+ */
+
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW (BIT(10))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_M (RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_V << RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_S)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_S 10
+
+/* RTC_CNTL_RTC_BROWN_OUT_INT_RAW : RO; bitpos: [9]; default: 0;
+ * brown out interrupt raw
+ */
+
+#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW (BIT(9))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_M (RTC_CNTL_RTC_BROWN_OUT_INT_RAW_V << RTC_CNTL_RTC_BROWN_OUT_INT_RAW_S)
+#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_S 9
+
+/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW : RO; bitpos: [8]; default: 0;
+ * touch inactive interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW (BIT(8))
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_S)
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_S 8
+
+/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW : RO; bitpos: [7]; default: 0;
+ * touch active interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW (BIT(7))
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_S)
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_S 7
+
+/* RTC_CNTL_RTC_TOUCH_DONE_INT_RAW : RO; bitpos: [6]; default: 0;
+ * touch interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_RAW (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_S)
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_S 6
+
+/* RTC_CNTL_RTC_ULP_CP_INT_RAW : RO; bitpos: [5]; default: 0;
+ * ULP-coprocessor interrupt raw
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_INT_RAW (BIT(5))
+#define RTC_CNTL_RTC_ULP_CP_INT_RAW_M (RTC_CNTL_RTC_ULP_CP_INT_RAW_V << RTC_CNTL_RTC_ULP_CP_INT_RAW_S)
+#define RTC_CNTL_RTC_ULP_CP_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_ULP_CP_INT_RAW_S 5
+
+/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW : RO; bitpos: [4]; default: 0;
+ * enable touch scan done interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW (BIT(4))
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_S)
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_S 4
+
+/* RTC_CNTL_RTC_WDT_INT_RAW : RO; bitpos: [3]; default: 0;
+ * RTC WDT interrupt raw
+ */
+
+#define RTC_CNTL_RTC_WDT_INT_RAW (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_RAW_M (RTC_CNTL_RTC_WDT_INT_RAW_V << RTC_CNTL_RTC_WDT_INT_RAW_S)
+#define RTC_CNTL_RTC_WDT_INT_RAW_V 0x00000001
+#define RTC_CNTL_RTC_WDT_INT_RAW_S 3
+
+/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO; bitpos: [2]; default: 0;
+ * SDIO idle interrupt raw
+ */
+
+#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (RTC_CNTL_SDIO_IDLE_INT_RAW_V << RTC_CNTL_SDIO_IDLE_INT_RAW_S)
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x00000001
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2
+
+/* RTC_CNTL_SLP_REJECT_INT_RAW : RO; bitpos: [1]; default: 0;
+ * sleep reject interrupt raw
+ */
+
+#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_M (RTC_CNTL_SLP_REJECT_INT_RAW_V << RTC_CNTL_SLP_REJECT_INT_RAW_S)
+#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x00000001
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1
+
+/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO; bitpos: [0]; default: 0;
+ * sleep wakeup interrupt raw
+ */
+
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (RTC_CNTL_SLP_WAKEUP_INT_RAW_V << RTC_CNTL_SLP_WAKEUP_INT_RAW_S)
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x00000001
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0
+
+/* RTC_CNTL_INT_ST_RTC_REG register
+ * rtc interrupt register
+ */
+
+#define RTC_CNTL_INT_ST_RTC_REG (DR_REG_RTCCNTL_BASE + 0x48)
+
+/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO; bitpos: [20]; default:
+ * 0;
+ * touch approach mode loop interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20))
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S)
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20
+
+/* RTC_CNTL_RTC_GLITCH_DET_INT_ST : RO; bitpos: [19]; default: 0;
+ * glitch_det_interrupt state
+ */
+
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ST (BIT(19))
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ST_M (RTC_CNTL_RTC_GLITCH_DET_INT_ST_V << RTC_CNTL_RTC_GLITCH_DET_INT_ST_S)
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ST_S 19
+
+/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [18]; default: 0;
+ * Touch timeout interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST (BIT(18))
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_S)
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_S 18
+
+/* RTC_CNTL_RTC_COCPU_TRAP_INT_ST : RO; bitpos: [17]; default: 0;
+ * cocpu trap interrupt state
+ */
+
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ST (BIT(17))
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ST_M (RTC_CNTL_RTC_COCPU_TRAP_INT_ST_V << RTC_CNTL_RTC_COCPU_TRAP_INT_ST_S)
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ST_S 17
+
+/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST : RO; bitpos: [16]; default: 0;
+ * xtal32k dead detection interrupt state
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST (BIT(16))
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_S)
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_S 16
+
+/* RTC_CNTL_RTC_SWD_INT_ST : RO; bitpos: [15]; default: 0;
+ * super watch dog interrupt state
+ */
+
+#define RTC_CNTL_RTC_SWD_INT_ST (BIT(15))
+#define RTC_CNTL_RTC_SWD_INT_ST_M (RTC_CNTL_RTC_SWD_INT_ST_V << RTC_CNTL_RTC_SWD_INT_ST_S)
+#define RTC_CNTL_RTC_SWD_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_SWD_INT_ST_S 15
+
+/* RTC_CNTL_RTC_SARADC2_INT_ST : RO; bitpos: [14]; default: 0;
+ * saradc2 interrupt state
+ */
+
+#define RTC_CNTL_RTC_SARADC2_INT_ST (BIT(14))
+#define RTC_CNTL_RTC_SARADC2_INT_ST_M (RTC_CNTL_RTC_SARADC2_INT_ST_V << RTC_CNTL_RTC_SARADC2_INT_ST_S)
+#define RTC_CNTL_RTC_SARADC2_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_SARADC2_INT_ST_S 14
+
+/* RTC_CNTL_RTC_COCPU_INT_ST : RO; bitpos: [13]; default: 0;
+ * riscV cocpu interrupt state
+ */
+
+#define RTC_CNTL_RTC_COCPU_INT_ST (BIT(13))
+#define RTC_CNTL_RTC_COCPU_INT_ST_M (RTC_CNTL_RTC_COCPU_INT_ST_V << RTC_CNTL_RTC_COCPU_INT_ST_S)
+#define RTC_CNTL_RTC_COCPU_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_INT_ST_S 13
+
+/* RTC_CNTL_RTC_TSENS_INT_ST : RO; bitpos: [12]; default: 0;
+ * tsens interrupt state
+ */
+
+#define RTC_CNTL_RTC_TSENS_INT_ST (BIT(12))
+#define RTC_CNTL_RTC_TSENS_INT_ST_M (RTC_CNTL_RTC_TSENS_INT_ST_V << RTC_CNTL_RTC_TSENS_INT_ST_S)
+#define RTC_CNTL_RTC_TSENS_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_TSENS_INT_ST_S 12
+
+/* RTC_CNTL_RTC_SARADC1_INT_ST : RO; bitpos: [11]; default: 0;
+ * saradc1 interrupt state
+ */
+
+#define RTC_CNTL_RTC_SARADC1_INT_ST (BIT(11))
+#define RTC_CNTL_RTC_SARADC1_INT_ST_M (RTC_CNTL_RTC_SARADC1_INT_ST_V << RTC_CNTL_RTC_SARADC1_INT_ST_S)
+#define RTC_CNTL_RTC_SARADC1_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_SARADC1_INT_ST_S 11
+
+/* RTC_CNTL_RTC_MAIN_TIMER_INT_ST : RO; bitpos: [10]; default: 0;
+ * RTC main timer interrupt state
+ */
+
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST (BIT(10))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_M (RTC_CNTL_RTC_MAIN_TIMER_INT_ST_V << RTC_CNTL_RTC_MAIN_TIMER_INT_ST_S)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_S 10
+
+/* RTC_CNTL_RTC_BROWN_OUT_INT_ST : RO; bitpos: [9]; default: 0;
+ * brown out interrupt state
+ */
+
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ST (BIT(9))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_M (RTC_CNTL_RTC_BROWN_OUT_INT_ST_V << RTC_CNTL_RTC_BROWN_OUT_INT_ST_S)
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_S 9
+
+/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST : RO; bitpos: [8]; default: 0;
+ * touch inactive interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST (BIT(8))
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_S)
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_S 8
+
+/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST : RO; bitpos: [7]; default: 0;
+ * touch active interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST (BIT(7))
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_S)
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_S 7
+
+/* RTC_CNTL_RTC_TOUCH_DONE_INT_ST : RO; bitpos: [6]; default: 0;
+ * touch done interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ST (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ST_M (RTC_CNTL_RTC_TOUCH_DONE_INT_ST_V << RTC_CNTL_RTC_TOUCH_DONE_INT_ST_S)
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ST_S 6
+
+/* RTC_CNTL_RTC_ULP_CP_INT_ST : RO; bitpos: [5]; default: 0;
+ * ULP-coprocessor interrupt state
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_INT_ST (BIT(5))
+#define RTC_CNTL_RTC_ULP_CP_INT_ST_M (RTC_CNTL_RTC_ULP_CP_INT_ST_V << RTC_CNTL_RTC_ULP_CP_INT_ST_S)
+#define RTC_CNTL_RTC_ULP_CP_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_ULP_CP_INT_ST_S 5
+
+/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ * enable touch scan done interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST (BIT(4))
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_S)
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_S 4
+
+/* RTC_CNTL_RTC_WDT_INT_ST : RO; bitpos: [3]; default: 0;
+ * RTC WDT interrupt state
+ */
+
+#define RTC_CNTL_RTC_WDT_INT_ST (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_ST_M (RTC_CNTL_RTC_WDT_INT_ST_V << RTC_CNTL_RTC_WDT_INT_ST_S)
+#define RTC_CNTL_RTC_WDT_INT_ST_V 0x00000001
+#define RTC_CNTL_RTC_WDT_INT_ST_S 3
+
+/* RTC_CNTL_SDIO_IDLE_INT_ST : RO; bitpos: [2]; default: 0;
+ * SDIO idle interrupt state
+ */
+
+#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ST_M (RTC_CNTL_SDIO_IDLE_INT_ST_V << RTC_CNTL_SDIO_IDLE_INT_ST_S)
+#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x00000001
+#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2
+
+/* RTC_CNTL_SLP_REJECT_INT_ST : RO; bitpos: [1]; default: 0;
+ * sleep reject interrupt state
+ */
+
+#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_M (RTC_CNTL_SLP_REJECT_INT_ST_V << RTC_CNTL_SLP_REJECT_INT_ST_S)
+#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x00000001
+#define RTC_CNTL_SLP_REJECT_INT_ST_S 1
+
+/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO; bitpos: [0]; default: 0;
+ * sleep wakeup interrupt state
+ */
+
+#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (RTC_CNTL_SLP_WAKEUP_INT_ST_V << RTC_CNTL_SLP_WAKEUP_INT_ST_S)
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x00000001
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0
+
+/* RTC_CNTL_INT_CLR_RTC_REG register
+ * rtc interrupt register
+ */
+
+#define RTC_CNTL_INT_CLR_RTC_REG (DR_REG_RTCCNTL_BASE + 0x4c)
+
+/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO; bitpos: [20];
+ * default: 0;
+ * cleartouch approach mode loop interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20))
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S)
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20
+
+/* RTC_CNTL_RTC_GLITCH_DET_INT_CLR : WO; bitpos: [19]; default: 0;
+ * Clear glitch det interrupt state
+ */
+
+#define RTC_CNTL_RTC_GLITCH_DET_INT_CLR (BIT(19))
+#define RTC_CNTL_RTC_GLITCH_DET_INT_CLR_M (RTC_CNTL_RTC_GLITCH_DET_INT_CLR_V << RTC_CNTL_RTC_GLITCH_DET_INT_CLR_S)
+#define RTC_CNTL_RTC_GLITCH_DET_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_GLITCH_DET_INT_CLR_S 19
+
+/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR : WO; bitpos: [18]; default: 0;
+ * Clear touch timeout interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR (BIT(18))
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_S)
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_S 18
+
+/* RTC_CNTL_RTC_COCPU_TRAP_INT_CLR : WO; bitpos: [17]; default: 0;
+ * Clear cocpu trap interrupt state
+ */
+
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_CLR (BIT(17))
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_M (RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_V << RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_S)
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_S 17
+
+/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR : WO; bitpos: [16]; default: 0;
+ * Clear RTC WDT interrupt state
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR (BIT(16))
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_S)
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_S 16
+
+/* RTC_CNTL_RTC_SWD_INT_CLR : WO; bitpos: [15]; default: 0;
+ * Clear super watch dog interrupt state
+ */
+
+#define RTC_CNTL_RTC_SWD_INT_CLR (BIT(15))
+#define RTC_CNTL_RTC_SWD_INT_CLR_M (RTC_CNTL_RTC_SWD_INT_CLR_V << RTC_CNTL_RTC_SWD_INT_CLR_S)
+#define RTC_CNTL_RTC_SWD_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_SWD_INT_CLR_S 15
+
+/* RTC_CNTL_RTC_SARADC2_INT_CLR : WO; bitpos: [14]; default: 0;
+ * Clear saradc2 interrupt state
+ */
+
+#define RTC_CNTL_RTC_SARADC2_INT_CLR (BIT(14))
+#define RTC_CNTL_RTC_SARADC2_INT_CLR_M (RTC_CNTL_RTC_SARADC2_INT_CLR_V << RTC_CNTL_RTC_SARADC2_INT_CLR_S)
+#define RTC_CNTL_RTC_SARADC2_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_SARADC2_INT_CLR_S 14
+
+/* RTC_CNTL_RTC_COCPU_INT_CLR : WO; bitpos: [13]; default: 0;
+ * Clear riscV cocpu interrupt state
+ */
+
+#define RTC_CNTL_RTC_COCPU_INT_CLR (BIT(13))
+#define RTC_CNTL_RTC_COCPU_INT_CLR_M (RTC_CNTL_RTC_COCPU_INT_CLR_V << RTC_CNTL_RTC_COCPU_INT_CLR_S)
+#define RTC_CNTL_RTC_COCPU_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_INT_CLR_S 13
+
+/* RTC_CNTL_RTC_TSENS_INT_CLR : WO; bitpos: [12]; default: 0;
+ * Clear tsens interrupt state
+ */
+
+#define RTC_CNTL_RTC_TSENS_INT_CLR (BIT(12))
+#define RTC_CNTL_RTC_TSENS_INT_CLR_M (RTC_CNTL_RTC_TSENS_INT_CLR_V << RTC_CNTL_RTC_TSENS_INT_CLR_S)
+#define RTC_CNTL_RTC_TSENS_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_TSENS_INT_CLR_S 12
+
+/* RTC_CNTL_RTC_SARADC1_INT_CLR : WO; bitpos: [11]; default: 0;
+ * Clear saradc1 interrupt state
+ */
+
+#define RTC_CNTL_RTC_SARADC1_INT_CLR (BIT(11))
+#define RTC_CNTL_RTC_SARADC1_INT_CLR_M (RTC_CNTL_RTC_SARADC1_INT_CLR_V << RTC_CNTL_RTC_SARADC1_INT_CLR_S)
+#define RTC_CNTL_RTC_SARADC1_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_SARADC1_INT_CLR_S 11
+
+/* RTC_CNTL_RTC_MAIN_TIMER_INT_CLR : WO; bitpos: [10]; default: 0;
+ * Clear RTC main timer interrupt state
+ */
+
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR (BIT(10))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_M (RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_V << RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_S)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_S 10
+
+/* RTC_CNTL_RTC_BROWN_OUT_INT_CLR : WO; bitpos: [9]; default: 0;
+ * Clear brown out interrupt state
+ */
+
+#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR (BIT(9))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_M (RTC_CNTL_RTC_BROWN_OUT_INT_CLR_V << RTC_CNTL_RTC_BROWN_OUT_INT_CLR_S)
+#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_S 9
+
+/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR : WO; bitpos: [8]; default: 0;
+ * Clear touch inactive interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR (BIT(8))
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_S)
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_S 8
+
+/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR : WO; bitpos: [7]; default: 0;
+ * Clear touch active interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR (BIT(7))
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_S)
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_S 7
+
+/* RTC_CNTL_RTC_TOUCH_DONE_INT_CLR : WO; bitpos: [6]; default: 0;
+ * Clear touch done interrupt state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_CLR (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_S)
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_S 6
+
+/* RTC_CNTL_RTC_ULP_CP_INT_CLR : WO; bitpos: [5]; default: 0;
+ * Clear ULP-coprocessor interrupt state
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_INT_CLR (BIT(5))
+#define RTC_CNTL_RTC_ULP_CP_INT_CLR_M (RTC_CNTL_RTC_ULP_CP_INT_CLR_V << RTC_CNTL_RTC_ULP_CP_INT_CLR_S)
+#define RTC_CNTL_RTC_ULP_CP_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_ULP_CP_INT_CLR_S 5
+
+/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR : WO; bitpos: [4]; default: 0;
+ * clear touch scan done interrupt raw
+ */
+
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR (BIT(4))
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_S)
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_S 4
+
+/* RTC_CNTL_RTC_WDT_INT_CLR : WO; bitpos: [3]; default: 0;
+ * Clear RTC WDT interrupt state
+ */
+
+#define RTC_CNTL_RTC_WDT_INT_CLR (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_CLR_M (RTC_CNTL_RTC_WDT_INT_CLR_V << RTC_CNTL_RTC_WDT_INT_CLR_S)
+#define RTC_CNTL_RTC_WDT_INT_CLR_V 0x00000001
+#define RTC_CNTL_RTC_WDT_INT_CLR_S 3
+
+/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO; bitpos: [2]; default: 0;
+ * Clear SDIO idle interrupt state
+ */
+
+#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (RTC_CNTL_SDIO_IDLE_INT_CLR_V << RTC_CNTL_SDIO_IDLE_INT_CLR_S)
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x00000001
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2
+
+/* RTC_CNTL_SLP_REJECT_INT_CLR : WO; bitpos: [1]; default: 0;
+ * Clear sleep reject interrupt state
+ */
+
+#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_M (RTC_CNTL_SLP_REJECT_INT_CLR_V << RTC_CNTL_SLP_REJECT_INT_CLR_S)
+#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x00000001
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1
+
+/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO; bitpos: [0]; default: 0;
+ * Clear sleep wakeup interrupt state
+ */
+
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (RTC_CNTL_SLP_WAKEUP_INT_CLR_V << RTC_CNTL_SLP_WAKEUP_INT_CLR_S)
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x00000001
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0
+
+/* RTC_CNTL_RTC_STORE0_REG register
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50)
+
+/* RTC_CNTL_RTC_SCRATCH0 : R/W; bitpos: [31:0]; default: 0;
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_SCRATCH0 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH0_M (RTC_CNTL_RTC_SCRATCH0_V << RTC_CNTL_RTC_SCRATCH0_S)
+#define RTC_CNTL_RTC_SCRATCH0_V 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH0_S 0
+
+/* RTC_CNTL_RTC_STORE1_REG register
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54)
+
+/* RTC_CNTL_RTC_SCRATCH1 : R/W; bitpos: [31:0]; default: 0;
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_SCRATCH1 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH1_M (RTC_CNTL_RTC_SCRATCH1_V << RTC_CNTL_RTC_SCRATCH1_S)
+#define RTC_CNTL_RTC_SCRATCH1_V 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH1_S 0
+
+/* RTC_CNTL_RTC_STORE2_REG register
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58)
+
+/* RTC_CNTL_RTC_SCRATCH2 : R/W; bitpos: [31:0]; default: 0;
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_SCRATCH2 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH2_M (RTC_CNTL_RTC_SCRATCH2_V << RTC_CNTL_RTC_SCRATCH2_S)
+#define RTC_CNTL_RTC_SCRATCH2_V 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH2_S 0
+
+/* RTC_CNTL_RTC_STORE3_REG register
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5c)
+
+/* RTC_CNTL_RTC_SCRATCH3 : R/W; bitpos: [31:0]; default: 0;
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_SCRATCH3 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH3_M (RTC_CNTL_RTC_SCRATCH3_V << RTC_CNTL_RTC_SCRATCH3_S)
+#define RTC_CNTL_RTC_SCRATCH3_V 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH3_S 0
+
+/* RTC_CNTL_RTC_EXT_XTL_CONF_REG register
+ * Reserved register
+ */
+
+#define RTC_CNTL_RTC_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60)
+
+/* RTC_CNTL_XTL_EXT_CTR_EN : R/W; bitpos: [31]; default: 0;
+ * Reserved register
+ */
+
+#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_M (RTC_CNTL_XTL_EXT_CTR_EN_V << RTC_CNTL_XTL_EXT_CTR_EN_S)
+#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x00000001
+#define RTC_CNTL_XTL_EXT_CTR_EN_S 31
+
+/* RTC_CNTL_XTL_EXT_CTR_LV : R/W; bitpos: [30]; default: 0;
+ * 0: power down XTAL at high level, 1: power down XTAL at low level
+ */
+
+#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_M (RTC_CNTL_XTL_EXT_CTR_LV_V << RTC_CNTL_XTL_EXT_CTR_LV_S)
+#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x00000001
+#define RTC_CNTL_XTL_EXT_CTR_LV_S 30
+
+/* RTC_CNTL_RTC_XTAL32K_GPIO_SEL : R/W; bitpos: [23]; default: 0;
+ * XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_GPIO_SEL (BIT(23))
+#define RTC_CNTL_RTC_XTAL32K_GPIO_SEL_M (RTC_CNTL_RTC_XTAL32K_GPIO_SEL_V << RTC_CNTL_RTC_XTAL32K_GPIO_SEL_S)
+#define RTC_CNTL_RTC_XTAL32K_GPIO_SEL_V 0x00000001
+#define RTC_CNTL_RTC_XTAL32K_GPIO_SEL_S 23
+
+/* RTC_CNTL_RTC_WDT_STATE : RO; bitpos: [22:20]; default: 0;
+ * state of 32k_wdt
+ */
+
+#define RTC_CNTL_RTC_WDT_STATE 0x00000007
+#define RTC_CNTL_RTC_WDT_STATE_M (RTC_CNTL_RTC_WDT_STATE_V << RTC_CNTL_RTC_WDT_STATE_S)
+#define RTC_CNTL_RTC_WDT_STATE_V 0x00000007
+#define RTC_CNTL_RTC_WDT_STATE_S 20
+
+/* RTC_CNTL_DAC_XTAL_32K : R/W; bitpos: [19:17]; default: 3;
+ * DAC_XTAL_32K
+ */
+
+#define RTC_CNTL_DAC_XTAL_32K 0x00000007
+#define RTC_CNTL_DAC_XTAL_32K_M (RTC_CNTL_DAC_XTAL_32K_V << RTC_CNTL_DAC_XTAL_32K_S)
+#define RTC_CNTL_DAC_XTAL_32K_V 0x00000007
+#define RTC_CNTL_DAC_XTAL_32K_S 17
+
+/* RTC_CNTL_XPD_XTAL_32K : R/W; bitpos: [16]; default: 0;
+ * XPD_XTAL_32K
+ */
+
+#define RTC_CNTL_XPD_XTAL_32K (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_M (RTC_CNTL_XPD_XTAL_32K_V << RTC_CNTL_XPD_XTAL_32K_S)
+#define RTC_CNTL_XPD_XTAL_32K_V 0x00000001
+#define RTC_CNTL_XPD_XTAL_32K_S 16
+
+/* RTC_CNTL_DRES_XTAL_32K : R/W; bitpos: [15:13]; default: 3;
+ * DRES_XTAL_32K
+ */
+
+#define RTC_CNTL_DRES_XTAL_32K 0x00000007
+#define RTC_CNTL_DRES_XTAL_32K_M (RTC_CNTL_DRES_XTAL_32K_V << RTC_CNTL_DRES_XTAL_32K_S)
+#define RTC_CNTL_DRES_XTAL_32K_V 0x00000007
+#define RTC_CNTL_DRES_XTAL_32K_S 13
+
+/* RTC_CNTL_DGM_XTAL_32K : R/W; bitpos: [12:10]; default: 3;
+ * xtal_32k gm control
+ */
+
+#define RTC_CNTL_DGM_XTAL_32K 0x00000007
+#define RTC_CNTL_DGM_XTAL_32K_M (RTC_CNTL_DGM_XTAL_32K_V << RTC_CNTL_DGM_XTAL_32K_S)
+#define RTC_CNTL_DGM_XTAL_32K_V 0x00000007
+#define RTC_CNTL_DGM_XTAL_32K_S 10
+
+/* RTC_CNTL_DBUF_XTAL_32K : R/W; bitpos: [9]; default: 0;
+ * 0: single-end buffer 1: differential buffer
+ */
+
+#define RTC_CNTL_DBUF_XTAL_32K (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_M (RTC_CNTL_DBUF_XTAL_32K_V << RTC_CNTL_DBUF_XTAL_32K_S)
+#define RTC_CNTL_DBUF_XTAL_32K_V 0x00000001
+#define RTC_CNTL_DBUF_XTAL_32K_S 9
+
+/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W; bitpos: [8]; default: 0;
+ * apply an internal clock to help xtal 32k to start
+ */
+
+#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_M (RTC_CNTL_ENCKINIT_XTAL_32K_V << RTC_CNTL_ENCKINIT_XTAL_32K_S)
+#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x00000001
+#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8
+
+/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W; bitpos: [7]; default: 1;
+ * Xtal 32k xpd control by sw or fsm
+ */
+
+#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_M (RTC_CNTL_XTAL32K_XPD_FORCE_V << RTC_CNTL_XTAL32K_XPD_FORCE_S)
+#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x00000001
+#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7
+
+/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W; bitpos: [6]; default: 0;
+ * xtal 32k switch back xtal when xtal is restarted
+ */
+
+#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (RTC_CNTL_XTAL32K_AUTO_RETURN_V << RTC_CNTL_XTAL32K_AUTO_RETURN_S)
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x00000001
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6
+
+/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W; bitpos: [5]; default: 0;
+ * xtal 32k restart xtal when xtal is dead
+ */
+
+#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (RTC_CNTL_XTAL32K_AUTO_RESTART_V << RTC_CNTL_XTAL32K_AUTO_RESTART_S)
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x00000001
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5
+
+/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W; bitpos: [4]; default: 0;
+ * xtal 32k switch to back up clock when xtal is dead
+ */
+
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (RTC_CNTL_XTAL32K_AUTO_BACKUP_V << RTC_CNTL_XTAL32K_AUTO_BACKUP_S)
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x00000001
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4
+
+/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W; bitpos: [3]; default: 0;
+ * xtal 32k external xtal clock force on
+ */
+
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (RTC_CNTL_XTAL32K_EXT_CLK_FO_V << RTC_CNTL_XTAL32K_EXT_CLK_FO_S)
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x00000001
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3
+
+/* RTC_CNTL_XTAL32K_WDT_RESET : R/W; bitpos: [2]; default: 0;
+ * xtal 32k watch dog sw reset
+ */
+
+#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_M (RTC_CNTL_XTAL32K_WDT_RESET_V << RTC_CNTL_XTAL32K_WDT_RESET_S)
+#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x00000001
+#define RTC_CNTL_XTAL32K_WDT_RESET_S 2
+
+/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W; bitpos: [1]; default: 0;
+ * xtal 32k watch dog clock force on
+ */
+
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (RTC_CNTL_XTAL32K_WDT_CLK_FO_V << RTC_CNTL_XTAL32K_WDT_CLK_FO_S)
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x00000001
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1
+
+/* RTC_CNTL_XTAL32K_WDT_EN : R/W; bitpos: [0]; default: 0;
+ * xtal 32k watch dog enable
+ */
+
+#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_M (RTC_CNTL_XTAL32K_WDT_EN_V << RTC_CNTL_XTAL32K_WDT_EN_S)
+#define RTC_CNTL_XTAL32K_WDT_EN_V 0x00000001
+#define RTC_CNTL_XTAL32K_WDT_EN_S 0
+
+/* RTC_CNTL_RTC_EXT_WAKEUP_CONF_REG register
+ * ext wakeup configure
+ */
+
+#define RTC_CNTL_RTC_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64)
+
+/* RTC_CNTL_EXT_WAKEUP1_LV : R/W; bitpos: [31]; default: 0;
+ * 0: external wakeup at low level, 1: external wakeup at high level
+ */
+
+#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31))
+#define RTC_CNTL_EXT_WAKEUP1_LV_M (RTC_CNTL_EXT_WAKEUP1_LV_V << RTC_CNTL_EXT_WAKEUP1_LV_S)
+#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x00000001
+#define RTC_CNTL_EXT_WAKEUP1_LV_S 31
+
+/* RTC_CNTL_EXT_WAKEUP0_LV : R/W; bitpos: [30]; default: 0;
+ * 0: external wakeup at low level, 1: external wakeup at high level
+ */
+
+#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30))
+#define RTC_CNTL_EXT_WAKEUP0_LV_M (RTC_CNTL_EXT_WAKEUP0_LV_V << RTC_CNTL_EXT_WAKEUP0_LV_S)
+#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x00000001
+#define RTC_CNTL_EXT_WAKEUP0_LV_S 30
+
+/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W; bitpos: [29]; default: 0;
+ * enable filter for gpio wakeup event
+ */
+
+#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (RTC_CNTL_GPIO_WAKEUP_FILTER_V << RTC_CNTL_GPIO_WAKEUP_FILTER_S)
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x00000001
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29
+
+/* RTC_CNTL_RTC_SLP_REJECT_CONF_REG register
+ * reject sleep register
+ */
+
+#define RTC_CNTL_RTC_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68)
+
+/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0;
+ * enable reject for deep sleep
+ */
+
+#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (RTC_CNTL_DEEP_SLP_REJECT_EN_V << RTC_CNTL_DEEP_SLP_REJECT_EN_S)
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x00000001
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31
+
+/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W; bitpos: [30]; default: 0;
+ * enable reject for light sleep
+ */
+
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (RTC_CNTL_LIGHT_SLP_REJECT_EN_V << RTC_CNTL_LIGHT_SLP_REJECT_EN_S)
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x00000001
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30
+
+/* RTC_CNTL_RTC_SLEEP_REJECT_ENA : R/W; bitpos: [29:12]; default: 0;
+ * sleep reject enable
+ */
+
+#define RTC_CNTL_RTC_SLEEP_REJECT_ENA 0x0003ffff
+#define RTC_CNTL_RTC_SLEEP_REJECT_ENA_M (RTC_CNTL_RTC_SLEEP_REJECT_ENA_V << RTC_CNTL_RTC_SLEEP_REJECT_ENA_S)
+#define RTC_CNTL_RTC_SLEEP_REJECT_ENA_V 0x0003ffff
+#define RTC_CNTL_RTC_SLEEP_REJECT_ENA_S 12
+
+/* RTC_CNTL_RTC_CPU_PERIOD_CONF_REG register
+ * conigure cpu freq
+ */
+
+#define RTC_CNTL_RTC_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c)
+
+/* RTC_CNTL_RTC_CPUPERIOD_SEL : R/W; bitpos: [31:30]; default: 0;
+ * conigure cpu freq
+ */
+
+#define RTC_CNTL_RTC_CPUPERIOD_SEL 0x00000003
+#define RTC_CNTL_RTC_CPUPERIOD_SEL_M (RTC_CNTL_RTC_CPUPERIOD_SEL_V << RTC_CNTL_RTC_CPUPERIOD_SEL_S)
+#define RTC_CNTL_RTC_CPUPERIOD_SEL_V 0x00000003
+#define RTC_CNTL_RTC_CPUPERIOD_SEL_S 30
+
+/* RTC_CNTL_RTC_CPUSEL_CONF : R/W; bitpos: [29]; default: 0;
+ * CPU sel option
+ */
+
+#define RTC_CNTL_RTC_CPUSEL_CONF (BIT(29))
+#define RTC_CNTL_RTC_CPUSEL_CONF_M (RTC_CNTL_RTC_CPUSEL_CONF_V << RTC_CNTL_RTC_CPUSEL_CONF_S)
+#define RTC_CNTL_RTC_CPUSEL_CONF_V 0x00000001
+#define RTC_CNTL_RTC_CPUSEL_CONF_S 29
+
+/* RTC_CNTL_RTC_SDIO_ACT_CONF_REG register
+ * No public
+ */
+
+#define RTC_CNTL_RTC_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70)
+
+/* RTC_CNTL_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_SDIO_ACT_DNUM 0x000003ff
+#define RTC_CNTL_SDIO_ACT_DNUM_M (RTC_CNTL_SDIO_ACT_DNUM_V << RTC_CNTL_SDIO_ACT_DNUM_S)
+#define RTC_CNTL_SDIO_ACT_DNUM_V 0x000003ff
+#define RTC_CNTL_SDIO_ACT_DNUM_S 22
+
+/* RTC_CNTL_RTC_CLK_CONF_REG register
+ * configure clock register
+ */
+
+#define RTC_CNTL_RTC_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74)
+
+/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W; bitpos: [31:30]; default: 0;
+ * select slow clock
+ */
+
+#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_M (RTC_CNTL_ANA_CLK_RTC_SEL_V << RTC_CNTL_ANA_CLK_RTC_SEL_S)
+#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30
+
+/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W; bitpos: [29]; default: 0;
+ * fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M
+ */
+
+#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_M (RTC_CNTL_FAST_CLK_RTC_SEL_V << RTC_CNTL_FAST_CLK_RTC_SEL_S)
+#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x00000001
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
+
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W; bitpos: [28]; default: 1;
+ * force global xtal no gating
+ */
+
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S)
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x00000001
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28
+
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W; bitpos: [27]; default: 0;
+ * force global xtal gating
+ */
+
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V << RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S)
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x00000001
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27
+
+/* RTC_CNTL_CK8M_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ * CK8M force power up
+ */
+
+#define RTC_CNTL_CK8M_FORCE_PU (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_M (RTC_CNTL_CK8M_FORCE_PU_V << RTC_CNTL_CK8M_FORCE_PU_S)
+#define RTC_CNTL_CK8M_FORCE_PU_V 0x00000001
+#define RTC_CNTL_CK8M_FORCE_PU_S 26
+
+/* RTC_CNTL_CK8M_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ * CK8M force power down
+ */
+
+#define RTC_CNTL_CK8M_FORCE_PD (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_M (RTC_CNTL_CK8M_FORCE_PD_V << RTC_CNTL_CK8M_FORCE_PD_S)
+#define RTC_CNTL_CK8M_FORCE_PD_V 0x00000001
+#define RTC_CNTL_CK8M_FORCE_PD_S 25
+
+/* RTC_CNTL_CK8M_DFREQ : R/W; bitpos: [24:17]; default: 172;
+ * CK8M_DFREQ
+ */
+
+#define RTC_CNTL_CK8M_DFREQ 0x000000ff
+#define RTC_CNTL_CK8M_DFREQ_M (RTC_CNTL_CK8M_DFREQ_V << RTC_CNTL_CK8M_DFREQ_S)
+#define RTC_CNTL_CK8M_DFREQ_V 0x000000ff
+#define RTC_CNTL_CK8M_DFREQ_S 17
+
+/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W; bitpos: [16]; default: 0;
+ * CK8M force no gating during sleep
+ */
+
+#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_M (RTC_CNTL_CK8M_FORCE_NOGATING_V << RTC_CNTL_CK8M_FORCE_NOGATING_S)
+#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x00000001
+#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16
+
+/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W; bitpos: [15]; default: 0;
+ * XTAL force no gating during sleep
+ */
+
+#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_FORCE_NOGATING_S)
+#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x00000001
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15
+
+/* RTC_CNTL_CK8M_DIV_SEL : R/W; bitpos: [14:12]; default: 3;
+ * divider = reg_ck8m_div_sel + 1
+ */
+
+#define RTC_CNTL_CK8M_DIV_SEL 0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_M (RTC_CNTL_CK8M_DIV_SEL_V << RTC_CNTL_CK8M_DIV_SEL_S)
+#define RTC_CNTL_CK8M_DIV_SEL_V 0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_S 12
+
+/* RTC_CNTL_DIG_CLK8M_EN : R/W; bitpos: [10]; default: 0;
+ * enable CK8M for digital core (no relationship with RTC core)
+ */
+
+#define RTC_CNTL_DIG_CLK8M_EN (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_M (RTC_CNTL_DIG_CLK8M_EN_V << RTC_CNTL_DIG_CLK8M_EN_S)
+#define RTC_CNTL_DIG_CLK8M_EN_V 0x00000001
+#define RTC_CNTL_DIG_CLK8M_EN_S 10
+
+/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W; bitpos: [9]; default: 1;
+ * enable CK8M_D256_OUT for digital core (no relationship with RTC core)
+ */
+
+#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_M (RTC_CNTL_DIG_CLK8M_D256_EN_V << RTC_CNTL_DIG_CLK8M_D256_EN_S)
+#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x00000001
+#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9
+
+/* RTC_CNTL_DIG_XTAL32K_EN : R/W; bitpos: [8]; default: 0;
+ * enable CK_XTAL_32K for digital core (no relationship with RTC core)
+ */
+
+#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_M (RTC_CNTL_DIG_XTAL32K_EN_V << RTC_CNTL_DIG_XTAL32K_EN_S)
+#define RTC_CNTL_DIG_XTAL32K_EN_V 0x00000001
+#define RTC_CNTL_DIG_XTAL32K_EN_S 8
+
+/* RTC_CNTL_ENB_CK8M_DIV : R/W; bitpos: [7]; default: 0;
+ * 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256
+ */
+
+#define RTC_CNTL_ENB_CK8M_DIV (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_M (RTC_CNTL_ENB_CK8M_DIV_V << RTC_CNTL_ENB_CK8M_DIV_S)
+#define RTC_CNTL_ENB_CK8M_DIV_V 0x00000001
+#define RTC_CNTL_ENB_CK8M_DIV_S 7
+
+/* RTC_CNTL_ENB_CK8M : R/W; bitpos: [6]; default: 0;
+ * disable CK8M and CK8M_D256_OUT
+ */
+
+#define RTC_CNTL_ENB_CK8M (BIT(6))
+#define RTC_CNTL_ENB_CK8M_M (RTC_CNTL_ENB_CK8M_V << RTC_CNTL_ENB_CK8M_S)
+#define RTC_CNTL_ENB_CK8M_V 0x00000001
+#define RTC_CNTL_ENB_CK8M_S 6
+
+/* RTC_CNTL_CK8M_DIV : R/W; bitpos: [5:4]; default: 1;
+ * CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024.
+ */
+
+#define RTC_CNTL_CK8M_DIV 0x00000003
+#define RTC_CNTL_CK8M_DIV_M (RTC_CNTL_CK8M_DIV_V << RTC_CNTL_CK8M_DIV_S)
+#define RTC_CNTL_CK8M_DIV_V 0x00000003
+#define RTC_CNTL_CK8M_DIV_S 4
+
+/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W; bitpos: [3]; default: 1;
+ * used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel,
+ * then set vld to actually switch the clk
+ */
+
+#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (RTC_CNTL_CK8M_DIV_SEL_VLD_V << RTC_CNTL_CK8M_DIV_SEL_VLD_S)
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x00000001
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3
+
+/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W; bitpos: [2]; default: 1;
+ * force efuse clk nogating
+ */
+
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V << RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S)
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x00000001
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2
+
+/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W; bitpos: [1]; default: 0;
+ * force efuse clk gating
+ */
+
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (RTC_CNTL_EFUSE_CLK_FORCE_GATING_V << RTC_CNTL_EFUSE_CLK_FORCE_GATING_S)
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x00000001
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1
+
+/* RTC_CNTL_RTC_SLOW_CLK_CONF_REG register
+ * configure slow clk
+ */
+
+#define RTC_CNTL_RTC_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78)
+
+/* RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE : R/W; bitpos: [31]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE (BIT(31))
+#define RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_M (RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_V << RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_S)
+#define RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_V 0x00000001
+#define RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_S 31
+
+/* RTC_CNTL_RTC_ANA_CLK_DIV : R/W; bitpos: [30:23]; default: 0;
+ * rtc clk div
+ */
+
+#define RTC_CNTL_RTC_ANA_CLK_DIV 0x000000ff
+#define RTC_CNTL_RTC_ANA_CLK_DIV_M (RTC_CNTL_RTC_ANA_CLK_DIV_V << RTC_CNTL_RTC_ANA_CLK_DIV_S)
+#define RTC_CNTL_RTC_ANA_CLK_DIV_V 0x000000ff
+#define RTC_CNTL_RTC_ANA_CLK_DIV_S 23
+
+/* RTC_CNTL_RTC_ANA_CLK_DIV_VLD : R/W; bitpos: [22]; default: 1;
+ * used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set
+ * vld to actually switch the clk
+ */
+
+#define RTC_CNTL_RTC_ANA_CLK_DIV_VLD (BIT(22))
+#define RTC_CNTL_RTC_ANA_CLK_DIV_VLD_M (RTC_CNTL_RTC_ANA_CLK_DIV_VLD_V << RTC_CNTL_RTC_ANA_CLK_DIV_VLD_S)
+#define RTC_CNTL_RTC_ANA_CLK_DIV_VLD_V 0x00000001
+#define RTC_CNTL_RTC_ANA_CLK_DIV_VLD_S 22
+
+/* RTC_CNTL_RTC_SDIO_CONF_REG register
+ * configure flash power
+ */
+
+#define RTC_CNTL_RTC_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7c)
+
+/* RTC_CNTL_XPD_SDIO_REG : R/W; bitpos: [31]; default: 0;
+ * power on flash regulator
+ */
+
+#define RTC_CNTL_XPD_SDIO_REG (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_M (RTC_CNTL_XPD_SDIO_REG_V << RTC_CNTL_XPD_SDIO_REG_S)
+#define RTC_CNTL_XPD_SDIO_REG_V 0x00000001
+#define RTC_CNTL_XPD_SDIO_REG_S 31
+
+/* RTC_CNTL_DREFH_SDIO : R/W; bitpos: [30:29]; default: 0;
+ * SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
+ */
+
+#define RTC_CNTL_DREFH_SDIO 0x00000003
+#define RTC_CNTL_DREFH_SDIO_M (RTC_CNTL_DREFH_SDIO_V << RTC_CNTL_DREFH_SDIO_S)
+#define RTC_CNTL_DREFH_SDIO_V 0x00000003
+#define RTC_CNTL_DREFH_SDIO_S 29
+
+/* RTC_CNTL_DREFM_SDIO : R/W; bitpos: [28:27]; default: 1;
+ * SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
+ */
+
+#define RTC_CNTL_DREFM_SDIO 0x00000003
+#define RTC_CNTL_DREFM_SDIO_M (RTC_CNTL_DREFM_SDIO_V << RTC_CNTL_DREFM_SDIO_S)
+#define RTC_CNTL_DREFM_SDIO_V 0x00000003
+#define RTC_CNTL_DREFM_SDIO_S 27
+
+/* RTC_CNTL_DREFL_SDIO : R/W; bitpos: [26:25]; default: 1;
+ * SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
+ */
+
+#define RTC_CNTL_DREFL_SDIO 0x00000003
+#define RTC_CNTL_DREFL_SDIO_M (RTC_CNTL_DREFL_SDIO_V << RTC_CNTL_DREFL_SDIO_S)
+#define RTC_CNTL_DREFL_SDIO_V 0x00000003
+#define RTC_CNTL_DREFL_SDIO_S 25
+
+/* RTC_CNTL_REG1P8_READY : RO; bitpos: [24]; default: 0;
+ * read only register for REG1P8_READY
+ */
+
+#define RTC_CNTL_REG1P8_READY (BIT(24))
+#define RTC_CNTL_REG1P8_READY_M (RTC_CNTL_REG1P8_READY_V << RTC_CNTL_REG1P8_READY_S)
+#define RTC_CNTL_REG1P8_READY_V 0x00000001
+#define RTC_CNTL_REG1P8_READY_S 24
+
+/* RTC_CNTL_SDIO_TIEH : R/W; bitpos: [23]; default: 1;
+ * SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
+ */
+
+#define RTC_CNTL_SDIO_TIEH (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_M (RTC_CNTL_SDIO_TIEH_V << RTC_CNTL_SDIO_TIEH_S)
+#define RTC_CNTL_SDIO_TIEH_V 0x00000001
+#define RTC_CNTL_SDIO_TIEH_S 23
+
+/* RTC_CNTL_SDIO_FORCE : R/W; bitpos: [22]; default: 0;
+ * 1: use SW option to control SDIO_REG, 0: use state machine
+ */
+
+#define RTC_CNTL_SDIO_FORCE (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_M (RTC_CNTL_SDIO_FORCE_V << RTC_CNTL_SDIO_FORCE_S)
+#define RTC_CNTL_SDIO_FORCE_V 0x00000001
+#define RTC_CNTL_SDIO_FORCE_S 22
+
+/* RTC_CNTL_SDIO_REG_PD_EN : R/W; bitpos: [21]; default: 1;
+ * power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
+ */
+
+#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21))
+#define RTC_CNTL_SDIO_REG_PD_EN_M (RTC_CNTL_SDIO_REG_PD_EN_V << RTC_CNTL_SDIO_REG_PD_EN_S)
+#define RTC_CNTL_SDIO_REG_PD_EN_V 0x00000001
+#define RTC_CNTL_SDIO_REG_PD_EN_S 21
+
+/* RTC_CNTL_SDIO_ENCURLIM : R/W; bitpos: [20]; default: 1;
+ * enable current limit
+ */
+
+#define RTC_CNTL_SDIO_ENCURLIM (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_M (RTC_CNTL_SDIO_ENCURLIM_V << RTC_CNTL_SDIO_ENCURLIM_S)
+#define RTC_CNTL_SDIO_ENCURLIM_V 0x00000001
+#define RTC_CNTL_SDIO_ENCURLIM_S 20
+
+/* RTC_CNTL_SDIO_MODECURLIM : R/W; bitpos: [19]; default: 0;
+ * select current limit mode
+ */
+
+#define RTC_CNTL_SDIO_MODECURLIM (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_M (RTC_CNTL_SDIO_MODECURLIM_V << RTC_CNTL_SDIO_MODECURLIM_S)
+#define RTC_CNTL_SDIO_MODECURLIM_V 0x00000001
+#define RTC_CNTL_SDIO_MODECURLIM_S 19
+
+/* RTC_CNTL_SDIO_DCURLIM : R/W; bitpos: [18:16]; default: 0;
+ * tune current limit threshold when tieh = 0. About 800mA/(8+d)
+ */
+
+#define RTC_CNTL_SDIO_DCURLIM 0x00000007
+#define RTC_CNTL_SDIO_DCURLIM_M (RTC_CNTL_SDIO_DCURLIM_V << RTC_CNTL_SDIO_DCURLIM_S)
+#define RTC_CNTL_SDIO_DCURLIM_V 0x00000007
+#define RTC_CNTL_SDIO_DCURLIM_S 16
+
+/* RTC_CNTL_SDIO_EN_INITI : R/W; bitpos: [15]; default: 1;
+ * 0 to set init[1:0]=0
+ */
+
+#define RTC_CNTL_SDIO_EN_INITI (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_M (RTC_CNTL_SDIO_EN_INITI_V << RTC_CNTL_SDIO_EN_INITI_S)
+#define RTC_CNTL_SDIO_EN_INITI_V 0x00000001
+#define RTC_CNTL_SDIO_EN_INITI_S 15
+
+/* RTC_CNTL_SDIO_INITI : R/W; bitpos: [14:13]; default: 1;
+ * add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k
+ */
+
+#define RTC_CNTL_SDIO_INITI 0x00000003
+#define RTC_CNTL_SDIO_INITI_M (RTC_CNTL_SDIO_INITI_V << RTC_CNTL_SDIO_INITI_S)
+#define RTC_CNTL_SDIO_INITI_V 0x00000003
+#define RTC_CNTL_SDIO_INITI_S 13
+
+/* RTC_CNTL_SDIO_DCAP : R/W; bitpos: [12:11]; default: 3;
+ * ability to prevent LDO from overshoot
+ */
+
+#define RTC_CNTL_SDIO_DCAP 0x00000003
+#define RTC_CNTL_SDIO_DCAP_M (RTC_CNTL_SDIO_DCAP_V << RTC_CNTL_SDIO_DCAP_S)
+#define RTC_CNTL_SDIO_DCAP_V 0x00000003
+#define RTC_CNTL_SDIO_DCAP_S 11
+
+/* RTC_CNTL_SDIO_DTHDRV : R/W; bitpos: [10:9]; default: 3;
+ * Tieh = 1 mode drive ability. Initially set to 0 to limit charge current,
+ * set to 3 after several us.
+ */
+
+#define RTC_CNTL_SDIO_DTHDRV 0x00000003
+#define RTC_CNTL_SDIO_DTHDRV_M (RTC_CNTL_SDIO_DTHDRV_V << RTC_CNTL_SDIO_DTHDRV_S)
+#define RTC_CNTL_SDIO_DTHDRV_V 0x00000003
+#define RTC_CNTL_SDIO_DTHDRV_S 9
+
+/* RTC_CNTL_SDIO_TIMER_TARGET : R/W; bitpos: [7:0]; default: 10;
+ * timer count to apply reg_sdio_dcap after sdio power on
+ */
+
+#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000ff
+#define RTC_CNTL_SDIO_TIMER_TARGET_M (RTC_CNTL_SDIO_TIMER_TARGET_V << RTC_CNTL_SDIO_TIMER_TARGET_S)
+#define RTC_CNTL_SDIO_TIMER_TARGET_V 0x000000ff
+#define RTC_CNTL_SDIO_TIMER_TARGET_S 0
+
+/* RTC_CNTL_RTC_BIAS_CONF_REG register
+ * No public
+ */
+
+#define RTC_CNTL_RTC_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80)
+
+/* RTC_CNTL_DBG_ATTEN_WAKEUP : R/W; bitpos: [29:26]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_DBG_ATTEN_WAKEUP 0x0000000f
+#define RTC_CNTL_DBG_ATTEN_WAKEUP_M (RTC_CNTL_DBG_ATTEN_WAKEUP_V << RTC_CNTL_DBG_ATTEN_WAKEUP_S)
+#define RTC_CNTL_DBG_ATTEN_WAKEUP_V 0x0000000f
+#define RTC_CNTL_DBG_ATTEN_WAKEUP_S 26
+
+/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W; bitpos: [25:22]; default: 0;
+ * DBG_ATTEN when rtc in monitor state
+ */
+
+#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000f
+#define RTC_CNTL_DBG_ATTEN_MONITOR_M (RTC_CNTL_DBG_ATTEN_MONITOR_V << RTC_CNTL_DBG_ATTEN_MONITOR_S)
+#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0x0000000f
+#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22
+
+/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W; bitpos: [21:18]; default: 0;
+ * DBG_ATTEN when rtc in sleep state
+ */
+
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000f
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M (RTC_CNTL_DBG_ATTEN_DEEP_SLP_V << RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0x0000000f
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18
+
+/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W; bitpos: [17]; default: 0;
+ * bias_sleep when rtc in monitor state
+ */
+
+#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (RTC_CNTL_BIAS_SLEEP_MONITOR_V << RTC_CNTL_BIAS_SLEEP_MONITOR_S)
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x00000001
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17
+
+/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W; bitpos: [16]; default: 1;
+ * bias_sleep when rtc in sleep_state
+ */
+
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V << RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S)
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x00000001
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16
+
+/* RTC_CNTL_PD_CUR_MONITOR : R/W; bitpos: [15]; default: 0;
+ * xpd cur when rtc in monitor state
+ */
+
+#define RTC_CNTL_PD_CUR_MONITOR (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_M (RTC_CNTL_PD_CUR_MONITOR_V << RTC_CNTL_PD_CUR_MONITOR_S)
+#define RTC_CNTL_PD_CUR_MONITOR_V 0x00000001
+#define RTC_CNTL_PD_CUR_MONITOR_S 15
+
+/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W; bitpos: [14]; default: 0;
+ * xpd cur when rtc in sleep_state
+ */
+
+#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_M (RTC_CNTL_PD_CUR_DEEP_SLP_V << RTC_CNTL_PD_CUR_DEEP_SLP_S)
+#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x00000001
+#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14
+
+/* RTC_CNTL_BIAS_BUF_MONITOR : R/W; bitpos: [13]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_M (RTC_CNTL_BIAS_BUF_MONITOR_V << RTC_CNTL_BIAS_BUF_MONITOR_S)
+#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x00000001
+#define RTC_CNTL_BIAS_BUF_MONITOR_S 13
+
+/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W; bitpos: [12]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (RTC_CNTL_BIAS_BUF_DEEP_SLP_V << RTC_CNTL_BIAS_BUF_DEEP_SLP_S)
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x00000001
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12
+
+/* RTC_CNTL_BIAS_BUF_WAKE : R/W; bitpos: [11]; default: 1;
+ * No public
+ */
+
+#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_M (RTC_CNTL_BIAS_BUF_WAKE_V << RTC_CNTL_BIAS_BUF_WAKE_S)
+#define RTC_CNTL_BIAS_BUF_WAKE_V 0x00000001
+#define RTC_CNTL_BIAS_BUF_WAKE_S 11
+
+/* RTC_CNTL_BIAS_BUF_IDLE : R/W; bitpos: [10]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_M (RTC_CNTL_BIAS_BUF_IDLE_V << RTC_CNTL_BIAS_BUF_IDLE_S)
+#define RTC_CNTL_BIAS_BUF_IDLE_V 0x00000001
+#define RTC_CNTL_BIAS_BUF_IDLE_S 10
+
+/* RTC_CNTL_RTC_REG register
+ * configure rtc regulator
+ */
+
+#define RTC_CNTL_RTC_REG (DR_REG_RTCCNTL_BASE + 0x84)
+
+/* RTC_CNTL_RTC_REGULATOR_FORCE_PU : R/W; bitpos: [31]; default: 1;
+ * RTC_REG force power on (for RTC_REG power down means decrease the voltage
+ * to 0.8v or lower )
+ */
+
+#define RTC_CNTL_RTC_REGULATOR_FORCE_PU (BIT(31))
+#define RTC_CNTL_RTC_REGULATOR_FORCE_PU_M (RTC_CNTL_RTC_REGULATOR_FORCE_PU_V << RTC_CNTL_RTC_REGULATOR_FORCE_PU_S)
+#define RTC_CNTL_RTC_REGULATOR_FORCE_PU_V 0x00000001
+#define RTC_CNTL_RTC_REGULATOR_FORCE_PU_S 31
+
+/* RTC_CNTL_RTC_REGULATOR_FORCE_PD : R/W; bitpos: [30]; default: 0;
+ * RTC_REG force power down (for RTC_REG power down means decrease the
+ * voltage to 0.8v or lower )
+ */
+
+#define RTC_CNTL_RTC_REGULATOR_FORCE_PD (BIT(30))
+#define RTC_CNTL_RTC_REGULATOR_FORCE_PD_M (RTC_CNTL_RTC_REGULATOR_FORCE_PD_V << RTC_CNTL_RTC_REGULATOR_FORCE_PD_S)
+#define RTC_CNTL_RTC_REGULATOR_FORCE_PD_V 0x00000001
+#define RTC_CNTL_RTC_REGULATOR_FORCE_PD_S 30
+
+/* RTC_CNTL_RTC_DBOOST_FORCE_PU : R/W; bitpos: [29]; default: 1;
+ * RTC_DBOOST force power up
+ */
+
+#define RTC_CNTL_RTC_DBOOST_FORCE_PU (BIT(29))
+#define RTC_CNTL_RTC_DBOOST_FORCE_PU_M (RTC_CNTL_RTC_DBOOST_FORCE_PU_V << RTC_CNTL_RTC_DBOOST_FORCE_PU_S)
+#define RTC_CNTL_RTC_DBOOST_FORCE_PU_V 0x00000001
+#define RTC_CNTL_RTC_DBOOST_FORCE_PU_S 29
+
+/* RTC_CNTL_RTC_DBOOST_FORCE_PD : R/W; bitpos: [28]; default: 0;
+ * RTC_DBOOST force power down
+ */
+
+#define RTC_CNTL_RTC_DBOOST_FORCE_PD (BIT(28))
+#define RTC_CNTL_RTC_DBOOST_FORCE_PD_M (RTC_CNTL_RTC_DBOOST_FORCE_PD_V << RTC_CNTL_RTC_DBOOST_FORCE_PD_S)
+#define RTC_CNTL_RTC_DBOOST_FORCE_PD_V 0x00000001
+#define RTC_CNTL_RTC_DBOOST_FORCE_PD_S 28
+
+/* RTC_CNTL_SCK_DCAP : R/W; bitpos: [21:14]; default: 0;
+ * SCK_DCAP
+ */
+
+#define RTC_CNTL_SCK_DCAP 0x000000ff
+#define RTC_CNTL_SCK_DCAP_M (RTC_CNTL_SCK_DCAP_V << RTC_CNTL_SCK_DCAP_S)
+#define RTC_CNTL_SCK_DCAP_V 0x000000ff
+#define RTC_CNTL_SCK_DCAP_S 14
+
+/* RTC_CNTL_DIG_REG_CAL_EN : R/W; bitpos: [7]; default: 0;
+ * enable dig regulator cali
+ */
+
+#define RTC_CNTL_DIG_REG_CAL_EN (BIT(7))
+#define RTC_CNTL_DIG_REG_CAL_EN_M (RTC_CNTL_DIG_REG_CAL_EN_V << RTC_CNTL_DIG_REG_CAL_EN_S)
+#define RTC_CNTL_DIG_REG_CAL_EN_V 0x00000001
+#define RTC_CNTL_DIG_REG_CAL_EN_S 7
+
+/* RTC_CNTL_RTC_PWC_REG register
+ * configure rtc power
+ */
+
+#define RTC_CNTL_RTC_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88)
+
+/* RTC_CNTL_RTC_PAD_FORCE_HOLD : R/W; bitpos: [21]; default: 0;
+ * rtc pad force hold
+ */
+
+#define RTC_CNTL_RTC_PAD_FORCE_HOLD (BIT(21))
+#define RTC_CNTL_RTC_PAD_FORCE_HOLD_M (RTC_CNTL_RTC_PAD_FORCE_HOLD_V << RTC_CNTL_RTC_PAD_FORCE_HOLD_S)
+#define RTC_CNTL_RTC_PAD_FORCE_HOLD_V 0x00000001
+#define RTC_CNTL_RTC_PAD_FORCE_HOLD_S 21
+
+/* RTC_CNTL_RTC_PD_EN : R/W; bitpos: [20]; default: 0;
+ * enable power down rtc_peri in sleep
+ */
+
+#define RTC_CNTL_RTC_PD_EN (BIT(20))
+#define RTC_CNTL_RTC_PD_EN_M (RTC_CNTL_RTC_PD_EN_V << RTC_CNTL_RTC_PD_EN_S)
+#define RTC_CNTL_RTC_PD_EN_V 0x00000001
+#define RTC_CNTL_RTC_PD_EN_S 20
+
+/* RTC_CNTL_RTC_FORCE_PU : R/W; bitpos: [19]; default: 0;
+ * rtc_peri force power up
+ */
+
+#define RTC_CNTL_RTC_FORCE_PU (BIT(19))
+#define RTC_CNTL_RTC_FORCE_PU_M (RTC_CNTL_RTC_FORCE_PU_V << RTC_CNTL_RTC_FORCE_PU_S)
+#define RTC_CNTL_RTC_FORCE_PU_V 0x00000001
+#define RTC_CNTL_RTC_FORCE_PU_S 19
+
+/* RTC_CNTL_RTC_FORCE_PD : R/W; bitpos: [18]; default: 0;
+ * rtc_peri force power down
+ */
+
+#define RTC_CNTL_RTC_FORCE_PD (BIT(18))
+#define RTC_CNTL_RTC_FORCE_PD_M (RTC_CNTL_RTC_FORCE_PD_V << RTC_CNTL_RTC_FORCE_PD_S)
+#define RTC_CNTL_RTC_FORCE_PD_V 0x00000001
+#define RTC_CNTL_RTC_FORCE_PD_S 18
+
+/* RTC_CNTL_RTC_SLOWMEM_FORCE_LPU : R/W; bitpos: [11]; default: 1;
+ * RTC memory force no PD
+ */
+
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU (BIT(11))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_M (RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_V << RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_S)
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_V 0x00000001
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_S 11
+
+/* RTC_CNTL_RTC_SLOWMEM_FORCE_LPD : R/W; bitpos: [10]; default: 0;
+ * RTC memory force PD
+ */
+
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD (BIT(10))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_M (RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_V << RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_S)
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_V 0x00000001
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_S 10
+
+/* RTC_CNTL_RTC_SLOWMEM_FOLW_CPU : R/W; bitpos: [9]; default: 0;
+ * 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state
+ * machine
+ */
+
+#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU (BIT(9))
+#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_M (RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_V << RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_S)
+#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_V 0x00000001
+#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_S 9
+
+/* RTC_CNTL_RTC_FASTMEM_FORCE_LPU : R/W; bitpos: [8]; default: 1;
+ * Fast RTC memory force no PD
+ */
+
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU (BIT(8))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_M (RTC_CNTL_RTC_FASTMEM_FORCE_LPU_V << RTC_CNTL_RTC_FASTMEM_FORCE_LPU_S)
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_V 0x00000001
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_S 8
+
+/* RTC_CNTL_RTC_FASTMEM_FORCE_LPD : R/W; bitpos: [7]; default: 0;
+ * Fast RTC memory force PD
+ */
+
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD (BIT(7))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_M (RTC_CNTL_RTC_FASTMEM_FORCE_LPD_V << RTC_CNTL_RTC_FASTMEM_FORCE_LPD_S)
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_V 0x00000001
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_S 7
+
+/* RTC_CNTL_RTC_FASTMEM_FOLW_CPU : R/W; bitpos: [6]; default: 0;
+ * 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC
+ * state machine
+ */
+
+#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU (BIT(6))
+#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_M (RTC_CNTL_RTC_FASTMEM_FOLW_CPU_V << RTC_CNTL_RTC_FASTMEM_FOLW_CPU_S)
+#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_V 0x00000001
+#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_S 6
+
+/* RTC_CNTL_RTC_FORCE_NOISO : R/W; bitpos: [5]; default: 1;
+ * rtc_peri force no ISO
+ */
+
+#define RTC_CNTL_RTC_FORCE_NOISO (BIT(5))
+#define RTC_CNTL_RTC_FORCE_NOISO_M (RTC_CNTL_RTC_FORCE_NOISO_V << RTC_CNTL_RTC_FORCE_NOISO_S)
+#define RTC_CNTL_RTC_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_RTC_FORCE_NOISO_S 5
+
+/* RTC_CNTL_RTC_FORCE_ISO : R/W; bitpos: [4]; default: 0;
+ * rtc_peri force ISO
+ */
+
+#define RTC_CNTL_RTC_FORCE_ISO (BIT(4))
+#define RTC_CNTL_RTC_FORCE_ISO_M (RTC_CNTL_RTC_FORCE_ISO_V << RTC_CNTL_RTC_FORCE_ISO_S)
+#define RTC_CNTL_RTC_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_RTC_FORCE_ISO_S 4
+
+/* RTC_CNTL_RTC_SLOWMEM_FORCE_ISO : R/W; bitpos: [3]; default: 0;
+ * RTC memory force ISO
+ */
+
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO (BIT(3))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_M (RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_V << RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_S)
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_S 3
+
+/* RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO : R/W; bitpos: [2]; default: 1;
+ * RTC memory force no ISO
+ */
+
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO (BIT(2))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_M (RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_V << RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_S)
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_S 2
+
+/* RTC_CNTL_RTC_FASTMEM_FORCE_ISO : R/W; bitpos: [1]; default: 0;
+ * Fast RTC memory force ISO
+ */
+
+#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO (BIT(1))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_M (RTC_CNTL_RTC_FASTMEM_FORCE_ISO_V << RTC_CNTL_RTC_FASTMEM_FORCE_ISO_S)
+#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_S 1
+
+/* RTC_CNTL_RTC_FASTMEM_FORCE_NOISO : R/W; bitpos: [0]; default: 1;
+ * Fast RTC memory force no ISO
+ */
+
+#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO (BIT(0))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_M (RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_V << RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_S)
+#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_S 0
+
+/* RTC_CNTL_RTC_REGULATOR_DRV_CTRL_REG register
+ * No public
+ */
+
+#define RTC_CNTL_RTC_REGULATOR_DRV_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x8c)
+
+/* RTC_CNTL_DG_VDD_DRV_B_MONITOR : R/W; bitpos: [27:20]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_DG_VDD_DRV_B_MONITOR 0x000000ff
+#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_M (RTC_CNTL_DG_VDD_DRV_B_MONITOR_V << RTC_CNTL_DG_VDD_DRV_B_MONITOR_S)
+#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_V 0x000000ff
+#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_S 20
+
+/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W; bitpos: [19:12]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000ff
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_M (RTC_CNTL_DG_VDD_DRV_B_SLP_V << RTC_CNTL_DG_VDD_DRV_B_SLP_S)
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0x000000ff
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 12
+
+/* RTC_CNTL_RTC_REGULATOR_DRV_B_SLP : R/W; bitpos: [11:6]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_RTC_REGULATOR_DRV_B_SLP 0x0000003f
+#define RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_M (RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_V << RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_S)
+#define RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_V 0x0000003f
+#define RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_S 6
+
+/* RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR : R/W; bitpos: [5:0]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR 0x0000003f
+#define RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_M (RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_V << RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_S)
+#define RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_V 0x0000003f
+#define RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_S 0
+
+/* RTC_CNTL_DIG_PWC_REG register
+ * configure digital power
+ */
+
+#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x90)
+
+/* RTC_CNTL_DG_WRAP_PD_EN : R/W; bitpos: [31]; default: 0;
+ * enable power down all digital logic
+ */
+
+#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_M (RTC_CNTL_DG_WRAP_PD_EN_V << RTC_CNTL_DG_WRAP_PD_EN_S)
+#define RTC_CNTL_DG_WRAP_PD_EN_V 0x00000001
+#define RTC_CNTL_DG_WRAP_PD_EN_S 31
+
+/* RTC_CNTL_WIFI_PD_EN : R/W; bitpos: [30]; default: 0;
+ * enable power down wifi in sleep
+ */
+
+#define RTC_CNTL_WIFI_PD_EN (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_M (RTC_CNTL_WIFI_PD_EN_V << RTC_CNTL_WIFI_PD_EN_S)
+#define RTC_CNTL_WIFI_PD_EN_V 0x00000001
+#define RTC_CNTL_WIFI_PD_EN_S 30
+
+/* RTC_CNTL_CPU_TOP_PD_EN : R/W; bitpos: [29]; default: 0;
+ * enable power down internal SRAM 4 in sleep
+ */
+
+#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29))
+#define RTC_CNTL_CPU_TOP_PD_EN_M (RTC_CNTL_CPU_TOP_PD_EN_V << RTC_CNTL_CPU_TOP_PD_EN_S)
+#define RTC_CNTL_CPU_TOP_PD_EN_V 0x00000001
+#define RTC_CNTL_CPU_TOP_PD_EN_S 29
+
+/* RTC_CNTL_DG_PERI_PD_EN : R/W; bitpos: [28]; default: 0;
+ * enable power down internal SRAM 3 in sleep
+ */
+
+#define RTC_CNTL_DG_PERI_PD_EN (BIT(28))
+#define RTC_CNTL_DG_PERI_PD_EN_M (RTC_CNTL_DG_PERI_PD_EN_V << RTC_CNTL_DG_PERI_PD_EN_S)
+#define RTC_CNTL_DG_PERI_PD_EN_V 0x00000001
+#define RTC_CNTL_DG_PERI_PD_EN_S 28
+
+/* RTC_CNTL_BT_PD_EN : R/W; bitpos: [27]; default: 0;
+ * enable power down internal SRAM 2 in sleep
+ */
+
+#define RTC_CNTL_BT_PD_EN (BIT(27))
+#define RTC_CNTL_BT_PD_EN_M (RTC_CNTL_BT_PD_EN_V << RTC_CNTL_BT_PD_EN_S)
+#define RTC_CNTL_BT_PD_EN_V 0x00000001
+#define RTC_CNTL_BT_PD_EN_S 27
+
+/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W; bitpos: [22]; default: 1;
+ * digital dcdc force power up
+ */
+
+#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22))
+#define RTC_CNTL_CPU_TOP_FORCE_PU_M (RTC_CNTL_CPU_TOP_FORCE_PU_V << RTC_CNTL_CPU_TOP_FORCE_PU_S)
+#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x00000001
+#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22
+
+/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W; bitpos: [21]; default: 0;
+ * digital dcdc force power down
+ */
+
+#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21))
+#define RTC_CNTL_CPU_TOP_FORCE_PD_M (RTC_CNTL_CPU_TOP_FORCE_PD_V << RTC_CNTL_CPU_TOP_FORCE_PD_S)
+#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x00000001
+#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21
+
+/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W; bitpos: [20]; default: 1;
+ * digital core force power up
+ */
+
+#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_M (RTC_CNTL_DG_WRAP_FORCE_PU_V << RTC_CNTL_DG_WRAP_FORCE_PU_S)
+#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x00000001
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20
+
+/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W; bitpos: [19]; default: 0;
+ * digital core force power down
+ */
+
+#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_M (RTC_CNTL_DG_WRAP_FORCE_PD_V << RTC_CNTL_DG_WRAP_FORCE_PD_S)
+#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x00000001
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19
+
+/* RTC_CNTL_WIFI_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ * wifi force power up
+ */
+
+#define RTC_CNTL_WIFI_FORCE_PU (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_M (RTC_CNTL_WIFI_FORCE_PU_V << RTC_CNTL_WIFI_FORCE_PU_S)
+#define RTC_CNTL_WIFI_FORCE_PU_V 0x00000001
+#define RTC_CNTL_WIFI_FORCE_PU_S 18
+
+/* RTC_CNTL_WIFI_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ * wifi force power down
+ */
+
+#define RTC_CNTL_WIFI_FORCE_PD (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_M (RTC_CNTL_WIFI_FORCE_PD_V << RTC_CNTL_WIFI_FORCE_PD_S)
+#define RTC_CNTL_WIFI_FORCE_PD_V 0x00000001
+#define RTC_CNTL_WIFI_FORCE_PD_S 17
+
+/* RTC_CNTL_DG_PERI_FORCE_PU : R/W; bitpos: [14]; default: 1;
+ * internal SRAM 3 force power up
+ */
+
+#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14))
+#define RTC_CNTL_DG_PERI_FORCE_PU_M (RTC_CNTL_DG_PERI_FORCE_PU_V << RTC_CNTL_DG_PERI_FORCE_PU_S)
+#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x00000001
+#define RTC_CNTL_DG_PERI_FORCE_PU_S 14
+
+/* RTC_CNTL_DG_PERI_FORCE_PD : R/W; bitpos: [13]; default: 0;
+ * internal SRAM 3 force power down
+ */
+
+#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13))
+#define RTC_CNTL_DG_PERI_FORCE_PD_M (RTC_CNTL_DG_PERI_FORCE_PD_V << RTC_CNTL_DG_PERI_FORCE_PD_S)
+#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x00000001
+#define RTC_CNTL_DG_PERI_FORCE_PD_S 13
+
+/* RTC_CNTL_BT_FORCE_PU : R/W; bitpos: [12]; default: 1;
+ * internal SRAM 2 force power up
+ */
+
+#define RTC_CNTL_BT_FORCE_PU (BIT(12))
+#define RTC_CNTL_BT_FORCE_PU_M (RTC_CNTL_BT_FORCE_PU_V << RTC_CNTL_BT_FORCE_PU_S)
+#define RTC_CNTL_BT_FORCE_PU_V 0x00000001
+#define RTC_CNTL_BT_FORCE_PU_S 12
+
+/* RTC_CNTL_BT_FORCE_PD : R/W; bitpos: [11]; default: 0;
+ * internal SRAM 2 force power down
+ */
+
+#define RTC_CNTL_BT_FORCE_PD (BIT(11))
+#define RTC_CNTL_BT_FORCE_PD_M (RTC_CNTL_BT_FORCE_PD_V << RTC_CNTL_BT_FORCE_PD_S)
+#define RTC_CNTL_BT_FORCE_PD_V 0x00000001
+#define RTC_CNTL_BT_FORCE_PD_S 11
+
+/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1;
+ * memories in digital core force no PD in sleep
+ */
+
+#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (RTC_CNTL_LSLP_MEM_FORCE_PU_V << RTC_CNTL_LSLP_MEM_FORCE_PU_S)
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x00000001
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4
+
+/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0;
+ * memories in digital core force PD in sleep
+ */
+
+#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (RTC_CNTL_LSLP_MEM_FORCE_PD_V << RTC_CNTL_LSLP_MEM_FORCE_PD_S)
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x00000001
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3
+
+/* RTC_CNTL_DIG_ISO_REG register
+ * congigure digital power isolation
+ */
+
+#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x94)
+
+/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W; bitpos: [31]; default: 1;
+ * digita core force no ISO
+ */
+
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (RTC_CNTL_DG_WRAP_FORCE_NOISO_V << RTC_CNTL_DG_WRAP_FORCE_NOISO_S)
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31
+
+/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W; bitpos: [30]; default: 0;
+ * digital core force ISO
+ */
+
+#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (RTC_CNTL_DG_WRAP_FORCE_ISO_V << RTC_CNTL_DG_WRAP_FORCE_ISO_S)
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30
+
+/* RTC_CNTL_WIFI_FORCE_NOISO : R/W; bitpos: [29]; default: 1;
+ * wifi force no ISO
+ */
+
+#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_M (RTC_CNTL_WIFI_FORCE_NOISO_V << RTC_CNTL_WIFI_FORCE_NOISO_S)
+#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_WIFI_FORCE_NOISO_S 29
+
+/* RTC_CNTL_WIFI_FORCE_ISO : R/W; bitpos: [28]; default: 0;
+ * wifi force ISO
+ */
+
+#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_M (RTC_CNTL_WIFI_FORCE_ISO_V << RTC_CNTL_WIFI_FORCE_ISO_S)
+#define RTC_CNTL_WIFI_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_WIFI_FORCE_ISO_S 28
+
+/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W; bitpos: [27]; default: 1;
+ * internal SRAM 4 force no ISO
+ */
+
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27))
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (RTC_CNTL_CPU_TOP_FORCE_NOISO_V << RTC_CNTL_CPU_TOP_FORCE_NOISO_S)
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27
+
+/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W; bitpos: [26]; default: 0;
+ * internal SRAM 4 force ISO
+ */
+
+#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26))
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (RTC_CNTL_CPU_TOP_FORCE_ISO_V << RTC_CNTL_CPU_TOP_FORCE_ISO_S)
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26
+
+/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W; bitpos: [25]; default: 1;
+ * internal SRAM 3 force no ISO
+ */
+
+#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25))
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (RTC_CNTL_DG_PERI_FORCE_NOISO_V << RTC_CNTL_DG_PERI_FORCE_NOISO_S)
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25
+
+/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W; bitpos: [24]; default: 0;
+ * internal SRAM 3 force ISO
+ */
+
+#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24))
+#define RTC_CNTL_DG_PERI_FORCE_ISO_M (RTC_CNTL_DG_PERI_FORCE_ISO_V << RTC_CNTL_DG_PERI_FORCE_ISO_S)
+#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24
+
+/* RTC_CNTL_BT_FORCE_NOISO : R/W; bitpos: [23]; default: 1;
+ * internal SRAM 2 force no ISO
+ */
+
+#define RTC_CNTL_BT_FORCE_NOISO (BIT(23))
+#define RTC_CNTL_BT_FORCE_NOISO_M (RTC_CNTL_BT_FORCE_NOISO_V << RTC_CNTL_BT_FORCE_NOISO_S)
+#define RTC_CNTL_BT_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_BT_FORCE_NOISO_S 23
+
+/* RTC_CNTL_BT_FORCE_ISO : R/W; bitpos: [22]; default: 0;
+ * internal SRAM 2 force ISO
+ */
+
+#define RTC_CNTL_BT_FORCE_ISO (BIT(22))
+#define RTC_CNTL_BT_FORCE_ISO_M (RTC_CNTL_BT_FORCE_ISO_V << RTC_CNTL_BT_FORCE_ISO_S)
+#define RTC_CNTL_BT_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_BT_FORCE_ISO_S 22
+
+/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W; bitpos: [15]; default: 0;
+ * digital pad force hold
+ */
+
+#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (RTC_CNTL_DG_PAD_FORCE_HOLD_V << RTC_CNTL_DG_PAD_FORCE_HOLD_S)
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x00000001
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15
+
+/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W; bitpos: [14]; default: 1;
+ * digital pad force un-hold
+ */
+
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (RTC_CNTL_DG_PAD_FORCE_UNHOLD_V << RTC_CNTL_DG_PAD_FORCE_UNHOLD_S)
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x00000001
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14
+
+/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W; bitpos: [13]; default: 0;
+ * digital pad force ISO
+ */
+
+#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_M (RTC_CNTL_DG_PAD_FORCE_ISO_V << RTC_CNTL_DG_PAD_FORCE_ISO_S)
+#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x00000001
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13
+
+/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W; bitpos: [12]; default: 1;
+ * digital pad force no ISO
+ */
+
+#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (RTC_CNTL_DG_PAD_FORCE_NOISO_V << RTC_CNTL_DG_PAD_FORCE_NOISO_S)
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x00000001
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12
+
+/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W; bitpos: [11]; default: 0;
+ * digital pad enable auto-hold
+ */
+
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (RTC_CNTL_DG_PAD_AUTOHOLD_EN_V << RTC_CNTL_DG_PAD_AUTOHOLD_EN_S)
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x00000001
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11
+
+/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO; bitpos: [10]; default: 0;
+ * wtite only register to clear digital pad auto-hold
+ */
+
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V << RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S)
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x00000001
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10
+
+/* RTC_CNTL_DG_PAD_AUTOHOLD : RO; bitpos: [9]; default: 0;
+ * read only register to indicate digital pad auto-hold status
+ */
+
+#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_M (RTC_CNTL_DG_PAD_AUTOHOLD_V << RTC_CNTL_DG_PAD_AUTOHOLD_S)
+#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x00000001
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9
+
+/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W; bitpos: [8]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_M (RTC_CNTL_DIG_ISO_FORCE_ON_V << RTC_CNTL_DIG_ISO_FORCE_ON_S)
+#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x00000001
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8
+
+/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W; bitpos: [7]; default: 1;
+ * No public
+ */
+
+#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (RTC_CNTL_DIG_ISO_FORCE_OFF_V << RTC_CNTL_DIG_ISO_FORCE_OFF_S)
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x00000001
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7
+
+/* RTC_CNTL_RTC_WDTCONFIG0_REG register
+ * configure rtc watch dog
+ */
+
+#define RTC_CNTL_RTC_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x98)
+
+/* RTC_CNTL_WDT_EN : R/W; bitpos: [31]; default: 0;
+ * enable rtc watch dog
+ */
+
+#define RTC_CNTL_WDT_EN (BIT(31))
+#define RTC_CNTL_WDT_EN_M (RTC_CNTL_WDT_EN_V << RTC_CNTL_WDT_EN_S)
+#define RTC_CNTL_WDT_EN_V 0x00000001
+#define RTC_CNTL_WDT_EN_S 31
+
+/* RTC_CNTL_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
+ * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4:
+ * RTC reset stage en
+ */
+
+#define RTC_CNTL_WDT_STG0 0x00000007
+#define RTC_CNTL_WDT_STG0_M (RTC_CNTL_WDT_STG0_V << RTC_CNTL_WDT_STG0_S)
+#define RTC_CNTL_WDT_STG0_V 0x00000007
+#define RTC_CNTL_WDT_STG0_S 28
+
+/* RTC_CNTL_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
+ * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4:
+ * RTC reset stage en
+ */
+
+#define RTC_CNTL_WDT_STG1 0x00000007
+#define RTC_CNTL_WDT_STG1_M (RTC_CNTL_WDT_STG1_V << RTC_CNTL_WDT_STG1_S)
+#define RTC_CNTL_WDT_STG1_V 0x00000007
+#define RTC_CNTL_WDT_STG1_S 25
+
+/* RTC_CNTL_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
+ * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4:
+ * RTC reset stage en
+ */
+
+#define RTC_CNTL_WDT_STG2 0x00000007
+#define RTC_CNTL_WDT_STG2_M (RTC_CNTL_WDT_STG2_V << RTC_CNTL_WDT_STG2_S)
+#define RTC_CNTL_WDT_STG2_V 0x00000007
+#define RTC_CNTL_WDT_STG2_S 22
+
+/* RTC_CNTL_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
+ * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4:
+ * RTC reset stage en
+ */
+
+#define RTC_CNTL_WDT_STG3 0x00000007
+#define RTC_CNTL_WDT_STG3_M (RTC_CNTL_WDT_STG3_V << RTC_CNTL_WDT_STG3_S)
+#define RTC_CNTL_WDT_STG3_V 0x00000007
+#define RTC_CNTL_WDT_STG3_S 19
+
+/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
+ * CPU reset counter length
+ */
+
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M (RTC_CNTL_WDT_CPU_RESET_LENGTH_V << RTC_CNTL_WDT_CPU_RESET_LENGTH_S)
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16
+
+/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
+ * system reset counter length
+ */
+
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M (RTC_CNTL_WDT_SYS_RESET_LENGTH_V << RTC_CNTL_WDT_SYS_RESET_LENGTH_S)
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13
+
+/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
+ * enable WDT in flash boot
+ */
+
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V << RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S)
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x00000001
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12
+
+/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
+ * enable WDT reset PRO CPU
+ */
+
+#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (RTC_CNTL_WDT_PROCPU_RESET_EN_V << RTC_CNTL_WDT_PROCPU_RESET_EN_S)
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x00000001
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11
+
+/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
+ * enable WDT reset APP CPU
+ */
+
+#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (RTC_CNTL_WDT_APPCPU_RESET_EN_V << RTC_CNTL_WDT_APPCPU_RESET_EN_S)
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x00000001
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10
+
+/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
+ * pause WDT in sleep
+ */
+
+#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (RTC_CNTL_WDT_PAUSE_IN_SLP_V << RTC_CNTL_WDT_PAUSE_IN_SLP_S)
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x00000001
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9
+
+/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0;
+ * wdt reset whole chip enable
+ */
+
+#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_M (RTC_CNTL_WDT_CHIP_RESET_EN_V << RTC_CNTL_WDT_CHIP_RESET_EN_S)
+#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x00000001
+#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8
+
+/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20;
+ * chip reset siginal pulse width
+ */
+
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000ff
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M (RTC_CNTL_WDT_CHIP_RESET_WIDTH_V << RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0x000000ff
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0
+
+/* RTC_CNTL_RTC_WDTCONFIG1_REG register
+ * stage0 hold time
+ */
+
+#define RTC_CNTL_RTC_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x9c)
+
+/* RTC_CNTL_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
+ * stage0 hold time
+ */
+
+#define RTC_CNTL_WDT_STG0_HOLD 0xffffffff
+#define RTC_CNTL_WDT_STG0_HOLD_M (RTC_CNTL_WDT_STG0_HOLD_V << RTC_CNTL_WDT_STG0_HOLD_S)
+#define RTC_CNTL_WDT_STG0_HOLD_V 0xffffffff
+#define RTC_CNTL_WDT_STG0_HOLD_S 0
+
+/* RTC_CNTL_RTC_WDTCONFIG2_REG register
+ * stage1 hold time
+ */
+
+#define RTC_CNTL_RTC_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0xa0)
+
+/* RTC_CNTL_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
+ * stage1 hold time
+ */
+
+#define RTC_CNTL_WDT_STG1_HOLD 0xffffffff
+#define RTC_CNTL_WDT_STG1_HOLD_M (RTC_CNTL_WDT_STG1_HOLD_V << RTC_CNTL_WDT_STG1_HOLD_S)
+#define RTC_CNTL_WDT_STG1_HOLD_V 0xffffffff
+#define RTC_CNTL_WDT_STG1_HOLD_S 0
+
+/* RTC_CNTL_RTC_WDTCONFIG3_REG register
+ * stage2 hold time
+ */
+
+#define RTC_CNTL_RTC_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xa4)
+
+/* RTC_CNTL_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
+ * stage2 hold time
+ */
+
+#define RTC_CNTL_WDT_STG2_HOLD 0xffffffff
+#define RTC_CNTL_WDT_STG2_HOLD_M (RTC_CNTL_WDT_STG2_HOLD_V << RTC_CNTL_WDT_STG2_HOLD_S)
+#define RTC_CNTL_WDT_STG2_HOLD_V 0xffffffff
+#define RTC_CNTL_WDT_STG2_HOLD_S 0
+
+/* RTC_CNTL_RTC_WDTCONFIG4_REG register
+ * stage3 hold time
+ */
+
+#define RTC_CNTL_RTC_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xa8)
+
+/* RTC_CNTL_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
+ * stage3 hold time
+ */
+
+#define RTC_CNTL_WDT_STG3_HOLD 0xffffffff
+#define RTC_CNTL_WDT_STG3_HOLD_M (RTC_CNTL_WDT_STG3_HOLD_V << RTC_CNTL_WDT_STG3_HOLD_S)
+#define RTC_CNTL_WDT_STG3_HOLD_V 0xffffffff
+#define RTC_CNTL_WDT_STG3_HOLD_S 0
+
+/* RTC_CNTL_RTC_WDTFEED_REG register
+ * rtc wdt feed
+ */
+
+#define RTC_CNTL_RTC_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xac)
+
+/* RTC_CNTL_RTC_WDT_FEED : WO; bitpos: [31]; default: 0;
+ * rtc wdt feed
+ */
+
+#define RTC_CNTL_RTC_WDT_FEED (BIT(31))
+#define RTC_CNTL_RTC_WDT_FEED_M (RTC_CNTL_RTC_WDT_FEED_V << RTC_CNTL_RTC_WDT_FEED_S)
+#define RTC_CNTL_RTC_WDT_FEED_V 0x00000001
+#define RTC_CNTL_RTC_WDT_FEED_S 31
+
+/* RTC_CNTL_RTC_WDTWPROTECT_REG register
+ * configure rtc watch dog
+ */
+
+#define RTC_CNTL_RTC_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xb0)
+
+/* RTC_CNTL_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
+ * rtc watch dog key
+ */
+
+#define RTC_CNTL_WDT_WKEY 0xffffffff
+#define RTC_CNTL_WDT_WKEY_M (RTC_CNTL_WDT_WKEY_V << RTC_CNTL_WDT_WKEY_S)
+#define RTC_CNTL_WDT_WKEY_V 0xffffffff
+#define RTC_CNTL_WDT_WKEY_S 0
+
+/* RTC_CNTL_RTC_SWD_CONF_REG register
+ * congfigure super watch dog
+ */
+
+#define RTC_CNTL_RTC_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xb4)
+
+/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W; bitpos: [31]; default: 0;
+ * automatically feed swd when int comes
+ */
+
+#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_M (RTC_CNTL_SWD_AUTO_FEED_EN_V << RTC_CNTL_SWD_AUTO_FEED_EN_S)
+#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x00000001
+#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31
+
+/* RTC_CNTL_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
+ * disabel SWD
+ */
+
+#define RTC_CNTL_SWD_DISABLE (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_M (RTC_CNTL_SWD_DISABLE_V << RTC_CNTL_SWD_DISABLE_S)
+#define RTC_CNTL_SWD_DISABLE_V 0x00000001
+#define RTC_CNTL_SWD_DISABLE_S 30
+
+/* RTC_CNTL_SWD_FEED : WO; bitpos: [29]; default: 0;
+ * Sw feed swd
+ */
+
+#define RTC_CNTL_SWD_FEED (BIT(29))
+#define RTC_CNTL_SWD_FEED_M (RTC_CNTL_SWD_FEED_V << RTC_CNTL_SWD_FEED_S)
+#define RTC_CNTL_SWD_FEED_V 0x00000001
+#define RTC_CNTL_SWD_FEED_S 29
+
+/* RTC_CNTL_SWD_RST_FLAG_CLR : WO; bitpos: [28]; default: 0;
+ * reset swd reset flag
+ */
+
+#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_M (RTC_CNTL_SWD_RST_FLAG_CLR_V << RTC_CNTL_SWD_RST_FLAG_CLR_S)
+#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x00000001
+#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28
+
+/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W; bitpos: [27:18]; default: 300;
+ * adjust signal width send to swd
+ */
+
+#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003ff
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_M (RTC_CNTL_SWD_SIGNAL_WIDTH_V << RTC_CNTL_SWD_SIGNAL_WIDTH_S)
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x000003ff
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18
+
+/* RTC_CNTL_SWD_BYPASS_RST : R/W; bitpos: [17]; default: 0;
+ * bypass super watch dog reset
+ */
+
+#define RTC_CNTL_SWD_BYPASS_RST (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_M (RTC_CNTL_SWD_BYPASS_RST_V << RTC_CNTL_SWD_BYPASS_RST_S)
+#define RTC_CNTL_SWD_BYPASS_RST_V 0x00000001
+#define RTC_CNTL_SWD_BYPASS_RST_S 17
+
+/* RTC_CNTL_SWD_FEED_INT : RO; bitpos: [1]; default: 0;
+ * swd interrupt for feeding
+ */
+
+#define RTC_CNTL_SWD_FEED_INT (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_M (RTC_CNTL_SWD_FEED_INT_V << RTC_CNTL_SWD_FEED_INT_S)
+#define RTC_CNTL_SWD_FEED_INT_V 0x00000001
+#define RTC_CNTL_SWD_FEED_INT_S 1
+
+/* RTC_CNTL_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
+ * swd reset flag
+ */
+
+#define RTC_CNTL_SWD_RESET_FLAG (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_M (RTC_CNTL_SWD_RESET_FLAG_V << RTC_CNTL_SWD_RESET_FLAG_S)
+#define RTC_CNTL_SWD_RESET_FLAG_V 0x00000001
+#define RTC_CNTL_SWD_RESET_FLAG_S 0
+
+/* RTC_CNTL_RTC_SWD_WPROTECT_REG register
+ * super watch dog key
+ */
+
+#define RTC_CNTL_RTC_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xb8)
+
+/* RTC_CNTL_SWD_WKEY : R/W; bitpos: [31:0]; default: 2401055018;
+ * super watch dog key
+ */
+
+#define RTC_CNTL_SWD_WKEY 0xffffffff
+#define RTC_CNTL_SWD_WKEY_M (RTC_CNTL_SWD_WKEY_V << RTC_CNTL_SWD_WKEY_S)
+#define RTC_CNTL_SWD_WKEY_V 0xffffffff
+#define RTC_CNTL_SWD_WKEY_S 0
+
+/* RTC_CNTL_RTC_SW_CPU_STALL_REG register
+ * configure cpu stall by sw
+ */
+
+#define RTC_CNTL_RTC_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xbc)
+
+/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W; bitpos: [31:26]; default: 0;
+ * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will
+ * stall APP CPU
+ */
+
+#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003f
+#define RTC_CNTL_SW_STALL_PROCPU_C1_M (RTC_CNTL_SW_STALL_PROCPU_C1_V << RTC_CNTL_SW_STALL_PROCPU_C1_S)
+#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x0000003f
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26
+
+/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W; bitpos: [25:20]; default: 0;
+ * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will
+ * stall APP CPU
+ */
+
+#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003f
+#define RTC_CNTL_SW_STALL_APPCPU_C1_M (RTC_CNTL_SW_STALL_APPCPU_C1_V << RTC_CNTL_SW_STALL_APPCPU_C1_S)
+#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x0000003f
+#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20
+
+/* RTC_CNTL_RTC_STORE4_REG register
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xc0)
+
+/* RTC_CNTL_RTC_SCRATCH4 : R/W; bitpos: [31:0]; default: 0;
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_SCRATCH4 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH4_M (RTC_CNTL_RTC_SCRATCH4_V << RTC_CNTL_RTC_SCRATCH4_S)
+#define RTC_CNTL_RTC_SCRATCH4_V 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH4_S 0
+
+/* RTC_CNTL_RTC_STORE5_REG register
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xc4)
+
+/* RTC_CNTL_RTC_SCRATCH5 : R/W; bitpos: [31:0]; default: 0;
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_SCRATCH5 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH5_M (RTC_CNTL_RTC_SCRATCH5_V << RTC_CNTL_RTC_SCRATCH5_S)
+#define RTC_CNTL_RTC_SCRATCH5_V 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH5_S 0
+
+/* RTC_CNTL_RTC_STORE6_REG register
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xc8)
+
+/* RTC_CNTL_RTC_SCRATCH6 : R/W; bitpos: [31:0]; default: 0;
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_SCRATCH6 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH6_M (RTC_CNTL_RTC_SCRATCH6_V << RTC_CNTL_RTC_SCRATCH6_S)
+#define RTC_CNTL_RTC_SCRATCH6_V 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH6_S 0
+
+/* RTC_CNTL_RTC_STORE7_REG register
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xcc)
+
+/* RTC_CNTL_RTC_SCRATCH7 : R/W; bitpos: [31:0]; default: 0;
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_SCRATCH7 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH7_M (RTC_CNTL_RTC_SCRATCH7_V << RTC_CNTL_RTC_SCRATCH7_S)
+#define RTC_CNTL_RTC_SCRATCH7_V 0xffffffff
+#define RTC_CNTL_RTC_SCRATCH7_S 0
+
+/* RTC_CNTL_RTC_LOW_POWER_ST_REG register
+ * reserved register
+ */
+
+#define RTC_CNTL_RTC_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xd0)
+
+/* RTC_CNTL_RTC_MAIN_STATE : RO; bitpos: [31:28]; default: 0;
+ * rtc main state machine status
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE 0x0000000f
+#define RTC_CNTL_RTC_MAIN_STATE_M (RTC_CNTL_RTC_MAIN_STATE_V << RTC_CNTL_RTC_MAIN_STATE_S)
+#define RTC_CNTL_RTC_MAIN_STATE_V 0x0000000f
+#define RTC_CNTL_RTC_MAIN_STATE_S 28
+
+/* RTC_CNTL_RTC_MAIN_STATE_IN_IDLE : RO; bitpos: [27]; default: 0;
+ * rtc main state machine is in idle state
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE_IN_IDLE (BIT(27))
+#define RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_M (RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_V << RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_S)
+#define RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_S 27
+
+/* RTC_CNTL_RTC_MAIN_STATE_IN_SLP : RO; bitpos: [26]; default: 0;
+ * rtc main state machine is in sleep state
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE_IN_SLP (BIT(26))
+#define RTC_CNTL_RTC_MAIN_STATE_IN_SLP_M (RTC_CNTL_RTC_MAIN_STATE_IN_SLP_V << RTC_CNTL_RTC_MAIN_STATE_IN_SLP_S)
+#define RTC_CNTL_RTC_MAIN_STATE_IN_SLP_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_STATE_IN_SLP_S 26
+
+/* RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL : RO; bitpos: [25]; default: 0;
+ * rtc main state machine is in wait xtal state
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL (BIT(25))
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_M (RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_V << RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_S)
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_S 25
+
+/* RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL : RO; bitpos: [24]; default: 0;
+ * rtc main state machine is in wait pll state
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL (BIT(24))
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_M (RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_V << RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_S)
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_S 24
+
+/* RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M : RO; bitpos: [23]; default: 0;
+ * rtc main state machine is in wait 8m state
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M (BIT(23))
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_M (RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_V << RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_S)
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_S 23
+
+/* RTC_CNTL_RTC_IN_LOW_POWER_STATE : RO; bitpos: [22]; default: 0;
+ * rtc main state machine is in the states of low power
+ */
+
+#define RTC_CNTL_RTC_IN_LOW_POWER_STATE (BIT(22))
+#define RTC_CNTL_RTC_IN_LOW_POWER_STATE_M (RTC_CNTL_RTC_IN_LOW_POWER_STATE_V << RTC_CNTL_RTC_IN_LOW_POWER_STATE_S)
+#define RTC_CNTL_RTC_IN_LOW_POWER_STATE_V 0x00000001
+#define RTC_CNTL_RTC_IN_LOW_POWER_STATE_S 22
+
+/* RTC_CNTL_RTC_IN_WAKEUP_STATE : RO; bitpos: [21]; default: 0;
+ * rtc main state machine is in the states of wakeup process
+ */
+
+#define RTC_CNTL_RTC_IN_WAKEUP_STATE (BIT(21))
+#define RTC_CNTL_RTC_IN_WAKEUP_STATE_M (RTC_CNTL_RTC_IN_WAKEUP_STATE_V << RTC_CNTL_RTC_IN_WAKEUP_STATE_S)
+#define RTC_CNTL_RTC_IN_WAKEUP_STATE_V 0x00000001
+#define RTC_CNTL_RTC_IN_WAKEUP_STATE_S 21
+
+/* RTC_CNTL_RTC_MAIN_STATE_WAIT_END : RO; bitpos: [20]; default: 0;
+ * rtc main state machine has been waited for some cycles
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE_WAIT_END (BIT(20))
+#define RTC_CNTL_RTC_MAIN_STATE_WAIT_END_M (RTC_CNTL_RTC_MAIN_STATE_WAIT_END_V << RTC_CNTL_RTC_MAIN_STATE_WAIT_END_S)
+#define RTC_CNTL_RTC_MAIN_STATE_WAIT_END_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_STATE_WAIT_END_S 20
+
+/* RTC_CNTL_RTC_RDY_FOR_WAKEUP : RO; bitpos: [19]; default: 0;
+ * rtc is ready to receive wake up trigger from wake up source
+ */
+
+#define RTC_CNTL_RTC_RDY_FOR_WAKEUP (BIT(19))
+#define RTC_CNTL_RTC_RDY_FOR_WAKEUP_M (RTC_CNTL_RTC_RDY_FOR_WAKEUP_V << RTC_CNTL_RTC_RDY_FOR_WAKEUP_S)
+#define RTC_CNTL_RTC_RDY_FOR_WAKEUP_V 0x00000001
+#define RTC_CNTL_RTC_RDY_FOR_WAKEUP_S 19
+
+/* RTC_CNTL_RTC_MAIN_STATE_PLL_ON : RO; bitpos: [18]; default: 0;
+ * rtc main state machine is in states that pll should be running
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE_PLL_ON (BIT(18))
+#define RTC_CNTL_RTC_MAIN_STATE_PLL_ON_M (RTC_CNTL_RTC_MAIN_STATE_PLL_ON_V << RTC_CNTL_RTC_MAIN_STATE_PLL_ON_S)
+#define RTC_CNTL_RTC_MAIN_STATE_PLL_ON_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_STATE_PLL_ON_S 18
+
+/* RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO : RO; bitpos: [17]; default: 0;
+ * no use any more
+ */
+
+#define RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO (BIT(17))
+#define RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_M (RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_V << RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_S)
+#define RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_S 17
+
+/* RTC_CNTL_RTC_COCPU_STATE_DONE : RO; bitpos: [16]; default: 0;
+ * ulp/cocpu is done
+ */
+
+#define RTC_CNTL_RTC_COCPU_STATE_DONE (BIT(16))
+#define RTC_CNTL_RTC_COCPU_STATE_DONE_M (RTC_CNTL_RTC_COCPU_STATE_DONE_V << RTC_CNTL_RTC_COCPU_STATE_DONE_S)
+#define RTC_CNTL_RTC_COCPU_STATE_DONE_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_STATE_DONE_S 16
+
+/* RTC_CNTL_RTC_COCPU_STATE_SLP : RO; bitpos: [15]; default: 0;
+ * ulp/cocpu is in sleep state
+ */
+
+#define RTC_CNTL_RTC_COCPU_STATE_SLP (BIT(15))
+#define RTC_CNTL_RTC_COCPU_STATE_SLP_M (RTC_CNTL_RTC_COCPU_STATE_SLP_V << RTC_CNTL_RTC_COCPU_STATE_SLP_S)
+#define RTC_CNTL_RTC_COCPU_STATE_SLP_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_STATE_SLP_S 15
+
+/* RTC_CNTL_RTC_COCPU_STATE_SWITCH : RO; bitpos: [14]; default: 0;
+ * ulp/cocpu is about to working. Switch rtc main state
+ */
+
+#define RTC_CNTL_RTC_COCPU_STATE_SWITCH (BIT(14))
+#define RTC_CNTL_RTC_COCPU_STATE_SWITCH_M (RTC_CNTL_RTC_COCPU_STATE_SWITCH_V << RTC_CNTL_RTC_COCPU_STATE_SWITCH_S)
+#define RTC_CNTL_RTC_COCPU_STATE_SWITCH_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_STATE_SWITCH_S 14
+
+/* RTC_CNTL_RTC_COCPU_STATE_START : RO; bitpos: [13]; default: 0;
+ * ulp/cocpu should start to work
+ */
+
+#define RTC_CNTL_RTC_COCPU_STATE_START (BIT(13))
+#define RTC_CNTL_RTC_COCPU_STATE_START_M (RTC_CNTL_RTC_COCPU_STATE_START_V << RTC_CNTL_RTC_COCPU_STATE_START_S)
+#define RTC_CNTL_RTC_COCPU_STATE_START_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_STATE_START_S 13
+
+/* RTC_CNTL_RTC_TOUCH_STATE_DONE : RO; bitpos: [12]; default: 0;
+ * touch is done
+ */
+
+#define RTC_CNTL_RTC_TOUCH_STATE_DONE (BIT(12))
+#define RTC_CNTL_RTC_TOUCH_STATE_DONE_M (RTC_CNTL_RTC_TOUCH_STATE_DONE_V << RTC_CNTL_RTC_TOUCH_STATE_DONE_S)
+#define RTC_CNTL_RTC_TOUCH_STATE_DONE_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_STATE_DONE_S 12
+
+/* RTC_CNTL_RTC_TOUCH_STATE_SLP : RO; bitpos: [11]; default: 0;
+ * touch is in sleep state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_STATE_SLP (BIT(11))
+#define RTC_CNTL_RTC_TOUCH_STATE_SLP_M (RTC_CNTL_RTC_TOUCH_STATE_SLP_V << RTC_CNTL_RTC_TOUCH_STATE_SLP_S)
+#define RTC_CNTL_RTC_TOUCH_STATE_SLP_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_STATE_SLP_S 11
+
+/* RTC_CNTL_RTC_TOUCH_STATE_SWITCH : RO; bitpos: [10]; default: 0;
+ * touch is about to working. Switch rtc main state
+ */
+
+#define RTC_CNTL_RTC_TOUCH_STATE_SWITCH (BIT(10))
+#define RTC_CNTL_RTC_TOUCH_STATE_SWITCH_M (RTC_CNTL_RTC_TOUCH_STATE_SWITCH_V << RTC_CNTL_RTC_TOUCH_STATE_SWITCH_S)
+#define RTC_CNTL_RTC_TOUCH_STATE_SWITCH_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_STATE_SWITCH_S 10
+
+/* RTC_CNTL_RTC_TOUCH_STATE_START : RO; bitpos: [9]; default: 0;
+ * touch should start to work
+ */
+
+#define RTC_CNTL_RTC_TOUCH_STATE_START (BIT(9))
+#define RTC_CNTL_RTC_TOUCH_STATE_START_M (RTC_CNTL_RTC_TOUCH_STATE_START_V << RTC_CNTL_RTC_TOUCH_STATE_START_S)
+#define RTC_CNTL_RTC_TOUCH_STATE_START_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_STATE_START_S 9
+
+/* RTC_CNTL_XPD_DIG : RO; bitpos: [8]; default: 0;
+ * digital wrap power down
+ */
+
+#define RTC_CNTL_XPD_DIG (BIT(8))
+#define RTC_CNTL_XPD_DIG_M (RTC_CNTL_XPD_DIG_V << RTC_CNTL_XPD_DIG_S)
+#define RTC_CNTL_XPD_DIG_V 0x00000001
+#define RTC_CNTL_XPD_DIG_S 8
+
+/* RTC_CNTL_DIG_ISO : RO; bitpos: [7]; default: 0;
+ * digital wrap iso
+ */
+
+#define RTC_CNTL_DIG_ISO (BIT(7))
+#define RTC_CNTL_DIG_ISO_M (RTC_CNTL_DIG_ISO_V << RTC_CNTL_DIG_ISO_S)
+#define RTC_CNTL_DIG_ISO_V 0x00000001
+#define RTC_CNTL_DIG_ISO_S 7
+
+/* RTC_CNTL_XPD_WIFI : RO; bitpos: [6]; default: 0;
+ * wifi wrap power down
+ */
+
+#define RTC_CNTL_XPD_WIFI (BIT(6))
+#define RTC_CNTL_XPD_WIFI_M (RTC_CNTL_XPD_WIFI_V << RTC_CNTL_XPD_WIFI_S)
+#define RTC_CNTL_XPD_WIFI_V 0x00000001
+#define RTC_CNTL_XPD_WIFI_S 6
+
+/* RTC_CNTL_WIFI_ISO : RO; bitpos: [5]; default: 0;
+ * wifi iso
+ */
+
+#define RTC_CNTL_WIFI_ISO (BIT(5))
+#define RTC_CNTL_WIFI_ISO_M (RTC_CNTL_WIFI_ISO_V << RTC_CNTL_WIFI_ISO_S)
+#define RTC_CNTL_WIFI_ISO_V 0x00000001
+#define RTC_CNTL_WIFI_ISO_S 5
+
+/* RTC_CNTL_XPD_RTC_PERI : RO; bitpos: [4]; default: 0;
+ * rtc peripheral power down
+ */
+
+#define RTC_CNTL_XPD_RTC_PERI (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_M (RTC_CNTL_XPD_RTC_PERI_V << RTC_CNTL_XPD_RTC_PERI_S)
+#define RTC_CNTL_XPD_RTC_PERI_V 0x00000001
+#define RTC_CNTL_XPD_RTC_PERI_S 4
+
+/* RTC_CNTL_RTC_PERI_ISO : RO; bitpos: [3]; default: 0;
+ * rtc peripheral iso
+ */
+
+#define RTC_CNTL_RTC_PERI_ISO (BIT(3))
+#define RTC_CNTL_RTC_PERI_ISO_M (RTC_CNTL_RTC_PERI_ISO_V << RTC_CNTL_RTC_PERI_ISO_S)
+#define RTC_CNTL_RTC_PERI_ISO_V 0x00000001
+#define RTC_CNTL_RTC_PERI_ISO_S 3
+
+/* RTC_CNTL_XPD_DIG_DCDC : RO; bitpos: [2]; default: 0;
+ * External DCDC power down
+ */
+
+#define RTC_CNTL_XPD_DIG_DCDC (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_M (RTC_CNTL_XPD_DIG_DCDC_V << RTC_CNTL_XPD_DIG_DCDC_S)
+#define RTC_CNTL_XPD_DIG_DCDC_V 0x00000001
+#define RTC_CNTL_XPD_DIG_DCDC_S 2
+
+/* RTC_CNTL_XPD_ROM0 : RO; bitpos: [0]; default: 0;
+ * rom0 power down
+ */
+
+#define RTC_CNTL_XPD_ROM0 (BIT(0))
+#define RTC_CNTL_XPD_ROM0_M (RTC_CNTL_XPD_ROM0_V << RTC_CNTL_XPD_ROM0_S)
+#define RTC_CNTL_XPD_ROM0_V 0x00000001
+#define RTC_CNTL_XPD_ROM0_S 0
+
+/* RTC_CNTL_RTC_DIAG0_REG register
+ * No public
+ */
+
+#define RTC_CNTL_RTC_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xd4)
+
+/* RTC_CNTL_RTC_LOW_POWER_DIAG1 : RO; bitpos: [31:0]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_RTC_LOW_POWER_DIAG1 0xffffffff
+#define RTC_CNTL_RTC_LOW_POWER_DIAG1_M (RTC_CNTL_RTC_LOW_POWER_DIAG1_V << RTC_CNTL_RTC_LOW_POWER_DIAG1_S)
+#define RTC_CNTL_RTC_LOW_POWER_DIAG1_V 0xffffffff
+#define RTC_CNTL_RTC_LOW_POWER_DIAG1_S 0
+
+/* RTC_CNTL_RTC_PAD_HOLD_REG register
+ * rtc pad hold configure
+ */
+
+#define RTC_CNTL_RTC_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xd8)
+
+/* RTC_CNTL_RTC_PAD21_HOLD : R/W; bitpos: [21]; default: 0;
+ * hold rtc pad-21
+ */
+
+#define RTC_CNTL_RTC_PAD21_HOLD (BIT(21))
+#define RTC_CNTL_RTC_PAD21_HOLD_M (RTC_CNTL_RTC_PAD21_HOLD_V << RTC_CNTL_RTC_PAD21_HOLD_S)
+#define RTC_CNTL_RTC_PAD21_HOLD_V 0x00000001
+#define RTC_CNTL_RTC_PAD21_HOLD_S 21
+
+/* RTC_CNTL_RTC_PAD20_HOLD : R/W; bitpos: [20]; default: 0;
+ * hold rtc pad-20
+ */
+
+#define RTC_CNTL_RTC_PAD20_HOLD (BIT(20))
+#define RTC_CNTL_RTC_PAD20_HOLD_M (RTC_CNTL_RTC_PAD20_HOLD_V << RTC_CNTL_RTC_PAD20_HOLD_S)
+#define RTC_CNTL_RTC_PAD20_HOLD_V 0x00000001
+#define RTC_CNTL_RTC_PAD20_HOLD_S 20
+
+/* RTC_CNTL_RTC_PAD19_HOLD : R/W; bitpos: [19]; default: 0;
+ * hold rtc pad-19
+ */
+
+#define RTC_CNTL_RTC_PAD19_HOLD (BIT(19))
+#define RTC_CNTL_RTC_PAD19_HOLD_M (RTC_CNTL_RTC_PAD19_HOLD_V << RTC_CNTL_RTC_PAD19_HOLD_S)
+#define RTC_CNTL_RTC_PAD19_HOLD_V 0x00000001
+#define RTC_CNTL_RTC_PAD19_HOLD_S 19
+
+/* RTC_CNTL_PDAC2_HOLD : R/W; bitpos: [18]; default: 0;
+ * hold rtc pad-18
+ */
+
+#define RTC_CNTL_PDAC2_HOLD (BIT(18))
+#define RTC_CNTL_PDAC2_HOLD_M (RTC_CNTL_PDAC2_HOLD_V << RTC_CNTL_PDAC2_HOLD_S)
+#define RTC_CNTL_PDAC2_HOLD_V 0x00000001
+#define RTC_CNTL_PDAC2_HOLD_S 18
+
+/* RTC_CNTL_PDAC1_HOLD : R/W; bitpos: [17]; default: 0;
+ * hold rtc pad-17
+ */
+
+#define RTC_CNTL_PDAC1_HOLD (BIT(17))
+#define RTC_CNTL_PDAC1_HOLD_M (RTC_CNTL_PDAC1_HOLD_V << RTC_CNTL_PDAC1_HOLD_S)
+#define RTC_CNTL_PDAC1_HOLD_V 0x00000001
+#define RTC_CNTL_PDAC1_HOLD_S 17
+
+/* RTC_CNTL_X32N_HOLD : R/W; bitpos: [16]; default: 0;
+ * hold rtc pad-16
+ */
+
+#define RTC_CNTL_X32N_HOLD (BIT(16))
+#define RTC_CNTL_X32N_HOLD_M (RTC_CNTL_X32N_HOLD_V << RTC_CNTL_X32N_HOLD_S)
+#define RTC_CNTL_X32N_HOLD_V 0x00000001
+#define RTC_CNTL_X32N_HOLD_S 16
+
+/* RTC_CNTL_X32P_HOLD : R/W; bitpos: [15]; default: 0;
+ * hold rtc pad-15
+ */
+
+#define RTC_CNTL_X32P_HOLD (BIT(15))
+#define RTC_CNTL_X32P_HOLD_M (RTC_CNTL_X32P_HOLD_V << RTC_CNTL_X32P_HOLD_S)
+#define RTC_CNTL_X32P_HOLD_V 0x00000001
+#define RTC_CNTL_X32P_HOLD_S 15
+
+/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W; bitpos: [14]; default: 0;
+ * hold rtc pad-14
+ */
+
+#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14))
+#define RTC_CNTL_TOUCH_PAD14_HOLD_M (RTC_CNTL_TOUCH_PAD14_HOLD_V << RTC_CNTL_TOUCH_PAD14_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14
+
+/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W; bitpos: [13]; default: 0;
+ * hold rtc pad-13
+ */
+
+#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13))
+#define RTC_CNTL_TOUCH_PAD13_HOLD_M (RTC_CNTL_TOUCH_PAD13_HOLD_V << RTC_CNTL_TOUCH_PAD13_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13
+
+/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W; bitpos: [12]; default: 0;
+ * hold rtc pad-12
+ */
+
+#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12))
+#define RTC_CNTL_TOUCH_PAD12_HOLD_M (RTC_CNTL_TOUCH_PAD12_HOLD_V << RTC_CNTL_TOUCH_PAD12_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12
+
+/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W; bitpos: [11]; default: 0;
+ * hold rtc pad-11
+ */
+
+#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11))
+#define RTC_CNTL_TOUCH_PAD11_HOLD_M (RTC_CNTL_TOUCH_PAD11_HOLD_V << RTC_CNTL_TOUCH_PAD11_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11
+
+/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W; bitpos: [10]; default: 0;
+ * hold rtc pad-10
+ */
+
+#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10))
+#define RTC_CNTL_TOUCH_PAD10_HOLD_M (RTC_CNTL_TOUCH_PAD10_HOLD_V << RTC_CNTL_TOUCH_PAD10_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10
+
+/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W; bitpos: [9]; default: 0;
+ * hold rtc pad-9
+ */
+
+#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9))
+#define RTC_CNTL_TOUCH_PAD9_HOLD_M (RTC_CNTL_TOUCH_PAD9_HOLD_V << RTC_CNTL_TOUCH_PAD9_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9
+
+/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W; bitpos: [8]; default: 0;
+ * hold rtc pad-8
+ */
+
+#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8))
+#define RTC_CNTL_TOUCH_PAD8_HOLD_M (RTC_CNTL_TOUCH_PAD8_HOLD_V << RTC_CNTL_TOUCH_PAD8_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8
+
+/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W; bitpos: [7]; default: 0;
+ * hold rtc pad-7
+ */
+
+#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7))
+#define RTC_CNTL_TOUCH_PAD7_HOLD_M (RTC_CNTL_TOUCH_PAD7_HOLD_V << RTC_CNTL_TOUCH_PAD7_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7
+
+/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W; bitpos: [6]; default: 0;
+ * hold rtc pad-6
+ */
+
+#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6))
+#define RTC_CNTL_TOUCH_PAD6_HOLD_M (RTC_CNTL_TOUCH_PAD6_HOLD_V << RTC_CNTL_TOUCH_PAD6_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6
+
+/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W; bitpos: [5]; default: 0;
+ * hold rtc pad-5
+ */
+
+#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5))
+#define RTC_CNTL_TOUCH_PAD5_HOLD_M (RTC_CNTL_TOUCH_PAD5_HOLD_V << RTC_CNTL_TOUCH_PAD5_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5
+
+/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W; bitpos: [4]; default: 0;
+ * hold rtc pad-4
+ */
+
+#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4))
+#define RTC_CNTL_TOUCH_PAD4_HOLD_M (RTC_CNTL_TOUCH_PAD4_HOLD_V << RTC_CNTL_TOUCH_PAD4_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4
+
+/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W; bitpos: [3]; default: 0;
+ * hold rtc pad-3
+ */
+
+#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3))
+#define RTC_CNTL_TOUCH_PAD3_HOLD_M (RTC_CNTL_TOUCH_PAD3_HOLD_V << RTC_CNTL_TOUCH_PAD3_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3
+
+/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W; bitpos: [2]; default: 0;
+ * hold rtc pad-2
+ */
+
+#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2))
+#define RTC_CNTL_TOUCH_PAD2_HOLD_M (RTC_CNTL_TOUCH_PAD2_HOLD_V << RTC_CNTL_TOUCH_PAD2_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2
+
+/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W; bitpos: [1]; default: 0;
+ * hold rtc pad-1
+ */
+
+#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1))
+#define RTC_CNTL_TOUCH_PAD1_HOLD_M (RTC_CNTL_TOUCH_PAD1_HOLD_V << RTC_CNTL_TOUCH_PAD1_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1
+
+/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W; bitpos: [0]; default: 0;
+ * hold rtc pad0
+ */
+
+#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0))
+#define RTC_CNTL_TOUCH_PAD0_HOLD_M (RTC_CNTL_TOUCH_PAD0_HOLD_V << RTC_CNTL_TOUCH_PAD0_HOLD_S)
+#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x00000001
+#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0
+
+/* RTC_CNTL_DIG_PAD_HOLD_REG register
+ * configure digtal pad hold
+ */
+
+#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xdc)
+
+/* RTC_CNTL_DIG_PAD_HOLD : R/W; bitpos: [31:0]; default: 0;
+ * configure digtal pad hold
+ */
+
+#define RTC_CNTL_DIG_PAD_HOLD 0xffffffff
+#define RTC_CNTL_DIG_PAD_HOLD_M (RTC_CNTL_DIG_PAD_HOLD_V << RTC_CNTL_DIG_PAD_HOLD_S)
+#define RTC_CNTL_DIG_PAD_HOLD_V 0xffffffff
+#define RTC_CNTL_DIG_PAD_HOLD_S 0
+
+/* RTC_CNTL_RTC_EXT_WAKEUP1_REG register
+ * configure ext1 wakeup
+ */
+
+#define RTC_CNTL_RTC_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xe0)
+
+/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO; bitpos: [22]; default: 0;
+ * clear ext wakeup1 status
+ */
+
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V << RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S)
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x00000001
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22
+
+/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W; bitpos: [21:0]; default: 0;
+ * Bitmap to select RTC pads for ext wakeup1
+ */
+
+#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003fffff
+#define RTC_CNTL_EXT_WAKEUP1_SEL_M (RTC_CNTL_EXT_WAKEUP1_SEL_V << RTC_CNTL_EXT_WAKEUP1_SEL_S)
+#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x003fffff
+#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0
+
+/* RTC_CNTL_RTC_EXT_WAKEUP1_STATUS_REG register
+ * check ext wakeup1 status
+ */
+
+#define RTC_CNTL_RTC_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xe4)
+
+/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO; bitpos: [21:0]; default: 0;
+ * ext wakeup1 status
+ */
+
+#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003fffff
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_M (RTC_CNTL_EXT_WAKEUP1_STATUS_V << RTC_CNTL_EXT_WAKEUP1_STATUS_S)
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x003fffff
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0
+
+/* RTC_CNTL_RTC_BROWN_OUT_REG register
+ * congfigure brownout
+ */
+
+#define RTC_CNTL_RTC_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xe8)
+
+/* RTC_CNTL_RTC_BROWN_OUT_DET : RO; bitpos: [31]; default: 0;
+ * get brown out detect
+ */
+
+#define RTC_CNTL_RTC_BROWN_OUT_DET (BIT(31))
+#define RTC_CNTL_RTC_BROWN_OUT_DET_M (RTC_CNTL_RTC_BROWN_OUT_DET_V << RTC_CNTL_RTC_BROWN_OUT_DET_S)
+#define RTC_CNTL_RTC_BROWN_OUT_DET_V 0x00000001
+#define RTC_CNTL_RTC_BROWN_OUT_DET_S 31
+
+/* RTC_CNTL_BROWN_OUT_ENA : R/W; bitpos: [30]; default: 1;
+ * enable brown out
+ */
+
+#define RTC_CNTL_BROWN_OUT_ENA (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_M (RTC_CNTL_BROWN_OUT_ENA_V << RTC_CNTL_BROWN_OUT_ENA_S)
+#define RTC_CNTL_BROWN_OUT_ENA_V 0x00000001
+#define RTC_CNTL_BROWN_OUT_ENA_S 30
+
+/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO; bitpos: [29]; default: 0;
+ * clear brown out counter
+ */
+
+#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (RTC_CNTL_BROWN_OUT_CNT_CLR_V << RTC_CNTL_BROWN_OUT_CNT_CLR_S)
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x00000001
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29
+
+/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W; bitpos: [28]; default: 0;
+ * enable brown out reset en
+ */
+
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (RTC_CNTL_BROWN_OUT_ANA_RST_EN_V << RTC_CNTL_BROWN_OUT_ANA_RST_EN_S)
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x00000001
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28
+
+/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W; bitpos: [27]; default: 0;
+ * 1: 4-pos reset, 0: sys_reset
+ */
+
+#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_M (RTC_CNTL_BROWN_OUT_RST_SEL_V << RTC_CNTL_BROWN_OUT_RST_SEL_S)
+#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x00000001
+#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27
+
+/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W; bitpos: [26]; default: 0;
+ * enable brown out reset
+ */
+
+#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_M (RTC_CNTL_BROWN_OUT_RST_ENA_V << RTC_CNTL_BROWN_OUT_RST_ENA_S)
+#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x00000001
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26
+
+/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W; bitpos: [25:16]; default: 1023;
+ * brown out reset wait cycles
+ */
+
+#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003ff
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_M (RTC_CNTL_BROWN_OUT_RST_WAIT_V << RTC_CNTL_BROWN_OUT_RST_WAIT_S)
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x000003ff
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16
+
+/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W; bitpos: [15]; default: 0;
+ * enable power down RF when brown out happens
+ */
+
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (RTC_CNTL_BROWN_OUT_PD_RF_ENA_V << RTC_CNTL_BROWN_OUT_PD_RF_ENA_S)
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x00000001
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15
+
+/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W; bitpos: [14]; default: 0;
+ * enable close flash when brown out happens
+ */
+
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V << RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S)
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x00000001
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14
+
+/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W; bitpos: [13:4]; default: 1;
+ * brown out interrupt wait cycles
+ */
+
+#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003ff
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_M (RTC_CNTL_BROWN_OUT_INT_WAIT_V << RTC_CNTL_BROWN_OUT_INT_WAIT_S)
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x000003ff
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4
+
+/* RTC_CNTL_RTC_TIME_LOW1_REG register
+ * RTC timer low 32 bits
+ */
+
+#define RTC_CNTL_RTC_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xec)
+
+/* RTC_CNTL_RTC_TIMER_VALUE1_LOW : RO; bitpos: [31:0]; default: 0;
+ * RTC timer low 32 bits
+ */
+
+#define RTC_CNTL_RTC_TIMER_VALUE1_LOW 0xffffffff
+#define RTC_CNTL_RTC_TIMER_VALUE1_LOW_M (RTC_CNTL_RTC_TIMER_VALUE1_LOW_V << RTC_CNTL_RTC_TIMER_VALUE1_LOW_S)
+#define RTC_CNTL_RTC_TIMER_VALUE1_LOW_V 0xffffffff
+#define RTC_CNTL_RTC_TIMER_VALUE1_LOW_S 0
+
+/* RTC_CNTL_RTC_TIME_HIGH1_REG register
+ * RTC timer high 16 bits
+ */
+
+#define RTC_CNTL_RTC_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xf0)
+
+/* RTC_CNTL_RTC_TIMER_VALUE1_HIGH : RO; bitpos: [15:0]; default: 0;
+ * RTC timer high 16 bits
+ */
+
+#define RTC_CNTL_RTC_TIMER_VALUE1_HIGH 0x0000ffff
+#define RTC_CNTL_RTC_TIMER_VALUE1_HIGH_M (RTC_CNTL_RTC_TIMER_VALUE1_HIGH_V << RTC_CNTL_RTC_TIMER_VALUE1_HIGH_S)
+#define RTC_CNTL_RTC_TIMER_VALUE1_HIGH_V 0x0000ffff
+#define RTC_CNTL_RTC_TIMER_VALUE1_HIGH_S 0
+
+/* RTC_CNTL_RTC_XTAL32K_CLK_FACTOR_REG register
+ * xtal 32k watch dog backup clock factor
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xf4)
+
+/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W; bitpos: [31:0]; default: 0;
+ * xtal 32k watch dog backup clock factor
+ */
+
+#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xffffffff
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_M (RTC_CNTL_XTAL32K_CLK_FACTOR_V << RTC_CNTL_XTAL32K_CLK_FACTOR_S)
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xffffffff
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0
+
+/* RTC_CNTL_RTC_XTAL32K_CONF_REG register
+ * configure xtal32k
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xf8)
+
+/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W; bitpos: [31:28]; default: 0;
+ * if restarted xtal32k period is smaller than this, it is regarded as stable
+ */
+
+#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000f
+#define RTC_CNTL_XTAL32K_STABLE_THRES_M (RTC_CNTL_XTAL32K_STABLE_THRES_V << RTC_CNTL_XTAL32K_STABLE_THRES_S)
+#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0x0000000f
+#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28
+
+/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W; bitpos: [27:20]; default: 255;
+ * If no clock detected for this amount of time 32k is regarded as dead
+ */
+
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000ff
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M (RTC_CNTL_XTAL32K_WDT_TIMEOUT_V << RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0x000000ff
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20
+
+/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W; bitpos: [19:4]; default: 0;
+ * cycles to wait to repower on xtal 32k
+ */
+
+#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000ffff
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_M (RTC_CNTL_XTAL32K_RESTART_WAIT_V << RTC_CNTL_XTAL32K_RESTART_WAIT_S)
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0x0000ffff
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4
+
+/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W; bitpos: [3:0]; default: 0;
+ * cycles to wait to return noral xtal 32k
+ */
+
+#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000f
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_M (RTC_CNTL_XTAL32K_RETURN_WAIT_V << RTC_CNTL_XTAL32K_RETURN_WAIT_S)
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0x0000000f
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0
+
+/* RTC_CNTL_RTC_ULP_CP_TIMER_REG register
+ * configure ulp
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xfc)
+
+/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W; bitpos: [31]; default: 0;
+ * ULP-coprocessor timer enable bit
+ */
+
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31))
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (RTC_CNTL_ULP_CP_SLP_TIMER_EN_V << RTC_CNTL_ULP_CP_SLP_TIMER_EN_S)
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x00000001
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31
+
+/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO; bitpos: [30]; default: 0;
+ * ULP-coprocessor wakeup by GPIO state clear
+ */
+
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S)
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x00000001
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30
+
+/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W; bitpos: [29]; default: 0;
+ * ULP-coprocessor wakeup by GPIO enable
+ */
+
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S)
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x00000001
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29
+
+/* RTC_CNTL_ULP_CP_PC_INIT : R/W; bitpos: [10:0]; default: 0;
+ * ULP-coprocessor PC initial address
+ */
+
+#define RTC_CNTL_ULP_CP_PC_INIT 0x000007ff
+#define RTC_CNTL_ULP_CP_PC_INIT_M (RTC_CNTL_ULP_CP_PC_INIT_V << RTC_CNTL_ULP_CP_PC_INIT_S)
+#define RTC_CNTL_ULP_CP_PC_INIT_V 0x000007ff
+#define RTC_CNTL_ULP_CP_PC_INIT_S 0
+
+/* RTC_CNTL_RTC_ULP_CP_CTRL_REG register
+ * configure ulp
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100)
+
+/* RTC_CNTL_ULP_CP_START_TOP : R/W; bitpos: [31]; default: 0;
+ * Write 1 to start ULP-coprocessor
+ */
+
+#define RTC_CNTL_ULP_CP_START_TOP (BIT(31))
+#define RTC_CNTL_ULP_CP_START_TOP_M (RTC_CNTL_ULP_CP_START_TOP_V << RTC_CNTL_ULP_CP_START_TOP_S)
+#define RTC_CNTL_ULP_CP_START_TOP_V 0x00000001
+#define RTC_CNTL_ULP_CP_START_TOP_S 31
+
+/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W; bitpos: [30]; default: 0;
+ * 1: ULP-coprocessor is started by SW
+ */
+
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30))
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (RTC_CNTL_ULP_CP_FORCE_START_TOP_V << RTC_CNTL_ULP_CP_FORCE_START_TOP_S)
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x00000001
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30
+
+/* RTC_CNTL_ULP_CP_RESET : R/W; bitpos: [29]; default: 0;
+ * ulp coprocessor clk software reset
+ */
+
+#define RTC_CNTL_ULP_CP_RESET (BIT(29))
+#define RTC_CNTL_ULP_CP_RESET_M (RTC_CNTL_ULP_CP_RESET_V << RTC_CNTL_ULP_CP_RESET_S)
+#define RTC_CNTL_ULP_CP_RESET_V 0x00000001
+#define RTC_CNTL_ULP_CP_RESET_S 29
+
+/* RTC_CNTL_ULP_CP_CLK_FO : R/W; bitpos: [28]; default: 0;
+ * ulp coprocessor clk force on
+ */
+
+#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28))
+#define RTC_CNTL_ULP_CP_CLK_FO_M (RTC_CNTL_ULP_CP_CLK_FO_V << RTC_CNTL_ULP_CP_CLK_FO_S)
+#define RTC_CNTL_ULP_CP_CLK_FO_V 0x00000001
+#define RTC_CNTL_ULP_CP_CLK_FO_S 28
+
+/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO; bitpos: [22]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22))
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V << RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S)
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x00000001
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22
+
+/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W; bitpos: [21:11]; default: 512;
+ * No public
+ */
+
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007ff
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M (RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V << RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x000007ff
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11
+
+/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W; bitpos: [10:0]; default: 512;
+ * No public
+ */
+
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007ff
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M (RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V << RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x000007ff
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0
+
+/* RTC_CNTL_RTC_COCPU_CTRL_REG register
+ * configure ulp-riscv
+ */
+
+#define RTC_CNTL_RTC_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x104)
+
+/* RTC_CNTL_COCPU_CLKGATE_EN : R/W; bitpos: [27]; default: 0;
+ * open ulp-riscv clk gate
+ */
+
+#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27))
+#define RTC_CNTL_COCPU_CLKGATE_EN_M (RTC_CNTL_COCPU_CLKGATE_EN_V << RTC_CNTL_COCPU_CLKGATE_EN_S)
+#define RTC_CNTL_COCPU_CLKGATE_EN_V 0x00000001
+#define RTC_CNTL_COCPU_CLKGATE_EN_S 27
+
+/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO; bitpos: [26]; default: 0;
+ * trigger cocpu register interrupt
+ */
+
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26))
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (RTC_CNTL_COCPU_SW_INT_TRIGGER_V << RTC_CNTL_COCPU_SW_INT_TRIGGER_S)
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x00000001
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26
+
+/* RTC_CNTL_COCPU_DONE : R/W; bitpos: [25]; default: 0;
+ * done signal used by riscv to control timer.
+ */
+
+#define RTC_CNTL_COCPU_DONE (BIT(25))
+#define RTC_CNTL_COCPU_DONE_M (RTC_CNTL_COCPU_DONE_V << RTC_CNTL_COCPU_DONE_S)
+#define RTC_CNTL_COCPU_DONE_V 0x00000001
+#define RTC_CNTL_COCPU_DONE_S 25
+
+/* RTC_CNTL_COCPU_DONE_FORCE : R/W; bitpos: [24]; default: 0;
+ * 1: select riscv done 0: select ulp done
+ */
+
+#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24))
+#define RTC_CNTL_COCPU_DONE_FORCE_M (RTC_CNTL_COCPU_DONE_FORCE_V << RTC_CNTL_COCPU_DONE_FORCE_S)
+#define RTC_CNTL_COCPU_DONE_FORCE_V 0x00000001
+#define RTC_CNTL_COCPU_DONE_FORCE_S 24
+
+/* RTC_CNTL_COCPU_SEL : R/W; bitpos: [23]; default: 1;
+ * 1: old ULP 0: new riscV
+ */
+
+#define RTC_CNTL_COCPU_SEL (BIT(23))
+#define RTC_CNTL_COCPU_SEL_M (RTC_CNTL_COCPU_SEL_V << RTC_CNTL_COCPU_SEL_S)
+#define RTC_CNTL_COCPU_SEL_V 0x00000001
+#define RTC_CNTL_COCPU_SEL_S 23
+
+/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W; bitpos: [22]; default: 0;
+ * to reset cocpu
+ */
+
+#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22))
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (RTC_CNTL_COCPU_SHUT_RESET_EN_V << RTC_CNTL_COCPU_SHUT_RESET_EN_S)
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x00000001
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22
+
+/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W; bitpos: [21:14]; default: 40;
+ * time from shut cocpu to disable clk
+ */
+
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000ff
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M (RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V << RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0x000000ff
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14
+
+/* RTC_CNTL_COCPU_SHUT : R/W; bitpos: [13]; default: 0;
+ * to shut cocpu
+ */
+
+#define RTC_CNTL_COCPU_SHUT (BIT(13))
+#define RTC_CNTL_COCPU_SHUT_M (RTC_CNTL_COCPU_SHUT_V << RTC_CNTL_COCPU_SHUT_S)
+#define RTC_CNTL_COCPU_SHUT_V 0x00000001
+#define RTC_CNTL_COCPU_SHUT_S 13
+
+/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W; bitpos: [12:7]; default: 16;
+ * time from start cocpu to give start interrupt
+ */
+
+#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003f
+#define RTC_CNTL_COCPU_START_2_INTR_EN_M (RTC_CNTL_COCPU_START_2_INTR_EN_V << RTC_CNTL_COCPU_START_2_INTR_EN_S)
+#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x0000003f
+#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7
+
+/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W; bitpos: [6:1]; default: 8;
+ * time from start cocpu to pull down reset
+ */
+
+#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003f
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_M (RTC_CNTL_COCPU_START_2_RESET_DIS_V << RTC_CNTL_COCPU_START_2_RESET_DIS_S)
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x0000003f
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1
+
+/* RTC_CNTL_COCPU_CLK_FO : R/W; bitpos: [0]; default: 0;
+ * cocpu clk force on
+ */
+
+#define RTC_CNTL_COCPU_CLK_FO (BIT(0))
+#define RTC_CNTL_COCPU_CLK_FO_M (RTC_CNTL_COCPU_CLK_FO_V << RTC_CNTL_COCPU_CLK_FO_S)
+#define RTC_CNTL_COCPU_CLK_FO_V 0x00000001
+#define RTC_CNTL_COCPU_CLK_FO_S 0
+
+/* RTC_CNTL_RTC_TOUCH_CTRL1_REG register
+ * configure touch controller
+ */
+
+#define RTC_CNTL_RTC_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x108)
+
+/* RTC_CNTL_TOUCH_MEAS_NUM : R/W; bitpos: [31:16]; default: 4096;
+ * the meas length (in 8MHz)
+ */
+
+#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000ffff
+#define RTC_CNTL_TOUCH_MEAS_NUM_M (RTC_CNTL_TOUCH_MEAS_NUM_V << RTC_CNTL_TOUCH_MEAS_NUM_S)
+#define RTC_CNTL_TOUCH_MEAS_NUM_V 0x0000ffff
+#define RTC_CNTL_TOUCH_MEAS_NUM_S 16
+
+/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 256;
+ * sleep cycles for timer
+ */
+
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000ffff
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M (RTC_CNTL_TOUCH_SLEEP_CYCLES_V << RTC_CNTL_TOUCH_SLEEP_CYCLES_S)
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0x0000ffff
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0
+
+/* RTC_CNTL_RTC_TOUCH_CTRL2_REG register
+ * configure touch controller
+ */
+
+#define RTC_CNTL_RTC_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x10c)
+
+/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W; bitpos: [31]; default: 0;
+ * touch clock enable
+ */
+
+#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31))
+#define RTC_CNTL_TOUCH_CLKGATE_EN_M (RTC_CNTL_TOUCH_CLKGATE_EN_V << RTC_CNTL_TOUCH_CLKGATE_EN_S)
+#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31
+
+/* RTC_CNTL_TOUCH_CLK_FO : R/W; bitpos: [30]; default: 0;
+ * touch clock force on
+ */
+
+#define RTC_CNTL_TOUCH_CLK_FO (BIT(30))
+#define RTC_CNTL_TOUCH_CLK_FO_M (RTC_CNTL_TOUCH_CLK_FO_V << RTC_CNTL_TOUCH_CLK_FO_S)
+#define RTC_CNTL_TOUCH_CLK_FO_V 0x00000001
+#define RTC_CNTL_TOUCH_CLK_FO_S 30
+
+/* RTC_CNTL_TOUCH_RESET : R/W; bitpos: [29]; default: 0;
+ * reset upgrade touch
+ */
+
+#define RTC_CNTL_TOUCH_RESET (BIT(29))
+#define RTC_CNTL_TOUCH_RESET_M (RTC_CNTL_TOUCH_RESET_V << RTC_CNTL_TOUCH_RESET_S)
+#define RTC_CNTL_TOUCH_RESET_V 0x00000001
+#define RTC_CNTL_TOUCH_RESET_S 29
+
+/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W; bitpos: [28:27]; default: 0;
+ * force touch timer done
+ */
+
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M (RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V << RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x00000003
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27
+
+/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W; bitpos: [26:25]; default: 0;
+ * when a touch pad is active sleep cycle could be divided by this number
+ */
+
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M (RTC_CNTL_TOUCH_SLP_CYC_DIV_V << RTC_CNTL_TOUCH_SLP_CYC_DIV_S)
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x00000003
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25
+
+/* RTC_CNTL_TOUCH_XPD_WAIT : R/W; bitpos: [24:17]; default: 4;
+ * the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
+ */
+
+#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000ff
+#define RTC_CNTL_TOUCH_XPD_WAIT_M (RTC_CNTL_TOUCH_XPD_WAIT_V << RTC_CNTL_TOUCH_XPD_WAIT_S)
+#define RTC_CNTL_TOUCH_XPD_WAIT_V 0x000000ff
+#define RTC_CNTL_TOUCH_XPD_WAIT_S 17
+
+/* RTC_CNTL_TOUCH_START_FORCE : R/W; bitpos: [16]; default: 0;
+ * 1: to start touch fsm by SW
+ */
+
+#define RTC_CNTL_TOUCH_START_FORCE (BIT(16))
+#define RTC_CNTL_TOUCH_START_FORCE_M (RTC_CNTL_TOUCH_START_FORCE_V << RTC_CNTL_TOUCH_START_FORCE_S)
+#define RTC_CNTL_TOUCH_START_FORCE_V 0x00000001
+#define RTC_CNTL_TOUCH_START_FORCE_S 16
+
+/* RTC_CNTL_TOUCH_START_EN : R/W; bitpos: [15]; default: 0;
+ * 1: start touch fsm
+ */
+
+#define RTC_CNTL_TOUCH_START_EN (BIT(15))
+#define RTC_CNTL_TOUCH_START_EN_M (RTC_CNTL_TOUCH_START_EN_V << RTC_CNTL_TOUCH_START_EN_S)
+#define RTC_CNTL_TOUCH_START_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_START_EN_S 15
+
+/* RTC_CNTL_TOUCH_START_FSM_EN : R/W; bitpos: [14]; default: 1;
+ * 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm
+ */
+
+#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14))
+#define RTC_CNTL_TOUCH_START_FSM_EN_M (RTC_CNTL_TOUCH_START_FSM_EN_V << RTC_CNTL_TOUCH_START_FSM_EN_S)
+#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_START_FSM_EN_S 14
+
+/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W; bitpos: [13]; default: 0;
+ * touch timer enable bit
+ */
+
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (RTC_CNTL_TOUCH_SLP_TIMER_EN_V << RTC_CNTL_TOUCH_SLP_TIMER_EN_S)
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13
+
+/* RTC_CNTL_TOUCH_DBIAS : R/W; bitpos: [12]; default: 0;
+ * 1:use self bias 0:use bandgap bias
+ */
+
+#define RTC_CNTL_TOUCH_DBIAS (BIT(12))
+#define RTC_CNTL_TOUCH_DBIAS_M (RTC_CNTL_TOUCH_DBIAS_V << RTC_CNTL_TOUCH_DBIAS_S)
+#define RTC_CNTL_TOUCH_DBIAS_V 0x00000001
+#define RTC_CNTL_TOUCH_DBIAS_S 12
+
+/* RTC_CNTL_TOUCH_REFC : R/W; bitpos: [11:9]; default: 0;
+ * TOUCH pad0 reference cap
+ */
+
+#define RTC_CNTL_TOUCH_REFC 0x00000007
+#define RTC_CNTL_TOUCH_REFC_M (RTC_CNTL_TOUCH_REFC_V << RTC_CNTL_TOUCH_REFC_S)
+#define RTC_CNTL_TOUCH_REFC_V 0x00000007
+#define RTC_CNTL_TOUCH_REFC_S 9
+
+/* RTC_CNTL_TOUCH_XPD_BIAS : R/W; bitpos: [8]; default: 0;
+ * TOUCH_XPD_BIAS
+ */
+
+#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8))
+#define RTC_CNTL_TOUCH_XPD_BIAS_M (RTC_CNTL_TOUCH_XPD_BIAS_V << RTC_CNTL_TOUCH_XPD_BIAS_S)
+#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x00000001
+#define RTC_CNTL_TOUCH_XPD_BIAS_S 8
+
+/* RTC_CNTL_TOUCH_DREFH : R/W; bitpos: [7:6]; default: 3;
+ * TOUCH_DREFH
+ */
+
+#define RTC_CNTL_TOUCH_DREFH 0x00000003
+#define RTC_CNTL_TOUCH_DREFH_M (RTC_CNTL_TOUCH_DREFH_V << RTC_CNTL_TOUCH_DREFH_S)
+#define RTC_CNTL_TOUCH_DREFH_V 0x00000003
+#define RTC_CNTL_TOUCH_DREFH_S 6
+
+/* RTC_CNTL_TOUCH_DREFL : R/W; bitpos: [5:4]; default: 0;
+ * TOUCH_DREFL
+ */
+
+#define RTC_CNTL_TOUCH_DREFL 0x00000003
+#define RTC_CNTL_TOUCH_DREFL_M (RTC_CNTL_TOUCH_DREFL_V << RTC_CNTL_TOUCH_DREFL_S)
+#define RTC_CNTL_TOUCH_DREFL_V 0x00000003
+#define RTC_CNTL_TOUCH_DREFL_S 4
+
+/* RTC_CNTL_TOUCH_DRANGE : R/W; bitpos: [3:2]; default: 3;
+ * TOUCH_DRANGE
+ */
+
+#define RTC_CNTL_TOUCH_DRANGE 0x00000003
+#define RTC_CNTL_TOUCH_DRANGE_M (RTC_CNTL_TOUCH_DRANGE_V << RTC_CNTL_TOUCH_DRANGE_S)
+#define RTC_CNTL_TOUCH_DRANGE_V 0x00000003
+#define RTC_CNTL_TOUCH_DRANGE_S 2
+
+/* RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG register
+ * configure touch controller
+ */
+
+#define RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x110)
+
+/* RTC_CNTL_TOUCH_OUT_RING : R/W; bitpos: [31:28]; default: 15;
+ * select out ring pad
+ */
+
+#define RTC_CNTL_TOUCH_OUT_RING 0x0000000f
+#define RTC_CNTL_TOUCH_OUT_RING_M (RTC_CNTL_TOUCH_OUT_RING_V << RTC_CNTL_TOUCH_OUT_RING_S)
+#define RTC_CNTL_TOUCH_OUT_RING_V 0x0000000f
+#define RTC_CNTL_TOUCH_OUT_RING_S 28
+
+/* RTC_CNTL_TOUCH_BUFDRV : R/W; bitpos: [27:25]; default: 0;
+ * touch7 buffer driver strength
+ */
+
+#define RTC_CNTL_TOUCH_BUFDRV 0x00000007
+#define RTC_CNTL_TOUCH_BUFDRV_M (RTC_CNTL_TOUCH_BUFDRV_V << RTC_CNTL_TOUCH_BUFDRV_S)
+#define RTC_CNTL_TOUCH_BUFDRV_V 0x00000007
+#define RTC_CNTL_TOUCH_BUFDRV_S 25
+
+/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [24:10]; default: 0;
+ * touch scan mode pad enable map
+ */
+
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007fff
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M (RTC_CNTL_TOUCH_SCAN_PAD_MAP_V << RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x00007fff
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10
+
+/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [9]; default: 0;
+ * touch pad14 will be used as shield
+ */
+
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9))
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (RTC_CNTL_TOUCH_SHIELD_PAD_EN_V << RTC_CNTL_TOUCH_SHIELD_PAD_EN_S)
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9
+
+/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [8]; default: 1;
+ * inactive touch pads connect to 1: gnd 0: HighZ
+ */
+
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V << RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S)
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x00000001
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8
+
+/* RTC_CNTL_TOUCH_DENOISE_EN : R/W; bitpos: [2]; default: 0;
+ * touch pad0 will be used to de-noise
+ */
+
+#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2))
+#define RTC_CNTL_TOUCH_DENOISE_EN_M (RTC_CNTL_TOUCH_DENOISE_EN_V << RTC_CNTL_TOUCH_DENOISE_EN_S)
+#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_DENOISE_EN_S 2
+
+/* RTC_CNTL_TOUCH_DENOISE_RES : R/W; bitpos: [1:0]; default: 2;
+ * De-noise resolution: 12/10/8/4 bit
+ */
+
+#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003
+#define RTC_CNTL_TOUCH_DENOISE_RES_M (RTC_CNTL_TOUCH_DENOISE_RES_V << RTC_CNTL_TOUCH_DENOISE_RES_S)
+#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x00000003
+#define RTC_CNTL_TOUCH_DENOISE_RES_S 0
+
+/* RTC_CNTL_RTC_TOUCH_SLP_THRES_REG register
+ * configure touch controller
+ */
+
+#define RTC_CNTL_RTC_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x114)
+
+/* RTC_CNTL_TOUCH_SLP_PAD : R/W; bitpos: [31:27]; default: 15;
+ * configure which pad as slp pad
+ */
+
+#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001f
+#define RTC_CNTL_TOUCH_SLP_PAD_M (RTC_CNTL_TOUCH_SLP_PAD_V << RTC_CNTL_TOUCH_SLP_PAD_S)
+#define RTC_CNTL_TOUCH_SLP_PAD_V 0x0000001f
+#define RTC_CNTL_TOUCH_SLP_PAD_S 27
+
+/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [26]; default: 0;
+ * sleep pad approach function enable
+ */
+
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26))
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (RTC_CNTL_TOUCH_SLP_APPROACH_EN_V << RTC_CNTL_TOUCH_SLP_APPROACH_EN_S)
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26
+
+/* RTC_CNTL_TOUCH_SLP_TH : R/W; bitpos: [21:0]; default: 0;
+ * the threshold for sleep touch pad
+ */
+
+#define RTC_CNTL_TOUCH_SLP_TH 0x003fffff
+#define RTC_CNTL_TOUCH_SLP_TH_M (RTC_CNTL_TOUCH_SLP_TH_V << RTC_CNTL_TOUCH_SLP_TH_S)
+#define RTC_CNTL_TOUCH_SLP_TH_V 0x003fffff
+#define RTC_CNTL_TOUCH_SLP_TH_S 0
+
+/* RTC_CNTL_RTC_TOUCH_APPROACH_REG register
+ * configure touch controller
+ */
+
+#define RTC_CNTL_RTC_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x118)
+
+/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W; bitpos: [31:24]; default: 80;
+ * approach pads total meas times
+ */
+
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000ff
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M (RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V << RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0x000000ff
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24
+
+/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO; bitpos: [23]; default: 0;
+ * clear touch slp channel
+ */
+
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V << RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S)
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x00000001
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23
+
+/* RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG register
+ * configure touch controller
+ */
+
+#define RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x11c)
+
+/* RTC_CNTL_TOUCH_FILTER_EN : R/W; bitpos: [31]; default: 1;
+ * touch filter enable
+ */
+
+#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31))
+#define RTC_CNTL_TOUCH_FILTER_EN_M (RTC_CNTL_TOUCH_FILTER_EN_V << RTC_CNTL_TOUCH_FILTER_EN_S)
+#define RTC_CNTL_TOUCH_FILTER_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_FILTER_EN_S 31
+
+/* RTC_CNTL_TOUCH_FILTER_MODE : R/W; bitpos: [30:28]; default: 1;
+ * 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter
+ */
+
+#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007
+#define RTC_CNTL_TOUCH_FILTER_MODE_M (RTC_CNTL_TOUCH_FILTER_MODE_V << RTC_CNTL_TOUCH_FILTER_MODE_S)
+#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x00000007
+#define RTC_CNTL_TOUCH_FILTER_MODE_S 28
+
+/* RTC_CNTL_TOUCH_DEBOUNCE : R/W; bitpos: [27:25]; default: 3;
+ * debounce counter
+ */
+
+#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007
+#define RTC_CNTL_TOUCH_DEBOUNCE_M (RTC_CNTL_TOUCH_DEBOUNCE_V << RTC_CNTL_TOUCH_DEBOUNCE_S)
+#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x00000007
+#define RTC_CNTL_TOUCH_DEBOUNCE_S 25
+
+/* RTC_CNTL_TOUCH_HYSTERESIS : R/W; bitpos: [24:23]; default: 1;
+ * hysteresis
+ */
+
+#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003
+#define RTC_CNTL_TOUCH_HYSTERESIS_M (RTC_CNTL_TOUCH_HYSTERESIS_V << RTC_CNTL_TOUCH_HYSTERESIS_S)
+#define RTC_CNTL_TOUCH_HYSTERESIS_V 0x00000003
+#define RTC_CNTL_TOUCH_HYSTERESIS_S 23
+
+/* RTC_CNTL_TOUCH_NOISE_THRES : R/W; bitpos: [22:21]; default: 1;
+ * noise thres
+ */
+
+#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003
+#define RTC_CNTL_TOUCH_NOISE_THRES_M (RTC_CNTL_TOUCH_NOISE_THRES_V << RTC_CNTL_TOUCH_NOISE_THRES_S)
+#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x00000003
+#define RTC_CNTL_TOUCH_NOISE_THRES_S 21
+
+/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W; bitpos: [20:19]; default: 1;
+ * neg noise thres
+ */
+
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M (RTC_CNTL_TOUCH_NEG_NOISE_THRES_V << RTC_CNTL_TOUCH_NEG_NOISE_THRES_S)
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x00000003
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19
+
+/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W; bitpos: [18:15]; default: 5;
+ * negative threshold counter limit
+ */
+
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000f
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M (RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V << RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S)
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0x0000000f
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15
+
+/* RTC_CNTL_TOUCH_JITTER_STEP : R/W; bitpos: [14:11]; default: 1;
+ * touch jitter step
+ */
+
+#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000f
+#define RTC_CNTL_TOUCH_JITTER_STEP_M (RTC_CNTL_TOUCH_JITTER_STEP_V << RTC_CNTL_TOUCH_JITTER_STEP_S)
+#define RTC_CNTL_TOUCH_JITTER_STEP_V 0x0000000f
+#define RTC_CNTL_TOUCH_JITTER_STEP_S 11
+
+/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W; bitpos: [10:9]; default: 0;
+ * smooth filter factor
+ */
+
+#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_M (RTC_CNTL_TOUCH_SMOOTH_LVL_V << RTC_CNTL_TOUCH_SMOOTH_LVL_S)
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x00000003
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9
+
+/* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W; bitpos: [8]; default: 0;
+ * bypaas noise thres
+ */
+
+#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8))
+#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V << RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S)
+#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x00000001
+#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8
+
+/* RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES : R/W; bitpos: [7]; default: 0;
+ * bypass neg noise thres
+ */
+
+#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(7))
+#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_M (RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_V << RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_S)
+#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_V 0x00000001
+#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_S 7
+
+/* RTC_CNTL_RTC_USB_CONF_REG register
+ * usb configure
+ */
+
+#define RTC_CNTL_RTC_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x120)
+
+/* RTC_CNTL_SW_HW_USB_PHY_SEL : R/W; bitpos: [20]; default: 0;
+ * reg_sw_hw_usb_phy_sel
+ */
+
+#define RTC_CNTL_SW_HW_USB_PHY_SEL (BIT(20))
+#define RTC_CNTL_SW_HW_USB_PHY_SEL_M (RTC_CNTL_SW_HW_USB_PHY_SEL_V << RTC_CNTL_SW_HW_USB_PHY_SEL_S)
+#define RTC_CNTL_SW_HW_USB_PHY_SEL_V 0x00000001
+#define RTC_CNTL_SW_HW_USB_PHY_SEL_S 20
+
+/* RTC_CNTL_SW_USB_PHY_SEL : R/W; bitpos: [19]; default: 0;
+ * reg_sw_usb_phy_sel
+ */
+
+#define RTC_CNTL_SW_USB_PHY_SEL (BIT(19))
+#define RTC_CNTL_SW_USB_PHY_SEL_M (RTC_CNTL_SW_USB_PHY_SEL_V << RTC_CNTL_SW_USB_PHY_SEL_S)
+#define RTC_CNTL_SW_USB_PHY_SEL_V 0x00000001
+#define RTC_CNTL_SW_USB_PHY_SEL_S 19
+
+/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W; bitpos: [18]; default: 0;
+ * reg_io_mux_reset_disable
+ */
+
+#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (RTC_CNTL_IO_MUX_RESET_DISABLE_V << RTC_CNTL_IO_MUX_RESET_DISABLE_S)
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x00000001
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18
+
+/* RTC_CNTL_USB_RESET_DISABLE : R/W; bitpos: [17]; default: 0;
+ * reg_usb_reset_disable
+ */
+
+#define RTC_CNTL_USB_RESET_DISABLE (BIT(17))
+#define RTC_CNTL_USB_RESET_DISABLE_M (RTC_CNTL_USB_RESET_DISABLE_V << RTC_CNTL_USB_RESET_DISABLE_S)
+#define RTC_CNTL_USB_RESET_DISABLE_V 0x00000001
+#define RTC_CNTL_USB_RESET_DISABLE_S 17
+
+/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W; bitpos: [16]; default: 0;
+ * reg_usb_tx_en_override
+ */
+
+#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16))
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (RTC_CNTL_USB_TX_EN_OVERRIDE_V << RTC_CNTL_USB_TX_EN_OVERRIDE_S)
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x00000001
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16
+
+/* RTC_CNTL_USB_TX_EN : R/W; bitpos: [15]; default: 0;
+ * reg_usb_tx_en
+ */
+
+#define RTC_CNTL_USB_TX_EN (BIT(15))
+#define RTC_CNTL_USB_TX_EN_M (RTC_CNTL_USB_TX_EN_V << RTC_CNTL_USB_TX_EN_S)
+#define RTC_CNTL_USB_TX_EN_V 0x00000001
+#define RTC_CNTL_USB_TX_EN_S 15
+
+/* RTC_CNTL_USB_TXP : R/W; bitpos: [14]; default: 0;
+ * reg_usb_txp
+ */
+
+#define RTC_CNTL_USB_TXP (BIT(14))
+#define RTC_CNTL_USB_TXP_M (RTC_CNTL_USB_TXP_V << RTC_CNTL_USB_TXP_S)
+#define RTC_CNTL_USB_TXP_V 0x00000001
+#define RTC_CNTL_USB_TXP_S 14
+
+/* RTC_CNTL_USB_TXM : R/W; bitpos: [13]; default: 0;
+ * reg_usb_txm
+ */
+
+#define RTC_CNTL_USB_TXM (BIT(13))
+#define RTC_CNTL_USB_TXM_M (RTC_CNTL_USB_TXM_V << RTC_CNTL_USB_TXM_S)
+#define RTC_CNTL_USB_TXM_V 0x00000001
+#define RTC_CNTL_USB_TXM_S 13
+
+/* RTC_CNTL_USB_PAD_ENABLE : R/W; bitpos: [12]; default: 0;
+ * reg_usb_pad_enable
+ */
+
+#define RTC_CNTL_USB_PAD_ENABLE (BIT(12))
+#define RTC_CNTL_USB_PAD_ENABLE_M (RTC_CNTL_USB_PAD_ENABLE_V << RTC_CNTL_USB_PAD_ENABLE_S)
+#define RTC_CNTL_USB_PAD_ENABLE_V 0x00000001
+#define RTC_CNTL_USB_PAD_ENABLE_S 12
+
+/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W; bitpos: [11]; default: 0;
+ * reg_usb_pad_enable_override
+ */
+
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11))
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V << RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S)
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x00000001
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11
+
+/* RTC_CNTL_USB_PULLUP_VALUE : R/W; bitpos: [10]; default: 0;
+ * reg_usb_pullup_value
+ */
+
+#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10))
+#define RTC_CNTL_USB_PULLUP_VALUE_M (RTC_CNTL_USB_PULLUP_VALUE_V << RTC_CNTL_USB_PULLUP_VALUE_S)
+#define RTC_CNTL_USB_PULLUP_VALUE_V 0x00000001
+#define RTC_CNTL_USB_PULLUP_VALUE_S 10
+
+/* RTC_CNTL_USB_DM_PULLDOWN : R/W; bitpos: [9]; default: 0;
+ * reg_usb_dm_pulldown
+ */
+
+#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9))
+#define RTC_CNTL_USB_DM_PULLDOWN_M (RTC_CNTL_USB_DM_PULLDOWN_V << RTC_CNTL_USB_DM_PULLDOWN_S)
+#define RTC_CNTL_USB_DM_PULLDOWN_V 0x00000001
+#define RTC_CNTL_USB_DM_PULLDOWN_S 9
+
+/* RTC_CNTL_USB_DM_PULLUP : R/W; bitpos: [8]; default: 0;
+ * reg_usb_dm_pullup
+ */
+
+#define RTC_CNTL_USB_DM_PULLUP (BIT(8))
+#define RTC_CNTL_USB_DM_PULLUP_M (RTC_CNTL_USB_DM_PULLUP_V << RTC_CNTL_USB_DM_PULLUP_S)
+#define RTC_CNTL_USB_DM_PULLUP_V 0x00000001
+#define RTC_CNTL_USB_DM_PULLUP_S 8
+
+/* RTC_CNTL_USB_DP_PULLDOWN : R/W; bitpos: [7]; default: 0;
+ * reg_usb_dp_pulldown
+ */
+
+#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7))
+#define RTC_CNTL_USB_DP_PULLDOWN_M (RTC_CNTL_USB_DP_PULLDOWN_V << RTC_CNTL_USB_DP_PULLDOWN_S)
+#define RTC_CNTL_USB_DP_PULLDOWN_V 0x00000001
+#define RTC_CNTL_USB_DP_PULLDOWN_S 7
+
+/* RTC_CNTL_USB_DP_PULLUP : R/W; bitpos: [6]; default: 0;
+ * reg_usb_dp_pullup
+ */
+
+#define RTC_CNTL_USB_DP_PULLUP (BIT(6))
+#define RTC_CNTL_USB_DP_PULLUP_M (RTC_CNTL_USB_DP_PULLUP_V << RTC_CNTL_USB_DP_PULLUP_S)
+#define RTC_CNTL_USB_DP_PULLUP_V 0x00000001
+#define RTC_CNTL_USB_DP_PULLUP_S 6
+
+/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W; bitpos: [5]; default: 0;
+ * reg_usb_pad_pull_override
+ */
+
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5))
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (RTC_CNTL_USB_PAD_PULL_OVERRIDE_V << RTC_CNTL_USB_PAD_PULL_OVERRIDE_S)
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x00000001
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5
+
+/* RTC_CNTL_USB_VREF_OVERRIDE : R/W; bitpos: [4]; default: 0;
+ * reg_usb_vref_override
+ */
+
+#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4))
+#define RTC_CNTL_USB_VREF_OVERRIDE_M (RTC_CNTL_USB_VREF_OVERRIDE_V << RTC_CNTL_USB_VREF_OVERRIDE_S)
+#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x00000001
+#define RTC_CNTL_USB_VREF_OVERRIDE_S 4
+
+/* RTC_CNTL_USB_VREFL : R/W; bitpos: [3:2]; default: 0;
+ * reg_usb_vrefl
+ */
+
+#define RTC_CNTL_USB_VREFL 0x00000003
+#define RTC_CNTL_USB_VREFL_M (RTC_CNTL_USB_VREFL_V << RTC_CNTL_USB_VREFL_S)
+#define RTC_CNTL_USB_VREFL_V 0x00000003
+#define RTC_CNTL_USB_VREFL_S 2
+
+/* RTC_CNTL_USB_VREFH : R/W; bitpos: [1:0]; default: 0;
+ * reg_usb_vrefh
+ */
+
+#define RTC_CNTL_USB_VREFH 0x00000003
+#define RTC_CNTL_USB_VREFH_M (RTC_CNTL_USB_VREFH_V << RTC_CNTL_USB_VREFH_S)
+#define RTC_CNTL_USB_VREFH_V 0x00000003
+#define RTC_CNTL_USB_VREFH_S 0
+
+/* RTC_CNTL_RTC_TOUCH_TIMEOUT_CTRL_REG register
+ * configure touch controller
+ */
+
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x124)
+
+/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 1;
+ * enable touch timerout
+ */
+
+#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22))
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (RTC_CNTL_TOUCH_TIMEOUT_EN_V << RTC_CNTL_TOUCH_TIMEOUT_EN_S)
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x00000001
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22
+
+/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:0]; default: 4194303;
+ * configure touch timerout time
+ */
+
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003fffff
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M (RTC_CNTL_TOUCH_TIMEOUT_NUM_V << RTC_CNTL_TOUCH_TIMEOUT_NUM_S)
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x003fffff
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0
+
+/* RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG register
+ * get reject casue
+ */
+
+#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x128)
+
+/* RTC_CNTL_REJECT_CAUSE : RO; bitpos: [17:0]; default: 0;
+ * sleep reject cause
+ */
+
+#define RTC_CNTL_REJECT_CAUSE 0x0003ffff
+#define RTC_CNTL_REJECT_CAUSE_M (RTC_CNTL_REJECT_CAUSE_V << RTC_CNTL_REJECT_CAUSE_S)
+#define RTC_CNTL_REJECT_CAUSE_V 0x0003ffff
+#define RTC_CNTL_REJECT_CAUSE_S 0
+
+/* RTC_CNTL_RTC_OPTION1_REG register
+ * rtc common configure
+ */
+
+#define RTC_CNTL_RTC_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x12c)
+
+/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [0]; default: 0;
+ * force chip entry download boot by sw
+ */
+
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (RTC_CNTL_FORCE_DOWNLOAD_BOOT_V << RTC_CNTL_FORCE_DOWNLOAD_BOOT_S)
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x00000001
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0
+
+/* RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG register
+ * get wakeup cause
+ */
+
+#define RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x130)
+
+/* RTC_CNTL_WAKEUP_CAUSE : RO; bitpos: [16:0]; default: 0;
+ * sleep wakeup cause
+ */
+
+#define RTC_CNTL_WAKEUP_CAUSE 0x0001ffff
+#define RTC_CNTL_WAKEUP_CAUSE_M (RTC_CNTL_WAKEUP_CAUSE_V << RTC_CNTL_WAKEUP_CAUSE_S)
+#define RTC_CNTL_WAKEUP_CAUSE_V 0x0001ffff
+#define RTC_CNTL_WAKEUP_CAUSE_S 0
+
+/* RTC_CNTL_RTC_ULP_CP_TIMER_1_REG register
+ * configure ulp sleep time
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x134)
+
+/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W; bitpos: [31:8]; default: 200;
+ * sleep cycles for ULP-coprocessor timer
+ */
+
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00ffffff
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M (RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V << RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0x00ffffff
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8
+
+/* RTC_CNTL_INT_ENA_RTC_W1TS_REG register
+ * oneset rtc interrupt
+ */
+
+#define RTC_CNTL_INT_ENA_RTC_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x138)
+
+/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO; bitpos: [20];
+ * default: 0;
+ * enbale touch approach_loop done interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20))
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20
+
+/* RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS : WO; bitpos: [19]; default: 0;
+ * enbale gitch det interrupt
+ */
+
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS (BIT(19))
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_M (RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_V << RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_S 19
+
+/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS : WO; bitpos: [18]; default: 0;
+ * enable touch timeout interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18))
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18
+
+/* RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS : WO; bitpos: [17]; default: 0;
+ * enable cocpu trap interrupt
+ */
+
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS (BIT(17))
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_M (RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_V << RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_S 17
+
+/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS : WO; bitpos: [16]; default: 0;
+ * enable xtal32k_dead interrupt
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16))
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_S 16
+
+/* RTC_CNTL_RTC_SWD_INT_ENA_W1TS : WO; bitpos: [15]; default: 0;
+ * enable super watch dog interrupt
+ */
+
+#define RTC_CNTL_RTC_SWD_INT_ENA_W1TS (BIT(15))
+#define RTC_CNTL_RTC_SWD_INT_ENA_W1TS_M (RTC_CNTL_RTC_SWD_INT_ENA_W1TS_V << RTC_CNTL_RTC_SWD_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_SWD_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_SWD_INT_ENA_W1TS_S 15
+
+/* RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS : WO; bitpos: [14]; default: 0;
+ * enable saradc2 interrupt
+ */
+
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS (BIT(14))
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_M (RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_V << RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_S 14
+
+/* RTC_CNTL_RTC_COCPU_INT_ENA_W1TS : WO; bitpos: [13]; default: 0;
+ * enable riscV cocpu interrupt
+ */
+
+#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TS (BIT(13))
+#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_M (RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_V << RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_S 13
+
+/* RTC_CNTL_RTC_TSENS_INT_ENA_W1TS : WO; bitpos: [12]; default: 0;
+ * enable tsens interrupt
+ */
+
+#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TS (BIT(12))
+#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_M (RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_V << RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_S 12
+
+/* RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS : WO; bitpos: [11]; default: 0;
+ * enable saradc1 interrupt
+ */
+
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS (BIT(11))
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_M (RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_V << RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_S 11
+
+/* RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS : WO; bitpos: [10]; default: 0;
+ * enable RTC main timer interrupt
+ */
+
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS (BIT(10))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_M (RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_V << RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_S 10
+
+/* RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS : WO; bitpos: [9]; default: 0;
+ * enable brown out interrupt
+ */
+
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS (BIT(9))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_M (RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_V << RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_S 9
+
+/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS : WO; bitpos: [8]; default: 0;
+ * enable touch inactive interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8))
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_S 8
+
+/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS : WO; bitpos: [7]; default: 0;
+ * enable touch active interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7))
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_S 7
+
+/* RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS : WO; bitpos: [6]; default: 0;
+ * enable touch done interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_S 6
+
+/* RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS : WO; bitpos: [5]; default: 0;
+ * enable ULP-coprocessor interrupt
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS (BIT(5))
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_M (RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_V << RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_S 5
+
+/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO; bitpos: [4]; default: 0;
+ * enable touch scan done interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4))
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4
+
+/* RTC_CNTL_RTC_WDT_INT_ENA_W1TS : WO; bitpos: [3]; default: 0;
+ * enable RTC WDT interrupt
+ */
+
+#define RTC_CNTL_RTC_WDT_INT_ENA_W1TS (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_ENA_W1TS_M (RTC_CNTL_RTC_WDT_INT_ENA_W1TS_V << RTC_CNTL_RTC_WDT_INT_ENA_W1TS_S)
+#define RTC_CNTL_RTC_WDT_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_RTC_WDT_INT_ENA_W1TS_S 3
+
+/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO; bitpos: [2]; default: 0;
+ * enable SDIO idle interrupt
+ */
+
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V << RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S)
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2
+
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO; bitpos: [1]; default: 0;
+ * enable sleep reject interrupt
+ */
+
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V << RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S)
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1
+
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO; bitpos: [0]; default: 0;
+ * enable sleep wakeup interrupt
+ */
+
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S)
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x00000001
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0
+
+/* RTC_CNTL_INT_ENA_RTC_W1TC_REG register
+ * oneset clr rtc interrupt enable
+ */
+
+#define RTC_CNTL_INT_ENA_RTC_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x13c)
+
+/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO; bitpos: [20];
+ * default: 0;
+ * enbale touch approach_loop done interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20))
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20
+
+/* RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC : WO; bitpos: [19]; default: 0;
+ * enbale gitch det interrupt
+ */
+
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC (BIT(19))
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_M (RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_V << RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_S 19
+
+/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC : WO; bitpos: [18]; default: 0;
+ * enable touch timeout interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18))
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18
+
+/* RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC : WO; bitpos: [17]; default: 0;
+ * enable cocpu trap interrupt
+ */
+
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC (BIT(17))
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_M (RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_V << RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_S 17
+
+/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC : WO; bitpos: [16]; default: 0;
+ * enable xtal32k_dead interrupt
+ */
+
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16))
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_S 16
+
+/* RTC_CNTL_RTC_SWD_INT_ENA_W1TC : WO; bitpos: [15]; default: 0;
+ * enable super watch dog interrupt
+ */
+
+#define RTC_CNTL_RTC_SWD_INT_ENA_W1TC (BIT(15))
+#define RTC_CNTL_RTC_SWD_INT_ENA_W1TC_M (RTC_CNTL_RTC_SWD_INT_ENA_W1TC_V << RTC_CNTL_RTC_SWD_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_SWD_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_SWD_INT_ENA_W1TC_S 15
+
+/* RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC : WO; bitpos: [14]; default: 0;
+ * enable saradc2 interrupt
+ */
+
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC (BIT(14))
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_M (RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_V << RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_S 14
+
+/* RTC_CNTL_RTC_COCPU_INT_ENA_W1TC : WO; bitpos: [13]; default: 0;
+ * enable riscV cocpu interrupt
+ */
+
+#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TC (BIT(13))
+#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_M (RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_V << RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_S 13
+
+/* RTC_CNTL_RTC_TSENS_INT_ENA_W1TC : WO; bitpos: [12]; default: 0;
+ * enable tsens interrupt
+ */
+
+#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TC (BIT(12))
+#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_M (RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_V << RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_S 12
+
+/* RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC : WO; bitpos: [11]; default: 0;
+ * enable saradc1 interrupt
+ */
+
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC (BIT(11))
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_M (RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_V << RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_S 11
+
+/* RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC : WO; bitpos: [10]; default: 0;
+ * enable RTC main timer interrupt
+ */
+
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC (BIT(10))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_M (RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_V << RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_S 10
+
+/* RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC : WO; bitpos: [9]; default: 0;
+ * enable brown out interrupt
+ */
+
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC (BIT(9))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_M (RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_V << RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_S 9
+
+/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC : WO; bitpos: [8]; default: 0;
+ * enable touch inactive interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8))
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_S 8
+
+/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC : WO; bitpos: [7]; default: 0;
+ * enable touch active interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7))
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_S 7
+
+/* RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC : WO; bitpos: [6]; default: 0;
+ * enable touch done interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_S 6
+
+/* RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC : WO; bitpos: [5]; default: 0;
+ * enable ULP-coprocessor interrupt
+ */
+
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC (BIT(5))
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_M (RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_V << RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_S 5
+
+/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO; bitpos: [4]; default: 0;
+ * enable touch scan done interrupt
+ */
+
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4))
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4
+
+/* RTC_CNTL_RTC_WDT_INT_ENA_W1TC : WO; bitpos: [3]; default: 0;
+ * enable RTC WDT interrupt
+ */
+
+#define RTC_CNTL_RTC_WDT_INT_ENA_W1TC (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_ENA_W1TC_M (RTC_CNTL_RTC_WDT_INT_ENA_W1TC_V << RTC_CNTL_RTC_WDT_INT_ENA_W1TC_S)
+#define RTC_CNTL_RTC_WDT_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_RTC_WDT_INT_ENA_W1TC_S 3
+
+/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO; bitpos: [2]; default: 0;
+ * enable SDIO idle interrupt
+ */
+
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V << RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S)
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2
+
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO; bitpos: [1]; default: 0;
+ * enable sleep reject interrupt
+ */
+
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V << RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S)
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1
+
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO; bitpos: [0]; default: 0;
+ * enable sleep wakeup interrupt
+ */
+
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S)
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x00000001
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0
+
+/* RTC_CNTL_RETENTION_CTRL_REG register
+ * configure retention
+ */
+
+#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x140)
+
+/* RTC_CNTL_RETENTION_WAIT : R/W; bitpos: [31:25]; default: 20;
+ * wait cycles for rention operation
+ */
+
+#define RTC_CNTL_RETENTION_WAIT 0x0000007f
+#define RTC_CNTL_RETENTION_WAIT_M (RTC_CNTL_RETENTION_WAIT_V << RTC_CNTL_RETENTION_WAIT_S)
+#define RTC_CNTL_RETENTION_WAIT_V 0x0000007f
+#define RTC_CNTL_RETENTION_WAIT_S 25
+
+/* RTC_CNTL_RETENTION_EN : R/W; bitpos: [24]; default: 0;
+ * enable retention
+ */
+
+#define RTC_CNTL_RETENTION_EN (BIT(24))
+#define RTC_CNTL_RETENTION_EN_M (RTC_CNTL_RETENTION_EN_V << RTC_CNTL_RETENTION_EN_S)
+#define RTC_CNTL_RETENTION_EN_V 0x00000001
+#define RTC_CNTL_RETENTION_EN_S 24
+
+/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W; bitpos: [23:20]; default: 3;
+ * wait clk off cycle
+ */
+
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000f
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M (RTC_CNTL_RETENTION_CLKOFF_WAIT_V << RTC_CNTL_RETENTION_CLKOFF_WAIT_S)
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0x0000000f
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 20
+
+/* RTC_CNTL_RETENTION_DONE_WAIT : R/W; bitpos: [19:17]; default: 2;
+ * wait retention done cycle
+ */
+
+#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007
+#define RTC_CNTL_RETENTION_DONE_WAIT_M (RTC_CNTL_RETENTION_DONE_WAIT_V << RTC_CNTL_RETENTION_DONE_WAIT_S)
+#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x00000007
+#define RTC_CNTL_RETENTION_DONE_WAIT_S 17
+
+/* RTC_CNTL_RETENTION_CLK_SEL : R/W; bitpos: [16]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_RETENTION_CLK_SEL (BIT(16))
+#define RTC_CNTL_RETENTION_CLK_SEL_M (RTC_CNTL_RETENTION_CLK_SEL_V << RTC_CNTL_RETENTION_CLK_SEL_S)
+#define RTC_CNTL_RETENTION_CLK_SEL_V 0x00000001
+#define RTC_CNTL_RETENTION_CLK_SEL_S 16
+
+/* RTC_CNTL_RETENTION_TARGET : R/W; bitpos: [15:14]; default: 0;
+ * congfigure retention target cpu and/or tag
+ */
+
+#define RTC_CNTL_RETENTION_TARGET 0x00000003
+#define RTC_CNTL_RETENTION_TARGET_M (RTC_CNTL_RETENTION_TARGET_V << RTC_CNTL_RETENTION_TARGET_S)
+#define RTC_CNTL_RETENTION_TARGET_V 0x00000003
+#define RTC_CNTL_RETENTION_TARGET_S 14
+
+/* RTC_CNTL_RETENTION_TAG_MODE : R/W; bitpos: [13:10]; default: 0;
+ * No public
+ */
+
+#define RTC_CNTL_RETENTION_TAG_MODE 0x0000000f
+#define RTC_CNTL_RETENTION_TAG_MODE_M (RTC_CNTL_RETENTION_TAG_MODE_V << RTC_CNTL_RETENTION_TAG_MODE_S)
+#define RTC_CNTL_RETENTION_TAG_MODE_V 0x0000000f
+#define RTC_CNTL_RETENTION_TAG_MODE_S 10
+
+/* RTC_CNTL_PG_CTRL_REG register
+ * configure power glitch
+ */
+
+#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x144)
+
+/* RTC_CNTL_POWER_GLITCH_EN : R/W; bitpos: [31]; default: 0;
+ * enable power glitch
+ */
+
+#define RTC_CNTL_POWER_GLITCH_EN (BIT(31))
+#define RTC_CNTL_POWER_GLITCH_EN_M (RTC_CNTL_POWER_GLITCH_EN_V << RTC_CNTL_POWER_GLITCH_EN_S)
+#define RTC_CNTL_POWER_GLITCH_EN_V 0x00000001
+#define RTC_CNTL_POWER_GLITCH_EN_S 31
+
+/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W; bitpos: [30]; default: 0;
+ * select use analog fib signal
+ */
+
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30))
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V << RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S)
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x00000001
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30
+
+/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W; bitpos: [29]; default: 0;
+ * force power glitch enable
+ */
+
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (RTC_CNTL_POWER_GLITCH_FORCE_PU_V << RTC_CNTL_POWER_GLITCH_FORCE_PU_S)
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x00000001
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29
+
+/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W; bitpos: [28]; default: 0;
+ * force power glitch disable
+ */
+
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (RTC_CNTL_POWER_GLITCH_FORCE_PD_V << RTC_CNTL_POWER_GLITCH_FORCE_PD_S)
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x00000001
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28
+
+/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W; bitpos: [27:26]; default: 0;
+ * GLITCH_DSENSE
+ */
+
+#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003
+#define RTC_CNTL_POWER_GLITCH_DSENSE_M (RTC_CNTL_POWER_GLITCH_DSENSE_V << RTC_CNTL_POWER_GLITCH_DSENSE_S)
+#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x00000003
+#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26
+
+/* RTC_CNTL_RTC_FIB_SEL_REG register
+ * No public
+ */
+
+#define RTC_CNTL_RTC_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148)
+
+/* RTC_CNTL_RTC_FIB_SEL : R/W; bitpos: [2:0]; default: 7;
+ * No public
+ */
+
+#define RTC_CNTL_RTC_FIB_SEL 0x00000007
+#define RTC_CNTL_RTC_FIB_SEL_M (RTC_CNTL_RTC_FIB_SEL_V << RTC_CNTL_RTC_FIB_SEL_S)
+#define RTC_CNTL_RTC_FIB_SEL_V 0x00000007
+#define RTC_CNTL_RTC_FIB_SEL_S 0
+
+/* RTC_CNTL_TOUCH_DAC_REG register
+ * configure touch dac
+ */
+
+#define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14c)
+
+/* RTC_CNTL_TOUCH_PAD0_DAC : R/W; bitpos: [31:29]; default: 0;
+ * configure touch pad dac0
+ */
+
+#define RTC_CNTL_TOUCH_PAD0_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD0_DAC_M (RTC_CNTL_TOUCH_PAD0_DAC_V << RTC_CNTL_TOUCH_PAD0_DAC_S)
+#define RTC_CNTL_TOUCH_PAD0_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD0_DAC_S 29
+
+/* RTC_CNTL_TOUCH_PAD1_DAC : R/W; bitpos: [28:26]; default: 0;
+ * configure touch pad dac1
+ */
+
+#define RTC_CNTL_TOUCH_PAD1_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD1_DAC_M (RTC_CNTL_TOUCH_PAD1_DAC_V << RTC_CNTL_TOUCH_PAD1_DAC_S)
+#define RTC_CNTL_TOUCH_PAD1_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD1_DAC_S 26
+
+/* RTC_CNTL_TOUCH_PAD2_DAC : R/W; bitpos: [25:23]; default: 0;
+ * configure touch pad dac2
+ */
+
+#define RTC_CNTL_TOUCH_PAD2_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD2_DAC_M (RTC_CNTL_TOUCH_PAD2_DAC_V << RTC_CNTL_TOUCH_PAD2_DAC_S)
+#define RTC_CNTL_TOUCH_PAD2_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD2_DAC_S 23
+
+/* RTC_CNTL_TOUCH_PAD3_DAC : R/W; bitpos: [22:20]; default: 0;
+ * configure touch pad dac3
+ */
+
+#define RTC_CNTL_TOUCH_PAD3_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD3_DAC_M (RTC_CNTL_TOUCH_PAD3_DAC_V << RTC_CNTL_TOUCH_PAD3_DAC_S)
+#define RTC_CNTL_TOUCH_PAD3_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD3_DAC_S 20
+
+/* RTC_CNTL_TOUCH_PAD4_DAC : R/W; bitpos: [19:17]; default: 0;
+ * configure touch pad dac4
+ */
+
+#define RTC_CNTL_TOUCH_PAD4_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD4_DAC_M (RTC_CNTL_TOUCH_PAD4_DAC_V << RTC_CNTL_TOUCH_PAD4_DAC_S)
+#define RTC_CNTL_TOUCH_PAD4_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD4_DAC_S 17
+
+/* RTC_CNTL_TOUCH_PAD5_DAC : R/W; bitpos: [16:14]; default: 0;
+ * configure touch pad dac5
+ */
+
+#define RTC_CNTL_TOUCH_PAD5_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD5_DAC_M (RTC_CNTL_TOUCH_PAD5_DAC_V << RTC_CNTL_TOUCH_PAD5_DAC_S)
+#define RTC_CNTL_TOUCH_PAD5_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD5_DAC_S 14
+
+/* RTC_CNTL_TOUCH_PAD6_DAC : R/W; bitpos: [13:11]; default: 0;
+ * configure touch pad dac6
+ */
+
+#define RTC_CNTL_TOUCH_PAD6_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD6_DAC_M (RTC_CNTL_TOUCH_PAD6_DAC_V << RTC_CNTL_TOUCH_PAD6_DAC_S)
+#define RTC_CNTL_TOUCH_PAD6_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD6_DAC_S 11
+
+/* RTC_CNTL_TOUCH_PAD7_DAC : R/W; bitpos: [10:8]; default: 0;
+ * configure touch pad dac7
+ */
+
+#define RTC_CNTL_TOUCH_PAD7_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD7_DAC_M (RTC_CNTL_TOUCH_PAD7_DAC_V << RTC_CNTL_TOUCH_PAD7_DAC_S)
+#define RTC_CNTL_TOUCH_PAD7_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD7_DAC_S 8
+
+/* RTC_CNTL_TOUCH_PAD8_DAC : R/W; bitpos: [7:5]; default: 0;
+ * configure touch pad dac8
+ */
+
+#define RTC_CNTL_TOUCH_PAD8_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD8_DAC_M (RTC_CNTL_TOUCH_PAD8_DAC_V << RTC_CNTL_TOUCH_PAD8_DAC_S)
+#define RTC_CNTL_TOUCH_PAD8_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD8_DAC_S 5
+
+/* RTC_CNTL_TOUCH_PAD9_DAC : R/W; bitpos: [4:2]; default: 0;
+ * configure touch pad dac9
+ */
+
+#define RTC_CNTL_TOUCH_PAD9_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD9_DAC_M (RTC_CNTL_TOUCH_PAD9_DAC_V << RTC_CNTL_TOUCH_PAD9_DAC_S)
+#define RTC_CNTL_TOUCH_PAD9_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD9_DAC_S 2
+
+/* RTC_CNTL_TOUCH_DAC1_REG register
+ * configure touch dac
+ */
+
+#define RTC_CNTL_TOUCH_DAC1_REG (DR_REG_RTCCNTL_BASE + 0x150)
+
+/* RTC_CNTL_TOUCH_PAD10_DAC : R/W; bitpos: [31:29]; default: 0;
+ * configure touch pad dac10
+ */
+
+#define RTC_CNTL_TOUCH_PAD10_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD10_DAC_M (RTC_CNTL_TOUCH_PAD10_DAC_V << RTC_CNTL_TOUCH_PAD10_DAC_S)
+#define RTC_CNTL_TOUCH_PAD10_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD10_DAC_S 29
+
+/* RTC_CNTL_TOUCH_PAD11_DAC : R/W; bitpos: [28:26]; default: 0;
+ * configure touch pad dac11
+ */
+
+#define RTC_CNTL_TOUCH_PAD11_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD11_DAC_M (RTC_CNTL_TOUCH_PAD11_DAC_V << RTC_CNTL_TOUCH_PAD11_DAC_S)
+#define RTC_CNTL_TOUCH_PAD11_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD11_DAC_S 26
+
+/* RTC_CNTL_TOUCH_PAD12_DAC : R/W; bitpos: [25:23]; default: 0;
+ * configure touch pad dac12
+ */
+
+#define RTC_CNTL_TOUCH_PAD12_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD12_DAC_M (RTC_CNTL_TOUCH_PAD12_DAC_V << RTC_CNTL_TOUCH_PAD12_DAC_S)
+#define RTC_CNTL_TOUCH_PAD12_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD12_DAC_S 23
+
+/* RTC_CNTL_TOUCH_PAD13_DAC : R/W; bitpos: [22:20]; default: 0;
+ * configure touch pad dac13
+ */
+
+#define RTC_CNTL_TOUCH_PAD13_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD13_DAC_M (RTC_CNTL_TOUCH_PAD13_DAC_V << RTC_CNTL_TOUCH_PAD13_DAC_S)
+#define RTC_CNTL_TOUCH_PAD13_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD13_DAC_S 20
+
+/* RTC_CNTL_TOUCH_PAD14_DAC : R/W; bitpos: [19:17]; default: 0;
+ * configure touch pad dac14
+ */
+
+#define RTC_CNTL_TOUCH_PAD14_DAC 0x00000007
+#define RTC_CNTL_TOUCH_PAD14_DAC_M (RTC_CNTL_TOUCH_PAD14_DAC_V << RTC_CNTL_TOUCH_PAD14_DAC_S)
+#define RTC_CNTL_TOUCH_PAD14_DAC_V 0x00000007
+#define RTC_CNTL_TOUCH_PAD14_DAC_S 17
+
+/* RTC_CNTL_RTC_COCPU_DISABLE_REG register
+ * configure ulp diable
+ */
+
+#define RTC_CNTL_RTC_COCPU_DISABLE_REG (DR_REG_RTCCNTL_BASE + 0x154)
+
+/* RTC_CNTL_DISABLE_RTC_CPU : R/W; bitpos: [31]; default: 0;
+ * configure ulp diable
+ */
+
+#define RTC_CNTL_DISABLE_RTC_CPU (BIT(31))
+#define RTC_CNTL_DISABLE_RTC_CPU_M (RTC_CNTL_DISABLE_RTC_CPU_V << RTC_CNTL_DISABLE_RTC_CPU_S)
+#define RTC_CNTL_DISABLE_RTC_CPU_V 0x00000001
+#define RTC_CNTL_DISABLE_RTC_CPU_S 31
+
+/* RTC_CNTL_DATE_REG register
+ * version register
+ */
+
+#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1fc)
+
+/* RTC_CNTL_DATE : R/W; bitpos: [27:0]; default: 34607729;
+ * version register
+ */
+
+#define RTC_CNTL_DATE 0x0fffffff
+#define RTC_CNTL_DATE_M (RTC_CNTL_DATE_V << RTC_CNTL_DATE_S)
+#define RTC_CNTL_DATE_V 0x0fffffff
+#define RTC_CNTL_DATE_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTC_CNTL_H */
Review comment:
```suggestion
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H */
```
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[GitHub] [incubator-nuttx] acassis merged pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
acassis merged pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352
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[GitHub] [incubator-nuttx] gustavonihei commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793629985
##########
File path: arch/xtensa/src/esp32s3/esp32s3_timerisr.c
##########
@@ -0,0 +1,143 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_timerisr.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <time.h>
+
+#include <arch/board/board.h>
+#include <arch/irq.h>
+#include <nuttx/arch.h>
+
+#include "chip.h"
+#include "esp32s3_irq.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_systimer.h"
+#include "xtensa.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP32S3_SYSTIMER_TICKS_PER_SEC (16 * 1000 * 1000)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: systimer_isr
+ *
+ * Description:
+ * The timer ISR will perform a variety of services for various portions
+ * of the systems.
+ *
+ * Input Parameters:
+ * irq - CPU interrupt index.
+ * context - Context data from the ISR.
+ * arg - Opaque pointer to the internal driver state structure.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned on
+ * failure.
+ *
+ ****************************************************************************/
+
+static int systimer_isr(int irq, void *context, void *arg)
+{
+ modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET0_INT_CLR);
+
+ /* Process timer interrupt */
+
+ nxsched_process_timer();
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_timer_initialize
+ *
+ * Description:
+ * This function is called during start-up to initialize the timer
+ * interrupt.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+ uint32_t regval;
+ int cpuint;
+
+ cpuint = esp32s3_setup_irq(0, ESP32S3_PERIPH_SYSTIMER_TARGET0, 1,
+ ESP32S3_CPUINT_LEVEL);
+ DEBUGASSERT(cpuint >= 0);
+
+ /* Attach the timer interrupt. */
+
+ irq_attach(ESP32S3_IRQ_SYSTIMER_TARGET0, (xcpt_t)systimer_isr, NULL);
Review comment:
Agreed. Thanks!
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[GitHub] [incubator-nuttx] pkarashchenko commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793422831
##########
File path: arch/xtensa/src/esp32s3/.gitignore
##########
@@ -0,0 +1 @@
+/esp-nuttx-bootloader
Review comment:
```suggestion
/esp-nuttx-bootloader
```
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[GitHub] [incubator-nuttx] Ouss4 commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
Ouss4 commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793479132
##########
File path: arch/xtensa/src/esp32s3/esp32s3_lowputc.c
##########
@@ -0,0 +1,851 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
Review comment:
There are situations where `cpuint` is tested to verify the validity of an operation, any error code would work for this however, the function that allocates a CPU interrupt returns `ENOMEM` in case of failure, "Out of Memory" here means "Out of CPU Interrupts".
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[GitHub] [incubator-nuttx] gustavonihei commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793521098
##########
File path: arch/xtensa/include/esp32s3/tie.h
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie.h
+ * Compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality. It is customized to this
+ * Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+
+#define XCHAL_CP_NUM 2 /* number of coprocessors */
+#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
Review comment:
Done.
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[GitHub] [incubator-nuttx] gustavonihei commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793635063
##########
File path: arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
##########
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <nuttx/mm/mm.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "hardware/esp32s3_rom_layout.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ * This function will be called to dynamically set aside the heap region.
+ *
+ * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
+ * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ * size of the unprotected, user-space heap.
+ *
+ * If a protected kernel-space heap is provided, the kernel heap must be
+ * allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(void **heap_start, size_t *heap_size)
+{
+ /* These values come from the linker scripts (esp32s3.ld and
+ * esp32s3.template.ld.) Check boards/xtensa/esp32s3.
+ */
+
+ extern uint8_t *_sheap;
+ extern const struct esp32s3_rom_layout_s *ets_rom_layout_p;
Review comment:
I've removed these declarations from here.
`_sheap` is already declared in `xtensa.h` and `ets_rom_layout_p` has been moved to the `esp32s3_rom_layout.h` header.
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[GitHub] [incubator-nuttx] gustavonihei commented on pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#issuecomment-1022755440
Please, ignore the Check failure, the `tie-asm.h` and `tie.h` files come from the Xtensa Overlays. We'd better include them unchanged.
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[GitHub] [incubator-nuttx] gustavonihei commented on a change in pull request #5352: xtensa: Add initial support for ESP32-S3
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on a change in pull request #5352:
URL: https://github.com/apache/incubator-nuttx/pull/5352#discussion_r793717220
##########
File path: boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3.ld
##########
@@ -0,0 +1,269 @@
+/****************************************************************************
+ * boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_flash.ld
+ ****************************************************************************/
+
+/* Default entry point: */
+
+ENTRY(__start);
+
+_diram_i_start = 0x40378000;
+
+SECTIONS
+{
+ /* Send .iram0 code to iram */
+
+ .iram0.vectors :
+ {
+ _iram_start = ABSOLUTE(.);
+
+ /* Vectors go to IRAM. */
+
+ _init_start = ABSOLUTE(.);
+
+ /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+
+ . = 0x0;
+ KEEP (*(.window_vectors.text));
+ . = 0x180;
+ KEEP (*(.xtensa_level2_vector.text));
+ . = 0x1c0;
+ KEEP (*(.xtensa_level3_vector.text));
+ . = 0x200;
+ KEEP (*(.xtensa_level4_vector.text));
+ . = 0x240;
+ KEEP (*(.xtensa_level5_vector.text));
+ . = 0x280;
+ KEEP (*(.debug_exception_vector.text));
+ . = 0x2c0;
+ KEEP (*(.nmi_vector.text));
+ . = 0x300;
+ KEEP (*(.kernel_exception_vector.text));
+ . = 0x340;
+ KEEP (*(.user_exception_vector.text));
+ . = 0x3c0;
+ KEEP (*(.double_exception_vector.text));
+ . = 0x400;
+ *(.*_vector.literal)
+
+ . = ALIGN (16);
+
+ *(.entry.text)
+ *(.init.literal)
+ *(.init)
+ } > iram0_0_seg
+
+ .iram0.text :
+ {
+ /* Code marked as running out of IRAM */
+
+ *(.iram1 .iram1.*)
+
+ /* align + add 16B for CPU dummy speculative instr. fetch */
+
+ . = ALIGN(4) + 16;
+
+ _iram_text = ABSOLUTE(.);
+ } > iram0_0_seg
+
+ .dram0.dummy (NOLOAD) :
+ {
+ /* This section is required to skip .iram0.text area because iram0_0_seg
+ * and dram0_0_seg reflect the same address space on different buses.
+ */
+
+ . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
+ } > dram0_0_seg
+
+ /* Shared RAM */
+
+ .dram0.bss (NOLOAD) :
+ {
+ /* .bss initialized on power-up */
+
+ . = ALIGN (8);
+ _sbss = ABSOLUTE(.);
+
+ *(.bss .bss.*)
+ *(COMMON)
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ *(.dynbss)
+ *(.share.mem)
+ *(.gnu.linkonce.b.*)
+
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .noinit (NOLOAD) :
+ {
+ /* This section contains data that is not initialized during load,
+ * or during the application's initialization sequence.
+ */
+
+ . = ALIGN(4);
+
+ *(.noinit .noinit.*)
+
+ . = ALIGN(4);
+ } > dram0_0_seg
+
+ .dram0.data :
+ {
+ /* .data initialized on power-up in ROMed configurations. */
+
+ _sdata = ABSOLUTE(.);
+ KEEP (*(.data))
+ KEEP (*(.data.*))
+ KEEP (*(.gnu.linkonce.d.*))
+ KEEP (*(.data1))
+ KEEP (*(.sdata))
+ KEEP (*(.sdata.*))
+ KEEP (*(.gnu.linkonce.s.*))
+ KEEP (*(.sdata2))
+ KEEP (*(.sdata2.*))
+ KEEP (*(.gnu.linkonce.s2.*))
+ KEEP (*(.jcr))
+ *(.dram1 .dram1.*)
+
+ _edata = ABSOLUTE(.);
+ . = ALIGN(4);
+
+ /* Heap starts at the end of .data */
+
+ _sheap = ABSOLUTE(.);
+ } > dram0_0_seg
+
+ .flash.text :
+ {
+ _stext = .;
+ *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.fini.literal)
+ *(.fini)
+ *(.gnu.version)
+
+ /* CPU will try to prefetch up to 16 bytes of instructions.
+ * This means that any configuration (e.g. MMU, PMS) must allow
+ * safe access to up to 16 bytes after the last real instruction, add
+ * dummy bytes to ensure this
+ */
+
+ . += 16;
+
+ _etext = .;
+ } > default_code_seg
+
+ .flash_rodata_dummy (NOLOAD) :
+ {
+ /* This dummy section represents the .flash.text section but in default_rodata_seg.
+ * Thus, it must have its alignment and (at least) its size.
+ */
+
+ /* Start at the same alignment constraint than .flash.text */
+
+ . = ALIGN(ALIGNOF(.flash.text));
+
+ /* Create an empty gap as big as .flash.text section */
+
+ . = SIZEOF(.flash.text);
+
+ /* Prepare the alignment of the section above. Few bytes (0x20) must be
+ * added for the mapping header.
+ */
+
+ . = ALIGN(0x10000) + 0x20;
+ _rodata_reserved_start = .;
+ } > default_rodata_seg
+
+ .flash.rodata : ALIGN(0x10)
+ {
+ _srodata = ABSOLUTE(.);
+
+ *(.rodata)
+ *(.rodata.*)
+ *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+ *(.gnu.linkonce.r.*)
+ *(.rodata1)
+ __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+ *(.xt_except_table)
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.gnu.linkonce.e.*)
+ *(.gnu.version_r)
+ *(.eh_frame)
+
+ . = (. + 3) & ~ 3;
Review comment:
Sure, much better this way. Thanks!
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