[nuttx] branch master updated: riscv/riscv_exception.c: Print the EPC value always

[xi...@apache.org]

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xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 9b88f8ea5c riscv/riscv_exception.c: Print the EPC value always
9b88f8ea5c is described below

commit 9b88f8ea5cf1e979b9066a6852b9b1c7c92aa15a
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Mon Jan 23 13:45:43 2023 +0200

    riscv/riscv_exception.c: Print the EPC value always
    
    The value printed by assert() cannot always be trusted to be correct,
    as it relies on the stack / stack pointer not being corrupt.
    
    The CPU register always points to the faulting instruction so print it
    out in the exception handler.
---
 arch/risc-v/src/common/riscv_exception.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/risc-v/src/common/riscv_exception.c b/arch/risc-v/src/common/riscv_exception.c
index 5b28946256..e8c0326b6d 100644
--- a/arch/risc-v/src/common/riscv_exception.c
+++ b/arch/risc-v/src/common/riscv_exception.c
@@ -74,9 +74,10 @@ int riscv_exception(int mcause, void *regs, void *args)
 {
   uintptr_t cause = mcause & RISCV_IRQ_MASK;
 
-  _alert("EXCEPTION: %s. MCAUSE: %" PRIxREG ", MTVAL: %" PRIxREG "\n",
+  _alert("EXCEPTION: %s. MCAUSE: %" PRIxREG ", EPC: %" PRIxREG
+         ", MTVAL: %" PRIxREG "\n",
          mcause > RISCV_MAX_EXCEPTION ? "Unknown" : g_reasons_str[cause],
-         cause, READ_CSR(CSR_TVAL));
+         cause, READ_CSR(CSR_EPC), READ_CSR(CSR_TVAL));
 
   _alert("PANIC!!! Exception = %" PRIxREG "\n", cause);
   up_irq_save();