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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/04/29 13:04:49 UTC
[GitHub] [incubator-nuttx] CV-Bowen opened a new pull request, #6179: tlsr82: first commit of telink tlsr82xx chip port.
CV-Bowen opened a new pull request, #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179
## Summary
tlsr82: first commit of telink tlsr82xx chip port.
[*] tc32 archtecture context switch;
[*] tc32 backtrace;
[*] timer, uart, pwm, gpio, adc driver;
[*] flash, watchdog driver;
[*] uart txdma/rxdma;
[*] spi console driver;
[*] add board bringup and reset;
## Impact
telink tlsr82xx chip
## Testing
local test
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r867373991
##########
boards/arm/tlsr82/tlsr8278adk80d/src/tlsr8278_gpio.c:
##########
@@ -0,0 +1,296 @@
+/****************************************************************************
+ * boards/arm/tlsr82/tlsr8278adk80d/src/tlsr8278_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/clock.h>
+#include <nuttx/wdog.h>
+#include <nuttx/ioexpander/gpio.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "tlsr82_gpio.h"
+#include "tlsr8278adk80d.h"
+
+#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct tlsr82gpio_dev_s
+{
+ struct gpio_dev_s gpio;
+ pin_interrupt_t callback;
+ uint8_t id;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int tlsr82_go_read(FAR struct gpio_dev_s *dev, FAR bool *value);
+static int tlsr82_go_write(FAR struct gpio_dev_s *dev, bool value);
+static int tlsr82_go_attach(FAR struct gpio_dev_s *dev,
+ pin_interrupt_t callback);
+static int tlsr82_go_enable(FAR struct gpio_dev_s *dev, bool enable);
+static int tlsr82_go_setpintype(FAR struct gpio_dev_s *dev,
+ enum gpio_pintype_e pintype);
+static int tlsr82_go_interrupt(int irq, void *context, void *arg);
Review Comment:
Probably do not need `FAR` for this arch in board files as well
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r866621450
##########
arch/arm/src/tlsr82/tc32/tc32_exception.S:
##########
@@ -0,0 +1,234 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82xx/tc32/tc32_exception.S
Review Comment:
If so, should we remove this file.
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r866027503
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,92 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include common/Make.defs
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS += -DMCU_STARTUP_FLASH
+
+# Filter-out unnecessary .S files
+CMN_ASRCS :=
+
+# Filter-out unnecessary .c files
+TLSR82_CSRCS_FILTER := arm_backtrace_fp.c arm_backtrace_thumb.c arm_hostfs.c
+TLSR82_CSRCS_FILTER += arm_etherstub.c arm_udelay.c arm_semi_syslog.c
+TLSR82_CSRCS_FILTER += arm_fullcontextrestore.c arm_saveusercontext.c
+TLSR82_CSRCS_FILTER += arm_switchcontext.c arm_vfork.c
Review Comment:
don't need filter out arm_etherstub.c and arm_udelay.c since PR https://github.com/apache/incubator-nuttx/pull/6208.
and arm_hostfs.c, arm_semi_syslog.c and arm_vfork.c.
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,92 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include common/Make.defs
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS += -DMCU_STARTUP_FLASH
+
+# Filter-out unnecessary .S files
+CMN_ASRCS :=
+
+# Filter-out unnecessary .c files
+TLSR82_CSRCS_FILTER := arm_backtrace_fp.c arm_backtrace_thumb.c arm_hostfs.c
+TLSR82_CSRCS_FILTER += arm_etherstub.c arm_udelay.c arm_semi_syslog.c
+TLSR82_CSRCS_FILTER += arm_fullcontextrestore.c arm_saveusercontext.c
+TLSR82_CSRCS_FILTER += arm_switchcontext.c arm_vfork.c
+CMN_CSRCS := $(filter-out $(TLSR82_CSRCS_FILTER), $(CMN_CSRCS))
+
+# Common files in arch/arm/armv6-m
+CMN_CSRCS += arm_sigdeliver.c
+
+# Chip arch related files in arch/arm/tlsr82/tc32
+CHIP_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
+
+CHIP_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
+CHIP_CSRCS += tc32_syscall.c tc32_udelay.c
+
+ifeq ($(CONFIG_SCHED_BACKTRACE),y)
+ CHIP_CSRCS += tc32_backtrace.c
+endif
Review Comment:
it's better to move tc32 specific to arch/arm/src/tlsr82/tc32/Make.defs and include arm/common/Make.defs there.
##########
arch/arm/src/tlsr82/common/div_mod.S:
##########
@@ -0,0 +1,345 @@
+/********************************************************************************************************
+ * @file div_mod.S
Review Comment:
why not move to tc32 folder?
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r865607689
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
Review Comment:
I'm not sure if that can be used due to
```
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CHIP_CSRCS += tc32_backtrace.c
endif
```
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[GitHub] [incubator-nuttx] CV-Bowen commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r867427704
##########
boards/arm/tlsr82/tlsr8278adk80d/src/tlsr8278_gpio.c:
##########
@@ -0,0 +1,296 @@
+/****************************************************************************
+ * boards/arm/tlsr82/tlsr8278adk80d/src/tlsr8278_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/clock.h>
+#include <nuttx/wdog.h>
+#include <nuttx/ioexpander/gpio.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "tlsr82_gpio.h"
+#include "tlsr8278adk80d.h"
+
+#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct tlsr82gpio_dev_s
+{
+ struct gpio_dev_s gpio;
+ pin_interrupt_t callback;
+ uint8_t id;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int tlsr82_go_read(FAR struct gpio_dev_s *dev, FAR bool *value);
+static int tlsr82_go_write(FAR struct gpio_dev_s *dev, bool value);
+static int tlsr82_go_attach(FAR struct gpio_dev_s *dev,
+ pin_interrupt_t callback);
+static int tlsr82_go_enable(FAR struct gpio_dev_s *dev, bool enable);
+static int tlsr82_go_setpintype(FAR struct gpio_dev_s *dev,
+ enum gpio_pintype_e pintype);
+static int tlsr82_go_interrupt(int irq, void *context, void *arg);
Review Comment:
Done.
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[GitHub] [incubator-nuttx] CV-Bowen commented on pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#issuecomment-1119349285
> Maybe we can just add a license header and `#ifndef` wrap into `arch/arm/include/tlsr82/chip.h` instead of committing an empty file?
Done
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[GitHub] [incubator-nuttx] CV-Bowen commented on pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#issuecomment-1120115014
Done, i format file cstartup_falsh.S and sync the Toolchain.defs with armv6-m. @pkarashchenko
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[GitHub] [incubator-nuttx] CV-Bowen commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r867291154
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,567 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/irq.h>
+
+#define SRAM_SIZE_32K_EN 0/*defaut sram size=64k*/
+
+#define FLL_STK_EN 1
+#define ZERO_IC_TAG_EN 1
+#define IC_TAG_CACEH_ADDR_EQU_EN 0
+#define FLASH_WAKEUP_EN 1
+#define COPY_DATA_EN 1
+#define MULTI_ADDRESS_START 1
+#define MOVE_BIN_CODE_EN 0
+
+#ifndef __LOAD_RAM_SIZE__
+#define __LOAD_RAM_SIZE__ 0xc
+#endif
+
+#ifndef __IRQ_STK_SIZE__
+#define __IRQ_STK_SIZE__ CONFIG_ARCH_INTERRUPTSTACK
+#if CONFIG_ARCH_INTERRUPTSTACK <= 128
+# error "Interrupt Stack must be larger than 128"
+#endif
+#endif
+ .code 16
+@********************************************************************************************************
+@ MACROS AND DEFINIITIONS
+@********************************************************************************************************
+
+ @ Mode, correspords to bits 0-5 in CPSR
+ .equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
+ .equ IRQ_MODE, 0x12 @ Interrupt Request mode
+ .equ SVC_MODE, 0x13 @ Supervisor mode
+ .equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
+ .equ __LOAD_FLASH, 1
+ .equ __LOAD_DUT, 0
+ .equ __LOAD_RAM, 0
+@********************************************************************************************************
+@ TC32 EXCEPTION VECTORS
+@********************************************************************************************************
+
+ .section .vectors,"ax"
+ .global __reset
+ .global __irq
+ .global __start
+ .global __LOAD_RAM
+ .global __LOAD_DUT
+ .global __LOAD_FLASH
+
+ .extern g_current_regs
+
+__start: @ MUST, referenced by boot.link
+
+ .extern irq_handler
+
+ .extern firmwareVersion
+
+ .extern _ramcode_size_div_16_
+ .extern _ramcode_size_div_256_
+ .extern _ramcode_size_div_16_align_256_
+ .extern _ramcode_size_align_256_
+ .extern _ictag_start_
+ .extern _ictag_end_
+ .extern tl_multi_addr_L
+ .extern tl_multi_addr_H
+ .org 0x0
+ tj __reset
+@ .word (firmwareVersion)
+ .org 0x8
+ .word (0x544c4e4b)
+#if MOVE_BIN_CODE_EN
+ .word (0x00880000 + _bin_size_div_16)
+#else
+ .word (0x00880000 + _ramcode_size_div_16_align_256_)
+#endif
+
+ .org 0x10
+ tj __irq
+ .org 0x18
+ .word (_bin_size_)
+ .extern __tc32_start
+
+ .org 0x20
+
+__reset:
+
+#if 0
+ @ add debug, PB4 output 1
+ tloadr r1, DEBUG_GPIO @0x80058a PB oen
+ tmov r0, #139 @0b 11101111
+ tstorerb r0, [r1, #0]
+
+ tmov r0, #16 @0b 00010000
+ tstorerb r0, [r1, #1] @0x800583 PB output
+#endif
+
+#if FLASH_WAKEUP_EN
+
+FLASH_WAKEUP_BEGIN:
+ tloadr r0,DATA_I+44
+ tmov r1,#0
+ tstorerb r1,[r0,#1]
+ tmov r1,#171 @Flash deep cmd: 0xAB
+ tstorerb r1,[r0,#0]
+ tmov r2,#0
+ tmov r3,#6
+TNOP:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle TNOP
+ tmov r1,#1
+ tstorerb r1,[r0,#1]
+FLASH_WAKEUP_END:
+
+#endif
+
+@ efuse load need delay about 18us
+ tmov r2,#0
+ tmov r3,#110
+EFUSE_DELAY:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle EFUSE_DELAY
+EFUSE_DELAY_END:
+
+@********************************************************************************************************
+@ FILL .DATA AND .BSS WITH 0xFF
+@********************************************************************************************************
+#if FLL_STK_EN
+
+ @ tloadr r0, FLL_D @r0 = 0xffffffff
+ tmov r0, #0 @r0 = 0xffffffff
+ tloadr r1, FLL_D+4 @r1 = _start_data_
+ tloadr r2, FLL_D+8 @r2 = 0x850000
+
+FLL_STK:
+ tcmp r1, r2 @
+ tjge FLL_STK_END @r1>=r2 jump to FLL_STK_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_start_data_)=0xffffffff
+ tadd r1, #4 @r1 = r1+4
+ tj FLL_STK @jump to FLL_STK
+FLL_STK_END:
+
+#endif
+@********************************************************************************************************
+@ UPDATE SP UNDER IRQ/SVC MODE
+@********************************************************************************************************
+ tloadr r0, DAT0 @r0 = 0x12 IRQ
+ tmcsr r0 @CPSR=r0
+ tloadr r0, DAT0 + 8 @r0 = g_intstacktop
+ tmov r13, r0 @r13/SP= r0 update SP under IRQ mode
+
+ tloadr r0, DAT0 + 4 @r0 = 0x13 SVC
+ tmcsr r0 @CPSR=r0
+ tloadr r0, IDLE_STACK @r0 = _ebss + CONFIG_IDLETHREAD_STACKSIZE
+ tmov r13, r0 @r13= r0 update SP under SVC mode
+@********************************************************************************************************
+@ .BSS INITIALIZATION FOR 0
+@********************************************************************************************************
+ tmov r0, #0 @r0 = 0
+ tloadr r1, DAT0 + 16 @r1 = _sbss
+ tloadr r2, DAT0 + 20 @r2 = _ebss
+
+ZERO_BSS_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_BSS_END @r1>=r2 jump to ZERO_BSS_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_sbss)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
+ tj ZERO_BSS_BEGIN @jump to ZERO_BSS_BEGIN
+ZERO_BSS_END:
+@********************************************************************************************************
+@ IC TAG INITIALIZATION
+@********************************************************************************************************
+#if ZERO_IC_TAG_EN
+ZERO_TAG:
+ tmov r0, #0
+ tloadr r1, DAT0 + 28 @r1 = _ictag_start_
+ tloadr r2, DAT0 + 32 @r2 = _ictag_end_
+ZERO_TAG_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_TAG_END @r1>=r2 jump to ZERO_TAG_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_ictag_start_)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
+ tj ZERO_TAG_BEGIN @jump to ZERO_TAG_BEGIN
+ZERO_TAG_END:
+#endif
+@********************************************************************************************************
+@ IC CACHE INITIALIZATION
+@********************************************************************************************************
+
+SET_IC:
+ tloadr r1, DAT0 + 24 @ r1 = 0x80060c
+ tloadr r0, DAT0 + 36 @ r0 = _ramcode_size_align_256_
+ tshftr r0,r0,#8 @ r0 = _ramcode_size_align_256_/256
+ tstorerb r0, [r1, #0] @ *(unsigned int*)(0x80060c) = r0
+#if IC_TAG_CACHE_ADDR_EQU_EN
+
+#else
+ tadd r0, #1 @ r0 = r0 + 1
+#endif
+ tstorerb r0, [r1, #1] @ *(unsigned int*)(0x80060d) = r0
+SET_IC_END:
+@********************************************************************************************************
+@ DCDC INITIALIZATION FOR FLASH
+@********************************************************************************************************
+ /*system on*/
+ tloadr r0,DATA_I+32 @0x00800060
+ tloadr r1,DATA_I+36 @0xff000000
+ tstorer r1,[r0,#0] @*(unsigned int*)0x800060=0xff000000
+ tshftr r1,r1,#24 @0x000000ff
+ tstorerb r1,[r0,#4] @dig_0x64=0xff
+ tloadr r1,DATA_I+40 @dig_0x65=0xf7
+ tstorerb r1,[r0,#5]
+
+
+ /*check ana_reg_0x7e*/
+ tloadr r0,DATA_I+24 @0x7e
+
+RANA_REG_BEGIN:
+ tloadr r1,DATA_I+28 @0x008000b8
+ tmov r2,r0 @ana_reg_adr:0x7e
+ tstorerb r2,[r1,#0] @*(unsigned int*)0x8000b8=0x7e;
+ tmov r2,#64 @ana_reg_dat:0x40=64
+ tstorerb r2,[r1,#2] @*(unsigned int*)0x8000ba=0x40;
+
+RWAIT_REG_FINISH:
+ tloadrb r2,[r1,#2]
+ tshftl r2,r2,#31
+ tshftr r2,r2,#31
+ tcmp r2,#1
+ tjeq RWAIT_REG_FINISH
+ tloadrb r2,[r1,#1]
+RANA_REG_END:
+
+ tshftl r2,r2,#31
+ tshftr r2,r2,#31
+ tcmp r2,#0
+ /*if ana_reg_0x7e==0x00 retention data initiate after waking up from deep*/
+#if MULTI_ADDRESS_START
+ tjeq MULTI_ADDRESS_END
+MULTI_ADDRESS_BEGIN:
+ tloadr r0, MULTI_ADDRESS_DATA
+ tloadr r1, MULTI_ADDRESS_DATA+4
+ tloadr r3, MULTI_ADDRESS_DATA+8
+ tloadrb r2, [r1,#0]
+ tstorerb r2, [r0,#0]
Review Comment:
Done
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,567 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/irq.h>
+
+#define SRAM_SIZE_32K_EN 0/*defaut sram size=64k*/
+
+#define FLL_STK_EN 1
+#define ZERO_IC_TAG_EN 1
+#define IC_TAG_CACEH_ADDR_EQU_EN 0
+#define FLASH_WAKEUP_EN 1
+#define COPY_DATA_EN 1
+#define MULTI_ADDRESS_START 1
+#define MOVE_BIN_CODE_EN 0
+
+#ifndef __LOAD_RAM_SIZE__
+#define __LOAD_RAM_SIZE__ 0xc
+#endif
+
+#ifndef __IRQ_STK_SIZE__
+#define __IRQ_STK_SIZE__ CONFIG_ARCH_INTERRUPTSTACK
+#if CONFIG_ARCH_INTERRUPTSTACK <= 128
+# error "Interrupt Stack must be larger than 128"
+#endif
+#endif
+ .code 16
+@********************************************************************************************************
+@ MACROS AND DEFINIITIONS
+@********************************************************************************************************
+
+ @ Mode, correspords to bits 0-5 in CPSR
+ .equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
+ .equ IRQ_MODE, 0x12 @ Interrupt Request mode
+ .equ SVC_MODE, 0x13 @ Supervisor mode
+ .equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
+ .equ __LOAD_FLASH, 1
+ .equ __LOAD_DUT, 0
+ .equ __LOAD_RAM, 0
+@********************************************************************************************************
+@ TC32 EXCEPTION VECTORS
+@********************************************************************************************************
+
+ .section .vectors,"ax"
+ .global __reset
+ .global __irq
+ .global __start
+ .global __LOAD_RAM
+ .global __LOAD_DUT
+ .global __LOAD_FLASH
+
+ .extern g_current_regs
+
+__start: @ MUST, referenced by boot.link
+
+ .extern irq_handler
+
+ .extern firmwareVersion
+
+ .extern _ramcode_size_div_16_
+ .extern _ramcode_size_div_256_
+ .extern _ramcode_size_div_16_align_256_
+ .extern _ramcode_size_align_256_
+ .extern _ictag_start_
+ .extern _ictag_end_
+ .extern tl_multi_addr_L
+ .extern tl_multi_addr_H
+ .org 0x0
+ tj __reset
+@ .word (firmwareVersion)
+ .org 0x8
+ .word (0x544c4e4b)
+#if MOVE_BIN_CODE_EN
+ .word (0x00880000 + _bin_size_div_16)
+#else
+ .word (0x00880000 + _ramcode_size_div_16_align_256_)
+#endif
+
+ .org 0x10
+ tj __irq
+ .org 0x18
+ .word (_bin_size_)
+ .extern __tc32_start
+
+ .org 0x20
+
+__reset:
+
+#if 0
+ @ add debug, PB4 output 1
+ tloadr r1, DEBUG_GPIO @0x80058a PB oen
+ tmov r0, #139 @0b 11101111
+ tstorerb r0, [r1, #0]
+
+ tmov r0, #16 @0b 00010000
+ tstorerb r0, [r1, #1] @0x800583 PB output
+#endif
+
+#if FLASH_WAKEUP_EN
+
+FLASH_WAKEUP_BEGIN:
+ tloadr r0,DATA_I+44
+ tmov r1,#0
+ tstorerb r1,[r0,#1]
+ tmov r1,#171 @Flash deep cmd: 0xAB
+ tstorerb r1,[r0,#0]
+ tmov r2,#0
+ tmov r3,#6
+TNOP:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle TNOP
+ tmov r1,#1
+ tstorerb r1,[r0,#1]
+FLASH_WAKEUP_END:
+
+#endif
+
+@ efuse load need delay about 18us
+ tmov r2,#0
+ tmov r3,#110
+EFUSE_DELAY:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle EFUSE_DELAY
+EFUSE_DELAY_END:
+
+@********************************************************************************************************
+@ FILL .DATA AND .BSS WITH 0xFF
+@********************************************************************************************************
+#if FLL_STK_EN
+
+ @ tloadr r0, FLL_D @r0 = 0xffffffff
+ tmov r0, #0 @r0 = 0xffffffff
+ tloadr r1, FLL_D+4 @r1 = _start_data_
+ tloadr r2, FLL_D+8 @r2 = 0x850000
+
+FLL_STK:
+ tcmp r1, r2 @
+ tjge FLL_STK_END @r1>=r2 jump to FLL_STK_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_start_data_)=0xffffffff
+ tadd r1, #4 @r1 = r1+4
+ tj FLL_STK @jump to FLL_STK
+FLL_STK_END:
+
+#endif
+@********************************************************************************************************
+@ UPDATE SP UNDER IRQ/SVC MODE
+@********************************************************************************************************
+ tloadr r0, DAT0 @r0 = 0x12 IRQ
+ tmcsr r0 @CPSR=r0
+ tloadr r0, DAT0 + 8 @r0 = g_intstacktop
+ tmov r13, r0 @r13/SP= r0 update SP under IRQ mode
+
+ tloadr r0, DAT0 + 4 @r0 = 0x13 SVC
+ tmcsr r0 @CPSR=r0
+ tloadr r0, IDLE_STACK @r0 = _ebss + CONFIG_IDLETHREAD_STACKSIZE
+ tmov r13, r0 @r13= r0 update SP under SVC mode
+@********************************************************************************************************
+@ .BSS INITIALIZATION FOR 0
+@********************************************************************************************************
+ tmov r0, #0 @r0 = 0
+ tloadr r1, DAT0 + 16 @r1 = _sbss
+ tloadr r2, DAT0 + 20 @r2 = _ebss
+
+ZERO_BSS_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_BSS_END @r1>=r2 jump to ZERO_BSS_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_sbss)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
+ tj ZERO_BSS_BEGIN @jump to ZERO_BSS_BEGIN
+ZERO_BSS_END:
+@********************************************************************************************************
+@ IC TAG INITIALIZATION
+@********************************************************************************************************
+#if ZERO_IC_TAG_EN
+ZERO_TAG:
+ tmov r0, #0
+ tloadr r1, DAT0 + 28 @r1 = _ictag_start_
+ tloadr r2, DAT0 + 32 @r2 = _ictag_end_
+ZERO_TAG_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_TAG_END @r1>=r2 jump to ZERO_TAG_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_ictag_start_)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
Review Comment:
Done
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,567 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/irq.h>
+
+#define SRAM_SIZE_32K_EN 0/*defaut sram size=64k*/
+
+#define FLL_STK_EN 1
+#define ZERO_IC_TAG_EN 1
+#define IC_TAG_CACEH_ADDR_EQU_EN 0
+#define FLASH_WAKEUP_EN 1
+#define COPY_DATA_EN 1
+#define MULTI_ADDRESS_START 1
+#define MOVE_BIN_CODE_EN 0
+
+#ifndef __LOAD_RAM_SIZE__
+#define __LOAD_RAM_SIZE__ 0xc
+#endif
+
+#ifndef __IRQ_STK_SIZE__
+#define __IRQ_STK_SIZE__ CONFIG_ARCH_INTERRUPTSTACK
+#if CONFIG_ARCH_INTERRUPTSTACK <= 128
+# error "Interrupt Stack must be larger than 128"
+#endif
+#endif
+ .code 16
+@********************************************************************************************************
+@ MACROS AND DEFINIITIONS
+@********************************************************************************************************
+
+ @ Mode, correspords to bits 0-5 in CPSR
+ .equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
+ .equ IRQ_MODE, 0x12 @ Interrupt Request mode
+ .equ SVC_MODE, 0x13 @ Supervisor mode
+ .equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
+ .equ __LOAD_FLASH, 1
+ .equ __LOAD_DUT, 0
+ .equ __LOAD_RAM, 0
+@********************************************************************************************************
+@ TC32 EXCEPTION VECTORS
+@********************************************************************************************************
+
+ .section .vectors,"ax"
+ .global __reset
+ .global __irq
+ .global __start
+ .global __LOAD_RAM
+ .global __LOAD_DUT
+ .global __LOAD_FLASH
+
+ .extern g_current_regs
+
+__start: @ MUST, referenced by boot.link
+
+ .extern irq_handler
+
+ .extern firmwareVersion
+
+ .extern _ramcode_size_div_16_
+ .extern _ramcode_size_div_256_
+ .extern _ramcode_size_div_16_align_256_
+ .extern _ramcode_size_align_256_
+ .extern _ictag_start_
+ .extern _ictag_end_
+ .extern tl_multi_addr_L
+ .extern tl_multi_addr_H
+ .org 0x0
+ tj __reset
+@ .word (firmwareVersion)
+ .org 0x8
+ .word (0x544c4e4b)
+#if MOVE_BIN_CODE_EN
+ .word (0x00880000 + _bin_size_div_16)
+#else
+ .word (0x00880000 + _ramcode_size_div_16_align_256_)
+#endif
+
+ .org 0x10
+ tj __irq
+ .org 0x18
+ .word (_bin_size_)
+ .extern __tc32_start
+
+ .org 0x20
+
+__reset:
+
+#if 0
+ @ add debug, PB4 output 1
+ tloadr r1, DEBUG_GPIO @0x80058a PB oen
+ tmov r0, #139 @0b 11101111
+ tstorerb r0, [r1, #0]
+
+ tmov r0, #16 @0b 00010000
+ tstorerb r0, [r1, #1] @0x800583 PB output
+#endif
+
+#if FLASH_WAKEUP_EN
+
+FLASH_WAKEUP_BEGIN:
+ tloadr r0,DATA_I+44
+ tmov r1,#0
+ tstorerb r1,[r0,#1]
+ tmov r1,#171 @Flash deep cmd: 0xAB
+ tstorerb r1,[r0,#0]
+ tmov r2,#0
+ tmov r3,#6
+TNOP:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle TNOP
+ tmov r1,#1
+ tstorerb r1,[r0,#1]
+FLASH_WAKEUP_END:
+
+#endif
+
+@ efuse load need delay about 18us
+ tmov r2,#0
+ tmov r3,#110
+EFUSE_DELAY:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle EFUSE_DELAY
+EFUSE_DELAY_END:
+
+@********************************************************************************************************
+@ FILL .DATA AND .BSS WITH 0xFF
+@********************************************************************************************************
+#if FLL_STK_EN
+
+ @ tloadr r0, FLL_D @r0 = 0xffffffff
+ tmov r0, #0 @r0 = 0xffffffff
+ tloadr r1, FLL_D+4 @r1 = _start_data_
+ tloadr r2, FLL_D+8 @r2 = 0x850000
+
+FLL_STK:
+ tcmp r1, r2 @
+ tjge FLL_STK_END @r1>=r2 jump to FLL_STK_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_start_data_)=0xffffffff
+ tadd r1, #4 @r1 = r1+4
+ tj FLL_STK @jump to FLL_STK
+FLL_STK_END:
+
+#endif
+@********************************************************************************************************
+@ UPDATE SP UNDER IRQ/SVC MODE
+@********************************************************************************************************
+ tloadr r0, DAT0 @r0 = 0x12 IRQ
+ tmcsr r0 @CPSR=r0
+ tloadr r0, DAT0 + 8 @r0 = g_intstacktop
+ tmov r13, r0 @r13/SP= r0 update SP under IRQ mode
+
+ tloadr r0, DAT0 + 4 @r0 = 0x13 SVC
+ tmcsr r0 @CPSR=r0
+ tloadr r0, IDLE_STACK @r0 = _ebss + CONFIG_IDLETHREAD_STACKSIZE
+ tmov r13, r0 @r13= r0 update SP under SVC mode
+@********************************************************************************************************
+@ .BSS INITIALIZATION FOR 0
+@********************************************************************************************************
+ tmov r0, #0 @r0 = 0
+ tloadr r1, DAT0 + 16 @r1 = _sbss
+ tloadr r2, DAT0 + 20 @r2 = _ebss
+
+ZERO_BSS_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_BSS_END @r1>=r2 jump to ZERO_BSS_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_sbss)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
Review Comment:
Done
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,567 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/irq.h>
+
+#define SRAM_SIZE_32K_EN 0/*defaut sram size=64k*/
+
+#define FLL_STK_EN 1
+#define ZERO_IC_TAG_EN 1
+#define IC_TAG_CACEH_ADDR_EQU_EN 0
+#define FLASH_WAKEUP_EN 1
+#define COPY_DATA_EN 1
+#define MULTI_ADDRESS_START 1
+#define MOVE_BIN_CODE_EN 0
+
+#ifndef __LOAD_RAM_SIZE__
+#define __LOAD_RAM_SIZE__ 0xc
+#endif
+
+#ifndef __IRQ_STK_SIZE__
+#define __IRQ_STK_SIZE__ CONFIG_ARCH_INTERRUPTSTACK
+#if CONFIG_ARCH_INTERRUPTSTACK <= 128
+# error "Interrupt Stack must be larger than 128"
+#endif
+#endif
+ .code 16
+@********************************************************************************************************
+@ MACROS AND DEFINIITIONS
+@********************************************************************************************************
+
+ @ Mode, correspords to bits 0-5 in CPSR
+ .equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
+ .equ IRQ_MODE, 0x12 @ Interrupt Request mode
+ .equ SVC_MODE, 0x13 @ Supervisor mode
+ .equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
+ .equ __LOAD_FLASH, 1
+ .equ __LOAD_DUT, 0
+ .equ __LOAD_RAM, 0
+@********************************************************************************************************
+@ TC32 EXCEPTION VECTORS
+@********************************************************************************************************
+
+ .section .vectors,"ax"
+ .global __reset
+ .global __irq
+ .global __start
Review Comment:
Done
--
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[GitHub] [incubator-nuttx] CV-Bowen commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r866445556
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,92 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include common/Make.defs
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS += -DMCU_STARTUP_FLASH
+
+# Filter-out unnecessary .S files
+CMN_ASRCS :=
+
+# Filter-out unnecessary .c files
+TLSR82_CSRCS_FILTER := arm_backtrace_fp.c arm_backtrace_thumb.c arm_hostfs.c
+TLSR82_CSRCS_FILTER += arm_etherstub.c arm_udelay.c arm_semi_syslog.c
+TLSR82_CSRCS_FILTER += arm_fullcontextrestore.c arm_saveusercontext.c
+TLSR82_CSRCS_FILTER += arm_switchcontext.c arm_vfork.c
Review Comment:
Done
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,92 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include common/Make.defs
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS += -DMCU_STARTUP_FLASH
+
+# Filter-out unnecessary .S files
+CMN_ASRCS :=
+
+# Filter-out unnecessary .c files
+TLSR82_CSRCS_FILTER := arm_backtrace_fp.c arm_backtrace_thumb.c arm_hostfs.c
+TLSR82_CSRCS_FILTER += arm_etherstub.c arm_udelay.c arm_semi_syslog.c
+TLSR82_CSRCS_FILTER += arm_fullcontextrestore.c arm_saveusercontext.c
+TLSR82_CSRCS_FILTER += arm_switchcontext.c arm_vfork.c
+CMN_CSRCS := $(filter-out $(TLSR82_CSRCS_FILTER), $(CMN_CSRCS))
+
+# Common files in arch/arm/armv6-m
+CMN_CSRCS += arm_sigdeliver.c
+
+# Chip arch related files in arch/arm/tlsr82/tc32
+CHIP_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
+
+CHIP_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
+CHIP_CSRCS += tc32_syscall.c tc32_udelay.c
+
+ifeq ($(CONFIG_SCHED_BACKTRACE),y)
+ CHIP_CSRCS += tc32_backtrace.c
+endif
Review Comment:
Done
##########
arch/arm/src/tlsr82/common/div_mod.S:
##########
@@ -0,0 +1,345 @@
+/********************************************************************************************************
+ * @file div_mod.S
Review Comment:
Done
--
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r867122658
##########
arch/arm/src/tlsr82/Toolchain.defs:
##########
@@ -0,0 +1,191 @@
+############################################################################
+# arch/arm/src/tlsr82/Toolchain.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Setup for the selected toolchain
+
+#
+# Handle old-style chip-specific toolchain names in the absence of
+# a new-style toolchain specification, force the selection of a single
+# toolchain and allow the selected toolchain to be overridden by a
+# command-line selection.
+#
+
+ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT)),y)
+ CONFIG_ARMV6M_TOOLCHAIN ?= BUILDROOT
+endif
+
+ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_GNU_EABI)),y)
+ CONFIG_ARMV6M_TOOLCHAIN ?= GNU_EABI
+endif
+
+ifeq ($(filter y, $(CONFIG_ARMV6M_TOOLCHAIN_CLANG)),y)
+ CONFIG_ARMV6M_TOOLCHAIN ?= CLANG
+endif
+
+#
+# Supported toolchains
+#
+# Each toolchain definition should set:
+#
+# CROSSDEV The GNU toolchain triple (command prefix)
+# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
+# options, etc.
+# ARCHOPTIMIZATION The maximum optimization level that results in
+# reliable code generation.
+#
+
+ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
+ ARCHOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL)
+else ifeq ($(CONFIG_DEBUG_FULLOPT),y)
+ ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CLANG)
+ ARCHOPTIMIZATION ?= -Oz
+ else
+ ARCHOPTIMIZATION ?= -Os
+ endif
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += -fno-strict-aliasing
+endif
+
+ifeq ($(CONFIG_FRAME_POINTER),y)
+ ARCHOPTIMIZATION += -fno-omit-frame-pointer -fno-optimize-sibling-calls
+else
+ ARCHOPTIMIZATION += -fomit-frame-pointer
+endif
+
+# Clang Configuration files
+
+ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CLANG)
+ TOOLCHAIN_MARCH := --config armv6m_soft_nofp_nosys
+endif
+
+# Link Time Optimization
+
+ifeq ($(CONFIG_LTO_THIN),y)
+ ARCHOPTIMIZATION += -flto=thin
+else ifeq ($(CONFIG_LTO_FULL),y)
+ ARCHOPTIMIZATION += -flto
+endif
+
+# NuttX buildroot under Linux or Cygwin
+
+ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),BUILDROOT)
+ CROSSDEV ?= arm-nuttx-eabi-
+ ARCHCPUFLAGS = $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MTUNE) $(TOOLCHAIN_MFLOAT)
+endif
+
+# Generic GNU EABI toolchain
+
+ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),GNU_EABI)
+ CROSSDEV ?= tc32-elf-
+ ARCHCPUFLAGS = $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MTUNE) $(TOOLCHAIN_MFLOAT)
+endif
+
+# Clang toolchain
+
+ifeq ($(CONFIG_ARMV6M_TOOLCHAIN),CLANG)
+ ARCHCPUFLAGS = $(TOOLCHAIN_MARCH) $(TOOLCHAIN_MTUNE) $(TOOLCHAIN_MFLOAT)
+
+ CC = clang
+ CXX = clang++
+ CPP = clang -E -P -x c
+ LD = ld.lld -m armelf
+ STRIP = llvm-strip --strip-unneeded
+ AR = llvm-ar rcs
+ NM = llvm-nm
+ OBJCOPY = llvm-objcopy
+ OBJDUMP = llvm-objdump
+
+ # Since the no_builtin attribute is not fully supported on Clang
+ # disable the built-in functions, refer:
+ # https://github.com/apache/incubator-nuttx/pull/5971
+
+ MAXOPTIMIZATION += -fno-builtin
+
+# Default toolchain
+
+else
+ CC = $(CROSSDEV)gcc
+ CXX = $(CROSSDEV)g++
+ CPP = $(CROSSDEV)gcc -E -P -x c
+ LD = $(CROSSDEV)ld
+ STRIP = $(CROSSDEV)strip --strip-unneeded
+ AR = $(CROSSDEV)ar rcs
+ NM = $(CROSSDEV)nm
+ OBJCOPY = $(CROSSDEV)objcopy
+ OBJDUMP = $(CROSSDEV)objdump
+endif
+
+# Architecture flags
+
+ifeq ($(CONFIG_MM_KASAN),y)
+ ARCHCPUFLAGS += -fsanitize=kernel-address
+endif
+
+ARCHCFLAGS += -fno-common
+ARCHCXXFLAGS += -fno-common
+
+ifneq ($(CONFIG_CXX_EXCEPTION),y)
+ ARCHCXXFLAGS += -fno-exceptions -fcheck-new
+endif
+
+ifneq ($(CONFIG_CXX_RTTI),y)
+ ARCHCXXFLAGS += -fno-rtti
+endif
+
+# Optimization of unused sections
+
+ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y)
+ LDFLAGS += --gc-sections
+ ARCHOPTIMIZATION += -ffunction-sections -fdata-sections
+endif
+
+# Debug link map
+
+ifeq ($(CONFIG_DEBUG_LINK_MAP),y)
+ LDFLAGS += --cref -Map=$(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx.map)
+endif
+
+# Debuf link symbols
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+ ARCHOPTIMIZATION += -g
+endif
+
+# Add the builtin library
+
+COMPILER_RT_LIB = $(shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name)
+ifeq ($(wildcard $(COMPILER_RT_LIB)),)
Review Comment:
There were some changes related to this merged into mainline recently. Please re-check and sync
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,567 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/irq.h>
+
+#define SRAM_SIZE_32K_EN 0/*defaut sram size=64k*/
+
+#define FLL_STK_EN 1
+#define ZERO_IC_TAG_EN 1
+#define IC_TAG_CACEH_ADDR_EQU_EN 0
+#define FLASH_WAKEUP_EN 1
+#define COPY_DATA_EN 1
+#define MULTI_ADDRESS_START 1
+#define MOVE_BIN_CODE_EN 0
+
+#ifndef __LOAD_RAM_SIZE__
+#define __LOAD_RAM_SIZE__ 0xc
+#endif
+
+#ifndef __IRQ_STK_SIZE__
+#define __IRQ_STK_SIZE__ CONFIG_ARCH_INTERRUPTSTACK
+#if CONFIG_ARCH_INTERRUPTSTACK <= 128
+# error "Interrupt Stack must be larger than 128"
+#endif
+#endif
+ .code 16
+@********************************************************************************************************
+@ MACROS AND DEFINIITIONS
+@********************************************************************************************************
+
+ @ Mode, correspords to bits 0-5 in CPSR
+ .equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
+ .equ IRQ_MODE, 0x12 @ Interrupt Request mode
+ .equ SVC_MODE, 0x13 @ Supervisor mode
+ .equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
+ .equ __LOAD_FLASH, 1
+ .equ __LOAD_DUT, 0
+ .equ __LOAD_RAM, 0
+@********************************************************************************************************
+@ TC32 EXCEPTION VECTORS
+@********************************************************************************************************
+
+ .section .vectors,"ax"
+ .global __reset
+ .global __irq
+ .global __start
+ .global __LOAD_RAM
+ .global __LOAD_DUT
+ .global __LOAD_FLASH
+
+ .extern g_current_regs
+
+__start: @ MUST, referenced by boot.link
+
+ .extern irq_handler
+
+ .extern firmwareVersion
+
+ .extern _ramcode_size_div_16_
+ .extern _ramcode_size_div_256_
+ .extern _ramcode_size_div_16_align_256_
+ .extern _ramcode_size_align_256_
+ .extern _ictag_start_
+ .extern _ictag_end_
+ .extern tl_multi_addr_L
+ .extern tl_multi_addr_H
+ .org 0x0
+ tj __reset
+@ .word (firmwareVersion)
+ .org 0x8
+ .word (0x544c4e4b)
+#if MOVE_BIN_CODE_EN
+ .word (0x00880000 + _bin_size_div_16)
+#else
+ .word (0x00880000 + _ramcode_size_div_16_align_256_)
+#endif
+
+ .org 0x10
+ tj __irq
+ .org 0x18
+ .word (_bin_size_)
+ .extern __tc32_start
+
+ .org 0x20
+
+__reset:
+
+#if 0
+ @ add debug, PB4 output 1
+ tloadr r1, DEBUG_GPIO @0x80058a PB oen
+ tmov r0, #139 @0b 11101111
+ tstorerb r0, [r1, #0]
+
+ tmov r0, #16 @0b 00010000
+ tstorerb r0, [r1, #1] @0x800583 PB output
+#endif
+
+#if FLASH_WAKEUP_EN
+
+FLASH_WAKEUP_BEGIN:
+ tloadr r0,DATA_I+44
+ tmov r1,#0
+ tstorerb r1,[r0,#1]
+ tmov r1,#171 @Flash deep cmd: 0xAB
+ tstorerb r1,[r0,#0]
+ tmov r2,#0
+ tmov r3,#6
+TNOP:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle TNOP
+ tmov r1,#1
+ tstorerb r1,[r0,#1]
+FLASH_WAKEUP_END:
+
+#endif
+
+@ efuse load need delay about 18us
+ tmov r2,#0
+ tmov r3,#110
+EFUSE_DELAY:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle EFUSE_DELAY
+EFUSE_DELAY_END:
+
+@********************************************************************************************************
+@ FILL .DATA AND .BSS WITH 0xFF
+@********************************************************************************************************
+#if FLL_STK_EN
+
+ @ tloadr r0, FLL_D @r0 = 0xffffffff
+ tmov r0, #0 @r0 = 0xffffffff
+ tloadr r1, FLL_D+4 @r1 = _start_data_
+ tloadr r2, FLL_D+8 @r2 = 0x850000
+
+FLL_STK:
+ tcmp r1, r2 @
+ tjge FLL_STK_END @r1>=r2 jump to FLL_STK_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_start_data_)=0xffffffff
+ tadd r1, #4 @r1 = r1+4
+ tj FLL_STK @jump to FLL_STK
+FLL_STK_END:
+
+#endif
+@********************************************************************************************************
+@ UPDATE SP UNDER IRQ/SVC MODE
+@********************************************************************************************************
+ tloadr r0, DAT0 @r0 = 0x12 IRQ
+ tmcsr r0 @CPSR=r0
+ tloadr r0, DAT0 + 8 @r0 = g_intstacktop
+ tmov r13, r0 @r13/SP= r0 update SP under IRQ mode
+
+ tloadr r0, DAT0 + 4 @r0 = 0x13 SVC
+ tmcsr r0 @CPSR=r0
+ tloadr r0, IDLE_STACK @r0 = _ebss + CONFIG_IDLETHREAD_STACKSIZE
+ tmov r13, r0 @r13= r0 update SP under SVC mode
+@********************************************************************************************************
+@ .BSS INITIALIZATION FOR 0
+@********************************************************************************************************
+ tmov r0, #0 @r0 = 0
+ tloadr r1, DAT0 + 16 @r1 = _sbss
+ tloadr r2, DAT0 + 20 @r2 = _ebss
+
+ZERO_BSS_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_BSS_END @r1>=r2 jump to ZERO_BSS_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_sbss)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
Review Comment:
please change to TABs
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,567 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/irq.h>
+
+#define SRAM_SIZE_32K_EN 0/*defaut sram size=64k*/
+
+#define FLL_STK_EN 1
+#define ZERO_IC_TAG_EN 1
+#define IC_TAG_CACEH_ADDR_EQU_EN 0
+#define FLASH_WAKEUP_EN 1
+#define COPY_DATA_EN 1
+#define MULTI_ADDRESS_START 1
+#define MOVE_BIN_CODE_EN 0
+
+#ifndef __LOAD_RAM_SIZE__
+#define __LOAD_RAM_SIZE__ 0xc
+#endif
+
+#ifndef __IRQ_STK_SIZE__
+#define __IRQ_STK_SIZE__ CONFIG_ARCH_INTERRUPTSTACK
+#if CONFIG_ARCH_INTERRUPTSTACK <= 128
+# error "Interrupt Stack must be larger than 128"
+#endif
+#endif
+ .code 16
+@********************************************************************************************************
+@ MACROS AND DEFINIITIONS
+@********************************************************************************************************
+
+ @ Mode, correspords to bits 0-5 in CPSR
+ .equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
+ .equ IRQ_MODE, 0x12 @ Interrupt Request mode
+ .equ SVC_MODE, 0x13 @ Supervisor mode
+ .equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
+ .equ __LOAD_FLASH, 1
+ .equ __LOAD_DUT, 0
+ .equ __LOAD_RAM, 0
+@********************************************************************************************************
+@ TC32 EXCEPTION VECTORS
+@********************************************************************************************************
+
+ .section .vectors,"ax"
+ .global __reset
+ .global __irq
+ .global __start
Review Comment:
TABs
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,567 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/irq.h>
+
+#define SRAM_SIZE_32K_EN 0/*defaut sram size=64k*/
+
+#define FLL_STK_EN 1
+#define ZERO_IC_TAG_EN 1
+#define IC_TAG_CACEH_ADDR_EQU_EN 0
+#define FLASH_WAKEUP_EN 1
+#define COPY_DATA_EN 1
+#define MULTI_ADDRESS_START 1
+#define MOVE_BIN_CODE_EN 0
+
+#ifndef __LOAD_RAM_SIZE__
+#define __LOAD_RAM_SIZE__ 0xc
+#endif
+
+#ifndef __IRQ_STK_SIZE__
+#define __IRQ_STK_SIZE__ CONFIG_ARCH_INTERRUPTSTACK
+#if CONFIG_ARCH_INTERRUPTSTACK <= 128
+# error "Interrupt Stack must be larger than 128"
+#endif
+#endif
+ .code 16
+@********************************************************************************************************
+@ MACROS AND DEFINIITIONS
+@********************************************************************************************************
+
+ @ Mode, correspords to bits 0-5 in CPSR
+ .equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
+ .equ IRQ_MODE, 0x12 @ Interrupt Request mode
+ .equ SVC_MODE, 0x13 @ Supervisor mode
+ .equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
+ .equ __LOAD_FLASH, 1
+ .equ __LOAD_DUT, 0
+ .equ __LOAD_RAM, 0
+@********************************************************************************************************
+@ TC32 EXCEPTION VECTORS
+@********************************************************************************************************
+
+ .section .vectors,"ax"
+ .global __reset
+ .global __irq
+ .global __start
+ .global __LOAD_RAM
+ .global __LOAD_DUT
+ .global __LOAD_FLASH
+
+ .extern g_current_regs
+
+__start: @ MUST, referenced by boot.link
+
+ .extern irq_handler
+
+ .extern firmwareVersion
+
+ .extern _ramcode_size_div_16_
+ .extern _ramcode_size_div_256_
+ .extern _ramcode_size_div_16_align_256_
+ .extern _ramcode_size_align_256_
+ .extern _ictag_start_
+ .extern _ictag_end_
+ .extern tl_multi_addr_L
+ .extern tl_multi_addr_H
+ .org 0x0
+ tj __reset
+@ .word (firmwareVersion)
+ .org 0x8
+ .word (0x544c4e4b)
+#if MOVE_BIN_CODE_EN
+ .word (0x00880000 + _bin_size_div_16)
+#else
+ .word (0x00880000 + _ramcode_size_div_16_align_256_)
+#endif
+
+ .org 0x10
+ tj __irq
+ .org 0x18
+ .word (_bin_size_)
+ .extern __tc32_start
+
+ .org 0x20
+
+__reset:
+
+#if 0
+ @ add debug, PB4 output 1
+ tloadr r1, DEBUG_GPIO @0x80058a PB oen
+ tmov r0, #139 @0b 11101111
+ tstorerb r0, [r1, #0]
+
+ tmov r0, #16 @0b 00010000
+ tstorerb r0, [r1, #1] @0x800583 PB output
+#endif
+
+#if FLASH_WAKEUP_EN
+
+FLASH_WAKEUP_BEGIN:
+ tloadr r0,DATA_I+44
+ tmov r1,#0
+ tstorerb r1,[r0,#1]
+ tmov r1,#171 @Flash deep cmd: 0xAB
+ tstorerb r1,[r0,#0]
+ tmov r2,#0
+ tmov r3,#6
+TNOP:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle TNOP
+ tmov r1,#1
+ tstorerb r1,[r0,#1]
+FLASH_WAKEUP_END:
+
+#endif
+
+@ efuse load need delay about 18us
+ tmov r2,#0
+ tmov r3,#110
+EFUSE_DELAY:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle EFUSE_DELAY
+EFUSE_DELAY_END:
+
+@********************************************************************************************************
+@ FILL .DATA AND .BSS WITH 0xFF
+@********************************************************************************************************
+#if FLL_STK_EN
+
+ @ tloadr r0, FLL_D @r0 = 0xffffffff
+ tmov r0, #0 @r0 = 0xffffffff
+ tloadr r1, FLL_D+4 @r1 = _start_data_
+ tloadr r2, FLL_D+8 @r2 = 0x850000
+
+FLL_STK:
+ tcmp r1, r2 @
+ tjge FLL_STK_END @r1>=r2 jump to FLL_STK_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_start_data_)=0xffffffff
+ tadd r1, #4 @r1 = r1+4
+ tj FLL_STK @jump to FLL_STK
+FLL_STK_END:
+
+#endif
+@********************************************************************************************************
+@ UPDATE SP UNDER IRQ/SVC MODE
+@********************************************************************************************************
+ tloadr r0, DAT0 @r0 = 0x12 IRQ
+ tmcsr r0 @CPSR=r0
+ tloadr r0, DAT0 + 8 @r0 = g_intstacktop
+ tmov r13, r0 @r13/SP= r0 update SP under IRQ mode
+
+ tloadr r0, DAT0 + 4 @r0 = 0x13 SVC
+ tmcsr r0 @CPSR=r0
+ tloadr r0, IDLE_STACK @r0 = _ebss + CONFIG_IDLETHREAD_STACKSIZE
+ tmov r13, r0 @r13= r0 update SP under SVC mode
+@********************************************************************************************************
+@ .BSS INITIALIZATION FOR 0
+@********************************************************************************************************
+ tmov r0, #0 @r0 = 0
+ tloadr r1, DAT0 + 16 @r1 = _sbss
+ tloadr r2, DAT0 + 20 @r2 = _ebss
+
+ZERO_BSS_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_BSS_END @r1>=r2 jump to ZERO_BSS_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_sbss)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
+ tj ZERO_BSS_BEGIN @jump to ZERO_BSS_BEGIN
+ZERO_BSS_END:
+@********************************************************************************************************
+@ IC TAG INITIALIZATION
+@********************************************************************************************************
+#if ZERO_IC_TAG_EN
+ZERO_TAG:
+ tmov r0, #0
+ tloadr r1, DAT0 + 28 @r1 = _ictag_start_
+ tloadr r2, DAT0 + 32 @r2 = _ictag_end_
+ZERO_TAG_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_TAG_END @r1>=r2 jump to ZERO_TAG_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_ictag_start_)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
Review Comment:
please change to TABs
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,567 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/chip/irq.h>
+
+#define SRAM_SIZE_32K_EN 0/*defaut sram size=64k*/
+
+#define FLL_STK_EN 1
+#define ZERO_IC_TAG_EN 1
+#define IC_TAG_CACEH_ADDR_EQU_EN 0
+#define FLASH_WAKEUP_EN 1
+#define COPY_DATA_EN 1
+#define MULTI_ADDRESS_START 1
+#define MOVE_BIN_CODE_EN 0
+
+#ifndef __LOAD_RAM_SIZE__
+#define __LOAD_RAM_SIZE__ 0xc
+#endif
+
+#ifndef __IRQ_STK_SIZE__
+#define __IRQ_STK_SIZE__ CONFIG_ARCH_INTERRUPTSTACK
+#if CONFIG_ARCH_INTERRUPTSTACK <= 128
+# error "Interrupt Stack must be larger than 128"
+#endif
+#endif
+ .code 16
+@********************************************************************************************************
+@ MACROS AND DEFINIITIONS
+@********************************************************************************************************
+
+ @ Mode, correspords to bits 0-5 in CPSR
+ .equ MODE_BITS, 0x1F @ Bit mask for mode bits in CPSR
+ .equ IRQ_MODE, 0x12 @ Interrupt Request mode
+ .equ SVC_MODE, 0x13 @ Supervisor mode
+ .equ IRQ_STK_SIZE, __IRQ_STK_SIZE__
+ .equ __LOAD_FLASH, 1
+ .equ __LOAD_DUT, 0
+ .equ __LOAD_RAM, 0
+@********************************************************************************************************
+@ TC32 EXCEPTION VECTORS
+@********************************************************************************************************
+
+ .section .vectors,"ax"
+ .global __reset
+ .global __irq
+ .global __start
+ .global __LOAD_RAM
+ .global __LOAD_DUT
+ .global __LOAD_FLASH
+
+ .extern g_current_regs
+
+__start: @ MUST, referenced by boot.link
+
+ .extern irq_handler
+
+ .extern firmwareVersion
+
+ .extern _ramcode_size_div_16_
+ .extern _ramcode_size_div_256_
+ .extern _ramcode_size_div_16_align_256_
+ .extern _ramcode_size_align_256_
+ .extern _ictag_start_
+ .extern _ictag_end_
+ .extern tl_multi_addr_L
+ .extern tl_multi_addr_H
+ .org 0x0
+ tj __reset
+@ .word (firmwareVersion)
+ .org 0x8
+ .word (0x544c4e4b)
+#if MOVE_BIN_CODE_EN
+ .word (0x00880000 + _bin_size_div_16)
+#else
+ .word (0x00880000 + _ramcode_size_div_16_align_256_)
+#endif
+
+ .org 0x10
+ tj __irq
+ .org 0x18
+ .word (_bin_size_)
+ .extern __tc32_start
+
+ .org 0x20
+
+__reset:
+
+#if 0
+ @ add debug, PB4 output 1
+ tloadr r1, DEBUG_GPIO @0x80058a PB oen
+ tmov r0, #139 @0b 11101111
+ tstorerb r0, [r1, #0]
+
+ tmov r0, #16 @0b 00010000
+ tstorerb r0, [r1, #1] @0x800583 PB output
+#endif
+
+#if FLASH_WAKEUP_EN
+
+FLASH_WAKEUP_BEGIN:
+ tloadr r0,DATA_I+44
+ tmov r1,#0
+ tstorerb r1,[r0,#1]
+ tmov r1,#171 @Flash deep cmd: 0xAB
+ tstorerb r1,[r0,#0]
+ tmov r2,#0
+ tmov r3,#6
+TNOP:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle TNOP
+ tmov r1,#1
+ tstorerb r1,[r0,#1]
+FLASH_WAKEUP_END:
+
+#endif
+
+@ efuse load need delay about 18us
+ tmov r2,#0
+ tmov r3,#110
+EFUSE_DELAY:
+ tadd r2,#1
+ tcmp r2,r3
+ tjle EFUSE_DELAY
+EFUSE_DELAY_END:
+
+@********************************************************************************************************
+@ FILL .DATA AND .BSS WITH 0xFF
+@********************************************************************************************************
+#if FLL_STK_EN
+
+ @ tloadr r0, FLL_D @r0 = 0xffffffff
+ tmov r0, #0 @r0 = 0xffffffff
+ tloadr r1, FLL_D+4 @r1 = _start_data_
+ tloadr r2, FLL_D+8 @r2 = 0x850000
+
+FLL_STK:
+ tcmp r1, r2 @
+ tjge FLL_STK_END @r1>=r2 jump to FLL_STK_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_start_data_)=0xffffffff
+ tadd r1, #4 @r1 = r1+4
+ tj FLL_STK @jump to FLL_STK
+FLL_STK_END:
+
+#endif
+@********************************************************************************************************
+@ UPDATE SP UNDER IRQ/SVC MODE
+@********************************************************************************************************
+ tloadr r0, DAT0 @r0 = 0x12 IRQ
+ tmcsr r0 @CPSR=r0
+ tloadr r0, DAT0 + 8 @r0 = g_intstacktop
+ tmov r13, r0 @r13/SP= r0 update SP under IRQ mode
+
+ tloadr r0, DAT0 + 4 @r0 = 0x13 SVC
+ tmcsr r0 @CPSR=r0
+ tloadr r0, IDLE_STACK @r0 = _ebss + CONFIG_IDLETHREAD_STACKSIZE
+ tmov r13, r0 @r13= r0 update SP under SVC mode
+@********************************************************************************************************
+@ .BSS INITIALIZATION FOR 0
+@********************************************************************************************************
+ tmov r0, #0 @r0 = 0
+ tloadr r1, DAT0 + 16 @r1 = _sbss
+ tloadr r2, DAT0 + 20 @r2 = _ebss
+
+ZERO_BSS_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_BSS_END @r1>=r2 jump to ZERO_BSS_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_sbss)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
+ tj ZERO_BSS_BEGIN @jump to ZERO_BSS_BEGIN
+ZERO_BSS_END:
+@********************************************************************************************************
+@ IC TAG INITIALIZATION
+@********************************************************************************************************
+#if ZERO_IC_TAG_EN
+ZERO_TAG:
+ tmov r0, #0
+ tloadr r1, DAT0 + 28 @r1 = _ictag_start_
+ tloadr r2, DAT0 + 32 @r2 = _ictag_end_
+ZERO_TAG_BEGIN:
+ tcmp r1, r2
+ tjge ZERO_TAG_END @r1>=r2 jump to ZERO_TAG_END
+ tstorer r0, [r1, #0] @*(unsigned int*)(_ictag_start_)=r0=0
+ tadd r1, #4 @r1 = r1 + 4
+ tj ZERO_TAG_BEGIN @jump to ZERO_TAG_BEGIN
+ZERO_TAG_END:
+#endif
+@********************************************************************************************************
+@ IC CACHE INITIALIZATION
+@********************************************************************************************************
+
+SET_IC:
+ tloadr r1, DAT0 + 24 @ r1 = 0x80060c
+ tloadr r0, DAT0 + 36 @ r0 = _ramcode_size_align_256_
+ tshftr r0,r0,#8 @ r0 = _ramcode_size_align_256_/256
+ tstorerb r0, [r1, #0] @ *(unsigned int*)(0x80060c) = r0
+#if IC_TAG_CACHE_ADDR_EQU_EN
+
+#else
+ tadd r0, #1 @ r0 = r0 + 1
+#endif
+ tstorerb r0, [r1, #1] @ *(unsigned int*)(0x80060d) = r0
+SET_IC_END:
+@********************************************************************************************************
+@ DCDC INITIALIZATION FOR FLASH
+@********************************************************************************************************
+ /*system on*/
+ tloadr r0,DATA_I+32 @0x00800060
+ tloadr r1,DATA_I+36 @0xff000000
+ tstorer r1,[r0,#0] @*(unsigned int*)0x800060=0xff000000
+ tshftr r1,r1,#24 @0x000000ff
+ tstorerb r1,[r0,#4] @dig_0x64=0xff
+ tloadr r1,DATA_I+40 @dig_0x65=0xf7
+ tstorerb r1,[r0,#5]
+
+
+ /*check ana_reg_0x7e*/
+ tloadr r0,DATA_I+24 @0x7e
+
+RANA_REG_BEGIN:
+ tloadr r1,DATA_I+28 @0x008000b8
+ tmov r2,r0 @ana_reg_adr:0x7e
+ tstorerb r2,[r1,#0] @*(unsigned int*)0x8000b8=0x7e;
+ tmov r2,#64 @ana_reg_dat:0x40=64
+ tstorerb r2,[r1,#2] @*(unsigned int*)0x8000ba=0x40;
+
+RWAIT_REG_FINISH:
+ tloadrb r2,[r1,#2]
+ tshftl r2,r2,#31
+ tshftr r2,r2,#31
+ tcmp r2,#1
+ tjeq RWAIT_REG_FINISH
+ tloadrb r2,[r1,#1]
+RANA_REG_END:
+
+ tshftl r2,r2,#31
+ tshftr r2,r2,#31
+ tcmp r2,#0
+ /*if ana_reg_0x7e==0x00 retention data initiate after waking up from deep*/
+#if MULTI_ADDRESS_START
+ tjeq MULTI_ADDRESS_END
+MULTI_ADDRESS_BEGIN:
+ tloadr r0, MULTI_ADDRESS_DATA
+ tloadr r1, MULTI_ADDRESS_DATA+4
+ tloadr r3, MULTI_ADDRESS_DATA+8
+ tloadrb r2, [r1,#0]
+ tstorerb r2, [r0,#0]
Review Comment:
please change to TABs
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[GitHub] [incubator-nuttx] CV-Bowen commented on pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#issuecomment-1118134931
CI failed, because mixed case identifier found in arch/arm/src/phy62xx/* and boards/arm/stm32l4/nucleo-l476rg/*, it seems unrelated to this pr.
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[GitHub] [incubator-nuttx] CV-Bowen commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r866574550
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,593 @@
+/********************************************************************************************************
Review Comment:
I have changed the license to Apache.
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[GitHub] [incubator-nuttx] CV-Bowen commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r866631152
##########
arch/arm/src/tlsr82/tc32/tc32_exception.S:
##########
@@ -0,0 +1,234 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82xx/tc32/tc32_exception.S
Review Comment:
Yes and Done.
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[GitHub] [incubator-nuttx] CV-Bowen commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r865728400
##########
arch/arm/src/tlsr82/tc32/tc32_exception.S:
##########
@@ -0,0 +1,234 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82xx/tc32/tc32_exception.S
Review Comment:
Yes, the common exception implementation is in cstartup_flash.S, __irq, line 411.
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[GitHub] [incubator-nuttx] CV-Bowen commented on pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#issuecomment-1118466085
@pkarashchenko i remove all the FAR and format the Make.defs, but about the license problem, i need more time to discuss with vendor.
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[GitHub] [incubator-nuttx] CV-Bowen commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r865824269
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
Review Comment:
@xiaoxiang781216 Done
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[GitHub] [incubator-nuttx] CV-Bowen commented on pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
CV-Bowen commented on PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#issuecomment-1120116157
It seems github treats tab as 8 spaces, i format file cstartup_flash.S again.
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r865591251
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
+CMN_CSRCS += arm_usestack.c arm_createstack.c arm_stackframe.c
+CMN_CSRCS += arm_releasepending.c arm_puts.c arm_pthread_start.c
+CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
+CMN_CSRCS += arm_blocktask.c arm_unblocktask.c arm_reprioritizertr.c
+CMN_CSRCS += arm_checkstack.c arm_exit.c arm_sigdeliver.c
+CMN_CSRCS += arm_releasestack.c arm_task_start.c arm_allocateheap.c
+CMN_CSRCS += arm_assert.c arm_lowputs.c arm_mdelay.c
+
+# Chip arch related files in arch/arm/tlsr82/tc32
+CHIP_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
+
+CHIP_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
+CHIP_CSRCS += tc32_syscall.c tc32_udelay.c
+
+ifeq ($(CONFIG_SCHED_BACKTRACE),y)
+CHIP_CSRCS += tc32_backtrace.c
+endif
+
+# Chip devices related files in arch/arm/tlsr82
+CHIP_CSRCS += tlsr82_start.c tlsr82_irq.c tlsr82_gpio.c tlsr82_timer_isr.c
+CHIP_CSRCS += tlsr82_serial.c tlsr82_gpio_cfg.c tlsr82_analog.c
+CHIP_CSRCS += tlsr82_clock.c tlsr82_cpu.c tlsr82_flash.c tlsr82_flash_mtd.c
+
+ifeq ($(CONFIG_TLSR82_SPI),y)
+CHIP_CSRCS += tlsr82_spi_console.c
+endif
+
+ifeq ($(CONFIG_TLSR82_TIMER),y)
+CHIP_CSRCS += tlsr82_timer.c tlsr82_timer_lowerhalf.c
Review Comment:
Optional
```suggestion
CHIP_CSRCS += tlsr82_timer.c tlsr82_timer_lowerhalf.c
```
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
+CMN_CSRCS += arm_usestack.c arm_createstack.c arm_stackframe.c
+CMN_CSRCS += arm_releasepending.c arm_puts.c arm_pthread_start.c
+CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
+CMN_CSRCS += arm_blocktask.c arm_unblocktask.c arm_reprioritizertr.c
+CMN_CSRCS += arm_checkstack.c arm_exit.c arm_sigdeliver.c
+CMN_CSRCS += arm_releasestack.c arm_task_start.c arm_allocateheap.c
+CMN_CSRCS += arm_assert.c arm_lowputs.c arm_mdelay.c
+
+# Chip arch related files in arch/arm/tlsr82/tc32
+CHIP_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
+
+CHIP_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
+CHIP_CSRCS += tc32_syscall.c tc32_udelay.c
+
+ifeq ($(CONFIG_SCHED_BACKTRACE),y)
+CHIP_CSRCS += tc32_backtrace.c
+endif
+
+# Chip devices related files in arch/arm/tlsr82
+CHIP_CSRCS += tlsr82_start.c tlsr82_irq.c tlsr82_gpio.c tlsr82_timer_isr.c
+CHIP_CSRCS += tlsr82_serial.c tlsr82_gpio_cfg.c tlsr82_analog.c
+CHIP_CSRCS += tlsr82_clock.c tlsr82_cpu.c tlsr82_flash.c tlsr82_flash_mtd.c
+
+ifeq ($(CONFIG_TLSR82_SPI),y)
+CHIP_CSRCS += tlsr82_spi_console.c
+endif
+
+ifeq ($(CONFIG_TLSR82_TIMER),y)
+CHIP_CSRCS += tlsr82_timer.c tlsr82_timer_lowerhalf.c
+ ifeq ($(CONFIG_TLSR82_WATCHDOG), y)
+ CHIP_CSRCS += tlsr82_watchdog.c
Review Comment:
```suggestion
CHIP_CSRCS += tlsr82_watchdog.c
```
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
+CMN_CSRCS += arm_usestack.c arm_createstack.c arm_stackframe.c
+CMN_CSRCS += arm_releasepending.c arm_puts.c arm_pthread_start.c
+CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
+CMN_CSRCS += arm_blocktask.c arm_unblocktask.c arm_reprioritizertr.c
+CMN_CSRCS += arm_checkstack.c arm_exit.c arm_sigdeliver.c
+CMN_CSRCS += arm_releasestack.c arm_task_start.c arm_allocateheap.c
+CMN_CSRCS += arm_assert.c arm_lowputs.c arm_mdelay.c
+
+# Chip arch related files in arch/arm/tlsr82/tc32
+CHIP_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
+
+CHIP_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
+CHIP_CSRCS += tc32_syscall.c tc32_udelay.c
+
+ifeq ($(CONFIG_SCHED_BACKTRACE),y)
+CHIP_CSRCS += tc32_backtrace.c
+endif
+
+# Chip devices related files in arch/arm/tlsr82
+CHIP_CSRCS += tlsr82_start.c tlsr82_irq.c tlsr82_gpio.c tlsr82_timer_isr.c
+CHIP_CSRCS += tlsr82_serial.c tlsr82_gpio_cfg.c tlsr82_analog.c
+CHIP_CSRCS += tlsr82_clock.c tlsr82_cpu.c tlsr82_flash.c tlsr82_flash_mtd.c
+
+ifeq ($(CONFIG_TLSR82_SPI),y)
+CHIP_CSRCS += tlsr82_spi_console.c
+endif
+
+ifeq ($(CONFIG_TLSR82_TIMER),y)
+CHIP_CSRCS += tlsr82_timer.c tlsr82_timer_lowerhalf.c
+ ifeq ($(CONFIG_TLSR82_WATCHDOG), y)
+ CHIP_CSRCS += tlsr82_watchdog.c
+ endif
+endif
+
+ifeq ($(CONFIG_TLSR82_PWM),y)
+CHIP_CSRCS += tlsr82_pwm.c
Review Comment:
Optional
```suggestion
CHIP_CSRCS += tlsr82_pwm.c
```
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
+CMN_CSRCS += arm_usestack.c arm_createstack.c arm_stackframe.c
+CMN_CSRCS += arm_releasepending.c arm_puts.c arm_pthread_start.c
+CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
+CMN_CSRCS += arm_blocktask.c arm_unblocktask.c arm_reprioritizertr.c
+CMN_CSRCS += arm_checkstack.c arm_exit.c arm_sigdeliver.c
+CMN_CSRCS += arm_releasestack.c arm_task_start.c arm_allocateheap.c
+CMN_CSRCS += arm_assert.c arm_lowputs.c arm_mdelay.c
+
+# Chip arch related files in arch/arm/tlsr82/tc32
+CHIP_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
+
+CHIP_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
+CHIP_CSRCS += tc32_syscall.c tc32_udelay.c
+
+ifeq ($(CONFIG_SCHED_BACKTRACE),y)
+CHIP_CSRCS += tc32_backtrace.c
Review Comment:
```suggestion
CHIP_CSRCS += tc32_backtrace.c
```
##########
arch/arm/src/tlsr82/chip/b87/boot/cstartup_flash.S:
##########
@@ -0,0 +1,593 @@
+/********************************************************************************************************
Review Comment:
So this file is not licensed with Apache?
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
Review Comment:
```suggestion
static void **g_backtrace_code_regions;
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
Review Comment:
do we need this?
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
Review Comment:
```suggestion
* return (*(uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
+{
+ int i = 0;
+
+#if 0
+ if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
+ (uintptr_t)pc < (uintptr_t)_END_TEXT)
+ {
+ return true;
+ }
+#endif
+
+ if (g_backtrace_code_regions)
+ {
+ while (g_backtrace_code_regions[i] &&
+ (g_backtrace_code_regions[i] !=
+ g_backtrace_code_regions[i + 1]))
+ {
+ if (g_backtrace_code_regions[i] <= pc &&
+ g_backtrace_code_regions[i + 1] > pc)
+ {
+ return true;
+ }
+
+ i += 2;
+ }
+ }
+
+ return false;
+}
+
+/****************************************************************************
+ * Name: backtrace_push_internal
+ *
+ * Description:
+ * backtrace_push_internal() returns the currect link address from
+ * program counter and stack pointer
+ *
+ * Input Parameters:
+ * psp - Double poninter to the SP, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ * ppc - Double poninter to the PC, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ *
+ * Returned Value:
+ * Link address should be returned if successful
+ * Otherwise, NULL is returned
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static FAR void *backtrace_push_internal(FAR void **psp,
+ FAR void **ppc)
+{
+ FAR uint8_t *sp = *psp;
+ FAR uint8_t *pc = *ppc;
+ FAR uint8_t *base;
+ FAR uint8_t *lr;
+ uint16_t ins16;
+ int offset = 1;
+ bool found;
+ int frame;
+ int i;
+#ifdef CONFIG_ALLSYMS
+ FAR const struct symtab_s *symbol;
Review Comment:
```suggestion
const struct symtab_s *symbol;
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
+{
+ int i = 0;
+
+#if 0
+ if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
+ (uintptr_t)pc < (uintptr_t)_END_TEXT)
+ {
+ return true;
+ }
+#endif
+
+ if (g_backtrace_code_regions)
+ {
+ while (g_backtrace_code_regions[i] &&
+ (g_backtrace_code_regions[i] !=
+ g_backtrace_code_regions[i + 1]))
+ {
+ if (g_backtrace_code_regions[i] <= pc &&
+ g_backtrace_code_regions[i + 1] > pc)
+ {
+ return true;
+ }
+
+ i += 2;
+ }
+ }
+
+ return false;
+}
+
+/****************************************************************************
+ * Name: backtrace_push_internal
+ *
+ * Description:
+ * backtrace_push_internal() returns the currect link address from
+ * program counter and stack pointer
+ *
+ * Input Parameters:
+ * psp - Double poninter to the SP, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ * ppc - Double poninter to the PC, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ *
+ * Returned Value:
+ * Link address should be returned if successful
+ * Otherwise, NULL is returned
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static FAR void *backtrace_push_internal(FAR void **psp,
+ FAR void **ppc)
+{
+ FAR uint8_t *sp = *psp;
+ FAR uint8_t *pc = *ppc;
+ FAR uint8_t *base;
+ FAR uint8_t *lr;
+ uint16_t ins16;
+ int offset = 1;
+ bool found;
+ int frame;
+ int i;
+#ifdef CONFIG_ALLSYMS
+ FAR const struct symtab_s *symbol;
+ size_t symbolsize;
+
+ symbol = allsyms_findbyvalue(pc, &symbolsize);
+ if (!symbol || !in_code_region(symbol->sym_value))
+ {
+ return NULL;
+ }
+#endif
+
+ found = false;
+
+ for (i = 0; i < INSTR_LIMIT; i += 2)
+ {
+ base = pc - i;
+ ins16 = *(FAR uint16_t *)(base);
+ if (INSTR_IS(ins16, T_PUSH))
+ {
+ /* Bit 1 number in low byte indicates the number of pushed
+ * low register, +1 for LR is alao pushed into the stack.
+ */
+
+ frame = __builtin_popcount(ins16 & 0xff) + 1;
+ ins16 = *(FAR uint16_t *)(base - 2);
+ if (INSTR_IS(ins16, T_PUSH_LO))
+ {
+ offset += __builtin_popcount(ins16 & 0xff);
+ frame += offset - 1;
+ }
+
+ found = true;
+ }
+
+ if (found)
+ {
+#ifdef CONFIG_ALLSYMS
+ if (base >= (uint8_t *)symbol->sym_value &&
+ base - (uint8_t *)symbol->sym_value < 8)
+ {
+ break;
+ }
+ else
+ {
+ found = false;
+ }
+#else
+ break;
+#endif
+ }
+ }
+
+ if (!found)
+ {
+ return NULL;
+ }
+
+ i = 0;
+
+ while (base + i < pc)
+ {
+ ins16 = *(FAR uint16_t *)(base + i);
+ if (INSTR_IS(ins16, T_SUB_SP_16))
+ {
+ /* Low 7 bit indicates the number sub to sp */
+
+ frame += (ins16 & 0x7f);
+ break;
+ }
+
+ if (INSTR_IS(ins16, T_PUSH_LO))
+ {
+ /* Bit 1 number in low 8bit indicated the number of pushed
+ * low register.
+ */
+
+ frame += __builtin_popcount(ins16 & 0xff);
+ }
+
+ /* 16bit instruction */
+
+ i += 2;
+ }
+
+ lr = (FAR uint8_t *)*((FAR uint32_t *)sp + frame - offset);
+ if (!in_code_region(lr))
+ {
+ return NULL;
+ }
+
+ offset = getlroffset(lr);
+ if (offset == 0)
+ {
+ return NULL;
+ }
+
+ *psp = (FAR uint32_t *)sp + frame;
Review Comment:
```suggestion
*psp = (uint32_t *)sp + frame;
```
##########
arch/arm/src/tlsr82/tc32/tc32_exception.S:
##########
@@ -0,0 +1,234 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82xx/tc32/tc32_exception.S
Review Comment:
seems like all the code is commented out
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
+{
+ int i = 0;
+
+#if 0
+ if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
+ (uintptr_t)pc < (uintptr_t)_END_TEXT)
+ {
+ return true;
+ }
+#endif
+
+ if (g_backtrace_code_regions)
+ {
+ while (g_backtrace_code_regions[i] &&
+ (g_backtrace_code_regions[i] !=
+ g_backtrace_code_regions[i + 1]))
+ {
+ if (g_backtrace_code_regions[i] <= pc &&
+ g_backtrace_code_regions[i + 1] > pc)
+ {
+ return true;
+ }
+
+ i += 2;
+ }
+ }
+
+ return false;
+}
+
+/****************************************************************************
+ * Name: backtrace_push_internal
+ *
+ * Description:
+ * backtrace_push_internal() returns the currect link address from
+ * program counter and stack pointer
+ *
+ * Input Parameters:
+ * psp - Double poninter to the SP, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ * ppc - Double poninter to the PC, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ *
+ * Returned Value:
+ * Link address should be returned if successful
+ * Otherwise, NULL is returned
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static FAR void *backtrace_push_internal(FAR void **psp,
+ FAR void **ppc)
+{
+ FAR uint8_t *sp = *psp;
+ FAR uint8_t *pc = *ppc;
+ FAR uint8_t *base;
+ FAR uint8_t *lr;
+ uint16_t ins16;
+ int offset = 1;
+ bool found;
+ int frame;
+ int i;
+#ifdef CONFIG_ALLSYMS
+ FAR const struct symtab_s *symbol;
+ size_t symbolsize;
+
+ symbol = allsyms_findbyvalue(pc, &symbolsize);
+ if (!symbol || !in_code_region(symbol->sym_value))
+ {
+ return NULL;
+ }
+#endif
+
+ found = false;
+
+ for (i = 0; i < INSTR_LIMIT; i += 2)
+ {
+ base = pc - i;
+ ins16 = *(FAR uint16_t *)(base);
+ if (INSTR_IS(ins16, T_PUSH))
+ {
+ /* Bit 1 number in low byte indicates the number of pushed
+ * low register, +1 for LR is alao pushed into the stack.
+ */
+
+ frame = __builtin_popcount(ins16 & 0xff) + 1;
+ ins16 = *(FAR uint16_t *)(base - 2);
+ if (INSTR_IS(ins16, T_PUSH_LO))
+ {
+ offset += __builtin_popcount(ins16 & 0xff);
+ frame += offset - 1;
+ }
+
+ found = true;
+ }
+
+ if (found)
+ {
+#ifdef CONFIG_ALLSYMS
+ if (base >= (uint8_t *)symbol->sym_value &&
+ base - (uint8_t *)symbol->sym_value < 8)
+ {
+ break;
+ }
+ else
+ {
+ found = false;
+ }
+#else
+ break;
+#endif
+ }
+ }
+
+ if (!found)
+ {
+ return NULL;
+ }
+
+ i = 0;
+
+ while (base + i < pc)
+ {
+ ins16 = *(FAR uint16_t *)(base + i);
Review Comment:
```suggestion
ins16 = *(uint16_t *)(base + i);
```
##########
arch/arm/src/tlsr82/tc32/tc32_schedulesigaction.c:
##########
@@ -0,0 +1,197 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_schedulesigaction.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "tc32.h"
+#include "sched/sched.h"
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_schedule_sigaction
+ *
+ * Description:
+ * This function is called by the OS when one or more
+ * signal handling actions have been queued for execution.
+ * The architecture specific code must configure things so
+ * that the 'sigdeliver' callback is executed on the thread
+ * specified by 'tcb' as soon as possible.
+ *
+ * This function may be called from interrupt handling logic.
+ *
+ * This operation should not cause the task to be unblocked
+ * nor should it cause any immediate execution of sigdeliver.
+ * Typically, a few cases need to be considered:
+ *
+ * (1) This function may be called from an interrupt handler
+ * During interrupt processing, all xcptcontext structures
+ * should be valid for all tasks. That structure should
+ * be modified to invoke sigdeliver() either on return
+ * from (this) interrupt or on some subsequent context
+ * switch to the recipient task.
+ * (2) If not in an interrupt handler and the tcb is NOT
+ * the currently executing task, then again just modify
+ * the saved xcptcontext structure for the recipient
+ * task so it will invoke sigdeliver when that task is
+ * later resumed.
+ * (3) If not in an interrupt handler and the tcb IS the
+ * currently executing task -- just call the signal
+ * handler now.
+ *
+ * Assumptions:
+ * Called from critical section
+ *
+ ****************************************************************************/
+
+void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
+{
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+
+ /* Refuse to handle nested signal actions */
+
+ if (!tcb->xcp.sigdeliver)
+ {
+ /* First, handle some special cases when the signal is
+ * being delivered to the currently executing task.
+ */
+
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+
+ if (tcb == this_task())
+ {
+ /* CASE 1: We are not in an interrupt handler and
+ * a task is signalling itself for some reason.
+ */
+
+ if (!CURRENT_REGS)
+ {
+ /* In this case just deliver the signal now. */
+
+ sigdeliver(tcb);
+ }
+
+ /* CASE 2: We are in an interrupt handler AND the
+ * interrupted task is the same as the one that
+ * must receive the signal, then we will have to modify
+ * the return state as well as the state in the TCB.
+ *
+ * Hmmm... there looks like a latent bug here: The following
+ * logic would fail in the strange case where we are in an
+ * interrupt handler, the thread is signalling itself, but
+ * a context switch to another task has occurred so that
+ * CURRENT_REGS does not refer to the thread of this_task()!
+ */
+
+ else
+ {
+ /* Save the return lr and cpsr and one scratch register
+ * These will be restored by the signal trampoline after
+ * the signals have been delivered.
+ */
+
+ tcb->xcp.sigdeliver = sigdeliver;
+
+ /* And make sure that the saved context in the TCB
+ * is the same as the interrupt return context.
+ */
+
+ arm_savestate(tcb->xcp.saved_regs);
+
+ /* Duplicate the register context. These will be
+ * restored by the signal trampoline after the signal has been
+ * delivered.
+ */
+
+ CURRENT_REGS = (FAR void *)
Review Comment:
```suggestion
CURRENT_REGS = (void *)
```
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
Review Comment:
```suggestion
AFLAGS += -DMCU_STARTUP_FLASH
```
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
+CMN_CSRCS += arm_usestack.c arm_createstack.c arm_stackframe.c
+CMN_CSRCS += arm_releasepending.c arm_puts.c arm_pthread_start.c
+CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
+CMN_CSRCS += arm_blocktask.c arm_unblocktask.c arm_reprioritizertr.c
+CMN_CSRCS += arm_checkstack.c arm_exit.c arm_sigdeliver.c
+CMN_CSRCS += arm_releasestack.c arm_task_start.c arm_allocateheap.c
+CMN_CSRCS += arm_assert.c arm_lowputs.c arm_mdelay.c
+
+# Chip arch related files in arch/arm/tlsr82/tc32
+CHIP_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
+
+CHIP_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
+CHIP_CSRCS += tc32_syscall.c tc32_udelay.c
+
+ifeq ($(CONFIG_SCHED_BACKTRACE),y)
+CHIP_CSRCS += tc32_backtrace.c
+endif
+
+# Chip devices related files in arch/arm/tlsr82
+CHIP_CSRCS += tlsr82_start.c tlsr82_irq.c tlsr82_gpio.c tlsr82_timer_isr.c
+CHIP_CSRCS += tlsr82_serial.c tlsr82_gpio_cfg.c tlsr82_analog.c
+CHIP_CSRCS += tlsr82_clock.c tlsr82_cpu.c tlsr82_flash.c tlsr82_flash_mtd.c
+
+ifeq ($(CONFIG_TLSR82_SPI),y)
+CHIP_CSRCS += tlsr82_spi_console.c
Review Comment:
Optional
```suggestion
CHIP_CSRCS += tlsr82_spi_console.c
```
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
+CMN_CSRCS += arm_usestack.c arm_createstack.c arm_stackframe.c
+CMN_CSRCS += arm_releasepending.c arm_puts.c arm_pthread_start.c
+CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
+CMN_CSRCS += arm_blocktask.c arm_unblocktask.c arm_reprioritizertr.c
+CMN_CSRCS += arm_checkstack.c arm_exit.c arm_sigdeliver.c
+CMN_CSRCS += arm_releasestack.c arm_task_start.c arm_allocateheap.c
+CMN_CSRCS += arm_assert.c arm_lowputs.c arm_mdelay.c
+
+# Chip arch related files in arch/arm/tlsr82/tc32
+CHIP_ASRCS += tc32_fullcontextrestore.S tc32_switchcontext.S tc32_saveusercontext.S
+
+CHIP_CSRCS += tc32_doirq.c tc32_initialstate.c tc32_schedulesigaction.c
+CHIP_CSRCS += tc32_syscall.c tc32_udelay.c
+
+ifeq ($(CONFIG_SCHED_BACKTRACE),y)
+CHIP_CSRCS += tc32_backtrace.c
+endif
+
+# Chip devices related files in arch/arm/tlsr82
+CHIP_CSRCS += tlsr82_start.c tlsr82_irq.c tlsr82_gpio.c tlsr82_timer_isr.c
+CHIP_CSRCS += tlsr82_serial.c tlsr82_gpio_cfg.c tlsr82_analog.c
+CHIP_CSRCS += tlsr82_clock.c tlsr82_cpu.c tlsr82_flash.c tlsr82_flash_mtd.c
+
+ifeq ($(CONFIG_TLSR82_SPI),y)
+CHIP_CSRCS += tlsr82_spi_console.c
+endif
+
+ifeq ($(CONFIG_TLSR82_TIMER),y)
+CHIP_CSRCS += tlsr82_timer.c tlsr82_timer_lowerhalf.c
+ ifeq ($(CONFIG_TLSR82_WATCHDOG), y)
+ CHIP_CSRCS += tlsr82_watchdog.c
+ endif
+endif
+
+ifeq ($(CONFIG_TLSR82_PWM),y)
+CHIP_CSRCS += tlsr82_pwm.c
+endif
+
+ifeq ($(CONFIG_TLSR82_ADC),y)
+CHIP_CSRCS += tlsr82_adc.c
Review Comment:
Optional
```suggestion
CHIP_CSRCS += tlsr82_adc.c
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
Review Comment:
```suggestion
static int getlroffset(uint8_t *lr)
```
##########
arch/arm/src/tlsr82/hardware/tlsr82_register.h:
##########
@@ -0,0 +1,99 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/hardware/tlsr82_register.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_REGISTER_H
+#define __ARCH_ARM_SRC_TLSR82_HARDWARE_TLSR82_REGISTER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Regisger base address */
+
+#define REG_BASE_ADDR 0x00800000
+
+#define REG_ADDR8(a) getreg8(REG_BASE_ADDR + (a))
+#define REG_ADDR16(a) getreg16(REG_BASE_ADDR + (a))
+#define REG_ADDR32(a) getreg32(REG_BASE_ADDR + (a))
+
+#define write_reg8(addr,v) putreg8(v, REG_BASE_ADDR + (addr))
+#define write_reg16(addr,v) putreg16(v, REG_BASE_ADDR + (addr))
+#define write_reg32(addr,v) putreg32(v, REG_BASE_ADDR + (addr))
+
+/* Common macros definition */
+
+#define BIT(n) (1 << (n))
+#define BIT_MASK_LEN(len) (BIT(len)-1)
+#define BIT_RNG(s, e) (BIT_MASK_LEN((e) - (s) + 1) << (s))
+#define BM_SET(x, m) ((x) |= (m))
+#define BM_CLR(x, m) ((x) &= ~(m))
+#define BM_IS_SET(x, m) ((x) & (m))
+#define BM_IS_CLR(x, m) ((~x) & (m))
Review Comment:
```suggestion
#define BM_IS_CLR(x, m) ((~(x)) & (m))
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
Review Comment:
```suggestion
static bool in_code_region(void *pc)
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
+{
+ int i = 0;
+
+#if 0
+ if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
+ (uintptr_t)pc < (uintptr_t)_END_TEXT)
+ {
+ return true;
+ }
+#endif
+
+ if (g_backtrace_code_regions)
+ {
+ while (g_backtrace_code_regions[i] &&
+ (g_backtrace_code_regions[i] !=
+ g_backtrace_code_regions[i + 1]))
+ {
+ if (g_backtrace_code_regions[i] <= pc &&
+ g_backtrace_code_regions[i + 1] > pc)
+ {
+ return true;
+ }
+
+ i += 2;
+ }
+ }
+
+ return false;
+}
+
+/****************************************************************************
+ * Name: backtrace_push_internal
+ *
+ * Description:
+ * backtrace_push_internal() returns the currect link address from
+ * program counter and stack pointer
+ *
+ * Input Parameters:
+ * psp - Double poninter to the SP, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ * ppc - Double poninter to the PC, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ *
+ * Returned Value:
+ * Link address should be returned if successful
+ * Otherwise, NULL is returned
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static FAR void *backtrace_push_internal(FAR void **psp,
+ FAR void **ppc)
+{
+ FAR uint8_t *sp = *psp;
+ FAR uint8_t *pc = *ppc;
+ FAR uint8_t *base;
+ FAR uint8_t *lr;
+ uint16_t ins16;
+ int offset = 1;
+ bool found;
+ int frame;
+ int i;
+#ifdef CONFIG_ALLSYMS
+ FAR const struct symtab_s *symbol;
+ size_t symbolsize;
+
+ symbol = allsyms_findbyvalue(pc, &symbolsize);
+ if (!symbol || !in_code_region(symbol->sym_value))
+ {
+ return NULL;
+ }
+#endif
+
+ found = false;
+
+ for (i = 0; i < INSTR_LIMIT; i += 2)
+ {
+ base = pc - i;
+ ins16 = *(FAR uint16_t *)(base);
+ if (INSTR_IS(ins16, T_PUSH))
+ {
+ /* Bit 1 number in low byte indicates the number of pushed
+ * low register, +1 for LR is alao pushed into the stack.
+ */
+
+ frame = __builtin_popcount(ins16 & 0xff) + 1;
+ ins16 = *(FAR uint16_t *)(base - 2);
Review Comment:
```suggestion
ins16 = *(uint16_t *)(base - 2);
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
+{
+ int i = 0;
+
+#if 0
+ if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
+ (uintptr_t)pc < (uintptr_t)_END_TEXT)
+ {
+ return true;
+ }
+#endif
+
+ if (g_backtrace_code_regions)
+ {
+ while (g_backtrace_code_regions[i] &&
+ (g_backtrace_code_regions[i] !=
+ g_backtrace_code_regions[i + 1]))
+ {
+ if (g_backtrace_code_regions[i] <= pc &&
+ g_backtrace_code_regions[i + 1] > pc)
+ {
+ return true;
+ }
+
+ i += 2;
+ }
+ }
+
+ return false;
+}
+
+/****************************************************************************
+ * Name: backtrace_push_internal
+ *
+ * Description:
+ * backtrace_push_internal() returns the currect link address from
+ * program counter and stack pointer
+ *
+ * Input Parameters:
+ * psp - Double poninter to the SP, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ * ppc - Double poninter to the PC, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ *
+ * Returned Value:
+ * Link address should be returned if successful
+ * Otherwise, NULL is returned
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static FAR void *backtrace_push_internal(FAR void **psp,
+ FAR void **ppc)
+{
+ FAR uint8_t *sp = *psp;
+ FAR uint8_t *pc = *ppc;
+ FAR uint8_t *base;
+ FAR uint8_t *lr;
Review Comment:
```suggestion
static void *backtrace_push_internal(void **psp, void **ppc)
{
uint8_t *sp = *psp;
uint8_t *pc = *ppc;
uint8_t *base;
uint8_t *lr;
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
+{
+ int i = 0;
+
+#if 0
+ if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
Review Comment:
So PC can point to any memory?
##########
arch/arm/src/tlsr82/tc32/tc32_exception.S:
##########
@@ -0,0 +1,234 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82xx/tc32/tc32_exception.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
+ @ .global exception_common
Review Comment:
```suggestion
@ .global exception_common
```
##########
arch/arm/src/tlsr82/tc32/tc32_initialstate.c:
##########
@@ -0,0 +1,152 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_initialstate.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <debug.h>
+#include <execinfo.h>
+
+#include <nuttx/arch.h>
+
+#include "tc32.h"
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_initial_state
+ *
+ * Description:
+ * A new thread is being started and a new TCB
+ * has been created. This function is called to initialize
+ * the processor specific portions of the new TCB.
+ *
+ * This function must setup the initial architecture registers
+ * and/or stack so that execution will begin at tcb->start
+ * on the next context switch.
+ *
+ ****************************************************************************/
+
+void up_initial_state(struct tcb_s *tcb)
+{
+ struct xcptcontext *xcp = &tcb->xcp;
+ uint32_t cpsr;
+
+ /* Initialize the initial exception register context structure */
+
+ memset(xcp, 0, sizeof(struct xcptcontext));
+
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == IDLE_PROCESS_ID)
+ {
+ tcb->stack_alloc_ptr = (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE);
+ tcb->stack_base_ptr = tcb->stack_alloc_ptr;
+ tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
+
+#ifdef CONFIG_STACK_COLORATION
+ /* If stack debug is enabled, then fill the stack with a
+ * recognizable value that we can use later to test for high
+ * water marks.
+ */
+
+ arm_stack_color(tcb->stack_alloc_ptr, 0);
+#endif /* CONFIG_STACK_COLORATION */
+
+ return;
+ }
+
+ /* Initialize the context registers to stack top */
+
+ xcp->regs = (FAR void *)((uint32_t)tcb->stack_base_ptr +
Review Comment:
```suggestion
xcp->regs = (void *)((uint32_t)tcb->stack_base_ptr +
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
+{
+ int i = 0;
+
+#if 0
+ if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
+ (uintptr_t)pc < (uintptr_t)_END_TEXT)
+ {
+ return true;
+ }
+#endif
+
+ if (g_backtrace_code_regions)
+ {
+ while (g_backtrace_code_regions[i] &&
+ (g_backtrace_code_regions[i] !=
+ g_backtrace_code_regions[i + 1]))
+ {
+ if (g_backtrace_code_regions[i] <= pc &&
+ g_backtrace_code_regions[i + 1] > pc)
+ {
+ return true;
+ }
+
+ i += 2;
+ }
+ }
+
+ return false;
+}
+
+/****************************************************************************
+ * Name: backtrace_push_internal
+ *
+ * Description:
+ * backtrace_push_internal() returns the currect link address from
+ * program counter and stack pointer
+ *
+ * Input Parameters:
+ * psp - Double poninter to the SP, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ * ppc - Double poninter to the PC, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ *
+ * Returned Value:
+ * Link address should be returned if successful
+ * Otherwise, NULL is returned
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static FAR void *backtrace_push_internal(FAR void **psp,
+ FAR void **ppc)
+{
+ FAR uint8_t *sp = *psp;
+ FAR uint8_t *pc = *ppc;
+ FAR uint8_t *base;
+ FAR uint8_t *lr;
+ uint16_t ins16;
+ int offset = 1;
+ bool found;
+ int frame;
+ int i;
+#ifdef CONFIG_ALLSYMS
+ FAR const struct symtab_s *symbol;
+ size_t symbolsize;
+
+ symbol = allsyms_findbyvalue(pc, &symbolsize);
+ if (!symbol || !in_code_region(symbol->sym_value))
+ {
+ return NULL;
+ }
+#endif
+
+ found = false;
+
+ for (i = 0; i < INSTR_LIMIT; i += 2)
+ {
+ base = pc - i;
+ ins16 = *(FAR uint16_t *)(base);
+ if (INSTR_IS(ins16, T_PUSH))
+ {
+ /* Bit 1 number in low byte indicates the number of pushed
+ * low register, +1 for LR is alao pushed into the stack.
+ */
+
+ frame = __builtin_popcount(ins16 & 0xff) + 1;
+ ins16 = *(FAR uint16_t *)(base - 2);
+ if (INSTR_IS(ins16, T_PUSH_LO))
+ {
+ offset += __builtin_popcount(ins16 & 0xff);
+ frame += offset - 1;
+ }
+
+ found = true;
+ }
+
+ if (found)
+ {
+#ifdef CONFIG_ALLSYMS
+ if (base >= (uint8_t *)symbol->sym_value &&
+ base - (uint8_t *)symbol->sym_value < 8)
+ {
+ break;
+ }
+ else
+ {
+ found = false;
+ }
+#else
+ break;
+#endif
+ }
+ }
+
+ if (!found)
+ {
+ return NULL;
+ }
+
+ i = 0;
+
+ while (base + i < pc)
+ {
+ ins16 = *(FAR uint16_t *)(base + i);
+ if (INSTR_IS(ins16, T_SUB_SP_16))
+ {
+ /* Low 7 bit indicates the number sub to sp */
+
+ frame += (ins16 & 0x7f);
+ break;
+ }
+
+ if (INSTR_IS(ins16, T_PUSH_LO))
+ {
+ /* Bit 1 number in low 8bit indicated the number of pushed
+ * low register.
+ */
+
+ frame += __builtin_popcount(ins16 & 0xff);
+ }
+
+ /* 16bit instruction */
+
+ i += 2;
+ }
+
+ lr = (FAR uint8_t *)*((FAR uint32_t *)sp + frame - offset);
Review Comment:
```suggestion
lr = (uint8_t *)*((uint32_t *)sp + frame - offset);
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
+
+ if (((uintptr_t)lr & 0xffffffe0) == 0xffffffe0)
+ {
+ return 0;
+ }
+
+ /* Always return 4, only tjl (32bit instruction) jump with lr in tc32
+ * return (*(FAR uint16_t *)(lr - 4) & 0xf000) == 0xf000 ? 5 : 3;
+ */
+
+ return 4;
+}
+
+/****************************************************************************
+ * Name: in_code_region
+ *
+ * Description:
+ * in_code_region() check if the program counter is in the program
+ * section, program counter should always be within the view of executable
+ * sections.
+ *
+ * Input Parameters:
+ * pc - Program counter address
+ *
+ * Returned Value:
+ * A boolean value: true the counter is vaild
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static bool in_code_region(FAR void *pc)
+{
+ int i = 0;
+
+#if 0
+ if ((uintptr_t)pc >= (uintptr_t)_START_TEXT &&
+ (uintptr_t)pc < (uintptr_t)_END_TEXT)
+ {
+ return true;
+ }
+#endif
+
+ if (g_backtrace_code_regions)
+ {
+ while (g_backtrace_code_regions[i] &&
+ (g_backtrace_code_regions[i] !=
+ g_backtrace_code_regions[i + 1]))
+ {
+ if (g_backtrace_code_regions[i] <= pc &&
+ g_backtrace_code_regions[i + 1] > pc)
+ {
+ return true;
+ }
+
+ i += 2;
+ }
+ }
+
+ return false;
+}
+
+/****************************************************************************
+ * Name: backtrace_push_internal
+ *
+ * Description:
+ * backtrace_push_internal() returns the currect link address from
+ * program counter and stack pointer
+ *
+ * Input Parameters:
+ * psp - Double poninter to the SP, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ * ppc - Double poninter to the PC, this parameter will be changed if
+ * the corresponding LR address is successfully found.
+ *
+ * Returned Value:
+ * Link address should be returned if successful
+ * Otherwise, NULL is returned
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static FAR void *backtrace_push_internal(FAR void **psp,
+ FAR void **ppc)
+{
+ FAR uint8_t *sp = *psp;
+ FAR uint8_t *pc = *ppc;
+ FAR uint8_t *base;
+ FAR uint8_t *lr;
+ uint16_t ins16;
+ int offset = 1;
+ bool found;
+ int frame;
+ int i;
+#ifdef CONFIG_ALLSYMS
+ FAR const struct symtab_s *symbol;
+ size_t symbolsize;
+
+ symbol = allsyms_findbyvalue(pc, &symbolsize);
+ if (!symbol || !in_code_region(symbol->sym_value))
+ {
+ return NULL;
+ }
+#endif
+
+ found = false;
+
+ for (i = 0; i < INSTR_LIMIT; i += 2)
+ {
+ base = pc - i;
+ ins16 = *(FAR uint16_t *)(base);
Review Comment:
```suggestion
ins16 = *(uint16_t *)(base);
```
##########
arch/arm/src/tlsr82/tc32/tc32_backtrace.c:
##########
@@ -0,0 +1,563 @@
+/****************************************************************************
+ * arch/arm/src/tlsr82/tc32/tc32_backtrace.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/allsyms.h>
+
+#include "sched/sched.h"
+
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if 1
+
+/* Macro and definitions for simple decoding of instuctions.
+ * To check an instruction, it is ANDed with the IMASK_ and
+ * the result is compared with the IOP_. The macro INSTR_IS
+ * does this and returns !0 to indicate a match.
+ */
+
+#define INSTR_IS(i, o) (((i) & (IMASK_##o)) == (IOP_##o))
+
+#define IMASK_T_PUSH_LO 0xff00 /* push {reglist} (not LR) */
+#define IOP_T_PUSH_LO 0x6400
+
+#define IMASK_T_PUSH 0xff00 /* push {reglist} (inc LR) */
+#define IOP_T_PUSH 0x6500
+
+#define IMASK_T_SUB_SP_16 0xff80 /* sub sp, # */
+#define IOP_T_SUB_SP_16 0x6080
+
+#define IMASK_T_BL 0xf000 /* bl */
+#define IOP_T_BL 0x9000
+
+#define INSTR_LIMIT 0x2000
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR void **g_backtrace_code_regions;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: getlroffset
+ *
+ * Description:
+ * getlroffset() returns the currect link address offset.
+ *
+ * Input Parameters:
+ * lr - Link register address
+ *
+ * Returned Value:
+ * Link address offset, 0 is returned if the lr is invalid.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MM_KASAN
+__attribute__((no_sanitize_address))
+#endif
+static int getlroffset(FAR uint8_t *lr)
+{
+ lr = (FAR uint8_t *)((uintptr_t)lr & 0xfffffffe);
Review Comment:
```suggestion
lr = (uint8_t *)((uintptr_t)lr & 0xfffffffe);
```
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r865603512
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
Review Comment:
let's use include common Makefile, e.g.:
common/Make.defs or armv6-m/Make.defs
Please reference PR https://github.com/apache/incubator-nuttx/pull/6165
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179#discussion_r865757072
##########
arch/arm/src/tlsr82/Make.defs:
##########
@@ -0,0 +1,87 @@
+############################################################################
+# arch/tc32/src/tlsr82/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = cstartup_flash.S
+
+# Arch Flags
+AFLAGS +=-DMCU_STARTUP_FLASH
+
+# Common files in arch/arm/common
+CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_idle.c
Review Comment:
fileter-out can help on this, it's already used in several place.
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[GitHub] [incubator-nuttx] xiaoxiang781216 merged pull request #6179: tlsr82: first commit of telink tlsr82xx chip port.
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 merged PR #6179:
URL: https://github.com/apache/incubator-nuttx/pull/6179
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