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Posted to commits@nuttx.apache.org by xi...@apache.org on 2021/10/17 05:56:28 UTC
[incubator-nuttx] branch master updated (d2bc011 -> 7b43d11)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from d2bc011 arch/xtensa/xtensa_cpupause.c: Allow a spin before taking the g_cpu_wait spinlock.
new f2c2323 esp32_intercpu_interrupt.c: Force the functions to internal SRAM.
new d1ecb8b esp32.ld: Force some of libarch.a symbols to internal SRAM. They are used when the cache is disabled.
new 1de17c3 esp32.ld: Force some of libsched.a symbols to internal SRAM. They are used when the cache is disabled.
new dfe1637 esp32_spiflash.c: Pause the other CPU during flash operation.
new eeb68bd xtensa_testset.c: Simplify the test-set function and remove some old comments.
new f54a929 esp32_spiflash.c: Keep the index of the other CPU between SPI Flash operations.
new 7b43d11 esp32_spiflash.c: Allocate only one variable to hold the cache state in single CPU mode.
The 7 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/xtensa/src/common/xtensa_testset.c | 33 +++------------------
arch/xtensa/src/esp32/esp32_intercpu_interrupt.c | 8 ++---
arch/xtensa/src/esp32/esp32_spiflash.c | 37 ++++++++++++------------
boards/xtensa/esp32/common/scripts/esp32.ld | 36 +++++++++++++++++++++++
4 files changed, 63 insertions(+), 51 deletions(-)
[incubator-nuttx] 05/07: xtensa_testset.c: Simplify the test-set
function and remove some old comments.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit eeb68bda3d808aba0dace20b72eef3a889bfe7fc
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Oct 13 10:32:24 2021 +0200
xtensa_testset.c: Simplify the test-set function and remove some old
comments.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/common/xtensa_testset.c | 33 ++++-----------------------------
1 file changed, 4 insertions(+), 29 deletions(-)
diff --git a/arch/xtensa/src/common/xtensa_testset.c b/arch/xtensa/src/common/xtensa_testset.c
index 169ff10..4753926 100644
--- a/arch/xtensa/src/common/xtensa_testset.c
+++ b/arch/xtensa/src/common/xtensa_testset.c
@@ -56,8 +56,9 @@ static inline uint32_t xtensa_compareset(volatile uint32_t *addr,
__asm__ __volatile__
(
"WSR %2, SCOMPARE1\n" /* Initialize SCOMPARE1 */
- "S32C1I %0, %1, 0\n" /* Store id into the lock, if the lock is the
- * same as comparel. Otherwise, no write-access */
+ "S32C1I %0, %1, 0\n" /* Store the compare value into the lock,
+ * if the lock is the same as compare1.
+ * Otherwise, no write-access */
: "=r"(set) : "r"(addr), "r"(compare), "0"(set)
);
@@ -90,36 +91,10 @@ static inline uint32_t xtensa_compareset(volatile uint32_t *addr,
spinlock_t up_testset(volatile spinlock_t *lock)
{
- spinlock_t prev;
-
/* Perform the 32-bit compare and set operation */
- prev = xtensa_compareset((volatile uint32_t *)lock,
+ return xtensa_compareset((volatile uint32_t *)lock,
SP_UNLOCKED, SP_LOCKED);
-
- /* xtensa_compareset() should return either SP_UNLOCKED if the spinlock
- * was locked or SP_LOCKED or possibly ~SP_UNLOCKED if the spinlock was
- * not locked:
- *
- * "In the RE-2013.0 release and after, there is a slight change in the
- * semantics of the S32C1I instruction. Nothing is changed about the
- * operation on memory. In rare cases the resulting value in register
- * at can be different in this and later releases. The rule still holds
- * that memory has been written if and only if the register result
- * equals SCOMPARE1.
- *
- * "The difference is that in some cases where memory has not been
- * written, the instruction returns ~SCOMPARE1 instead of the current
- * value of memory. Although this change can, in principle, affect
- * the operation of code, scanning all internal Cadence code produced
- * no examples where this change would change the operation of the
- * code."
- *
- * In any case, the return value of SP_UNLOCKED can be trusted and will
- * always mean that the spinlock was set.
- */
-
- return (prev == SP_UNLOCKED) ? SP_UNLOCKED : SP_LOCKED;
}
#endif /* CONFIG_SPINLOCK */
[incubator-nuttx] 06/07: esp32_spiflash.c: Keep the index of the
other CPU between SPI Flash operations.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit f54a9290015e2525223a8dac377efbfc8d48ca58
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Oct 13 11:11:47 2021 +0200
esp32_spiflash.c: Keep the index of the other CPU between SPI Flash
operations.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/esp32/esp32_spiflash.c | 31 ++++++++++++-------------------
1 file changed, 12 insertions(+), 19 deletions(-)
diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c
index 3f90bc8..5060473 100644
--- a/arch/xtensa/src/esp32/esp32_spiflash.c
+++ b/arch/xtensa/src/esp32/esp32_spiflash.c
@@ -161,6 +161,9 @@ struct spiflash_map_req
struct spiflash_cachestate_s
{
int cpu;
+#ifdef CONFIG_SMP
+ int other;
+#endif
irqstate_t flags;
uint32_t val[2];
};
@@ -405,26 +408,23 @@ static inline void spi_reset_regbits(struct esp32_spiflash_s *priv,
static inline void IRAM_ATTR
esp32_spiflash_opstart(struct spiflash_cachestate_s *state)
{
-#ifdef CONFIG_SMP
- int other;
-#endif
-
state->flags = enter_critical_section();
state->cpu = up_cpu_index();
#ifdef CONFIG_SMP
- other = state->cpu ? 0 : 1;
+ state->other = state->cpu ? 0 : 1;
#endif
DEBUGASSERT(state->cpu == 0 || state->cpu == 1);
#ifdef CONFIG_SMP
- DEBUGASSERT(other == 0 || other == 1);
- up_cpu_pause(other);
+ DEBUGASSERT(state->other == 0 || state->other == 1);
+ DEBUGASSERT(state->other != state->cpu);
+ up_cpu_pause(state->other);
#endif
spi_disable_cache(state->cpu, &state->val[state->cpu]);
#ifdef CONFIG_SMP
- spi_disable_cache(other, &state->val[other]);
+ spi_disable_cache(state->other, &state->val[state->other]);
#endif
}
@@ -439,23 +439,16 @@ static inline void IRAM_ATTR
static inline void IRAM_ATTR
esp32_spiflash_opdone(const struct spiflash_cachestate_s *state)
{
-#ifdef CONFIG_SMP
- int other;
-#endif
-
-#ifdef CONFIG_SMP
- other = state->cpu ? 0 : 1;
-#endif
-
DEBUGASSERT(state->cpu == 0 || state->cpu == 1);
#ifdef CONFIG_SMP
- DEBUGASSERT(other == 0 || other == 1);
+ DEBUGASSERT(state->other == 0 || state->other == 1);
+ DEBUGASSERT(state->other != state->cpu);
#endif
spi_enable_cache(state->cpu, state->val[state->cpu]);
#ifdef CONFIG_SMP
- spi_enable_cache(other, state->val[other]);
- up_cpu_resume(other);
+ spi_enable_cache(state->other, state->val[state->other]);
+ up_cpu_resume(state->other);
#endif
leave_critical_section(state->flags);
[incubator-nuttx] 01/07: esp32_intercpu_interrupt.c: Force the
functions to internal SRAM.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit f2c23236429dfcde7155e42d8287f641c7e6f099
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Jul 21 10:12:22 2021 +0200
esp32_intercpu_interrupt.c: Force the functions to internal SRAM.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/esp32/esp32_intercpu_interrupt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c
index 09b2d21..115a0e2 100644
--- a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c
+++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c
@@ -48,7 +48,7 @@
*
****************************************************************************/
-static int esp32_fromcpu_interrupt(int fromcpu)
+static int IRAM_ATTR esp32_fromcpu_interrupt(int fromcpu)
{
uintptr_t regaddr;
@@ -80,12 +80,12 @@ static int esp32_fromcpu_interrupt(int fromcpu)
*
****************************************************************************/
-int esp32_fromcpu0_interrupt(int irq, void *context, void *arg)
+int IRAM_ATTR esp32_fromcpu0_interrupt(int irq, void *context, void *arg)
{
return esp32_fromcpu_interrupt(0);
}
-int esp32_fromcpu1_interrupt(int irq, void *context, void *arg)
+int IRAM_ATTR esp32_fromcpu1_interrupt(int irq, void *context, void *arg)
{
return esp32_fromcpu_interrupt(1);
}
@@ -98,7 +98,7 @@ int esp32_fromcpu1_interrupt(int irq, void *context, void *arg)
*
****************************************************************************/
-int xtensa_intercpu_interrupt(int tocpu, int intcode)
+int IRAM_ATTR xtensa_intercpu_interrupt(int tocpu, int intcode)
{
int fromcpu;
[incubator-nuttx] 04/07: esp32_spiflash.c: Pause the other CPU
during flash operation.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit dfe16378645d6ec4680aecd9a7124d03ced65bae
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Sep 29 14:08:17 2021 +0200
esp32_spiflash.c: Pause the other CPU during flash operation.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/esp32/esp32_spiflash.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c
index 295bfec..3f90bc8 100644
--- a/arch/xtensa/src/esp32/esp32_spiflash.c
+++ b/arch/xtensa/src/esp32/esp32_spiflash.c
@@ -419,6 +419,7 @@ static inline void IRAM_ATTR
DEBUGASSERT(state->cpu == 0 || state->cpu == 1);
#ifdef CONFIG_SMP
DEBUGASSERT(other == 0 || other == 1);
+ up_cpu_pause(other);
#endif
spi_disable_cache(state->cpu, &state->val[state->cpu]);
@@ -454,6 +455,7 @@ static inline void IRAM_ATTR
spi_enable_cache(state->cpu, state->val[state->cpu]);
#ifdef CONFIG_SMP
spi_enable_cache(other, state->val[other]);
+ up_cpu_resume(other);
#endif
leave_critical_section(state->flags);
[incubator-nuttx] 03/07: esp32.ld: Force some of libsched.a symbols
to internal SRAM. They are used when the cache is disabled.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 1de17c364f3e1ab10a17e5f360d7ca00eb7260c0
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Fri Jul 23 11:34:10 2021 +0200
esp32.ld: Force some of libsched.a symbols to internal SRAM. They are used
when the cache is disabled.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
boards/xtensa/esp32/common/scripts/esp32.ld | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/boards/xtensa/esp32/common/scripts/esp32.ld b/boards/xtensa/esp32/common/scripts/esp32.ld
index 28e388f..0996b09 100644
--- a/boards/xtensa/esp32/common/scripts/esp32.ld
+++ b/boards/xtensa/esp32/common/scripts/esp32.ld
@@ -76,6 +76,14 @@ SECTIONS
*libarch.a:xtensa_copystate.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_interruptcontext.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
+
+ *libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
+ *libsched.a:sched_note.*(.literal .text .literal.* .text.*)
+ *libsched.a:sched_thistask.*(.literal .text .literal.* .text.*)
+ *libsched.a:spinlock.*(.literal .text .literal.* .text.*)
+ *libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
+ *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
+
*(.wifirxiram .wifirxiram.*)
*(.wifi0iram .wifi0iram.*)
*(.wifislpiram .wifislpiram.*)
@@ -127,6 +135,14 @@ SECTIONS
*libarch.a:xtensa_copystate.*(.bss .bss.* COMMON)
*libarch.a:xtensa_interruptcontext.*(.bss .bss.* COMMON)
*libarch.a:xtensa_testset.*(.bss .bss.* COMMON)
+
+ *libsched.a:sched_suspendscheduler.*(.bss .bss.* COMMON)
+ *libsched.a:sched_thistask.*(.bss .bss.* COMMON)
+ *libsched.a:sched_note.*(.bss .bss.* COMMON)
+ *libsched.a:spinlock.*(.bss .bss.* COMMON)
+ *libsched.a:irq_csection.*(.bss .bss.* COMMON)
+ *libsched.a:irq_dispatch.*(.bss .bss.* COMMON)
+
. = ALIGN(8);
_bss_end = ABSOLUTE(.);
_ebss = ABSOLUTE(.);
@@ -172,6 +188,14 @@ SECTIONS
*libarch.a:xtensa_copystate.*(.rodata .rodata.*)
*libarch.a:xtensa_interruptcontext.*(.rodata .rodata.*)
*libarch.a:xtensa_testset.*(.rodata .rodata.*)
+
+ *libsched.a:sched_suspendscheduler.*(.rodata .rodata.*)
+ *libsched.a:sched_thistask.*(.rodata .rodata.*)
+ *libsched.a:sched_note.*(.rodata .rodata.*)
+ *libsched.a:spinlock.*(.rodata .rodata.*)
+ *libsched.a:irq_csection.*(.rodata .rodata.*)
+ *libsched.a:irq_dispatch.*(.rodata .rodata.*)
+
. = ALIGN(4);
_edata = ABSOLUTE(.);
[incubator-nuttx] 07/07: esp32_spiflash.c: Allocate only one
variable to hold the cache state in single CPU mode.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 7b43d114357d772ed3259de35e134fe30dc75586
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Oct 13 12:44:53 2021 +0200
esp32_spiflash.c: Allocate only one variable to hold the cache state in
single CPU mode.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/esp32/esp32_spiflash.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c
index 5060473..7c085ab 100644
--- a/arch/xtensa/src/esp32/esp32_spiflash.c
+++ b/arch/xtensa/src/esp32/esp32_spiflash.c
@@ -59,6 +59,12 @@
* Pre-processor Definitions
****************************************************************************/
+/* Used in spiflash_cachestate_s structure even when SMP is disabled. */
+
+#ifndef CONFIG_SMP_NCPUS
+# define CONFIG_SMP_NCPUS 1
+#endif
+
#define SPI_FLASH_WRITE_BUF_SIZE (32)
#define SPI_FLASH_READ_BUF_SIZE (64)
@@ -165,7 +171,7 @@ struct spiflash_cachestate_s
int other;
#endif
irqstate_t flags;
- uint32_t val[2];
+ uint32_t val[CONFIG_SMP_NCPUS];
};
/****************************************************************************
[incubator-nuttx] 02/07: esp32.ld: Force some of libarch.a symbols
to internal SRAM. They are used when the cache is disabled.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d1ecb8b2e64c79b1669b39173229b64ba77276be
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Jul 21 10:16:49 2021 +0200
esp32.ld: Force some of libarch.a symbols to internal SRAM. They are used
when the cache is disabled.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
boards/xtensa/esp32/common/scripts/esp32.ld | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/boards/xtensa/esp32/common/scripts/esp32.ld b/boards/xtensa/esp32/common/scripts/esp32.ld
index f047908..28e388f 100644
--- a/boards/xtensa/esp32/common/scripts/esp32.ld
+++ b/boards/xtensa/esp32/common/scripts/esp32.ld
@@ -72,6 +72,10 @@ SECTIONS
*(.iram1 .iram1.*)
*librtc.a:(.literal .text .literal.* .text.*)
*libarch.a:esp32_spiflash.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_copystate.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_interruptcontext.*(.literal .text .literal.* .text.*)
+ *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
*(.wifirxiram .wifirxiram.*)
*(.wifi0iram .wifi0iram.*)
*(.wifislpiram .wifislpiram.*)
@@ -119,6 +123,10 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(COMMON)
*libarch.a:esp32_spiflash.*(.bss .bss.* COMMON)
+ *libarch.a:xtensa_cpupause.*(.bss .bss.* COMMON)
+ *libarch.a:xtensa_copystate.*(.bss .bss.* COMMON)
+ *libarch.a:xtensa_interruptcontext.*(.bss .bss.* COMMON)
+ *libarch.a:xtensa_testset.*(.bss .bss.* COMMON)
. = ALIGN(8);
_bss_end = ABSOLUTE(.);
_ebss = ABSOLUTE(.);
@@ -160,6 +168,10 @@ SECTIONS
*(.dram1 .dram1.*)
*libphy.a:(.rodata .rodata.*)
*libarch.a:esp32_spiflash.*(.rodata .rodata.*)
+ *libarch.a:xtensa_cpupause.*(.rodata .rodata.*)
+ *libarch.a:xtensa_copystate.*(.rodata .rodata.*)
+ *libarch.a:xtensa_interruptcontext.*(.rodata .rodata.*)
+ *libarch.a:xtensa_testset.*(.rodata .rodata.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);