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Posted to commits@nuttx.apache.org by xi...@apache.org on 2023/01/16 01:41:52 UTC

[nuttx] branch master updated: esp32: Fix QEnconder reset position and small typo

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 97402f9121 esp32: Fix QEnconder reset position and small typo
97402f9121 is described below

commit 97402f9121319dce38400e6a067451d25a7df39e
Author: Alan Carvalho de Assis <ac...@gmail.com>
AuthorDate: Sun Jan 15 16:52:02 2023 -0300

    esp32: Fix QEnconder reset position and small typo
    
    The PCNT RST bit needs to be set to zeroing the counter and then
    this same bit needs to be cleared to returning counting.
---
 arch/xtensa/src/esp32/esp32_qencoder.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/xtensa/src/esp32/esp32_qencoder.c b/arch/xtensa/src/esp32/esp32_qencoder.c
index 326f27b723..3eba0ef2a5 100644
--- a/arch/xtensa/src/esp32/esp32_qencoder.c
+++ b/arch/xtensa/src/esp32/esp32_qencoder.c
@@ -463,7 +463,7 @@ static void esp32_dumpregs(struct esp32_lowerhalf_s *priv,
          getreg32(PCNT_CNT_U(6)),
          getreg32(PCNT_CNT_U(7)));
   sninfo("  PCNT_CTRL_REF: %08x\n",
-         getreg32(PCNT_CTRL_REG);
+         getreg32(PCNT_CTRL_REG));
 }
 #endif
 
@@ -607,7 +607,7 @@ static int esp32_setup(struct qe_lowerhalf_s *lower)
   esp32_gpio_matrix_in(priv->config->ch0_gpio,
                        priv->config->ch1_ctrl_sig, 0);
 
-  /* Clear the Reset bit to nable the Pulse Counter */
+  /* Clear the Reset bit to enable the Pulse Counter */
 
   regval = getreg32(PCNT_CTRL_REG);
   regval &= ~(1 << (2 * priv->config->pcntid));
@@ -710,8 +710,14 @@ static int esp32_reset(struct qe_lowerhalf_s *lower)
 
   flags = spin_lock_irqsave(&priv->lock);
 
+  /* Reset RST bit */
+
   modifyreg32(PCNT_CTRL_REG, 0, PCNT_CNT_RST_U(priv->config->pcntid));
 
+  /* Clear RST bit to enable counting again */
+
+  modifyreg32(PCNT_CTRL_REG, PCNT_CNT_RST_U(priv->config->pcntid), 0);
+
   priv->position = 0;
 
   spin_unlock_irqrestore(&priv->lock, flags);