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Posted to commits@nuttx.apache.org by pk...@apache.org on 2023/08/30 09:28:31 UTC
[nuttx] 01/07: arch/risc-v/src/mpfs/mpfs_ddr.c: Correct the DDR training dq/dqs status check
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 8fb2e4199406af51fe73e764cf8346bcbd6ae123
Author: Jukka Laitinen <ju...@ssrc.tii.ae>
AuthorDate: Thu Aug 24 10:58:09 2023 +0300
arch/risc-v/src/mpfs/mpfs_ddr.c: Correct the DDR training dq/dqs status check
It was checking a wrong register for dq/dqs window size.
Signed-off-by: Jukka Laitinen <ju...@ssrc.tii.ae>
---
arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h | 1 +
arch/risc-v/src/mpfs/mpfs_ddr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h b/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h
index 65959492be..566e1fe654 100644
--- a/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h
+++ b/arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h
@@ -654,6 +654,7 @@
#define MPFS_CFG_DDR_SGMII_PHY_GT_ERR_COMB (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_GT_ERR_COMB_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_DQ_DQS_ERR_DONE (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_DQ_DQS_ERR_DONE_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_DQDQS_STATUS1 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_DQDQS_STATUS1_OFFSET)
+#define MPFS_CFG_DDR_SGMII_PHY_DQDQS_STATUS2 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_DQDQS_STATUS2_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_GT_CLK_SEL (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_GT_CLK_SEL_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_GT_TXDLY (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_GT_TXDLY_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_DYN_CNTL_OFFSET)
diff --git a/arch/risc-v/src/mpfs/mpfs_ddr.c b/arch/risc-v/src/mpfs/mpfs_ddr.c
index b2f8b368ec..3b5806c07a 100644
--- a/arch/risc-v/src/mpfs/mpfs_ddr.c
+++ b/arch/risc-v/src/mpfs/mpfs_ddr.c
@@ -3532,7 +3532,7 @@ static int mpfs_training_verify(void)
/* Check that DQ/DQS calculated window is above 5 taps. */
- if (getreg32(MPFS_CFG_DDR_SGMII_PHY_DQDQS_STATUS1) < DQ_DQS_NUM_TAPS)
+ if (getreg32(MPFS_CFG_DDR_SGMII_PHY_DQDQS_STATUS2) < DQ_DQS_NUM_TAPS)
{
t_status |= 0x01;
}