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Posted to commits@nuttx.apache.org by ac...@apache.org on 2020/09/23 16:17:28 UTC
[incubator-nuttx] branch master updated (6696d72 -> f193f0f)
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 6696d72 boards: spresense: Adjust parameters for wifi and wifi_smp
new d67bc0c imxrt: ADC driver
new f193f0f imxrt: Style fixes in mux and ADC hardware headers
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/imxrt/Kconfig | 18 +
arch/arm/src/imxrt/Make.defs | 4 +
arch/arm/src/imxrt/hardware/imxrt_adc.h | 87 +--
arch/arm/src/imxrt/hardware/imxrt_iomuxc.h | 37 +-
.../src/imxrt/hardware/rt106x/imxrt106x_pinmux.h | 34 ++
arch/arm/src/imxrt/imxrt_adc.c | 619 +++++++++++++++++++++
.../src/{lpc43xx/lpc43_adc.h => imxrt/imxrt_adc.h} | 44 +-
boards/arm/imxrt/imxrt1060-evk/src/Makefile | 4 +
boards/arm/imxrt/imxrt1060-evk/src/imxrt1060-evk.h | 12 +
.../imxrt1060-evk/src/imxrt_adc.c} | 106 ++--
boards/arm/imxrt/imxrt1060-evk/src/imxrt_bringup.c | 10 +
11 files changed, 848 insertions(+), 127 deletions(-)
create mode 100644 arch/arm/src/imxrt/imxrt_adc.c
copy arch/arm/src/{lpc43xx/lpc43_adc.h => imxrt/imxrt_adc.h} (77%)
copy boards/arm/{stm32/stm3210e-eval/src/stm32_adc.c => imxrt/imxrt1060-evk/src/imxrt_adc.c} (66%)
[incubator-nuttx] 01/02: imxrt: ADC driver
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d67bc0c3c82dd5fb4f7b2feaae1601207c1c84ab
Author: Thomas Axelsson <th...@actia.se>
AuthorDate: Tue Sep 15 14:50:19 2020 +0200
imxrt: ADC driver
Based on LPC17xx_40xx and STM32 drivers.
---
arch/arm/src/imxrt/Kconfig | 18 +
arch/arm/src/imxrt/Make.defs | 4 +
arch/arm/src/imxrt/hardware/imxrt_adc.h | 8 +-
arch/arm/src/imxrt/hardware/imxrt_iomuxc.h | 2 +
.../src/imxrt/hardware/rt106x/imxrt106x_pinmux.h | 34 ++
arch/arm/src/imxrt/imxrt_adc.c | 619 +++++++++++++++++++++
arch/arm/src/imxrt/imxrt_adc.h | 100 ++++
boards/arm/imxrt/imxrt1060-evk/src/Makefile | 4 +
boards/arm/imxrt/imxrt1060-evk/src/imxrt1060-evk.h | 12 +
boards/arm/imxrt/imxrt1060-evk/src/imxrt_adc.c | 167 ++++++
boards/arm/imxrt/imxrt1060-evk/src/imxrt_bringup.c | 10 +
11 files changed, 974 insertions(+), 4 deletions(-)
diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig
index 8290ff5..0364e47 100644
--- a/arch/arm/src/imxrt/Kconfig
+++ b/arch/arm/src/imxrt/Kconfig
@@ -163,6 +163,10 @@ config IMXRT_LPSPI
bool
default n
+config IMXRT_ADC
+ bool
+ default n
+
config IMXRT_ENC
bool
default n
@@ -518,6 +522,20 @@ menuconfig IMXRT_LPSPI4
endmenu # LPSPI Peripherals
+menu "ADC Peripherals"
+
+menuconfig IMXRT_ADC1
+ bool "ADC1"
+ default n
+ select IMXRT_ADC
+
+menuconfig IMXRT_ADC2
+ bool "ADC2"
+ default n
+ select IMXRT_ADC
+
+endmenu
+
config IMXRT_SEMC
bool "Smart External Memory Controller (SEMC)"
default n
diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs
index 3d3b8cf..bfcefe5 100644
--- a/arch/arm/src/imxrt/Make.defs
+++ b/arch/arm/src/imxrt/Make.defs
@@ -167,3 +167,7 @@ endif
ifeq ($(CONFIG_IMXRT_USBDEV),y)
CHIP_CSRCS += imxrt_usbdev.c
endif
+
+ifeq ($(CONFIG_IMXRT_ADC),y)
+CHIP_CSRCS += imxrt_adc.c
+endif
diff --git a/arch/arm/src/imxrt/hardware/imxrt_adc.h b/arch/arm/src/imxrt/hardware/imxrt_adc.h
index de19fc8..78f04ae 100644
--- a/arch/arm/src/imxrt/hardware/imxrt_adc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_adc.h
@@ -194,10 +194,10 @@
#define ADC_CFG_ADSTS_SHIFT (8) /* Bits: 8-9 Defines the sample time duration. */
#define ADC_CFG_ADSTS_MASK (3 << ADC_CFG_ADSTS_SHIFT)
# define ADC_CFG_ADSTS(n) ((uint32_t)(n) << ADC_CFG_ADSTS_SHIFT)
-# define ADC_CFG_ADSTS_2_12 (0 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 2 if ADLSMP=0b, 12 if ADLSMP=1b */
-# define ADC_CFG_ADSTS_4_16 (1 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 4 if ADLSMP=0b, 16 if ADLSMP=1b */
-# define ADC_CFG_ADSTS_6_20 (2 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 6 if ADLSMP=0b, 20 if ADLSMP=1b */
-# define ADC_CFG_ADSTS_8_24 (3 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 8 if ADLSMP=0b, 24 if ADLSMP=1b */
+# define ADC_CFG_ADSTS_3_13 (0 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 3 if ADLSMP=0b, 13 if ADLSMP=1b */
+# define ADC_CFG_ADSTS_5_17 (1 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 5 if ADLSMP=0b, 17 if ADLSMP=1b */
+# define ADC_CFG_ADSTS_7_21 (2 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 7 if ADLSMP=0b, 21 if ADLSMP=1b */
+# define ADC_CFG_ADSTS_9_25 (3 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 9 if ADLSMP=0b, 25 if ADLSMP=1b */
#define ADC_CFG_ADHSC (1 << 10) /* Bit: 10 High Speed Configuration*/
#define ADC_CFG_REFSEL_SHIFT (11) /* Bits: 11-12 Voltage Reference Selection */
#define ADC_CFG_REFSEL_MASK (3 << ADC_CFG_REFSEL_SHIFT)
diff --git a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
index 43041f4..493bf3b 100644
--- a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
@@ -181,4 +181,6 @@
IOMUX_SPEED_LOW )
#define IOMUX_USBOTG_OC_DEFAULT (IOMUX_PULL_UP_100K)
+#define IOMUX_ADC_DEFAULT (0)
+
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_IOMUXC_H */
diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h
index 94608d0..8b71af2 100644
--- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h
+++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h
@@ -1081,4 +1081,38 @@
#define GPIO_XBAR1_INOUT19_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX))
#define GPIO_XBAR1_XBAR_IN02_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
+/* ADC */
+#define GPIO_ADC1_CH0 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX))
+#define GPIO_ADC1_CH1 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX))
+#define GPIO_ADC1_CH2 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX))
+#define GPIO_ADC1_CH3 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX))
+#define GPIO_ADC1_CH4 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX))
+#define GPIO_ADC1_CH5 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_ADC1_CH6 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_ADC1_CH7 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+#define GPIO_ADC1_CH8 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_ADC1_CH9 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX))
+#define GPIO_ADC1_CH10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX))
+#define GPIO_ADC1_CH11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_ADC1_CH12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+#define GPIO_ADC1_CH13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX))
+#define GPIO_ADC1_CH14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX))
+#define GPIO_ADC1_CH15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX))
+#define GPIO_ADC2_CH0 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX))
+#define GPIO_ADC2_CH1 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX))
+#define GPIO_ADC2_CH2 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX))
+#define GPIO_ADC2_CH3 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX))
+#define GPIO_ADC2_CH4 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX))
+#define GPIO_ADC2_CH5 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_ADC2_CH6 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_ADC2_CH7 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+#define GPIO_ADC2_CH8 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_ADC2_CH9 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX))
+#define GPIO_ADC2_CH10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX))
+#define GPIO_ADC2_CH11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_ADC2_CH12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+#define GPIO_ADC2_CH13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX))
+#define GPIO_ADC2_CH14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX))
+#define GPIO_ADC2_CH15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX))
+
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_PINMUX_H */
diff --git a/arch/arm/src/imxrt/imxrt_adc.c b/arch/arm/src/imxrt/imxrt_adc.c
new file mode 100644
index 0000000..585eb60
--- /dev/null
+++ b/arch/arm/src/imxrt/imxrt_adc.c
@@ -0,0 +1,619 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt_adc.c
+ *
+ * Copyright (C) 2020 Actia Nordic AB. All rights reserved.
+ * Author: Thomas Axelsson <th...@actia.se>
+ *
+ * Based on arch/arm/src/lpc_17xx_40xx/imxrt_adc.c
+ *
+ * Copyright (C) 2011 Li Zhuoyi. All rights reserved.
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Li Zhuoyi <lz...@gmail.com>
+ * Gregory Nutt <gn...@nuttx.org>
+ *
+ * and arch/arm/src/stm32/stm32_adc.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
+ * Authors: Gregory Nutt <gn...@nuttx.org>
+ * Diego Sanchez <ds...@nx-engineering.com>
+ * Paul Alexander Patience <pa...@polymtl.ca>
+ * Mateusz Szafoni <ra...@railab.me>
+ *
+ * This file is a part of NuttX:
+ *
+ * Copyright (C) 2010, 2013, 2016 Gregory Nutt. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <assert.h>
+#include <debug.h>
+#include <errno.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <arch/board/board.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/analog/adc.h>
+
+#include "arm_internal.h"
+#include "arm_arch.h"
+
+#include "chip.h"
+#include "hardware/imxrt_adc.h"
+#include "hardware/imxrt_pinmux.h"
+#include "imxrt_gpio.h"
+#include "imxrt_periphclks.h"
+
+#ifdef CONFIG_IMXRT_ADC
+
+/* Some ADC peripheral must be enabled */
+
+#if defined(CONFIG_IMXRT_ADC1) || defined(CONFIG_IMXRT_ADC2)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ADC_MAX_CHANNELS 16
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct imxrt_dev_s
+{
+ FAR const struct adc_callback_s *cb; /* Upper driver callback */
+ uint8_t intf; /* ADC number (i.e. ADC1, ADC2) */
+ uint32_t base; /* ADC register base */
+ uint8_t initialized; /* ADC initialization counter */
+ int irq; /* ADC IRQ number */
+ int nchannels; /* Number of configured ADC channels */
+ uint8_t chanlist[ADC_MAX_CHANNELS]; /* ADC channel list */
+ uint8_t current; /* Current channel being converted */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void adc_putreg(FAR struct imxrt_dev_s *priv, uint32_t offset,
+ uint32_t value);
+static uint32_t adc_getreg(FAR struct imxrt_dev_s *priv, uint32_t offset);
+static void adc_modifyreg(FAR struct imxrt_dev_s *priv, uint32_t offset,
+ uint32_t clearbits, uint32_t setbits);
+
+/* ADC methods */
+
+static int adc_bind(FAR struct adc_dev_s *dev,
+ FAR const struct adc_callback_s *callback);
+static void adc_reset(FAR struct adc_dev_s *dev);
+static int adc_setup(FAR struct adc_dev_s *dev);
+static void adc_shutdown(FAR struct adc_dev_s *dev);
+static void adc_rxint(FAR struct adc_dev_s *dev, bool enable);
+static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg);
+static int adc_interrupt(int irq, void *context, FAR void *arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct adc_ops_s g_adcops =
+{
+ .ao_bind = adc_bind,
+ .ao_reset = adc_reset,
+ .ao_setup = adc_setup,
+ .ao_shutdown = adc_shutdown,
+ .ao_rxint = adc_rxint,
+ .ao_ioctl = adc_ioctl,
+};
+
+#ifdef CONFIG_IMXRT_ADC1
+static struct imxrt_dev_s g_adcpriv1 =
+{
+ .irq = IMXRT_IRQ_ADC1,
+ .intf = 1,
+ .initialized = 0,
+ .base = IMXRT_ADC1_BASE,
+};
+
+static struct adc_dev_s g_adcdev1 =
+{
+ .ad_ops = &g_adcops,
+ .ad_priv = &g_adcpriv1,
+};
+
+gpio_pinset_t g_adcpinlist1[ADC_MAX_CHANNELS] =
+{
+ GPIO_ADC1_CH0,
+ GPIO_ADC1_CH1,
+ GPIO_ADC1_CH2,
+ GPIO_ADC1_CH3,
+ GPIO_ADC1_CH4,
+ GPIO_ADC1_CH5,
+ GPIO_ADC1_CH6,
+ GPIO_ADC1_CH7,
+ GPIO_ADC1_CH8,
+ GPIO_ADC1_CH9,
+ GPIO_ADC1_CH10,
+ GPIO_ADC1_CH11,
+ GPIO_ADC1_CH12,
+ GPIO_ADC1_CH13,
+ GPIO_ADC1_CH14,
+ GPIO_ADC1_CH15,
+};
+#endif
+
+#ifdef CONFIG_IMXRT_ADC2
+static struct imxrt_dev_s g_adcpriv2 =
+{
+ .irq = IMXRT_IRQ_ADC2,
+ .intf = 2,
+ .initialized = 0,
+ .base = IMXRT_ADC2_BASE,
+};
+
+static struct adc_dev_s g_adcdev2 =
+{
+ .ad_ops = &g_adcops,
+ .ad_priv = &g_adcpriv2,
+};
+
+gpio_pinset_t g_adcpinlist2[ADC_MAX_CHANNELS] =
+{
+ GPIO_ADC2_CH0,
+ GPIO_ADC2_CH1,
+ GPIO_ADC2_CH2,
+ GPIO_ADC2_CH3,
+ GPIO_ADC2_CH4,
+ GPIO_ADC2_CH5,
+ GPIO_ADC2_CH6,
+ GPIO_ADC2_CH7,
+ GPIO_ADC2_CH8,
+ GPIO_ADC2_CH9,
+ GPIO_ADC2_CH10,
+ GPIO_ADC2_CH11,
+ GPIO_ADC2_CH12,
+ GPIO_ADC2_CH13,
+ GPIO_ADC2_CH14,
+ GPIO_ADC2_CH15,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void adc_putreg(FAR struct imxrt_dev_s *priv, uint32_t offset,
+ uint32_t value)
+{
+ putreg32(value, priv->base + offset);
+}
+
+static uint32_t adc_getreg(FAR struct imxrt_dev_s *priv, uint32_t offset)
+{
+ return getreg32(priv->base + offset);
+}
+
+static void adc_modifyreg(FAR struct imxrt_dev_s *priv, uint32_t offset,
+ uint32_t clearbits, uint32_t setbits)
+{
+ modifyreg32(priv->base + offset, clearbits, setbits);
+}
+
+/****************************************************************************
+ * Name: adc_bind
+ *
+ * Description:
+ * Bind the upper-half driver callbacks to the lower-half implementation.
+ * This must be called early in order to receive ADC event notifications.
+ *
+ ****************************************************************************/
+
+static int adc_bind(FAR struct adc_dev_s *dev,
+ FAR const struct adc_callback_s *callback)
+{
+ FAR struct imxrt_dev_s *priv = (FAR struct imxrt_dev_s *)dev->ad_priv;
+
+ DEBUGASSERT(priv != NULL);
+ priv->cb = callback;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: adc_reset
+ *
+ * Description:
+ * Reset the ADC device. Called early to initialize the hardware. This
+ * is called, before adc_setup() and on error conditions.
+ *
+ ****************************************************************************/
+
+static void adc_reset(FAR struct adc_dev_s *dev)
+{
+ FAR struct imxrt_dev_s *priv = (FAR struct imxrt_dev_s *)dev->ad_priv;
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ /* Do nothing if ADC instance is currently in use */
+
+ if (priv->initialized > 0)
+ {
+ goto exit_leave_critical;
+ }
+
+ /* Configure clock gating */
+
+ switch (priv->intf)
+ {
+#ifdef CONFIG_IMXRT_ADC1
+ case 1:
+ imxrt_clockall_adc1();
+ break;
+#endif
+#ifdef CONFIG_IMXRT_ADC2
+ case 2:
+ imxrt_clockall_adc2();
+ break;
+#endif
+ default:
+ aerr("ERROR: Tried to reset non-existing ADC: %d\n", priv->intf);
+ goto exit_leave_critical;
+ }
+
+ leave_critical_section(flags);
+
+ /* Configure ADC */
+
+ uint32_t adc_cfg = ADC_CFG_AVGS_4SMPL | ADC_CFG_ADTRG_SW |
+ ADC_CFG_REFSEL_VREF | ADC_CFG_ADSTS_7_21 | ADC_CFG_ADIV_DIV8 | \
+ ADC_CFG_ADLSMP | ADC_CFG_MODE_10BIT | ADC_CFG_ADICLK_IPGDIV2;
+ adc_putreg(priv, IMXRT_ADC_CFG_OFFSET, adc_cfg);
+
+ uint32_t adc_gc = 0;
+ adc_putreg(priv, IMXRT_ADC_GC_OFFSET, adc_gc);
+
+ /* Calibration - After ADC has been configured as desired.
+ * ADTRG in ADC_CFG must be SW (0) during calibration
+ */
+
+ /* Clear calibration error */
+
+ adc_modifyreg(priv, IMXRT_ADC_GS_OFFSET, 0, ADC_GS_CALF);
+
+ /* Start calibration */
+
+ adc_modifyreg(priv, IMXRT_ADC_GC_OFFSET, 0, ADC_GC_CAL);
+
+ while ((adc_getreg(priv, IMXRT_ADC_GC_OFFSET) & ADC_GC_CAL) != 0 &&
+ (adc_getreg(priv, IMXRT_ADC_GS_OFFSET) & ADC_GS_CALF) == 0);
+
+ if ((adc_getreg(priv, IMXRT_ADC_GS_OFFSET) & ADC_GS_CALF) != 0 ||
+ (adc_getreg(priv, IMXRT_ADC_HS_OFFSET) & ADC_HS_COCO0) == 0)
+ {
+ aerr("ERROR: ADC%d calibration failed\n", priv->intf);
+ return;
+ }
+
+ /* Clear "conversion complete" */
+
+ uint32_t adc_r0 = adc_getreg(priv, IMXRT_ADC_R0_OFFSET);
+ UNUSED(adc_r0);
+
+ /* Pad configuration */
+
+ gpio_pinset_t *pinlist = NULL;
+ switch (priv->intf)
+ {
+#ifdef CONFIG_IMXRT_ADC1
+ case 1:
+ pinlist = g_adcpinlist1;
+ break;
+#endif
+#ifdef CONFIG_IMXRT_ADC2
+ case 2:
+ pinlist = g_adcpinlist2;
+ break;
+#endif
+ default:
+ /* We have already checked the intf number earlier in this function,
+ * so we should never get here.
+ */
+
+ return;
+ }
+
+ gpio_pinset_t pinset = 0;
+ for (int i = 0; i < priv->nchannels; i++)
+ {
+ DEBUGASSERT(priv->chanlist[i] < ADC_MAX_CHANNELS);
+ pinset = pinlist[priv->chanlist[i]] | IOMUX_ADC_DEFAULT;
+ imxrt_config_gpio(pinset);
+ }
+
+ return;
+
+exit_leave_critical:
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: adc_setup
+ *
+ * Description:
+ * Configure the ADC. This method is called the first time that the ADC
+ * device is opened. This will occur when the port is first opened.
+ * This setup includes configuring and attaching ADC interrupts.
+ * Interrupts are all disabled upon return.
+ *
+ ****************************************************************************/
+
+static int adc_setup(FAR struct adc_dev_s *dev)
+{
+ FAR struct imxrt_dev_s *priv = (FAR struct imxrt_dev_s *)dev->ad_priv;
+
+ /* Do nothing when the ADC device is already set up */
+
+ if (priv->initialized > 0)
+ {
+ return OK;
+ }
+
+ priv->initialized++;
+
+ int ret = irq_attach(priv->irq, adc_interrupt, dev);
+ if (ret < 0)
+ {
+ ainfo("irq_attach failed: %d\n", ret);
+ return ret;
+ }
+
+ up_enable_irq(priv->irq);
+
+ /* Start the first conversion */
+
+ priv->current = 0;
+ adc_putreg(priv, IMXRT_ADC_HC0_OFFSET,
+ ADC_HC_ADCH(priv->chanlist[priv->current]));
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: adc_shutdown
+ *
+ * Description:
+ * Disable the ADC. This method is called when the ADC device is closed.
+ * This method reverses the operation the setup method.
+ *
+ ****************************************************************************/
+
+static void adc_shutdown(FAR struct adc_dev_s *dev)
+{
+ FAR struct imxrt_dev_s *priv = (FAR struct imxrt_dev_s *)dev->ad_priv;
+
+ /* Shutdown the ADC device only when not in use */
+
+ priv->initialized--;
+
+ if (priv->initialized > 0)
+ {
+ return;
+ }
+
+ /* Disable ADC interrupts, both at the level of the ADC device and at the
+ * level of the NVIC.
+ */
+
+ /* Disable interrupt and stop any on-going conversion */
+
+ adc_putreg(priv, IMXRT_ADC_HC0_OFFSET, ~ADC_HC_AIEN | ADC_HC_ADCH_DIS);
+
+ up_disable_irq(priv->irq);
+
+ /* Then detach the ADC interrupt handler. */
+
+ irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: adc_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
+{
+ FAR struct imxrt_dev_s *priv = (FAR struct imxrt_dev_s *)dev->ad_priv;
+
+ if (enable)
+ {
+ adc_modifyreg(priv, IMXRT_ADC_HC0_OFFSET, 0, ADC_HC_AIEN);
+ }
+ else
+ {
+ adc_modifyreg(priv, IMXRT_ADC_HC0_OFFSET, ADC_HC_AIEN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: adc_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ *
+ * Input Parameters:
+ * dev - pointer to device structure used by the driver
+ * cmd - command
+ * arg - arguments passed with command
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
+{
+ /* No ioctl commands supported */
+
+ /* TODO: ANIOC_TRIGGER, for SW triggered conversion */
+
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: adc_interrupt
+ *
+ * Description:
+ * ADC interrupt handler
+ *
+ ****************************************************************************/
+
+static int adc_interrupt(int irq, void *context, FAR void *arg)
+{
+ FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg;
+ FAR struct imxrt_dev_s *priv = (FAR struct imxrt_dev_s *)dev->ad_priv;
+ int32_t data;
+
+ if ((adc_getreg(priv, IMXRT_ADC_HS_OFFSET) & ADC_HS_COCO0) != 0)
+ {
+ /* Read data. This also clears the COCO bit. */
+
+ data = (int32_t)adc_getreg(priv, IMXRT_ADC_R0_OFFSET);
+
+ if (priv->cb != NULL)
+ {
+ DEBUGASSERT(priv->cb->au_receive != NULL);
+ priv->cb->au_receive(dev, priv->chanlist[priv->current], data);
+ }
+
+ /* Set the channel number of the next channel that will complete
+ * conversion.
+ */
+
+ priv->current++;
+
+ if (priv->current >= priv->nchannels)
+ {
+ /* Restart the conversion sequence from the beginning */
+
+ priv->current = 0;
+ }
+
+ /* Start the next conversion */
+
+ adc_modifyreg(priv, IMXRT_ADC_HC0_OFFSET, ADC_HC_ADCH_MASK,
+ ADC_HC_ADCH(priv->chanlist[priv->current]));
+ }
+
+ /* There are no interrupt flags left to clear */
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_adcinitialize
+ *
+ * Description:
+ * Initialize the adc
+ *
+ * Input Parameters:
+ * intf - ADC number (1 or 2)
+ * chanlist - The list of channels
+ * nchannels - Number of channels
+ *
+ * Returned Value:
+ * Valid can device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+FAR struct adc_dev_s *imxrt_adcinitialize(int intf,
+ FAR const uint8_t *chanlist,
+ int nchannels)
+{
+ FAR struct adc_dev_s *dev;
+ FAR struct imxrt_dev_s *priv;
+
+ DEBUGASSERT(nchannels > 0);
+
+ switch (intf)
+ {
+#ifdef CONFIG_IMXRT_ADC1
+ case 1:
+ {
+ dev = &g_adcdev1;
+ break;
+ }
+#endif /* CONFIG_IMXRT_ADC1 */
+
+#ifdef CONFIG_IMXRT_ADC2
+ case 2:
+ {
+ dev = &g_adcdev2;
+ break;
+ }
+#endif /* CONFIG_IMXRT_ADC2 */
+
+ default:
+ {
+ aerr("ERROR: Tried to initialize invalid ADC: %d\n", intf);
+ return NULL;
+ }
+ }
+
+ priv = (FAR struct imxrt_dev_s *)dev->ad_priv;
+
+ priv->nchannels = nchannels;
+ memcpy(priv->chanlist, chanlist, nchannels);
+
+ ainfo("intf: %d nchannels: %d\n", priv->intf, priv->nchannels);
+
+ return dev;
+}
+
+#endif /* CONFIG_IMXRT_ADC1 || CONFIG_IMXRT_ADC2 */
+
+#endif /* CONFIG_IMXRT_ADC */
diff --git a/arch/arm/src/imxrt/imxrt_adc.h b/arch/arm/src/imxrt/imxrt_adc.h
new file mode 100644
index 0000000..1525f51
--- /dev/null
+++ b/arch/arm/src/imxrt/imxrt_adc.h
@@ -0,0 +1,100 @@
+/****************************************************************************
+ * arch/arm/src/lpc17xx_40xx/lpc17_40_adc.h
+ *
+ * Copyright (C) 2020 Actia Nordic AB. All rights reserved.
+ * Author: Thomas Axelsson <th...@actia.se>
+ *
+ * Based on arch/arm/src/lpc_17xx_40xx/imxrt_adc.h
+ *
+ * Copyright (C) 2010, 2012, 2013 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_ADC_H
+#define __ARCH_ARM_SRC_IMXRT_ADC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: imxrt_adcinitialize
+ *
+ * Description:
+ * Initialize the adc
+ *
+ * Input Parameters:
+ * intf - ADC number (1 or 2)
+ * chanlist - The list of channels
+ * nchannels - Number of channels
+ *
+ * Returned Value:
+ * Valid can device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_IMXRT_ADC
+FAR struct adc_dev_s *imxrt_adcinitialize(int intf,
+ FAR const uint8_t *chanlist,
+ int nchannels);
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARCH_ARM_SRC_IMXRT_ADC_H */
diff --git a/boards/arm/imxrt/imxrt1060-evk/src/Makefile b/boards/arm/imxrt/imxrt1060-evk/src/Makefile
index 7a073dc..9efc123 100644
--- a/boards/arm/imxrt/imxrt1060-evk/src/Makefile
+++ b/boards/arm/imxrt/imxrt1060-evk/src/Makefile
@@ -73,6 +73,10 @@ ifeq ($(CONFIG_DEV_GPIO),y)
CSRCS += imxrt_gpio.c
endif
+ifeq ($(CONFIG_IMXRT_ADC),y)
+CSRCS += imxrt_adc.c
+endif
+
ifeq ($(CONFIG_INPUT_FT5X06),y)
CSRCS += imxrt_ft5x06.c
endif
diff --git a/boards/arm/imxrt/imxrt1060-evk/src/imxrt1060-evk.h b/boards/arm/imxrt/imxrt1060-evk/src/imxrt1060-evk.h
index eb6e011..216b916 100644
--- a/boards/arm/imxrt/imxrt1060-evk/src/imxrt1060-evk.h
+++ b/boards/arm/imxrt/imxrt1060-evk/src/imxrt1060-evk.h
@@ -276,6 +276,18 @@ int imxrt_gpio_initialize(void);
#endif
/****************************************************************************
+ * Name: imxrt_adc_initialize
+ *
+ * Description:
+ * Initialize ADC drivers
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_IMXRT_ADC
+int imxrt_adc_initialize(void);
+#endif
+
+/****************************************************************************
* Name: imxrt_ft5x06_register
*
* Description:
diff --git a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_adc.c b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_adc.c
new file mode 100644
index 0000000..119535f
--- /dev/null
+++ b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_adc.c
@@ -0,0 +1,167 @@
+/****************************************************************************
+ * boards/arm/imxrt/imxrt1060-evk/src/imxrt_adc.c
+ *
+ * Copyright (C) 2020 Actia Nordic AB. All rights reserved.
+ * Author: Thomas Axelsson <th...@actia.se>
+ *
+ * Based on boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_adc.c
+ *
+ * Based on boards/zkit-arm-176/src/up-adc
+ *
+ * Copyright (C) 2013 Zilogic Systems. All rights reserved.
+ * Author: Kannan <co...@nuttx.org>
+ *
+ * Based on boards/lpc1720g-eval/src/lpc17_40_adc.c
+ *
+ * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/analog/adc.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "arm_arch.h"
+
+#include "imxrt_adc.h"
+
+#ifdef CONFIG_IMXRT_ADC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#define ADC1_NCHANNELS 3
+#define ADC2_NCHANNELS 3
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const uint8_t g_chanlist1[ADC1_NCHANNELS] =
+ {
+ /* Arduino Interface pins A0 to A2 */
+
+ 15,
+ 0,
+ 9,
+ };
+
+static const uint8_t g_chanlist2[ADC2_NCHANNELS] =
+ {
+ /* Arduino Interface pins A3 to A5 */
+
+ 10,
+ 6,
+ 5
+ };
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: imxrt_adc_setup
+ *
+ * Description:
+ * Initialize ADC and register the ADC driver.
+ *
+ ****************************************************************************/
+
+int imxrt_adc_initialize(void)
+{
+ static bool initialized = false;
+ struct adc_dev_s *adc;
+ int ret;
+
+ /* Check if we have already initialized */
+
+ if (!initialized)
+ {
+ /* Call imxrt_adcinitialize() to get an instance of the ADC interface */
+
+#ifdef CONFIG_IMXRT_ADC1
+ adc = imxrt_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS);
+ if (adc == NULL)
+ {
+ aerr("ERROR: Failed to get ADC interface for ADC1\n");
+ return -ENODEV;
+ }
+
+ /* Register the ADC driver at "/dev/adc1" */
+
+ ret = adc_register("/dev/adc1", adc);
+ if (ret < 0)
+ {
+ aerr("ERROR: adc_register adc1 failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+#ifdef CONFIG_IMXRT_ADC2
+ adc = imxrt_adcinitialize(2, g_chanlist2, ADC2_NCHANNELS);
+ if (adc == NULL)
+ {
+ aerr("ERROR: Failed to get ADC interface for ADC2\n");
+ return -ENODEV;
+ }
+
+ /* Register the ADC driver at "/dev/adc2" */
+
+ ret = adc_register("/dev/adc2", adc);
+ if (ret < 0)
+ {
+ aerr("ERROR: adc_register adc2 failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+ /* Now we are initialized */
+
+ initialized = true;
+ }
+
+ return OK;
+}
+
+#endif /* CONFIG_ADC */
diff --git a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_bringup.c b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_bringup.c
index 8584f9e..c0e07ba 100644
--- a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_bringup.c
+++ b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_bringup.c
@@ -223,6 +223,16 @@ int imxrt_bringup(void)
}
#endif
+#ifdef CONFIG_IMXRT_ADC
+ /* Initialize ADC and register the ADC driver. */
+
+ ret = imxrt_adc_initialize();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: imxrt_adc_initialize() failed: %d\n", ret);
+ }
+#endif
+
#ifdef CONFIG_INPUT_FT5X06
/* Initialize the FT5X06 touchscreen driver */
[incubator-nuttx] 02/02: imxrt: Style fixes in mux and ADC hardware
headers
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit f193f0f70278ac1e1c7ccd87d488e460d93f2bd6
Author: Thomas Axelsson <th...@actia.se>
AuthorDate: Wed Sep 23 16:13:02 2020 +0200
imxrt: Style fixes in mux and ADC hardware headers
---
arch/arm/src/imxrt/hardware/imxrt_adc.h | 87 +++++++++++++++---------------
arch/arm/src/imxrt/hardware/imxrt_iomuxc.h | 35 ++++++------
2 files changed, 64 insertions(+), 58 deletions(-)
diff --git a/arch/arm/src/imxrt/hardware/imxrt_adc.h b/arch/arm/src/imxrt/hardware/imxrt_adc.h
index 78f04ae..486c03c 100644
--- a/arch/arm/src/imxrt/hardware/imxrt_adc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_adc.h
@@ -74,11 +74,11 @@
#define IMXRT_ADC_OFS_OFFSET 0x0054 /* Offset correction value register */
#define IMXRT_ADC_CAL_OFFSET 0x0058 /* Calibration value register */
-/* Register addresses ***********************************************************************/
+/* Register addresses ***************************************************************/
/* ADC1 Register Addresses */
-#define IMXRT_ADC1_HC0 (IMXRT_ADC1_BASE + IMXRT_ADC_HC_OFFSET) /* ADC1 Control register for hardware triggers */
+#define IMXRT_ADC1_HC0 (IMXRT_ADC1_BASE + IMXRT_ADC_HC_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC1 (IMXRT_ADC1_BASE + IMXRT_ADC_HC1_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC2 (IMXRT_ADC1_BASE + IMXRT_ADC_HC2_OFFSET) /* ADC1 Control register for hardware triggers */
#define IMXRT_ADC1_HC3 (IMXRT_ADC1_BASE + IMXRT_ADC_HC3_OFFSET) /* ADC1 Control register for hardware triggers */
@@ -104,7 +104,7 @@
/* ADC2 Register Addresses */
-#define IMXRT_ADC2_HC0 (IMXRT_ADC2_BASE + IMXRT_ADC_HC_OFFSET) /* ADC2 Control register for hardware triggers */
+#define IMXRT_ADC2_HC0 (IMXRT_ADC2_BASE + IMXRT_ADC_HC_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC1 (IMXRT_ADC2_BASE + IMXRT_ADC_HC1_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC2 (IMXRT_ADC2_BASE + IMXRT_ADC_HC2_OFFSET) /* ADC2 Control register for hardware triggers */
#define IMXRT_ADC2_HC3 (IMXRT_ADC2_BASE + IMXRT_ADC_HC3_OFFSET) /* ADC2 Control register for hardware triggers */
@@ -135,16 +135,16 @@
#define ADC_HC_ADCH_SHIFT (0) /* Bits: 0-4 Input Channel Select */
#define ADC_HC_ADCH_MASK (31 << ADC_HC_ADCH_SHIFT)
# define ADC_HC_ADCH(n) ((uint32_t)(n) << ADC_HC_ADCH_SHIFT)
-# define ADC_HC_ADCH_EXT_0 (0 << ADC_HC_ADCH_SHIFT) /* External channels 0 */
-# define ADC_HC_ADCH_EXT_1 (1 << ADC_HC_ADCH_SHIFT) /* External channels 1 */
-# define ADC_HC_ADCH_EXT_2 (2 << ADC_HC_ADCH_SHIFT) /* External channels 2 */
-# define ADC_HC_ADCH_EXT_3 (3 << ADC_HC_ADCH_SHIFT) /* External channels 3 */
-# define ADC_HC_ADCH_EXT_4 (4 << ADC_HC_ADCH_SHIFT) /* External channels 4 */
-# define ADC_HC_ADCH_EXT_5 (5 << ADC_HC_ADCH_SHIFT) /* External channels 5 */
-# define ADC_HC_ADCH_EXT_6 (6 << ADC_HC_ADCH_SHIFT) /* External channels 6 */
-# define ADC_HC_ADCH_EXT_7 (7 << ADC_HC_ADCH_SHIFT) /* External channels 7 */
-# define ADC_HC_ADCH_EXT_8 (8 << ADC_HC_ADCH_SHIFT) /* External channels 8 */
-# define ADC_HC_ADCH_EXT_9 (9 << ADC_HC_ADCH_SHIFT) /* External channels 9 */
+# define ADC_HC_ADCH_EXT_0 (0 << ADC_HC_ADCH_SHIFT) /* External channels 0 */
+# define ADC_HC_ADCH_EXT_1 (1 << ADC_HC_ADCH_SHIFT) /* External channels 1 */
+# define ADC_HC_ADCH_EXT_2 (2 << ADC_HC_ADCH_SHIFT) /* External channels 2 */
+# define ADC_HC_ADCH_EXT_3 (3 << ADC_HC_ADCH_SHIFT) /* External channels 3 */
+# define ADC_HC_ADCH_EXT_4 (4 << ADC_HC_ADCH_SHIFT) /* External channels 4 */
+# define ADC_HC_ADCH_EXT_5 (5 << ADC_HC_ADCH_SHIFT) /* External channels 5 */
+# define ADC_HC_ADCH_EXT_6 (6 << ADC_HC_ADCH_SHIFT) /* External channels 6 */
+# define ADC_HC_ADCH_EXT_7 (7 << ADC_HC_ADCH_SHIFT) /* External channels 7 */
+# define ADC_HC_ADCH_EXT_8 (8 << ADC_HC_ADCH_SHIFT) /* External channels 8 */
+# define ADC_HC_ADCH_EXT_9 (9 << ADC_HC_ADCH_SHIFT) /* External channels 9 */
# define ADC_HC_ADCH_EXT_10 (10 << ADC_HC_ADCH_SHIFT) /* External channels 10 */
# define ADC_HC_ADCH_EXT_11 (11 << ADC_HC_ADCH_SHIFT) /* External channels 11 */
# define ADC_HC_ADCH_EXT_12 (12 << ADC_HC_ADCH_SHIFT) /* External channels 12 */
@@ -154,7 +154,8 @@
# define ADC_HC_ADCH_EXT_ADC_ETC (16 << ADC_HC_ADCH_SHIFT) /* External channel selection from ADC_ETC */
# define ADC_HC_ADCH_VREFSH (25 << ADC_HC_ADCH_SHIFT) /* internal channel, for ADC self-test, hard connected to VRH internally */
# define ADC_HC_ADCH_DIS (31 << ADC_HC_ADCH_SHIFT) /* */
- /* Bits: 5-6 Reserved */
+
+ /* Bits: 5-6 Reserved */
#define ADC_HC_AIEN (1 << 7) /* Bit: 7 Conversion Complete Interrupt Enable/Disable Control */
/* Bits: 8-31 Reserved */
@@ -170,51 +171,51 @@
/* Configuration register */
-#define ADC_CFG_ADICLK_SHIFT (0) /* Bits: 0-1 Input Clock Select */
+#define ADC_CFG_ADICLK_SHIFT (0) /* Bits: 0-1 Input Clock Select */
#define ADC_CFG_ADICLK_MASK (3 << ADC_CFG_ADICLK_SHIFT)
# define ADC_CFG_ADICLK(n) ((uint32_t)(n) << ADC_CFG_ADICLK_SHIFT)
# define ADC_CFG_ADICLK_IPG (0 << ADC_CFG_ADICLK_SHIFT) /* IPG clock */
# define ADC_CFG_ADICLK_IPGDIV2 (1 << ADC_CFG_ADICLK_SHIFT) /* IPG clock divided by 2 */
# define ADC_CFG_ADICLK_ADACK (3 << ADC_CFG_ADICLK_SHIFT) /* Asynchronous clock (ADACK) */
-#define ADC_CFG_MODE_SHIFT (2) /* Bits: 2-3 Conversion Mode Selection */
+#define ADC_CFG_MODE_SHIFT (2) /* Bits: 2-3 Conversion Mode Selection */
#define ADC_CFG_MODE_MASK (3 << ADC_CFG_MODE_SHIFT)
# define ADC_CFG_MODE(n) ((uint32_t)(n) << ADC_CFG_MODE_SHIFT)
-# define ADC_CFG_MODE_8BIT (0 << ADC_CFG_MODE_SHIFT) /* 8-bit conversion */
-# define ADC_CFG_MODE_10BIT (1 << ADC_CFG_MODE_SHIFT) /* 10-bit conversion */
-# define ADC_CFG_MODE_12BIT (2 << ADC_CFG_MODE_SHIFT) /* 12-bit conversion */
-#define ADC_CFG_ADLSMP (1 << 4) /* Bit: 4 Long Sample Time Configuration */
-#define ADC_CFG_ADIV_SHIFT (5) /* Bits: 5-6 Clock Divide Select */
+# define ADC_CFG_MODE_8BIT (0 << ADC_CFG_MODE_SHIFT) /* 8-bit conversion */
+# define ADC_CFG_MODE_10BIT (1 << ADC_CFG_MODE_SHIFT) /* 10-bit conversion */
+# define ADC_CFG_MODE_12BIT (2 << ADC_CFG_MODE_SHIFT) /* 12-bit conversion */
+#define ADC_CFG_ADLSMP (1 << 4) /* Bit: 4 Long Sample Time Configuration */
+#define ADC_CFG_ADIV_SHIFT (5) /* Bits: 5-6 Clock Divide Select */
#define ADC_CFG_ADIV_MASK (3 << ADC_CFG_ADIV_SHIFT)
# define ADC_CFG_ADIV(n) ((uint32_t)(n) << ADC_CFG_ADIV_SHIFT)
-# define ADC_CFG_ADIV_DIV1 (0 << ADC_CFG_ADIV_SHIFT) /* Input clock */
-# define ADC_CFG_ADIV_DIV2 (1 << ADC_CFG_ADIV_SHIFT) /* Input clock / 2 */
-# define ADC_CFG_ADIV_DIV4 (2 << ADC_CFG_ADIV_SHIFT) /* Input clock / 4 */
-# define ADC_CFG_ADIV_DIV8 (3 << ADC_CFG_ADIV_SHIFT) /* Input clock / 8 */
-#define ADC_CFG_ADLPC (1 << 7) /* Bit: 7 Low-Power Configuration */
-#define ADC_CFG_ADSTS_SHIFT (8) /* Bits: 8-9 Defines the sample time duration. */
+# define ADC_CFG_ADIV_DIV1 (0 << ADC_CFG_ADIV_SHIFT) /* Input clock */
+# define ADC_CFG_ADIV_DIV2 (1 << ADC_CFG_ADIV_SHIFT) /* Input clock / 2 */
+# define ADC_CFG_ADIV_DIV4 (2 << ADC_CFG_ADIV_SHIFT) /* Input clock / 4 */
+# define ADC_CFG_ADIV_DIV8 (3 << ADC_CFG_ADIV_SHIFT) /* Input clock / 8 */
+#define ADC_CFG_ADLPC (1 << 7) /* Bit: 7 Low-Power Configuration */
+#define ADC_CFG_ADSTS_SHIFT (8) /* Bits: 8-9 Defines the sample time duration. */
#define ADC_CFG_ADSTS_MASK (3 << ADC_CFG_ADSTS_SHIFT)
# define ADC_CFG_ADSTS(n) ((uint32_t)(n) << ADC_CFG_ADSTS_SHIFT)
-# define ADC_CFG_ADSTS_3_13 (0 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 3 if ADLSMP=0b, 13 if ADLSMP=1b */
-# define ADC_CFG_ADSTS_5_17 (1 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 5 if ADLSMP=0b, 17 if ADLSMP=1b */
-# define ADC_CFG_ADSTS_7_21 (2 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 7 if ADLSMP=0b, 21 if ADLSMP=1b */
-# define ADC_CFG_ADSTS_9_25 (3 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 9 if ADLSMP=0b, 25 if ADLSMP=1b */
-#define ADC_CFG_ADHSC (1 << 10) /* Bit: 10 High Speed Configuration*/
-#define ADC_CFG_REFSEL_SHIFT (11) /* Bits: 11-12 Voltage Reference Selection */
+# define ADC_CFG_ADSTS_3_13 (0 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 3 if ADLSMP=0b, 13 if ADLSMP=1b */
+# define ADC_CFG_ADSTS_5_17 (1 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 5 if ADLSMP=0b, 17 if ADLSMP=1b */
+# define ADC_CFG_ADSTS_7_21 (2 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 7 if ADLSMP=0b, 21 if ADLSMP=1b */
+# define ADC_CFG_ADSTS_9_25 (3 << ADC_CFG_ADSTS_SHIFT) /* Sample period (ADC clocks) = 9 if ADLSMP=0b, 25 if ADLSMP=1b */
+#define ADC_CFG_ADHSC (1 << 10) /* Bit: 10 High Speed Configuration*/
+#define ADC_CFG_REFSEL_SHIFT (11) /* Bits: 11-12 Voltage Reference Selection */
#define ADC_CFG_REFSEL_MASK (3 << ADC_CFG_REFSEL_SHIFT)
# define ADC_CFG_REFSEL(n) ((uint32_t)(n) << ADC_CFG_REFSEL_SHIFT)
# define ADC_CFG_REFSEL_VREF (0 << ADC_CFG_REFSEL_SHIFT) /* Selects VREFH/VREFL as reference voltage. */
-#define ADC_CFG_ADTRG (1 << 13) /* Bit: 13 Conversion Trigger Select */
-# define ADC_CFG_ADTRG_SW (0 << 13) /* SW trigger selected */
-# define ADC_CFG_ADTRG_HW (1 << 13) /* HW trigger selected */
-#define ADC_CFG_AVGS_SHIFT (14) /* Bits: 14-15 Hardware Average select */
+#define ADC_CFG_ADTRG (1 << 13) /* Bit: 13 Conversion Trigger Select */
+# define ADC_CFG_ADTRG_SW (0 << 13) /* SW trigger selected */
+# define ADC_CFG_ADTRG_HW (1 << 13) /* HW trigger selected */
+#define ADC_CFG_AVGS_SHIFT (14) /* Bits: 14-15 Hardware Average select */
#define ADC_CFG_AVGS_MASK (3 << ADC_CFG_AVGS_SHIFT)
# define ADC_CFG_AVGS(n) ((uint32_t)(n) << ADC_CFG_AVGS_SHIFT)
-# define ADC_CFG_AVGS_4SMPL (0 << ADC_CFG_AVGS_SHIFT) /* 4 samples averaged */
-# define ADC_CFG_AVGS_8SMPL (1 << ADC_CFG_AVGS_SHIFT) /* 8 samples averaged */
-# define ADC_CFG_AVGS_16SMPL (2 << ADC_CFG_AVGS_SHIFT) /* 16 samples averaged */
-# define ADC_CFG_AVGS_32SMPL (3 << ADC_CFG_AVGS_SHIFT) /* 32 samples averaged */
-#define ADC_CFG_OVWREN (1 << 16) /* Bit: 16 Data Overwrite Enable */
- /* Bits: 17-31 Reserved */
+# define ADC_CFG_AVGS_4SMPL (0 << ADC_CFG_AVGS_SHIFT) /* 4 samples averaged */
+# define ADC_CFG_AVGS_8SMPL (1 << ADC_CFG_AVGS_SHIFT) /* 8 samples averaged */
+# define ADC_CFG_AVGS_16SMPL (2 << ADC_CFG_AVGS_SHIFT) /* 16 samples averaged */
+# define ADC_CFG_AVGS_32SMPL (3 << ADC_CFG_AVGS_SHIFT) /* 32 samples averaged */
+#define ADC_CFG_OVWREN (1 << 16) /* Bit: 16 Data Overwrite Enable */
+ /* Bits: 17-31 Reserved */
/* General control register */
diff --git a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
index 493bf3b..42a9303 100644
--- a/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
@@ -93,32 +93,37 @@
#define PADCTL_SRE (1 << 0) /* Bit 0: Slew Rate Field */
#define PADCTL_DSE_SHIFT (3) /* Bits 3-5: Drive Strength Field */
+
#define PADCTL_DSE_MASK (7 << PADCTL_DSE_SHIFT)
# define PADCTL_DSE(n) ((uint32_t)(n) << PADCTL_DSE_SHIFT) /* n=DRIVE_* */
-# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */
-# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
-# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
-# define PADCTL_DSE_90OHM (3 << PADCTL_DSE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */
-# define PADCTL_DSE_60OHM (4 << PADCTL_DSE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */
-# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
-# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
-# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
+# define PADCTL_DSE_HIZ (0 << PADCTL_DSE_SHIFT) /* HI-Z */
+# define PADCTL_DSE_260OHM (1 << PADCTL_DSE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */
+# define PADCTL_DSE_130OHM (2 << PADCTL_DSE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */
+# define PADCTL_DSE_90OHM (3 << PADCTL_DSE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */
+# define PADCTL_DSE_60OHM (4 << PADCTL_DSE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */
+# define PADCTL_DSE_50OHM (5 << PADCTL_DSE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */
+# define PADCTL_DSE_40OHM (6 << PADCTL_DSE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */
+# define PADCTL_DSE_33OHM (7 << PADCTL_DSE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */
+
#define PADCTL_SPEED_SHIFT (6) /* Bits 6-7: Speed Field */
#define PADCTL_SPEED_MASK (3 << PADCTL_SPEED_SHIFT)
# define PADCTL_SPEED(n) ((uint32_t)(n) << PADCTL_SPEED_SHIFT) /* n=SPEED_* */
-# define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */
-# define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */
-# define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */
+# define PADCTL_SPEED_LOW (0 << PADCTL_SPEED_SHIFT) /* Low frequency (50 MHz) */
+# define PADCTL_SPEED_MEDIUM (1 << PADCTL_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */
+# define PADCTL_SPEED_MAX (3 << PADCTL_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */
+
#define PADCTL_ODE (1 << 11) /* Bit 11: Open Drain Enable Field */
#define PADCTL_PKE (1 << 12) /* Bit 12: Pull / Keep Enable Field */
#define PADCTL_PUE (1 << 13) /* Bit 13: Pull / Keep Select Field */
+
#define PADCTL_PUS_SHIFT (14) /* Bits 14-15: Pull Up / Down Config. Field */
#define PADCTL_PUS_MASK (3 << PADCTL_PUS_SHIFT)
# define PADCTL_PUS(n) ((uint32_t)(n) << PADCTL_PUS_SHIFT) /* n=PULL_* */
-# define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */
-# define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */
-# define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */
-# define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */
+# define PADCTL_PUS_DOWN_100K (0 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Down */
+# define PADCTL_PUS_UP_47K (1 << PADCTL_PUS_SHIFT) /* 47K Ohm Pull Up */
+# define PADCTL_PUS_UP_100K (2 << PADCTL_PUS_SHIFT) /* 100K Ohm Pull Up */
+# define PADCTL_PUS_UP_22K (3 << PADCTL_PUS_SHIFT) /* 22K Ohm Pull Up */
+
#define PADCTL_HYS (1 << 16) /* Bit 16: Hysteresis Enable Field */
/* Defaults for drive conditions for each set of pins. These are a good