You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2020/08/21 13:52:59 UTC
[GitHub] [incubator-nuttx] RB-tel opened a new pull request #1622: I2C(RIIC) support for RX65N
RB-tel opened a new pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622
## Summary
RIIC suport for RX65N
## Impact
## Testing
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] acassis commented on a change in pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
acassis commented on a change in pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#discussion_r478383977
##########
File path: arch/renesas/src/rx65n/rx65n_vector.S
##########
@@ -564,6 +548,21 @@ _uprx65_groupbl1_handler:
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 27, RX65N_ERI9_IRQ
#endif /* CONFIG_RX65N_SCI9 */
+#ifdef CONFIG_RX65N_RIIC0
+ multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 13, RX65N_RIIC0_TEI0_IRQ
Review comment:
> Renesas RX65N supports Group Interrupts. Each Group Interrupt groups “unrelated” events from multiple peripherals. So segregating these events into respective peripheral drivers at the do_irq level complicates the implementation. And also in order to maintain trampoline style of implementation, ‘multi_switching’ assembly macro was implemented. With this implementation, single interrupt is expanded into multiple vector numbers and rest of the interrupt handling mechanism are maintained as is. Please let us know your comments.
Ok, thank you for this explanation.
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] acassis commented on pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
acassis commented on pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#issuecomment-681922794
Ok, let's merge it!
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] acassis commented on a change in pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
acassis commented on a change in pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#discussion_r478386331
##########
File path: arch/renesas/src/rx65n/rx65n_irq.c
##########
@@ -426,6 +426,77 @@ void up_disable_irq(int irq)
#endif
#endif
+#ifdef CONFIG_RX65N_RIIC0
+ if (irq == RX65N_RIIC0_RXI0_IRQ)
+ {
+ ICU.IER[6].BIT.IEN4 = 0;
Review comment:
Ok, I recall this discussion.
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] RB-tel commented on a change in pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
RB-tel commented on a change in pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#discussion_r478345364
##########
File path: arch/renesas/src/rx65n/rx65n_irq.c
##########
@@ -426,6 +426,77 @@ void up_disable_irq(int irq)
#endif
#endif
+#ifdef CONFIG_RX65N_RIIC0
+ if (irq == RX65N_RIIC0_RXI0_IRQ)
+ {
+ ICU.IER[6].BIT.IEN4 = 0;
Review comment:
Firstly, it is observed that output binary image size is smaller when bit fields are used in RX65N compilation. Secondly, bit fields are generally used in Renesas drivers as part of their FIT driver package releases. We feel that keeping the same coding style would help users in porting across platforms. Because of these advantages we would like to retain the coding style if it is not violating any NuttX guidelines.
Discussion on the same topic was done on NuttX google group some time back and the discussion link is given below:
https://groups.google.com/forum/#!searchin/nuttx/rx65n%7Csort:date/nuttx/jwV1n6oiDQQ/uMUFtF7OBgAJ
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] RB-tel commented on a change in pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
RB-tel commented on a change in pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#discussion_r478377814
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
Review comment:
corrected the alignment
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC0_ICCR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC0_ICMR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC0_ICMR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC0_ICMR3 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC0_ICFER (RX65N_RIIC0_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC0_ICSER (RX65N_RIIC0_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC0_ICIER (RX65N_RIIC0_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC0_ICSR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC0_ICSR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC0_SARL0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC0_SARU0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC0_SARL1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC0_SARU1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC0_SARL2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC0_SARU2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC0_ICBRL (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC0_ICBRH (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC0_ICDRT (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC0_ICDRR (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC1_ICCR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC1_ICCR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC1_ICMR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC1_ICMR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC1_ICMR3 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC1_ICFER (RX65N_RIIC1_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC1_ICSER (RX65N_RIIC1_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC1_ICIER (RX65N_RIIC1_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC1_ICSR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC1_ICSR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC1_SARL0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC1_SARU0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC1_SARL1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC1_SARU1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC1_SARL2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC1_SARU2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC1_ICBRL (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC1_ICBRH (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC1_ICDRT (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC1_ICDRR (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC2_ICCR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC2_ICCR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC2_ICMR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC2_ICMR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC2_ICMR3 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC2_ICFER (RX65N_RIIC2_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC2_ICSER (RX65N_RIIC2_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC2_ICIER (RX65N_RIIC2_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC2_ICSR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC2_ICSR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC2_SARL0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC2_SARU0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC2_SARL1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC2_SARU1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC2_SARL2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC2_SARU2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC2_ICBRL (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC2_ICBRH (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC2_ICDRT (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC2_ICDRR (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC_ICCR1_ICE_RST (0x7f)
+#define RX65N_RIIC_ICCR1_IICRST_SET (0x40)
+
+#define RX65N_RIIC_ICCR2_ST_SET (0x02)
+#define RX65N_RIIC_ICCR2_SP_SET (0x08)
Review comment:
corrected the alignment
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC0_ICCR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC0_ICMR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC0_ICMR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC0_ICMR3 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC0_ICFER (RX65N_RIIC0_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC0_ICSER (RX65N_RIIC0_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC0_ICIER (RX65N_RIIC0_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC0_ICSR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC0_ICSR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC0_SARL0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC0_SARU0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC0_SARL1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC0_SARU1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC0_SARL2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC0_SARU2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC0_ICBRL (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC0_ICBRH (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC0_ICDRT (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC0_ICDRR (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC1_ICCR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC1_ICCR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC1_ICMR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC1_ICMR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC1_ICMR3 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC1_ICFER (RX65N_RIIC1_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC1_ICSER (RX65N_RIIC1_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC1_ICIER (RX65N_RIIC1_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC1_ICSR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC1_ICSR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC1_SARL0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC1_SARU0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC1_SARL1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC1_SARU1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC1_SARL2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC1_SARU2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC1_ICBRL (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC1_ICBRH (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC1_ICDRT (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC1_ICDRR (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC2_ICCR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC2_ICCR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC2_ICMR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC2_ICMR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC2_ICMR3 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC2_ICFER (RX65N_RIIC2_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC2_ICSER (RX65N_RIIC2_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC2_ICIER (RX65N_RIIC2_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC2_ICSR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC2_ICSR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC2_SARL0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC2_SARU0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC2_SARL1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC2_SARU1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC2_SARL2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC2_SARU2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC2_ICBRL (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC2_ICBRH (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC2_ICDRT (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC2_ICDRR (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC_ICCR1_ICE_RST (0x7f)
+#define RX65N_RIIC_ICCR1_IICRST_SET (0x40)
+
+#define RX65N_RIIC_ICCR2_ST_SET (0x02)
+#define RX65N_RIIC_ICCR2_SP_SET (0x08)
+#define RX65N_RIIC_ICCR2_RS_SET (0x04)
+
+#define RX65N_RIIC_ICSR2_STOP_SET (0x08)
Review comment:
corrected the alignment
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] RB-tel commented on a change in pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
RB-tel commented on a change in pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#discussion_r478378104
##########
File path: boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c
##########
@@ -129,6 +133,41 @@ int rx65n_bringup(void)
/* Initialize battery-backed RAM */
(void)rx65n_sbram_int();
+#endif
+#ifdef HAVE_RIIC_DRIVER
+ FAR struct i2c_master_s *i2c;
+
+ /* Get the I2C lower half instance */
+#ifdef CONFIG_RX65N_RIIC0
+ #ifdef CONFIG_RX65N_SCI2
+ i2cerr("Port is initialized for RIIC0. SCI2 cannot be used\n");
+ #endif
+ riic0_init_port();
+ i2c = rx65n_i2cbus_initialize(0);
+ if (i2c == NULL)
+ {
+ i2cerr("ERROR: Initialization of RIIC Channel 0 failed: %d\n", ret);
+ }
+
Review comment:
corrected
##########
File path: boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c
##########
@@ -129,6 +133,51 @@ int rx65n_bringup(void)
/* Initialize standby RAM */
(void)rx65n_sbram_int();
+#endif
+#ifdef HAVE_RIIC_DRIVER
+ FAR struct i2c_master_s *i2c;
+
+ /* Get the I2C lower half instance */
Review comment:
corrected
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] acassis merged pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
acassis merged pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] acassis commented on a change in pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
acassis commented on a change in pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#discussion_r474720538
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC0_ICCR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC0_ICMR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC0_ICMR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC0_ICMR3 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC0_ICFER (RX65N_RIIC0_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC0_ICSER (RX65N_RIIC0_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC0_ICIER (RX65N_RIIC0_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC0_ICSR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC0_ICSR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC0_SARL0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC0_SARU0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC0_SARL1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC0_SARU1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC0_SARL2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC0_SARU2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC0_ICBRL (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC0_ICBRH (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC0_ICDRT (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC0_ICDRR (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC1_ICCR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC1_ICCR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC1_ICMR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC1_ICMR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC1_ICMR3 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC1_ICFER (RX65N_RIIC1_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC1_ICSER (RX65N_RIIC1_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC1_ICIER (RX65N_RIIC1_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC1_ICSR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC1_ICSR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC1_SARL0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC1_SARU0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC1_SARL1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC1_SARU1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC1_SARL2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC1_SARU2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC1_ICBRL (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC1_ICBRH (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC1_ICDRT (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC1_ICDRR (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC2_ICCR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC2_ICCR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC2_ICMR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC2_ICMR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC2_ICMR3 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC2_ICFER (RX65N_RIIC2_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC2_ICSER (RX65N_RIIC2_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC2_ICIER (RX65N_RIIC2_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC2_ICSR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC2_ICSR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC2_SARL0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC2_SARU0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC2_SARL1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC2_SARU1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC2_SARL2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC2_SARU2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC2_ICBRL (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC2_ICBRH (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC2_ICDRT (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC2_ICDRR (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC_ICCR1_ICE_RST (0x7f)
+#define RX65N_RIIC_ICCR1_IICRST_SET (0x40)
+
+#define RX65N_RIIC_ICCR2_ST_SET (0x02)
+#define RX65N_RIIC_ICCR2_SP_SET (0x08)
Review comment:
not aligned
##########
File path: arch/renesas/src/rx65n/rx65n_irq.c
##########
@@ -426,6 +426,77 @@ void up_disable_irq(int irq)
#endif
#endif
+#ifdef CONFIG_RX65N_RIIC0
+ if (irq == RX65N_RIIC0_RXI0_IRQ)
+ {
+ ICU.IER[6].BIT.IEN4 = 0;
Review comment:
It should be nice if RX64 could follow the other NuttX ports and void accessing registers this way. It could keep all codes on NuttX more consistent. I mean: use putreg() and getreg() macros to access the registers.
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
Review comment:
Please try to keep the alignment of these values at same position as the previous block
##########
File path: arch/renesas/src/rx65n/rx65n_definitions.h
##########
@@ -585,6 +592,162 @@
#define RX65N_SBRAM_BASE 0x000a4000
+/* RIIC related definitions */
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_DRIVER)
+ #define HAVE_RIIC_DRIVER 1
+#endif
+
+#define RX65N_RIIC0_BASE (uint32_t)&RIIC0
+#define RX65N_RIIC1_BASE (uint32_t)&RIIC1
+#define RX65N_RIIC2_BASE (uint32_t)&RIIC2
+
+#define RX65N_RIIC_ICCR1_OFFSET (0x0000)
+#define RX65N_RIIC_ICCR2_OFFSET (0x0001)
+#define RX65N_RIIC_ICMR1_OFFSET (0x0002)
+#define RX65N_RIIC_ICMR2_OFFSET (0x0003)
+#define RX65N_RIIC_ICMR3_OFFSET (0x0004)
+#define RX65N_RIIC_ICFER_OFFSET (0x0005)
+#define RX65N_RIIC_ICSER_OFFSET (0x0006)
+#define RX65N_RIIC_ICIER_OFFSET (0x0007)
+#define RX65N_RIIC_ICSR1_OFFSET (0x0008)
+#define RX65N_RIIC_ICSR2_OFFSET (0x0009)
+#define RX65N_RIIC_SARL0_OFFSET (0x000a)
+#define RX65N_RIIC_SARU0_OFFSET (0x000b)
+#define RX65N_RIIC_SARL1_OFFSET (0x000c)
+#define RX65N_RIIC_SARU1_OFFSET (0x000d)
+#define RX65N_RIIC_SARL2_OFFSET (0x000e)
+#define RX65N_RIIC_SARU2_OFFSET (0x000f)
+#define RX65N_RIIC_ICBRL_OFFSET (0x0010)
+#define RX65N_RIIC_ICBRH_OFFSET (0x0011)
+#define RX65N_RIIC_ICDRT_OFFSET (0x0012)
+#define RX65N_RIIC_ICDRR_OFFSET (0x0013)
+
+#define RX65N_RIIC0_ICCR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC0_ICCR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC0_ICMR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC0_ICMR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC0_ICMR3 (RX65N_RIIC0_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC0_ICFER (RX65N_RIIC0_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC0_ICSER (RX65N_RIIC0_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC0_ICIER (RX65N_RIIC0_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC0_ICSR1 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC0_ICSR2 (RX65N_RIIC0_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC0_SARL0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC0_SARU0 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC0_SARL1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC0_SARU1 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC0_SARL2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC0_SARU2 (RX65N_RIIC0_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC0_ICBRL (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC0_ICBRH (RX65N_RIIC0_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC0_ICDRT (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC0_ICDRR (RX65N_RIIC0_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC1_ICCR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC1_ICCR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC1_ICMR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC1_ICMR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC1_ICMR3 (RX65N_RIIC1_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC1_ICFER (RX65N_RIIC1_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC1_ICSER (RX65N_RIIC1_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC1_ICIER (RX65N_RIIC1_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC1_ICSR1 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC1_ICSR2 (RX65N_RIIC1_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC1_SARL0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC1_SARU0 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC1_SARL1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC1_SARU1 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC1_SARL2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC1_SARU2 (RX65N_RIIC1_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC1_ICBRL (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC1_ICBRH (RX65N_RIIC1_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC1_ICDRT (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC1_ICDRR (RX65N_RIIC1_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC2_ICCR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR1_OFFSET)
+#define RX65N_RIIC2_ICCR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICCR2_OFFSET)
+#define RX65N_RIIC2_ICMR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR1_OFFSET)
+#define RX65N_RIIC2_ICMR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR2_OFFSET)
+#define RX65N_RIIC2_ICMR3 (RX65N_RIIC2_BASE + RX65N_RIIC_ICMR3_OFFSET)
+#define RX65N_RIIC2_ICFER (RX65N_RIIC2_BASE + RX65N_RIIC_ICFER_OFFSET)
+#define RX65N_RIIC2_ICSER (RX65N_RIIC2_BASE + RX65N_RIIC_ICSER_OFFSET)
+#define RX65N_RIIC2_ICIER (RX65N_RIIC2_BASE + RX65N_RIIC_ICIER_OFFSET)
+#define RX65N_RIIC2_ICSR1 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR1_OFFSET)
+#define RX65N_RIIC2_ICSR2 (RX65N_RIIC2_BASE + RX65N_RIIC_ICSR2_OFFSET)
+#define RX65N_RIIC2_SARL0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL0_OFFSET)
+#define RX65N_RIIC2_SARU0 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU0_OFFSET)
+#define RX65N_RIIC2_SARL1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL1_OFFSET)
+#define RX65N_RIIC2_SARU1 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU1_OFFSET)
+#define RX65N_RIIC2_SARL2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARL2_OFFSET)
+#define RX65N_RIIC2_SARU2 (RX65N_RIIC2_BASE + RX65N_RIIC_SARU2_OFFSET)
+#define RX65N_RIIC2_ICBRL (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRL_OFFSET)
+#define RX65N_RIIC2_ICBRH (RX65N_RIIC2_BASE + RX65N_RIIC_ICBRH_OFFSET)
+#define RX65N_RIIC2_ICDRT (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRT_OFFSET)
+#define RX65N_RIIC2_ICDRR (RX65N_RIIC2_BASE + RX65N_RIIC_ICDRR_OFFSET)
+
+#define RX65N_RIIC_ICCR1_ICE_RST (0x7f)
+#define RX65N_RIIC_ICCR1_IICRST_SET (0x40)
+
+#define RX65N_RIIC_ICCR2_ST_SET (0x02)
+#define RX65N_RIIC_ICCR2_SP_SET (0x08)
+#define RX65N_RIIC_ICCR2_RS_SET (0x04)
+
+#define RX65N_RIIC_ICSR2_STOP_SET (0x08)
Review comment:
Please align all these columns
##########
File path: boards/renesas/rx65n/rx65n-grrose/src/rx65n_bringup.c
##########
@@ -129,6 +133,41 @@ int rx65n_bringup(void)
/* Initialize battery-backed RAM */
(void)rx65n_sbram_int();
+#endif
+#ifdef HAVE_RIIC_DRIVER
+ FAR struct i2c_master_s *i2c;
+
+ /* Get the I2C lower half instance */
+#ifdef CONFIG_RX65N_RIIC0
+ #ifdef CONFIG_RX65N_SCI2
+ i2cerr("Port is initialized for RIIC0. SCI2 cannot be used\n");
+ #endif
+ riic0_init_port();
+ i2c = rx65n_i2cbus_initialize(0);
+ if (i2c == NULL)
+ {
+ i2cerr("ERROR: Initialization of RIIC Channel 0 failed: %d\n", ret);
+ }
+
Review comment:
I think this space here is not needed. Does nxstyle require it?
##########
File path: arch/renesas/src/rx65n/rx65n_vector.S
##########
@@ -564,6 +548,21 @@ _uprx65_groupbl1_handler:
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 27, RX65N_ERI9_IRQ
#endif /* CONFIG_RX65N_SCI9 */
+#ifdef CONFIG_RX65N_RIIC0
+ multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 13, RX65N_RIIC0_TEI0_IRQ
Review comment:
I think "multi_switching" is other strange thing that entered on NuttX, should be interesting if it could be called more like a function. Could you please think about it.
##########
File path: boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_bringup.c
##########
@@ -129,6 +133,51 @@ int rx65n_bringup(void)
/* Initialize standby RAM */
(void)rx65n_sbram_int();
+#endif
+#ifdef HAVE_RIIC_DRIVER
+ FAR struct i2c_master_s *i2c;
+
+ /* Get the I2C lower half instance */
Review comment:
You missed an empty line after this comment
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org
[GitHub] [incubator-nuttx] RB-tel commented on a change in pull request #1622: I2C(RIIC) support for RX65N
Posted by GitBox <gi...@apache.org>.
RB-tel commented on a change in pull request #1622:
URL: https://github.com/apache/incubator-nuttx/pull/1622#discussion_r478345636
##########
File path: arch/renesas/src/rx65n/rx65n_vector.S
##########
@@ -564,6 +548,21 @@ _uprx65_groupbl1_handler:
multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 27, RX65N_ERI9_IRQ
#endif /* CONFIG_RX65N_SCI9 */
+#ifdef CONFIG_RX65N_RIIC0
+ multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 13, RX65N_RIIC0_TEI0_IRQ
Review comment:
Renesas RX65N supports Group Interrupts. Each Group Interrupt groups “unrelated” events from multiple peripherals. So segregating these events into respective peripheral drivers at the do_irq level complicates the implementation. And also in order to maintain trampoline style of implementation, ‘multi_switching’ assembly macro was implemented. With this implementation, single interrupt is expanded into multiple vector numbers and rest of the interrupt handling mechanism are maintained as is. Please let us know your comments.
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org