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Posted to commits@datasketches.apache.org by ti...@apache.org on 2026/05/11 10:00:02 UTC
(datasketches-rust) branch main updated: fix: correct assetion logic (#122)
This is an automated email from the ASF dual-hosted git repository.
tisonkun pushed a commit to branch main
in repository https://gitbox.apache.org/repos/asf/datasketches-rust.git
The following commit(s) were added to refs/heads/main by this push:
new 812aa90 fix: correct assetion logic (#122)
812aa90 is described below
commit 812aa90284494140eea68836b21baeb5afd0ff26
Author: Anastasios Bakogiannis <t....@gmail.com>
AuthorDate: Mon May 11 11:59:56 2026 +0200
fix: correct assetion logic (#122)
---
datasketches/src/hll/array4.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/datasketches/src/hll/array4.rs b/datasketches/src/hll/array4.rs
index b8e5b36..f0f6132 100644
--- a/datasketches/src/hll/array4.rs
+++ b/datasketches/src/hll/array4.rs
@@ -230,10 +230,10 @@ impl Array4 {
let mut new_aux = None;
for (slot, old_actual_val) in old_aux.into_iter() {
- debug_assert_ne!(
+ debug_assert_eq!(
self.get_raw(slot),
AUX_TOKEN,
- "AuxMap contains slow without AUX_TOKEN"
+ "AuxMap contains slot != AUX_TOKEN"
);
let new_shifted = old_actual_val - new_cur_min;
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