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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/10/02 14:32:14 UTC

[incubator-nuttx] branch master updated: arch: qemu-rv: Fix qemu_rv_start_s() for S-mode

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new b3e300f8e6 arch: qemu-rv: Fix qemu_rv_start_s() for S-mode
b3e300f8e6 is described below

commit b3e300f8e61b1572349bb253d5c5a55fe0d63570
Author: Masayuki Ishikawa <ma...@gmail.com>
AuthorDate: Sun Oct 2 19:15:00 2022 +0900

    arch: qemu-rv: Fix qemu_rv_start_s() for S-mode
    
    Summary:
    - I found inappropriate SET_CSR() usage in the function.
    - This PR fixes this issue.
    
    Impact:
    - None
    
    Testing:
    - tested with rv-virt:knsh64
    
    Signed-off-by: Masayuki Ishikawa <Ma...@jp.sony.com>
---
 arch/risc-v/src/qemu-rv/qemu_rv_start.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_start.c b/arch/risc-v/src/qemu-rv/qemu_rv_start.c
index be831f6904..d9aacda827 100644
--- a/arch/risc-v/src/qemu-rv/qemu_rv_start.c
+++ b/arch/risc-v/src/qemu-rv/qemu_rv_start.c
@@ -131,14 +131,14 @@ void qemu_rv_start_s(int mhartid)
 {
   /* Disable MMU and enable PMP */
 
-  SET_CSR(satp, 0x0);
-  SET_CSR(pmpaddr0, 0x3fffffffffffffull);
-  SET_CSR(pmpcfg0, 0xf);
+  WRITE_CSR(satp, 0x0);
+  WRITE_CSR(pmpaddr0, 0x3fffffffffffffull);
+  WRITE_CSR(pmpcfg0, 0xf);
 
   /* Set exception and interrupt delegation for S-mode */
 
-  SET_CSR(medeleg, 0xffff);
-  SET_CSR(mideleg, 0xffff);
+  WRITE_CSR(medeleg, 0xffff);
+  WRITE_CSR(mideleg, 0xffff);
 
   /* Allow to write satp from S-mode */
 
@@ -152,11 +152,11 @@ void qemu_rv_start_s(int mhartid)
   /* Set the trap vector for S-mode */
 
   extern void __trap_vec(void);
-  SET_CSR(stvec, (uintptr_t)__trap_vec);
+  WRITE_CSR(stvec, (uintptr_t)__trap_vec);
 
   /* Set mepc to the entry */
 
-  SET_CSR(mepc, (uintptr_t)qemu_rv_start);
+  WRITE_CSR(mepc, (uintptr_t)qemu_rv_start);
   asm volatile("mret");
 }
 #endif