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Posted to commits@mynewt.apache.org by we...@apache.org on 2016/12/28 21:43:07 UTC
[3/5] incubator-mynewt-core git commit: MYNEWT-524 Initial support
for nrf52840pdk
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/afecb4cd/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf52840.h
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diff --git a/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf52840.h b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf52840.h
new file mode 100755
index 0000000..465ade1
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nRF5_SDK_11.0.0_89a8197/components/device/nrf52840.h
@@ -0,0 +1,2417 @@
+
+/****************************************************************************************************//**
+ * @file nrf52840.h
+ *
+ * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
+ * nrf52840 from Nordic Semiconductor.
+ *
+ * @version V1
+ * @date 18. November 2016
+ *
+ * @note Generated with SVDConv V2.81d
+ * from CMSIS SVD File 'nrf52840.svd' Version 1,
+ *
+ * @par Copyright (c) 2016, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+ * @{
+ */
+
+/** @addtogroup nrf52840
+ * @{
+ */
+
+#ifndef NRF52840_H
+#define NRF52840_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* --------------------- nrf52840 Specific Interrupt Numbers -------------------- */
+ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
+ RADIO_IRQn = 1, /*!< 1 RADIO */
+ UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
+ NFCT_IRQn = 5, /*!< 5 NFCT */
+ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
+ SAADC_IRQn = 7, /*!< 7 SAADC */
+ TIMER0_IRQn = 8, /*!< 8 TIMER0 */
+ TIMER1_IRQn = 9, /*!< 9 TIMER1 */
+ TIMER2_IRQn = 10, /*!< 10 TIMER2 */
+ RTC0_IRQn = 11, /*!< 11 RTC0 */
+ TEMP_IRQn = 12, /*!< 12 TEMP */
+ RNG_IRQn = 13, /*!< 13 RNG */
+ ECB_IRQn = 14, /*!< 14 ECB */
+ CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
+ WDT_IRQn = 16, /*!< 16 WDT */
+ RTC1_IRQn = 17, /*!< 17 RTC1 */
+ QDEC_IRQn = 18, /*!< 18 QDEC */
+ COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
+ SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
+ SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
+ SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
+ SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
+ SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
+ SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
+ TIMER3_IRQn = 26, /*!< 26 TIMER3 */
+ TIMER4_IRQn = 27, /*!< 27 TIMER4 */
+ PWM0_IRQn = 28, /*!< 28 PWM0 */
+ PDM_IRQn = 29, /*!< 29 PDM */
+ MWU_IRQn = 32, /*!< 32 MWU */
+ PWM1_IRQn = 33, /*!< 33 PWM1 */
+ PWM2_IRQn = 34, /*!< 34 PWM2 */
+ SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
+ RTC2_IRQn = 36, /*!< 36 RTC2 */
+ I2S_IRQn = 37, /*!< 37 I2S */
+ FPU_IRQn = 38, /*!< 38 FPU */
+ USBD_IRQn = 39, /*!< 39 USBD */
+ UARTE1_IRQn = 40, /*!< 40 UARTE1 */
+ QSPI_IRQn = 41, /*!< 41 QSPI */
+ CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */
+ SPIM3_IRQn = 43, /*!< 43 SPIM3 */
+ PWM3_IRQn = 45 /*!< 45 PWM3 */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
+#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
+#include "system_nrf52840.h" /*!< nrf52840 System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+ __I uint32_t PART; /*!< Part code */
+ __I uint32_t VARIANT; /*!< Part variant (hardware version and production configuration). */
+ __I uint32_t PACKAGE; /*!< Package option */
+ __I uint32_t RAM; /*!< RAM variant */
+ __I uint32_t FLASH; /*!< Flash variant */
+ __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */
+} FICR_INFO_Type;
+
+typedef struct {
+ __I uint32_t A0; /*!< Slope definition A0. */
+ __I uint32_t A1; /*!< Slope definition A1. */
+ __I uint32_t A2; /*!< Slope definition A2. */
+ __I uint32_t A3; /*!< Slope definition A3. */
+ __I uint32_t A4; /*!< Slope definition A4. */
+ __I uint32_t A5; /*!< Slope definition A5. */
+ __I uint32_t B0; /*!< y-intercept B0. */
+ __I uint32_t B1; /*!< y-intercept B1. */
+ __I uint32_t B2; /*!< y-intercept B2. */
+ __I uint32_t B3; /*!< y-intercept B3. */
+ __I uint32_t B4; /*!< y-intercept B4. */
+ __I uint32_t B5; /*!< y-intercept B5. */
+ __I uint32_t T0; /*!< Segment end T0. */
+ __I uint32_t T1; /*!< Segment end T1. */
+ __I uint32_t T2; /*!< Segment end T2. */
+ __I uint32_t T3; /*!< Segment end T3. */
+ __I uint32_t T4; /*!< Segment end T4. */
+} FICR_TEMP_Type;
+
+typedef struct {
+ __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to
+ populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+ __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to
+ populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+ __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to
+ populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+ __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to
+ populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+} FICR_NFC_Type;
+
+typedef struct {
+ __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */
+ __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */
+ __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */
+ __I uint32_t RESERVED0;
+} POWER_RAM_Type;
+
+typedef struct {
+ __IO uint32_t RTS; /*!< Pin select for RTS signal */
+ __IO uint32_t TXD; /*!< Pin select for TXD signal */
+ __IO uint32_t CTS; /*!< Pin select for CTS signal */
+ __IO uint32_t RXD; /*!< Pin select for RXD signal */
+} UARTE_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
+} UARTE_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
+} UARTE_TXD_Type;
+
+typedef struct {
+ __IO uint32_t RTS; /*!< Pin select for RTS */
+ __IO uint32_t TXD; /*!< Pin select for TXD */
+ __IO uint32_t CTS; /*!< Pin select for CTS */
+ __IO uint32_t RXD; /*!< Pin select for RXD */
+} UART_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t SCK; /*!< Pin select for SCK */
+ __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
+ __IO uint32_t MISO; /*!< Pin select for MISO signal */
+ __IO uint32_t CSN; /*!< Pin select for CSN */
+} SPIM_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
+ __IO uint32_t LIST; /*!< EasyDMA list type */
+} SPIM_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Number of bytes in transmit buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
+ __IO uint32_t LIST; /*!< EasyDMA list type */
+} SPIM_TXD_Type;
+
+typedef struct {
+ __IO uint32_t RXDELAY; /*!< Sample delay for input serial data on MISO */
+ __IO uint32_t CSNDUR; /*!< Minimum duration between edge of CSN and edge of SCK and minimum
+ duration CSN must stay high between transactions */
+} SPIM_IFTIMING_Type;
+
+typedef struct {
+ __IO uint32_t SCK; /*!< Pin select for SCK */
+ __IO uint32_t MISO; /*!< Pin select for MISO signal */
+ __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
+ __IO uint32_t CSN; /*!< Pin select for CSN signal */
+} SPIS_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< RXD data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */
+} SPIS_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< TXD data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */
+} SPIS_TXD_Type;
+
+typedef struct {
+ __IO uint32_t SCL; /*!< Pin select for SCL signal */
+ __IO uint32_t SDA; /*!< Pin select for SDA signal */
+} TWIM_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
+ __IO uint32_t LIST; /*!< EasyDMA list type */
+} TWIM_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
+ __IO uint32_t LIST; /*!< EasyDMA list type */
+} TWIM_TXD_Type;
+
+typedef struct {
+ __IO uint32_t SCL; /*!< Pin select for SCL signal */
+ __IO uint32_t SDA; /*!< Pin select for SDA signal */
+} TWIS_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< RXD Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */
+} TWIS_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< TXD Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */
+} TWIS_TXD_Type;
+
+typedef struct {
+ __IO uint32_t SCK; /*!< Pin select for SCK */
+ __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
+ __IO uint32_t MISO; /*!< Pin select for MISO signal */
+} SPI_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t SCL; /*!< Pin select for SCL */
+ __IO uint32_t SDA; /*!< Pin select for SDA */
+} TWI_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t RX; /*!< Result of last incoming frame */
+} NFCT_FRAMESTATUS_Type;
+
+typedef struct {
+ __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */
+ __IO uint32_t AMOUNT; /*!< Size of outgoing frame */
+} NFCT_TXD_Type;
+
+typedef struct {
+ __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */
+ __I uint32_t AMOUNT; /*!< Size of last incoming frame */
+} NFCT_RXD_Type;
+
+typedef struct {
+ __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
+ __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type;
+
+typedef struct {
+ __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */
+ __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */
+ __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */
+ __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring
+ a channel */
+} SAADC_CH_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */
+ __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */
+} SAADC_RESULT_Type;
+
+typedef struct {
+ __IO uint32_t LED; /*!< Pin select for LED signal */
+ __IO uint32_t A; /*!< Pin select for A signal */
+ __IO uint32_t B; /*!< Pin select for B signal */
+} QDEC_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence
+ A */
+ __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence
+ A */
+ __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between
+ samples loaded to compare register (load every CNT+1 PWM periods) */
+ __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */
+ __I uint32_t RESERVED1[4];
+} PWM_SEQ_Type;
+
+typedef struct {
+ __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel
+ 0 */
+} PWM_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */
+ __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */
+} PDM_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */
+ __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */
+} PDM_SAMPLE_Type;
+
+typedef struct {
+ __IO uint32_t ADDR; /*!< Description cluster[0]: Configure the word-aligned start address
+ of region 0 to protect */
+ __IO uint32_t SIZE; /*!< Description cluster[0]: Size of region to protect counting from
+ address ACL[0].ADDR. Write '0' as no effect. */
+ __IO uint32_t PERM; /*!< Description cluster[0]: Access permissions for region 0 as defined
+ by start address ACL[0].ADDR and size ACL[0].SIZE */
+ __IO uint32_t UNUSED0; /*!< Unspecified */
+} ACL_ACL_Type;
+
+typedef struct {
+ __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */
+ __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+ __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */
+ __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
+} PPI_CH_Type;
+
+typedef struct {
+ __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
+} PPI_FORK_Type;
+
+typedef struct {
+ __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */
+ __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */
+} MWU_EVENTS_REGION_Type;
+
+typedef struct {
+ __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0
+ detected */
+ __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */
+} MWU_EVENTS_PREGION_Type;
+
+typedef struct {
+ __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region
+ 0, write access detected while corresponding subregion was enabled
+ for watching */
+ __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region
+ 0, read access detected while corresponding subregion was enabled
+ for watching */
+} MWU_PERREGION_Type;
+
+typedef struct {
+ __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */
+ __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */
+ __I uint32_t RESERVED2[2];
+} MWU_REGION_Type;
+
+typedef struct {
+ __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */
+ __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */
+ __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */
+ __I uint32_t RESERVED3;
+} MWU_PREGION_Type;
+
+typedef struct {
+ __IO uint32_t MODE; /*!< I2S mode. */
+ __IO uint32_t RXEN; /*!< Reception (RX) enable. */
+ __IO uint32_t TXEN; /*!< Transmission (TX) enable. */
+ __IO uint32_t MCKEN; /*!< Master clock generator enable. */
+ __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */
+ __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */
+ __IO uint32_t SWIDTH; /*!< Sample width. */
+ __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */
+ __IO uint32_t FORMAT; /*!< Frame format. */
+ __IO uint32_t CHANNELS; /*!< Enable channels. */
+} I2S_CONFIG_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Receive buffer RAM start address. */
+} I2S_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */
+} I2S_TXD_Type;
+
+typedef struct {
+ __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */
+} I2S_RXTXD_Type;
+
+typedef struct {
+ __IO uint32_t MCK; /*!< Pin select for MCK signal. */
+ __IO uint32_t SCK; /*!< Pin select for SCK signal. */
+ __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */
+ __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */
+ __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */
+} I2S_PSEL_Type;
+
+typedef struct {
+ __I uint32_t EPIN[8]; /*!< Description collection[0]: IN endpoint halted status. Can be
+ used as is as response to a GetStatus() request to endpoint. */
+ __I uint32_t RESERVED4;
+ __I uint32_t EPOUT[8]; /*!< Description collection[0]: OUT endpoint halted status. Can be
+ used as is as response to a GetStatus() request to endpoint. */
+} USBD_HALTED_Type;
+
+typedef struct {
+ __IO uint32_t EPOUT[8]; /*!< Description collection[0]: Amount of bytes received last in
+ the data stage of this OUT endpoint */
+ __IO uint32_t ISOOUT; /*!< Amount of bytes received last on this iso OUT data endpoint */
+} USBD_SIZE_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Description cluster[0]: Data pointer */
+ __IO uint32_t MAXCNT; /*!< Description cluster[0]: Maximum number of bytes to transfer */
+ __I uint32_t AMOUNT; /*!< Description cluster[0]: Number of bytes transferred in the last
+ transaction */
+ __I uint32_t RESERVED5[2];
+} USBD_EPIN_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes to transfer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
+} USBD_ISOIN_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Description cluster[0]: Data pointer */
+ __IO uint32_t MAXCNT; /*!< Description cluster[0]: Maximum number of bytes to transfer */
+ __I uint32_t AMOUNT; /*!< Description cluster[0]: Number of bytes transferred in the last
+ transaction */
+ __I uint32_t RESERVED6[2];
+} USBD_EPOUT_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer */
+ __IO uint32_t MAXCNT; /*!< Maximum number of bytes to transfer */
+ __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
+} USBD_ISOOUT_Type;
+
+typedef struct {
+ __IO uint32_t SRC; /*!< Flash memory source address */
+ __IO uint32_t DST; /*!< RAM destination address */
+ __IO uint32_t CNT; /*!< Read transfer length */
+} QSPI_READ_Type;
+
+typedef struct {
+ __IO uint32_t DST; /*!< Flash destination address */
+ __IO uint32_t SRC; /*!< RAM source address */
+ __IO uint32_t CNT; /*!< Write transfer length */
+} QSPI_WRITE_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Start address of flash block to be erased */
+ __IO uint32_t LEN; /*!< Size of block to be erased. */
+} QSPI_ERASE_Type;
+
+typedef struct {
+ __IO uint32_t SCK; /*!< Pin select for serial clock SCK */
+ __IO uint32_t CSN; /*!< Pin select for chip select signal CSN. */
+ __I uint32_t RESERVED7;
+ __IO uint32_t IO0; /*!< Pin select for serial data MOSI/IO0. */
+ __IO uint32_t IO1; /*!< Pin select for serial data MISO/IO1. */
+ __IO uint32_t IO2; /*!< Pin select for serial data IO2. */
+ __IO uint32_t IO3; /*!< Pin select for serial data IO3. */
+} QSPI_PSEL_Type;
+
+
+/* ================================================================================ */
+/* ================ FICR ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Factory Information Configuration Registers (FICR)
+ */
+
+typedef struct { /*!< FICR Structure */
+ __I uint32_t RESERVED0[4];
+ __I uint32_t CODEPAGESIZE; /*!< Code memory page size */
+ __I uint32_t CODESIZE; /*!< Code memory size */
+ __I uint32_t RESERVED1[18];
+ __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */
+ __I uint32_t RESERVED2[6];
+ __I uint32_t ER[4]; /*!< Description collection[0]: Encryption root, word 0 */
+ __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */
+ __I uint32_t DEVICEADDRTYPE; /*!< Device address type */
+ __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */
+ __I uint32_t RESERVED3[21];
+ FICR_INFO_Type INFO; /*!< Device info */
+ __I uint32_t RESERVED4[185];
+ FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */
+ __I uint32_t RESERVED5[2];
+ FICR_NFC_Type NFC; /*!< Unspecified */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================ UICR ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief User Information Configuration Registers (UICR)
+ */
+
+typedef struct { /*!< UICR Structure */
+ __IO uint32_t UNUSED0; /*!< Unspecified */
+ __IO uint32_t UNUSED1; /*!< Unspecified */
+ __IO uint32_t UNUSED2; /*!< Unspecified */
+ __I uint32_t RESERVED0;
+ __IO uint32_t UNUSED3; /*!< Unspecified */
+ __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */
+ __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */
+ __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */
+ __I uint32_t RESERVED1[64];
+ __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function */
+ __IO uint32_t APPROTECT; /*!< Access port protection */
+ __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna
+ or GPIO */
+ __I uint32_t RESERVED2[60];
+ __IO uint32_t EXTSUPPLY; /*!< Enable external circuitry to be supplied from VDD pin. Applicable
+ in 'High voltage mode' only. */
+ __IO uint32_t REGOUT0; /*!< GPIO reference voltage / external output supply voltage in 'High
+ voltage mode'. */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================ POWER ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Power control (POWER)
+ */
+
+typedef struct { /*!< POWER Structure */
+ __I uint32_t RESERVED0[30];
+ __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */
+ __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */
+ __I uint32_t RESERVED1[34];
+ __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */
+ __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */
+ __IO uint32_t EVENTS_USBDETECTED; /*!< Voltage supply detected on VBUS */
+ __IO uint32_t EVENTS_USBREMOVED; /*!< Voltage supply removed from VBUS */
+ __IO uint32_t EVENTS_USBPWRRDY; /*!< USB 3.3 V supply ready */
+ __I uint32_t RESERVED3[119];
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED4[61];
+ __IO uint32_t RESETREAS; /*!< Reset reason */
+ __I uint32_t RESERVED5[9];
+ __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */
+ __I uint32_t RESERVED6[3];
+ __I uint32_t USBREGSTATUS; /*!< USB supply status */
+ __I uint32_t RESERVED7[49];
+ __O uint32_t SYSTEMOFF; /*!< System OFF register */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t POFCON; /*!< Power failure comparator configuration */
+ __I uint32_t RESERVED9[2];
+ __IO uint32_t GPREGRET; /*!< General purpose retention register */
+ __IO uint32_t GPREGRET2; /*!< General purpose retention register */
+ __I uint32_t RESERVED10[21];
+ __IO uint32_t DCDCEN; /*!< Enable DC/DC converter for REG1 stage. */
+ __I uint32_t RESERVED11;
+ __IO uint32_t DCDCEN0; /*!< Enable DC/DC converter for REG0 stage. */
+ __I uint32_t RESERVED12[47];
+ __I uint32_t MAINREGSTATUS; /*!< Main supply status */
+ __I uint32_t RESERVED13[175];
+ POWER_RAM_Type RAM[9]; /*!< Unspecified */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================ CLOCK ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Clock control (CLOCK)
+ */
+
+typedef struct { /*!< CLOCK Structure */
+ __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */
+ __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */
+ __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */
+ __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */
+ __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC or LFULP oscillator */
+ __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */
+ __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */
+ __I uint32_t RESERVED0[57];
+ __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */
+ __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */
+ __I uint32_t RESERVED1;
+ __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */
+ __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */
+ __I uint32_t RESERVED2[124];
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED3[63];
+ __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */
+ __I uint32_t HFCLKSTAT; /*!< HFCLK status */
+ __I uint32_t RESERVED4;
+ __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */
+ __I uint32_t LFCLKSTAT; /*!< LFCLK status */
+ __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+ __I uint32_t RESERVED5[62];
+ __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */
+ __I uint32_t RESERVED6[7];
+ __IO uint32_t CTIV; /*!< Calibration timer interval */
+ __I uint32_t RESERVED7[8];
+ __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================ RADIO ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief 2.4 GHz Radio (RADIO)
+ */
+
+typedef struct { /*!< RADIO Structure */
+ __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */
+ __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */
+ __O uint32_t TASKS_START; /*!< Start RADIO */
+ __O uint32_t TASKS_STOP; /*!< Stop RADIO */
+ __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */
+ __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal
+ strength. */
+ __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */
+ __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */
+ __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */
+ __O uint32_t TASKS_EDSTART; /*!< Start the Energy Detect measurement used in IEEE 802.15.4 mode */
+ __O uint32_t TASKS_EDSTOP; /*!< Stop the Energy Detect measurement */
+ __O uint32_t TASKS_CCASTART; /*!< Start the Clear Channel Assessment used in IEEE 802.15.4 mode */
+ __O uint32_t TASKS_CCASTOP; /*!< Stop the Clear Channel Assessment */
+ __I uint32_t RESERVED0[51];
+ __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */
+ __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */
+ __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */
+ __IO uint32_t EVENTS_END; /*!< Packet sent or received */
+ __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */
+ __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */
+ __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */
+ __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */
+ __I uint32_t RESERVED2;
+ __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */
+ __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */
+ __IO uint32_t EVENTS_FRAMESTART; /*!< IEEE 802.15.4 length field received */
+ __IO uint32_t EVENTS_EDEND; /*!< Sampling of Energy Detection complete. A new ED sample is ready
+ for readout from the RADIO.EDSAMPLE register */
+ __IO uint32_t EVENTS_EDSTOPPED; /*!< The sampling of Energy Detection has stopped */
+ __IO uint32_t EVENTS_CCAIDLE; /*!< Wireless medium in idle - clear to send */
+ __IO uint32_t EVENTS_CCABUSY; /*!< Wireless medium busy - do not send */
+ __IO uint32_t EVENTS_CCASTOPPED; /*!< The CCA has stopped */
+ __IO uint32_t EVENTS_RATEBOOST; /*!< Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit
+ to Ble_LR500Kbit. */
+ __IO uint32_t EVENTS_TXREADY; /*!< RADIO has ramped up and is ready to be started TX path */
+ __IO uint32_t EVENTS_RXREADY; /*!< RADIO has ramped up and is ready to be started RX path */
+ __IO uint32_t EVENTS_MHRMATCH; /*!< MAC Header match found. */
+ __I uint32_t RESERVED3[40];
+ __IO uint32_t SHORTS; /*!< Shortcut register */
+ __I uint32_t RESERVED4[64];
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED5[61];
+ __I uint32_t CRCSTATUS; /*!< CRC status */
+ __I uint32_t RESERVED6;
+ __I uint32_t RXMATCH; /*!< Received address */
+ __I uint32_t RXCRC; /*!< CRC field of previously received packet */
+ __I uint32_t DAI; /*!< Device address match index */
+ __I uint32_t RESERVED7[60];
+ __IO uint32_t PACKETPTR; /*!< Packet pointer */
+ __IO uint32_t FREQUENCY; /*!< Frequency */
+ __IO uint32_t TXPOWER; /*!< Output power */
+ __IO uint32_t MODE; /*!< Data rate and modulation */
+ __IO uint32_t PCNF0; /*!< Packet configuration register 0 */
+ __IO uint32_t PCNF1; /*!< Packet configuration register 1 */
+ __IO uint32_t BASE0; /*!< Base address 0 */
+ __IO uint32_t BASE1; /*!< Base address 1 */
+ __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */
+ __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */
+ __IO uint32_t TXADDRESS; /*!< Transmit address select */
+ __IO uint32_t RXADDRESSES; /*!< Receive address select */
+ __IO uint32_t CRCCNF; /*!< CRC configuration */
+ __IO uint32_t CRCPOLY; /*!< CRC polynomial */
+ __IO uint32_t CRCINIT; /*!< CRC initial value */
+ __I uint32_t RESERVED8;
+ __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */
+ __I uint32_t RSSISAMPLE; /*!< RSSI sample */
+ __I uint32_t RESERVED9;
+ __I uint32_t STATE; /*!< Current radio state */
+ __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */
+ __I uint32_t RESERVED10[2];
+ __IO uint32_t BCC; /*!< Bit counter compare */
+ __I uint32_t RESERVED11[39];
+ __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */
+ __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */
+ __IO uint32_t DACNF; /*!< Device address match configuration */
+ __IO uint32_t MHRMATCHCONF; /*!< Search Pattern Configuration */
+ __IO uint32_t MHRMATCHMAS; /*!< Pattern mask */
+ __I uint32_t RESERVED12;
+ __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */
+ __I uint32_t RESERVED13[3];
+ __IO uint32_t SFD; /*!< IEEE 802.15.4 Start of Frame Delimiter */
+ __IO uint32_t EDCNT; /*!< IEEE 802.15.4 Energy Detect Loop Count */
+ __IO uint32_t EDSAMPLE; /*!< IEEE 802.15.4 Energy Detect Level */
+ __IO uint32_t CCACTRL; /*!< IEEE 802.15.4 Clear Channel Assessment Control */
+ __I uint32_t RESERVED14[611];
+ __IO uint32_t POWER; /*!< Peripheral power control */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================ UARTE ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief UART with EasyDMA 0 (UARTE)
+ */
+
+typedef struct { /*!< UARTE Structure */
+ __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
+ __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
+ __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
+ __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
+ __I uint32_t RESERVED0[7];
+ __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */
+ __I uint32_t RESERVED1[52];
+ __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
+ __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
+ __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to
+ Data RAM) */
+ __I uint32_t RESERVED2;
+ __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */
+ __I uint32_t RESERVED3[2];
+ __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */
+ __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */
+ __IO uint32_t EVENTS_ERROR; /*!< Error detected */
+ __I uint32_t RESERVED4[7];
+ __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
+ __I uint32_t RESERVED5;
+ __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */
+ __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */
+ __I uint32_t RESERVED6;
+ __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */
+ __I uint32_t RESERVED7[41];
+ __IO uint32_t SHORTS; /*!< Shortcut register */
+ __I uint32_t RESERVED8[63];
+ __IO uint32_t INTEN; /*!< Enable or disable interrupt */
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED9[93];
+ __IO uint32_t ERRORSRC; /*!< Error source Note : this register is read / write one to clear. */
+ __I uint32_t RESERVED10[31];
+ __IO uint32_t ENABLE; /*!< Enable UART */
+ __I uint32_t RESERVED11;
+ UARTE_PSEL_Type PSEL; /*!< Unspecified */
+ __I uint32_t RESERVED12[3];
+ __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */
+ __I uint32_t RESERVED13[3];
+ UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */
+ __I uint32_t RESERVED14;
+ UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */
+ __I uint32_t RESERVED15[7];
+ __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
+} NRF_UARTE_Type;
+
+
+/* ================================================================================ */
+/* ================ UART ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter (UART)
+ */
+
+typedef struct { /*!< UART Structure */
+ __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
+ __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
+ __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
+ __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
+ __I uint32_t RESERVED0[3];
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */
+ __I uint32_t RESERVED1[56];
+ __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
+ __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
+ __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */
+ __I uint32_t RESERVED2[4];
+ __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */
+ __I uint32_t RESERVED3;
+ __IO uint32_t EVENTS_ERROR; /*!< Error detected */
+ __I uint32_t RESERVED4[7];
+ __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
+ __I uint32_t RESERVED5[46];
+ __IO uint32_t SHORTS; /*!< Shortcut register */
+ __I uint32_t RESERVED6[64];
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED7[93];
+ __IO uint32_t ERRORSRC; /*!< Error source */
+ __I uint32_t RESERVED8[31];
+ __IO uint32_t ENABLE; /*!< Enable UART */
+ __I uint32_t RESERVED9;
+ UART_PSEL_Type PSEL; /*!< Unspecified */
+ __I uint32_t RXD; /*!< RXD register */
+ __O uint32_t TXD; /*!< TXD register */
+ __I uint32_t RESERVED10;
+ __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */
+ __I uint32_t RESERVED11[17];
+ __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================ SPIM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
+ */
+
+typedef struct { /*!< SPIM Structure */
+ __I uint32_t RESERVED0[4];
+ __O uint32_t TASKS_START; /*!< Start SPI transaction */
+ __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */
+ __I uint32_t RESERVED1;
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */
+ __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */
+ __I uint32_t RESERVED2[56];
+ __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */
+ __I uint32_t RESERVED3[2];
+ __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
+ __I uint32_t RESERVED4;
+ __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */
+ __I uint32_t RESERVED5;
+ __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */
+ __I uint32_t RESERVED6[10];
+ __IO uint32_t EVENTS_STARTED; /*!< Transaction started */
+ __I uint32_t RESERVED7[44];
+ __IO uint32_t SHORTS; /*!< Shortcut register */
+ __I uint32_t RESERVED8[64];
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED9[61];
+ __IO uint32_t STALLSTAT; /*!< Stall status for EasyDMA RAM accesses. The fields in this register
+ is set to STALL by hardware whenever a stall occurres and can
+ be cleared (set to NOSTALL) by the CPU. */
+ __I uint32_t RESERVED10[63];
+ __IO uint32_t ENABLE; /*!< Enable SPIM */
+ __I uint32_t RESERVED11;
+ SPIM_PSEL_Type PSEL; /*!< Unspecified */
+ __I uint32_t RESERVED12[3];
+ __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */
+ __I uint32_t RESERVED13[3];
+ SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */
+ SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */
+ __IO uint32_t CONFIG; /*!< Configuration register */
+ __I uint32_t RESERVED14[2];
+ SPIM_IFTIMING_Type IFTIMING; /*!< Unspecified */
+ __I uint32_t RESERVED15[22];
+ __IO uint32_t ORC; /*!< Byte transmitted after TXD.MAXCNT bytes have been transmitted
+ in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================ SPIS ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI Slave 0 (SPIS)
+ */
+
+typedef struct { /*!< SPIS Structure */
+ __I uint32_t RESERVED0[9];
+ __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */
+ __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */
+ __I uint32_t RESERVED1[54];
+ __IO uint32_t EVENTS_END; /*!< Granted transaction completed */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
+ __I uint32_t RESERVED3[5];
+ __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */
+ __I uint32_t RESERVED4[53];
+ __IO uint32_t SHORTS; /*!< Shortcut register */
+ __I uint32_t RESERVED5[64];
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED6[61];
+ __I uint32_t SEMSTAT; /*!< Semaphore status register */
+ __I uint32_t RESERVED7[15];
+ __IO uint32_t STATUS; /*!< Status from last transaction */
+ __I uint32_t RESERVED8[47];
+ __IO uint32_t ENABLE; /*!< Enable SPI slave */
+ __I uint32_t RESERVED9;
+ SPIS_PSEL_Type PSEL; /*!< Unspecified */
+ __I uint32_t RESERVED10[7];
+ SPIS_RXD_Type RXD; /*!< Unspecified */
+ __I uint32_t RESERVED11;
+ SPIS_TXD_Type TXD; /*!< Unspecified */
+ __I uint32_t RESERVED12;
+ __IO uint32_t CONFIG; /*!< Configuration register */
+ __I uint32_t RESERVED13;
+ __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored
+ transaction. */
+ __I uint32_t RESERVED14[24];
+ __IO uint32_t ORC; /*!< Over-read character */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================ TWIM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
+ */
+
+typedef struct { /*!< TWIM Structure */
+ __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */
+ __I uint32_t RESERVED0;
+ __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */
+ __I uint32_t RESERVED1[2];
+ __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is
+ not suspended. */
+ __I uint32_t RESERVED2;
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
+ __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
+ __I uint32_t RESERVED3[56];
+ __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
+ __I uint32_t RESERVED4[7];
+ __IO uint32_t EVENTS_ERROR; /*!< TWI error */
+ __I uint32_t RESERVED5[8];
+ __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been
+ issued, TWI traffic is now suspended. */
+ __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */
+ __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */
+ __I uint32_t RESERVED6[2];
+ __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */
+ __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */
+ __I uint32_t RESERVED7[39];
+ __IO uint32_t SHORTS; /*!< Shortcut register */
+ __I uint32_t RESERVED8[63];
+ __IO uint32_t INTEN; /*!< Enable or disable interrupt */
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED9[110];
+ __IO uint32_t ERRORSRC; /*!< Error source */
+ __I uint32_t RESERVED10[14];
+ __IO uint32_t ENABLE; /*!< Enable TWIM */
+ __I uint32_t RESERVED11;
+ TWIM_PSEL_Type PSEL; /*!< Unspecified */
+ __I uint32_t RESERVED12[5];
+ __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */
+ __I uint32_t RESERVED13[3];
+ TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */
+ TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */
+ __I uint32_t RESERVED14[13];
+ __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */
+} NRF_TWIM_Type;
+
+
+/* ================================================================================ */
+/* ================ TWIS ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
+ */
+
+typedef struct { /*!< TWIS Structure */
+ __I uint32_t RESERVED0[5];
+ __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */
+ __I uint32_t RESERVED1;
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
+ __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
+ __I uint32_t RESERVED2[3];
+ __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */
+ __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */
+ __I uint32_t RESERVED3[51];
+ __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
+ __I uint32_t RESERVED4[7];
+ __IO uint32_t EVENTS_ERROR; /*!< TWI error */
+ __I uint32_t RESERVED5[9];
+ __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */
+ __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */
+ __I uint32_t RESERVED6[4];
+ __IO uint32_t EVENTS_WRITE; /*!< Write command received */
+ __IO uint32_t EVENTS_READ; /*!< Read command received */
+ __I uint32_t RESERVED7[37];
+ __IO uint32_t SHORTS; /*!< Shortcut register */
+ __I uint32_t RESERVED8[63];
+ __IO uint32_t INTEN; /*!< Enable or disable interrupt */
+ __IO uint32_t INTENSET; /*!< Enable interrupt */
+ __IO uint32_t INTENCLR; /*!< Disable interrupt */
+ __I uint32_t RESERVED9[113];
+ __IO uint32_t ERRORSRC; /*!< Error source */
+ __I uint32_t MATCH; /*!< Status register indicating which address had a match */
+ __I uint32_t RESERVED10[10];
+ __IO uint32_t ENABLE; /*!< Enable TWIS */
+ __I uint32_t RESERVED11;
+ TWIS_PSEL_Type PSEL; /*!< Unspecified */
+ __I uint32_t RESERVED12[9];
+ TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */
+ __I uint32_t RESERVED13;
+ TWIS_TXD_Type TXD;
<TRUNCATED>