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Posted to commits@mynewt.apache.org by je...@apache.org on 2019/05/29 11:50:18 UTC
[mynewt-core] branch master updated (a3b17df -> 1b6fca3)
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git.
from a3b17df sensors: mpu6050 add flexibility
new 2397e0c nucleo-l476: Add second UART
new 1b6fca3 nucleo-l476: Add 2 I2C interfaces
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
hw/bsp/nucleo-l476rg/include/bsp/bsp.h | 2 +-
hw/bsp/nucleo-l476rg/src/hal_bsp.c | 94 ++++++++++++++++++++++++++++------
hw/bsp/nucleo-l476rg/syscfg.yml | 30 ++++++++++-
hw/mcu/stm/stm32l4xx/syscfg.yml | 34 +++++++++++-
4 files changed, 141 insertions(+), 19 deletions(-)
[mynewt-core] 02/02: nucleo-l476: Add 2 I2C interfaces
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 1b6fca335e0da58859bf543132bc6d1b32ac47be
Author: Jerzy Kasenberg <je...@gmail.com>
AuthorDate: Mon May 27 13:25:41 2019 +0200
nucleo-l476: Add 2 I2C interfaces
On ST MCUs pin assignment is no as flexible as on other
manufactures MCUs.
In case I2C_0 available pins are used for some other peripheral
other I2C interfaces can be handy.
---
hw/bsp/nucleo-l476rg/src/hal_bsp.c | 48 +++++++++++++++++++++++++++++++++++---
hw/mcu/stm/stm32l4xx/syscfg.yml | 34 ++++++++++++++++++++++++++-
2 files changed, 78 insertions(+), 4 deletions(-)
diff --git a/hw/bsp/nucleo-l476rg/src/hal_bsp.c b/hw/bsp/nucleo-l476rg/src/hal_bsp.c
index 8e769d0..e25224d 100644
--- a/hw/bsp/nucleo-l476rg/src/hal_bsp.c
+++ b/hw/bsp/nucleo-l476rg/src/hal_bsp.c
@@ -89,11 +89,43 @@ static struct stm32_hal_i2c_cfg i2c_cfg0 = {
.hic_i2c = I2C1,
.hic_rcc_reg = &RCC->APB1ENR1,
.hic_rcc_dev = RCC_APB1ENR1_I2C1EN,
- .hic_pin_sda = MCU_GPIO_PORTB(9), /* PB9 - D14 on CN5 */
- .hic_pin_scl = MCU_GPIO_PORTB(8), /* PB8 - D15 on CN5 */
+ .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL),
.hic_pin_af = GPIO_AF4_I2C1,
.hic_10bit = 0,
- .hic_timingr = 0x10420F13, /* 100KHz at 8MHz of SysCoreClock */
+ .hic_timingr = 0x00000E14, /* 100KHz at 4MHz of SysCoreClock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static struct stm32_hal_i2c_cfg i2c_cfg1 = {
+ .hic_i2c = I2C2,
+ .hic_rcc_reg = &RCC->APB1ENR1,
+ .hic_rcc_dev = RCC_APB1ENR1_I2C2EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C2,
+ .hic_10bit = 0,
+ .hic_timingr = 0x00000E14, /* 100KHz at 4MHz of SysCoreClock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+/*
+ * NOTE: The PC0 and PC1 pins are connected through solder bridges SB51/SB56
+ * in the board to A4 and A5 pins.
+ * If solder brides are removed I2C_2 can't be accessed since only PC0, PC1
+ * are present on Nucleo-64 board for I2C3 to use.
+ */
+static struct stm32_hal_i2c_cfg i2c_cfg2 = {
+ .hic_i2c = I2C3,
+ .hic_rcc_reg = &RCC->APB1ENR1,
+ .hic_rcc_dev = RCC_APB1ENR1_I2C3EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C3,
+ .hic_10bit = 0,
+ .hic_timingr = 0x00000E14, /* 100KHz at 4MHz of SysCoreClock */
};
#endif
@@ -184,6 +216,16 @@ hal_bsp_init(void)
rc = hal_i2c_init(0, &i2c_cfg0);
assert(rc == 0);
#endif
+
+#if MYNEWT_VAL(I2C_1)
+ rc = hal_i2c_init(1, &i2c_cfg1);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+ rc = hal_i2c_init(2, &i2c_cfg2);
+ assert(rc == 0);
+#endif
}
/**
diff --git a/hw/mcu/stm/stm32l4xx/syscfg.yml b/hw/mcu/stm/stm32l4xx/syscfg.yml
index 0d0ba08..5b6d8e8 100644
--- a/hw/mcu/stm/stm32l4xx/syscfg.yml
+++ b/hw/mcu/stm/stm32l4xx/syscfg.yml
@@ -18,9 +18,41 @@
syscfg.defs:
I2C_0:
- description: 'I2C (TWI) interface 0'
+ description: 'I2C (TWI) interface I2C1'
value: 0
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C1, PB6, PB8, PG14'
+ value: MCU_GPIO_PORTB(8)
+
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C1, PB7, PB9, PG13'
+ value: MCU_GPIO_PORTB(9)
+
+ I2C_1:
+ description: 'I2C (TWI) interface I2C2'
+ value: 0
+
+ I2C_1_PIN_SCL:
+ description: 'SCL pin for I2C2, PB10, PB13, PF1'
+ value: MCU_GPIO_PORTB(10)
+
+ I2C_1_PIN_SDA:
+ description: 'SDA pin for I2C2, PB11, PB14, PF0'
+ value: MCU_GPIO_PORTB(11)
+
+ I2C_2:
+ description: 'I2C (TWI) interface I2C3'
+ value: 0
+
+ I2C_2_PIN_SCL:
+ description: 'SCL pin for I2C3, PC0, PF1, PG7'
+ value: MCU_GPIO_PORTC(0)
+
+ I2C_2_PIN_SDA:
+ description: 'SDA pin for I2C3, PC1, PF0, PG8'
+ value: MCU_GPIO_PORTC(1)
+
MCU_FLASH_MIN_WRITE_SIZE:
description: >
Specifies the required alignment for internal flash writes.
[mynewt-core] 01/02: nucleo-l476: Add second UART
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 2397e0ccf9ab2a1265b16c836adcb43a9a93f86b
Author: Jerzy Kasenberg <je...@gmail.com>
AuthorDate: Mon May 27 13:23:00 2019 +0200
nucleo-l476: Add second UART
It just adds second uart that can be used, so one
can be used for console and second for newtmgr.
Pins configuration in syscfg.
---
hw/bsp/nucleo-l476rg/include/bsp/bsp.h | 2 +-
hw/bsp/nucleo-l476rg/src/hal_bsp.c | 46 ++++++++++++++++++++++++----------
hw/bsp/nucleo-l476rg/syscfg.yml | 30 +++++++++++++++++++++-
3 files changed, 63 insertions(+), 15 deletions(-)
diff --git a/hw/bsp/nucleo-l476rg/include/bsp/bsp.h b/hw/bsp/nucleo-l476rg/include/bsp/bsp.h
index f00ccc6..5084118 100644
--- a/hw/bsp/nucleo-l476rg/include/bsp/bsp.h
+++ b/hw/bsp/nucleo-l476rg/include/bsp/bsp.h
@@ -42,7 +42,7 @@ extern uint8_t _ram_start;
#define LED_BLINK_PIN MCU_GPIO_PORTA(5)
/* UART */
-#define UART_CNT 1
+#define UART_CNT 2
/* Arduino pins */
#define ARDUINO_PIN_D0 MCU_GPIO_PORTA(3)
diff --git a/hw/bsp/nucleo-l476rg/src/hal_bsp.c b/hw/bsp/nucleo-l476rg/src/hal_bsp.c
index c167a17..8e769d0 100644
--- a/hw/bsp/nucleo-l476rg/src/hal_bsp.c
+++ b/hw/bsp/nucleo-l476rg/src/hal_bsp.c
@@ -49,18 +49,32 @@
#if MYNEWT_VAL(UART_0)
static struct uart_dev hal_uart0;
-static const struct stm32_uart_cfg uart_cfg[UART_CNT] = {
- [0] = {
- .suc_uart = USART2,
- .suc_rcc_reg = &RCC->APB1ENR1,
- .suc_rcc_dev = RCC_APB1ENR1_USART2EN,
- .suc_pin_tx = MCU_GPIO_PORTA(2),
- .suc_pin_rx = MCU_GPIO_PORTA(3),
- .suc_pin_rts = -1,
- .suc_pin_cts = -1,
- .suc_pin_af = GPIO_AF7_USART2,
- .suc_irqn = USART2_IRQn
- }
+static const struct stm32_uart_cfg uart0_cfg = {
+ .suc_uart = USART2,
+ .suc_rcc_reg = &RCC->APB1ENR1,
+ .suc_rcc_dev = RCC_APB1ENR1_USART2EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART2,
+ .suc_irqn = USART2_IRQn
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev hal_uart1;
+
+static const struct stm32_uart_cfg uart1_cfg = {
+ .suc_uart = USART1,
+ .suc_rcc_reg = &RCC->APB2ENR,
+ .suc_rcc_dev = RCC_APB2ENR_USART1EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART1,
+ .suc_irqn = USART1_IRQn
};
#endif
@@ -129,7 +143,13 @@ hal_bsp_init(void)
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *) &hal_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &hal_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart1_cfg);
assert(rc == 0);
#endif
diff --git a/hw/bsp/nucleo-l476rg/syscfg.yml b/hw/bsp/nucleo-l476rg/syscfg.yml
index 44b67cc..658a453 100644
--- a/hw/bsp/nucleo-l476rg/syscfg.yml
+++ b/hw/bsp/nucleo-l476rg/syscfg.yml
@@ -23,8 +23,36 @@ syscfg.defs:
value: 1024
UART_0:
- description: 'Whether to enable UART0'
+ description: 'Whether to enable USART2'
value: 1
+ UART_0_PIN_TX:
+ description: 'TX pin for USART2, PA2, PD5'
+ value: MCU_GPIO_PORTA(2)
+ UART_0_PIN_RX:
+ description: 'RX pin for USART2, PA3, PD6'
+ value: MCU_GPIO_PORTA(3)
+ UART_0_PIN_CTS:
+ description: 'CTS pin for USART2, PA0, PD3'
+ value: -1
+ UART_0_PIN_RTS:
+ description: 'RTS pin for USART2, PA1, PD4'
+ value: -1
+
+ UART_1:
+ description: 'Whether to enable USART1'
+ value: 0
+ UART_1_PIN_TX:
+ description: 'TX pin for USART1, PA9, PB6'
+ value: MCU_GPIO_PORTA(9)
+ UART_1_PIN_RX:
+ description: 'RX pin for USART1, PA10, PB7'
+ value: MCU_GPIO_PORTA(10)
+ UART_1_PIN_CTS:
+ description: 'CTS pin for USART1, PA11, PB4'
+ value: -1
+ UART_1_PIN_RTS:
+ description: 'RTS pin for USART1, PA12, PB3'
+ value: -1
TIMER_0:
description: 'Whether to enable TIMER_0'