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Posted to commits@nuttx.apache.org by xi...@apache.org on 2020/12/31 05:27:48 UTC
[incubator-nuttx] branch master updated (1473768 -> c8db329)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 1473768 vfs: Fix unsed label warning
new e062bd0 bl602: Update register defines and drivers
new c8db329 BL602: Use sig mask instead of number for AHB swrst
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/risc-v/src/bl602/Kconfig | 40 -
arch/risc-v/src/bl602/bl602_boot2.h | 40 +-
arch/risc-v/src/bl602/bl602_glb.c | 87 +-
.../bl602/{hardware/bl602_clint.h => bl602_glb.h} | 51 +-
arch/risc-v/src/bl602/bl602_gpio.c | 241 +-
arch/risc-v/src/bl602/bl602_gpio.h | 297 ++
arch/risc-v/src/bl602/bl602_hbn.c | 18 +-
.../board.h => arch/risc-v/src/bl602/bl602_hbn.h | 37 +-
arch/risc-v/src/bl602/bl602_irq.c | 10 +-
arch/risc-v/src/bl602/bl602_lowputc.c | 294 +-
arch/risc-v/src/bl602/bl602_lowputc.h | 17 +-
arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c | 42 +-
arch/risc-v/src/bl602/bl602_serial.c | 297 +-
arch/risc-v/src/bl602/bl602_start.c | 19 +-
arch/risc-v/src/bl602/bl602_tim.c | 318 +-
arch/risc-v/src/bl602/bl602_tim.h | 513 ++
arch/risc-v/src/bl602/bl602_tim_lowerhalf.c | 35 +-
arch/risc-v/src/bl602/bl602_tim_lowerhalf.h | 5 +-
arch/risc-v/src/bl602/bl602_timerisr.c | 10 +-
arch/risc-v/src/bl602/hardware/bl602_aon.h | 387 ++
arch/risc-v/src/bl602/hardware/bl602_cci.h | 69 +
.../risc-v/src/bl602/hardware/bl602_cks.h | 50 +-
.../risc-v/src/bl602/hardware/bl602_clic.h | 53 +-
arch/risc-v/src/bl602/hardware/bl602_common.h | 183 -
arch/risc-v/src/bl602/hardware/bl602_dma.h | 254 +
arch/risc-v/src/bl602/hardware/bl602_ef.h | 372 ++
arch/risc-v/src/bl602/hardware/bl602_glb.h | 5056 ++++----------------
arch/risc-v/src/bl602/hardware/bl602_gpio.h | 501 --
arch/risc-v/src/bl602/hardware/bl602_gpip.h | 105 +
arch/risc-v/src/bl602/hardware/bl602_hbn.h | 801 +---
arch/risc-v/src/bl602/hardware/bl602_i2c.h | 154 +
arch/risc-v/src/bl602/hardware/bl602_ir.h | 155 +
arch/risc-v/src/bl602/hardware/bl602_l1c.h | 90 +
arch/risc-v/src/bl602/hardware/bl602_memorymap.h | 60 +
arch/risc-v/src/bl602/hardware/bl602_pds.h | 243 +
arch/risc-v/src/bl602/hardware/bl602_pwm.h | 143 +
arch/risc-v/src/bl602/hardware/bl602_rf.h | 1639 +++++++
arch/risc-v/src/bl602/hardware/bl602_sec.h | 399 ++
arch/risc-v/src/bl602/hardware/bl602_sf.h | 449 ++
arch/risc-v/src/bl602/hardware/bl602_spi.h | 139 +
arch/risc-v/src/bl602/hardware/bl602_timer.h | 756 +--
arch/risc-v/src/bl602/hardware/bl602_tzc.h | 135 +
arch/risc-v/src/bl602/hardware/bl602_uart.h | 858 +---
arch/risc-v/src/bl602/hardware/clic.h | 43 -
boards/risc-v/bl602/bl602evb/include/board.h | 9 +
45 files changed, 7644 insertions(+), 7830 deletions(-)
rename arch/risc-v/src/bl602/{hardware/bl602_clint.h => bl602_glb.h} (57%)
create mode 100644 arch/risc-v/src/bl602/bl602_gpio.h
copy boards/risc-v/bl602/bl602evb/include/board.h => arch/risc-v/src/bl602/bl602_hbn.h (73%)
create mode 100644 arch/risc-v/src/bl602/bl602_tim.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_aon.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_cci.h
copy boards/risc-v/bl602/bl602evb/include/board.h => arch/risc-v/src/bl602/hardware/bl602_cks.h (55%)
copy boards/risc-v/bl602/bl602evb/include/board.h => arch/risc-v/src/bl602/hardware/bl602_clic.h (52%)
delete mode 100644 arch/risc-v/src/bl602/hardware/bl602_common.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_dma.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_ef.h
delete mode 100644 arch/risc-v/src/bl602/hardware/bl602_gpio.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_gpip.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_i2c.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_ir.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_l1c.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_memorymap.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_pds.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_pwm.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_rf.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_sec.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_sf.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_spi.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_tzc.h
delete mode 100644 arch/risc-v/src/bl602/hardware/clic.h
[incubator-nuttx] 02/02: BL602: Use sig mask instead of number for
AHB swrst
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit c8db3293bb6c44a0b4fe0d9554f24e354ec8ae56
Author: Brennan Ashton <ba...@brennanashton.com>
AuthorDate: Wed Dec 30 13:06:13 2020 -0800
BL602: Use sig mask instead of number for AHB swrst
---
arch/risc-v/src/bl602/hardware/bl602_glb.h | 51 +++++++++++++++---------------
1 file changed, 26 insertions(+), 25 deletions(-)
diff --git a/arch/risc-v/src/bl602/hardware/bl602_glb.h b/arch/risc-v/src/bl602/hardware/bl602_glb.h
index 2d19cc7..15b5b2f 100644
--- a/arch/risc-v/src/bl602/hardware/bl602_glb.h
+++ b/arch/risc-v/src/bl602/hardware/bl602_glb.h
@@ -823,30 +823,31 @@
#define TZC_GLB_CTRL_2_GPIO_1_LOCK (1 << 1)
#define TZC_GLB_CTRL_2_GPIO_0_LOCK (1 << 0)
-#define AHB_SLAVE1_
-#define AHB_SLAVE1_GLB (0)
-#define AHB_SLAVE1_RF (1)
-#define AHB_SLAVE1_GPIP (2)
-#define AHB_SLAVE1_DBG (3)
-#define AHB_SLAVE1_SEC (4)
-#define AHB_SLAVE1_TZ1 (5)
-#define AHB_SLAVE1_TZ2 (6)
-#define AHB_SLAVE1_EFUSE (7)
-#define AHB_SLAVE1_CCI (8)
-#define AHB_SLAVE1_L1C (9)
-#define AHB_SLAVE1_RESV10 (10)
-#define AHB_SLAVE1_SFC (11)
-#define AHB_SLAVE1_DMA (12)
-#define AHB_SLAVE1_SDU (13)
-#define AHB_SLAVE1_PDSHBN (14)
-#define AHB_SLAVE1_WRAM (15)
-#define AHB_SLAVE1_UART0 (16)
-#define AHB_SLAVE1_UART1 (17)
-#define AHB_SLAVE1_SPI (18)
-#define AHB_SLAVE1_I2C (19)
-#define AHB_SLAVE1_PWM (20)
-#define AHB_SLAVE1_TMR (21)
-#define AHB_SLAVE1_IRR (22)
-#define AHB_SLAVE1_CKS (23)
+/* Map common names to these SWRST signals */
+
+#define AHB_SLAVE1_GLB (SWRST_CFG1_SWRST_S10)
+#define AHB_SLAVE1_RF (SWRST_CFG1_SWRST_S11)
+#define AHB_SLAVE1_GPIP (SWRST_CFG1_SWRST_S12)
+#define AHB_SLAVE1_DBG (SWRST_CFG1_SWRST_S13)
+#define AHB_SLAVE1_SEC (SWRST_CFG1_SWRST_S14)
+#define AHB_SLAVE1_TZ1 (SWRST_CFG1_SWRST_S15)
+#define AHB_SLAVE1_TZ2 (SWRST_CFG1_SWRST_S16)
+#define AHB_SLAVE1_EFUSE (SWRST_CFG1_SWRST_S17)
+#define AHB_SLAVE1_CCI (SWRST_CFG1_SWRST_S18)
+#define AHB_SLAVE1_L1C (SWRST_CFG1_SWRST_S19)
+
+#define AHB_SLAVE1_SFC (SWRST_CFG1_SWRST_S1B)
+#define AHB_SLAVE1_DMA (SWRST_CFG1_SWRST_S1C)
+#define AHB_SLAVE1_SDU (SWRST_CFG1_SWRST_S1D)
+#define AHB_SLAVE1_PDSHBN (SWRST_CFG1_SWRST_S1E)
+#define AHB_SLAVE1_WRAM (SWRST_CFG1_SWRST_S1F)
+#define AHB_SLAVE1_UART0 (SWRST_CFG1_SWRST_S1A0)
+#define AHB_SLAVE1_UART1 (SWRST_CFG1_SWRST_S1A1)
+#define AHB_SLAVE1_SPI (SWRST_CFG1_SWRST_S1A2)
+#define AHB_SLAVE1_I2C (SWRST_CFG1_SWRST_S1A3)
+#define AHB_SLAVE1_PWM (SWRST_CFG1_SWRST_S1A4)
+#define AHB_SLAVE1_TMR (SWRST_CFG1_SWRST_S1A5)
+#define AHB_SLAVE1_IRR (SWRST_CFG1_SWRST_S1A6)
+#define AHB_SLAVE1_CKS (SWRST_CFG1_SWRST_S1A7)
#endif /* __ARCH_RISCV_SRC_HARDWARE_GLB_H */
[incubator-nuttx] 01/02: bl602: Update register defines and drivers
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit e062bd08cee79fa6b15f27d4898fbde2583e90c8
Author: Brennan Ashton <ba...@brennanashton.com>
AuthorDate: Sun Dec 27 10:53:42 2020 -0800
bl602: Update register defines and drivers
---
arch/risc-v/src/bl602/Kconfig | 40 -
arch/risc-v/src/bl602/bl602_boot2.h | 40 +-
arch/risc-v/src/bl602/bl602_glb.c | 87 +-
.../bl602/{hardware/bl602_clint.h => bl602_glb.h} | 51 +-
arch/risc-v/src/bl602/bl602_gpio.c | 241 +-
arch/risc-v/src/bl602/bl602_gpio.h | 297 ++
arch/risc-v/src/bl602/bl602_hbn.c | 18 +-
.../board.h => arch/risc-v/src/bl602/bl602_hbn.h | 37 +-
arch/risc-v/src/bl602/bl602_irq.c | 10 +-
arch/risc-v/src/bl602/bl602_lowputc.c | 294 +-
arch/risc-v/src/bl602/bl602_lowputc.h | 17 +-
arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c | 42 +-
arch/risc-v/src/bl602/bl602_serial.c | 297 +-
arch/risc-v/src/bl602/bl602_start.c | 19 +-
arch/risc-v/src/bl602/bl602_tim.c | 318 +-
arch/risc-v/src/bl602/bl602_tim.h | 513 ++
arch/risc-v/src/bl602/bl602_tim_lowerhalf.c | 35 +-
arch/risc-v/src/bl602/bl602_tim_lowerhalf.h | 5 +-
arch/risc-v/src/bl602/bl602_timerisr.c | 10 +-
arch/risc-v/src/bl602/hardware/bl602_aon.h | 387 ++
arch/risc-v/src/bl602/hardware/bl602_cci.h | 69 +
.../risc-v/src/bl602/hardware/bl602_cks.h | 50 +-
.../risc-v/src/bl602/hardware/bl602_clic.h | 53 +-
arch/risc-v/src/bl602/hardware/bl602_common.h | 183 -
arch/risc-v/src/bl602/hardware/bl602_dma.h | 254 +
arch/risc-v/src/bl602/hardware/bl602_ef.h | 372 ++
arch/risc-v/src/bl602/hardware/bl602_glb.h | 5055 ++++----------------
arch/risc-v/src/bl602/hardware/bl602_gpio.h | 501 --
arch/risc-v/src/bl602/hardware/bl602_gpip.h | 105 +
arch/risc-v/src/bl602/hardware/bl602_hbn.h | 801 +---
arch/risc-v/src/bl602/hardware/bl602_i2c.h | 154 +
arch/risc-v/src/bl602/hardware/bl602_ir.h | 155 +
arch/risc-v/src/bl602/hardware/bl602_l1c.h | 90 +
arch/risc-v/src/bl602/hardware/bl602_memorymap.h | 60 +
arch/risc-v/src/bl602/hardware/bl602_pds.h | 243 +
arch/risc-v/src/bl602/hardware/bl602_pwm.h | 143 +
arch/risc-v/src/bl602/hardware/bl602_rf.h | 1639 +++++++
arch/risc-v/src/bl602/hardware/bl602_sec.h | 399 ++
arch/risc-v/src/bl602/hardware/bl602_sf.h | 449 ++
arch/risc-v/src/bl602/hardware/bl602_spi.h | 139 +
arch/risc-v/src/bl602/hardware/bl602_timer.h | 756 +--
arch/risc-v/src/bl602/hardware/bl602_tzc.h | 135 +
arch/risc-v/src/bl602/hardware/bl602_uart.h | 858 +---
arch/risc-v/src/bl602/hardware/clic.h | 43 -
boards/risc-v/bl602/bl602evb/include/board.h | 9 +
45 files changed, 7643 insertions(+), 7830 deletions(-)
diff --git a/arch/risc-v/src/bl602/Kconfig b/arch/risc-v/src/bl602/Kconfig
index ea59f21..8be82cf 100644
--- a/arch/risc-v/src/bl602/Kconfig
+++ b/arch/risc-v/src/bl602/Kconfig
@@ -18,26 +18,6 @@ config BL602_UART0
bool
default n
-config BL602_UART0_TX_PIN
- int "UART0 tx pin num"
- default 16
- depends on BL602_UART0
-
-config BL602_UART0_RX_PIN
- int "UART0 rx pin num"
- default 7
- depends on BL602_UART0
-
-config BL602_UART0_RTS_PIN
- int "UART0 rts pin num"
- default -1
- depends on BL602_UART0
-
-config BL602_UART0_CTS_PIN
- int "UART0 cts pin num"
- default -1
- depends on BL602_UART0
-
config BL602_HAVE_UART1
bool "UART1"
select BL602_UART1
@@ -48,26 +28,6 @@ config BL602_HAVE_UART1
config BL602_UART1
bool
default n
-
-config BL602_UART1_TX_PIN
- int "UART1 tx pin num"
- default 4
- depends on BL602_UART1
-
-config BL602_UART1_RX_PIN
- int "UART1 rx pin num"
- default 3
- depends on BL602_UART1
-
-config BL602_UART1_RTS_PIN
- int "UART1 rts pin num"
- default -1
- depends on BL602_UART1
-
-config BL602_UART1_CTS_PIN
- int "UART1 cts pin num"
- default -1
- depends on BL602_UART1
config BL602_TIMER0
bool "TIMER0"
diff --git a/arch/risc-v/src/bl602/bl602_boot2.h b/arch/risc-v/src/bl602/bl602_boot2.h
index f6624ff..2ddba45 100644
--- a/arch/risc-v/src/bl602/bl602_boot2.h
+++ b/arch/risc-v/src/bl602/bl602_boot2.h
@@ -33,22 +33,15 @@
/* Partition table error type definition */
-#define PT_ERROR_SUCCESS 0 /* Partition table error type:success */
-#define PT_ERROR_TABLE_NOT_VALID \
- 1 /* Partition table error type:entry not found */
-#define PT_ERROR_ENTRY_NOT_FOUND \
- 2 /* Partition table error type:entry not found */
-#define PT_ERROR_ENTRY_UPDATE_FAIL \
- 3 /* Partition table error type:entry update fail */
-#define PT_ERROR_CRC32 4 /* Partition table error type:crc32 error */
-#define PT_ERROR_PARAMETER \
- 5 /* Partition table error type:input parameter error */
-#define PT_ERROR_FALSH_READ \
- 6 /* Partition table error type:flash read error */
-#define PT_ERROR_FALSH_WRITE \
- 7 /* Partition table error type:flash write error */
-#define PT_ERROR_FALSH_ERASE \
- 8 /* Partition table error type:flash erase error */
+#define PT_ERROR_SUCCESS 0 /* Success */
+#define PT_ERROR_TABLE_NOT_VALID 1 /* Table not valid */
+#define PT_ERROR_ENTRY_NOT_FOUND 2 /* Entry not found */
+#define PT_ERROR_ENTRY_UPDATE_FAIL 3 /* Entry update fail */
+#define PT_ERROR_CRC32 4 /* CRC32 error */
+#define PT_ERROR_PARAMETER 5 /* Input parameter error */
+#define PT_ERROR_FALSH_READ 6 /* Flash read error */
+#define PT_ERROR_FALSH_WRITE 7 /* Flash write error */
+#define PT_ERROR_FALSH_ERASE 8 /* Flash erase error */
/* Partition id type definition */
@@ -70,10 +63,10 @@
/* Partition table config definition */
-struct pt_table_config_s
+struct pt_config_s
{
uint32_t magic_code; /* Partition table magic code */
- uint16_t version; /* Partition table verdion */
+ uint16_t version; /* Partition table version */
uint16_t entry_cnt; /* Partition table entry count */
uint32_t age; /* Partition table age */
uint32_t crc32; /* Partition table CRC32 value */
@@ -81,7 +74,7 @@ struct pt_table_config_s
/* Partition table entry config definition */
-struct pt_table_entry_config_s
+struct pt_entry_config_s
{
uint8_t type; /* Partition entry type */
uint8_t device; /* Partition entry device */
@@ -95,12 +88,11 @@ struct pt_table_entry_config_s
/* Partition table stuff config definition */
-struct pt_table_stuff_config_s
+struct pt_stuff_config_s
{
- struct pt_table_config_s pt_table; /* Partition table */
- struct pt_table_entry_config_s
- pt_entries[PT_ENTRY_MAX]; /* Partition entries */
- uint32_t crc32; /* Partition entries crc32 */
+ struct pt_config_s table; /* Partition table */
+ struct pt_entry_config_s entries[PT_ENTRY_MAX]; /* Entries */
+ uint32_t crc32; /* Entries crc32 */
};
#endif /* __ASSEMBLY__ */
diff --git a/arch/risc-v/src/bl602/bl602_glb.c b/arch/risc-v/src/bl602/bl602_glb.c
index 092f3e3..bf709db 100644
--- a/arch/risc-v/src/bl602/bl602_glb.c
+++ b/arch/risc-v/src/bl602/bl602_glb.c
@@ -22,87 +22,52 @@
* Included Files
****************************************************************************/
-#include "hardware/bl602_glb.h"
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
#include "riscv_arch.h"
+#include "hardware/bl602_glb.h"
/****************************************************************************
- * Public Functions
+ * Pre-Processor Declarations
****************************************************************************/
+#define nop() asm volatile ("nop")
+
/****************************************************************************
- * Name: bl602_glb_uart_fun_sel
- *
- * Description:
- * Select UART signal function.
- *
- * Input Parameters:
- * sig: UART signal
- * fun: UART function
- *
- * Returned Value:
- * None
- *
+ * Public Functions
****************************************************************************/
-void bl602_glb_uart_fun_sel(int sig, int fun)
-{
- uint32_t sig_pos = 0;
- uint32_t tmp_val = 0;
-
- tmp_val = getreg32(GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
-
- sig_pos = (sig * 4);
-
- /* Clear original val */
-
- tmp_val = tmp_val & (~(0xf << sig_pos));
-
- /* Set new value */
-
- tmp_val = tmp_val | (fun << sig_pos);
- putreg32(tmp_val, GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
-}
-
/****************************************************************************
- * Name: bl602_glb_ahb_slave1_reset
+ * Name: bl602_swrst_ahb_slave1
*
* Description:
- * Select UART signal function.
+ * SW Reset ahb slave.
*
* Input Parameters:
- * sig: UART signal
- * fun: UART function
+ * slave1: reset signal
*
* Returned Value:
* None
*
****************************************************************************/
-void bl602_glb_ahb_slave1_reset(uint32_t slave1)
+void bl602_swrst_ahb_slave1(uint32_t slave1)
{
- uint32_t tmp_val = 0;
-
- tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
- tmp_val &= (~(1 << slave1));
- putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
-
- /* It is to prevent glitch, which cannot be accessed via bus immediately
- * after certain register operations, so some nop is added
+ /* To prevent glitch from accessing bus immediately
+ * after certain register operations, so some nop delay is added
*/
- BL_DRV_DUMMY();
-
- tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
- tmp_val |= (1 << slave1);
- putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
-
- /* It is to prevent glitch, which cannot be accessed via bus immediately
- * after certain register operations, so some nop is added
- */
-
- BL_DRV_DUMMY();
-
- tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
- tmp_val &= (~(1 << slave1));
- putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
+ modifyreg32(BL602_SWRST_CFG1, slave1, 0);
+ nop();
+ nop();
+ nop();
+ nop();
+ modifyreg32(BL602_SWRST_CFG1, 0, slave1);
+ nop();
+ nop();
+ nop();
+ nop();
+ modifyreg32(BL602_SWRST_CFG1, slave1, 0);
}
diff --git a/arch/risc-v/src/bl602/hardware/bl602_clint.h b/arch/risc-v/src/bl602/bl602_glb.h
similarity index 57%
rename from arch/risc-v/src/bl602/hardware/bl602_clint.h
rename to arch/risc-v/src/bl602/bl602_glb.h
index b147a11..519035a 100644
--- a/arch/risc-v/src/bl602/hardware/bl602_clint.h
+++ b/arch/risc-v/src/bl602/bl602_glb.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/bl602/hardware/bl602_clint.h
+ * arch/risc-v/src/bl602/bl602_glb.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,23 +18,56 @@
*
****************************************************************************/
-#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H
-#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H
+#ifndef __ARCH_RISCV_SRC_BL602_BL602_GLB_H
+#define __ARCH_RISCV_SRC_BL602_BL602_GLB_H
/****************************************************************************
* Included Files
****************************************************************************/
+#include <nuttx/config.h>
+
#include <stdint.h>
/****************************************************************************
- * Pre-processor Definitions
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_swrst_ahb_slave1
+ *
+ * Description:
+ * SW Reset ahb slave.
+ *
+ * Input Parameters:
+ * slave1: reset signal
+ *
+ * Returned Value:
+ * None
+ *
****************************************************************************/
-#define BL602_CLINT_BASE (0x02000000)
+void bl602_swrst_ahb_slave1(uint32_t slave1);
-#define BL602_MTIMER_HIGH ((uint32_t *)(BL602_CLINT_BASE + 0xBFFC))
-#define BL602_MTIMER_LOW ((uint32_t *)(BL602_CLINT_BASE + 0xBFF8))
-#define BL602_MTIMER_CMP ((uint64_t *)(BL602_CLINT_BASE + 0x4000))
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
-#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H */
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_BL602_GLB_H */
diff --git a/arch/risc-v/src/bl602/bl602_gpio.c b/arch/risc-v/src/bl602/bl602_gpio.c
index 4725cbe..c671a5d 100644
--- a/arch/risc-v/src/bl602/bl602_gpio.c
+++ b/arch/risc-v/src/bl602/bl602_gpio.c
@@ -23,122 +23,183 @@
****************************************************************************/
#include <stdint.h>
-#include "hardware/bl602_gpio.h"
-#include "hardware/bl602_glb.h"
+
#include "riscv_arch.h"
+#include "hardware/bl602_glb.h"
+#include "bl602_gpio.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+const uintptr_t g_gpio_base[] =
+{
+ BL602_GPIO_CFGCTL0,
+ BL602_GPIO_CFGCTL1,
+ BL602_GPIO_CFGCTL2,
+ BL602_GPIO_CFGCTL3,
+ BL602_GPIO_CFGCTL4,
+ BL602_GPIO_CFGCTL5,
+ BL602_GPIO_CFGCTL6,
+ BL602_GPIO_CFGCTL7,
+ BL602_GPIO_CFGCTL8,
+ BL602_GPIO_CFGCTL9,
+ BL602_GPIO_CFGCTL10,
+ BL602_GPIO_CFGCTL11,
+ BL602_GPIO_CFGCTL12,
+ BL602_GPIO_CFGCTL13,
+ BL602_GPIO_CFGCTL14
+};
+
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: bl602_gpio_init
+ * Name: bl602_configgpio
*
* Description:
- * Init a gpio pin.
- *
- * Input Parameters:
- * cfg: gpio configuration
+ * Configure a GPIO pin based on bit-encoded description of the pin.
*
* Returned Value:
- * Description of the value returned by this function (if any),
- * including an enumeration of all possible error values.
+ * OK on success
+ * ERROR on invalid port.
+ *
+ ****************************************************************************/
+
+int bl602_configgpio(gpio_pinset_t cfgset)
+{
+ uint32_t mask;
+ uintptr_t regaddr;
+ uint32_t cfg = 0;
+ uint8_t pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+
+ if (pin > 27)
+ {
+ return ERROR;
+ }
+
+ /* The configuration masks will just use the defines for GPIO0 which is
+ * the same as all GPIO config bit fields besides the offset.
+ */
+
+ if (cfgset & GPIO_INPUT)
+ {
+ cfg |= GPIO_CFGCTL0_GPIO_0_IE;
+ }
+
+ if (cfgset & GPIO_PULLUP)
+ {
+ cfg |= GPIO_CFGCTL0_GPIO_0_PU;
+ }
+
+ if (cfgset & GPIO_PULLDOWN)
+ {
+ cfg |= GPIO_CFGCTL0_GPIO_0_PD;
+ }
+
+ if (cfgset & GPIO_DRV_MASK)
+ {
+ cfg |= ((cfgset & GPIO_DRV_MASK) >> GPIO_DRV_SHIFT) << \
+ GPIO_CFGCTL0_GPIO_0_DRV_SHIFT;
+ }
+
+ if (cfgset & GPIO_SMT_EN)
+ {
+ cfg |= GPIO_CFGCTL0_GPIO_0_SMT;
+ }
+
+ if (cfgset & GPIO_FUNC_MASK)
+ {
+ cfg |= ((cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT) << \
+ GPIO_CFGCTL0_GPIO_0_FUNC_SEL_SHIFT;
+ }
+
+ /* Grab the register that contains the pin config, this is shared between
+ * two pins so we must shift accordingly.
+ */
+
+ regaddr = g_gpio_base[pin / 2];
+ mask = 0xffff;
+ if ((pin & 1) == 1)
+ {
+ cfg = cfg << 16;
+ mask = mask << 16;
+ }
+
+ modifyreg32(regaddr, mask, cfg);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: bl602_config_uart_sel
*
- * Assumptions/Limitations:
- * Anything else that one might need to know to use this function.
+ * Description:
+ * Configure the GPIO UART pin selection mux based on bit-encoded
+ * description of the pin and the selection signal
+ *
+ * Returned Value:
+ * OK on success
+ * ERROR on invalid port.
*
****************************************************************************/
-void bl602_gpio_init(struct gpio_cfg_s *cfg)
+int bl602_config_uart_sel(gpio_pinset_t pinset, uint8_t sig_sel)
{
- uint8_t gpio_pin = cfg->gpio_pin;
- uint32_t *p_out;
- uint32_t pos;
- uint32_t tmp_out;
- uint32_t tmp_val;
+ irqstate_t flags;
+ uint8_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+ uint8_t sel_idx;
+ uint32_t reg;
+
+ if ((pin > 27) || sig_sel > UART_SIG_SEL_UART1_RXD)
+ {
+ return ERROR;
+ }
- p_out = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET +
- ((gpio_pin >> 5) << 2));
- pos = gpio_pin % 32;
- tmp_out = *p_out;
+ sel_idx = pin % 8;
+ flags = enter_critical_section();
- /* Disable output anyway */
+ reg = getreg32(BL602_UART_SIG_SEL_0);
+ reg &= ~(0xf << (sel_idx * 4));
+ reg |= sig_sel << (sel_idx * 4);
+ putreg32(reg, BL602_UART_SIG_SEL_0);
- tmp_out &= (~(1 << pos));
- *p_out = tmp_out;
+ leave_critical_section(flags);
+ return OK;
+}
- tmp_val = getreg32(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
+/****************************************************************************
+ * Name: bl602_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
- if (gpio_pin % 2 == 0)
+void bl602_gpiowrite(gpio_pinset_t pinset, bool value)
+{
+ uint8_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+ if (value)
{
- /* Set input or output */
-
- if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
- {
- tmp_val = tmp_val & GLB_REG_GPIO_0_IE_UMSK;
- tmp_out |= (1 << pos);
- }
- else
- {
- tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_IE_POS);
- }
-
- /* Set pull up or down */
-
- tmp_val &= GLB_REG_GPIO_0_PU_UMSK;
- tmp_val &= GLB_REG_GPIO_0_PD_UMSK;
- if (cfg->pull_type == GPIO_PULL_UP)
- {
- tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_PU_POS);
- }
- else if (cfg->pull_type == GPIO_PULL_DOWN)
- {
- tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_PD_POS);
- }
-
- tmp_val = (tmp_val & GLB_REG_GPIO_0_DRV_UMSK) |
- (cfg->drive << GLB_REG_GPIO_0_DRV_POS);
- tmp_val = (tmp_val & GLB_REG_GPIO_0_SMT_UMSK) |
- (cfg->smt_ctrl << GLB_REG_GPIO_0_SMT_POS);
- tmp_val = (tmp_val & GLB_REG_GPIO_0_FUNC_SEL_UMSK) |
- (cfg->gpio_fun << GLB_REG_GPIO_0_FUNC_SEL_POS);
+ modifyreg32(BL602_GPIO_CFGCTL32, 0, (1 << pin));
}
else
{
- /* Set input or output */
-
- if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
- {
- tmp_val &= GLB_REG_GPIO_1_IE_UMSK;
- tmp_out |= (1 << pos);
- }
- else
- {
- tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_IE_POS);
- }
-
- /* Set pull up or down */
-
- tmp_val &= GLB_REG_GPIO_1_PU_UMSK;
- tmp_val &= GLB_REG_GPIO_1_PD_UMSK;
- if (cfg->pull_type == GPIO_PULL_UP)
- {
- tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_PU_POS);
- }
- else if (cfg->pull_type == GPIO_PULL_DOWN)
- {
- tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_PD_POS);
- }
-
- tmp_val = (tmp_val & GLB_REG_GPIO_1_DRV_UMSK) |
- (cfg->drive << GLB_REG_GPIO_1_DRV_POS);
- tmp_val = (tmp_val & GLB_REG_GPIO_1_SMT_UMSK) |
- (cfg->smt_ctrl << GLB_REG_GPIO_1_SMT_POS);
- tmp_val = (tmp_val & GLB_REG_GPIO_1_FUNC_SEL_UMSK) |
- (cfg->gpio_fun << GLB_REG_GPIO_1_FUNC_SEL_POS);
+ modifyreg32(BL602_GPIO_CFGCTL32, (1 << pin), 0);
}
+}
- putreg32(tmp_val, GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
+/****************************************************************************
+ * Name: bl602_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
- *p_out = tmp_out;
+bool bl602_gpioread(gpio_pinset_t pinset)
+{
+ uint8_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
+ return (getreg32(BL602_GPIO_CFGCTL30) & (1 << pin)) == 1;
}
diff --git a/arch/risc-v/src/bl602/bl602_gpio.h b/arch/risc-v/src/bl602/bl602_gpio.h
new file mode 100644
index 0000000..b253454
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_gpio.h
@@ -0,0 +1,297 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_BL602_GPIO_H
+#define __ARCH_RISCV_SRC_BL602_BL602_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+# include <stdbool.h>
+#endif
+
+#include <nuttx/irq.h>
+
+#include "chip.h"
+#include "hardware/bl602_glb.h"
+
+/****************************************************************************
+ * Pre-Processor Declarations
+ ****************************************************************************/
+
+/* Bit-encoded input to bl602_configgpio() */
+
+/* Each port bit of the general-purpose I/O (GPIO) ports can be individually
+ * configured by software in several modes:
+ *
+ * - Input floating
+ * - Input pull-up
+ * - Input-pull-down
+ * - Output floating
+ * - Output with pull-up
+ * - Output with pull-down
+ * - Alternate function (Digital and Analog)
+ *
+ * 16-bit Encoding: 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .MUU DDSF FFFP PPPP
+ */
+
+/* Mode:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .M.. .... .... ....
+ */
+
+#define GPIO_MODE_SHIFT (14) /* Bits 14: Port Mode */
+#define GPIO_MODE_MASK (1 << GPIO_MODE_SHIFT)
+# define GPIO_INPUT (1 << GPIO_MODE_SHIFT) /* Input Enable */
+
+/* Input/output pull-ups/downs:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * ..UU .... .... ....
+ */
+
+#define GPIO_PUPD_SHIFT (12) /* Bits 16-17: Pull-up/down */
+#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT)
+# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
+# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */
+# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */
+
+/* Drive:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... DD.. .... ....
+ */
+
+#define GPIO_DRV_SHIFT (10) /* Bits 10-11: Drive */
+#define GPIO_DRV_MASK (3 << GPIO_DRV_SHIFT)
+# define GPIO_DRV_0 (0 << GPIO_DRV_SHIFT)
+# define GPIO_DRV_1 (1 << GPIO_DRV_SHIFT)
+# define GPIO_DRV_2 (2 << GPIO_DRV_SHIFT)
+# define GPIO_DRV_3 (3 << GPIO_DRV_SHIFT)
+
+/* Input Schmitt trigger:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... ..S. .... ....
+ */
+
+#define GPIO_SMT_SHIFT (9) /* Bits 9: SMT Enable */
+#define GPIO_SMT_MASK (3 << GPIO_SMT_SHIFT)
+# define GPIO_SMT_DIS (0 << GPIO_SMT_SHIFT)
+# define GPIO_SMT_EN (1 << GPIO_SMT_SHIFT)
+
+/* GPIO type selection:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... ...F FFF. ....
+ */
+
+#define GPIO_FUNC_SHIFT (5) /* Bits 5-8: GPIO Type */
+#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT)
+# define GPIO_FUNC_SDIO (1 << GPIO_FUNC_SHIFT) /* SDIO */
+# define GPIO_FUNC_FLASH (2 << GPIO_FUNC_SHIFT) /* Flash */
+# define GPIO_FUNC_SPI (4 << GPIO_FUNC_SHIFT) /* SPI */
+# define GPIO_FUNC_I2C (6 << GPIO_FUNC_SHIFT) /* I2C */
+# define GPIO_FUNC_UART (7 << GPIO_FUNC_SHIFT) /* UART */
+# define GPIO_FUNC_PWM (8 << GPIO_FUNC_SHIFT) /* PWM */
+# define GPIO_FUNC_EXT_PA (9 << GPIO_FUNC_SHIFT) /* Analog */
+# define GPIO_FUNC_ANA (10 << GPIO_FUNC_SHIFT) /* Analog */
+# define GPIO_FUNC_SWGPIO (11 << GPIO_FUNC_SHIFT) /* Software GPIO */
+# define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT) /* JTAG */
+
+/* This identifies the bit in the port:
+ *
+ * 1111 1100 0000 0000
+ * 5432 1098 7654 3210
+ * ---- ---- ---- ----
+ * .... .... ...P PPPP
+ */
+
+#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-28 */
+#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT)
+# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
+# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
+# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
+# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
+# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
+# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
+# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
+# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
+# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
+# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
+# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
+# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
+# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
+# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
+# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
+# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
+# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
+# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
+# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
+# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
+# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
+# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
+# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
+# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
+# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
+# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
+# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
+# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
+# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* The smallest integer type that can hold the GPIO encoding */
+
+typedef uint16_t gpio_pinset_t;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ * Returned Value:
+ * OK on success
+ * ERROR on invalid port.
+ *
+ ****************************************************************************/
+
+int bl602_configgpio(gpio_pinset_t cfgset);
+
+/****************************************************************************
+ * Name: bl602_config_uart_sel
+ *
+ * Description:
+ * Configure the GPIO UART pin selection mux based on bit-encoded
+ * description of the pin and the selection signal
+ *
+ * Returned Value:
+ * OK on success
+ * ERROR on invalid port.
+ *
+ ****************************************************************************/
+
+int bl602_config_uart_sel(gpio_pinset_t cfgset, uint8_t sig_sel);
+
+/****************************************************************************
+ * Name: bl602_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void bl602_gpiowrite(gpio_pinset_t pinset, bool value);
+
+/****************************************************************************
+ * Name: bl602_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool bl602_gpioread(gpio_pinset_t pinset);
+
+/****************************************************************************
+ * Name: bl602_gpiosetevent
+ *
+ * Description:
+ * Sets/clears GPIO based event and interrupt triggers.
+ *
+ * Input Parameters:
+ * - pinset: GPIO pin configuration
+ * - risingedge: Enables interrupt on rising edges
+ * - fallingedge: Enables interrupt on falling edges
+ * - event: Generate event when set
+ * - func: When non-NULL, generate interrupt
+ * - arg: Argument passed to the interrupt callback
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure indicating the
+ * nature of the failure.
+ *
+ ****************************************************************************/
+
+int bl602_gpiosetevent(gpio_pinset_t pinset, bool risingedge,
+ bool fallingedge, bool event, xcpt_t func, void *arg);
+
+/****************************************************************************
+ * Function: bl602_dumpgpio
+ *
+ * Description:
+ * Dump all GPIO registers associated with the provided base address
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+int bl602_dumpgpio(gpio_pinset_t pinset, const char *msg);
+#else
+# define bl602_dumpgpio(p,m)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_BL602_GPIO_H */
diff --git a/arch/risc-v/src/bl602/bl602_hbn.c b/arch/risc-v/src/bl602/bl602_hbn.c
index b90e1d8..1e057d4 100644
--- a/arch/risc-v/src/bl602/bl602_hbn.c
+++ b/arch/risc-v/src/bl602/bl602_hbn.c
@@ -36,7 +36,7 @@
* Select uart clock source.
*
* Input Parameters:
- * clk_sel: uart clock type selection
+ * clk_sel: uart clock type selection, 0 for FCLK or 1 for 160MHz CLK
*
* Returned Value:
* Description of the value returned by this function (if any),
@@ -47,12 +47,14 @@
*
****************************************************************************/
-void bl602_hbn_set_uart_clk_sel(int clk_sel)
+void bl602_set_uart_clk_sel(int clk_sel)
{
- uint32_t tmp_val;
-
- tmp_val = getreg32(HBN_BASE + HBN_GLB_OFFSET);
- tmp_val &= ~(1 << 2);
- tmp_val |= (clk_sel << 2);
- putreg32(tmp_val, HBN_BASE + HBN_GLB_OFFSET);
+ if (clk_sel)
+ {
+ modifyreg32(BL602_HBN_GLB, 0, HBN_GLB_HBN_UART_CLK_SEL);
+ }
+ else
+ {
+ modifyreg32(BL602_HBN_GLB, HBN_GLB_HBN_UART_CLK_SEL, 0);
+ }
}
diff --git a/boards/risc-v/bl602/bl602evb/include/board.h b/arch/risc-v/src/bl602/bl602_hbn.h
similarity index 73%
copy from boards/risc-v/bl602/bl602evb/include/board.h
copy to arch/risc-v/src/bl602/bl602_hbn.h
index be3f808..b6808e1 100644
--- a/boards/risc-v/bl602/bl602evb/include/board.h
+++ b/arch/risc-v/src/bl602/bl602_hbn.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/risc-v/bl602/bl602evb/include/board.h
+ * arch/risc-v/src/bl602/bl602_hbn.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,8 +18,8 @@
*
****************************************************************************/
-#ifndef __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
-#define __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
+#ifndef __ARCH_RISCV_SRC_BL602_BL602_HBN_H
+#define __ARCH_RISCV_SRC_BL602_BL602_HBN_H
/****************************************************************************
* Included Files
@@ -27,20 +27,14 @@
#include <nuttx/config.h>
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
+#include <stdint.h>
/****************************************************************************
- * Public Types
+ * Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
@@ -55,14 +49,29 @@ extern "C"
****************************************************************************/
/****************************************************************************
- * Name: litex_boardinitialize
+ * Name: bl602_hbn_set_uart_clk_sel
+ *
+ * Description:
+ * Select uart clock source.
+ *
+ * Input Parameters:
+ * clk_sel: uart clock type selection, 0 for FCLK or 1 for 160MHz CLK
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
****************************************************************************/
-void bl602_boardinitialize(void);
+void bl602_set_uart_clk_sel(int clk_sel);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
+
#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_RISC_V_BL602_BL602EVB_INCLUDE_BOARD_H */
+#endif /* __ARCH_RISCV_SRC_BL602_BL602_HBN_H */
diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c
index 9f35b3a..8bacc6c 100644
--- a/arch/risc-v/src/bl602/bl602_irq.c
+++ b/arch/risc-v/src/bl602/bl602_irq.c
@@ -36,7 +36,7 @@
#include "riscv_internal.h"
#include "riscv_arch.h"
-#include "hardware/clic.h"
+#include "hardware/bl602_clic.h"
#include "chip.h"
@@ -46,22 +46,22 @@
static inline void bl_irq_enable(unsigned int source)
{
- putreg8(1, CLIC_HART0_ADDR + CLIC_INTIE + source);
+ putreg8(1, BL602_CLIC_INTIE + source);
}
static inline void bl_irq_disable(unsigned int source)
{
- putreg8(0, CLIC_HART0_ADDR + CLIC_INTIE + source);
+ putreg8(0, BL602_CLIC_INTIE + source);
}
static inline void bl_irq_pending_set(unsigned int source)
{
- putreg8(1, CLIC_HART0_ADDR + CLIC_INTIP + source);
+ putreg8(1, BL602_CLIC_INTIP + source);
}
static inline void bl_irq_pending_clear(unsigned int source)
{
- putreg8(0, CLIC_HART0_ADDR + CLIC_INTIP + source);
+ putreg8(0, BL602_CLIC_INTIP + source);
}
/****************************************************************************
diff --git a/arch/risc-v/src/bl602/bl602_lowputc.c b/arch/risc-v/src/bl602/bl602_lowputc.c
index 2bddb0a..a8bb8ca 100644
--- a/arch/risc-v/src/bl602/bl602_lowputc.c
+++ b/arch/risc-v/src/bl602/bl602_lowputc.c
@@ -37,12 +37,12 @@
#include <arch/board/board.h>
-#include "hardware/bl602_gpio.h"
-#include "hardware/bl602_glb.h"
#include "hardware/bl602_hbn.h"
#include "hardware/bl602_uart.h"
#include "bl602_lowputc.h"
+#include "bl602_gpio.h"
+#include "bl602_hbn.h"
#include "riscv_arch.h"
#include "riscv_internal.h"
@@ -53,12 +53,15 @@
* Pre-processor Definitions
****************************************************************************/
+#define UART_PARITY_NONE (0)
+#define UART_PARITY_ODD (1)
+#define UART_PARITY_EVEN (2)
+
/* Select UART parameters for the selected console */
#ifdef HAVE_SERIAL_CONSOLE
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
#define BL602_CONSOLE_IDX 0
-#define BL602_CONSOLE_BASE UART0_BASE
#define BL602_CONSOLE_BAUD CONFIG_UART0_BAUD
#define BL602_CONSOLE_BITS CONFIG_UART0_BITS
#define BL602_CONSOLE_PARITY CONFIG_UART0_PARITY
@@ -73,14 +76,10 @@
#else
#define BL602_CONSOLE_OFLOWCTL 0
#endif
-#define BL602_CONSOLE_TX_PIN CONFIG_BL602_UART0_TX_PIN
-#define BL602_CONSOLE_RX_PIN CONFIG_BL602_UART0_RX_PIN
-#define BL602_CONSOLE_RTS_PIN CONFIG_BL602_UART0_RTS_PIN
-#define BL602_CONSOLE_CTS_PIN CONFIG_BL602_UART0_CTS_PIN
+#endif
#define HAVE_UART
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
#define BL602_CONSOLE_IDX 1
-#define BL602_CONSOLE_BASE UART1_BASE
#define BL602_CONSOLE_BAUD CONFIG_UART1_BAUD
#define BL602_CONSOLE_BITS CONFIG_UART1_BITS
#define BL602_CONSOLE_PARITY CONFIG_UART1_PARITY
@@ -95,15 +94,11 @@
#else
#define BL602_CONSOLE_OFLOWCTL 0
#endif
-#define BL602_CONSOLE_TX_PIN CONFIG_BL602_UART1_TX_PIN
-#define BL602_CONSOLE_RX_PIN CONFIG_BL602_UART1_RX_PIN
-#define BL602_CONSOLE_RTS_PIN CONFIG_BL602_UART1_RTS_PIN
-#define BL602_CONSOLE_CTS_PIN CONFIG_BL602_UART1_CTS_PIN
#define HAVE_UART
-#endif
#endif /* HAVE_CONSOLE */
#define _BL602_UART_CLOCK (160 * 1000 * 1000UL) /* UART clock */
+#define HBN_UART_CLK_160M (1)
/****************************************************************************
* Private Data
@@ -128,10 +123,6 @@ static const struct uart_config_s g_bl602_console_config =
#else
.oflow_ctl = 0,
#endif
- .tx_pin = BL602_CONSOLE_TX_PIN,
- .rx_pin = BL602_CONSOLE_RX_PIN,
- .rts_pin = BL602_CONSOLE_RTS_PIN,
- .cts_pin = BL602_CONSOLE_CTS_PIN,
};
#endif /* HAVE_SERIAL_CONSOLE */
@@ -139,145 +130,99 @@ static const struct uart_config_s g_bl602_console_config =
* Private Functions
****************************************************************************/
-static void uart_gpio_init(uint8_t id,
- uint8_t tx_pin,
- uint8_t rx_pin,
- uint8_t cts_pin,
- uint8_t rts_pin)
+static void bl602_uart_gpio_init(uint8_t id)
{
- struct gpio_cfg_s cfg;
- int tx_sigfun;
- int rx_sigfun;
-
- cfg.drive = 1;
- cfg.smt_ctrl = 1;
- cfg.gpio_fun = 7;
-
- cfg.gpio_pin = rx_pin;
- cfg.gpio_mode = GPIO_MODE_AF;
- cfg.pull_type = GPIO_PULL_UP;
- bl602_gpio_init(&cfg);
-
- cfg.gpio_pin = tx_pin;
- cfg.gpio_mode = GPIO_MODE_AF;
- cfg.pull_type = GPIO_PULL_UP;
- bl602_gpio_init(&cfg);
-
- /* select uart gpio function */
-
if (id == 0)
{
- tx_sigfun = GLB_UART_SIG_FUN_UART0_TXD;
- rx_sigfun = GLB_UART_SIG_FUN_UART0_RXD;
+#ifdef BOARD_UART_0_TX_PIN
+ bl602_config_uart_sel(BOARD_UART_0_TX_PIN, UART_SIG_SEL_UART0_TXD);
+ bl602_configgpio(BOARD_UART_0_TX_PIN);
+#endif
+#ifdef BOARD_UART_0_RX_PIN
+ bl602_config_uart_sel(BOARD_UART_0_RX_PIN, UART_SIG_SEL_UART0_RXD);
+ bl602_configgpio(BOARD_UART_0_RX_PIN);
+#endif
+#ifdef BOARD_UART_0_CTS_PIN
+ bl602_config_uart_sel(BOARD_UART_0_CTS_PIN, UART_SIG_SEL_UART0_CTS);
+ bl602_configgpio(BOARD_UART_0_CTS_PIN);
+#endif
+#ifdef BOARD_UART_0_RTS_PIN
+ bl602_config_uart_sel(BOARD_UART_0_RTS_PIN, UART_SIG_SEL_UART0_RTS);
+ bl602_configgpio(BOARD_UART_0_RTS_PIN);
+#endif
}
else
{
- tx_sigfun = GLB_UART_SIG_FUN_UART1_TXD;
- rx_sigfun = GLB_UART_SIG_FUN_UART1_RXD;
+#ifdef BOARD_UART_1_TX_PIN
+ bl602_config_uart_sel(BOARD_UART_1_TX_PIN, UART_SIG_SEL_UART1_TXD);
+ bl602_configgpio(BOARD_UART_1_TX_PIN);
+#endif
+#ifdef BOARD_UART_1_RX_PIN
+ bl602_config_uart_sel(BOARD_UART_1_RX_PIN, UART_SIG_SEL_UART1_RXD);
+ bl602_configgpio(BOARD_UART_1_RX_PIN);
+#endif
+#ifdef BOARD_UART_1_CTS_PIN
+ bl602_config_uart_sel(BOARD_UART_1_CTS_PIN, UART_SIG_SEL_UART1_CTS);
+ bl602_configgpio(BOARD_UART_1_CTS_PIN);
+#endif
+#ifdef BOARD_UART_1_RTS_PIN
+ bl602_config_uart_sel(BOARD_UART_1_RTS_PIN, UART_SIG_SEL_UART1_RTS);
+ bl602_configgpio(BOARD_UART_1_RTS_PIN);
+#endif
}
-
- bl602_glb_uart_fun_sel(tx_pin % 8, tx_sigfun);
- bl602_glb_uart_fun_sel(rx_pin % 8, rx_sigfun);
}
static void bl602_enable_uart_clk(uint8_t enable, int clk_sel, uint8_t div)
{
- uint32_t tmp_val;
-
/* disable UART clock first */
- bl602_up_serialmodify(GLB_BASE, GLB_CLK_CFG2_OFFSET, (1 << 4), 0);
+ modifyreg32(BL602_CLK_CFG2, CLK_CFG2_UART_CLK_EN, 0);
/* Set div */
- bl602_up_serialmodify(GLB_BASE, GLB_CLK_CFG2_OFFSET, 0x7, div);
+ modifyreg32(BL602_CLK_CFG2, CLK_CFG2_UART_CLK_DIV_MASK, div);
/* Select clock source for uart */
- bl602_hbn_set_uart_clk_sel(clk_sel);
+ bl602_set_uart_clk_sel(clk_sel);
/* Set enable or disable */
- tmp_val = bl602_up_serialin(GLB_BASE, GLB_CLK_CFG2_OFFSET);
if (enable)
{
- tmp_val |= (1 << 4);
- }
- else
- {
- tmp_val &= ~(1 << 4);
+ modifyreg32(BL602_CLK_CFG2, 0, CLK_CFG2_UART_CLK_EN);
}
-
- bl602_up_serialout(GLB_BASE, GLB_CLK_CFG2_OFFSET, tmp_val);
}
/****************************************************************************
* Public Functions
****************************************************************************/
-uint32_t bl602_up_serialin(uint32_t reg_base, int offset)
-{
- return getreg32(reg_base + offset);
-}
-
-void bl602_up_serialout(uint32_t reg_base, int offset, uint32_t value)
-{
- putreg32(value, reg_base + offset);
-}
-
-void bl602_up_serialmodify(uint32_t reg_base,
- int offset,
- uint32_t clearbits,
- uint32_t setbits)
+void bl602_uart_configure(const struct uart_config_s *config)
{
- modifyreg32(reg_base + offset, clearbits, setbits);
-}
+ uint32_t div;
+ uint32_t fraction;
+ uint32_t tx_cfg;
+ uint32_t rx_cfg;
+ uint8_t clk_div = 3;
-/****************************************************************************
- * Name: bl602_data_setbits
- ****************************************************************************/
-
-static uint32_t bl602_data_setbits(uint32_t data,
- uint32_t start,
- uint32_t len,
- uint32_t value)
-{
- return (((data) & ~((~((~0) << (len))) << (start))) |
- (((value) & ((~((~0) << (len))))) << (start)));
-}
+ bl602_enable_uart_clk(1, HBN_UART_CLK_160M, clk_div);
-void bl602_uart_configure(uint32_t uartbase,
- const struct uart_config_s *config)
-{
- uint32_t tmp_val;
- uint32_t div = 0;
- uint32_t fraction = 0;
- uint32_t tmp_tx_cfg = 0;
- uint32_t tmp_rx_cfg = 0;
- int data_bits;
- int stop_bits;
-
- bl602_enable_uart_clk(1, HBN_UART_CLK_160M, 3);
-
- uart_gpio_init(config->idx,
- config->tx_pin,
- config->rx_pin,
- config->cts_pin,
- config->rts_pin);
+ bl602_uart_gpio_init(config->idx);
/* Disable all interrupt */
- bl602_up_serialmodify(uartbase, UART_INT_MASK_OFFSET, 0, 0xff);
+ modifyreg32(BL602_UART_INT_MASK(config->idx), 0, 0xff);
/* Disable uart before config */
- bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 1, 0);
- bl602_up_serialmodify(uartbase, UART_URX_CONFIG_OFFSET, 1, 0);
+ modifyreg32(BL602_UART_UTX_CONFIG(config->idx), UART_UTX_CONFIG_CR_EN, 0);
+ modifyreg32(BL602_UART_URX_CONFIG(config->idx), UART_URX_CONFIG_CR_EN, 0);
/* cal the baud rate divisor */
- fraction = (_BL602_UART_CLOCK / (3 + 1)) * 10 / config->baud % 10;
- div = (_BL602_UART_CLOCK / (3 + 1)) / config->baud;
+ fraction = (_BL602_UART_CLOCK / (clk_div + 1)) * 10 / config->baud % 10;
+ div = (_BL602_UART_CLOCK / (clk_div + 1)) / config->baud;
if (fraction >= 5)
{
++div;
@@ -285,120 +230,106 @@ void bl602_uart_configure(uint32_t uartbase,
/* set the baud rate register value */
- bl602_up_serialout(uartbase,
- UART_BIT_PRD_OFFSET,
- ((div - 1) << 0x10) | ((div - 1) & 0xffff));
+ putreg32(((div - 1) << 0x10) | ((div - 1) & 0xffff),
+ BL602_UART_BIT_PRD(config->idx));
/* configure parity type */
- tmp_tx_cfg = bl602_up_serialin(uartbase, UART_UTX_CONFIG_OFFSET);
- tmp_rx_cfg = bl602_up_serialin(uartbase, UART_URX_CONFIG_OFFSET);
+ tx_cfg = getreg32(BL602_UART_UTX_CONFIG(config->idx));
+ rx_cfg = getreg32(BL602_UART_URX_CONFIG(config->idx));
switch (config->parity)
{
case UART_PARITY_NONE:
- tmp_tx_cfg &= ~(1 << 4);
- tmp_rx_cfg &= ~(1 << 4);
+ tx_cfg &= ~UART_UTX_CONFIG_CR_PRT_EN;
+ rx_cfg &= ~UART_URX_CONFIG_CR_PRT_EN;
break;
case UART_PARITY_ODD:
- tmp_tx_cfg |= 1 << 4;
- tmp_tx_cfg |= 1 << 5;
- tmp_rx_cfg |= 1 << 4;
- tmp_rx_cfg |= 1 << 5;
+ tx_cfg |= UART_UTX_CONFIG_CR_PRT_EN;
+ tx_cfg |= UART_UTX_CONFIG_CR_PRT_SEL;
+ rx_cfg |= UART_URX_CONFIG_CR_PRT_EN;
+ rx_cfg |= UART_URX_CONFIG_CR_PRT_SEL;
break;
case UART_PARITY_EVEN:
- tmp_tx_cfg |= 1 << 4;
- tmp_tx_cfg &= ~(1 << 5);
- tmp_rx_cfg |= 1 << 4;
- tmp_rx_cfg &= ~(1 << 5);
+ tx_cfg |= UART_UTX_CONFIG_CR_PRT_EN;
+ tx_cfg &= ~UART_UTX_CONFIG_CR_PRT_SEL;
+ rx_cfg |= UART_URX_CONFIG_CR_PRT_EN;
+ rx_cfg &= ~UART_URX_CONFIG_CR_PRT_SEL;
break;
default:
break;
}
- if (config->data_bits == 5)
- {
- data_bits = UART_DATABITS_5;
- }
- else if (config->data_bits == 6)
- {
- data_bits = UART_DATABITS_6;
- }
- else if (config->data_bits == 7)
- {
- data_bits = UART_DATABITS_7;
- }
- else
- {
- data_bits = UART_DATABITS_8;
- }
+ /* Configure data and stop bits */
- if (config->stop_bits == 1)
- {
- stop_bits = UART_STOPBITS_2;
- }
- else
- {
- stop_bits = UART_STOPBITS_1;
- }
-
- /* Configure data bits */
-
- tmp_tx_cfg = bl602_data_setbits(tmp_tx_cfg, 8, 3, (data_bits + 4));
- tmp_rx_cfg = bl602_data_setbits(tmp_tx_cfg, 8, 3, (data_bits + 4));
+ rx_cfg &= ~UART_URX_CONFIG_CR_BIT_CNT_D_MASK;
+ rx_cfg |= ((uint32_t)config->data_bits - 1) << \
+ UART_URX_CONFIG_CR_BIT_CNT_D_SHIFT;
- /* Configure tx stop bits */
-
- tmp_tx_cfg = bl602_data_setbits(tmp_tx_cfg, 12, 2, (stop_bits + 1));
+ tx_cfg &= ~(UART_UTX_CONFIG_CR_BIT_CNT_D_MASK | \
+ UART_UTX_CONFIG_CR_BIT_CNT_P_MASK);
+ tx_cfg |= (((uint32_t)config->data_bits - 1) << \
+ UART_UTX_CONFIG_CR_BIT_CNT_D_SHIFT) | \
+ (((uint32_t)config->stop_bits + 1) << \
+ UART_UTX_CONFIG_CR_BIT_CNT_P_SHIFT);
/* Configure tx cts flow control function */
if (config->oflow_ctl)
{
- tmp_tx_cfg |= 1 << 1;
+ tx_cfg |= UART_UTX_CONFIG_CR_CTS_EN;
}
else
{
- tmp_tx_cfg &= ~(1 << 1);
+ tx_cfg &= ~(UART_UTX_CONFIG_CR_CTS_EN);
}
/* Disable rx input de-glitch function */
- tmp_rx_cfg &= ~(1 << 11);
+ rx_cfg &= ~(UART_URX_CONFIG_CR_DEG_EN);
+
+ /* Configure rx rts flow control function */
+
+ /* TODO: What about UART_URX_CONFIG_CR_RTS_SW_VAL? */
if (config->iflow_ctl)
{
- tmp_rx_cfg |= 1 << 1;
+ rx_cfg |= UART_URX_CONFIG_CR_RTS_SW_MODE;
}
else
{
- tmp_rx_cfg &= ~(1 << 1);
+ rx_cfg &= ~(UART_URX_CONFIG_CR_RTS_SW_MODE);
}
/* Write back */
- bl602_up_serialout(uartbase, UART_UTX_CONFIG_OFFSET, tmp_tx_cfg);
- bl602_up_serialout(uartbase, UART_URX_CONFIG_OFFSET, tmp_rx_cfg);
+ putreg32(rx_cfg, BL602_UART_URX_CONFIG(config->idx));
+ putreg32(tx_cfg, BL602_UART_UTX_CONFIG(config->idx));
/* Configure LSB-first */
- bl602_up_serialmodify(uartbase, UART_DATA_CONFIG_OFFSET, 1, 0);
+ modifyreg32(BL602_UART_DATA_CONFIG(config->idx),
+ UART_DATA_CONFIG_CR_UART_BIT_INV, 0);
/* Enable tx free run mode */
- bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 0, 1 << 2);
+ modifyreg32(BL602_UART_UTX_CONFIG(config->idx), 0,
+ UART_UTX_CONFIG_CR_FRM_EN);
- /* Deal with uart fifo configure register */
+ /* Configure FIFO thresholds */
- tmp_val = bl602_up_serialin(uartbase, UART_FIFO_CONFIG_1_OFFSET);
- tmp_val = bl602_data_setbits(tmp_val, UART_TX_FIFO_TH_POS, 5, 0x10 - 1);
- tmp_val = bl602_data_setbits(tmp_val, UART_RX_FIFO_TH_POS, 5, 0x10 - 1);
- bl602_up_serialout(uartbase, UART_FIFO_CONFIG_1_OFFSET, tmp_val);
+ modifyreg32(BL602_UART_FIFO_CONFIG_1(config->idx),
+ (UART_FIFO_CONFIG_1_RX_TH_MASK | \
+ UART_FIFO_CONFIG_1_TX_TH_MASK),
+ ((0x10 - 1) << UART_FIFO_CONFIG_1_RX_TH_SHIFT) | \
+ ((0x10 - 1) << UART_FIFO_CONFIG_1_TX_TH_SHIFT));
/* Enable UART tx rx unit */
- bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 0, 1);
- bl602_up_serialmodify(uartbase, UART_URX_CONFIG_OFFSET, 0, 1);
+ modifyreg32(BL602_UART_UTX_CONFIG(config->idx), 0,
+ UART_UTX_CONFIG_CR_EN);
+ modifyreg32(BL602_UART_URX_CONFIG(config->idx), 0,
+ UART_URX_CONFIG_CR_EN);
}
/****************************************************************************
@@ -414,13 +345,10 @@ void up_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE
/* Wait for FIFO */
- while (
- ((bl602_up_serialin(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1_OFFSET)) >>
- (UART_TX_FIFO_CNT_POS)) &
- (~((~0) << (6))))
- ;
+ while ((getreg32(BL602_UART_FIFO_CONFIG_1(BL602_CONSOLE_IDX)) & \
+ UART_FIFO_CONFIG_1_TX_CNT_MASK) == 0);
- bl602_up_serialout(BL602_CONSOLE_BASE, UART_FIFO_WDATA_OFFSET, ch);
+ putreg32(ch, BL602_UART_FIFO_WDATA(BL602_CONSOLE_IDX));
#endif /* HAVE_CONSOLE */
}
@@ -429,7 +357,7 @@ void bl602_lowsetup(void)
#ifdef HAVE_SERIAL_CONSOLE
/* Configure the console UART (if any) */
- bl602_uart_configure(BL602_CONSOLE_BASE, &g_bl602_console_config);
+ bl602_uart_configure(&g_bl602_console_config);
#endif /* HAVE_SERIAL_CONSOLE */
}
diff --git a/arch/risc-v/src/bl602/bl602_lowputc.h b/arch/risc-v/src/bl602/bl602_lowputc.h
index ef79460..ce96029 100644
--- a/arch/risc-v/src/bl602/bl602_lowputc.h
+++ b/arch/risc-v/src/bl602/bl602_lowputc.h
@@ -44,10 +44,6 @@ struct uart_config_s
uint8_t data_bits; /* Number of bits per word */
bool stop_bits; /* true=2 stop bits; false=1 stop bit */
uint8_t parity; /* Parity selection: 0=none, 1=odd, 2=even */
- uint8_t tx_pin; /* TX pin */
- uint8_t rx_pin; /* RX pin */
- uint8_t cts_pin; /* CTS pin */
- uint8_t rts_pin; /* RTS pin */
};
#undef EXTERN
@@ -59,20 +55,9 @@ extern "C"
#define EXTERN extern
#endif
-EXTERN uint32_t bl602_up_serialin(uint32_t reg_base, int offset);
-
-EXTERN void bl602_up_serialout(uint32_t reg_base, int offset,
- uint32_t value);
-
-EXTERN void bl602_up_serialmodify(uint32_t reg_base,
- int offset,
- uint32_t clearbits,
- uint32_t setbits);
-
EXTERN void bl602_lowsetup(void);
-EXTERN void bl602_uart_configure(uint32_t base_addr,
- const struct uart_config_s *config);
+EXTERN void bl602_uart_configure(const struct uart_config_s *config);
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
index d754cc1..34e500d 100644
--- a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
+++ b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
@@ -37,6 +37,7 @@
#include "riscv_internal.h"
#include <hardware/bl602_timer.h>
+#include "bl602_tim.h"
#include "bl602_oneshot_lowerhalf.h"
/****************************************************************************
@@ -72,7 +73,7 @@ struct bl602_oneshot_lowerhalf_s
oneshot_callback_t callback; /* Internal handler that receives callback */
FAR void * arg; /* Argument that is passed to the handler */
uint8_t tim; /* timer tim 0,1 */
- uint8_t irq; /* IRQ associated with this UART */
+ uint8_t irq; /* IRQ associated with this timer */
bool started; /* True: Timer has been started */
};
@@ -132,18 +133,27 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
/* Clear Interrupt Bits */
uint32_t int_id;
- uint32_t tmp_val;
- uint32_t tmp_addr;
+ uint32_t ticr_val;
+ uint32_t ticr_addr;
- int_id = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
- tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
- tmp_val = getreg32(tmp_addr);
+ if (priv->tim == 0)
+ {
+ int_id = getreg32(BL602_TIMER_TMSR2);
+ ticr_addr = BL602_TIMER_TICR2;
+ }
+ else
+ {
+ int_id = getreg32(BL602_TIMER_TMSR3);
+ ticr_addr = BL602_TIMER_TICR3;
+ }
+
+ ticr_val = getreg32(ticr_addr);
/* Comparator 0 match interrupt */
- if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0)
+ if ((int_id & TIMER_TMSR2_TMSR_0) != 0)
{
- putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr);
+ putreg32(ticr_val | TIMER_TICR2_TCLR_0, ticr_addr);
callback = priv->callback;
cbarg = priv->arg;
@@ -155,16 +165,16 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
/* Comparator 1 match interrupt */
- if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0)
+ if ((int_id & TIMER_TMSR2_TMSR_1) != 0)
{
- putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr);
+ putreg32(ticr_val | TIMER_TICR2_TCLR_1, ticr_addr);
}
/* Comparator 2 match interrupt */
- if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0)
+ if ((int_id & TIMER_TMSR2_TMSR_2) != 0)
{
- putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr);
+ putreg32(ticr_val | TIMER_TICR2_TCLR_2, ticr_addr);
}
return 0;
@@ -353,7 +363,7 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
uint16_t resolution)
{
FAR struct bl602_oneshot_lowerhalf_s *priv;
- timer_cfg_t timstr;
+ struct timer_cfg_s timstr;
/* Allocate an instance of the lower half driver */
@@ -372,7 +382,7 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
priv->lh.ops = &g_oneshot_ops;
priv->freq = TIMER_CLK_FREQ / resolution;
priv->tim = chan;
- if (priv->tim == 0)
+ if (priv->tim == TIMER_CH0)
{
priv->irq = BL602_IRQ_TIMER_CH0;
}
@@ -387,12 +397,12 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
timstr.clk_src = TIMER_CLKSRC_FCLK; /* Timer clock source */
timstr.pl_trig_src =
TIMER_PRELOAD_TRIG_COMP0; /* Timer count register preload trigger source
- * slelect */
+ * select */
timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */
timstr.clock_division =
- (TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */
+ (TIMER_CLK_DIV * resolution) - 1; /* Timer clock division value */
timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
diff --git a/arch/risc-v/src/bl602/bl602_serial.c b/arch/risc-v/src/bl602/bl602_serial.c
index 03a71c6..a41722f 100644
--- a/arch/risc-v/src/bl602/bl602_serial.c
+++ b/arch/risc-v/src/bl602/bl602_serial.c
@@ -36,11 +36,9 @@
#include <nuttx/irq.h>
#include <nuttx/serial/serial.h>
-#include <arch/board/board.h>
-
#include "bl602_lowputc.h"
+#include "bl602_gpio.h"
-#include "hardware/bl602_gpio.h"
#include "hardware/bl602_uart.h"
#include "hardware/bl602_glb.h"
@@ -77,6 +75,7 @@
#define HAVE_UART
#endif
#endif /* HAVE_CONSOLE */
+
/* If we are not using the serial driver for the console, then we still must
* provide some minimal implementation of up_putc.
*/
@@ -122,9 +121,8 @@
* Private Types
****************************************************************************/
-struct up_dev_s
+struct bl602_uart_s
{
- const uint32_t uartbase; /* Base address of UART registers */
uint8_t irq; /* IRQ associated with this UART */
struct uart_config_s config;
};
@@ -135,18 +133,18 @@ struct up_dev_s
/* Serial driver methods */
-static int up_setup(struct uart_dev_s *dev);
-static void up_shutdown(struct uart_dev_s *dev);
-static int up_attach(struct uart_dev_s *dev);
-static void up_detach(struct uart_dev_s *dev);
-static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
-static int up_receive(struct uart_dev_s *dev, unsigned int *status);
-static void up_rxint(struct uart_dev_s *dev, bool enable);
-static bool up_rxavailable(struct uart_dev_s *dev);
-static void up_send(struct uart_dev_s *dev, int ch);
-static void up_txint(struct uart_dev_s *dev, bool enable);
-static bool up_txready(struct uart_dev_s *dev);
-static bool up_txempty(struct uart_dev_s *dev);
+static int bl602_setup(struct uart_dev_s *dev);
+static void bl602_shutdown(struct uart_dev_s *dev);
+static int bl602_attach(struct uart_dev_s *dev);
+static void bl602_detach(struct uart_dev_s *dev);
+static int bl602_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int bl602_receive(struct uart_dev_s *dev, unsigned int *status);
+static void bl602_rxint(struct uart_dev_s *dev, bool enable);
+static bool bl602_rxavailable(struct uart_dev_s *dev);
+static void bl602_send(struct uart_dev_s *dev, int ch);
+static void bl602_txint(struct uart_dev_s *dev, bool enable);
+static bool bl602_txready(struct uart_dev_s *dev);
+static bool bl602_txempty(struct uart_dev_s *dev);
/****************************************************************************
* Private Data
@@ -154,21 +152,21 @@ static bool up_txempty(struct uart_dev_s *dev);
static const struct uart_ops_s g_uart_ops =
{
- .setup = up_setup,
- .shutdown = up_shutdown,
- .attach = up_attach,
- .detach = up_detach,
- .ioctl = up_ioctl,
- .receive = up_receive,
- .rxint = up_rxint,
- .rxavailable = up_rxavailable,
+ .setup = bl602_setup,
+ .shutdown = bl602_shutdown,
+ .attach = bl602_attach,
+ .detach = bl602_detach,
+ .ioctl = bl602_ioctl,
+ .receive = bl602_receive,
+ .rxint = bl602_rxint,
+ .rxavailable = bl602_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = NULL,
#endif
- .send = up_send,
- .txint = up_txint,
- .txready = up_txready,
- .txempty = up_txempty,
+ .send = bl602_send,
+ .txint = bl602_txint,
+ .txready = bl602_txready,
+ .txempty = bl602_txempty,
};
/* I/O buffers */
@@ -177,11 +175,9 @@ static const struct uart_ops_s g_uart_ops =
static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
-static struct up_dev_s g_uart0priv =
+static struct bl602_uart_s g_uart0priv =
{
- .uartbase = UART0_BASE,
.irq = BL602_IRQ_UART0,
-
.config =
{
.idx = 0,
@@ -189,10 +185,6 @@ static struct up_dev_s g_uart0priv =
.parity = CONFIG_UART0_PARITY,
.data_bits = CONFIG_UART0_BITS,
.stop_bits = CONFIG_UART0_2STOP,
- .tx_pin = CONFIG_BL602_UART0_TX_PIN,
- .rx_pin = CONFIG_BL602_UART0_RX_PIN,
- .rts_pin = CONFIG_BL602_UART0_RTS_PIN,
- .cts_pin = CONFIG_BL602_UART0_CTS_PIN,
#ifdef CONFIG_UART0_IFLOWCONTROL
.iflow_ctl = CONFIG_UART0_IFLOWCONTROL,
@@ -232,11 +224,9 @@ static uart_dev_t g_uart0port =
static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
-static struct up_dev_s g_uart1priv =
+static struct bl602_uart_s g_uart1priv =
{
- .uartbase = UART1_BASE,
.irq = BL602_IRQ_UART1,
-
.config =
{
.idx = 1,
@@ -244,10 +234,6 @@ static struct up_dev_s g_uart1priv =
.parity = CONFIG_UART1_PARITY,
.data_bits = CONFIG_UART1_BITS,
.stop_bits = CONFIG_UART1_2STOP,
- .tx_pin = CONFIG_BL602_UART1_TX_PIN,
- .rx_pin = CONFIG_BL602_UART1_RX_PIN,
- .rts_pin = CONFIG_BL602_UART1_RTS_PIN,
- .cts_pin = CONFIG_BL602_UART1_CTS_PIN,
#ifdef CONFIG_UART1_IFLOWCONTROL
.iflow_ctl = CONFIG_UART1_IFLOWCONTROL,
@@ -307,20 +293,22 @@ static struct uart_dev_s *const g_uart_devs[] =
static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
{
- uart_dev_t * dev = (uart_dev_t *)arg;
- struct up_dev_s *uart_priv = dev->priv;
- uint32_t tmp_val = 0;
- uint32_t mask_val = 0;
+ uart_dev_t *dev = (uart_dev_t *)arg;
+ struct bl602_uart_s *priv = dev->priv;
+ uint8_t uart_idx = priv->config.idx;
+ uint32_t int_status;
+ uint32_t int_mask;
- tmp_val = bl602_up_serialin(uart_priv->uartbase, UART_INT_STS_OFFSET);
- mask_val = bl602_up_serialin(uart_priv->uartbase, UART_INT_MASK_OFFSET);
+ int_status = getreg32(BL602_UART_INT_STS(uart_idx));
+ int_mask = getreg32(BL602_UART_INT_MASK(uart_idx));
/* Length of uart rx data transfer arrived interrupt */
- if ((tmp_val & (1 << UART_URX_END_INT_POS)) &&
- !(mask_val & (1 << UART_CR_URX_END_MASK_POS)))
+ if ((int_status & UART_INT_STS_URX_END_INT) &&
+ !(int_mask & UART_INT_MASK_CR_URX_END_MASK))
{
- bl602_up_serialout(uart_priv->uartbase, UART_INT_CLEAR_OFFSET, 0x2);
+ putreg32(UART_INT_CLEAR_CR_URX_END_CLR,
+ BL602_UART_INT_CLEAR(uart_idx));
/* Receive Data ready */
@@ -329,8 +317,8 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
/* Tx fifo ready interrupt,auto-cleared when data is pushed */
- if ((tmp_val & (1 << UART_UTX_FIFO_INT_POS)) &&
- !(mask_val & (1 << UART_CR_UTX_FIFO_MASK_POS)))
+ if ((int_status & UART_INT_STS_UTX_FIFO_INT) &&
+ !(int_mask & UART_INT_MASK_CR_UTX_FIFO_MASK))
{
/* Transmit data request interrupt */
@@ -339,8 +327,8 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
/* Rx fifo ready interrupt,auto-cleared when data is popped */
- if ((tmp_val & (1 << UART_URX_FIFO_INT_POS)) &&
- !(mask_val & (1 << UART_CR_URX_FIFO_MASK_POS)))
+ if ((int_status & UART_INT_STS_URX_FIFO_INT) &&
+ !(int_mask & UART_INT_MASK_CR_URX_FIFO_MASK))
{
/* Receive Data ready */
@@ -351,7 +339,7 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
}
/****************************************************************************
- * Name: up_setup
+ * Name: bl602_setup
*
* Description:
* Configure the UART baud, bits, parity, etc. This method is called the
@@ -359,16 +347,16 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
*
****************************************************************************/
-static int up_setup(struct uart_dev_s *dev)
+static int bl602_setup(struct uart_dev_s *dev)
{
- struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
- bl602_uart_configure(uart_priv->uartbase, &uart_priv->config);
+ bl602_uart_configure(&priv->config);
return OK;
}
/****************************************************************************
- * Name: up_shutdown
+ * Name: bl602_shutdown
*
* Description:
* Disable the UART. This method is called when the serial
@@ -376,18 +364,19 @@ static int up_setup(struct uart_dev_s *dev)
*
****************************************************************************/
-static void up_shutdown(struct uart_dev_s *dev)
+static void bl602_shutdown(struct uart_dev_s *dev)
{
- struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
+ uint8_t uart_idx = priv->config.idx;
/* Disable uart before config */
- bl602_up_serialmodify(uart_priv->uartbase, UART_UTX_CONFIG_OFFSET, 1, 0);
- bl602_up_serialmodify(uart_priv->uartbase, UART_URX_CONFIG_OFFSET, 1, 0);
+ modifyreg32(BL602_UART_UTX_CONFIG(uart_idx), UART_UTX_CONFIG_CR_EN, 0);
+ modifyreg32(BL602_UART_URX_CONFIG(uart_idx), UART_URX_CONFIG_CR_EN, 0);
}
/****************************************************************************
- * Name: up_attach
+ * Name: bl602_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method
@@ -401,10 +390,10 @@ static void up_shutdown(struct uart_dev_s *dev)
*
****************************************************************************/
-static int up_attach(struct uart_dev_s *dev)
+static int bl602_attach(struct uart_dev_s *dev)
{
int ret;
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
ret = irq_attach(priv->irq, __uart_interrupt, (void *)dev);
if (ret == OK)
@@ -416,7 +405,7 @@ static int up_attach(struct uart_dev_s *dev)
}
/****************************************************************************
- * Name: up_detach
+ * Name: bl602_detach
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
@@ -425,9 +414,9 @@ static int up_attach(struct uart_dev_s *dev)
*
****************************************************************************/
-static void up_detach(struct uart_dev_s *dev)
+static void bl602_detach(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
/* Disable interrupts */
@@ -439,24 +428,14 @@ static void up_detach(struct uart_dev_s *dev)
}
/****************************************************************************
- * Name: bl602_data_getbits
- ****************************************************************************/
-
-static uint32_t
-bl602_data_getbits(uint32_t data, uint32_t start, uint32_t len)
-{
- return (((data) >> (start)) & (~((~0) << (len))));
-}
-
-/****************************************************************************
- * Name: up_ioctl
+ * Name: bl602_ioctl
*
* Description:
* All ioctl calls will be routed through this method
*
****************************************************************************/
-static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+static int bl602_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
struct inode * inode = filep->f_inode;
@@ -471,7 +450,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
do
{
struct termios * termiosp = (struct termios *)arg;
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
if (!termiosp)
{
@@ -527,7 +506,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
do
{
struct termios * termiosp = (struct termios *)arg;
- struct up_dev_s * priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s * priv = (struct bl602_uart_s *)dev->priv;
struct uart_config_s config;
uint32_t tmp_val;
@@ -615,11 +594,9 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
* implement TCSADRAIN / TCSAFLUSH
*/
- tmp_val =
- bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
- bl602_uart_configure(priv->uartbase, &config);
- bl602_up_serialout(
- priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
+ tmp_val = getreg32(BL602_UART_INT_MASK(config->idx));
+ bl602_uart_configure(&config);
+ putreg32(tmp_val, BL602_UART_INT_MASK(config->idx));
}
}
while (0);
@@ -635,7 +612,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
}
/****************************************************************************
- * Name: up_receive
+ * Name: bl602_receive
*
* Description:
* Called (usually) from the interrupt level to receive one
@@ -644,10 +621,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
*
****************************************************************************/
-static int up_receive(struct uart_dev_s *dev, unsigned int *status)
+static int bl602_receive(struct uart_dev_s *dev, unsigned int *status)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
- int rxdata;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
+ uint8_t uart_idx = priv->config.idx;
+ int rxdata;
/* Return status information */
@@ -658,12 +636,11 @@ static int up_receive(struct uart_dev_s *dev, unsigned int *status)
/* if uart fifo cnts > 0 */
- if (bl602_data_getbits(
- bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
- UART_RX_FIFO_CNT_POS,
- 6) > 0)
+ if (getreg32(BL602_UART_FIFO_CONFIG_1(uart_idx)) & \
+ UART_FIFO_CONFIG_1_RX_CNT_MASK)
{
- rxdata = bl602_up_serialin(priv->uartbase, UART_FIFO_RDATA_OFFSET);
+ rxdata = getreg32(BL602_UART_FIFO_RDATA(uart_idx)) & \
+ UART_FIFO_RDATA_MASK;
}
else
{
@@ -673,97 +650,94 @@ static int up_receive(struct uart_dev_s *dev, unsigned int *status)
}
/****************************************************************************
- * Name: up_rxint
+ * Name: bl602_rxint
*
* Description:
* Call to enable or disable RX interrupts
*
****************************************************************************/
-static void up_rxint(struct uart_dev_s *dev, bool enable)
+static void bl602_rxint(struct uart_dev_s *dev, bool enable)
{
- uint32_t tmp_val;
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ uint32_t int_mask;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
+ uint8_t uart_idx = priv->config.idx;
irqstate_t flags = enter_critical_section();
if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
- tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
- tmp_val &= ~(1 << UART_INT_RX_FIFO_REQ);
- tmp_val &= ~(1 << UART_INT_RX_END);
- bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
+ int_mask = getreg32(BL602_UART_INT_MASK(uart_idx));
+ int_mask &= ~(UART_INT_MASK_CR_URX_FIFO_MASK);
+ int_mask &= ~(UART_INT_MASK_CR_URX_END_MASK);
+ putreg32(int_mask, BL602_UART_INT_MASK(uart_idx));
#endif
}
else
{
- tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
- tmp_val |= (1 << UART_INT_RX_FIFO_REQ);
- tmp_val |= (1 << UART_INT_RX_END);
- bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
+ int_mask = getreg32(BL602_UART_INT_MASK(uart_idx));
+ int_mask |= UART_INT_MASK_CR_URX_FIFO_MASK;
+ int_mask |= UART_INT_MASK_CR_URX_END_MASK;
+ putreg32(int_mask, BL602_UART_INT_MASK(uart_idx));
}
leave_critical_section(flags);
}
/****************************************************************************
- * Name: up_rxavailable
+ * Name: bl602_rxavailable
*
* Description:
* Return true if the receive register is not empty
*
****************************************************************************/
-static bool up_rxavailable(struct uart_dev_s *dev)
+static bool bl602_rxavailable(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
+ uint8_t uart_idx = priv->config.idx;
/* Return true is data is available in the receive data buffer */
- uint32_t rxcnt = bl602_data_getbits(
- bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
- UART_RX_FIFO_CNT_POS,
- 6);
-
- return rxcnt != 0;
+ return (getreg32(BL602_UART_FIFO_CONFIG_1(uart_idx)) & \
+ UART_FIFO_CONFIG_1_RX_CNT_MASK) != 0;
}
/****************************************************************************
- * Name: up_send
+ * Name: bl602_send
*
* Description:
* This method will send one byte on the UART.
*
****************************************************************************/
-static void up_send(struct uart_dev_s *dev, int ch)
+static void bl602_send(struct uart_dev_s *dev, int ch)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
+ uint8_t uart_idx = priv->config.idx;
- /* Wait for FIFO */
+ /* Wait for FIFO to be empty */
- while (bl602_data_getbits(
- bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
- UART_TX_FIFO_CNT_POS,
- 6) == 0)
- ;
+ while ((getreg32(BL602_UART_FIFO_CONFIG_1(uart_idx)) & \
+ UART_FIFO_CONFIG_1_TX_CNT_MASK) == 0);
- bl602_up_serialout(priv->uartbase, UART_FIFO_WDATA_OFFSET, ch);
+ putreg32(ch, BL602_UART_FIFO_WDATA(uart_idx));
}
/****************************************************************************
- * Name: up_txint
+ * Name: bl602_txint
*
* Description:
* Call to enable or disable TX interrupts
*
****************************************************************************/
-static void up_txint(struct uart_dev_s *dev, bool enable)
+static void bl602_txint(struct uart_dev_s *dev, bool enable)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
+ uint8_t uart_idx = priv->config.idx;
irqstate_t flags;
- uint32_t tmp_val;
+ uint32_t int_mask;
flags = enter_critical_section();
@@ -772,9 +746,9 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
/* Enable the TX interrupt */
- tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
- tmp_val &= ~(1 << UART_INT_TX_FIFO_REQ);
- bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
+ int_mask = getreg32(BL602_UART_INT_MASK(uart_idx));
+ int_mask &= ~(UART_INT_MASK_CR_UTX_FIFO_MASK);
+ putreg32(int_mask, BL602_UART_INT_MASK(uart_idx));
/* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse).
@@ -787,55 +761,48 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
{
/* Disable the TX interrupt */
- tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
- tmp_val |= (1 << UART_INT_TX_FIFO_REQ);
- bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
+ int_mask = getreg32(BL602_UART_INT_MASK(uart_idx));
+ int_mask |= UART_INT_MASK_CR_UTX_FIFO_MASK;
+ putreg32(int_mask, BL602_UART_INT_MASK(uart_idx));
}
leave_critical_section(flags);
}
/****************************************************************************
- * Name: up_txready
+ * Name: bl602_txready
*
* Description:
- * Return true if the tranmsit data register is not full
+ * Return true if the transmit data register is not full
*
****************************************************************************/
-static bool up_txready(struct uart_dev_s *dev)
+static bool bl602_txready(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
+ uint8_t uart_idx = priv->config.idx;
/* Return TRUE if the TX FIFO is not full */
- uint32_t txcnt =
- bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET);
- txcnt = (txcnt & UART_TX_FIFO_CNT_MSK) >> UART_TX_FIFO_CNT_POS;
-
- return (txcnt != 0);
+ return (getreg32(BL602_UART_FIFO_CONFIG_1(uart_idx)) & \
+ UART_FIFO_CONFIG_1_TX_CNT_MASK) != 0;
}
/****************************************************************************
- * Name: up_txempty
+ * Name: bl602_txempty
*
* Description:
- * Return true if the tranmsit data register is empty
+ * Return true if the transmit data register is empty
*
****************************************************************************/
-static bool up_txempty(struct uart_dev_s *dev)
+static bool bl602_txempty(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-
- /* Return TRUE if the TX is pending */
-
- uint32_t txcnt = bl602_data_getbits(
- bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
- UART_TX_FIFO_CNT_POS,
- 6);
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)dev->priv;
+ uint8_t uart_idx = priv->config.idx;
- return (txcnt == 0);
+ return (getreg32(BL602_UART_FIFO_CONFIG_1(uart_idx)) & \
+ UART_FIFO_CONFIG_1_TX_CNT_MASK) == 0;
}
/****************************************************************************
@@ -851,8 +818,8 @@ static bool up_txempty(struct uart_dev_s *dev)
* Performs the low level UART initialization early in debug so that the
* serial console will be available during bootup. This must be called
* before up_serialinit. NOTE: This function depends on GPIO pin
- * configuration performed in up_consoleinit() and main clock iniialization
- * performed in up_clkinitialize().
+ * configuration performed in up_consoleinit() and main clock
+ * initialization performed in up_clkinitialize().
*
****************************************************************************/
@@ -862,7 +829,7 @@ void up_earlyserialinit(void)
/* Configuration whichever one is the console */
CONSOLE_DEV.isconsole = true;
- up_setup(&CONSOLE_DEV);
+ bl602_setup(&CONSOLE_DEV);
#endif
}
#endif
@@ -922,7 +889,7 @@ void up_serialinit(void)
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
- struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
+ struct bl602_uart_s *priv = (struct bl602_uart_s *)CONSOLE_DEV.priv;
(void)priv;
irqstate_t flags = enter_critical_section();
diff --git a/arch/risc-v/src/bl602/bl602_start.c b/arch/risc-v/src/bl602/bl602_start.c
index cf9f85c..36df476 100644
--- a/arch/risc-v/src/bl602/bl602_start.c
+++ b/arch/risc-v/src/bl602/bl602_start.c
@@ -64,15 +64,15 @@
static uint8_t g_idle_stack[BL602_IDLESTACK_SIZE];
-/* Dont change the name of varaible, since we refer this
+/* Dont change the name of variable, since we refer this
* boot2_partition_table in linker script
*/
static struct
{
- uint8_t partition_active_idx;
- uint8_t pad[3];
- struct pt_table_stuff_config_s table;
+ uint8_t partition_active_idx;
+ uint8_t pad[3];
+ struct pt_stuff_config_s table;
} boot2_partition_table;
/****************************************************************************
@@ -98,8 +98,8 @@ uint32_t boot2_get_flash_addr(void)
extern uint8_t __boot2_flash_cfg_src;
return (uint32_t)(&__boot2_flash_cfg_src +
- (sizeof(boot2_partition_table.table.pt_entries[0]) *
- boot2_partition_table.table.pt_table.entry_cnt));
+ (sizeof(boot2_partition_table.table.entries[0]) *
+ boot2_partition_table.table.table.entry_cnt));
}
/****************************************************************************
@@ -108,8 +108,6 @@ uint32_t boot2_get_flash_addr(void)
void bfl_main(void)
{
- uint32_t tmp_val;
-
/* set interrupt vector */
asm volatile("csrw mtvec, %0" ::"r"((uintptr_t)exception_common + 2));
@@ -120,10 +118,7 @@ void bfl_main(void)
/* HBN Config AON pad input and SMT */
- tmp_val = getreg32(HBN_BASE + HBN_IRQ_MODE_OFFSET);
- tmp_val = (tmp_val & HBN_REG_AON_PAD_IE_SMT_UMSK) |
- (1 << HBN_REG_AON_PAD_IE_SMT_POS);
- putreg32(tmp_val, HBN_BASE + HBN_IRQ_MODE_OFFSET);
+ modifyreg32(BL602_HBN_IRQ_MODE, 0, HBN_IRQ_MODE_REG_AON_PAD_IE_SMT);
#ifdef USE_EARLYSERIALINIT
up_earlyserialinit();
diff --git a/arch/risc-v/src/bl602/bl602_tim.c b/arch/risc-v/src/bl602/bl602_tim.c
index de8ff97..b0500c1 100644
--- a/arch/risc-v/src/bl602/bl602_tim.c
+++ b/arch/risc-v/src/bl602/bl602_tim.c
@@ -22,55 +22,24 @@
* Included Files
****************************************************************************/
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
#include <hardware/bl602_timer.h>
+#include "bl602_tim.h"
#include "riscv_arch.h"
#include "riscv_internal.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define TIMER_MAX_MATCH 3
-
-/****************************************************************************
- * Static Functions
- ****************************************************************************/
-
-static inline uint32_t bl602_up_tim_regin(uint32_t reg_addr)
-{
- return getreg32(reg_addr);
-}
-
-static inline void bl602_up_tim_regout(uint32_t reg_addr, uint32_t value)
-{
- putreg32(value, reg_addr);
-}
-
-/****************************************************************************
* Name: bl602_data_setbits
****************************************************************************/
-static uint32_t bl602_data_setbits(uint32_t data,
- uint32_t start,
- uint32_t len,
- uint32_t value)
-{
- return (((data) & ~((~((~0) << (len))) << (start))) |
- (((value) & ((~((~0) << (len))))) << (start)));
-}
-
static void bl602_wdt_access(void)
{
- uint32_t tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WFAR_OFFSET);
-
- bl602_up_tim_regout(
- TIMER_BASE + TIMER_WFAR_OFFSET,
- bl602_data_setbits(tmp_val, TIMER_WFAR_POS, 16, 0xbaba));
-
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSAR_OFFSET);
- bl602_up_tim_regout(
- TIMER_BASE + TIMER_WSAR_OFFSET,
- bl602_data_setbits(tmp_val, TIMER_WSAR_POS, 16, 0xeb10));
+ modifyreg32(BL602_TIMER_WFAR, TIMER_WFAR_MASK, 0xbaba);
+ modifyreg32(BL602_TIMER_WFAR, TIMER_WSAR_MASK, 0xeb10);
}
/****************************************************************************
@@ -92,13 +61,10 @@ static void bl602_wdt_access(void)
*
****************************************************************************/
-uint32_t bl602_timer_getcompvalue(uint32_t timer_ch, uint32_t cmp_no)
+uint32_t bl602_timer_getcompvalue(uint8_t timer_ch, uint8_t cmp_no)
{
- uint32_t tmp_val;
-
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TMR2_0_OFFSET +
- 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no));
- return tmp_val;
+ return getreg32(BL602_TIMER_TMR2_0 + \
+ 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no));
}
/****************************************************************************
@@ -117,13 +83,12 @@ uint32_t bl602_timer_getcompvalue(uint32_t timer_ch, uint32_t cmp_no)
*
****************************************************************************/
-void bl602_timer_setcompvalue(uint32_t timer_ch,
- uint32_t cmp_no,
+void bl602_timer_setcompvalue(uint8_t timer_ch,
+ uint8_t cmp_no,
uint32_t val)
{
- bl602_up_tim_regout(TIMER_BASE + TIMER_TMR2_0_OFFSET +
- 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no),
- val);
+ putreg32(val,
+ BL602_TIMER_TMR2_0 + 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no));
}
/****************************************************************************
@@ -142,23 +107,23 @@ void bl602_timer_setcompvalue(uint32_t timer_ch,
uint32_t bl602_timer_getcountervalue(uint32_t timer_ch)
{
- uint32_t tmp_val;
- uint32_t tmp_addr;
+ uint32_t count;
+ uint32_t tcvwr_addr;
/* TO avoid risk of reading, don't read TCVWR directly
- * request for read
+ * request for read. Why? This register is read-only.
*/
- tmp_addr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timer_ch;
- bl602_up_tim_regout(tmp_addr, 1);
+ tcvwr_addr = BL602_TIMER_TCVWR2 + 4 * timer_ch;
+ putreg32(1, tcvwr_addr);
/* Need wait */
- tmp_val = bl602_up_tim_regin(tmp_addr);
- tmp_val = bl602_up_tim_regin(tmp_addr);
- tmp_val = bl602_up_tim_regin(tmp_addr);
+ count = getreg32(tcvwr_addr);
+ count = getreg32(tcvwr_addr);
+ count = getreg32(tcvwr_addr);
- return tmp_val;
+ return count;
}
/****************************************************************************
@@ -172,33 +137,27 @@ uint32_t bl602_timer_getcountervalue(uint32_t timer_ch)
* cmp_no - TIMER comparator ID type.
*
* Returned Value:
- * 0 or 1
+ * match status
*
****************************************************************************/
-uint32_t bl602_timer_getmatchstatus(uint32_t timer_ch, uint32_t cmp_no)
+bool bl602_timer_getmatchstatus(uint32_t timer_ch, uint8_t cmp_no)
{
- uint32_t tmp_val;
- uint32_t bit_status = 0;
+ uint32_t status = getreg32(BL602_TIMER_TMSR2 + 4 * timer_ch);
- tmp_val =
- bl602_up_tim_regin(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timer_ch);
switch (cmp_no)
{
case TIMER_COMP_ID_0:
- bit_status = (((tmp_val) & (1 << (TIMER_TMSR_0_POS))) ? 1 : 0);
- break;
+ return ((status & TIMER_TMSR2_TMSR_0) != 0);
case TIMER_COMP_ID_1:
- bit_status = (((tmp_val) & (1 << (TIMER_TMSR_1_POS))) ? 1 : 0);
- break;
+ return ((status & TIMER_TMSR2_TMSR_1) != 0);
case TIMER_COMP_ID_2:
- bit_status = (((tmp_val) & (1 << (TIMER_TMSR_2_POS))) ? 1 : 0);
- break;
+ return ((status & TIMER_TMSR2_TMSR_2) != 0);
default:
break;
}
- return bit_status;
+ return false;
}
/****************************************************************************
@@ -217,11 +176,7 @@ uint32_t bl602_timer_getmatchstatus(uint32_t timer_ch, uint32_t cmp_no)
uint32_t bl602_timer_getpreloadvalue(uint32_t timer_ch)
{
- uint32_t tmp_val;
- tmp_val =
- bl602_up_tim_regin(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch);
-
- return tmp_val;
+ return getreg32(BL602_TIMER_TPLVR2 + 4 * timer_ch);
}
/****************************************************************************
@@ -239,9 +194,9 @@ uint32_t bl602_timer_getpreloadvalue(uint32_t timer_ch)
*
****************************************************************************/
-void bl602_timer_setpreloadvalue(uint32_t timer_ch, uint32_t val)
+void bl602_timer_setpreloadvalue(uint8_t timer_ch, uint32_t val)
{
- bl602_up_tim_regout(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch, val);
+ putreg32(val, BL602_TIMER_TPLVR2 + 4 * timer_ch);
}
/****************************************************************************
@@ -259,10 +214,9 @@ void bl602_timer_setpreloadvalue(uint32_t timer_ch, uint32_t val)
*
****************************************************************************/
-void bl602_timer_setpreloadtrigsrc(uint32_t timer_ch, uint32_t pl_src)
+void bl602_timer_setpreloadtrigsrc(uint8_t timer_ch, uint32_t pl_src)
{
- bl602_up_tim_regout(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_ch,
- pl_src);
+ putreg32(pl_src, BL602_TIMER_TPLCR2 + 4 * timer_ch);
}
/****************************************************************************
@@ -272,24 +226,20 @@ void bl602_timer_setpreloadtrigsrc(uint32_t timer_ch, uint32_t pl_src)
* TIMER set count mode:preload or free run
*
* Input Parameters:
- * timer_ch - TIMER channel type.
+ * timer_ch - TIMER channel type.
* count_mode - TIMER count mode: TIMER_COUNT_PRELOAD or
- *TIMER_COUNT_FREERUN.
+ * TIMER_COUNT_FREERUN.
*
* Returned Value:
* None.
*
****************************************************************************/
-void bl602_timer_setcountmode(uint32_t timer_ch, uint32_t count_mode)
+void bl602_timer_setcountmode(uint32_t timer_ch, uint8_t count_mode)
{
- uint32_t tmpval;
-
- tmpval = bl602_up_tim_regin(TIMER_BASE + TIMER_TCMR_OFFSET);
- tmpval &= (~(1 << (timer_ch + 1)));
- tmpval |= (count_mode << (timer_ch + 1));
-
- bl602_up_tim_regout(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval);
+ modifyreg32(BL602_TIMER_TCMR,
+ TIMER_TCMR_TIMER2_MODE << timer_ch,
+ count_mode ? TIMER_TCMR_TIMER2_MODE << timer_ch : 0);
}
/****************************************************************************
@@ -307,17 +257,9 @@ void bl602_timer_setcountmode(uint32_t timer_ch, uint32_t count_mode)
*
****************************************************************************/
-void bl602_timer_clearintstatus(uint32_t timer_ch, uint32_t cmp_no)
+void bl602_timer_clearintstatus(uint8_t timer_ch, uint32_t cmp_no)
{
- uint32_t tmp_addr;
- uint32_t tmp_val;
-
- tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timer_ch;
-
- tmp_val = bl602_up_tim_regin(tmp_addr);
- tmp_val |= (1 << cmp_no);
-
- bl602_up_tim_regout(tmp_addr, tmp_val);
+ putreg32(BL602_TIMER_TICR2 + 4 * timer_ch, 1 << cmp_no);
}
/****************************************************************************
@@ -334,43 +276,36 @@ void bl602_timer_clearintstatus(uint32_t timer_ch, uint32_t cmp_no)
*
****************************************************************************/
-void bl602_timer_init(timer_cfg_t *timer_cfg)
+void bl602_timer_init(struct timer_cfg_s *timer_cfg)
{
- uint32_t timer_ch = timer_cfg->timer_ch;
- uint32_t tmp_val;
+ uint8_t timer_ch = timer_cfg->timer_ch;
/* Configure timer clock source */
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCCR_OFFSET);
if (timer_ch == TIMER_CH0)
{
- tmp_val =
- bl602_data_setbits(tmp_val, TIMER_CS_1_POS, 2, timer_cfg->clk_src);
+ modifyreg32(BL602_TIMER_TCCR, TIMER_TCCR_CS_1_MASK,
+ timer_cfg->clk_src << TIMER_TCCR_CS_1_SHIFT);
}
else
{
- tmp_val =
- bl602_data_setbits(tmp_val, TIMER_CS_2_POS, 2, timer_cfg->clk_src);
+ modifyreg32(BL602_TIMER_TCCR, TIMER_TCCR_CS_2_MASK,
+ timer_cfg->clk_src << TIMER_TCCR_CS_2_SHIFT);
}
- bl602_up_tim_regout(TIMER_BASE + TIMER_TCCR_OFFSET, tmp_val);
-
/* Configure timer clock division */
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCDR_OFFSET);
if (timer_ch == TIMER_CH0)
{
- tmp_val = bl602_data_setbits(
- tmp_val, TIMER_TCDR2_POS, 8, timer_cfg->clock_division);
+ modifyreg32(BL602_TIMER_TCDR, TIMER_TCDR_TCDR2_MASK,
+ timer_cfg->clock_division << TIMER_TCDR_TCDR2_SHIFT);
}
else
{
- tmp_val = bl602_data_setbits(
- tmp_val, TIMER_TCDR3_POS, 8, timer_cfg->clock_division);
+ modifyreg32(BL602_TIMER_TCDR, TIMER_TCDR_TCDR3_MASK,
+ timer_cfg->clock_division << TIMER_TCDR_TCDR3_SHIFT);
}
- bl602_up_tim_regout(TIMER_BASE + TIMER_TCDR_OFFSET, tmp_val);
-
/* Configure timer count mode: preload or free run */
bl602_timer_setcountmode(timer_ch, timer_cfg->count_mode);
@@ -388,9 +323,9 @@ void bl602_timer_init(timer_cfg_t *timer_cfg)
/* Configure match compare values */
- bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_0, timer_cfg->match_val0);
- bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_1, timer_cfg->match_val1);
- bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_2, timer_cfg->match_val2);
+ bl602_timer_setcompvalue(timer_ch, 0, timer_cfg->match_val0);
+ bl602_timer_setcompvalue(timer_ch, 1, timer_cfg->match_val1);
+ bl602_timer_setcompvalue(timer_ch, 2, timer_cfg->match_val2);
}
/****************************************************************************
@@ -407,14 +342,9 @@ void bl602_timer_init(timer_cfg_t *timer_cfg)
*
****************************************************************************/
-void bl602_timer_enable(uint32_t timer_ch)
+void bl602_timer_enable(uint8_t timer_ch)
{
- uint32_t tmp_val;
-
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCER_OFFSET);
- tmp_val |= (1 << (timer_ch + 1));
-
- bl602_up_tim_regout(TIMER_BASE + TIMER_TCER_OFFSET, tmp_val);
+ modifyreg32(BL602_TIMER_TCER, 0, (TIMER_TCER_TIMER2_EN << timer_ch));
}
/****************************************************************************
@@ -431,14 +361,9 @@ void bl602_timer_enable(uint32_t timer_ch)
*
****************************************************************************/
-void bl602_timer_disable(uint32_t timer_ch)
+void bl602_timer_disable(uint8_t timer_ch)
{
- uint32_t tmp_val;
-
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCER_OFFSET);
- tmp_val &= (~(1 << (timer_ch + 1)));
-
- bl602_up_tim_regout(TIMER_BASE + TIMER_TCER_OFFSET, tmp_val);
+ modifyreg32(BL602_TIMER_TCER, (TIMER_TCER_TIMER2_EN << timer_ch), 0);
}
/****************************************************************************
@@ -451,22 +376,17 @@ void bl602_timer_disable(uint32_t timer_ch)
* timer_ch - TIMER channel type.
* int_type - TIMER interrupt type.
* int_mask - TIMER interrupt mask value:1:disbale interrupt.0:enable
- *interrupt.
+ * interrupt.
*
* Returned Value:
* None.
*
****************************************************************************/
-void bl602_timer_intmask(uint32_t timer_ch,
- uint32_t int_type,
- uint32_t int_mask)
+void bl602_timer_intmask(uint8_t timer_ch, uint8_t int_type,
+ uint8_t int_mask)
{
- uint32_t tmp_addr;
- uint32_t tmp_val;
-
- tmp_addr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timer_ch;
- tmp_val = bl602_up_tim_regin(tmp_addr);
+ uint32_t tier_addr = BL602_TIMER_TIER2 + 4 * timer_ch;
switch (int_type)
{
@@ -475,13 +395,13 @@ void bl602_timer_intmask(uint32_t timer_ch,
{
/* Enable this interrupt */
- bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_0_POS);
+ modifyreg32(tier_addr, 0, TIMER_TIER2_TIER_0);
}
else
{
/* Disable this interrupt */
- bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_0_POS));
+ modifyreg32(tier_addr, TIMER_TIER2_TIER_0, 0);
}
break;
@@ -491,13 +411,13 @@ void bl602_timer_intmask(uint32_t timer_ch,
{
/* Enable this interrupt */
- bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_1_POS);
+ modifyreg32(tier_addr, 0, TIMER_TIER2_TIER_1);
}
else
{
/* Disable this interrupt */
- bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_1_POS));
+ modifyreg32(tier_addr, TIMER_TIER2_TIER_1, 0);
}
break;
@@ -507,13 +427,13 @@ void bl602_timer_intmask(uint32_t timer_ch,
{
/* Enable this interrupt */
- bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_2_POS);
+ modifyreg32(tier_addr, 0, TIMER_TIER2_TIER_2);
}
else
{
/* Disable this interrupt */
- bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_2_POS));
+ modifyreg32(tier_addr, TIMER_TIER2_TIER_2, 0);
}
break;
@@ -523,17 +443,15 @@ void bl602_timer_intmask(uint32_t timer_ch,
{
/* Enable this interrupt */
- bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_0_POS);
- bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_1_POS);
- bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_2_POS);
+ modifyreg32(tier_addr, 0,
+ TIMER_TIER2_TIER_0 | TIMER_TIER2_TIER_1 | TIMER_TIER2_TIER_2);
}
else
{
/* Disable this interrupt */
- bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_0_POS));
- bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_1_POS));
- bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_2_POS));
+ modifyreg32(tier_addr,
+ TIMER_TIER2_TIER_0 | TIMER_TIER2_TIER_1 | TIMER_TIER2_TIER_2, 0);
}
break;
@@ -558,21 +476,17 @@ void bl602_timer_intmask(uint32_t timer_ch,
*
****************************************************************************/
-void bl602_wdt_set_clock(uint32_t clk_src, uint8_t div)
+void bl602_wdt_set_clock(uint8_t clk_src, uint8_t div)
{
- uint32_t tmp_val;
-
/* Configure watchdog timer clock source */
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCCR_OFFSET);
- tmp_val = bl602_data_setbits(tmp_val, TIMER_CS_WDT_POS, 2, clk_src);
- bl602_up_tim_regout(TIMER_BASE + TIMER_TCCR_OFFSET, tmp_val);
+ modifyreg32(BL602_TIMER_TCCR, TIMER_TCCR_CS_WDT_MASK,
+ clk_src << TIMER_TCCR_CS_WDT_SHIFT);
- /* Configure watchdog timer clock divison */
+ /* Configure watchdog timer clock division */
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCDR_OFFSET);
- tmp_val = bl602_data_setbits(tmp_val, TIMER_WCDR_POS, 8, div);
- bl602_up_tim_regout(TIMER_BASE + TIMER_TCDR_OFFSET, tmp_val);
+ modifyreg32(BL602_TIMER_TCDR, TIMER_TCDR_WCDR_MASK,
+ div << TIMER_TCDR_WCDR_SHIFT);
}
/****************************************************************************
@@ -589,17 +503,13 @@ void bl602_wdt_set_clock(uint32_t clk_src, uint8_t div)
*
****************************************************************************/
-uint32_t bl602_wdt_getmatchvalue(void)
+uint16_t bl602_wdt_getmatchvalue(void)
{
- uint32_t tmp_val;
-
bl602_wdt_access();
/* Get watchdog timer match register value */
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMR_OFFSET);
-
- return tmp_val;
+ return (uint16_t)(getreg32(BL602_TIMER_WMR) & TIMER_WMR_WMR_MASK);
}
/****************************************************************************
@@ -622,7 +532,7 @@ void bl602_wdt_setcompvalue(uint16_t val)
/* Set watchdog timer match register value */
- bl602_up_tim_regout(TIMER_BASE + TIMER_WMR_OFFSET, val);
+ putreg32(val, BL602_TIMER_WMR);
}
/****************************************************************************
@@ -641,15 +551,11 @@ void bl602_wdt_setcompvalue(uint16_t val)
uint16_t bl602_wdt_getcountervalue(void)
{
- uint32_t tmp_val;
-
bl602_wdt_access();
/* Get watchdog timer count register value */
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WVR_OFFSET);
-
- return tmp_val;
+ return (uint16_t)(getreg32(BL602_TIMER_WVR) & TIMER_WVR_WVR_MASK);
}
/****************************************************************************
@@ -668,18 +574,13 @@ uint16_t bl602_wdt_getcountervalue(void)
void bl602_wdt_resetcountervalue(void)
{
- uint32_t tmp_val;
-
/* Reset watchdog timer count register value */
bl602_wdt_access();
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WCR_OFFSET);
-
/* Set watchdog counter reset register bit0 to 1 */
- bl602_up_tim_regout(TIMER_BASE + TIMER_WCR_OFFSET,
- tmp_val |= 1 << TIMER_WCR_POS);
+ modifyreg32(BL602_TIMER_WCR, 0, TIMER_WCR_WCR);
}
/****************************************************************************
@@ -696,19 +597,13 @@ void bl602_wdt_resetcountervalue(void)
*
****************************************************************************/
-uint32_t bl602_wdt_getresetstatus(void)
+bool bl602_wdt_getresetstatus(void)
{
- uint32_t tmp_val;
- uint32_t ret;
-
bl602_wdt_access();
/* Get watchdog status register */
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSR_OFFSET);
-
- ret = (((tmp_val) & (1 << (TIMER_WTS_POS))) ? 1 : 0);
- return ret;
+ return ((getreg32(BL602_TIMER_WSR) & TIMER_WSR_WTS) != 0);
}
/****************************************************************************
@@ -727,16 +622,11 @@ uint32_t bl602_wdt_getresetstatus(void)
void bl602_wdt_clearresetstatus(void)
{
- uint32_t tmp_val;
-
bl602_wdt_access();
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSR_OFFSET);
-
/* Set watchdog status register */
- bl602_up_tim_regout(TIMER_BASE + TIMER_WSR_OFFSET,
- tmp_val &= ~(1 << TIMER_WTS_POS));
+ modifyreg32(BL602_TIMER_WSR, TIMER_WSR_WTS, 0);
}
/****************************************************************************
@@ -755,14 +645,9 @@ void bl602_wdt_clearresetstatus(void)
void bl602_wdt_enable(void)
{
- uint32_t tmp_val;
-
bl602_wdt_access();
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET);
-
- bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET,
- tmp_val |= 1 << TIMER_WE_POS);
+ modifyreg32(BL602_TIMER_WMER, 0, TIMER_WMER_WE);
}
/****************************************************************************
@@ -781,14 +666,9 @@ void bl602_wdt_enable(void)
void bl602_wdt_disable(void)
{
- uint32_t tmp_val;
-
bl602_wdt_access();
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET);
-
- bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET,
- tmp_val &= ~(1 << TIMER_WE_POS));
+ modifyreg32(BL602_TIMER_WMER, TIMER_WMER_WE, 0);
}
/****************************************************************************
@@ -799,26 +679,22 @@ void bl602_wdt_disable(void)
*
* Input Parameters:
* int_type - Watchdog interrupt type.
- * int_mask - Watchdog interrupt mask value:BL_STD_MASK:disbale
- *interrupt.BL_STD_UNMASK:enable interrupt.
+ * int_mask - Watchdog interrupt mask value:BL_STD_MASK:disable
+ * interrupt.BL_STD_UNMASK:enable interrupt.
*
* Returned Value:
* None.
*
****************************************************************************/
-void bl602_wdt_intmask(uint32_t int_type, uint32_t int_mask)
+void bl602_wdt_intmask(uint8_t int_type, uint8_t int_mask)
{
- uint32_t tmp_val;
-
bl602_wdt_access();
/* Deal with watchdog match/interrupt enable register,WRIE:watchdog
* reset/interrupt enable
*/
- tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET);
-
switch (int_type)
{
case WDT_INT:
@@ -830,8 +706,7 @@ void bl602_wdt_intmask(uint32_t int_type, uint32_t int_mask)
* not generated
*/
- bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET,
- tmp_val &= ~(1 << TIMER_WRIE_POS));
+ modifyreg32(BL602_TIMER_WMER, TIMER_WMER_WRIE, 0);
}
else
{
@@ -841,8 +716,7 @@ void bl602_wdt_intmask(uint32_t int_type, uint32_t int_mask)
* not generated
*/
- bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET,
- tmp_val |= 1 << TIMER_WRIE_POS);
+ modifyreg32(BL602_TIMER_WMER, 0, TIMER_WMER_WRIE);
}
break;
diff --git a/arch/risc-v/src/bl602/bl602_tim.h b/arch/risc-v/src/bl602/bl602_tim.h
new file mode 100644
index 0000000..6e408fb
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_tim.h
@@ -0,0 +1,513 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_tim.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_BL602_TIM_H
+#define __ARCH_RISCV_SRC_BL602_BL602_TIM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* TIMER channel type definition */
+
+#define TIMER_CH0 0 /* TIMER channel 0 port */
+#define TIMER_CH1 1 /* TIMER channel 1 port */
+#define TIMER_CH_MAX 2
+
+/* TIMER clock source type definition */
+
+#define TIMER_CLKSRC_FCLK 0 /* TIMER clock source :System CLK */
+#define TIMER_CLKSRC_32K 1 /* TIMER clock source :32K CLK */
+#define TIMER_CLKSRC_1K 2 /* TIMER clock source :1K CLK (not for WDT) */
+#define TIMER_CLKSRC_XTAL 3 /* TIMER clock source :XTAL CLK */
+
+/* TIMER match compare ID type definition */
+
+#define TIMER_COMP_ID_0 0 /* TIMER match compare ID 0 */
+#define TIMER_COMP_ID_1 1 /* TIMER match compare ID 1 */
+#define TIMER_COMP_ID_2 2 /* TIMER match compare ID 2 */
+#define TIMER_MAX_MATCH 3
+
+/* TIMER preload source type definition */
+
+#define TIMER_PRELOAD_TRIG_NONE 0 /* TIMER no preload source, free run */
+#define TIMER_PRELOAD_TRIG_COMP0 1 /* TIMER count register preload triggered by comparator 0 */
+#define TIMER_PRELOAD_TRIG_COMP1 2 /* TIMER count register preload triggered by comparator 1 */
+#define TIMER_PRELOAD_TRIG_COMP2 3 /* TIMER count register preload triggered by comparator 2 */
+
+/* TIMER count register run mode type definition */
+
+#define TIMER_COUNT_PRELOAD 0 /* TIMER count register preload from comparator register */
+#define TIMER_COUNT_FREERUN 1 /* TIMER count register free run */
+
+/* TIMER interrupt type definition */
+
+#define TIMER_INT_COMP_0 0 /* Comparator 0 match cause interrupt */
+#define TIMER_INT_COMP_1 1 /* Comparator 1 match cause interrupt */
+#define TIMER_INT_COMP_2 2 /* Comparator 2 match cause interrupt */
+#define TIMER_INT_ALL 3
+
+/* Watchdog timer interrupt type definition */
+
+#define WDT_INT 0 /* Comparator 0 match cause interrupt */
+#define WDT_INT_ALL 1
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+struct timer_cfg_s
+{
+ uint8_t timer_ch; /* Timer channel */
+ uint8_t clk_src; /* Timer clock source */
+
+ /* Timer count register preload trigger source select */
+
+ uint8_t pl_trig_src;
+
+ uint8_t count_mode; /* Timer count mode */
+ uint8_t clock_division; /* Timer clock division value */
+ uint32_t match_val0; /* Timer match 0 value 0 */
+ uint32_t match_val1; /* Timer match 1 value 0 */
+ uint32_t match_val2; /* Timer match 2 value 0 */
+ uint32_t pre_load_val; /* Timer preload value */
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_timer_getcompvalue
+ *
+ * Description:
+ * Get the specified channel and match comparator value.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * cmp_no - TIMER comparator ID type.
+ *
+ * Returned Value:
+ * Match comapre register value
+ *
+ ****************************************************************************/
+
+uint32_t bl602_timer_getcompvalue(uint8_t timer_ch, uint8_t cmp_no);
+
+/****************************************************************************
+ * Name: bl602_timer_setcompvalue
+ *
+ * Description:
+ * TIMER set specified channel and comparator compare value
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * cmp_no - TIMER comparator ID type.
+ * val - TIMER match comapre register value.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void bl602_timer_setcompvalue(uint8_t timer_ch, uint8_t cmp_no,
+ uint32_t val);
+
+/****************************************************************************
+ * Name: bl602_timer_getcountervalue
+ *
+ * Description:
+ * TIMER get the specified channel count value.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type
+ *
+ * Returned Value:
+ * TIMER count register value
+ *
+ ****************************************************************************/
+
+uint32_t bl602_timer_getcountervalue(uint32_t timer_ch);
+
+/****************************************************************************
+ * Name: bl602_timer_getmatchstatus
+ *
+ * Description:
+ * TIMER get specified channel and comparator match status
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * cmp_no - TIMER comparator ID type.
+ *
+ * Returned Value:
+ * match status
+ *
+ ****************************************************************************/
+
+bool bl602_timer_getmatchstatus(uint32_t timer_ch, uint8_t cmp_no);
+
+/****************************************************************************
+ * Name: bl602_timer_getpreloadvalue
+ *
+ * Description:
+ * TIMER get specified channel preload value
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ *
+ * Returned Value:
+ * Preload register value.
+ *
+ ****************************************************************************/
+
+uint32_t bl602_timer_getpreloadvalue(uint32_t timer_ch);
+
+/****************************************************************************
+ * Name: bl602_timer_setpreloadvalue
+ *
+ * Description:
+ * TIMER set preload register low 32bits value
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * val - Preload register low 32bits value.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_timer_setpreloadvalue(uint8_t timer_ch, uint32_t val);
+
+/****************************************************************************
+ * Name: bl602_timer_setpreloadtrigsrc
+ *
+ * Description:
+ * TIMER set preload trigger source,COMP0,COMP1,COMP2 or None
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * pl_src - TIMER preload source type.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_timer_setpreloadtrigsrc(uint8_t timer_ch, uint32_t pl_src);
+
+/****************************************************************************
+ * Name: bl602_timer_setcountmode
+ *
+ * Description:
+ * TIMER set count mode:preload or free run
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * count_mode - TIMER count mode: TIMER_COUNT_PRELOAD or
+ * TIMER_COUNT_FREERUN.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_timer_setcountmode(uint32_t timer_ch, uint8_t count_mode);
+
+/****************************************************************************
+ * Name: bl602_timer_clearintstatus
+ *
+ * Description:
+ * TIMER clear interrupt status
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * cmp_no - TIMER macth comparator ID type.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_timer_clearintstatus(uint8_t timer_ch, uint32_t cmp_no);
+
+/****************************************************************************
+ * Name: bl602_timer_init
+ *
+ * Description:
+ * TIMER initialization function.
+ *
+ * Input Parameters:
+ * timer_cfg - TIMER configuration structure pointer.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void bl602_timer_init(struct timer_cfg_s *timer_cfg);
+
+/****************************************************************************
+ * Name: bl602_timer_enable
+ *
+ * Description:
+ * TIMER enable one channel function.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_timer_enable(uint8_t timer_ch);
+
+/****************************************************************************
+ * Name: bl602_timer_disable
+ *
+ * Description:
+ * TIMER disable one channel function.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_timer_disable(uint8_t timer_ch);
+
+/****************************************************************************
+ * Name: bl602_timer_intmask
+ *
+ * Description:
+ * TIMER mask or unmask certain or all interrupt.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * int_type - TIMER interrupt type.
+ * int_mask - TIMER interrupt mask value:1:disbale interrupt.0:enable
+ * interrupt.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_timer_intmask(uint8_t timer_ch, uint8_t int_type,
+ uint8_t int_mask);
+
+/****************************************************************************
+ * Name: bl602_wdt_set_clock
+ *
+ * Description:
+ * TIMER set watchdog clock source and clock division.
+ *
+ * Input Parameters:
+ * clk_src - Watchdog timer clock source type.
+ * div - Watchdog timer clock division value.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_wdt_set_clock(uint8_t clk_src, uint8_t div);
+
+/****************************************************************************
+ * Name: bl602_wdt_getmatchvalue
+ *
+ * Description:
+ * TIMER get watchdog match compare value.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Watchdog match comapre register value.
+ *
+ ****************************************************************************/
+
+uint16_t bl602_wdt_getmatchvalue(void);
+
+/****************************************************************************
+ * Name: bl602_wdt_setcompvalue
+ *
+ * Description:
+ * TIMER set watchdog match compare value.
+ *
+ * Input Parameters:
+ * val - Watchdog match compare value
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_wdt_setcompvalue(uint16_t val);
+
+/****************************************************************************
+ * Name: bl602_wdt_getcountervalue
+ *
+ * Description:
+ * TIMER get watchdog count register value.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Watchdog count register value.
+ *
+ ****************************************************************************/
+
+uint16_t bl602_wdt_getcountervalue(void);
+
+/****************************************************************************
+ * Name: bl602_wdt_resetcountervalue
+ *
+ * Description:
+ * TIMER reset watchdog count register value.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_wdt_resetcountervalue(void);
+
+/****************************************************************************
+ * Name: bl602_wdt_getresetstatus
+ *
+ * Description:
+ * TIMER get watchdog reset status.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * 0 or 1.
+ *
+ ****************************************************************************/
+
+bool bl602_wdt_getresetstatus(void);
+
+/****************************************************************************
+ * Name: bl602_wdt_clearresetstatus
+ *
+ * Description:
+ * TIMER clear watchdog reset status.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_wdt_clearresetstatus(void);
+
+/****************************************************************************
+ * Name: bl602_wdt_enable
+ *
+ * Description:
+ * TIMER enable watchdog function.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_wdt_enable(void);
+
+/****************************************************************************
+ * Name: bl602_wdt_disable
+ *
+ * Description:
+ * Watchdog timer disable function.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_wdt_disable(void);
+
+/****************************************************************************
+ * Name: bl602_wdt_intmask
+ *
+ * Description:
+ * Watchdog timer mask or unmask certain or all interrupt.
+ *
+ * Input Parameters:
+ * int_type - Watchdog interrupt type.
+ * int_mask - Watchdog interrupt mask value:BL_STD_MASK:disable
+ * interrupt.BL_STD_UNMASK:enable interrupt.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void bl602_wdt_intmask(uint8_t int_type, uint8_t int_mask);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_BL602_TIM_H */
diff --git a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
index 5cc756c..5e8f5e1 100644
--- a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
+++ b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
@@ -37,8 +37,10 @@
#include <arch/board/board.h>
#include "riscv_arch.h"
-#include <hardware/bl602_glb.h>
-#include <hardware/bl602_timer.h>
+#include "hardware/bl602_glb.h"
+#include "hardware/bl602_timer.h"
+#include "bl602_tim_lowerhalf.h"
+#include "bl602_glb.h"
/****************************************************************************
* Pre-processor Definitions
@@ -142,15 +144,15 @@ static int bl602_timer_handler(int irq, void *context, void *arg)
uint32_t tmp_val;
uint32_t tmp_addr;
- int_id = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
- tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
+ int_id = getreg32(BL602_TIMER_TMSR2 + 4 * priv->tim);
+ tmp_addr = BL602_TIMER_TICR2 + 4 * priv->tim;
tmp_val = getreg32(tmp_addr);
/* Comparator 0 match interrupt */
- if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0)
+ if ((int_id & TIMER_TMSR2_TMSR_0) != 0)
{
- putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr);
+ putreg32(tmp_val | TIMER_TMSR2_TMSR_0, tmp_addr);
if (priv->callback(&next_interval_us, priv->arg))
{
if (next_interval_us > 0)
@@ -173,16 +175,16 @@ static int bl602_timer_handler(int irq, void *context, void *arg)
/* Comparator 1 match interrupt */
- if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0)
+ if ((int_id & TIMER_TMSR2_TMSR_1) != 0)
{
- putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr);
+ putreg32(tmp_val | TIMER_TICR2_TCLR_1, tmp_addr);
}
/* Comparator 2 match interrupt */
- if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0)
+ if ((int_id & TIMER_TMSR2_TMSR_2) != 0)
{
- putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr);
+ putreg32(tmp_val | TIMER_TICR2_TCLR_2, tmp_addr);
}
return OK;
@@ -337,10 +339,11 @@ static int bl602_tim_settimeout(FAR struct timer_lowerhalf_s *lower,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
- *"lower-half" driver state structure. callback - The new timer expiration
- *function pointer. If this function pointer is NULL, then the
- *reset-on-expiration behavior is restored, arg - Argument that will be
- *provided in the callback
+ * "lower-half" driver state structure.
+ * callback - The new timer expiration function pointer. If this function
+ * pointer is NULL, then the reset-on-expiration behavior is
+ * restored.
+ * arg - Argument that will be provided in the callback
*
* Returned Value:
* The previous timer expiration function pointer or NULL is there was
@@ -389,7 +392,7 @@ static void bl602_tim_setcallback(FAR struct timer_lowerhalf_s *lower,
int bl602_timer_initialize(FAR const char *devpath, int timer)
{
FAR struct bl602_tim_lowerhalf_s *lower;
- timer_cfg_t timstr;
+ struct timer_cfg_s timstr;
switch (timer)
{
@@ -420,7 +423,7 @@ int bl602_timer_initialize(FAR const char *devpath, int timer)
timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
- bl602_glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR);
+ bl602_swrst_ahb_slave1(AHB_SLAVE1_TMR);
bl602_timer_intmask(lower->tim, TIMER_INT_ALL, 1);
diff --git a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
index 5514532..1fe11d3 100644
--- a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
+++ b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
@@ -27,7 +27,8 @@
#include <nuttx/config.h>
-#include <bl602_tim_lowerhalf.h>
+#include "bl602_tim_lowerhalf.h"
+#include "bl602_tim.h"
/****************************************************************************
* Public Function Prototypes
@@ -37,6 +38,6 @@
* Name: bl602_timer_initialize
****************************************************************************/
-int bl602_timer_initialize(FAR const char *devpath, uint8_t timer);
+int bl602_timer_initialize(FAR const char *devpath, int timer);
#endif /* __ARCH_RISCV_SRC_BL602_TIM_LOWERHALF_H */
diff --git a/arch/risc-v/src/bl602/bl602_timerisr.c b/arch/risc-v/src/bl602/bl602_timerisr.c
index 1f6e22e..f02b2ec 100644
--- a/arch/risc-v/src/bl602/bl602_timerisr.c
+++ b/arch/risc-v/src/bl602/bl602_timerisr.c
@@ -31,7 +31,7 @@
#include <nuttx/arch.h>
#include <nuttx/clock.h>
#include <arch/board/board.h>
-#include "hardware/bl602_clint.h"
+#include "hardware/bl602_clic.h"
#include "riscv_arch.h"
#include "chip.h"
@@ -61,21 +61,21 @@ static bool g_b_tick_started = false;
static inline uint64_t bl602_clint_time_read(void)
{
- uint64_t r = getreg32(BL602_MTIMER_HIGH);
+ uint64_t r = getreg32(BL602_CLIC_MTIME + 4);
r <<= 32;
- r |= getreg32(BL602_MTIMER_LOW);
+ r |= getreg32(BL602_CLIC_MTIME);
return r;
}
static inline uint64_t bl602_clint_time_cmp_read(void)
{
- return getreg64(BL602_MTIMER_CMP);
+ return getreg64(BL602_CLIC_MTIMECMP);
}
static inline void bl602_clint_time_cmp_write(uint64_t v)
{
- putreg64(v, BL602_MTIMER_CMP);
+ putreg64(v, BL602_CLIC_MTIMECMP);
}
/****************************************************************************
diff --git a/arch/risc-v/src/bl602/hardware/bl602_aon.h b/arch/risc-v/src/bl602/hardware/bl602_aon.h
new file mode 100644
index 0000000..81990e3
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_aon.h
@@ -0,0 +1,387 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_aon.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_AON_SEC_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_AON_SEC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "bl602_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define BL602_AON_OFFSET 0x000800 /* aon */
+#define BL602_AON_COMMON_OFFSET 0x000804 /* aon_common */
+#define BL602_AON_MISC_OFFSET 0x000808 /* aon_misc */
+#define BL602_BG_SYS_TOP_OFFSET 0x000810 /* bg_sys_top */
+#define BL602_DCDC18_TOP_0_OFFSET 0x000814 /* dcdc18_top_0 */
+#define BL602_DCDC18_TOP_1_OFFSET 0x000818 /* dcdc18_top_1 */
+#define BL602_LDO11SOC_AND_DCTEST_OFFSET 0x00081c /* ldo11soc_and_dctest */
+#define BL602_PSW_IRRCV_OFFSET 0x000820 /* psw_irrcv */
+#define BL602_RF_TOP_AON_OFFSET 0x000880 /* rf_top_aon */
+#define BL602_XTAL_CFG_OFFSET 0x000884 /* xtal_cfg */
+#define BL602_TSEN_OFFSET 0x000888 /* tsen */
+#define BL602_ACOMP0_CTRL_OFFSET 0x000900 /* acomp0_ctrl */
+#define BL602_ACOMP1_CTRL_OFFSET 0x000904 /* acomp1_ctrl */
+#define BL602_ACOMP_CTRL_OFFSET 0x000908 /* acomp_ctrl */
+#define BL602_GPADC_REG_CMD_OFFSET 0x00090c /* gpadc_reg_cmd */
+#define BL602_GPADC_REG_CONFIG1_OFFSET 0x000910 /* gpadc_reg_config1 */
+#define BL602_GPADC_REG_CONFIG2_OFFSET 0x000914 /* gpadc_reg_config2 */
+#define BL602_GPADC_REG_SCN_POS1_OFFSET 0x000918 /* adc conversion sequence 1 */
+#define BL602_GPADC_REG_SCN_POS2_OFFSET 0x00091c /* adc conversion sequence 2 */
+#define BL602_GPADC_REG_SCN_NEG1_OFFSET 0x000920 /* adc conversion sequence 3 */
+#define BL602_GPADC_REG_SCN_NEG2_OFFSET 0x000924 /* adc conversion sequence 4 */
+#define BL602_GPADC_REG_STATUS_OFFSET 0x000928 /* gpadc_reg_status */
+#define BL602_GPADC_REG_ISR_OFFSET 0x00092c /* gpadc_reg_isr */
+#define BL602_GPADC_REG_RESULT_OFFSET 0x000930 /* gpadc_reg_result */
+#define BL602_GPADC_REG_RAW_RESULT_OFFSET 0x000934 /* gpadc_reg_raw_result */
+#define BL602_GPADC_REG_DEFINE_OFFSET 0x000938 /* gpadc_reg_define */
+#define BL602_HBNCORE_RESV0_OFFSET 0x00093c /* hbncore_resv0 */
+#define BL602_HBNCORE_RESV1_OFFSET 0x000940 /* hbncore_resv1 */
+
+/* Register definitions *****************************************************/
+
+#define BL602_AON (BL602_AON_BASE + BL602_AON_OFFSET)
+#define BL602_AON_COMMON (BL602_AON_BASE + BL602_AON_COMMON_OFFSET)
+#define BL602_AON_MISC (BL602_AON_BASE + BL602_AON_MISC_OFFSET)
+#define BL602_BG_SYS_TOP (BL602_AON_BASE + BL602_BG_SYS_TOP_OFFSET)
+#define BL602_DCDC18_TOP_0 (BL602_AON_BASE + BL602_DCDC18_TOP_0_OFFSET)
+#define BL602_DCDC18_TOP_1 (BL602_AON_BASE + BL602_DCDC18_TOP_1_OFFSET)
+#define BL602_LDO11SOC_AND_DCTEST (BL602_AON_BASE + BL602_LDO11SOC_AND_DCTEST_OFFSET)
+#define BL602_PSW_IRRCV (BL602_AON_BASE + BL602_PSW_IRRCV_OFFSET)
+#define BL602_RF_TOP_AON (BL602_AON_BASE + BL602_RF_TOP_AON_OFFSET)
+#define BL602_XTAL_CFG (BL602_AON_BASE + BL602_XTAL_CFG_OFFSET)
+#define BL602_TSEN (BL602_AON_BASE + BL602_TSEN_OFFSET)
+#define BL602_ACOMP0_CTRL (BL602_AON_BASE + BL602_ACOMP0_CTRL_OFFSET)
+#define BL602_ACOMP1_CTRL (BL602_AON_BASE + BL602_ACOMP1_CTRL_OFFSET)
+#define BL602_ACOMP_CTRL (BL602_AON_BASE + BL602_ACOMP_CTRL_OFFSET)
+#define BL602_GPADC_REG_CMD (BL602_AON_BASE + BL602_GPADC_REG_CMD_OFFSET)
+#define BL602_GPADC_REG_CONFIG1 (BL602_AON_BASE + BL602_GPADC_REG_CONFIG1_OFFSET)
+#define BL602_GPADC_REG_CONFIG2 (BL602_AON_BASE + BL602_GPADC_REG_CONFIG2_OFFSET)
+#define BL602_GPADC_REG_SCN_POS1 (BL602_AON_BASE + BL602_GPADC_REG_SCN_POS1_OFFSET)
+#define BL602_GPADC_REG_SCN_POS2 (BL602_AON_BASE + BL602_GPADC_REG_SCN_POS2_OFFSET)
+#define BL602_GPADC_REG_SCN_NEG1 (BL602_AON_BASE + BL602_GPADC_REG_SCN_NEG1_OFFSET)
+#define BL602_GPADC_REG_SCN_NEG2 (BL602_AON_BASE + BL602_GPADC_REG_SCN_NEG2_OFFSET)
+#define BL602_GPADC_REG_STATUS (BL602_AON_BASE + BL602_GPADC_REG_STATUS_OFFSET)
+#define BL602_GPADC_REG_ISR (BL602_AON_BASE + BL602_GPADC_REG_ISR_OFFSET)
+#define BL602_GPADC_REG_RESULT (BL602_AON_BASE + BL602_GPADC_REG_RESULT_OFFSET)
+#define BL602_GPADC_REG_RAW_RESULT (BL602_AON_BASE + BL602_GPADC_REG_RAW_RESULT_OFFSET)
+#define BL602_GPADC_REG_DEFINE (BL602_AON_BASE + BL602_GPADC_REG_DEFINE_OFFSET)
+#define BL602_HBNCORE_RESV0 (BL602_AON_BASE + BL602_HBNCORE_RESV0_OFFSET)
+#define BL602_HBNCORE_RESV1 (BL602_AON_BASE + BL602_HBNCORE_RESV1_OFFSET)
+
+/* Register bit definitions *************************************************/
+
+#define SW_PU_LDO11_RT (1 << 22)
+#define LDO11_RT_PULLDOWN_SEL (1 << 21)
+#define LDO11_RT_PULLDOWN (1 << 20)
+#define PU_AON_DC_TBUF (1 << 12)
+#define RESV_MASK (0xff)
+
+#define COMMON_TEN_CIP_MISC_AON (1 << 20)
+#define COMMON_TEN_MBG_AON (1 << 19)
+#define COMMON_DTEN_XTAL_AON (1 << 18)
+#define COMMON_TEN_XTAL_AON (1 << 17)
+#define COMMON_TEN_LDO15RF_AON (1 << 16)
+#define COMMON_TEN_BG_SYS_AON (1 << 12)
+#define COMMON_TEN_DCDC18_1_AON (1 << 11)
+#define COMMON_TEN_DCDC18_0_AON (1 << 10)
+#define COMMON_TEN_LDO11SOC_AON (1 << 9)
+#define COMMON_TEN_VDDCORE_AON (1 << 8)
+#define COMMON_TEN_XTAL32K (1 << 6)
+#define COMMON_DTEN_XTAL32K (1 << 5)
+#define COMMON_TEN_AON (1 << 4)
+#define COMMON_TMUX_AON_MASK (0x07)
+
+#define MISC_SW_WB_EN_AON (1 << 1)
+#define MISC_SW_SOC_EN_AON (1 << 0)
+
+#define BG_SYS_TOP_BG_SYS_START_CTRL_AON (1 << 12)
+#define BG_SYS_TOP_PU_BG_SYS_AON (1 << 8)
+#define BG_SYS_TOP_PMIP_RESV_MASK (0xff)
+
+#define DCDC18_TOP_0_DCDC18_RDY_AON (1 << 31)
+#define DCDC18_TOP_0_DCDC18_SSTART_TIME_AON_SHIFT (28)
+#define DCDC18_TOP_0_DCDC18_SSTART_TIME_AON_MASK (0x03 << DCDC18_TOP_0_DCDC18_SSTART_TIME_AON_SHIFT)
+#define DCDC18_TOP_0_DCDC18_OSC_INHIBIT_T2_AON (1 << 27)
+#define DCDC18_TOP_0_DCDC18_SLOW_OSC_AON (1 << 26)
+#define DCDC18_TOP_0_DCDC18_STOP_OSC_AON (1 << 25)
+#define DCDC18_TOP_0_DCDC18_SLOPE_CURR_SEL_AON_SHIFT (20)
+#define DCDC18_TOP_0_DCDC18_SLOPE_CURR_SEL_AON_MASK (0x1f << DCDC18_TOP_0_DCDC18_SLOPE_CURR_SEL_AON_SHIFT)
+#define DCDC18_TOP_0_DCDC18_OSC_FREQ_TRIM_AON_SHIFT (16)
+#define DCDC18_TOP_0_DCDC18_OSC_FREQ_TRIM_AON_MASK (0x0f << DCDC18_TOP_0_DCDC18_OSC_FREQ_TRIM_AON_SHIFT)
+#define DCDC18_TOP_0_DCDC18_OSC_2M_MODE_AON (1 << 12)
+#define DCDC18_TOP_0_DCDC18_VPFM_AON_SHIFT (8)
+#define DCDC18_TOP_0_DCDC18_VPFM_AON_MASK (0x0f << DCDC18_TOP_0_DCDC18_VPFM_AON_SHIFT)
+#define DCDC18_TOP_0_DCDC18_VOUT_SEL_AON_SHIFT (1)
+#define DCDC18_TOP_0_DCDC18_VOUT_SEL_AON_MASK (0x1f << DCDC18_TOP_0_DCDC18_VOUT_SEL_AON_SHIFT)
+
+#define DCDC18_TOP_1_DCDC18_PULLDOWN_AON (1 << 29)
+#define DCDC18_TOP_1_DCDC18_EN_ANTIRING_AON (1 << 28)
+#define DCDC18_TOP_1_DCDC18_CFB_SEL_AON_SHIFT (24)
+#define DCDC18_TOP_1_DCDC18_CFB_SEL_AON_MASK (0x0f << DCDC18_TOP_1_DCDC18_CFB_SEL_AON_SHIFT)
+#define DCDC18_TOP_1_DCDC18_CHF_SEL_AON_SHIFT (20)
+#define DCDC18_TOP_1_DCDC18_CHF_SEL_AON_MASK (0x0f << DCDC18_TOP_1_DCDC18_CHF_SEL_AON_SHIFT)
+#define DCDC18_TOP_1_DCDC18_RC_SEL_AON_SHIFT (16)
+#define DCDC18_TOP_1_DCDC18_RC_SEL_AON_MASK (0x0f << DCDC18_TOP_1_DCDC18_RC_SEL_AON_SHIFT)
+#define DCDC18_TOP_1_DCDC18_NONOVERLAP_TD_AON_SHIFT (8)
+#define DCDC18_TOP_1_DCDC18_NONOVERLAP_TD_AON_MASK (0x1f << DCDC18_TOP_1_DCDC18_NONOVERLAP_TD_AON_SHIFT)
+#define DCDC18_TOP_1_DCDC18_ZVS_TD_OPT_AON_SHIFT (4)
+#define DCDC18_TOP_1_DCDC18_ZVS_TD_OPT_AON_MASK (0x07 << DCDC18_TOP_1_DCDC18_ZVS_TD_OPT_AON_SHIFT)
+#define DCDC18_TOP_1_DCDC18_CS_DELAY_AON_SHIFT (1)
+#define DCDC18_TOP_1_DCDC18_CS_DELAY_AON_MASK (0x07 << DCDC18_TOP_1_DCDC18_CS_DELAY_AON_SHIFT)
+#define DCDC18_TOP_1_DCDC18_FORCE_CS_ZVS_AON (1 << 0)
+
+#define LDO11SOC_AND_DCTEST_PMIP_DC_TP_OUT_EN_AON (1 << 31)
+#define LDO11SOC_AND_DCTEST_PU_VDDCORE_MISC_AON (1 << 30)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_POWER_GOOD_AON (1 << 29)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_RDY_AON (1 << 28)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_CC_AON_SHIFT (24)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_CC_AON_MASK (0x03 << LDO11SOC_AND_DCTEST_LDO11SOC_CC_AON_SHIFT)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_VTH_SEL_AON_SHIFT (12)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_VTH_SEL_AON_MASK (0x03 << LDO11SOC_AND_DCTEST_LDO11SOC_VTH_SEL_AON_SHIFT)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_PULLDOWN_SEL_AON (1 << 11)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_PULLDOWN_AON (1 << 10)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_SSTART_DELAY_AON_SHIFT (8)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_SSTART_DELAY_AON_MASK (0x03 << LDO11SOC_AND_DCTEST_LDO11SOC_SSTART_DELAY_AON_SHIFT)
+#define LDO11SOC_AND_DCTEST_LDO11SOC_SSTART_SEL_AON (1 << 4)
+#define LDO11SOC_AND_DCTEST_PU_LDO11SOC_AON (1 << 0)
+
+#define PSW_IRRCV_PU_IR_PSW_AON (1 << 0)
+
+#define RF_TOP_AON_LDO15RF_BYPASS_AON (1 << 28)
+#define RF_TOP_AON_LDO15RF_CC_AON_SHIFT (24)
+#define RF_TOP_AON_LDO15RF_CC_AON_MASK (0x03 << RF_TOP_AON_LDO15RF_CC_AON_SHIFT)
+#define RF_TOP_AON_LDO15RF_VOUT_SEL_AON_SHIFT (16)
+#define RF_TOP_AON_LDO15RF_VOUT_SEL_AON_MASK (0x07 << RF_TOP_AON_LDO15RF_VOUT_SEL_AON_SHIFT)
+#define RF_TOP_AON_LDO15RF_PULLDOWN_SEL_AON (1 << 13)
+#define RF_TOP_AON_LDO15RF_PULLDOWN_AON (1 << 12)
+#define RF_TOP_AON_LDO15RF_SSTART_DELAY_AON_SHIFT (9)
+#define RF_TOP_AON_LDO15RF_SSTART_DELAY_AON_MASK (0x03 << RF_TOP_AON_LDO15RF_SSTART_DELAY_AON_SHIFT)
+#define RF_TOP_AON_LDO15RF_SSTART_SEL_AON (1 << 8)
+#define RF_TOP_AON_PU_XTAL_AON (1 << 5)
+#define RF_TOP_AON_PU_XTAL_BUF_AON (1 << 4)
+#define RF_TOP_AON_PU_SFREG_AON (1 << 2)
+#define RF_TOP_AON_PU_LDO15RF_AON (1 << 1)
+#define RF_TOP_AON_PU_MBG_AON (1 << 0)
+
+#define XTAL_CFG_XTAL_RDY_SEL_AON_SHIFT (30)
+#define XTAL_CFG_XTAL_RDY_SEL_AON_MASK (0x03 << XTAL_CFG_XTAL_RDY_SEL_AON_SHIFT)
+#define XTAL_CFG_XTAL_GM_BOOST_AON_SHIFT (28)
+#define XTAL_CFG_XTAL_GM_BOOST_AON_MASK (0x03 << XTAL_CFG_XTAL_GM_BOOST_AON_SHIFT)
+#define XTAL_CFG_XTAL_CAPCODE_IN_AON_SHIFT (22)
+#define XTAL_CFG_XTAL_CAPCODE_IN_AON_MASK (0x3f << XTAL_CFG_XTAL_CAPCODE_IN_AON_SHIFT)
+#define XTAL_CFG_XTAL_CAPCODE_OUT_AON_SHIFT (16)
+#define XTAL_CFG_XTAL_CAPCODE_OUT_AON_MASK (0x3f << XTAL_CFG_XTAL_CAPCODE_OUT_AON_SHIFT)
+#define XTAL_CFG_XTAL_AMP_CTRL_AON_SHIFT (14)
+#define XTAL_CFG_XTAL_AMP_CTRL_AON_MASK (0x03 << XTAL_CFG_XTAL_AMP_CTRL_AON_SHIFT)
+#define XTAL_CFG_XTAL_SLEEP_AON (1 << 13)
+#define XTAL_CFG_XTAL_FAST_STARTUP_AON (1 << 12)
+#define XTAL_CFG_XTAL_BUF_HP_AON_SHIFT (8)
+#define XTAL_CFG_XTAL_BUF_HP_AON_MASK (0x0f << XTAL_CFG_XTAL_BUF_HP_AON_SHIFT)
+#define XTAL_CFG_XTAL_BUF_EN_AON_SHIFT (4)
+#define XTAL_CFG_XTAL_BUF_EN_AON_MASK (0x0f << XTAL_CFG_XTAL_BUF_EN_AON_SHIFT)
+#define XTAL_CFG_XTAL_EXT_SEL_AON (1 << 3)
+#define XTAL_CFG_XTAL_CAPCODE_EXTRA_AON (1 << 2)
+#define XTAL_CFG_XTAL_BK_AON_MASK (0x03)
+
+#define TSEN_XTAL_RDY_INT_SEL_AON_SHIFT (30)
+#define TSEN_XTAL_RDY_INT_SEL_AON_MASK (0x03 << TSEN_XTAL_RDY_INT_SEL_AON_SHIFT)
+#define TSEN_XTAL_INN_CFG_EN_AON (1 << 29)
+#define TSEN_XTAL_RDY (1 << 28)
+#define TSEN_TSEN_REFCODE_RFCAL_SHIFT (16)
+#define TSEN_TSEN_REFCODE_RFCAL_MASK (0xfff << TSEN_TSEN_REFCODE_RFCAL_SHIFT)
+#define TSEN_TSEN_REFCODE_CORNER_MASK (0xfff)
+
+#define ACOMP0_CTRL_ACOMP0_MUXEN (1 << 26)
+#define ACOMP0_CTRL_ACOMP0_POS_SEL_SHIFT (22)
+#define ACOMP0_CTRL_ACOMP0_POS_SEL_MASK (0x0f << ACOMP0_CTRL_ACOMP0_POS_SEL_SHIFT)
+#define ACOMP0_CTRL_ACOMP0_NEG_SEL_SHIFT (18)
+#define ACOMP0_CTRL_ACOMP0_NEG_SEL_MASK (0x0f << ACOMP0_CTRL_ACOMP0_NEG_SEL_SHIFT)
+#define ACOMP0_CTRL_ACOMP0_LEVEL_SEL_SHIFT (12)
+#define ACOMP0_CTRL_ACOMP0_LEVEL_SEL_MASK (0x3f << ACOMP0_CTRL_ACOMP0_LEVEL_SEL_SHIFT)
+#define ACOMP0_CTRL_ACOMP0_BIAS_PROG_SHIFT (10)
+#define ACOMP0_CTRL_ACOMP0_BIAS_PROG_MASK (0x03 << ACOMP0_CTRL_ACOMP0_BIAS_PROG_SHIFT)
+#define ACOMP0_CTRL_ACOMP0_HYST_SELP_SHIFT (7)
+#define ACOMP0_CTRL_ACOMP0_HYST_SELP_MASK (0x07 << ACOMP0_CTRL_ACOMP0_HYST_SELP_SHIFT)
+#define ACOMP0_CTRL_ACOMP0_HYST_SELN_SHIFT (4)
+#define ACOMP0_CTRL_ACOMP0_HYST_SELN_MASK (0x07 << ACOMP0_CTRL_ACOMP0_HYST_SELN_SHIFT)
+#define ACOMP0_CTRL_ACOMP0_EN (1 << 0)
+
+#define ACOMP1_CTRL_ACOMP1_MUXEN (1 << 26)
+#define ACOMP1_CTRL_ACOMP1_POS_SEL_SHIFT (22)
+#define ACOMP1_CTRL_ACOMP1_POS_SEL_MASK (0x0f << ACOMP1_CTRL_ACOMP1_POS_SEL_SHIFT)
+#define ACOMP1_CTRL_ACOMP1_NEG_SEL_SHIFT (18)
+#define ACOMP1_CTRL_ACOMP1_NEG_SEL_MASK (0x0f << ACOMP1_CTRL_ACOMP1_NEG_SEL_SHIFT)
+#define ACOMP1_CTRL_ACOMP1_LEVEL_SEL_SHIFT (12)
+#define ACOMP1_CTRL_ACOMP1_LEVEL_SEL_MASK (0x3f << ACOMP1_CTRL_ACOMP1_LEVEL_SEL_SHIFT)
+#define ACOMP1_CTRL_ACOMP1_BIAS_PROG_SHIFT (10)
+#define ACOMP1_CTRL_ACOMP1_BIAS_PROG_MASK (0x03 << ACOMP1_CTRL_ACOMP1_BIAS_PROG_SHIFT)
+#define ACOMP1_CTRL_ACOMP1_HYST_SELP_SHIFT (7)
+#define ACOMP1_CTRL_ACOMP1_HYST_SELP_MASK (0x07 << ACOMP1_CTRL_ACOMP1_HYST_SELP_SHIFT)
+#define ACOMP1_CTRL_ACOMP1_HYST_SELN_SHIFT (4)
+#define ACOMP1_CTRL_ACOMP1_HYST_SELN_MASK (0x07 << ACOMP1_CTRL_ACOMP1_HYST_SELN_SHIFT)
+#define ACOMP1_CTRL_ACOMP1_EN (1 << 0)
+
+#define ACOMP_CTRL_ACOMP0_OUT_RAW (1 << 19)
+#define ACOMP_CTRL_ACOMP1_OUT_RAW (1 << 17)
+#define ACOMP_CTRL_ACOMP0_TEST_SEL_SHIFT (12)
+#define ACOMP_CTRL_ACOMP0_TEST_SEL_MASK (0x03 << ACOMP_CTRL_ACOMP0_TEST_SEL_SHIFT)
+#define ACOMP_CTRL_ACOMP1_TEST_SEL_SHIFT (10)
+#define ACOMP_CTRL_ACOMP1_TEST_SEL_MASK (0x03 << ACOMP_CTRL_ACOMP1_TEST_SEL_SHIFT)
+#define ACOMP_CTRL_ACOMP0_TEST_EN (1 << 9)
+#define ACOMP_CTRL_ACOMP1_TEST_EN (1 << 8)
+#define ACOMP_CTRL_ACOMP0_RSTN_ANA (1 << 1)
+#define ACOMP_CTRL_ACOMP1_RSTN_ANA (1 << 0)
+
+#define GPADC_REG_CMD_GPADC_SEN_TEST_EN (1 << 30)
+#define GPADC_REG_CMD_GPADC_SEN_SEL_SHIFT (28)
+#define GPADC_REG_CMD_GPADC_SEN_SEL_MASK (0x03 << GPADC_REG_CMD_GPADC_SEN_SEL_SHIFT)
+#define GPADC_REG_CMD_GPADC_CHIP_SEN_PU (1 << 27)
+#define GPADC_REG_CMD_GPADC_MICBOOST_32DB_EN (1 << 23)
+#define GPADC_REG_CMD_GPADC_MIC_PGA2_GAIN_SHIFT (21)
+#define GPADC_REG_CMD_GPADC_MIC_PGA2_GAIN_MASK (0x03 << GPADC_REG_CMD_GPADC_MIC_PGA2_GAIN_SHIFT)
+#define GPADC_REG_CMD_GPADC_MIC1_DIFF (1 << 20)
+#define GPADC_REG_CMD_GPADC_MIC2_DIFF (1 << 19)
+#define GPADC_REG_CMD_GPADC_DWA_EN (1 << 18)
+#define GPADC_REG_CMD_GPADC_BYP_MICBOOST (1 << 16)
+#define GPADC_REG_CMD_GPADC_MICPGA_EN (1 << 15)
+#define GPADC_REG_CMD_GPADC_MICBIAS_EN (1 << 14)
+#define GPADC_REG_CMD_GPADC_NEG_GND (1 << 13)
+#define GPADC_REG_CMD_GPADC_POS_SEL_SHIFT (8)
+#define GPADC_REG_CMD_GPADC_POS_SEL_MASK (0x1f << GPADC_REG_CMD_GPADC_POS_SEL_SHIFT)
+#define GPADC_REG_CMD_GPADC_NEG_SEL_SHIFT (3)
+#define GPADC_REG_CMD_GPADC_NEG_SEL_MASK (0x1f << GPADC_REG_CMD_GPADC_NEG_SEL_SHIFT)
+#define GPADC_REG_CMD_GPADC_SOFT_RST (1 << 2)
+#define GPADC_REG_CMD_GPADC_CONV_START (1 << 1)
+#define GPADC_REG_CMD_GPADC_GLOBAL_EN (1 << 0)
+
+#define GPADC_REG_CONFIG1_GPADC_V18_SEL_SHIFT (29)
+#define GPADC_REG_CONFIG1_GPADC_V18_SEL_MASK (0x03 << GPADC_REG_CONFIG1_GPADC_V18_SEL_SHIFT)
+#define GPADC_REG_CONFIG1_GPADC_V11_SEL_SHIFT (27)
+#define GPADC_REG_CONFIG1_GPADC_V11_SEL_MASK (0x03 << GPADC_REG_CONFIG1_GPADC_V11_SEL_SHIFT)
+#define GPADC_REG_CONFIG1_GPADC_DITHER_EN (1 << 26)
+#define GPADC_REG_CONFIG1_GPADC_SCAN_EN (1 << 25)
+#define GPADC_REG_CONFIG1_GPADC_SCAN_LENGTH_SHIFT (21)
+#define GPADC_REG_CONFIG1_GPADC_SCAN_LENGTH_MASK (0x0f << GPADC_REG_CONFIG1_GPADC_SCAN_LENGTH_SHIFT)
+#define GPADC_REG_CONFIG1_GPADC_CLK_DIV_RATIO_SHIFT (18)
+#define GPADC_REG_CONFIG1_GPADC_CLK_DIV_RATIO_MASK (0x07 << GPADC_REG_CONFIG1_GPADC_CLK_DIV_RATIO_SHIFT)
+#define GPADC_REG_CONFIG1_GPADC_CLK_ANA_INV (1 << 17)
+#define GPADC_REG_CONFIG1_GPADC_RES_SEL_SHIFT (2)
+#define GPADC_REG_CONFIG1_GPADC_RES_SEL_MASK (0x07 << GPADC_REG_CONFIG1_GPADC_RES_SEL_SHIFT)
+#define GPADC_REG_CONFIG1_GPADC_CONT_CONV_EN (1 << 1)
+#define GPADC_REG_CONFIG1_GPADC_CAL_OS_EN (1 << 0)
+
+#define GPADC_REG_CONFIG2_GPADC_TSVBE_LOW (1 << 31)
+#define GPADC_REG_CONFIG2_GPADC_DLY_SEL_SHIFT (28)
+#define GPADC_REG_CONFIG2_GPADC_DLY_SEL_MASK (0x07 << GPADC_REG_CONFIG2_GPADC_DLY_SEL_SHIFT)
+#define GPADC_REG_CONFIG2_GPADC_PGA1_GAIN_SHIFT (25)
+#define GPADC_REG_CONFIG2_GPADC_PGA1_GAIN_MASK (0x07 << GPADC_REG_CONFIG2_GPADC_PGA1_GAIN_SHIFT)
+#define GPADC_REG_CONFIG2_GPADC_PGA2_GAIN_SHIFT (22)
+#define GPADC_REG_CONFIG2_GPADC_PGA2_GAIN_MASK (0x07 << GPADC_REG_CONFIG2_GPADC_PGA2_GAIN_SHIFT)
+#define GPADC_REG_CONFIG2_GPADC_TEST_SEL_SHIFT (19)
+#define GPADC_REG_CONFIG2_GPADC_TEST_SEL_MASK (0x07 << GPADC_REG_CONFIG2_GPADC_TEST_SEL_SHIFT)
+#define GPADC_REG_CONFIG2_GPADC_TEST_EN (1 << 18)
+#define GPADC_REG_CONFIG2_GPADC_BIAS_SEL (1 << 17)
+#define GPADC_REG_CONFIG2_GPADC_CHOP_MODE_SHIFT (15)
+#define GPADC_REG_CONFIG2_GPADC_CHOP_MODE_MASK (0x03 << GPADC_REG_CONFIG2_GPADC_CHOP_MODE_SHIFT)
+#define GPADC_REG_CONFIG2_GPADC_PGA_VCMI_EN (1 << 14)
+#define GPADC_REG_CONFIG2_GPADC_PGA_EN (1 << 13)
+#define GPADC_REG_CONFIG2_GPADC_PGA_OS_CAL_SHIFT (9)
+#define GPADC_REG_CONFIG2_GPADC_PGA_OS_CAL_MASK (0x0f << GPADC_REG_CONFIG2_GPADC_PGA_OS_CAL_SHIFT)
+#define GPADC_REG_CONFIG2_GPADC_PGA_VCM_SHIFT (7)
+#define GPADC_REG_CONFIG2_GPADC_PGA_VCM_MASK (0x03 << GPADC_REG_CONFIG2_GPADC_PGA_VCM_SHIFT)
+#define GPADC_REG_CONFIG2_GPADC_TS_EN (1 << 6)
+#define GPADC_REG_CONFIG2_GPADC_TSEXT_SEL (1 << 5)
+#define GPADC_REG_CONFIG2_GPADC_VBAT_EN (1 << 4)
+#define GPADC_REG_CONFIG2_GPADC_VREF_SEL (1 << 3)
+#define GPADC_REG_CONFIG2_GPADC_DIFF_MODE (1 << 2)
+
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_5_SHIFT (25)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_5_MASK (0x1f << GPADC_REG_SCN_POS1_GPADC_SCAN_POS_5_SHIFT)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_4_SHIFT (20)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_4_MASK (0x1f << GPADC_REG_SCN_POS1_GPADC_SCAN_POS_4_SHIFT)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_3_SHIFT (15)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_3_MASK (0x1f << GPADC_REG_SCN_POS1_GPADC_SCAN_POS_3_SHIFT)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_2_SHIFT (10)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_2_MASK (0x1f << GPADC_REG_SCN_POS1_GPADC_SCAN_POS_2_SHIFT)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_1_SHIFT (5)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_1_MASK (0x1f << GPADC_REG_SCN_POS1_GPADC_SCAN_POS_1_SHIFT)
+#define GPADC_REG_SCN_POS1_GPADC_SCAN_POS_0_MASK (0x1f)
+
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_11_SHIFT (25)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_11_MASK (0x1f << GPADC_REG_SCN_POS2_GPADC_SCAN_POS_11_SHIFT)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_10_SHIFT (20)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_10_MASK (0x1f << GPADC_REG_SCN_POS2_GPADC_SCAN_POS_10_SHIFT)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_9_SHIFT (15)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_9_MASK (0x1f << GPADC_REG_SCN_POS2_GPADC_SCAN_POS_9_SHIFT)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_8_SHIFT (10)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_8_MASK (0x1f << GPADC_REG_SCN_POS2_GPADC_SCAN_POS_8_SHIFT)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_7_SHIFT (5)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_7_MASK (0x1f << GPADC_REG_SCN_POS2_GPADC_SCAN_POS_7_SHIFT)
+#define GPADC_REG_SCN_POS2_GPADC_SCAN_POS_6_MASK (0x1f)
+
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_5_SHIFT (25)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_5_MASK (0x1f << GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_5_SHIFT)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_4_SHIFT (20)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_4_MASK (0x1f << GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_4_SHIFT)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_3_SHIFT (15)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_3_MASK (0x1f << GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_3_SHIFT)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_2_SHIFT (10)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_2_MASK (0x1f << GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_2_SHIFT)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_1_SHIFT (5)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_1_MASK (0x1f << GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_1_SHIFT)
+#define GPADC_REG_SCN_NEG1_GPADC_SCAN_NEG_0_MASK (0x1f)
+
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_11_SHIFT (25)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_11_MASK (0x1f << GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_11_SHIFT)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_10_SHIFT (20)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_10_MASK (0x1f << GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_10_SHIFT)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_9_SHIFT (15)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_9_MASK (0x1f << GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_9_SHIFT)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_8_SHIFT (10)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_8_MASK (0x1f << GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_8_SHIFT)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_7_SHIFT (5)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_7_MASK (0x1f << GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_7_SHIFT)
+#define GPADC_REG_SCN_NEG2_GPADC_SCAN_NEG_6_MASK (0x1f)
+
+#define GPADC_REG_STATUS_GPADC_DATA_RDY (1 << 0)
+
+#define GPADC_REG_ISR_GPADC_POS_SATUR_MASK (1 << 9)
+#define GPADC_REG_ISR_GPADC_NEG_SATUR_MASK (1 << 8)
+#define GPADC_REG_ISR_GPADC_POS_SATUR_CLR (1 << 5)
+#define GPADC_REG_ISR_GPADC_NEG_SATUR_CLR (1 << 4)
+#define GPADC_REG_ISR_GPADC_POS_SATUR (1 << 1)
+#define GPADC_REG_ISR_GPADC_NEG_SATUR (1 << 0)
+
+#define GPADC_REG_RESULT_GPADC_DATA_OUT_MASK (0x3ffffff)
+
+#define GPADC_REG_RAW_RESULT_GPADC_RAW_DATA_MASK (0xfff)
+
+#define GPADC_REG_DEFINE_GPADC_OS_CAL_DATA_MASK (0xffff)
+
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_AON_SEC_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_cci.h b/arch/risc-v/src/bl602/hardware/bl602_cci.h
new file mode 100644
index 0000000..101f9c8
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_cci.h
@@ -0,0 +1,69 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_cci.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "bl602_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define BL602_CCI_CFG_OFFSET 0x000000 /* cci_cfg */
+#define BL602_CCI_ADDR_OFFSET 0x000004 /* cci_addr */
+#define BL602_CCI_WDATA_OFFSET 0x000008 /* cci_wdata */
+#define BL602_CCI_RDATA_OFFSET 0x00000c /* cci_rdata */
+#define BL602_CCI_CTL_OFFSET 0x000010 /* cci_ctl */
+
+/* Register definitions *****************************************************/
+
+#define BL602_CCI_CFG (BL602_CCI_BASE + BL602_CCI_CFG_OFFSET)
+#define BL602_CCI_ADDR (BL602_CCI_BASE + BL602_CCI_ADDR_OFFSET)
+#define BL602_CCI_WDATA (BL602_CCI_BASE + BL602_CCI_WDATA_OFFSET)
+#define BL602_CCI_RDATA (BL602_CCI_BASE + BL602_CCI_RDATA_OFFSET)
+#define BL602_CCI_CTL (BL602_CCI_BASE + BL602_CCI_CTL_OFFSET)
+
+/* Register bit definitions *************************************************/
+
+#define CCI_CFG_REG_MCCI_CLK_INV (1 << 9)
+#define CCI_CFG_REG_SCCI_CLK_INV (1 << 8)
+#define CCI_CFG_CFG_CCI1_PRE_READ (1 << 7)
+#define CCI_CFG_REG_DIV_M_CCI_SCLK_SHIFT (5)
+#define CCI_CFG_REG_DIV_M_CCI_SCLK_MASK (0x03 << CCI_CFG_REG_DIV_M_CCI_SCLK_SHIFT)
+#define CCI_CFG_REG_M_CCI_SCLK_EN (1 << 4)
+#define CCI_CFG_CCI_MAS_HW_MODE (1 << 3)
+#define CCI_CFG_CCI_MAS_SEL_CCI2 (1 << 2)
+#define CCI_CFG_CCI_SLV_SEL_CCI2 (1 << 1)
+#define CCI_CFG_CCI_EN (1 << 0)
+
+#define CCI_CTL_AHB_STATE_SHIFT (2)
+#define CCI_CTL_AHB_STATE_MASK (0x03 << CCI_CTL_AHB_STATE_SHIFT)
+#define CCI_CTL_CCI_READ_FLAG (1 << 1)
+#define CCI_CTL_CCI_WRITE_FLAG (1 << 0)
+
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H */
diff --git a/boards/risc-v/bl602/bl602evb/include/board.h b/arch/risc-v/src/bl602/hardware/bl602_cks.h
similarity index 55%
copy from boards/risc-v/bl602/bl602evb/include/board.h
copy to arch/risc-v/src/bl602/hardware/bl602_cks.h
index be3f808..fb69f31 100644
--- a/boards/risc-v/bl602/bl602evb/include/board.h
+++ b/arch/risc-v/src/bl602/hardware/bl602_cks.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/risc-v/bl602/bl602evb/include/board.h
+ * arch/risc-v/src/bl602/hardware/bl602_cks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,51 +18,39 @@
*
****************************************************************************/
-#ifndef __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
-#define __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CKS_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
+#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-/****************************************************************************
- * Public Types
- ****************************************************************************/
+/* Register offsets *********************************************************/
-#ifndef __ASSEMBLY__
+#define BL602_CKS_CONFIG_OFFSET 0x000000 /* cks_config */
+#define BL602_CKS_DATA_IN_OFFSET 0x000004 /* data_in */
+#define BL602_CKS_OUT_OFFSET 0x000008 /* cks_out */
-/****************************************************************************
- * Public Data
- ****************************************************************************/
+/* Register definitions *****************************************************/
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
+#define BL602_CKS_CONFIG (BL602_CKS_BASE + BL602_CKS_CONFIG_OFFSET)
+#define BL602_CKS_DATA_IN (BL602_CKS_BASE + BL602_CKS_DATA_IN_OFFSET)
+#define BL602_CKS_OUT (BL602_CKS_BASE + BL602_CKS_OUT_OFFSET)
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
+/* Register bit definitions *************************************************/
-/****************************************************************************
- * Name: litex_boardinitialize
- ****************************************************************************/
+#define CKS_CONFIG_CR_CKS_BYTE_SWAP (1 << 1)
+#define CKS_CKS_CONFIG_CR_CKS_CLR (1 << 0)
+
+#define CKS_DATA_IN_MASK (0xff)
-void bl602_boardinitialize(void);
+#define CKS_OUT_MASK (0xffff)
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_RISC_V_BL602_BL602EVB_INCLUDE_BOARD_H */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CKS_H */
diff --git a/boards/risc-v/bl602/bl602evb/include/board.h b/arch/risc-v/src/bl602/hardware/bl602_clic.h
similarity index 52%
copy from boards/risc-v/bl602/bl602evb/include/board.h
copy to arch/risc-v/src/bl602/hardware/bl602_clic.h
index be3f808..c40c182 100644
--- a/boards/risc-v/bl602/bl602evb/include/board.h
+++ b/arch/risc-v/src/bl602/hardware/bl602_clic.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/risc-v/bl602/bl602evb/include/board.h
+ * arch/risc-v/src/bl602/hardware/bl602_clic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,51 +18,40 @@
*
****************************************************************************/
-#ifndef __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
-#define __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLIC_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLIC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
+#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-/****************************************************************************
- * Public Types
- ****************************************************************************/
+/* Register offsets *********************************************************/
-#ifndef __ASSEMBLY__
+#define BL602_CLIC_MSIP_OFFSET 0x0000
+#define BL602_CLIC_MTIMECMP_OFFSET 0x4000
+#define BL602_CLIC_MTIME_OFFSET 0xbff8
-/****************************************************************************
- * Public Data
- ****************************************************************************/
+#define BL602_CLIC_INTIP_OFFSET 0x000
+#define BL602_CLIC_INTIE_OFFSET 0x400
+#define BL602_CLIC_INTCFG_OFFSET 0x800
+#define BL602_CLIC_CFG_OFFSET 0xc00
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
+/* Register definitions *****************************************************/
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: litex_boardinitialize
- ****************************************************************************/
+#define BL602_CLIC_MSIP (BL602_CLIC_CTRL_BASE + BL602_CLIC_MSIP_OFFSET)
+#define BL602_CLIC_MTIMECMP (BL602_CLIC_CTRL_BASE + BL602_CLIC_MTIMECMP_OFFSET)
+#define BL602_CLIC_MTIME (BL602_CLIC_CTRL_BASE + BL602_CLIC_MTIME_OFFSET)
-void bl602_boardinitialize(void);
+#define BL602_CLIC_INTIP (BL602_CLIC_HART0_BASE + BL602_CLIC_INTIP_OFFSET)
+#define BL602_CLIC_INTIE (BL602_CLIC_HART0_BASE + BL602_CLIC_INTIE_OFFSET)
+#define BL602_CLIC_INTCFG (BL602_CLIC_HART0_BASE + BL602_CLIC_INTCFG_OFFSET)
+#define BL602_CLIC_CFG (BL602_CLIC_HART0_BASE + BL602_CLIC_CFG_OFFSET)
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_RISC_V_BL602_BL602EVB_INCLUDE_BOARD_H */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLIC_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_common.h b/arch/risc-v/src/bl602/hardware/bl602_common.h
deleted file mode 100644
index 2cd44dc..0000000
--- a/arch/risc-v/src/bl602/hardware/bl602_common.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/****************************************************************************
- * arch/risc-v/src/bl602/hardware/bl602_common.h
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
-#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <stdint.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define BL602_FLASH_XIP_BASE (0x23000000)
-#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP0_BASE (0x33000000)
-#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP1_BASE (0x43000000)
-#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP2_BASE (0x53000000)
-#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024)
-
-#define BL602_WRAM_BASE (0x42020000)
-#define BL602_WRAM_END (0x42020000 + 176 * 1024)
-#define BL602_WRAM_REMAP0_BASE (0x22020000)
-#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024)
-#define BL602_WRAM_REMAP1_BASE (0x32020000)
-
-#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024)
-#define BL602_WRAM_REMAP2_BASE (0x52020000)
-#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024)
-
-#define BL602_TCM_BASE (0x22008000)
-#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP0_BASE (0x32008000)
-#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP1_BASE (0x42008000)
-#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP2_BASE (0x52008000)
-#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024)
-
-/* BL602 peripherals base address */
-
-#define GLB_BASE (0x40000000)
-#define RF_BASE (0x40001000)
-
-/* AUX module base address */
-
-#define GPIP_BASE (0x40002000)
-
-/* Security Debug module base address */
-
-#define SEC_DBG_BASE (0x40003000)
-
-/* Security Engine module base address */
-
-#define SEC_ENG_BASE (0x40004000)
-
-/* Trustzone control security base address */
-
-#define TZC_SEC_BASE (0x40005000)
-
-/* Trustzone control none-security base address */
-
-#define TZC_NSEC_BASE (0x40006000)
-#define EF_DATA_BASE (0x40007000)
-#define EF_CTRL_BASE (0x40007000)
-#define CCI_BASE (0x40008000)
-
-/* L1 cache config base address */
-
-#define L1C_BASE (0x40009000)
-#define UART0_BASE (0x4000A000)
-#define UART1_BASE (0x4000A100)
-#define SPI_BASE (0x4000A200)
-#define I2C_BASE (0x4000A300)
-#define PWM_BASE (0x4000A400)
-#define TIMER_BASE (0x4000A500)
-#define IR_BASE (0x4000A600)
-#define SF_CTRL_BASE (0x4000B000)
-#define SF_CTRL_BUF_BASE (0x4000B700)
-#define DMA_BASE (0x4000C000)
-#define SDU_BASE (0x4000D000)
-
-/* Power down sleep module base address */
-
-#define PDS_BASE (0x4000E000)
-
-/* Hibernate module base address */
-
-#define HBN_BASE (0x4000F000)
-
-/* Always on module base address */
-
-#define AON_BASE (0x4000F000)
-#define HBN_RAM_BASE (0x40010000)
-
-/* Delay for a while */
-
-#define BL_DRV_DUMMY() \
- { \
- __asm volatile("nop"); \
- __asm volatile("nop"); \
- __asm volatile("nop"); \
- __asm volatile("nop"); \
- }
-
-#define BL_AHB_SLAVE1_GLB 0x00
-#define BL_AHB_SLAVE1_RF 0x01
-#define BL_AHB_SLAVE1_GPIP_PHY_AGC 0x02
-#define BL_AHB_SLAVE1_SEC_DBG 0x03
-#define BL_AHB_SLAVE1_SEC 0x04
-#define BL_AHB_SLAVE1_TZ1 0x05
-#define BL_AHB_SLAVE1_TZ2 0x06
-#define BL_AHB_SLAVE1_EFUSE 0x07
-#define BL_AHB_SLAVE1_CCI 0x08
-#define BL_AHB_SLAVE1_L1C 0x09
-#define BL_AHB_SLAVE1_RSVD0A 0x0a
-#define BL_AHB_SLAVE1_SFC 0x0b
-#define BL_AHB_SLAVE1_DMA 0x0c
-#define BL_AHB_SLAVE1_SDU 0x0d
-#define BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM 0x0e
-#define BL_AHB_SLAVE1_RSVD0F 0x0f
-#define BL_AHB_SLAVE1_UART0 0x10
-#define BL_AHB_SLAVE1_UART1 0x11
-#define BL_AHB_SLAVE1_SPI 0x12
-#define BL_AHB_SLAVE1_I2C 0x13
-#define BL_AHB_SLAVE1_PWM 0x14
-#define BL_AHB_SLAVE1_TMR 0x15
-#define BL_AHB_SLAVE1_IRR 0x16
-#define BL_AHB_SLAVE1_CKS 0x17
-#define BL_AHB_SLAVE1_MAX 0x18
-
-/* Std driver attribute macro */
-
-#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code")))
-#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const")))
-#define ATTR_TCM_SECTION __attribute__((section(".tcm_code")))
-#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const")))
-#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data")))
-#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code")))
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_dma.h b/arch/risc-v/src/bl602/hardware/bl602_dma.h
new file mode 100644
index 0000000..6d8a89b
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_dma.h
@@ -0,0 +1,254 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_dma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_DMA_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_DMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "bl602_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define BL602_DMA_INTSTATUS_OFFSET 0x000000 /* IntStatus */
+#define BL602_DMA_INTTCSTATUS_OFFSET 0x000004 /* IntTCStatus */
+#define BL602_DMA_INTTCCLEAR_OFFSET 0x000008 /* IntTCClear */
+#define BL602_DMA_INTERRORSTATUS_OFFSET 0x00000c /* IntErrorStatus */
+#define BL602_DMA_INTERRCLR_OFFSET 0x000010 /* IntErrClr */
+#define BL602_DMA_RAWINTTCSTATUS_OFFSET 0x000014 /* RawIntTCStatus */
+#define BL602_DMA_RAWINTERRORSTATUS_OFFSET 0x000018 /* RawIntErrorStatus */
+#define BL602_DMA_ENBLDCHNS_OFFSET 0x00001c /* EnbldChns */
+#define BL602_DMA_SOFTBREQ_OFFSET 0x000020 /* SoftBReq */
+#define BL602_DMA_SOFTSREQ_OFFSET 0x000024 /* SoftSReq */
+#define BL602_DMA_SOFTLBREQ_OFFSET 0x000028 /* SoftLBReq */
+#define BL602_DMA_SOFTLSREQ_OFFSET 0x00002c /* SoftLSReq */
+#define BL602_DMA_TOP_CONFIG_OFFSET 0x000030 /* Top_Config */
+#define BL602_DMA_SYNC_OFFSET 0x000034 /* Sync */
+#define BL602_DMA_C0SRCADDR_OFFSET 0x000100 /* C0SrcAddr */
+#define BL602_DMA_C0DSTADDR_OFFSET 0x000104 /* C0DstAddr */
+#define BL602_DMA_C0LLI_OFFSET 0x000108 /* C0LLI */
+#define BL602_DMA_C0CONTROL_OFFSET 0x00010c /* C0Control */
+#define BL602_DMA_C0CONFIG_OFFSET 0x000110 /* C0Config */
+#define BL602_DMA_C1SRCADDR_OFFSET 0x000200 /* C1SrcAddr */
+#define BL602_DMA_C1DSTADDR_OFFSET 0x000204 /* C1DstAddr */
+#define BL602_DMA_C1LLI_OFFSET 0x000208 /* C1LLI */
+#define BL602_DMA_C1CONTROL_OFFSET 0x00020c /* C1Control */
+#define BL602_DMA_C1CONFIG_OFFSET 0x000210 /* C1Config */
+#define BL602_DMA_C2SRCADDR_OFFSET 0x000300 /* C2SrcAddr */
+#define BL602_DMA_C2DSTADDR_OFFSET 0x000304 /* C2DstAddr */
+#define BL602_DMA_C2LLI_OFFSET 0x000308 /* C2LLI */
+#define BL602_DMA_C2CONTROL_OFFSET 0x00030c /* C2Control */
+#define BL602_DMA_C2CONFIG_OFFSET 0x000310 /* C2Config */
+#define BL602_DMA_C3SRCADDR_OFFSET 0x000400 /* C3SrcAddr */
+#define BL602_DMA_C3DSTADDR_OFFSET 0x000404 /* C3DstAddr */
+#define BL602_DMA_C3LLI_OFFSET 0x000408 /* C3LLI */
+#define BL602_DMA_C3CONTROL_OFFSET 0x00040c /* C3Control */
+#define BL602_DMA_C3CONFIG_OFFSET 0x000410 /* C3Config */
+
+/* Register definitions *****************************************************/
+
+#define BL602_DMA_INTSTATUS (BL602_DMA_BASE + BL602_DMA_INTSTATUS_OFFSET)
+#define BL602_DMA_INTTCSTATUS (BL602_DMA_BASE + BL602_DMA_INTTCSTATUS_OFFSET)
+#define BL602_DMA_INTTCCLEAR (BL602_DMA_BASE + BL602_DMA_INTTCCLEAR_OFFSET)
+#define BL602_DMA_INTERRORSTATUS (BL602_DMA_BASE + BL602_DMA_INTERRORSTATUS_OFFSET)
+#define BL602_DMA_INTERRCLR (BL602_DMA_BASE + BL602_DMA_INTERRCLR_OFFSET)
+#define BL602_DMA_RAWINTTCSTATUS (BL602_DMA_BASE + BL602_DMA_RAWINTTCSTATUS_OFFSET)
+#define BL602_DMA_RAWINTERRORSTATUS (BL602_DMA_BASE + BL602_DMA_RAWINTERRORSTATUS_OFFSET)
+#define BL602_DMA_ENBLDCHNS (BL602_DMA_BASE + BL602_DMA_ENBLDCHNS_OFFSET)
+#define BL602_DMA_SOFTBREQ (BL602_DMA_BASE + BL602_DMA_SOFTBREQ_OFFSET)
+#define BL602_DMA_SOFTSREQ (BL602_DMA_BASE + BL602_DMA_SOFTSREQ_OFFSET)
+#define BL602_DMA_SOFTLBREQ (BL602_DMA_BASE + BL602_DMA_SOFTLBREQ_OFFSET)
+#define BL602_DMA_SOFTLSREQ (BL602_DMA_BASE + BL602_DMA_SOFTLSREQ_OFFSET)
+#define BL602_DMA_TOP_CONFIG (BL602_DMA_BASE + BL602_DMA_TOP_CONFIG_OFFSET)
+#define BL602_DMA_SYNC (BL602_DMA_BASE + BL602_DMA_SYNC_OFFSET)
+#define BL602_DMA_C0SRCADDR (BL602_DMA_BASE + BL602_DMA_C0SRCADDR_OFFSET)
+#define BL602_DMA_C0DSTADDR (BL602_DMA_BASE + BL602_DMA_C0DSTADDR_OFFSET)
+#define BL602_DMA_C0LLI (BL602_DMA_BASE + BL602_DMA_C0LLI_OFFSET)
+#define BL602_DMA_C0CONTROL (BL602_DMA_BASE + BL602_DMA_C0CONTROL_OFFSET)
+#define BL602_DMA_C0CONFIG (BL602_DMA_BASE + BL602_DMA_C0CONFIG_OFFSET)
+#define BL602_DMA_C1SRCADDR (BL602_DMA_BASE + BL602_DMA_C1SRCADDR_OFFSET)
+#define BL602_DMA_C1DSTADDR (BL602_DMA_BASE + BL602_DMA_C1DSTADDR_OFFSET)
+#define BL602_DMA_C1LLI (BL602_DMA_BASE + BL602_DMA_C1LLI_OFFSET)
+#define BL602_DMA_C1CONTROL (BL602_DMA_BASE + BL602_DMA_C1CONTROL_OFFSET)
+#define BL602_DMA_C1CONFIG (BL602_DMA_BASE + BL602_DMA_C1CONFIG_OFFSET)
+#define BL602_DMA_C2SRCADDR (BL602_DMA_BASE + BL602_DMA_C2SRCADDR_OFFSET)
+#define BL602_DMA_C2DSTADDR (BL602_DMA_BASE + BL602_DMA_C2DSTADDR_OFFSET)
+#define BL602_DMA_C2LLI (BL602_DMA_BASE + BL602_DMA_C2LLI_OFFSET)
+#define BL602_DMA_C2CONTROL (BL602_DMA_BASE + BL602_DMA_C2CONTROL_OFFSET)
+#define BL602_DMA_C2CONFIG (BL602_DMA_BASE + BL602_DMA_C2CONFIG_OFFSET)
+#define BL602_DMA_C3SRCADDR (BL602_DMA_BASE + BL602_DMA_C3SRCADDR_OFFSET)
+#define BL602_DMA_C3DSTADDR (BL602_DMA_BASE + BL602_DMA_C3DSTADDR_OFFSET)
+#define BL602_DMA_C3LLI (BL602_DMA_BASE + BL602_DMA_C3LLI_OFFSET)
+#define BL602_DMA_C3CONTROL (BL602_DMA_BASE + BL602_DMA_C3CONTROL_OFFSET)
+#define BL602_DMA_C3CONFIG (BL602_DMA_BASE + BL602_DMA_C3CONFIG_OFFSET)
+
+/* Register bit definitions *************************************************/
+
+#define DMA_INTSTATUS_MASK (0xff)
+
+#define DMA_INTTCSTATUS_MASK (0xff)
+
+#define DMA_INTTCCLEAR_MASK (0xff)
+
+#define DMA_INTERRORSTATUS_MASK (0xff)
+
+#define DMA_INTERRCLR_MASK (0xff)
+
+#define DMA_RAWINTTCSTATUS_MASK (0xff)
+
+#define DMA_RAWINTERRORSTATUS_MASK (0xff)
+
+#define DMA_ENBLDCHNS_MASK (0xff)
+
+#define DMA_TOP_CONFIG_M (1 << 1)
+#define DMA_TOP_CONFIG_E (1 << 0)
+
+#define DMA_C0CONTROL_I (1 << 31)
+#define DMA_C0CONTROL_PROT_SHIFT (28)
+#define DMA_C0CONTROL_PROT_MASK (0x07 << DMA_C0CONTROL_PROT_SHIFT)
+#define DMA_C0CONTROL_DI (1 << 27)
+#define DMA_C0CONTROL_SI (1 << 26)
+#define DMA_C0CONTROL_SLARGERD (1 << 24)
+#define DMA_C0CONTROL_DWIDTH_SHIFT (21)
+#define DMA_C0CONTROL_DWIDTH_MASK (0x07 << DMA_C0CONTROL_DWIDTH_SHIFT)
+#define DMA_C0CONTROL_SWIDTH_SHIFT (18)
+#define DMA_C0CONTROL_SWIDTH_MASK (0x07 << DMA_C0CONTROL_SWIDTH_SHIFT)
+#define DMA_C0CONTROL_DBSIZE_SHIFT (15)
+#define DMA_C0CONTROL_DBSIZE_MASK (0x07 << DMA_C0CONTROL_DBSIZE_SHIFT)
+#define DMA_C0CONTROL_SBSIZE_SHIFT (12)
+#define DMA_C0CONTROL_SBSIZE_MASK (0x07 << DMA_C0CONTROL_SBSIZE_SHIFT)
+#define DMA_C0CONTROL_TRANSFERSIZE_MASK (0xfff)
+
+#define DMA_C0CONFIG_LLICOUNTER_SHIFT (20)
+#define DMA_C0CONFIG_LLICOUNTER_MASK (0x3ff << DMA_C0CONFIG_LLICOUNTER_SHIFT)
+#define DMA_C0CONFIG_H (1 << 18)
+#define DMA_C0CONFIG_A (1 << 17)
+#define DMA_C0CONFIG_L (1 << 16)
+#define DMA_C0CONFIG_ITC (1 << 15)
+#define DMA_C0CONFIG_IE (1 << 14)
+#define DMA_C0CONFIG_FLOWCNTRL_SHIFT (11)
+#define DMA_C0CONFIG_FLOWCNTRL_MASK (0x07 << DMA_C0CONFIG_FLOWCNTRL_SHIFT)
+#define DMA_C0CONFIG_DSTPERIPHERAL_SHIFT (6)
+#define DMA_C0CONFIG_DSTPERIPHERAL_MASK (0x1f << DMA_C0CONFIG_DSTPERIPHERAL_SHIFT)
+#define DMA_C0CONFIG_SRCPERIPHERAL_SHIFT (1)
+#define DMA_C0CONFIG_SRCPERIPHERAL_MASK (0x1f << DMA_C0CONFIG_SRCPERIPHERAL_SHIFT)
+#define DMA_C0CONFIG_E (1 << 0)
+
+#define DMA_C1LLI_LLI_SHIFT (2)
+#define DMA_C1LLI_LLI_MASK (0x3fffffff << DMA_C1LLI_LLI_SHIFT)
+
+#define DMA_C1CONTROL_I (1 << 31)
+#define DMA_C1CONTROL_PROT_SHIFT (28)
+#define DMA_C1CONTROL_PROT_MASK (0x07 << DMA_C1CONTROL_PROT_SHIFT)
+#define DMA_C1CONTROL_DI (1 << 27)
+#define DMA_C1CONTROL_SI (1 << 26)
+#define DMA_C1CONTROL_DWIDTH_SHIFT (21)
+#define DMA_C1CONTROL_DWIDTH_MASK (0x07 << DMA_C1CONTROL_DWIDTH_SHIFT)
+#define DMA_C1CONTROL_SWIDTH_SHIFT (18)
+#define DMA_C1CONTROL_SWIDTH_MASK (0x07 << DMA_C1CONTROL_SWIDTH_SHIFT)
+#define DMA_C1CONTROL_DBSIZE_SHIFT (15)
+#define DMA_C1CONTROL_DBSIZE_MASK (0x07 << DMA_C1CONTROL_DBSIZE_SHIFT)
+#define DMA_C1CONTROL_SBSIZE_SHIFT (12)
+#define DMA_C1CONTROL_SBSIZE_MASK (0x07 << DMA_C1CONTROL_SBSIZE_SHIFT)
+#define DMA_C1CONTROL_TRANSFERSIZE_MASK (0xfff)
+
+#define DMA_C1CONFIG_H (1 << 18)
+#define DMA_C1CONFIG_A (1 << 17)
+#define DMA_C1CONFIG_L (1 << 16)
+#define DMA_C1CONFIG_ITC (1 << 15)
+#define DMA_C1CONFIG_IE (1 << 14)
+#define DMA_C1CONFIG_FLOWCNTRL_SHIFT (11)
+#define DMA_C1CONFIG_FLOWCNTRL_MASK (0x07 << DMA_C1CONFIG_FLOWCNTRL_SHIFT)
+#define DMA_C1CONFIG_DSTPERIPHERAL_SHIFT (6)
+#define DMA_C1CONFIG_DSTPERIPHERAL_MASK (0x1f << DMA_C1CONFIG_DSTPERIPHERAL_SHIFT)
+#define DMA_C1CONFIG_SRCPERIPHERAL_SHIFT (1)
+#define DMA_C1CONFIG_SRCPERIPHERAL_MASK (0x1f << DMA_C1CONFIG_SRCPERIPHERAL_SHIFT)
+#define DMA_C1CONFIG_E (1 << 0)
+
+#define DMA_C2LLI_LLI_SHIFT (2)
+#define DMA_C2LLI_LLI_MASK (0x3fffffff << DMA_C2LLI_LLI_SHIFT)
+
+#define DMA_C2CONTROL_I (1 << 31)
+#define DMA_C2CONTROL_PROT_SHIFT (28)
+#define DMA_C2CONTROL_PROT_MASK (0x07 << DMA_C2CONTROL_PROT_SHIFT)
+#define DMA_C2CONTROL_DI (1 << 27)
+#define DMA_C2CONTROL_SI (1 << 26)
+#define DMA_C2CONTROL_DWIDTH_SHIFT (21)
+#define DMA_C2CONTROL_DWIDTH_MASK (0x07 << DMA_C2CONTROL_DWIDTH_SHIFT)
+#define DMA_C2CONTROL_SWIDTH_SHIFT (18)
+#define DMA_C2CONTROL_SWIDTH_MASK (0x07 << DMA_C2CONTROL_SWIDTH_SHIFT)
+#define DMA_C2CONTROL_DBSIZE_SHIFT (15)
+#define DMA_C2CONTROL_DBSIZE_MASK (0x07 << DMA_C2CONTROL_DBSIZE_SHIFT)
+#define DMA_C2CONTROL_SBSIZE_SHIFT (12)
+#define DMA_C2CONTROL_SBSIZE_MASK (0x07 << DMA_C2CONTROL_SBSIZE_SHIFT)
+#define DMA_C2CONTROL_TRANSFERSIZE_MASK (0xfff)
+
+#define DMA_C2CONFIG_H (1 << 18)
+#define DMA_C2CONFIG_A (1 << 17)
+#define DMA_C2CONFIG_L (1 << 16)
+#define DMA_C2CONFIG_ITC (1 << 15)
+#define DMA_C2CONFIG_IE (1 << 14)
+#define DMA_C2CONFIG_FLOWCNTRL_SHIFT (11)
+#define DMA_C2CONFIG_FLOWCNTRL_MASK (0x07 << DMA_C2CONFIG_FLOWCNTRL_SHIFT)
+#define DMA_C2CONFIG_DSTPERIPHERAL_SHIFT (6)
+#define DMA_C2CONFIG_DSTPERIPHERAL_MASK (0x1f << DMA_C2CONFIG_DSTPERIPHERAL_SHIFT)
+#define DMA_C2CONFIG_SRCPERIPHERAL_SHIFT (1)
+#define DMA_C2CONFIG_SRCPERIPHERAL_MASK (0x1f << DMA_C2CONFIG_SRCPERIPHERAL_SHIFT)
+#define DMA_C2CONFIG_E (1 << 0)
+
+#define DMA_C3LLI_LLI_SHIFT (2)
+#define DMA_C3LLI_LLI_MASK (0x3fffffff << DMA_C3LLI_LLI_SHIFT)
+
+#define DMA_C3CONTROL_I (1 << 31)
+#define DMA_C3CONTROL_PROT_SHIFT (28)
+#define DMA_C3CONTROL_PROT_MASK (0x07 << DMA_C3CONTROL_PROT_SHIFT)
+#define DMA_C3CONTROL_DI (1 << 27)
+#define DMA_C3CONTROL_SI (1 << 26)
+#define DMA_C3CONTROL_DWIDTH_SHIFT (21)
+#define DMA_C3CONTROL_DWIDTH_MASK (0x07 << DMA_C3CONTROL_DWIDTH_SHIFT)
+#define DMA_C3CONTROL_SWIDTH_SHIFT (18)
+#define DMA_C3CONTROL_SWIDTH_MASK (0x07 << DMA_C3CONTROL_SWIDTH_SHIFT)
+#define DMA_C3CONTROL_DBSIZE_SHIFT (15)
+#define DMA_C3CONTROL_DBSIZE_MASK (0x07 << DMA_C3CONTROL_DBSIZE_SHIFT)
+#define DMA_C3CONTROL_SBSIZE_SHIFT (12)
+#define DMA_C3CONTROL_SBSIZE_MASK (0x07 << DMA_C3CONTROL_SBSIZE_SHIFT)
+#define DMA_C3CONTROL_TRANSFERSIZE_MASK (0xfff)
+
+#define DMA_C3CONFIG_H (1 << 18)
+#define DMA_C3CONFIG_A (1 << 17)
+#define DMA_C3CONFIG_L (1 << 16)
+#define DMA_C3CONFIG_ITC (1 << 15)
+#define DMA_C3CONFIG_IE (1 << 14)
+#define DMA_C3CONFIG_FLOWCNTRL_SHIFT (11)
+#define DMA_C3CONFIG_FLOWCNTRL_MASK (0x07 << DMA_C3CONFIG_FLOWCNTRL_SHIFT)
+#define DMA_C3CONFIG_DSTPERIPHERAL_SHIFT (6)
+#define DMA_C3CONFIG_DSTPERIPHERAL_MASK (0x1f << DMA_C3CONFIG_DSTPERIPHERAL_SHIFT)
+#define DMA_C3CONFIG_SRCPERIPHERAL_SHIFT (1)
+#define DMA_C3CONFIG_SRCPERIPHERAL_MASK (0x1f << DMA_C3CONFIG_SRCPERIPHERAL_SHIFT)
+#define DMA_C3CONFIG_E (1 << 0)
+
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_DMA_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_ef.h b/arch/risc-v/src/bl602/hardware/bl602_ef.h
new file mode 100644
index 0000000..11cfc9b
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_ef.h
@@ -0,0 +1,372 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_ef.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_EF_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_EF_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "bl602_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define BL602_EF_CFG_0_OFFSET 0x000000 /* ef_cfg_0 */
+#define BL602_EF_DBG_PWD_LOW_OFFSET 0x000004 /* ef_dbg_pwd_low */
+#define BL602_EF_DBG_PWD_HIGH_OFFSET 0x000008 /* ef_dbg_pwd_high */
+#define BL602_EF_ANA_TRIM_0_OFFSET 0x00000c /* ef_ana_trim_0 */
+#define BL602_EF_SW_USAGE_0_OFFSET 0x000010 /* ef_sw_usage_0 */
+#define BL602_EF_WIFI_MAC_LOW_OFFSET 0x000014 /* ef_wifi_mac_low */
+#define BL602_EF_WIFI_MAC_HIGH_OFFSET 0x000018 /* ef_wifi_mac_high */
+#define BL602_EF_KEY_SLOT_0_W0_OFFSET 0x00001c /* ef_key_slot_0_w0 */
+#define BL602_EF_KEY_SLOT_0_W1_OFFSET 0x000020 /* ef_key_slot_0_w1 */
+#define BL602_EF_KEY_SLOT_0_W2_OFFSET 0x000024 /* ef_key_slot_0_w2 */
+#define BL602_EF_KEY_SLOT_0_W3_OFFSET 0x000028 /* ef_key_slot_0_w3 */
+#define BL602_EF_KEY_SLOT_1_W0_OFFSET 0x00002c /* ef_key_slot_1_w0 */
+#define BL602_EF_KEY_SLOT_1_W1_OFFSET 0x000030 /* ef_key_slot_1_w1 */
+#define BL602_EF_KEY_SLOT_1_W2_OFFSET 0x000034 /* ef_key_slot_1_w2 */
+#define BL602_EF_KEY_SLOT_1_W3_OFFSET 0x000038 /* ef_key_slot_1_w3 */
+#define BL602_EF_KEY_SLOT_2_W0_OFFSET 0x00003c /* ef_key_slot_2_w0 */
+#define BL602_EF_KEY_SLOT_2_W1_OFFSET 0x000040 /* ef_key_slot_2_w1 */
+#define BL602_EF_KEY_SLOT_2_W2_OFFSET 0x000044 /* ef_key_slot_2_w2 */
+#define BL602_EF_KEY_SLOT_2_W3_OFFSET 0x000048 /* ef_key_slot_2_w3 */
+#define BL602_EF_KEY_SLOT_3_W0_OFFSET 0x00004c /* ef_key_slot_3_w0 */
+#define BL602_EF_KEY_SLOT_3_W1_OFFSET 0x000050 /* ef_key_slot_3_w1 */
+#define BL602_EF_KEY_SLOT_3_W2_OFFSET 0x000054 /* ef_key_slot_3_w2 */
+#define BL602_EF_KEY_SLOT_3_W3_OFFSET 0x000058 /* ef_key_slot_3_w3 */
+#define BL602_EF_KEY_SLOT_4_W0_OFFSET 0x00005c /* ef_key_slot_4_w0 */
+#define BL602_EF_KEY_SLOT_4_W1_OFFSET 0x000060 /* ef_key_slot_4_w1 */
+#define BL602_EF_KEY_SLOT_4_W2_OFFSET 0x000064 /* ef_key_slot_4_w2 */
+#define BL602_EF_KEY_SLOT_4_W3_OFFSET 0x000068 /* ef_key_slot_4_w3 */
+#define BL602_EF_KEY_SLOT_5_W0_OFFSET 0x00006c /* ef_key_slot_5_w0 */
+#define BL602_EF_KEY_SLOT_5_W1_OFFSET 0x000070 /* ef_key_slot_5_w1 */
+#define BL602_EF_KEY_SLOT_5_W2_OFFSET 0x000074 /* ef_key_slot_5_w2 */
+#define BL602_EF_KEY_SLOT_5_W3_OFFSET 0x000078 /* ef_key_slot_5_w3 */
+#define BL602_EF_DATA_0_LOCK_OFFSET 0x00007c /* ef_data_0_lock */
+
+#define BL602_EF_REG_KEY_SLOT_6_W0_OFFSET 0x000080 /* reg_key_slot_6_w0 */
+#define BL602_EF_REG_KEY_SLOT_6_W1_OFFSET 0x000084 /* reg_key_slot_6_w1 */
+#define BL602_EF_REG_KEY_SLOT_6_W2_OFFSET 0x000088 /* reg_key_slot_6_w2 */
+#define BL602_EF_REG_KEY_SLOT_6_W3_OFFSET 0x00008c /* reg_key_slot_6_w3 */
+#define BL602_EF_REG_KEY_SLOT_7_W0_OFFSET 0x000090 /* reg_key_slot_7_w0 */
+#define BL602_EF_REG_KEY_SLOT_7_W1_OFFSET 0x000094 /* reg_key_slot_7_w1 */
+#define BL602_EF_REG_KEY_SLOT_7_W2_OFFSET 0x000098 /* reg_key_slot_7_w2 */
+#define BL602_EF_REG_KEY_SLOT_7_W3_OFFSET 0x00009c /* reg_key_slot_7_w3 */
+#define BL602_EF_REG_KEY_SLOT_8_W0_OFFSET 0x0000a0 /* reg_key_slot_8_w0 */
+#define BL602_EF_REG_KEY_SLOT_8_W1_OFFSET 0x0000a4 /* reg_key_slot_8_w1 */
+#define BL602_EF_REG_KEY_SLOT_8_W2_OFFSET 0x0000a8 /* reg_key_slot_8_w2 */
+#define BL602_EF_REG_KEY_SLOT_8_W3_OFFSET 0x0000ac /* reg_key_slot_8_w3 */
+#define BL602_EF_REG_KEY_SLOT_9_W0_OFFSET 0x0000b0 /* reg_key_slot_9_w0 */
+#define BL602_EF_REG_KEY_SLOT_9_W1_OFFSET 0x0000b4 /* reg_key_slot_9_w1 */
+#define BL602_EF_REG_KEY_SLOT_9_W2_OFFSET 0x0000b8 /* reg_key_slot_9_w2 */
+#define BL602_EF_REG_KEY_SLOT_9_W3_OFFSET 0x0000bc /* reg_key_slot_9_w3 */
+#define BL602_EF_REG_KEY_SLOT_10_W0_OFFSET 0x0000c0 /* reg_key_slot_10_w0 */
+#define BL602_EF_REG_KEY_SLOT_10_W1_OFFSET 0x0000c4 /* reg_key_slot_10_w1 */
+#define BL602_EF_REG_KEY_SLOT_10_W2_OFFSET 0x0000c8 /* reg_key_slot_10_w2 */
+#define BL602_EF_REG_KEY_SLOT_10_W3_OFFSET 0x0000cc /* reg_key_slot_10_w3 */
+#define BL602_EF_REG_KEY_SLOT_11_W0_OFFSET 0x0000d0 /* reg_key_slot_11_w0 */
+#define BL602_EF_REG_KEY_SLOT_11_W1_OFFSET 0x0000d4 /* reg_key_slot_11_w1 */
+#define BL602_EF_REG_KEY_SLOT_11_W2_OFFSET 0x0000d8 /* reg_key_slot_11_w2 */
+#define BL602_EF_REG_KEY_SLOT_11_W3_OFFSET 0x0000dc /* reg_key_slot_11_w3 */
+#define BL602_EF_REG_DATA_1_LOCK_OFFSET 0x0000e0 /* reg_data_1_lock */
+
+#define BL602_EF_IF_CTRL_0_OFFSET 0x000800 /* ef_if_ctrl_0 */
+#define BL602_EF_IF_CYC_0_OFFSET 0x000804 /* ef_if_cyc_0 */
+#define BL602_EF_IF_CYC_1_OFFSET 0x000808 /* ef_if_cyc_1 */
+#define BL602_EF_IF_0_MANUAL_OFFSET 0x00080c /* ef_if_0_manual */
+#define BL602_EF_IF_0_STATUS_OFFSET 0x000810 /* ef_if_0_status */
+#define BL602_EF_IF_CFG_0_OFFSET 0x000814 /* ef_if_cfg_0 */
+#define BL602_EF_SW_CFG_0_OFFSET 0x000818 /* ef_sw_cfg_0 */
+#define BL602_EF_RESERVED_OFFSET 0x00081c /* ef_reserved */
+#define BL602_EF_IF_ANA_TRIM_0_OFFSET 0x000820 /* ef_if_ana_trim_0 */
+#define BL602_EF_IF_SW_USAGE_0_OFFSET 0x000824 /* ef_if_sw_usage_0 */
+#define BL602_EF_CRC_CTRL_0_OFFSET 0x000a00 /* ef_crc_ctrl_0 */
+#define BL602_EF_CRC_CTRL_1_OFFSET 0x000a04 /* ef_crc_ctrl_1 */
+#define BL602_EF_CRC_CTRL_2_OFFSET 0x000a08 /* ef_crc_ctrl_2 */
+#define BL602_EF_CRC_CTRL_3_OFFSET 0x000a0c /* ef_crc_ctrl_3 */
+#define BL602_EF_CRC_CTRL_4_OFFSET 0x000a10 /* ef_crc_ctrl_4 */
+#define BL602_EF_CRC_CTRL_5_OFFSET 0x000a14 /* ef_crc_ctrl_5 */
+
+/* Register definitions *****************************************************/
+
+#define BL602_EF_CFG_0 ( BL602_EF_BASE + BL602_EF_CFG_0_OFFSET)
+#define BL602_EF_DBG_PWD_LOW ( BL602_EF_BASE + BL602_EF_DBG_PWD_LOW_OFFSET)
+#define BL602_EF_DBG_PWD_HIGH ( BL602_EF_BASE + BL602_EF_DBG_PWD_HIGH_OFFSET)
+#define BL602_EF_ANA_TRIM_0 ( BL602_EF_BASE + BL602_EF_ANA_TRIM_0_OFFSET)
+#define BL602_EF_SW_USAGE_0 ( BL602_EF_BASE + BL602_EF_SW_USAGE_0_OFFSET)
+#define BL602_EF_WIFI_MAC_LOW ( BL602_EF_BASE + BL602_EF_WIFI_MAC_LOW_OFFSET)
+#define BL602_EF_WIFI_MAC_HIGH ( BL602_EF_BASE + BL602_EF_WIFI_MAC_HIGH_OFFSET)
+#define BL602_EF_KEY_SLOT_0_W0 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_0_W0_OFFSET)
+#define BL602_EF_KEY_SLOT_0_W1 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_0_W1_OFFSET)
+#define BL602_EF_KEY_SLOT_0_W2 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_0_W2_OFFSET)
+#define BL602_EF_KEY_SLOT_0_W3 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_0_W3_OFFSET)
+#define BL602_EF_KEY_SLOT_1_W0 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_1_W0_OFFSET)
+#define BL602_EF_KEY_SLOT_1_W1 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_1_W1_OFFSET)
+#define BL602_EF_KEY_SLOT_1_W2 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_1_W2_OFFSET)
+#define BL602_EF_KEY_SLOT_1_W3 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_1_W3_OFFSET)
+#define BL602_EF_KEY_SLOT_2_W0 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_2_W0_OFFSET)
+#define BL602_EF_KEY_SLOT_2_W1 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_2_W1_OFFSET)
+#define BL602_EF_KEY_SLOT_2_W2 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_2_W2_OFFSET)
+#define BL602_EF_KEY_SLOT_2_W3 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_2_W3_OFFSET)
+#define BL602_EF_KEY_SLOT_3_W0 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_3_W0_OFFSET)
+#define BL602_EF_KEY_SLOT_3_W1 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_3_W1_OFFSET)
+#define BL602_EF_KEY_SLOT_3_W2 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_3_W2_OFFSET)
+#define BL602_EF_KEY_SLOT_3_W3 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_3_W3_OFFSET)
+#define BL602_EF_KEY_SLOT_4_W0 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_4_W0_OFFSET)
+#define BL602_EF_KEY_SLOT_4_W1 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_4_W1_OFFSET)
+#define BL602_EF_KEY_SLOT_4_W2 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_4_W2_OFFSET)
+#define BL602_EF_KEY_SLOT_4_W3 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_4_W3_OFFSET)
+#define BL602_EF_KEY_SLOT_5_W0 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_5_W0_OFFSET)
+#define BL602_EF_KEY_SLOT_5_W1 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_5_W1_OFFSET)
+#define BL602_EF_KEY_SLOT_5_W2 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_5_W2_OFFSET)
+#define BL602_EF_KEY_SLOT_5_W3 ( BL602_EF_BASE + BL602_EF_KEY_SLOT_5_W3_OFFSET)
+#define BL602_EF_DATA_0_LOCK ( BL602_EF_BASE + BL602_EF_DATA_0_LOCK_OFFSET)
+
+#define BL602_EF_REG_KEY_SLOT_6_W0 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_6_W0_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_6_W1 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_6_W1_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_6_W2 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_6_W2_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_6_W3 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_6_W3_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_7_W0 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_7_W0_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_7_W1 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_7_W1_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_7_W2 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_7_W2_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_7_W3 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_7_W3_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_8_W0 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_8_W0_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_8_W1 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_8_W1_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_8_W2 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_8_W2_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_8_W3 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_8_W3_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_9_W0 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_9_W0_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_9_W1 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_9_W1_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_9_W2 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_9_W2_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_9_W3 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_9_W3_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_10_W0 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_10_W0_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_10_W1 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_10_W1_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_10_W2 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_10_W2_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_10_W3 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_10_W3_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_11_W0 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_11_W0_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_11_W1 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_11_W1_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_11_W2 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_11_W2_OFFSET)
+#define BL602_EF_REG_KEY_SLOT_11_W3 ( BL602_EF_BASE + BL602_EF_REG_KEY_SLOT_11_W3_OFFSET)
+#define BL602_EF_REG_DATA_1_LOCK ( BL602_EF_BASE + BL602_EF_REG_DATA_1_LOCK_OFFSET)
+
+#define BL602_EF_IF_CTRL_0 ( BL602_EF_BASE + BL602_EF_IF_CTRL_0_OFFSET)
+#define BL602_EF_IF_CYC_0 ( BL602_EF_BASE + BL602_EF_IF_CYC_0_OFFSET)
+#define BL602_EF_IF_CYC_1 ( BL602_EF_BASE + BL602_EF_IF_CYC_1_OFFSET)
+#define BL602_EF_IF_0_MANUAL ( BL602_EF_BASE + BL602_EF_IF_0_MANUAL_OFFSET)
+#define BL602_EF_IF_0_STATUS ( BL602_EF_BASE + BL602_EF_IF_0_STATUS_OFFSET)
+#define BL602_EF_IF_CFG_0 ( BL602_EF_BASE + BL602_EF_IF_CFG_0_OFFSET)
+#define BL602_EF_SW_CFG_0 ( BL602_EF_BASE + BL602_EF_SW_CFG_0_OFFSET)
+#define BL602_EF_RESERVED ( BL602_EF_BASE + BL602_EF_RESERVED_OFFSET)
+#define BL602_EF_IF_ANA_TRIM_0 ( BL602_EF_BASE + BL602_EF_IF_ANA_TRIM_0_OFFSET)
+#define BL602_EF_IF_SW_USAGE_0 ( BL602_EF_BASE + BL602_EF_IF_SW_USAGE_0_OFFSET)
+#define BL602_EF_CRC_CTRL_0 ( BL602_EF_BASE + BL602_EF_CRC_CTRL_0_OFFSET)
+#define BL602_EF_CRC_CTRL_1 ( BL602_EF_BASE + BL602_EF_CRC_CTRL_1_OFFSET)
+#define BL602_EF_CRC_CTRL_2 ( BL602_EF_BASE + BL602_EF_CRC_CTRL_2_OFFSET)
+#define BL602_EF_CRC_CTRL_3 ( BL602_EF_BASE + BL602_EF_CRC_CTRL_3_OFFSET)
+#define BL602_EF_CRC_CTRL_4 ( BL602_EF_BASE + BL602_EF_CRC_CTRL_4_OFFSET)
+#define BL602_EF_CRC_CTRL_5 ( BL602_EF_BASE + BL602_EF_CRC_CTRL_5_OFFSET)
+
+/* Register bit definitions *************************************************/
+
+#define EF_CFG_0_EF_DBG_MODE_SHIFT (28)
+#define EF_CFG_0_EF_DBG_MODE_MASK (0x0f << EF_CFG_0_EF_DBG_MODE_SHIFT)
+#define EF_CFG_0_EF_DBG_JTAG_0_DIS_SHIFT (26)
+#define EF_CFG_0_EF_DBG_JTAG_0_DIS_MASK (0x03 << EF_CFG_0_EF_DBG_JTAG_0_DIS_SHIFT)
+#define EF_CFG_0_EF_DBG_JTAG_1_DIS_SHIFT (24)
+#define EF_CFG_0_EF_DBG_JTAG_1_DIS_MASK (0x03 << EF_CFG_0_EF_DBG_JTAG_1_DIS_SHIFT)
+#define EF_CFG_0_EF_EFUSE_DBG_DIS (1 << 23)
+#define EF_CFG_0_EF_SE_DBG_DIS (1 << 22)
+#define EF_CFG_0_EF_CPU_RST_DBG_DIS (1 << 21)
+#define EF_CFG_0_EF_CPU1_DIS (1 << 20)
+#define EF_CFG_0_EF_SF_DIS (1 << 19)
+#define EF_CFG_0_EF_CAM_DIS (1 << 18)
+#define EF_CFG_0_EF_0_KEY_ENC_EN (1 << 17)
+#define EF_CFG_0_EF_WIFI_DIS (1 << 16)
+#define EF_CFG_0_EF_BLE_DIS (1 << 15)
+#define EF_CFG_0_EF_SDU_DIS (1 << 14)
+#define EF_CFG_0_EF_SW_USAGE_1_SHIFT (12)
+#define EF_CFG_0_EF_SW_USAGE_1_MASK (0x03 << EF_CFG_0_EF_SW_USAGE_1_SHIFT)
+#define EF_CFG_0_EF_BOOT_SEL_SHIFT (8)
+#define EF_CFG_0_EF_BOOT_SEL_MASK (0x0f << EF_CFG_0_EF_BOOT_SEL_SHIFT)
+#define EF_CFG_0_EF_CPU0_ENC_EN (1 << 7)
+#define EF_CFG_0_EF_CPU1_ENC_EN (1 << 6)
+#define EF_CFG_0_EF_SBOOT_EN_SHIFT (4)
+#define EF_CFG_0_EF_SBOOT_EN_MASK (0x03 << EF_CFG_0_EF_SBOOT_EN_SHIFT)
+#define EF_CFG_0_EF_SBOOT_SIGN_MODE_SHIFT (2)
+#define EF_CFG_0_EF_SBOOT_SIGN_MODE_MASK (0x03 << EF_CFG_0_EF_SBOOT_SIGN_MODE_SHIFT)
+#define EF_CFG_0_EF_SF_AES_MODE_MASK (0x03)
+
+#define EF_LOCK_RD_LOCK_KEY_SLOT_5 (1 << 31)
+#define EF_LOCK_RD_LOCK_KEY_SLOT_4 (1 << 30)
+#define EF_LOCK_RD_LOCK_KEY_SLOT_3 (1 << 29)
+#define EF_LOCK_RD_LOCK_KEY_SLOT_2 (1 << 28)
+#define EF_LOCK_RD_LOCK_KEY_SLOT_1 (1 << 27)
+#define EF_LOCK_RD_LOCK_KEY_SLOT_0 (1 << 26)
+#define EF_LOCK_RD_LOCK_DBG_PWD (1 << 25)
+#define EF_LOCK_WR_LOCK_KEY_SLOT_5_H (1 << 24)
+#define EF_LOCK_WR_LOCK_KEY_SLOT_4_H (1 << 23)
+#define EF_LOCK_WR_LOCK_KEY_SLOT_3 (1 << 22)
+#define EF_LOCK_WR_LOCK_KEY_SLOT_2 (1 << 21)
+#define EF_LOCK_WR_LOCK_KEY_SLOT_1 (1 << 20)
+#define EF_LOCK_WR_LOCK_KEY_SLOT_0 (1 << 19)
+#define EF_LOCK_WR_LOCK_WIFI_MAC (1 << 18)
+#define EF_LOCK_WR_LOCK_SW_USAGE_0 (1 << 17)
+#define EF_LOCK_WR_LOCK_DBG_PWD (1 << 16)
+#define EF_LOCK_WR_LOCK_BOOT_MODE (1 << 15)
+#define EF_LOCK_WR_LOCK_KEY_SLOT_5_L (1 << 14)
+#define EF_LOCK_WR_LOCK_KEY_SLOT_4_L (1 << 13)
+#define EF_LOCK_EF_ANA_TRIM_1_MASK (0x1fff)
+
+#define EF_DATA_1_REG_DATA_1_LOCK_RD_LOCK_KEY_SLOT_9 (1 << 29)
+#define EF_DATA_1_REG_DATA_1_LOCK_RD_LOCK_KEY_SLOT_8 (1 << 28)
+#define EF_DATA_1_REG_DATA_1_LOCK_RD_LOCK_KEY_SLOT_7 (1 << 27)
+#define EF_DATA_1_REG_DATA_1_LOCK_RD_LOCK_KEY_SLOT_6 (1 << 26)
+#define EF_DATA_1_REG_DATA_1_LOCK_WR_LOCK_KEY_SLOT_9 (1 << 13)
+#define EF_DATA_1_REG_DATA_1_LOCK_WR_LOCK_KEY_SLOT_8 (1 << 12)
+#define EF_DATA_1_REG_DATA_1_LOCK_WR_LOCK_KEY_SLOT_7 (1 << 11)
+#define EF_DATA_1_REG_DATA_1_LOCK_WR_LOCK_KEY_SLOT_6 (1 << 10)
+
+#define EF_IF_CTRL_0_EF_IF_PROT_CODE_CYC_SHIFT (24)
+#define EF_IF_CTRL_0_EF_IF_PROT_CODE_CYC_MASK (0xff << EF_IF_CTRL_0_EF_IF_PROT_CODE_CYC_SHIFT)
+#define EF_IF_CTRL_0_EF_IF_0_INT_SET (1 << 22)
+#define EF_IF_CTRL_0_EF_IF_0_INT_CLR (1 << 21)
+#define EF_IF_CTRL_0_EF_IF_0_INT (1 << 20)
+#define EF_IF_CTRL_0_EF_IF_CYC_MODIFY_LOCK (1 << 19)
+#define EF_IF_CTRL_0_EF_IF_AUTO_RD_EN (1 << 18)
+#define EF_IF_CTRL_0_EF_CLK_SAHB_DATA_GATE (1 << 17)
+#define EF_IF_CTRL_0_EF_IF_POR_DIG (1 << 16)
+#define EF_IF_CTRL_0_EF_IF_PROT_CODE_CTRL_SHIFT (8)
+#define EF_IF_CTRL_0_EF_IF_PROT_CODE_CTRL_MASK (0xff << EF_IF_CTRL_0_EF_IF_PROT_CODE_CTRL_SHIFT)
+#define EF_IF_CTRL_0_EF_CLK_SAHB_DATA_SEL (1 << 7)
+#define EF_IF_CTRL_0_EF_IF_0_CYC_MODIFY (1 << 6)
+#define EF_IF_CTRL_0_EF_IF_0_MANUAL_EN (1 << 5)
+#define EF_IF_CTRL_0_EF_IF_0_TRIG (1 << 4)
+#define EF_IF_CTRL_0_EF_IF_0_RW (1 << 3)
+#define EF_IF_CTRL_0_EF_IF_0_BUSY (1 << 2)
+#define EF_IF_CTRL_0_EF_IF_0_AUTOLOAD_DONE (1 << 1)
+#define EF_IF_CTRL_0_EF_IF_0_AUTOLOAD_P1_DONE (1 << 0)
+
+#define EF_IF_CYC_0_EF_IF_CYC_PD_CS_S_SHIFT (24)
+#define EF_IF_CYC_0_EF_IF_CYC_PD_CS_S_MASK (0xff << EF_IF_CYC_0_EF_IF_CYC_PD_CS_S_SHIFT)
+#define EF_IF_CYC_0_EF_IF_CYC_CS_SHIFT (18)
+#define EF_IF_CYC_0_EF_IF_CYC_CS_MASK (0x3f << EF_IF_CYC_0_EF_IF_CYC_CS_SHIFT)
+#define EF_IF_CYC_0_EF_IF_CYC_RD_ADR_SHIFT (12)
+#define EF_IF_CYC_0_EF_IF_CYC_RD_ADR_MASK (0x3f << EF_IF_CYC_0_EF_IF_CYC_RD_ADR_SHIFT)
+#define EF_IF_CYC_0_EF_IF_CYC_RD_DAT_SHIFT (6)
+#define EF_IF_CYC_0_EF_IF_CYC_RD_DAT_MASK (0x3f << EF_IF_CYC_0_EF_IF_CYC_RD_DAT_SHIFT)
+#define EF_IF_CYC_0_EF_IF_CYC_RD_DMY_MASK (0x3f)
+
+#define EF_IF_CYC_1_EF_IF_CYC_PD_CS_H_SHIFT (26)
+#define EF_IF_CYC_1_EF_IF_CYC_PD_CS_H_MASK (0x3f << EF_IF_CYC_1_EF_IF_CYC_PD_CS_H_SHIFT)
+#define EF_IF_CYC_1_EF_IF_CYC_PS_CS_SHIFT (20)
+#define EF_IF_CYC_1_EF_IF_CYC_PS_CS_MASK (0x3f << EF_IF_CYC_1_EF_IF_CYC_PS_CS_SHIFT)
+#define EF_IF_CYC_1_EF_IF_CYC_WR_ADR_SHIFT (14)
+#define EF_IF_CYC_1_EF_IF_CYC_WR_ADR_MASK (0x3f << EF_IF_CYC_1_EF_IF_CYC_WR_ADR_SHIFT)
+#define EF_IF_CYC_1_EF_IF_CYC_PP_SHIFT (6)
+#define EF_IF_CYC_1_EF_IF_CYC_PP_MASK (0xff << EF_IF_CYC_1_EF_IF_CYC_PP_SHIFT)
+#define EF_IF_CYC_1_EF_IF_CYC_PI_MASK (0x3f)
+
+#define EF_IF_0_MANUAL_EF_IF_PROT_CODE_MANUAL_SHIFT (24)
+#define EF_IF_0_MANUAL_EF_IF_PROT_CODE_MANUAL_MASK (0xff << EF_IF_0_MANUAL_EF_IF_PROT_CODE_MANUAL_SHIFT)
+#define EF_IF_0_MANUAL_EF_IF_0_Q_SHIFT (16)
+#define EF_IF_0_MANUAL_EF_IF_0_Q_MASK (0xff << EF_IF_0_MANUAL_EF_IF_0_Q_SHIFT)
+#define EF_IF_0_MANUAL_EF_IF_CSB (1 << 15)
+#define EF_IF_0_MANUAL_EF_IF_LOAD (1 << 14)
+#define EF_IF_0_MANUAL_EF_IF_PGENB (1 << 13)
+#define EF_IF_0_MANUAL_EF_IF_STROBE (1 << 12)
+#define EF_IF_0_MANUAL_EF_IF_PS (1 << 11)
+#define EF_IF_0_MANUAL_EF_IF_PD (1 << 10)
+#define EF_IF_0_MANUAL_EF_IF_A_MASK (0x3ff)
+
+#define EF_IF_CFG_0_EF_IF_DBG_MODE_SHIFT (28)
+#define EF_IF_CFG_0_EF_IF_DBG_MODE_MASK (0x0f << EF_IF_CFG_0_EF_IF_DBG_MODE_SHIFT)
+#define EF_IF_CFG_0_EF_IF_DBG_JTAG_0_DIS_SHIFT (26)
+#define EF_IF_CFG_0_EF_IF_DBG_JTAG_0_DIS_MASK (0x03 << EF_IF_CFG_0_EF_IF_DBG_JTAG_0_DIS_SHIFT)
+#define EF_IF_CFG_0_EF_IF_DBG_JTAG_1_DIS_SHIFT (24)
+#define EF_IF_CFG_0_EF_IF_DBG_JTAG_1_DIS_MASK (0x03 << EF_IF_CFG_0_EF_IF_DBG_JTAG_1_DIS_SHIFT)
+#define EF_IF_CFG_0_EF_IF_EFUSE_DBG_DIS (1 << 23)
+#define EF_IF_CFG_0_EF_IF_SE_DBG_DIS (1 << 22)
+#define EF_IF_CFG_0_EF_IF_CPU_RST_DBG_DIS (1 << 21)
+#define EF_IF_CFG_0_EF_IF_CPU1_DIS (1 << 20)
+#define EF_IF_CFG_0_EF_IF_SF_DIS (1 << 19)
+#define EF_IF_CFG_0_EF_IF_CAM_DIS (1 << 18)
+#define EF_IF_CFG_0_EF_IF_0_KEY_ENC_EN (1 << 17)
+#define EF_IF_CFG_0_EF_IF_WIFI_DIS (1 << 16)
+#define EF_IF_CFG_0_EF_IF_BLE_DIS (1 << 15)
+#define EF_IF_CFG_0_EF_IF_SDU_DIS (1 << 14)
+#define EF_IF_CFG_0_EF_IF_SW_USAGE_1_SHIFT (12)
+#define EF_IF_CFG_0_EF_IF_SW_USAGE_1_MASK (0x03 << EF_IF_CFG_0_EF_IF_SW_USAGE_1_SHIFT)
+#define EF_IF_CFG_0_EF_IF_BOOT_SEL_SHIFT (8)
+#define EF_IF_CFG_0_EF_IF_BOOT_SEL_MASK (0x0f << EF_IF_CFG_0_EF_IF_BOOT_SEL_SHIFT)
+#define EF_IF_CFG_0_EF_IF_CPU0_ENC_EN (1 << 7)
+#define EF_IF_CFG_0_EF_IF_CPU1_ENC_EN (1 << 6)
+#define EF_IF_CFG_0_EF_IF_SBOOT_EN_SHIFT (4)
+#define EF_IF_CFG_0_EF_IF_SBOOT_EN_MASK (0x03 << EF_IF_CFG_0_EF_IF_SBOOT_EN_SHIFT)
+#define EF_IF_CFG_0_EF_IF_SBOOT_SIGN_MODE_SHIFT (2)
+#define EF_IF_CFG_0_EF_IF_SBOOT_SIGN_MODE_MASK (0x03 << EF_IF_CFG_0_EF_IF_SBOOT_SIGN_MODE_SHIFT)
+#define EF_IF_CFG_0_EF_IF_SF_AES_MODE_MASK (0x03)
+
+#define EF_SW_CFG_0_EF_SW_DBG_MODE_SHIFT (28)
+#define EF_SW_CFG_0_EF_SW_DBG_MODE_MASK (0x0f << EF_SW_CFG_0_EF_SW_DBG_MODE_SHIFT)
+#define EF_SW_CFG_0_EF_SW_DBG_JTAG_0_DIS_SHIFT (26)
+#define EF_SW_CFG_0_EF_SW_DBG_JTAG_0_DIS_MASK (0x03 << EF_SW_CFG_0_EF_SW_DBG_JTAG_0_DIS_SHIFT)
+#define EF_SW_CFG_0_EF_SW_DBG_JTAG_1_DIS_SHIFT (24)
+#define EF_SW_CFG_0_EF_SW_DBG_JTAG_1_DIS_MASK (0x03 << EF_SW_CFG_0_EF_SW_DBG_JTAG_1_DIS_SHIFT)
+#define EF_SW_CFG_0_EF_SW_EFUSE_DBG_DIS (1 << 23)
+#define EF_SW_CFG_0_EF_SW_SE_DBG_DIS (1 << 22)
+#define EF_SW_CFG_0_EF_SW_CPU_RST_DBG_DIS (1 << 21)
+#define EF_SW_CFG_0_EF_SW_CPU1_DIS (1 << 20)
+#define EF_SW_CFG_0_EF_SW_SF_DIS (1 << 19)
+#define EF_SW_CFG_0_EF_SW_CAM_DIS (1 << 18)
+#define EF_SW_CFG_0_EF_SW_0_KEY_ENC_EN (1 << 17)
+#define EF_SW_CFG_0_EF_SW_WIFI_DIS (1 << 16)
+#define EF_SW_CFG_0_EF_SW_BLE_DIS (1 << 15)
+#define EF_SW_CFG_0_EF_SW_SDU_DIS (1 << 14)
+#define EF_SW_CFG_0_EF_SW_SW_USAGE_1_SHIFT (12)
+#define EF_SW_CFG_0_EF_SW_SW_USAGE_1_MASK (0x03 << EF_SW_CFG_0_EF_SW_SW_USAGE_1_SHIFT)
+#define EF_SW_CFG_0_EF_SW_CPU0_ENC_EN (1 << 7)
+#define EF_SW_CFG_0_EF_SW_CPU1_ENC_EN (1 << 6)
+#define EF_SW_CFG_0_EF_SW_SBOOT_EN_SHIFT (4)
+#define EF_SW_CFG_0_EF_SW_SBOOT_EN_MASK (0x03 << EF_SW_CFG_0_EF_SW_SBOOT_EN_SHIFT)
+#define EF_SW_CFG_0_EF_SW_SBOOT_SIGN_MODE_SHIFT (2)
+#define EF_SW_CFG_0_EF_SW_SBOOT_SIGN_MODE_MASK (0x03 << EF_SW_CFG_0_EF_SW_SBOOT_SIGN_MODE_SHIFT)
+#define EF_SW_CFG_0_EF_SW_SF_AES_MODE_MASK (0x03)
+
+#define EF_CRC_CTRL_0_EF_CRC_SLP_N_SHIFT (16)
+#define EF_CRC_CTRL_0_EF_CRC_SLP_N_MASK (0xffff << EF_CRC_CTRL_0_EF_CRC_SLP_N_SHIFT)
+#define EF_CRC_CTRL_0_EF_CRC_LOCK (1 << 11)
+#define EF_CRC_CTRL_0_EF_CRC_INT_SET (1 << 10)
+#define EF_CRC_CTRL_0_EF_CRC_INT_CLR (1 << 9)
+#define EF_CRC_CTRL_0_EF_CRC_INT (1 << 8)
+#define EF_CRC_CTRL_0_EF_CRC_DIN_ENDIAN (1 << 7)
+#define EF_CRC_CTRL_0_EF_CRC_DOUT_ENDIAN (1 << 6)
+#define EF_CRC_CTRL_0_EF_CRC_DOUT_INV_EN (1 << 5)
+#define EF_CRC_CTRL_0_EF_CRC_ERROR (1 << 4)
+#define EF_CRC_CTRL_0_EF_CRC_MODE (1 << 3)
+#define EF_CRC_CTRL_0_EF_CRC_EN (1 << 2)
+#define EF_CRC_CTRL_0_EF_CRC_TRIG (1 << 1)
+#define EF_CRC_CTRL_0_EF_CRC_BUSY (1 << 0)
+
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_EF_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_glb.h b/arch/risc-v/src/bl602/hardware/bl602_glb.h
index 00ce876..2d19cc7 100644
--- a/arch/risc-v/src/bl602/hardware/bl602_glb.h
+++ b/arch/risc-v/src/bl602/hardware/bl602_glb.h
@@ -25,4243 +25,828 @@
* Included Files
****************************************************************************/
-#include "hardware/bl602_common.h"
+#include <nuttx/config.h>
+#include "bl602_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-/* 0x0 : clk_cfg0 */
-
-#define GLB_CLK_CFG0_OFFSET (0x0)
-#define GLB_REG_PLL_EN GLB_REG_PLL_EN
-#define GLB_REG_PLL_EN_POS (0)
-#define GLB_REG_PLL_EN_LEN (1)
-#define GLB_REG_PLL_EN_MSK \
- (((1 << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
-#define GLB_REG_PLL_EN_UMSK \
- (~(((1 << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
-#define GLB_REG_FCLK_EN GLB_REG_FCLK_EN
-#define GLB_REG_FCLK_EN_POS (1)
-#define GLB_REG_FCLK_EN_LEN (1)
-#define GLB_REG_FCLK_EN_MSK \
- (((1 << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
-#define GLB_REG_FCLK_EN_UMSK \
- (~(((1 << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
-#define GLB_REG_HCLK_EN GLB_REG_HCLK_EN
-#define GLB_REG_HCLK_EN_POS (2)
-#define GLB_REG_HCLK_EN_LEN (1)
-#define GLB_REG_HCLK_EN_MSK \
- (((1 << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
-#define GLB_REG_HCLK_EN_UMSK \
- (~(((1 << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
-#define GLB_REG_BCLK_EN GLB_REG_BCLK_EN
-#define GLB_REG_BCLK_EN_POS (3)
-#define GLB_REG_BCLK_EN_LEN (1)
-#define GLB_REG_BCLK_EN_MSK \
- (((1 << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
-#define GLB_REG_BCLK_EN_UMSK \
- (~(((1 << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
-#define GLB_REG_PLL_SEL GLB_REG_PLL_SEL
-#define GLB_REG_PLL_SEL_POS (4)
-#define GLB_REG_PLL_SEL_LEN (2)
-#define GLB_REG_PLL_SEL_MSK \
- (((1 << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)
-#define GLB_REG_PLL_SEL_UMSK \
- (~(((1 << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS))
-#define GLB_HBN_ROOT_CLK_SEL GLB_HBN_ROOT_CLK_SEL
-#define GLB_HBN_ROOT_CLK_SEL_POS (6)
-#define GLB_HBN_ROOT_CLK_SEL_LEN (2)
-#define GLB_HBN_ROOT_CLK_SEL_MSK \
- (((1 << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
-#define GLB_HBN_ROOT_CLK_SEL_UMSK \
- (~(((1 << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
-#define GLB_REG_HCLK_DIV GLB_REG_HCLK_DIV
-#define GLB_REG_HCLK_DIV_POS (8)
-#define GLB_REG_HCLK_DIV_LEN (8)
-#define GLB_REG_HCLK_DIV_MSK \
- (((1 << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
-#define GLB_REG_HCLK_DIV_UMSK \
- (~(((1 << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
-#define GLB_REG_BCLK_DIV GLB_REG_BCLK_DIV
-#define GLB_REG_BCLK_DIV_POS (16)
-#define GLB_REG_BCLK_DIV_LEN (8)
-#define GLB_REG_BCLK_DIV_MSK \
- (((1 << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
-#define GLB_REG_BCLK_DIV_UMSK \
- (~(((1 << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
-#define GLB_FCLK_SW_STATE GLB_FCLK_SW_STATE
-#define GLB_FCLK_SW_STATE_POS (24)
-#define GLB_FCLK_SW_STATE_LEN (3)
-#define GLB_FCLK_SW_STATE_MSK \
- (((1 << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
-#define GLB_FCLK_SW_STATE_UMSK \
- (~(((1 << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
-#define GLB_CHIP_RDY GLB_CHIP_RDY
-#define GLB_CHIP_RDY_POS (27)
-#define GLB_CHIP_RDY_LEN (1)
-#define GLB_CHIP_RDY_MSK (((1 << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
-#define GLB_CHIP_RDY_UMSK \
- (~(((1 << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
-#define GLB_ID GLB_ID
-#define GLB_ID_POS (28)
-#define GLB_ID_LEN (4)
-#define GLB_ID_MSK (((1 << GLB_ID_LEN) - 1) << GLB_ID_POS)
-#define GLB_ID_UMSK (~(((1 << GLB_ID_LEN) - 1) << GLB_ID_POS))
-
-/* 0x4 : clk_cfg1 */
-
-#define GLB_CLK_CFG1_OFFSET (0x4)
-#define GLB_WIFI_MAC_CORE_DIV GLB_WIFI_MAC_CORE_DIV
-#define GLB_WIFI_MAC_CORE_DIV_POS (0)
-#define GLB_WIFI_MAC_CORE_DIV_LEN (4)
-#define GLB_WIFI_MAC_CORE_DIV_MSK \
- (((1 << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)
-#define GLB_WIFI_MAC_CORE_DIV_UMSK \
- (~(((1 << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS))
-#define GLB_WIFI_MAC_WT_DIV GLB_WIFI_MAC_WT_DIV
-#define GLB_WIFI_MAC_WT_DIV_POS (4)
-#define GLB_WIFI_MAC_WT_DIV_LEN (4)
-#define GLB_WIFI_MAC_WT_DIV_MSK \
- (((1 << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)
-#define GLB_WIFI_MAC_WT_DIV_UMSK \
- (~(((1 << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS))
-#define GLB_BLE_CLK_SEL GLB_BLE_CLK_SEL
-#define GLB_BLE_CLK_SEL_POS (16)
-#define GLB_BLE_CLK_SEL_LEN (6)
-#define GLB_BLE_CLK_SEL_MSK \
- (((1 << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)
-#define GLB_BLE_CLK_SEL_UMSK \
- (~(((1 << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS))
-#define GLB_BLE_EN GLB_BLE_EN
-#define GLB_BLE_EN_POS (24)
-#define GLB_BLE_EN_LEN (1)
-#define GLB_BLE_EN_MSK (((1 << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)
-#define GLB_BLE_EN_UMSK (~(((1 << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS))
-
-/* 0x8 : clk_cfg2 */
-
-#define GLB_CLK_CFG2_OFFSET (0x8)
-#define GLB_UART_CLK_DIV GLB_UART_CLK_DIV
-#define GLB_UART_CLK_DIV_POS (0)
-#define GLB_UART_CLK_DIV_LEN (3)
-#define GLB_UART_CLK_DIV_MSK \
- (((1 << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
-#define GLB_UART_CLK_DIV_UMSK \
- (~(((1 << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
-#define GLB_UART_CLK_EN GLB_UART_CLK_EN
-#define GLB_UART_CLK_EN_POS (4)
-#define GLB_UART_CLK_EN_LEN (1)
-#define GLB_UART_CLK_EN_MSK \
- (((1 << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
-#define GLB_UART_CLK_EN_UMSK \
- (~(((1 << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
-#define GLB_HBN_UART_CLK_SEL GLB_HBN_UART_CLK_SEL
-#define GLB_HBN_UART_CLK_SEL_POS (7)
-#define GLB_HBN_UART_CLK_SEL_LEN (1)
-#define GLB_HBN_UART_CLK_SEL_MSK \
- (((1 << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
-#define GLB_HBN_UART_CLK_SEL_UMSK \
- (~(((1 << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
-#define GLB_SF_CLK_DIV GLB_SF_CLK_DIV
-#define GLB_SF_CLK_DIV_POS (8)
-#define GLB_SF_CLK_DIV_LEN (3)
-#define GLB_SF_CLK_DIV_MSK \
- (((1 << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
-#define GLB_SF_CLK_DIV_UMSK \
- (~(((1 << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
-#define GLB_SF_CLK_EN GLB_SF_CLK_EN
-#define GLB_SF_CLK_EN_POS (11)
-#define GLB_SF_CLK_EN_LEN (1)
-#define GLB_SF_CLK_EN_MSK \
- (((1 << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
-#define GLB_SF_CLK_EN_UMSK \
- (~(((1 << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
-#define GLB_SF_CLK_SEL GLB_SF_CLK_SEL
-#define GLB_SF_CLK_SEL_POS (12)
-#define GLB_SF_CLK_SEL_LEN (2)
-#define GLB_SF_CLK_SEL_MSK \
- (((1 << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
-#define GLB_SF_CLK_SEL_UMSK \
- (~(((1 << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
-#define GLB_SF_CLK_SEL2 GLB_SF_CLK_SEL2
-#define GLB_SF_CLK_SEL2_POS (14)
-#define GLB_SF_CLK_SEL2_LEN (2)
-#define GLB_SF_CLK_SEL2_MSK \
- (((1 << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
-#define GLB_SF_CLK_SEL2_UMSK \
- (~(((1 << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
-#define GLB_IR_CLK_DIV GLB_IR_CLK_DIV
-#define GLB_IR_CLK_DIV_POS (16)
-#define GLB_IR_CLK_DIV_LEN (6)
-#define GLB_IR_CLK_DIV_MSK \
- (((1 << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
-#define GLB_IR_CLK_DIV_UMSK \
- (~(((1 << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
-#define GLB_IR_CLK_EN GLB_IR_CLK_EN
-#define GLB_IR_CLK_EN_POS (23)
-#define GLB_IR_CLK_EN_LEN (1)
-#define GLB_IR_CLK_EN_MSK \
- (((1 << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
-#define GLB_IR_CLK_EN_UMSK \
- (~(((1 << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
-#define GLB_DMA_CLK_EN GLB_DMA_CLK_EN
-#define GLB_DMA_CLK_EN_POS (24)
-#define GLB_DMA_CLK_EN_LEN (8)
-#define GLB_DMA_CLK_EN_MSK \
- (((1 << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
-#define GLB_DMA_CLK_EN_UMSK \
- (~(((1 << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
-
-/* 0xC : clk_cfg3 */
-
-#define GLB_CLK_CFG3_OFFSET (0xC)
-#define GLB_SPI_CLK_DIV GLB_SPI_CLK_DIV
-#define GLB_SPI_CLK_DIV_POS (0)
-#define GLB_SPI_CLK_DIV_LEN (5)
-#define GLB_SPI_CLK_DIV_MSK \
- (((1 << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
-#define GLB_SPI_CLK_DIV_UMSK \
- (~(((1 << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
-#define GLB_SPI_CLK_EN GLB_SPI_CLK_EN
-#define GLB_SPI_CLK_EN_POS (8)
-#define GLB_SPI_CLK_EN_LEN (1)
-#define GLB_SPI_CLK_EN_MSK \
- (((1 << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
-#define GLB_SPI_CLK_EN_UMSK \
- (~(((1 << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
-#define GLB_I2C_CLK_DIV GLB_I2C_CLK_DIV
-#define GLB_I2C_CLK_DIV_POS (16)
-#define GLB_I2C_CLK_DIV_LEN (8)
-#define GLB_I2C_CLK_DIV_MSK \
- (((1 << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
-#define GLB_I2C_CLK_DIV_UMSK \
- (~(((1 << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
-#define GLB_I2C_CLK_EN GLB_I2C_CLK_EN
-#define GLB_I2C_CLK_EN_POS (24)
-#define GLB_I2C_CLK_EN_LEN (1)
-#define GLB_I2C_CLK_EN_MSK \
- (((1 << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
-#define GLB_I2C_CLK_EN_UMSK \
- (~(((1 << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
-
-/* 0x10 : swrst_cfg0 */
-
-#define GLB_SWRST_CFG0_OFFSET (0x10)
-#define GLB_SWRST_S00 GLB_SWRST_S00
-#define GLB_SWRST_S00_POS (0)
-#define GLB_SWRST_S00_LEN (1)
-#define GLB_SWRST_S00_MSK \
- (((1 << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
-#define GLB_SWRST_S00_UMSK \
- (~(((1 << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
-#define GLB_SWRST_S01 GLB_SWRST_S01
-#define GLB_SWRST_S01_POS (1)
-#define GLB_SWRST_S01_LEN (1)
-#define GLB_SWRST_S01_MSK \
- (((1 << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
-#define GLB_SWRST_S01_UMSK \
- (~(((1 << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
-#define GLB_SWRST_S20 GLB_SWRST_S20
-#define GLB_SWRST_S20_POS (4)
-#define GLB_SWRST_S20_LEN (1)
-#define GLB_SWRST_S20_MSK \
- (((1 << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
-#define GLB_SWRST_S20_UMSK \
- (~(((1 << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
-#define GLB_SWRST_S30 GLB_SWRST_S30
-#define GLB_SWRST_S30_POS (8)
-#define GLB_SWRST_S30_LEN (1)
-#define GLB_SWRST_S30_MSK \
- (((1 << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
-#define GLB_SWRST_S30_UMSK \
- (~(((1 << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
-
-/* 0x14 : swrst_cfg1 */
-
-#define GLB_SWRST_CFG1_OFFSET (0x14)
-#define GLB_SWRST_S10 GLB_SWRST_S10
-#define GLB_SWRST_S10_POS (0)
-#define GLB_SWRST_S10_LEN (1)
-#define GLB_SWRST_S10_MSK \
- (((1 << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
-#define GLB_SWRST_S10_UMSK \
- (~(((1 << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
-#define GLB_SWRST_S11 GLB_SWRST_S11
-#define GLB_SWRST_S11_POS (1)
-#define GLB_SWRST_S11_LEN (1)
-#define GLB_SWRST_S11_MSK \
- (((1 << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
-#define GLB_SWRST_S11_UMSK \
- (~(((1 << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
-#define GLB_SWRST_S12 GLB_SWRST_S12
-#define GLB_SWRST_S12_POS (2)
-#define GLB_SWRST_S12_LEN (1)
-#define GLB_SWRST_S12_MSK \
- (((1 << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
-#define GLB_SWRST_S12_UMSK \
- (~(((1 << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
-#define GLB_SWRST_S13 GLB_SWRST_S13
-#define GLB_SWRST_S13_POS (3)
-#define GLB_SWRST_S13_LEN (1)
-#define GLB_SWRST_S13_MSK \
- (((1 << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
-#define GLB_SWRST_S13_UMSK \
- (~(((1 << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
-#define GLB_SWRST_S14 GLB_SWRST_S14
-#define GLB_SWRST_S14_POS (4)
-#define GLB_SWRST_S14_LEN (1)
-#define GLB_SWRST_S14_MSK \
- (((1 << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
-#define GLB_SWRST_S14_UMSK \
- (~(((1 << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
-#define GLB_SWRST_S15 GLB_SWRST_S15
-#define GLB_SWRST_S15_POS (5)
-#define GLB_SWRST_S15_LEN (1)
-#define GLB_SWRST_S15_MSK \
- (((1 << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
-#define GLB_SWRST_S15_UMSK \
- (~(((1 << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
-#define GLB_SWRST_S16 GLB_SWRST_S16
-#define GLB_SWRST_S16_POS (6)
-#define GLB_SWRST_S16_LEN (1)
-#define GLB_SWRST_S16_MSK \
- (((1 << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
-#define GLB_SWRST_S16_UMSK \
- (~(((1 << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
-#define GLB_SWRST_S17 GLB_SWRST_S17
-#define GLB_SWRST_S17_POS (7)
-#define GLB_SWRST_S17_LEN (1)
-#define GLB_SWRST_S17_MSK \
- (((1 << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
-#define GLB_SWRST_S17_UMSK \
- (~(((1 << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
-#define GLB_SWRST_S18 GLB_SWRST_S18
-#define GLB_SWRST_S18_POS (8)
-#define GLB_SWRST_S18_LEN (1)
-#define GLB_SWRST_S18_MSK \
- (((1 << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
-#define GLB_SWRST_S18_UMSK \
- (~(((1 << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
-#define GLB_SWRST_S19 GLB_SWRST_S19
-#define GLB_SWRST_S19_POS (9)
-#define GLB_SWRST_S19_LEN (1)
-#define GLB_SWRST_S19_MSK \
- (((1 << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
-#define GLB_SWRST_S19_UMSK \
- (~(((1 << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
-#define GLB_SWRST_S1A GLB_SWRST_S1A
-#define GLB_SWRST_S1A_POS (10)
-#define GLB_SWRST_S1A_LEN (1)
-#define GLB_SWRST_S1A_MSK \
- (((1 << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
-#define GLB_SWRST_S1A_UMSK \
- (~(((1 << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
-#define GLB_SWRST_S1B GLB_SWRST_S1B
-#define GLB_SWRST_S1B_POS (11)
-#define GLB_SWRST_S1B_LEN (1)
-#define GLB_SWRST_S1B_MSK \
- (((1 << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
-#define GLB_SWRST_S1B_UMSK \
- (~(((1 << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
-#define GLB_SWRST_S1C GLB_SWRST_S1C
-#define GLB_SWRST_S1C_POS (12)
-#define GLB_SWRST_S1C_LEN (1)
-#define GLB_SWRST_S1C_MSK \
- (((1 << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
-#define GLB_SWRST_S1C_UMSK \
- (~(((1 << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
-#define GLB_SWRST_S1D GLB_SWRST_S1D
-#define GLB_SWRST_S1D_POS (13)
-#define GLB_SWRST_S1D_LEN (1)
-#define GLB_SWRST_S1D_MSK \
- (((1 << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
-#define GLB_SWRST_S1D_UMSK \
- (~(((1 << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
-#define GLB_SWRST_S1E GLB_SWRST_S1E
-#define GLB_SWRST_S1E_POS (14)
-#define GLB_SWRST_S1E_LEN (1)
-#define GLB_SWRST_S1E_MSK \
- (((1 << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
-#define GLB_SWRST_S1E_UMSK \
- (~(((1 << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
-#define GLB_SWRST_S1F GLB_SWRST_S1F
-#define GLB_SWRST_S1F_POS (15)
-#define GLB_SWRST_S1F_LEN (1)
-#define GLB_SWRST_S1F_MSK \
- (((1 << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
-#define GLB_SWRST_S1F_UMSK \
- (~(((1 << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
-#define GLB_SWRST_S1A0 GLB_SWRST_S1A0
-#define GLB_SWRST_S1A0_POS (16)
-#define GLB_SWRST_S1A0_LEN (1)
-#define GLB_SWRST_S1A0_MSK \
- (((1 << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
-#define GLB_SWRST_S1A0_UMSK \
- (~(((1 << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
-#define GLB_SWRST_S1A1 GLB_SWRST_S1A1
-#define GLB_SWRST_S1A1_POS (17)
-#define GLB_SWRST_S1A1_LEN (1)
-#define GLB_SWRST_S1A1_MSK \
- (((1 << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
-#define GLB_SWRST_S1A1_UMSK \
- (~(((1 << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
-#define GLB_SWRST_S1A2 GLB_SWRST_S1A2
-#define GLB_SWRST_S1A2_POS (18)
-#define GLB_SWRST_S1A2_LEN (1)
-#define GLB_SWRST_S1A2_MSK \
- (((1 << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
-#define GLB_SWRST_S1A2_UMSK \
- (~(((1 << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
-#define GLB_SWRST_S1A3 GLB_SWRST_S1A3
-#define GLB_SWRST_S1A3_POS (19)
-#define GLB_SWRST_S1A3_LEN (1)
-#define GLB_SWRST_S1A3_MSK \
- (((1 << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
-#define GLB_SWRST_S1A3_UMSK \
- (~(((1 << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
-#define GLB_SWRST_S1A4 GLB_SWRST_S1A4
-#define GLB_SWRST_S1A4_POS (20)
-#define GLB_SWRST_S1A4_LEN (1)
-#define GLB_SWRST_S1A4_MSK \
- (((1 << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
-#define GLB_SWRST_S1A4_UMSK \
- (~(((1 << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
-#define GLB_SWRST_S1A5 GLB_SWRST_S1A5
-#define GLB_SWRST_S1A5_POS (21)
-#define GLB_SWRST_S1A5_LEN (1)
-#define GLB_SWRST_S1A5_MSK \
- (((1 << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
-#define GLB_SWRST_S1A5_UMSK \
- (~(((1 << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
-#define GLB_SWRST_S1A6 GLB_SWRST_S1A6
-#define GLB_SWRST_S1A6_POS (22)
-#define GLB_SWRST_S1A6_LEN (1)
-#define GLB_SWRST_S1A6_MSK \
- (((1 << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
-#define GLB_SWRST_S1A6_UMSK \
- (~(((1 << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
-#define GLB_SWRST_S1A7 GLB_SWRST_S1A7
-#define GLB_SWRST_S1A7_POS (23)
-#define GLB_SWRST_S1A7_LEN (1)
-#define GLB_SWRST_S1A7_MSK \
- (((1 << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
-#define GLB_SWRST_S1A7_UMSK \
- (~(((1 << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
-
-/* 0x18 : swrst_cfg2 */
-
-#define GLB_SWRST_CFG2_OFFSET (0x18)
-#define GLB_REG_CTRL_PWRON_RST GLB_REG_CTRL_PWRON_RST
-#define GLB_REG_CTRL_PWRON_RST_POS (0)
-#define GLB_REG_CTRL_PWRON_RST_LEN (1)
-#define GLB_REG_CTRL_PWRON_RST_MSK \
- (((1 << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
-#define GLB_REG_CTRL_PWRON_RST_UMSK \
- (~(((1 << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
-#define GLB_REG_CTRL_CPU_RESET GLB_REG_CTRL_CPU_RESET
-#define GLB_REG_CTRL_CPU_RESET_POS (1)
-#define GLB_REG_CTRL_CPU_RESET_LEN (1)
-#define GLB_REG_CTRL_CPU_RESET_MSK \
- (((1 << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
-#define GLB_REG_CTRL_CPU_RESET_UMSK \
- (~(((1 << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
-#define GLB_REG_CTRL_SYS_RESET GLB_REG_CTRL_SYS_RESET
-#define GLB_REG_CTRL_SYS_RESET_POS (2)
-#define GLB_REG_CTRL_SYS_RESET_LEN (1)
-#define GLB_REG_CTRL_SYS_RESET_MSK \
- (((1 << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
-#define GLB_REG_CTRL_SYS_RESET_UMSK \
- (~(((1 << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
-#define GLB_REG_CTRL_RESET_DUMMY GLB_REG_CTRL_RESET_DUMMY
-#define GLB_REG_CTRL_RESET_DUMMY_POS (4)
-#define GLB_REG_CTRL_RESET_DUMMY_LEN (4)
-#define GLB_REG_CTRL_RESET_DUMMY_MSK \
- (((1 << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
-#define GLB_REG_CTRL_RESET_DUMMY_UMSK \
- (~(((1 << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) \
- << GLB_REG_CTRL_RESET_DUMMY_POS))
-#define GLB_PKA_CLK_SEL GLB_PKA_CLK_SEL
-#define GLB_PKA_CLK_SEL_POS (24)
-#define GLB_PKA_CLK_SEL_LEN (1)
-#define GLB_PKA_CLK_SEL_MSK \
- (((1 << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
-#define GLB_PKA_CLK_SEL_UMSK \
- (~(((1 << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
-
-/* 0x1C : swrst_cfg3 */
-
-#define GLB_SWRST_CFG3_OFFSET (0x1C)
-
-/* 0x20 : cgen_cfg0 */
-
-#define GLB_CGEN_CFG0_OFFSET (0x20)
-#define GLB_CGEN_M GLB_CGEN_M
-#define GLB_CGEN_M_POS (0)
-#define GLB_CGEN_M_LEN (8)
-#define GLB_CGEN_M_MSK (((1 << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)
-#define GLB_CGEN_M_UMSK (~(((1 << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS))
-
-/* 0x24 : cgen_cfg1 */
-
-#define GLB_CGEN_CFG1_OFFSET (0x24)
-#define GLB_CGEN_S1 GLB_CGEN_S1
-#define GLB_CGEN_S1_POS (0)
-#define GLB_CGEN_S1_LEN (16)
-#define GLB_CGEN_S1_MSK (((1 << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)
-#define GLB_CGEN_S1_UMSK (~(((1 << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS))
-#define GLB_CGEN_S1A GLB_CGEN_S1A
-#define GLB_CGEN_S1A_POS (16)
-#define GLB_CGEN_S1A_LEN (8)
-#define GLB_CGEN_S1A_MSK (((1 << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)
-#define GLB_CGEN_S1A_UMSK \
- (~(((1 << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS))
-
-/* 0x28 : cgen_cfg2 */
-
-#define GLB_CGEN_CFG2_OFFSET (0x28)
-#define GLB_CGEN_S2 GLB_CGEN_S2
-#define GLB_CGEN_S2_POS (0)
-#define GLB_CGEN_S2_LEN (1)
-#define GLB_CGEN_S2_MSK (((1 << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)
-#define GLB_CGEN_S2_UMSK (~(((1 << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS))
-#define GLB_CGEN_S3 GLB_CGEN_S3
-#define GLB_CGEN_S3_POS (4)
-#define GLB_CGEN_S3_LEN (1)
-#define GLB_CGEN_S3_MSK (((1 << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)
-#define GLB_CGEN_S3_UMSK (~(((1 << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS))
-
-/* 0x2C : cgen_cfg3 */
-
-#define GLB_CGEN_CFG3_OFFSET (0x2C)
-
-/* 0x30 : MBIST_CTL */
-
-#define GLB_MBIST_CTL_OFFSET (0x30)
-#define GLB_IROM_MBIST_MODE GLB_IROM_MBIST_MODE
-#define GLB_IROM_MBIST_MODE_POS (0)
-#define GLB_IROM_MBIST_MODE_LEN (1)
-#define GLB_IROM_MBIST_MODE_MSK \
- (((1 << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)
-#define GLB_IROM_MBIST_MODE_UMSK \
- (~(((1 << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS))
-#define GLB_HSRAM_MBIST_MODE GLB_HSRAM_MBIST_MODE
-#define GLB_HSRAM_MBIST_MODE_POS (1)
-#define GLB_HSRAM_MBIST_MODE_LEN (1)
-#define GLB_HSRAM_MBIST_MODE_MSK \
- (((1 << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)
-#define GLB_HSRAM_MBIST_MODE_UMSK \
- (~(((1 << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS))
-#define GLB_TAG_MBIST_MODE GLB_TAG_MBIST_MODE
-#define GLB_TAG_MBIST_MODE_POS (2)
-#define GLB_TAG_MBIST_MODE_LEN (1)
-#define GLB_TAG_MBIST_MODE_MSK \
- (((1 << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)
-#define GLB_TAG_MBIST_MODE_UMSK \
- (~(((1 << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS))
-#define GLB_OCRAM_MBIST_MODE GLB_OCRAM_MBIST_MODE
-#define GLB_OCRAM_MBIST_MODE_POS (3)
-#define GLB_OCRAM_MBIST_MODE_LEN (1)
-#define GLB_OCRAM_MBIST_MODE_MSK \
- (((1 << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
-#define GLB_OCRAM_MBIST_MODE_UMSK \
- (~(((1 << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
-#define GLB_WIFI_MBIST_MODE GLB_WIFI_MBIST_MODE
-#define GLB_WIFI_MBIST_MODE_POS (4)
-#define GLB_WIFI_MBIST_MODE_LEN (1)
-#define GLB_WIFI_MBIST_MODE_MSK \
- (((1 << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)
-#define GLB_WIFI_MBIST_MODE_UMSK \
- (~(((1 << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS))
-#define GLB_REG_MBIST_RST_N GLB_REG_MBIST_RST_N
-#define GLB_REG_MBIST_RST_N_POS (31)
-#define GLB_REG_MBIST_RST_N_LEN (1)
-#define GLB_REG_MBIST_RST_N_MSK \
- (((1 << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)
-#define GLB_REG_MBIST_RST_N_UMSK \
- (~(((1 << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS))
-
-/* 0x34 : MBIST_STAT */
-
-#define GLB_MBIST_STAT_OFFSET (0x34)
-#define GLB_IROM_MBIST_DONE GLB_IROM_MBIST_DONE
-#define GLB_IROM_MBIST_DONE_POS (0)
-#define GLB_IROM_MBIST_DONE_LEN (1)
-#define GLB_IROM_MBIST_DONE_MSK \
- (((1 << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)
-#define GLB_IROM_MBIST_DONE_UMSK \
- (~(((1 << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS))
-#define GLB_HSRAM_MBIST_DONE GLB_HSRAM_MBIST_DONE
-#define GLB_HSRAM_MBIST_DONE_POS (1)
-#define GLB_HSRAM_MBIST_DONE_LEN (1)
-#define GLB_HSRAM_MBIST_DONE_MSK \
- (((1 << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)
-#define GLB_HSRAM_MBIST_DONE_UMSK \
- (~(((1 << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS))
-#define GLB_TAG_MBIST_DONE GLB_TAG_MBIST_DONE
-#define GLB_TAG_MBIST_DONE_POS (2)
-#define GLB_TAG_MBIST_DONE_LEN (1)
-#define GLB_TAG_MBIST_DONE_MSK \
- (((1 << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)
-#define GLB_TAG_MBIST_DONE_UMSK \
- (~(((1 << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS))
-#define GLB_OCRAM_MBIST_DONE GLB_OCRAM_MBIST_DONE
-#define GLB_OCRAM_MBIST_DONE_POS (3)
-#define GLB_OCRAM_MBIST_DONE_LEN (1)
-#define GLB_OCRAM_MBIST_DONE_MSK \
- (((1 << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
-#define GLB_OCRAM_MBIST_DONE_UMSK \
- (~(((1 << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
-#define GLB_WIFI_MBIST_DONE GLB_WIFI_MBIST_DONE
-#define GLB_WIFI_MBIST_DONE_POS (4)
-#define GLB_WIFI_MBIST_DONE_LEN (1)
-#define GLB_WIFI_MBIST_DONE_MSK \
- (((1 << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)
-#define GLB_WIFI_MBIST_DONE_UMSK \
- (~(((1 << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS))
-#define GLB_IROM_MBIST_FAIL GLB_IROM_MBIST_FAIL
-#define GLB_IROM_MBIST_FAIL_POS (16)
-#define GLB_IROM_MBIST_FAIL_LEN (1)
-#define GLB_IROM_MBIST_FAIL_MSK \
- (((1 << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)
-#define GLB_IROM_MBIST_FAIL_UMSK \
- (~(((1 << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS))
-#define GLB_HSRAM_MBIST_FAIL GLB_HSRAM_MBIST_FAIL
-#define GLB_HSRAM_MBIST_FAIL_POS (17)
-#define GLB_HSRAM_MBIST_FAIL_LEN (1)
-#define GLB_HSRAM_MBIST_FAIL_MSK \
- (((1 << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)
-#define GLB_HSRAM_MBIST_FAIL_UMSK \
- (~(((1 << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS))
-#define GLB_TAG_MBIST_FAIL GLB_TAG_MBIST_FAIL
-#define GLB_TAG_MBIST_FAIL_POS (18)
-#define GLB_TAG_MBIST_FAIL_LEN (1)
-#define GLB_TAG_MBIST_FAIL_MSK \
- (((1 << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)
-#define GLB_TAG_MBIST_FAIL_UMSK \
- (~(((1 << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS))
-#define GLB_OCRAM_MBIST_FAIL GLB_OCRAM_MBIST_FAIL
-#define GLB_OCRAM_MBIST_FAIL_POS (19)
-#define GLB_OCRAM_MBIST_FAIL_LEN (1)
-#define GLB_OCRAM_MBIST_FAIL_MSK \
- (((1 << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
-#define GLB_OCRAM_MBIST_FAIL_UMSK \
- (~(((1 << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
-#define GLB_WIFI_MBIST_FAIL GLB_WIFI_MBIST_FAIL
-#define GLB_WIFI_MBIST_FAIL_POS (20)
-#define GLB_WIFI_MBIST_FAIL_LEN (1)
-#define GLB_WIFI_MBIST_FAIL_MSK \
- (((1 << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)
-#define GLB_WIFI_MBIST_FAIL_UMSK \
- (~(((1 << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS))
-
-/* 0x50 : bmx_cfg1 */
-
-#define GLB_BMX_CFG1_OFFSET (0x50)
-#define GLB_BMX_TIMEOUT_EN GLB_BMX_TIMEOUT_EN
-#define GLB_BMX_TIMEOUT_EN_POS (0)
-#define GLB_BMX_TIMEOUT_EN_LEN (4)
-#define GLB_BMX_TIMEOUT_EN_MSK \
- (((1 << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)
-#define GLB_BMX_TIMEOUT_EN_UMSK \
- (~(((1 << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS))
-#define GLB_BMX_ARB_MODE GLB_BMX_ARB_MODE
-#define GLB_BMX_ARB_MODE_POS (4)
-#define GLB_BMX_ARB_MODE_LEN (2)
-#define GLB_BMX_ARB_MODE_MSK \
- (((1 << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)
-#define GLB_BMX_ARB_MODE_UMSK \
- (~(((1 << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS))
-#define GLB_BMX_ERR_EN GLB_BMX_ERR_EN
-#define GLB_BMX_ERR_EN_POS (8)
-#define GLB_BMX_ERR_EN_LEN (1)
-#define GLB_BMX_ERR_EN_MSK \
- (((1 << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)
-#define GLB_BMX_ERR_EN_UMSK \
- (~(((1 << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS))
-#define GLB_BMX_BUSY_OPTION_DIS GLB_BMX_BUSY_OPTION_DIS
-#define GLB_BMX_BUSY_OPTION_DIS_POS (9)
-#define GLB_BMX_BUSY_OPTION_DIS_LEN (1)
-#define GLB_BMX_BUSY_OPTION_DIS_MSK \
- (((1 << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
-#define GLB_BMX_BUSY_OPTION_DIS_UMSK \
- (~(((1 << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS))
-#define GLB_BMX_GATING_DIS GLB_BMX_GATING_DIS
-#define GLB_BMX_GATING_DIS_POS (10)
-#define GLB_BMX_GATING_DIS_LEN (1)
-#define GLB_BMX_GATING_DIS_MSK \
- (((1 << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
-#define GLB_BMX_GATING_DIS_UMSK \
- (~(((1 << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
-#define GLB_HSEL_OPTION GLB_HSEL_OPTION
-#define GLB_HSEL_OPTION_POS (12)
-#define GLB_HSEL_OPTION_LEN (4)
-#define GLB_HSEL_OPTION_MSK \
- (((1 << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)
-#define GLB_HSEL_OPTION_UMSK \
- (~(((1 << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS))
-#define GLB_PDS_APB_CFG GLB_PDS_APB_CFG
-#define GLB_PDS_APB_CFG_POS (16)
-#define GLB_PDS_APB_CFG_LEN (8)
-#define GLB_PDS_APB_CFG_MSK \
- (((1 << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
-#define GLB_PDS_APB_CFG_UMSK \
- (~(((1 << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
-#define GLB_HBN_APB_CFG GLB_HBN_APB_CFG
-#define GLB_HBN_APB_CFG_POS (24)
-#define GLB_HBN_APB_CFG_LEN (8)
-#define GLB_HBN_APB_CFG_MSK \
- (((1 << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
-#define GLB_HBN_APB_CFG_UMSK \
- (~(((1 << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
-
-/* 0x54 : bmx_cfg2 */
-
-#define GLB_BMX_CFG2_OFFSET (0x54)
-#define GLB_BMX_ERR_ADDR_DIS GLB_BMX_ERR_ADDR_DIS
-#define GLB_BMX_ERR_ADDR_DIS_POS (0)
-#define GLB_BMX_ERR_ADDR_DIS_LEN (1)
-#define GLB_BMX_ERR_ADDR_DIS_MSK \
- (((1 << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)
-#define GLB_BMX_ERR_ADDR_DIS_UMSK \
- (~(((1 << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS))
-#define GLB_BMX_ERR_DEC GLB_BMX_ERR_DEC
-#define GLB_BMX_ERR_DEC_POS (4)
-#define GLB_BMX_ERR_DEC_LEN (1)
-#define GLB_BMX_ERR_DEC_MSK \
- (((1 << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)
-#define GLB_BMX_ERR_DEC_UMSK \
- (~(((1 << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS))
-#define GLB_BMX_ERR_TZ GLB_BMX_ERR_TZ
-#define GLB_BMX_ERR_TZ_POS (5)
-#define GLB_BMX_ERR_TZ_LEN (1)
-#define GLB_BMX_ERR_TZ_MSK \
- (((1 << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)
-#define GLB_BMX_ERR_TZ_UMSK \
- (~(((1 << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS))
-#define GLB_BMX_DBG_SEL GLB_BMX_DBG_SEL
-#define GLB_BMX_DBG_SEL_POS (28)
-#define GLB_BMX_DBG_SEL_LEN (4)
-#define GLB_BMX_DBG_SEL_MSK \
- (((1 << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
-#define GLB_BMX_DBG_SEL_UMSK \
- (~(((1 << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
-
-/* 0x58 : bmx_err_addr */
-
-#define GLB_BMX_ERR_ADDR_OFFSET (0x58)
-#define GLB_BMX_ERR_ADDR GLB_BMX_ERR_ADDR
-#define GLB_BMX_ERR_ADDR_POS (0)
-#define GLB_BMX_ERR_ADDR_LEN (32)
-#define GLB_BMX_ERR_ADDR_MSK \
- (((1 << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)
-#define GLB_BMX_ERR_ADDR_UMSK \
- (~(((1 << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS))
-
-/* 0x5C : bmx_dbg_out */
-
-#define GLB_BMX_DBG_OUT_OFFSET (0x5C)
-#define GLB_BMX_DBG_OUT GLB_BMX_DBG_OUT
-#define GLB_BMX_DBG_OUT_POS (0)
-#define GLB_BMX_DBG_OUT_LEN (32)
-#define GLB_BMX_DBG_OUT_MSK \
- (((1 << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)
-#define GLB_BMX_DBG_OUT_UMSK \
- (~(((1 << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS))
-
-/* 0x60 : rsv0 */
-
-#define GLB_RSV0_OFFSET (0x60)
-
-/* 0x64 : rsv1 */
-
-#define GLB_RSV1_OFFSET (0x64)
-
-/* 0x68 : rsv2 */
-
-#define GLB_RSV2_OFFSET (0x68)
-
-/* 0x6C : rsv3 */
-
-#define GLB_RSV3_OFFSET (0x6C)
-
-/* 0x70 : sram_ret */
-
-#define GLB_SRAM_RET_OFFSET (0x70)
-#define GLB_REG_SRAM_RET GLB_REG_SRAM_RET
-#define GLB_REG_SRAM_RET_POS (0)
-#define GLB_REG_SRAM_RET_LEN (32)
-#define GLB_REG_SRAM_RET_MSK \
- (((1 << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)
-#define GLB_REG_SRAM_RET_UMSK \
- (~(((1 << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS))
-
-/* 0x74 : sram_slp */
-
-#define GLB_SRAM_SLP_OFFSET (0x74)
-#define GLB_REG_SRAM_SLP GLB_REG_SRAM_SLP
-#define GLB_REG_SRAM_SLP_POS (0)
-#define GLB_REG_SRAM_SLP_LEN (32)
-#define GLB_REG_SRAM_SLP_MSK \
- (((1 << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)
-#define GLB_REG_SRAM_SLP_UMSK \
- (~(((1 << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS))
-
-/* 0x78 : sram_parm */
-
-#define GLB_SRAM_PARM_OFFSET (0x78)
-#define GLB_REG_SRAM_PARM GLB_REG_SRAM_PARM
-#define GLB_REG_SRAM_PARM_POS (0)
-#define GLB_REG_SRAM_PARM_LEN (32)
-#define GLB_REG_SRAM_PARM_MSK \
- (((1 << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)
-#define GLB_REG_SRAM_PARM_UMSK \
- (~(((1 << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS))
-
-/* 0x7C : seam_misc */
-
-#define GLB_SEAM_MISC_OFFSET (0x7C)
-#define GLB_EM_SEL GLB_EM_SEL
-#define GLB_EM_SEL_POS (0)
-#define GLB_EM_SEL_LEN (4)
-#define GLB_EM_SEL_MSK (((1 << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
-#define GLB_EM_SEL_UMSK (~(((1 << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
-
-/* 0x80 : glb_parm */
-
-#define GLB_PARM_OFFSET (0x80)
-#define GLB_REG_BD_EN GLB_REG_BD_EN
-#define GLB_REG_BD_EN_POS (0)
-#define GLB_REG_BD_EN_LEN (1)
-#define GLB_REG_BD_EN_MSK \
- (((1 << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)
-#define GLB_REG_BD_EN_UMSK \
- (~(((1 << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS))
-#define GLB_REG_EXT_RST_SMT GLB_REG_EXT_RST_SMT
-#define GLB_REG_EXT_RST_SMT_POS (1)
-#define GLB_REG_EXT_RST_SMT_LEN (1)
-#define GLB_REG_EXT_RST_SMT_MSK \
- (((1 << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)
-#define GLB_REG_EXT_RST_SMT_UMSK \
- (~(((1 << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS))
-#define GLB_JTAG_SWAP_SET GLB_JTAG_SWAP_SET
-#define GLB_JTAG_SWAP_SET_POS (2)
-#define GLB_JTAG_SWAP_SET_LEN (6)
-#define GLB_JTAG_SWAP_SET_MSK \
- (((1 << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)
-#define GLB_JTAG_SWAP_SET_UMSK \
- (~(((1 << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS))
-#define GLB_SWAP_SFLASH_IO_3_IO_0 GLB_SWAP_SFLASH_IO_3_IO_0
-#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8)
-#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1)
-#define GLB_SWAP_SFLASH_IO_3_IO_0_MSK \
- (((1 << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \
- << GLB_SWAP_SFLASH_IO_3_IO_0_POS)
-#define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK \
- (~(((1 << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \
- << GLB_SWAP_SFLASH_IO_3_IO_0_POS))
-#define GLB_SEL_EMBEDDED_SFLASH GLB_SEL_EMBEDDED_SFLASH
-#define GLB_SEL_EMBEDDED_SFLASH_POS (9)
-#define GLB_SEL_EMBEDDED_SFLASH_LEN (1)
-#define GLB_SEL_EMBEDDED_SFLASH_MSK \
- (((1 << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)
-#define GLB_SEL_EMBEDDED_SFLASH_UMSK \
- (~(((1 << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS))
-#define GLB_REG_SPI_0_MASTER_MODE GLB_REG_SPI_0_MASTER_MODE
-#define GLB_REG_SPI_0_MASTER_MODE_POS (12)
-#define GLB_REG_SPI_0_MASTER_MODE_LEN (1)
-#define GLB_REG_SPI_0_MASTER_MODE_MSK \
- (((1 << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \
- << GLB_REG_SPI_0_MASTER_MODE_POS)
-#define GLB_REG_SPI_0_MASTER_MODE_UMSK \
- (~(((1 << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \
- << GLB_REG_SPI_0_MASTER_MODE_POS))
-#define GLB_REG_SPI_0_SWAP GLB_REG_SPI_0_SWAP
-#define GLB_REG_SPI_0_SWAP_POS (13)
-#define GLB_REG_SPI_0_SWAP_LEN (1)
-#define GLB_REG_SPI_0_SWAP_MSK \
- (((1 << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
-#define GLB_REG_SPI_0_SWAP_UMSK \
- (~(((1 << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
-#define GLB_REG_CCI_USE_JTAG_PIN GLB_REG_CCI_USE_JTAG_PIN
-#define GLB_REG_CCI_USE_JTAG_PIN_POS (15)
-#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1)
-#define GLB_REG_CCI_USE_JTAG_PIN_MSK \
- (((1 << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)
-#define GLB_REG_CCI_USE_JTAG_PIN_UMSK \
- (~(((1 << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) \
- << GLB_REG_CCI_USE_JTAG_PIN_POS))
-#define GLB_REG_CCI_USE_SDIO_PIN GLB_REG_CCI_USE_SDIO_PIN
-#define GLB_REG_CCI_USE_SDIO_PIN_POS (16)
-#define GLB_REG_CCI_USE_SDIO_PIN_LEN (1)
-#define GLB_REG_CCI_USE_SDIO_PIN_MSK \
- (((1 << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS)
-#define GLB_REG_CCI_USE_SDIO_PIN_UMSK \
- (~(((1 << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) \
- << GLB_REG_CCI_USE_SDIO_PIN_POS))
-#define GLB_P1_ADC_TEST_WITH_CCI GLB_P1_ADC_TEST_WITH_CCI
-#define GLB_P1_ADC_TEST_WITH_CCI_POS (17)
-#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1)
-#define GLB_P1_ADC_TEST_WITH_CCI_MSK \
- (((1 << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
-#define GLB_P1_ADC_TEST_WITH_CCI_UMSK \
- (~(((1 << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) \
- << GLB_P1_ADC_TEST_WITH_CCI_POS))
-#define GLB_P2_DAC_TEST_WITH_CCI GLB_P2_DAC_TEST_WITH_CCI
-#define GLB_P2_DAC_TEST_WITH_CCI_POS (18)
-#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1)
-#define GLB_P2_DAC_TEST_WITH_CCI_MSK \
- (((1 << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
-#define GLB_P2_DAC_TEST_WITH_CCI_UMSK \
- (~(((1 << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) \
- << GLB_P2_DAC_TEST_WITH_CCI_POS))
-#define GLB_P3_CCI_USE_IO_2_5 GLB_P3_CCI_USE_IO_2_5
-#define GLB_P3_CCI_USE_IO_2_5_POS (19)
-#define GLB_P3_CCI_USE_IO_2_5_LEN (1)
-#define GLB_P3_CCI_USE_IO_2_5_MSK \
- (((1 << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)
-#define GLB_P3_CCI_USE_IO_2_5_UMSK \
- (~(((1 << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS))
-#define GLB_P4_ADC_TEST_WITH_JTAG GLB_P4_ADC_TEST_WITH_JTAG
-#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20)
-#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1)
-#define GLB_P4_ADC_TEST_WITH_JTAG_MSK \
- (((1 << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \
- << GLB_P4_ADC_TEST_WITH_JTAG_POS)
-#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK \
- (~(((1 << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \
- << GLB_P4_ADC_TEST_WITH_JTAG_POS))
-#define GLB_P5_DAC_TEST_WITH_JTAG GLB_P5_DAC_TEST_WITH_JTAG
-#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21)
-#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1)
-#define GLB_P5_DAC_TEST_WITH_JTAG_MSK \
- (((1 << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \
- << GLB_P5_DAC_TEST_WITH_JTAG_POS)
-#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK \
- (~(((1 << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \
- << GLB_P5_DAC_TEST_WITH_JTAG_POS))
-#define GLB_P6_SDIO_USE_IO_0_5 GLB_P6_SDIO_USE_IO_0_5
-#define GLB_P6_SDIO_USE_IO_0_5_POS (22)
-#define GLB_P6_SDIO_USE_IO_0_5_LEN (1)
-#define GLB_P6_SDIO_USE_IO_0_5_MSK \
- (((1 << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)
-#define GLB_P6_SDIO_USE_IO_0_5_UMSK \
- (~(((1 << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS))
-#define GLB_P7_JTAG_USE_IO_2_5 GLB_P7_JTAG_USE_IO_2_5
-#define GLB_P7_JTAG_USE_IO_2_5_POS (23)
-#define GLB_P7_JTAG_USE_IO_2_5_LEN (1)
-#define GLB_P7_JTAG_USE_IO_2_5_MSK \
- (((1 << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)
-#define GLB_P7_JTAG_USE_IO_2_5_UMSK \
- (~(((1 << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS))
-#define GLB_UART_SWAP_SET GLB_UART_SWAP_SET
-#define GLB_UART_SWAP_SET_POS (24)
-#define GLB_UART_SWAP_SET_LEN (3)
-#define GLB_UART_SWAP_SET_MSK \
- (((1 << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
-#define GLB_UART_SWAP_SET_UMSK \
- (~(((1 << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
-
-/* 0x90 : CPU_CLK_CFG */
-
-#define GLB_CPU_CLK_CFG_OFFSET (0x90)
-#define GLB_CPU_RTC_DIV GLB_CPU_RTC_DIV
-#define GLB_CPU_RTC_DIV_POS (0)
-#define GLB_CPU_RTC_DIV_LEN (17)
-#define GLB_CPU_RTC_DIV_MSK \
- (((1 << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
-#define GLB_CPU_RTC_DIV_UMSK \
- (~(((1 << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
-#define GLB_CPU_RTC_EN GLB_CPU_RTC_EN
-#define GLB_CPU_RTC_EN_POS (18)
-#define GLB_CPU_RTC_EN_LEN (1)
-#define GLB_CPU_RTC_EN_MSK \
- (((1 << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
-#define GLB_CPU_RTC_EN_UMSK \
- (~(((1 << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
-#define GLB_CPU_RTC_SEL GLB_CPU_RTC_SEL
-#define GLB_CPU_RTC_SEL_POS (19)
-#define GLB_CPU_RTC_SEL_LEN (1)
-#define GLB_CPU_RTC_SEL_MSK \
- (((1 << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
-#define GLB_CPU_RTC_SEL_UMSK \
- (~(((1 << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
-#define GLB_DEBUG_NDRESET_GATE GLB_DEBUG_NDRESET_GATE
-#define GLB_DEBUG_NDRESET_GATE_POS (20)
-#define GLB_DEBUG_NDRESET_GATE_LEN (1)
-#define GLB_DEBUG_NDRESET_GATE_MSK \
- (((1 << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
-#define GLB_DEBUG_NDRESET_GATE_UMSK \
- (~(((1 << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
-
-/* 0xA4 : GPADC_32M_SRC_CTRL */
-
-#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4)
-#define GLB_GPADC_32M_CLK_DIV GLB_GPADC_32M_CLK_DIV
-#define GLB_GPADC_32M_CLK_DIV_POS (0)
-#define GLB_GPADC_32M_CLK_DIV_LEN (6)
-#define GLB_GPADC_32M_CLK_DIV_MSK \
- (((1 << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
-#define GLB_GPADC_32M_CLK_DIV_UMSK \
- (~(((1 << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
-#define GLB_GPADC_32M_CLK_SEL GLB_GPADC_32M_CLK_SEL
-#define GLB_GPADC_32M_CLK_SEL_POS (7)
-#define GLB_GPADC_32M_CLK_SEL_LEN (1)
-#define GLB_GPADC_32M_CLK_SEL_MSK \
- (((1 << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
-#define GLB_GPADC_32M_CLK_SEL_UMSK \
- (~(((1 << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
-#define GLB_GPADC_32M_DIV_EN GLB_GPADC_32M_DIV_EN
-#define GLB_GPADC_32M_DIV_EN_POS (8)
-#define GLB_GPADC_32M_DIV_EN_LEN (1)
-#define GLB_GPADC_32M_DIV_EN_MSK \
- (((1 << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
-#define GLB_GPADC_32M_DIV_EN_UMSK \
- (~(((1 << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
-
-/* 0xA8 : DIG32K_WAKEUP_CTRL */
-
-#define GLB_DIG32K_WAKEUP_CTRL_OFFSET (0xA8)
-#define GLB_DIG_32K_DIV GLB_DIG_32K_DIV
-#define GLB_DIG_32K_DIV_POS (0)
-#define GLB_DIG_32K_DIV_LEN (11)
-#define GLB_DIG_32K_DIV_MSK \
- (((1 << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
-#define GLB_DIG_32K_DIV_UMSK \
- (~(((1 << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
-#define GLB_DIG_32K_EN GLB_DIG_32K_EN
-#define GLB_DIG_32K_EN_POS (12)
-#define GLB_DIG_32K_EN_LEN (1)
-#define GLB_DIG_32K_EN_MSK \
- (((1 << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
-#define GLB_DIG_32K_EN_UMSK \
- (~(((1 << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
-#define GLB_DIG_32K_COMP GLB_DIG_32K_COMP
-#define GLB_DIG_32K_COMP_POS (13)
-#define GLB_DIG_32K_COMP_LEN (1)
-#define GLB_DIG_32K_COMP_MSK \
- (((1 << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
-#define GLB_DIG_32K_COMP_UMSK \
- (~(((1 << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
-#define GLB_DIG_512K_DIV GLB_DIG_512K_DIV
-#define GLB_DIG_512K_DIV_POS (16)
-#define GLB_DIG_512K_DIV_LEN (7)
-#define GLB_DIG_512K_DIV_MSK \
- (((1 << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
-#define GLB_DIG_512K_DIV_UMSK \
- (~(((1 << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
-#define GLB_DIG_512K_EN GLB_DIG_512K_EN
-#define GLB_DIG_512K_EN_POS (24)
-#define GLB_DIG_512K_EN_LEN (1)
-#define GLB_DIG_512K_EN_MSK \
- (((1 << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
-#define GLB_DIG_512K_EN_UMSK \
- (~(((1 << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
-#define GLB_DIG_512K_COMP GLB_DIG_512K_COMP
-#define GLB_DIG_512K_COMP_POS (25)
-#define GLB_DIG_512K_COMP_LEN (1)
-#define GLB_DIG_512K_COMP_MSK \
- (((1 << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
-#define GLB_DIG_512K_COMP_UMSK \
- (~(((1 << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
-#define GLB_DIG_CLK_SRC_SEL GLB_DIG_CLK_SRC_SEL
-#define GLB_DIG_CLK_SRC_SEL_POS (28)
-#define GLB_DIG_CLK_SRC_SEL_LEN (1)
-#define GLB_DIG_CLK_SRC_SEL_MSK \
- (((1 << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
-#define GLB_DIG_CLK_SRC_SEL_UMSK \
- (~(((1 << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
-#define GLB_REG_EN_PLATFORM_WAKEUP GLB_REG_EN_PLATFORM_WAKEUP
-#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31)
-#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1)
-#define GLB_REG_EN_PLATFORM_WAKEUP_MSK \
- (((1 << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \
- << GLB_REG_EN_PLATFORM_WAKEUP_POS)
-#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK \
- (~(((1 << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \
- << GLB_REG_EN_PLATFORM_WAKEUP_POS))
-
-/* 0xAC : WIFI_BT_COEX_CTRL */
-
-#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC)
-#define GLB_COEX_BT_CHANNEL GLB_COEX_BT_CHANNEL
-#define GLB_COEX_BT_CHANNEL_POS (0)
-#define GLB_COEX_BT_CHANNEL_LEN (7)
-#define GLB_COEX_BT_CHANNEL_MSK \
- (((1 << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)
-#define GLB_COEX_BT_CHANNEL_UMSK \
- (~(((1 << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS))
-#define GLB_COEX_BT_PTI GLB_COEX_BT_PTI
-#define GLB_COEX_BT_PTI_POS (7)
-#define GLB_COEX_BT_PTI_LEN (4)
-#define GLB_COEX_BT_PTI_MSK \
- (((1 << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)
-#define GLB_COEX_BT_PTI_UMSK \
- (~(((1 << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS))
-#define GLB_COEX_BT_BW GLB_COEX_BT_BW
-#define GLB_COEX_BT_BW_POS (11)
-#define GLB_COEX_BT_BW_LEN (1)
-#define GLB_COEX_BT_BW_MSK \
- (((1 << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)
-#define GLB_COEX_BT_BW_UMSK \
- (~(((1 << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS))
-#define GLB_EN_GPIO_BT_COEX GLB_EN_GPIO_BT_COEX
-#define GLB_EN_GPIO_BT_COEX_POS (12)
-#define GLB_EN_GPIO_BT_COEX_LEN (1)
-#define GLB_EN_GPIO_BT_COEX_MSK \
- (((1 << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)
-#define GLB_EN_GPIO_BT_COEX_UMSK \
- (~(((1 << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS))
-
-/* 0xC0 : UART_SIG_SEL_0 */
-
-#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
-#define GLB_UART_SIG_0_SEL GLB_UART_SIG_0_SEL
-#define GLB_UART_SIG_0_SEL_POS (0)
-#define GLB_UART_SIG_0_SEL_LEN (4)
-#define GLB_UART_SIG_0_SEL_MSK \
- (((1 << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
-#define GLB_UART_SIG_0_SEL_UMSK \
- (~(((1 << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
-#define GLB_UART_SIG_1_SEL GLB_UART_SIG_1_SEL
-#define GLB_UART_SIG_1_SEL_POS (4)
-#define GLB_UART_SIG_1_SEL_LEN (4)
-#define GLB_UART_SIG_1_SEL_MSK \
- (((1 << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
-#define GLB_UART_SIG_1_SEL_UMSK \
- (~(((1 << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
-#define GLB_UART_SIG_2_SEL GLB_UART_SIG_2_SEL
-#define GLB_UART_SIG_2_SEL_POS (8)
-#define GLB_UART_SIG_2_SEL_LEN (4)
-#define GLB_UART_SIG_2_SEL_MSK \
- (((1 << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
-#define GLB_UART_SIG_2_SEL_UMSK \
- (~(((1 << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
-#define GLB_UART_SIG_3_SEL GLB_UART_SIG_3_SEL
-#define GLB_UART_SIG_3_SEL_POS (12)
-#define GLB_UART_SIG_3_SEL_LEN (4)
-#define GLB_UART_SIG_3_SEL_MSK \
- (((1 << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
-#define GLB_UART_SIG_3_SEL_UMSK \
- (~(((1 << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
-#define GLB_UART_SIG_4_SEL GLB_UART_SIG_4_SEL
-#define GLB_UART_SIG_4_SEL_POS (16)
-#define GLB_UART_SIG_4_SEL_LEN (4)
-#define GLB_UART_SIG_4_SEL_MSK \
- (((1 << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
-#define GLB_UART_SIG_4_SEL_UMSK \
- (~(((1 << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
-#define GLB_UART_SIG_5_SEL GLB_UART_SIG_5_SEL
-#define GLB_UART_SIG_5_SEL_POS (20)
-#define GLB_UART_SIG_5_SEL_LEN (4)
-#define GLB_UART_SIG_5_SEL_MSK \
- (((1 << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
-#define GLB_UART_SIG_5_SEL_UMSK \
- (~(((1 << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
-#define GLB_UART_SIG_6_SEL GLB_UART_SIG_6_SEL
-#define GLB_UART_SIG_6_SEL_POS (24)
-#define GLB_UART_SIG_6_SEL_LEN (4)
-#define GLB_UART_SIG_6_SEL_MSK \
- (((1 << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
-#define GLB_UART_SIG_6_SEL_UMSK \
- (~(((1 << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
-#define GLB_UART_SIG_7_SEL GLB_UART_SIG_7_SEL
-#define GLB_UART_SIG_7_SEL_POS (28)
-#define GLB_UART_SIG_7_SEL_LEN (4)
-#define GLB_UART_SIG_7_SEL_MSK \
- (((1 << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
-#define GLB_UART_SIG_7_SEL_UMSK \
- (~(((1 << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
-
-/* 0xD0 : DBG_SEL_LL */
-
-#define GLB_DBG_SEL_LL_OFFSET (0xD0)
-#define GLB_REG_DBG_LL_CTRL GLB_REG_DBG_LL_CTRL
-#define GLB_REG_DBG_LL_CTRL_POS (0)
-#define GLB_REG_DBG_LL_CTRL_LEN (32)
-#define GLB_REG_DBG_LL_CTRL_MSK \
- (((1 << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
-#define GLB_REG_DBG_LL_CTRL_UMSK \
- (~(((1 << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
-
-/* 0xD4 : DBG_SEL_LH */
-
-#define GLB_DBG_SEL_LH_OFFSET (0xD4)
-#define GLB_REG_DBG_LH_CTRL GLB_REG_DBG_LH_CTRL
-#define GLB_REG_DBG_LH_CTRL_POS (0)
-#define GLB_REG_DBG_LH_CTRL_LEN (32)
-#define GLB_REG_DBG_LH_CTRL_MSK \
- (((1 << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
-#define GLB_REG_DBG_LH_CTRL_UMSK \
- (~(((1 << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
-
-/* 0xD8 : DBG_SEL_HL */
-
-#define GLB_DBG_SEL_HL_OFFSET (0xD8)
-#define GLB_REG_DBG_HL_CTRL GLB_REG_DBG_HL_CTRL
-#define GLB_REG_DBG_HL_CTRL_POS (0)
-#define GLB_REG_DBG_HL_CTRL_LEN (32)
-#define GLB_REG_DBG_HL_CTRL_MSK \
- (((1 << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
-#define GLB_REG_DBG_HL_CTRL_UMSK \
- (~(((1 << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
-
-/* 0xDC : DBG_SEL_HH */
-
-#define GLB_DBG_SEL_HH_OFFSET (0xDC)
-#define GLB_REG_DBG_HH_CTRL GLB_REG_DBG_HH_CTRL
-#define GLB_REG_DBG_HH_CTRL_POS (0)
-#define GLB_REG_DBG_HH_CTRL_LEN (32)
-#define GLB_REG_DBG_HH_CTRL_MSK \
- (((1 << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
-#define GLB_REG_DBG_HH_CTRL_UMSK \
- (~(((1 << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
-
-/* 0xE0 : debug */
-
-#define GLB_DEBUG_OFFSET (0xE0)
-#define GLB_DEBUG_OE GLB_DEBUG_OE
-#define GLB_DEBUG_OE_POS (0)
-#define GLB_DEBUG_OE_LEN (1)
-#define GLB_DEBUG_OE_MSK (((1 << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
-#define GLB_DEBUG_OE_UMSK \
- (~(((1 << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
-#define GLB_DEBUG_I GLB_DEBUG_I
-#define GLB_DEBUG_I_POS (1)
-#define GLB_DEBUG_I_LEN (31)
-#define GLB_DEBUG_I_MSK (((1 << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
-#define GLB_DEBUG_I_UMSK (~(((1 << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
-
-/* 0x100 : GPIO_CFGCTL0 */
-
-#define GLB_GPIO_CFGCTL0_OFFSET (0x100)
-#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE
-#define GLB_REG_GPIO_0_IE_POS (0)
-#define GLB_REG_GPIO_0_IE_LEN (1)
-#define GLB_REG_GPIO_0_IE_MSK \
- (((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
-#define GLB_REG_GPIO_0_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
-#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT
-#define GLB_REG_GPIO_0_SMT_POS (1)
-#define GLB_REG_GPIO_0_SMT_LEN (1)
-#define GLB_REG_GPIO_0_SMT_MSK \
- (((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
-#define GLB_REG_GPIO_0_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
-#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV
-#define GLB_REG_GPIO_0_DRV_POS (2)
-#define GLB_REG_GPIO_0_DRV_LEN (2)
-#define GLB_REG_GPIO_0_DRV_MSK \
- (((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
-#define GLB_REG_GPIO_0_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
-#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU
-#define GLB_REG_GPIO_0_PU_POS (4)
-#define GLB_REG_GPIO_0_PU_LEN (1)
-#define GLB_REG_GPIO_0_PU_MSK \
- (((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
-#define GLB_REG_GPIO_0_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
-#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD
-#define GLB_REG_GPIO_0_PD_POS (5)
-#define GLB_REG_GPIO_0_PD_LEN (1)
-#define GLB_REG_GPIO_0_PD_MSK \
- (((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
-#define GLB_REG_GPIO_0_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
-#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL
-#define GLB_REG_GPIO_0_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_0_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
-#define GLB_REG_GPIO_0_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
-#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL
-#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12)
-#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4)
-#define GLB_REAL_GPIO_0_FUNC_SEL_MSK \
- (((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
-#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK \
- (~(((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \
- << GLB_REAL_GPIO_0_FUNC_SEL_POS))
-#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE
-#define GLB_REG_GPIO_1_IE_POS (16)
-#define GLB_REG_GPIO_1_IE_LEN (1)
-#define GLB_REG_GPIO_1_IE_MSK \
- (((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
-#define GLB_REG_GPIO_1_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
-#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT
-#define GLB_REG_GPIO_1_SMT_POS (17)
-#define GLB_REG_GPIO_1_SMT_LEN (1)
-#define GLB_REG_GPIO_1_SMT_MSK \
- (((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
-#define GLB_REG_GPIO_1_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
-#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV
-#define GLB_REG_GPIO_1_DRV_POS (18)
-#define GLB_REG_GPIO_1_DRV_LEN (2)
-#define GLB_REG_GPIO_1_DRV_MSK \
- (((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
-#define GLB_REG_GPIO_1_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
-#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU
-#define GLB_REG_GPIO_1_PU_POS (20)
-#define GLB_REG_GPIO_1_PU_LEN (1)
-#define GLB_REG_GPIO_1_PU_MSK \
- (((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
-#define GLB_REG_GPIO_1_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
-#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD
-#define GLB_REG_GPIO_1_PD_POS (21)
-#define GLB_REG_GPIO_1_PD_LEN (1)
-#define GLB_REG_GPIO_1_PD_MSK \
- (((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
-#define GLB_REG_GPIO_1_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
-#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL
-#define GLB_REG_GPIO_1_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_1_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
-#define GLB_REG_GPIO_1_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
-#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL
-#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28)
-#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4)
-#define GLB_REAL_GPIO_1_FUNC_SEL_MSK \
- (((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
-#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK \
- (~(((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \
- << GLB_REAL_GPIO_1_FUNC_SEL_POS))
-
-/* 0x104 : GPIO_CFGCTL1 */
-
-#define GLB_GPIO_CFGCTL1_OFFSET (0x104)
-#define GLB_REG_GPIO_2_IE GLB_REG_GPIO_2_IE
-#define GLB_REG_GPIO_2_IE_POS (0)
-#define GLB_REG_GPIO_2_IE_LEN (1)
-#define GLB_REG_GPIO_2_IE_MSK \
- (((1 << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
-#define GLB_REG_GPIO_2_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
-#define GLB_REG_GPIO_2_SMT GLB_REG_GPIO_2_SMT
-#define GLB_REG_GPIO_2_SMT_POS (1)
-#define GLB_REG_GPIO_2_SMT_LEN (1)
-#define GLB_REG_GPIO_2_SMT_MSK \
- (((1 << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
-#define GLB_REG_GPIO_2_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
-#define GLB_REG_GPIO_2_DRV GLB_REG_GPIO_2_DRV
-#define GLB_REG_GPIO_2_DRV_POS (2)
-#define GLB_REG_GPIO_2_DRV_LEN (2)
-#define GLB_REG_GPIO_2_DRV_MSK \
- (((1 << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
-#define GLB_REG_GPIO_2_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
-#define GLB_REG_GPIO_2_PU GLB_REG_GPIO_2_PU
-#define GLB_REG_GPIO_2_PU_POS (4)
-#define GLB_REG_GPIO_2_PU_LEN (1)
-#define GLB_REG_GPIO_2_PU_MSK \
- (((1 << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
-#define GLB_REG_GPIO_2_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
-#define GLB_REG_GPIO_2_PD GLB_REG_GPIO_2_PD
-#define GLB_REG_GPIO_2_PD_POS (5)
-#define GLB_REG_GPIO_2_PD_LEN (1)
-#define GLB_REG_GPIO_2_PD_MSK \
- (((1 << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
-#define GLB_REG_GPIO_2_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
-#define GLB_REG_GPIO_2_FUNC_SEL GLB_REG_GPIO_2_FUNC_SEL
-#define GLB_REG_GPIO_2_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_2_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_2_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
-#define GLB_REG_GPIO_2_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS))
-#define GLB_REAL_GPIO_2_FUNC_SEL GLB_REAL_GPIO_2_FUNC_SEL
-#define GLB_REAL_GPIO_2_FUNC_SEL_POS (12)
-#define GLB_REAL_GPIO_2_FUNC_SEL_LEN (4)
-#define GLB_REAL_GPIO_2_FUNC_SEL_MSK \
- (((1 << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS)
-#define GLB_REAL_GPIO_2_FUNC_SEL_UMSK \
- (~(((1 << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) \
- << GLB_REAL_GPIO_2_FUNC_SEL_POS))
-#define GLB_REG_GPIO_3_IE GLB_REG_GPIO_3_IE
-#define GLB_REG_GPIO_3_IE_POS (16)
-#define GLB_REG_GPIO_3_IE_LEN (1)
-#define GLB_REG_GPIO_3_IE_MSK \
- (((1 << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
-#define GLB_REG_GPIO_3_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
-#define GLB_REG_GPIO_3_SMT GLB_REG_GPIO_3_SMT
-#define GLB_REG_GPIO_3_SMT_POS (17)
-#define GLB_REG_GPIO_3_SMT_LEN (1)
-#define GLB_REG_GPIO_3_SMT_MSK \
- (((1 << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
-#define GLB_REG_GPIO_3_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
-#define GLB_REG_GPIO_3_DRV GLB_REG_GPIO_3_DRV
-#define GLB_REG_GPIO_3_DRV_POS (18)
-#define GLB_REG_GPIO_3_DRV_LEN (2)
-#define GLB_REG_GPIO_3_DRV_MSK \
- (((1 << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
-#define GLB_REG_GPIO_3_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
-#define GLB_REG_GPIO_3_PU GLB_REG_GPIO_3_PU
-#define GLB_REG_GPIO_3_PU_POS (20)
-#define GLB_REG_GPIO_3_PU_LEN (1)
-#define GLB_REG_GPIO_3_PU_MSK \
- (((1 << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
-#define GLB_REG_GPIO_3_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
-#define GLB_REG_GPIO_3_PD GLB_REG_GPIO_3_PD
-#define GLB_REG_GPIO_3_PD_POS (21)
-#define GLB_REG_GPIO_3_PD_LEN (1)
-#define GLB_REG_GPIO_3_PD_MSK \
- (((1 << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
-#define GLB_REG_GPIO_3_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
-#define GLB_REG_GPIO_3_FUNC_SEL GLB_REG_GPIO_3_FUNC_SEL
-#define GLB_REG_GPIO_3_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_3_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_3_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
-#define GLB_REG_GPIO_3_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS))
-#define GLB_REAL_GPIO_3_FUNC_SEL GLB_REAL_GPIO_3_FUNC_SEL
-#define GLB_REAL_GPIO_3_FUNC_SEL_POS (28)
-#define GLB_REAL_GPIO_3_FUNC_SEL_LEN (4)
-#define GLB_REAL_GPIO_3_FUNC_SEL_MSK \
- (((1 << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS)
-#define GLB_REAL_GPIO_3_FUNC_SEL_UMSK \
- (~(((1 << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) \
- << GLB_REAL_GPIO_3_FUNC_SEL_POS))
-
-/* 0x108 : GPIO_CFGCTL2 */
-
-#define GLB_GPIO_CFGCTL2_OFFSET (0x108)
-#define GLB_REG_GPIO_4_IE GLB_REG_GPIO_4_IE
-#define GLB_REG_GPIO_4_IE_POS (0)
-#define GLB_REG_GPIO_4_IE_LEN (1)
-#define GLB_REG_GPIO_4_IE_MSK \
- (((1 << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
-#define GLB_REG_GPIO_4_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
-#define GLB_REG_GPIO_4_SMT GLB_REG_GPIO_4_SMT
-#define GLB_REG_GPIO_4_SMT_POS (1)
-#define GLB_REG_GPIO_4_SMT_LEN (1)
-#define GLB_REG_GPIO_4_SMT_MSK \
- (((1 << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
-#define GLB_REG_GPIO_4_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
-#define GLB_REG_GPIO_4_DRV GLB_REG_GPIO_4_DRV
-#define GLB_REG_GPIO_4_DRV_POS (2)
-#define GLB_REG_GPIO_4_DRV_LEN (2)
-#define GLB_REG_GPIO_4_DRV_MSK \
- (((1 << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
-#define GLB_REG_GPIO_4_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
-#define GLB_REG_GPIO_4_PU GLB_REG_GPIO_4_PU
-#define GLB_REG_GPIO_4_PU_POS (4)
-#define GLB_REG_GPIO_4_PU_LEN (1)
-#define GLB_REG_GPIO_4_PU_MSK \
- (((1 << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
-#define GLB_REG_GPIO_4_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
-#define GLB_REG_GPIO_4_PD GLB_REG_GPIO_4_PD
-#define GLB_REG_GPIO_4_PD_POS (5)
-#define GLB_REG_GPIO_4_PD_LEN (1)
-#define GLB_REG_GPIO_4_PD_MSK \
- (((1 << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
-#define GLB_REG_GPIO_4_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
-#define GLB_REG_GPIO_4_FUNC_SEL GLB_REG_GPIO_4_FUNC_SEL
-#define GLB_REG_GPIO_4_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_4_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_4_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
-#define GLB_REG_GPIO_4_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS))
-#define GLB_REAL_GPIO_4_FUNC_SEL GLB_REAL_GPIO_4_FUNC_SEL
-#define GLB_REAL_GPIO_4_FUNC_SEL_POS (12)
-#define GLB_REAL_GPIO_4_FUNC_SEL_LEN (4)
-#define GLB_REAL_GPIO_4_FUNC_SEL_MSK \
- (((1 << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS)
-#define GLB_REAL_GPIO_4_FUNC_SEL_UMSK \
- (~(((1 << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) \
- << GLB_REAL_GPIO_4_FUNC_SEL_POS))
-#define GLB_REG_GPIO_5_IE GLB_REG_GPIO_5_IE
-#define GLB_REG_GPIO_5_IE_POS (16)
-#define GLB_REG_GPIO_5_IE_LEN (1)
-#define GLB_REG_GPIO_5_IE_MSK \
- (((1 << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
-#define GLB_REG_GPIO_5_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
-#define GLB_REG_GPIO_5_SMT GLB_REG_GPIO_5_SMT
-#define GLB_REG_GPIO_5_SMT_POS (17)
-#define GLB_REG_GPIO_5_SMT_LEN (1)
-#define GLB_REG_GPIO_5_SMT_MSK \
- (((1 << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
-#define GLB_REG_GPIO_5_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
-#define GLB_REG_GPIO_5_DRV GLB_REG_GPIO_5_DRV
-#define GLB_REG_GPIO_5_DRV_POS (18)
-#define GLB_REG_GPIO_5_DRV_LEN (2)
-#define GLB_REG_GPIO_5_DRV_MSK \
- (((1 << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
-#define GLB_REG_GPIO_5_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
-#define GLB_REG_GPIO_5_PU GLB_REG_GPIO_5_PU
-#define GLB_REG_GPIO_5_PU_POS (20)
-#define GLB_REG_GPIO_5_PU_LEN (1)
-#define GLB_REG_GPIO_5_PU_MSK \
- (((1 << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
-#define GLB_REG_GPIO_5_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
-#define GLB_REG_GPIO_5_PD GLB_REG_GPIO_5_PD
-#define GLB_REG_GPIO_5_PD_POS (21)
-#define GLB_REG_GPIO_5_PD_LEN (1)
-#define GLB_REG_GPIO_5_PD_MSK \
- (((1 << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
-#define GLB_REG_GPIO_5_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
-#define GLB_REG_GPIO_5_FUNC_SEL GLB_REG_GPIO_5_FUNC_SEL
-#define GLB_REG_GPIO_5_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_5_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_5_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
-#define GLB_REG_GPIO_5_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS))
-#define GLB_REAL_GPIO_5_FUNC_SEL GLB_REAL_GPIO_5_FUNC_SEL
-#define GLB_REAL_GPIO_5_FUNC_SEL_POS (28)
-#define GLB_REAL_GPIO_5_FUNC_SEL_LEN (4)
-#define GLB_REAL_GPIO_5_FUNC_SEL_MSK \
- (((1 << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS)
-#define GLB_REAL_GPIO_5_FUNC_SEL_UMSK \
- (~(((1 << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) \
- << GLB_REAL_GPIO_5_FUNC_SEL_POS))
-
-/* 0x10C : GPIO_CFGCTL3 */
-
-#define GLB_GPIO_CFGCTL3_OFFSET (0x10C)
-#define GLB_REG_GPIO_6_IE GLB_REG_GPIO_6_IE
-#define GLB_REG_GPIO_6_IE_POS (0)
-#define GLB_REG_GPIO_6_IE_LEN (1)
-#define GLB_REG_GPIO_6_IE_MSK \
- (((1 << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
-#define GLB_REG_GPIO_6_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
-#define GLB_REG_GPIO_6_SMT GLB_REG_GPIO_6_SMT
-#define GLB_REG_GPIO_6_SMT_POS (1)
-#define GLB_REG_GPIO_6_SMT_LEN (1)
-#define GLB_REG_GPIO_6_SMT_MSK \
- (((1 << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
-#define GLB_REG_GPIO_6_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
-#define GLB_REG_GPIO_6_DRV GLB_REG_GPIO_6_DRV
-#define GLB_REG_GPIO_6_DRV_POS (2)
-#define GLB_REG_GPIO_6_DRV_LEN (2)
-#define GLB_REG_GPIO_6_DRV_MSK \
- (((1 << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
-#define GLB_REG_GPIO_6_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
-#define GLB_REG_GPIO_6_PU GLB_REG_GPIO_6_PU
-#define GLB_REG_GPIO_6_PU_POS (4)
-#define GLB_REG_GPIO_6_PU_LEN (1)
-#define GLB_REG_GPIO_6_PU_MSK \
- (((1 << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
-#define GLB_REG_GPIO_6_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
-#define GLB_REG_GPIO_6_PD GLB_REG_GPIO_6_PD
-#define GLB_REG_GPIO_6_PD_POS (5)
-#define GLB_REG_GPIO_6_PD_LEN (1)
-#define GLB_REG_GPIO_6_PD_MSK \
- (((1 << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
-#define GLB_REG_GPIO_6_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
-#define GLB_REG_GPIO_6_FUNC_SEL GLB_REG_GPIO_6_FUNC_SEL
-#define GLB_REG_GPIO_6_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_6_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_6_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
-#define GLB_REG_GPIO_6_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS))
-#define GLB_REG_GPIO_7_IE GLB_REG_GPIO_7_IE
-#define GLB_REG_GPIO_7_IE_POS (16)
-#define GLB_REG_GPIO_7_IE_LEN (1)
-#define GLB_REG_GPIO_7_IE_MSK \
- (((1 << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
-#define GLB_REG_GPIO_7_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
-#define GLB_REG_GPIO_7_SMT GLB_REG_GPIO_7_SMT
-#define GLB_REG_GPIO_7_SMT_POS (17)
-#define GLB_REG_GPIO_7_SMT_LEN (1)
-#define GLB_REG_GPIO_7_SMT_MSK \
- (((1 << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
-#define GLB_REG_GPIO_7_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
-#define GLB_REG_GPIO_7_DRV GLB_REG_GPIO_7_DRV
-#define GLB_REG_GPIO_7_DRV_POS (18)
-#define GLB_REG_GPIO_7_DRV_LEN (2)
-#define GLB_REG_GPIO_7_DRV_MSK \
- (((1 << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
-#define GLB_REG_GPIO_7_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
-#define GLB_REG_GPIO_7_PU GLB_REG_GPIO_7_PU
-#define GLB_REG_GPIO_7_PU_POS (20)
-#define GLB_REG_GPIO_7_PU_LEN (1)
-#define GLB_REG_GPIO_7_PU_MSK \
- (((1 << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
-#define GLB_REG_GPIO_7_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
-#define GLB_REG_GPIO_7_PD GLB_REG_GPIO_7_PD
-#define GLB_REG_GPIO_7_PD_POS (21)
-#define GLB_REG_GPIO_7_PD_LEN (1)
-#define GLB_REG_GPIO_7_PD_MSK \
- (((1 << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
-#define GLB_REG_GPIO_7_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
-#define GLB_REG_GPIO_7_FUNC_SEL GLB_REG_GPIO_7_FUNC_SEL
-#define GLB_REG_GPIO_7_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_7_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_7_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
-#define GLB_REG_GPIO_7_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS))
-
-/* 0x110 : GPIO_CFGCTL4 */
-
-#define GLB_GPIO_CFGCTL4_OFFSET (0x110)
-#define GLB_REG_GPIO_8_IE GLB_REG_GPIO_8_IE
-#define GLB_REG_GPIO_8_IE_POS (0)
-#define GLB_REG_GPIO_8_IE_LEN (1)
-#define GLB_REG_GPIO_8_IE_MSK \
- (((1 << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
-#define GLB_REG_GPIO_8_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
-#define GLB_REG_GPIO_8_SMT GLB_REG_GPIO_8_SMT
-#define GLB_REG_GPIO_8_SMT_POS (1)
-#define GLB_REG_GPIO_8_SMT_LEN (1)
-#define GLB_REG_GPIO_8_SMT_MSK \
- (((1 << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
-#define GLB_REG_GPIO_8_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
-#define GLB_REG_GPIO_8_DRV GLB_REG_GPIO_8_DRV
-#define GLB_REG_GPIO_8_DRV_POS (2)
-#define GLB_REG_GPIO_8_DRV_LEN (2)
-#define GLB_REG_GPIO_8_DRV_MSK \
- (((1 << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
-#define GLB_REG_GPIO_8_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
-#define GLB_REG_GPIO_8_PU GLB_REG_GPIO_8_PU
-#define GLB_REG_GPIO_8_PU_POS (4)
-#define GLB_REG_GPIO_8_PU_LEN (1)
-#define GLB_REG_GPIO_8_PU_MSK \
- (((1 << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
-#define GLB_REG_GPIO_8_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
-#define GLB_REG_GPIO_8_PD GLB_REG_GPIO_8_PD
-#define GLB_REG_GPIO_8_PD_POS (5)
-#define GLB_REG_GPIO_8_PD_LEN (1)
-#define GLB_REG_GPIO_8_PD_MSK \
- (((1 << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
-#define GLB_REG_GPIO_8_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
-#define GLB_REG_GPIO_8_FUNC_SEL GLB_REG_GPIO_8_FUNC_SEL
-#define GLB_REG_GPIO_8_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_8_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_8_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
-#define GLB_REG_GPIO_8_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS))
-#define GLB_REG_GPIO_9_IE GLB_REG_GPIO_9_IE
-#define GLB_REG_GPIO_9_IE_POS (16)
-#define GLB_REG_GPIO_9_IE_LEN (1)
-#define GLB_REG_GPIO_9_IE_MSK \
- (((1 << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
-#define GLB_REG_GPIO_9_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
-#define GLB_REG_GPIO_9_SMT GLB_REG_GPIO_9_SMT
-#define GLB_REG_GPIO_9_SMT_POS (17)
-#define GLB_REG_GPIO_9_SMT_LEN (1)
-#define GLB_REG_GPIO_9_SMT_MSK \
- (((1 << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
-#define GLB_REG_GPIO_9_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
-#define GLB_REG_GPIO_9_DRV GLB_REG_GPIO_9_DRV
-#define GLB_REG_GPIO_9_DRV_POS (18)
-#define GLB_REG_GPIO_9_DRV_LEN (2)
-#define GLB_REG_GPIO_9_DRV_MSK \
- (((1 << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
-#define GLB_REG_GPIO_9_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
-#define GLB_REG_GPIO_9_PU GLB_REG_GPIO_9_PU
-#define GLB_REG_GPIO_9_PU_POS (20)
-#define GLB_REG_GPIO_9_PU_LEN (1)
-#define GLB_REG_GPIO_9_PU_MSK \
- (((1 << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
-#define GLB_REG_GPIO_9_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
-#define GLB_REG_GPIO_9_PD GLB_REG_GPIO_9_PD
-#define GLB_REG_GPIO_9_PD_POS (21)
-#define GLB_REG_GPIO_9_PD_LEN (1)
-#define GLB_REG_GPIO_9_PD_MSK \
- (((1 << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
-#define GLB_REG_GPIO_9_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
-#define GLB_REG_GPIO_9_FUNC_SEL GLB_REG_GPIO_9_FUNC_SEL
-#define GLB_REG_GPIO_9_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_9_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_9_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
-#define GLB_REG_GPIO_9_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS))
-
-/* 0x114 : GPIO_CFGCTL5 */
-
-#define GLB_GPIO_CFGCTL5_OFFSET (0x114)
-#define GLB_REG_GPIO_10_IE GLB_REG_GPIO_10_IE
-#define GLB_REG_GPIO_10_IE_POS (0)
-#define GLB_REG_GPIO_10_IE_LEN (1)
-#define GLB_REG_GPIO_10_IE_MSK \
- (((1 << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
-#define GLB_REG_GPIO_10_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
-#define GLB_REG_GPIO_10_SMT GLB_REG_GPIO_10_SMT
-#define GLB_REG_GPIO_10_SMT_POS (1)
-#define GLB_REG_GPIO_10_SMT_LEN (1)
-#define GLB_REG_GPIO_10_SMT_MSK \
- (((1 << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
-#define GLB_REG_GPIO_10_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
-#define GLB_REG_GPIO_10_DRV GLB_REG_GPIO_10_DRV
-#define GLB_REG_GPIO_10_DRV_POS (2)
-#define GLB_REG_GPIO_10_DRV_LEN (2)
-#define GLB_REG_GPIO_10_DRV_MSK \
- (((1 << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
-#define GLB_REG_GPIO_10_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
-#define GLB_REG_GPIO_10_PU GLB_REG_GPIO_10_PU
-#define GLB_REG_GPIO_10_PU_POS (4)
-#define GLB_REG_GPIO_10_PU_LEN (1)
-#define GLB_REG_GPIO_10_PU_MSK \
- (((1 << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
-#define GLB_REG_GPIO_10_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
-#define GLB_REG_GPIO_10_PD GLB_REG_GPIO_10_PD
-#define GLB_REG_GPIO_10_PD_POS (5)
-#define GLB_REG_GPIO_10_PD_LEN (1)
-#define GLB_REG_GPIO_10_PD_MSK \
- (((1 << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
-#define GLB_REG_GPIO_10_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
-#define GLB_REG_GPIO_10_FUNC_SEL GLB_REG_GPIO_10_FUNC_SEL
-#define GLB_REG_GPIO_10_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_10_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_10_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
-#define GLB_REG_GPIO_10_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_10_FUNC_SEL_POS))
-#define GLB_REG_GPIO_11_IE GLB_REG_GPIO_11_IE
-#define GLB_REG_GPIO_11_IE_POS (16)
-#define GLB_REG_GPIO_11_IE_LEN (1)
-#define GLB_REG_GPIO_11_IE_MSK \
- (((1 << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
-#define GLB_REG_GPIO_11_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
-#define GLB_REG_GPIO_11_SMT GLB_REG_GPIO_11_SMT
-#define GLB_REG_GPIO_11_SMT_POS (17)
-#define GLB_REG_GPIO_11_SMT_LEN (1)
-#define GLB_REG_GPIO_11_SMT_MSK \
- (((1 << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
-#define GLB_REG_GPIO_11_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
-#define GLB_REG_GPIO_11_DRV GLB_REG_GPIO_11_DRV
-#define GLB_REG_GPIO_11_DRV_POS (18)
-#define GLB_REG_GPIO_11_DRV_LEN (2)
-#define GLB_REG_GPIO_11_DRV_MSK \
- (((1 << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
-#define GLB_REG_GPIO_11_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
-#define GLB_REG_GPIO_11_PU GLB_REG_GPIO_11_PU
-#define GLB_REG_GPIO_11_PU_POS (20)
-#define GLB_REG_GPIO_11_PU_LEN (1)
-#define GLB_REG_GPIO_11_PU_MSK \
- (((1 << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
-#define GLB_REG_GPIO_11_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
-#define GLB_REG_GPIO_11_PD GLB_REG_GPIO_11_PD
-#define GLB_REG_GPIO_11_PD_POS (21)
-#define GLB_REG_GPIO_11_PD_LEN (1)
-#define GLB_REG_GPIO_11_PD_MSK \
- (((1 << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
-#define GLB_REG_GPIO_11_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
-#define GLB_REG_GPIO_11_FUNC_SEL GLB_REG_GPIO_11_FUNC_SEL
-#define GLB_REG_GPIO_11_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_11_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_11_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
-#define GLB_REG_GPIO_11_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_11_FUNC_SEL_POS))
-
-/* 0x118 : GPIO_CFGCTL6 */
-
-#define GLB_GPIO_CFGCTL6_OFFSET (0x118)
-#define GLB_REG_GPIO_12_IE GLB_REG_GPIO_12_IE
-#define GLB_REG_GPIO_12_IE_POS (0)
-#define GLB_REG_GPIO_12_IE_LEN (1)
-#define GLB_REG_GPIO_12_IE_MSK \
- (((1 << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
-#define GLB_REG_GPIO_12_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
-#define GLB_REG_GPIO_12_SMT GLB_REG_GPIO_12_SMT
-#define GLB_REG_GPIO_12_SMT_POS (1)
-#define GLB_REG_GPIO_12_SMT_LEN (1)
-#define GLB_REG_GPIO_12_SMT_MSK \
- (((1 << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
-#define GLB_REG_GPIO_12_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
-#define GLB_REG_GPIO_12_DRV GLB_REG_GPIO_12_DRV
-#define GLB_REG_GPIO_12_DRV_POS (2)
-#define GLB_REG_GPIO_12_DRV_LEN (2)
-#define GLB_REG_GPIO_12_DRV_MSK \
- (((1 << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
-#define GLB_REG_GPIO_12_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
-#define GLB_REG_GPIO_12_PU GLB_REG_GPIO_12_PU
-#define GLB_REG_GPIO_12_PU_POS (4)
-#define GLB_REG_GPIO_12_PU_LEN (1)
-#define GLB_REG_GPIO_12_PU_MSK \
- (((1 << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
-#define GLB_REG_GPIO_12_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
-#define GLB_REG_GPIO_12_PD GLB_REG_GPIO_12_PD
-#define GLB_REG_GPIO_12_PD_POS (5)
-#define GLB_REG_GPIO_12_PD_LEN (1)
-#define GLB_REG_GPIO_12_PD_MSK \
- (((1 << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
-#define GLB_REG_GPIO_12_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
-#define GLB_REG_GPIO_12_FUNC_SEL GLB_REG_GPIO_12_FUNC_SEL
-#define GLB_REG_GPIO_12_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_12_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_12_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
-#define GLB_REG_GPIO_12_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_12_FUNC_SEL_POS))
-#define GLB_REG_GPIO_13_IE GLB_REG_GPIO_13_IE
-#define GLB_REG_GPIO_13_IE_POS (16)
-#define GLB_REG_GPIO_13_IE_LEN (1)
-#define GLB_REG_GPIO_13_IE_MSK \
- (((1 << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
-#define GLB_REG_GPIO_13_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
-#define GLB_REG_GPIO_13_SMT GLB_REG_GPIO_13_SMT
-#define GLB_REG_GPIO_13_SMT_POS (17)
-#define GLB_REG_GPIO_13_SMT_LEN (1)
-#define GLB_REG_GPIO_13_SMT_MSK \
- (((1 << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
-#define GLB_REG_GPIO_13_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
-#define GLB_REG_GPIO_13_DRV GLB_REG_GPIO_13_DRV
-#define GLB_REG_GPIO_13_DRV_POS (18)
-#define GLB_REG_GPIO_13_DRV_LEN (2)
-#define GLB_REG_GPIO_13_DRV_MSK \
- (((1 << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
-#define GLB_REG_GPIO_13_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
-#define GLB_REG_GPIO_13_PU GLB_REG_GPIO_13_PU
-#define GLB_REG_GPIO_13_PU_POS (20)
-#define GLB_REG_GPIO_13_PU_LEN (1)
-#define GLB_REG_GPIO_13_PU_MSK \
- (((1 << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
-#define GLB_REG_GPIO_13_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
-#define GLB_REG_GPIO_13_PD GLB_REG_GPIO_13_PD
-#define GLB_REG_GPIO_13_PD_POS (21)
-#define GLB_REG_GPIO_13_PD_LEN (1)
-#define GLB_REG_GPIO_13_PD_MSK \
- (((1 << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
-#define GLB_REG_GPIO_13_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
-#define GLB_REG_GPIO_13_FUNC_SEL GLB_REG_GPIO_13_FUNC_SEL
-#define GLB_REG_GPIO_13_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_13_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_13_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
-#define GLB_REG_GPIO_13_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_13_FUNC_SEL_POS))
-
-/* 0x11C : GPIO_CFGCTL7 */
-
-#define GLB_GPIO_CFGCTL7_OFFSET (0x11C)
-#define GLB_REG_GPIO_14_IE GLB_REG_GPIO_14_IE
-#define GLB_REG_GPIO_14_IE_POS (0)
-#define GLB_REG_GPIO_14_IE_LEN (1)
-#define GLB_REG_GPIO_14_IE_MSK \
- (((1 << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
-#define GLB_REG_GPIO_14_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
-#define GLB_REG_GPIO_14_SMT GLB_REG_GPIO_14_SMT
-#define GLB_REG_GPIO_14_SMT_POS (1)
-#define GLB_REG_GPIO_14_SMT_LEN (1)
-#define GLB_REG_GPIO_14_SMT_MSK \
- (((1 << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
-#define GLB_REG_GPIO_14_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
-#define GLB_REG_GPIO_14_DRV GLB_REG_GPIO_14_DRV
-#define GLB_REG_GPIO_14_DRV_POS (2)
-#define GLB_REG_GPIO_14_DRV_LEN (2)
-#define GLB_REG_GPIO_14_DRV_MSK \
- (((1 << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
-#define GLB_REG_GPIO_14_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
-#define GLB_REG_GPIO_14_PU GLB_REG_GPIO_14_PU
-#define GLB_REG_GPIO_14_PU_POS (4)
-#define GLB_REG_GPIO_14_PU_LEN (1)
-#define GLB_REG_GPIO_14_PU_MSK \
- (((1 << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
-#define GLB_REG_GPIO_14_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
-#define GLB_REG_GPIO_14_PD GLB_REG_GPIO_14_PD
-#define GLB_REG_GPIO_14_PD_POS (5)
-#define GLB_REG_GPIO_14_PD_LEN (1)
-#define GLB_REG_GPIO_14_PD_MSK \
- (((1 << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
-#define GLB_REG_GPIO_14_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
-#define GLB_REG_GPIO_14_FUNC_SEL GLB_REG_GPIO_14_FUNC_SEL
-#define GLB_REG_GPIO_14_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_14_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_14_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
-#define GLB_REG_GPIO_14_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_14_FUNC_SEL_POS))
-#define GLB_REG_GPIO_15_IE GLB_REG_GPIO_15_IE
-#define GLB_REG_GPIO_15_IE_POS (16)
-#define GLB_REG_GPIO_15_IE_LEN (1)
-#define GLB_REG_GPIO_15_IE_MSK \
- (((1 << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
-#define GLB_REG_GPIO_15_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
-#define GLB_REG_GPIO_15_SMT GLB_REG_GPIO_15_SMT
-#define GLB_REG_GPIO_15_SMT_POS (17)
-#define GLB_REG_GPIO_15_SMT_LEN (1)
-#define GLB_REG_GPIO_15_SMT_MSK \
- (((1 << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
-#define GLB_REG_GPIO_15_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
-#define GLB_REG_GPIO_15_DRV GLB_REG_GPIO_15_DRV
-#define GLB_REG_GPIO_15_DRV_POS (18)
-#define GLB_REG_GPIO_15_DRV_LEN (2)
-#define GLB_REG_GPIO_15_DRV_MSK \
- (((1 << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
-#define GLB_REG_GPIO_15_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
-#define GLB_REG_GPIO_15_PU GLB_REG_GPIO_15_PU
-#define GLB_REG_GPIO_15_PU_POS (20)
-#define GLB_REG_GPIO_15_PU_LEN (1)
-#define GLB_REG_GPIO_15_PU_MSK \
- (((1 << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
-#define GLB_REG_GPIO_15_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
-#define GLB_REG_GPIO_15_PD GLB_REG_GPIO_15_PD
-#define GLB_REG_GPIO_15_PD_POS (21)
-#define GLB_REG_GPIO_15_PD_LEN (1)
-#define GLB_REG_GPIO_15_PD_MSK \
- (((1 << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
-#define GLB_REG_GPIO_15_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
-#define GLB_REG_GPIO_15_FUNC_SEL GLB_REG_GPIO_15_FUNC_SEL
-#define GLB_REG_GPIO_15_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_15_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_15_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
-#define GLB_REG_GPIO_15_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_15_FUNC_SEL_POS))
-
-/* 0x120 : GPIO_CFGCTL8 */
-
-#define GLB_GPIO_CFGCTL8_OFFSET (0x120)
-#define GLB_REG_GPIO_16_IE GLB_REG_GPIO_16_IE
-#define GLB_REG_GPIO_16_IE_POS (0)
-#define GLB_REG_GPIO_16_IE_LEN (1)
-#define GLB_REG_GPIO_16_IE_MSK \
- (((1 << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
-#define GLB_REG_GPIO_16_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
-#define GLB_REG_GPIO_16_SMT GLB_REG_GPIO_16_SMT
-#define GLB_REG_GPIO_16_SMT_POS (1)
-#define GLB_REG_GPIO_16_SMT_LEN (1)
-#define GLB_REG_GPIO_16_SMT_MSK \
- (((1 << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
-#define GLB_REG_GPIO_16_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
-#define GLB_REG_GPIO_16_DRV GLB_REG_GPIO_16_DRV
-#define GLB_REG_GPIO_16_DRV_POS (2)
-#define GLB_REG_GPIO_16_DRV_LEN (2)
-#define GLB_REG_GPIO_16_DRV_MSK \
- (((1 << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
-#define GLB_REG_GPIO_16_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
-#define GLB_REG_GPIO_16_PU GLB_REG_GPIO_16_PU
-#define GLB_REG_GPIO_16_PU_POS (4)
-#define GLB_REG_GPIO_16_PU_LEN (1)
-#define GLB_REG_GPIO_16_PU_MSK \
- (((1 << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
-#define GLB_REG_GPIO_16_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
-#define GLB_REG_GPIO_16_PD GLB_REG_GPIO_16_PD
-#define GLB_REG_GPIO_16_PD_POS (5)
-#define GLB_REG_GPIO_16_PD_LEN (1)
-#define GLB_REG_GPIO_16_PD_MSK \
- (((1 << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
-#define GLB_REG_GPIO_16_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
-#define GLB_REG_GPIO_16_FUNC_SEL GLB_REG_GPIO_16_FUNC_SEL
-#define GLB_REG_GPIO_16_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_16_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_16_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
-#define GLB_REG_GPIO_16_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_16_FUNC_SEL_POS))
-#define GLB_REG_GPIO_17_IE GLB_REG_GPIO_17_IE
-#define GLB_REG_GPIO_17_IE_POS (16)
-#define GLB_REG_GPIO_17_IE_LEN (1)
-#define GLB_REG_GPIO_17_IE_MSK \
- (((1 << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
-#define GLB_REG_GPIO_17_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
-#define GLB_REG_GPIO_17_SMT GLB_REG_GPIO_17_SMT
-#define GLB_REG_GPIO_17_SMT_POS (17)
-#define GLB_REG_GPIO_17_SMT_LEN (1)
-#define GLB_REG_GPIO_17_SMT_MSK \
- (((1 << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
-#define GLB_REG_GPIO_17_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
-#define GLB_REG_GPIO_17_DRV GLB_REG_GPIO_17_DRV
-#define GLB_REG_GPIO_17_DRV_POS (18)
-#define GLB_REG_GPIO_17_DRV_LEN (2)
-#define GLB_REG_GPIO_17_DRV_MSK \
- (((1 << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
-#define GLB_REG_GPIO_17_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
-#define GLB_REG_GPIO_17_PU GLB_REG_GPIO_17_PU
-#define GLB_REG_GPIO_17_PU_POS (20)
-#define GLB_REG_GPIO_17_PU_LEN (1)
-#define GLB_REG_GPIO_17_PU_MSK \
- (((1 << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
-#define GLB_REG_GPIO_17_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
-#define GLB_REG_GPIO_17_PD GLB_REG_GPIO_17_PD
-#define GLB_REG_GPIO_17_PD_POS (21)
-#define GLB_REG_GPIO_17_PD_LEN (1)
-#define GLB_REG_GPIO_17_PD_MSK \
- (((1 << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
-#define GLB_REG_GPIO_17_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
-#define GLB_REG_GPIO_17_FUNC_SEL GLB_REG_GPIO_17_FUNC_SEL
-#define GLB_REG_GPIO_17_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_17_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_17_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
-#define GLB_REG_GPIO_17_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_17_FUNC_SEL_POS))
-
-/* 0x124 : GPIO_CFGCTL9 */
-
-#define GLB_GPIO_CFGCTL9_OFFSET (0x124)
-#define GLB_REG_GPIO_18_IE GLB_REG_GPIO_18_IE
-#define GLB_REG_GPIO_18_IE_POS (0)
-#define GLB_REG_GPIO_18_IE_LEN (1)
-#define GLB_REG_GPIO_18_IE_MSK \
- (((1 << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
-#define GLB_REG_GPIO_18_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
-#define GLB_REG_GPIO_18_SMT GLB_REG_GPIO_18_SMT
-#define GLB_REG_GPIO_18_SMT_POS (1)
-#define GLB_REG_GPIO_18_SMT_LEN (1)
-#define GLB_REG_GPIO_18_SMT_MSK \
- (((1 << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
-#define GLB_REG_GPIO_18_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
-#define GLB_REG_GPIO_18_DRV GLB_REG_GPIO_18_DRV
-#define GLB_REG_GPIO_18_DRV_POS (2)
-#define GLB_REG_GPIO_18_DRV_LEN (2)
-#define GLB_REG_GPIO_18_DRV_MSK \
- (((1 << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
-#define GLB_REG_GPIO_18_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
-#define GLB_REG_GPIO_18_PU GLB_REG_GPIO_18_PU
-#define GLB_REG_GPIO_18_PU_POS (4)
-#define GLB_REG_GPIO_18_PU_LEN (1)
-#define GLB_REG_GPIO_18_PU_MSK \
- (((1 << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
-#define GLB_REG_GPIO_18_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
-#define GLB_REG_GPIO_18_PD GLB_REG_GPIO_18_PD
-#define GLB_REG_GPIO_18_PD_POS (5)
-#define GLB_REG_GPIO_18_PD_LEN (1)
-#define GLB_REG_GPIO_18_PD_MSK \
- (((1 << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
-#define GLB_REG_GPIO_18_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
-#define GLB_REG_GPIO_18_FUNC_SEL GLB_REG_GPIO_18_FUNC_SEL
-#define GLB_REG_GPIO_18_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_18_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_18_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
-#define GLB_REG_GPIO_18_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_18_FUNC_SEL_POS))
-#define GLB_REG_GPIO_19_IE GLB_REG_GPIO_19_IE
-#define GLB_REG_GPIO_19_IE_POS (16)
-#define GLB_REG_GPIO_19_IE_LEN (1)
-#define GLB_REG_GPIO_19_IE_MSK \
- (((1 << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
-#define GLB_REG_GPIO_19_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
-#define GLB_REG_GPIO_19_SMT GLB_REG_GPIO_19_SMT
-#define GLB_REG_GPIO_19_SMT_POS (17)
-#define GLB_REG_GPIO_19_SMT_LEN (1)
-#define GLB_REG_GPIO_19_SMT_MSK \
- (((1 << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
-#define GLB_REG_GPIO_19_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
-#define GLB_REG_GPIO_19_DRV GLB_REG_GPIO_19_DRV
-#define GLB_REG_GPIO_19_DRV_POS (18)
-#define GLB_REG_GPIO_19_DRV_LEN (2)
-#define GLB_REG_GPIO_19_DRV_MSK \
- (((1 << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
-#define GLB_REG_GPIO_19_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
-#define GLB_REG_GPIO_19_PU GLB_REG_GPIO_19_PU
-#define GLB_REG_GPIO_19_PU_POS (20)
-#define GLB_REG_GPIO_19_PU_LEN (1)
-#define GLB_REG_GPIO_19_PU_MSK \
- (((1 << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
-#define GLB_REG_GPIO_19_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
-#define GLB_REG_GPIO_19_PD GLB_REG_GPIO_19_PD
-#define GLB_REG_GPIO_19_PD_POS (21)
-#define GLB_REG_GPIO_19_PD_LEN (1)
-#define GLB_REG_GPIO_19_PD_MSK \
- (((1 << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
-#define GLB_REG_GPIO_19_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
-#define GLB_REG_GPIO_19_FUNC_SEL GLB_REG_GPIO_19_FUNC_SEL
-#define GLB_REG_GPIO_19_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_19_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_19_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
-#define GLB_REG_GPIO_19_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_19_FUNC_SEL_POS))
-
-/* 0x128 : GPIO_CFGCTL10 */
-
-#define GLB_GPIO_CFGCTL10_OFFSET (0x128)
-#define GLB_REG_GPIO_20_IE GLB_REG_GPIO_20_IE
-#define GLB_REG_GPIO_20_IE_POS (0)
-#define GLB_REG_GPIO_20_IE_LEN (1)
-#define GLB_REG_GPIO_20_IE_MSK \
- (((1 << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
-#define GLB_REG_GPIO_20_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
-#define GLB_REG_GPIO_20_SMT GLB_REG_GPIO_20_SMT
-#define GLB_REG_GPIO_20_SMT_POS (1)
-#define GLB_REG_GPIO_20_SMT_LEN (1)
-#define GLB_REG_GPIO_20_SMT_MSK \
- (((1 << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
-#define GLB_REG_GPIO_20_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
-#define GLB_REG_GPIO_20_DRV GLB_REG_GPIO_20_DRV
-#define GLB_REG_GPIO_20_DRV_POS (2)
-#define GLB_REG_GPIO_20_DRV_LEN (2)
-#define GLB_REG_GPIO_20_DRV_MSK \
- (((1 << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
-#define GLB_REG_GPIO_20_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
-#define GLB_REG_GPIO_20_PU GLB_REG_GPIO_20_PU
-#define GLB_REG_GPIO_20_PU_POS (4)
-#define GLB_REG_GPIO_20_PU_LEN (1)
-#define GLB_REG_GPIO_20_PU_MSK \
- (((1 << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
-#define GLB_REG_GPIO_20_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
-#define GLB_REG_GPIO_20_PD GLB_REG_GPIO_20_PD
-#define GLB_REG_GPIO_20_PD_POS (5)
-#define GLB_REG_GPIO_20_PD_LEN (1)
-#define GLB_REG_GPIO_20_PD_MSK \
- (((1 << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
-#define GLB_REG_GPIO_20_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
-#define GLB_REG_GPIO_20_FUNC_SEL GLB_REG_GPIO_20_FUNC_SEL
-#define GLB_REG_GPIO_20_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_20_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_20_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
-#define GLB_REG_GPIO_20_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_20_FUNC_SEL_POS))
-#define GLB_REG_GPIO_21_IE GLB_REG_GPIO_21_IE
-#define GLB_REG_GPIO_21_IE_POS (16)
-#define GLB_REG_GPIO_21_IE_LEN (1)
-#define GLB_REG_GPIO_21_IE_MSK \
- (((1 << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
-#define GLB_REG_GPIO_21_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
-#define GLB_REG_GPIO_21_SMT GLB_REG_GPIO_21_SMT
-#define GLB_REG_GPIO_21_SMT_POS (17)
-#define GLB_REG_GPIO_21_SMT_LEN (1)
-#define GLB_REG_GPIO_21_SMT_MSK \
- (((1 << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
-#define GLB_REG_GPIO_21_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
-#define GLB_REG_GPIO_21_DRV GLB_REG_GPIO_21_DRV
-#define GLB_REG_GPIO_21_DRV_POS (18)
-#define GLB_REG_GPIO_21_DRV_LEN (2)
-#define GLB_REG_GPIO_21_DRV_MSK \
- (((1 << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
-#define GLB_REG_GPIO_21_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
-#define GLB_REG_GPIO_21_PU GLB_REG_GPIO_21_PU
-#define GLB_REG_GPIO_21_PU_POS (20)
-#define GLB_REG_GPIO_21_PU_LEN (1)
-#define GLB_REG_GPIO_21_PU_MSK \
- (((1 << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
-#define GLB_REG_GPIO_21_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
-#define GLB_REG_GPIO_21_PD GLB_REG_GPIO_21_PD
-#define GLB_REG_GPIO_21_PD_POS (21)
-#define GLB_REG_GPIO_21_PD_LEN (1)
-#define GLB_REG_GPIO_21_PD_MSK \
- (((1 << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
-#define GLB_REG_GPIO_21_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
-#define GLB_REG_GPIO_21_FUNC_SEL GLB_REG_GPIO_21_FUNC_SEL
-#define GLB_REG_GPIO_21_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_21_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_21_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
-#define GLB_REG_GPIO_21_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_21_FUNC_SEL_POS))
-
-/* 0x12C : GPIO_CFGCTL11 */
-
-#define GLB_GPIO_CFGCTL11_OFFSET (0x12C)
-#define GLB_REG_GPIO_22_IE GLB_REG_GPIO_22_IE
-#define GLB_REG_GPIO_22_IE_POS (0)
-#define GLB_REG_GPIO_22_IE_LEN (1)
-#define GLB_REG_GPIO_22_IE_MSK \
- (((1 << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
-#define GLB_REG_GPIO_22_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
-#define GLB_REG_GPIO_22_SMT GLB_REG_GPIO_22_SMT
-#define GLB_REG_GPIO_22_SMT_POS (1)
-#define GLB_REG_GPIO_22_SMT_LEN (1)
-#define GLB_REG_GPIO_22_SMT_MSK \
- (((1 << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
-#define GLB_REG_GPIO_22_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
-#define GLB_REG_GPIO_22_DRV GLB_REG_GPIO_22_DRV
-#define GLB_REG_GPIO_22_DRV_POS (2)
-#define GLB_REG_GPIO_22_DRV_LEN (2)
-#define GLB_REG_GPIO_22_DRV_MSK \
- (((1 << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
-#define GLB_REG_GPIO_22_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
-#define GLB_REG_GPIO_22_PU GLB_REG_GPIO_22_PU
-#define GLB_REG_GPIO_22_PU_POS (4)
-#define GLB_REG_GPIO_22_PU_LEN (1)
-#define GLB_REG_GPIO_22_PU_MSK \
- (((1 << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
-#define GLB_REG_GPIO_22_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
-#define GLB_REG_GPIO_22_PD GLB_REG_GPIO_22_PD
-#define GLB_REG_GPIO_22_PD_POS (5)
-#define GLB_REG_GPIO_22_PD_LEN (1)
-#define GLB_REG_GPIO_22_PD_MSK \
- (((1 << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
-#define GLB_REG_GPIO_22_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
-#define GLB_REG_GPIO_22_FUNC_SEL GLB_REG_GPIO_22_FUNC_SEL
-#define GLB_REG_GPIO_22_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_22_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_22_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
-#define GLB_REG_GPIO_22_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_22_FUNC_SEL_POS))
-#define GLB_REG_GPIO_23_IE GLB_REG_GPIO_23_IE
-#define GLB_REG_GPIO_23_IE_POS (16)
-#define GLB_REG_GPIO_23_IE_LEN (1)
-#define GLB_REG_GPIO_23_IE_MSK \
- (((1 << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
-#define GLB_REG_GPIO_23_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
-#define GLB_REG_GPIO_23_SMT GLB_REG_GPIO_23_SMT
-#define GLB_REG_GPIO_23_SMT_POS (17)
-#define GLB_REG_GPIO_23_SMT_LEN (1)
-#define GLB_REG_GPIO_23_SMT_MSK \
- (((1 << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
-#define GLB_REG_GPIO_23_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
-#define GLB_REG_GPIO_23_DRV GLB_REG_GPIO_23_DRV
-#define GLB_REG_GPIO_23_DRV_POS (18)
-#define GLB_REG_GPIO_23_DRV_LEN (2)
-#define GLB_REG_GPIO_23_DRV_MSK \
- (((1 << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
-#define GLB_REG_GPIO_23_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
-#define GLB_REG_GPIO_23_PU GLB_REG_GPIO_23_PU
-#define GLB_REG_GPIO_23_PU_POS (20)
-#define GLB_REG_GPIO_23_PU_LEN (1)
-#define GLB_REG_GPIO_23_PU_MSK \
- (((1 << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
-#define GLB_REG_GPIO_23_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
-#define GLB_REG_GPIO_23_PD GLB_REG_GPIO_23_PD
-#define GLB_REG_GPIO_23_PD_POS (21)
-#define GLB_REG_GPIO_23_PD_LEN (1)
-#define GLB_REG_GPIO_23_PD_MSK \
- (((1 << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
-#define GLB_REG_GPIO_23_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
-
-/* 0x130 : GPIO_CFGCTL12 */
-
-#define GLB_GPIO_CFGCTL12_OFFSET (0x130)
-#define GLB_REG_GPIO_24_IE GLB_REG_GPIO_24_IE
-#define GLB_REG_GPIO_24_IE_POS (0)
-#define GLB_REG_GPIO_24_IE_LEN (1)
-#define GLB_REG_GPIO_24_IE_MSK \
- (((1 << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
-#define GLB_REG_GPIO_24_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
-#define GLB_REG_GPIO_24_SMT GLB_REG_GPIO_24_SMT
-#define GLB_REG_GPIO_24_SMT_POS (1)
-#define GLB_REG_GPIO_24_SMT_LEN (1)
-#define GLB_REG_GPIO_24_SMT_MSK \
- (((1 << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
-#define GLB_REG_GPIO_24_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
-#define GLB_REG_GPIO_24_DRV GLB_REG_GPIO_24_DRV
-#define GLB_REG_GPIO_24_DRV_POS (2)
-#define GLB_REG_GPIO_24_DRV_LEN (2)
-#define GLB_REG_GPIO_24_DRV_MSK \
- (((1 << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
-#define GLB_REG_GPIO_24_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
-#define GLB_REG_GPIO_24_PU GLB_REG_GPIO_24_PU
-#define GLB_REG_GPIO_24_PU_POS (4)
-#define GLB_REG_GPIO_24_PU_LEN (1)
-#define GLB_REG_GPIO_24_PU_MSK \
- (((1 << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
-#define GLB_REG_GPIO_24_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
-#define GLB_REG_GPIO_24_PD GLB_REG_GPIO_24_PD
-#define GLB_REG_GPIO_24_PD_POS (5)
-#define GLB_REG_GPIO_24_PD_LEN (1)
-#define GLB_REG_GPIO_24_PD_MSK \
- (((1 << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
-#define GLB_REG_GPIO_24_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
-#define GLB_REG_GPIO_25_IE GLB_REG_GPIO_25_IE
-#define GLB_REG_GPIO_25_IE_POS (16)
-#define GLB_REG_GPIO_25_IE_LEN (1)
-#define GLB_REG_GPIO_25_IE_MSK \
- (((1 << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
-#define GLB_REG_GPIO_25_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
-#define GLB_REG_GPIO_25_SMT GLB_REG_GPIO_25_SMT
-#define GLB_REG_GPIO_25_SMT_POS (17)
-#define GLB_REG_GPIO_25_SMT_LEN (1)
-#define GLB_REG_GPIO_25_SMT_MSK \
- (((1 << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
-#define GLB_REG_GPIO_25_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
-#define GLB_REG_GPIO_25_DRV GLB_REG_GPIO_25_DRV
-#define GLB_REG_GPIO_25_DRV_POS (18)
-#define GLB_REG_GPIO_25_DRV_LEN (2)
-#define GLB_REG_GPIO_25_DRV_MSK \
- (((1 << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
-#define GLB_REG_GPIO_25_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
-#define GLB_REG_GPIO_25_PU GLB_REG_GPIO_25_PU
-#define GLB_REG_GPIO_25_PU_POS (20)
-#define GLB_REG_GPIO_25_PU_LEN (1)
-#define GLB_REG_GPIO_25_PU_MSK \
- (((1 << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
-#define GLB_REG_GPIO_25_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
-#define GLB_REG_GPIO_25_PD GLB_REG_GPIO_25_PD
-#define GLB_REG_GPIO_25_PD_POS (21)
-#define GLB_REG_GPIO_25_PD_LEN (1)
-#define GLB_REG_GPIO_25_PD_MSK \
- (((1 << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
-#define GLB_REG_GPIO_25_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
-
-/* 0x134 : GPIO_CFGCTL13 */
-
-#define GLB_GPIO_CFGCTL13_OFFSET (0x134)
-#define GLB_REG_GPIO_26_IE GLB_REG_GPIO_26_IE
-#define GLB_REG_GPIO_26_IE_POS (0)
-#define GLB_REG_GPIO_26_IE_LEN (1)
-#define GLB_REG_GPIO_26_IE_MSK \
- (((1 << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
-#define GLB_REG_GPIO_26_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
-#define GLB_REG_GPIO_26_SMT GLB_REG_GPIO_26_SMT
-#define GLB_REG_GPIO_26_SMT_POS (1)
-#define GLB_REG_GPIO_26_SMT_LEN (1)
-#define GLB_REG_GPIO_26_SMT_MSK \
- (((1 << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
-#define GLB_REG_GPIO_26_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
-#define GLB_REG_GPIO_26_DRV GLB_REG_GPIO_26_DRV
-#define GLB_REG_GPIO_26_DRV_POS (2)
-#define GLB_REG_GPIO_26_DRV_LEN (2)
-#define GLB_REG_GPIO_26_DRV_MSK \
- (((1 << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
-#define GLB_REG_GPIO_26_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
-#define GLB_REG_GPIO_26_PU GLB_REG_GPIO_26_PU
-#define GLB_REG_GPIO_26_PU_POS (4)
-#define GLB_REG_GPIO_26_PU_LEN (1)
-#define GLB_REG_GPIO_26_PU_MSK \
- (((1 << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
-#define GLB_REG_GPIO_26_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
-#define GLB_REG_GPIO_26_PD GLB_REG_GPIO_26_PD
-#define GLB_REG_GPIO_26_PD_POS (5)
-#define GLB_REG_GPIO_26_PD_LEN (1)
-#define GLB_REG_GPIO_26_PD_MSK \
- (((1 << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
-#define GLB_REG_GPIO_26_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
-#define GLB_REG_GPIO_27_IE GLB_REG_GPIO_27_IE
-#define GLB_REG_GPIO_27_IE_POS (16)
-#define GLB_REG_GPIO_27_IE_LEN (1)
-#define GLB_REG_GPIO_27_IE_MSK \
- (((1 << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
-#define GLB_REG_GPIO_27_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
-#define GLB_REG_GPIO_27_SMT GLB_REG_GPIO_27_SMT
-#define GLB_REG_GPIO_27_SMT_POS (17)
-#define GLB_REG_GPIO_27_SMT_LEN (1)
-#define GLB_REG_GPIO_27_SMT_MSK \
- (((1 << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
-#define GLB_REG_GPIO_27_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
-#define GLB_REG_GPIO_27_DRV GLB_REG_GPIO_27_DRV
-#define GLB_REG_GPIO_27_DRV_POS (18)
-#define GLB_REG_GPIO_27_DRV_LEN (2)
-#define GLB_REG_GPIO_27_DRV_MSK \
- (((1 << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
-#define GLB_REG_GPIO_27_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
-#define GLB_REG_GPIO_27_PU GLB_REG_GPIO_27_PU
-#define GLB_REG_GPIO_27_PU_POS (20)
-#define GLB_REG_GPIO_27_PU_LEN (1)
-#define GLB_REG_GPIO_27_PU_MSK \
- (((1 << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
-#define GLB_REG_GPIO_27_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
-#define GLB_REG_GPIO_27_PD GLB_REG_GPIO_27_PD
-#define GLB_REG_GPIO_27_PD_POS (21)
-#define GLB_REG_GPIO_27_PD_LEN (1)
-#define GLB_REG_GPIO_27_PD_MSK \
- (((1 << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
-#define GLB_REG_GPIO_27_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
-
-/* 0x138 : GPIO_CFGCTL14 */
-
-#define GLB_GPIO_CFGCTL14_OFFSET (0x138)
-#define GLB_REG_GPIO_28_IE GLB_REG_GPIO_28_IE
-#define GLB_REG_GPIO_28_IE_POS (0)
-#define GLB_REG_GPIO_28_IE_LEN (1)
-#define GLB_REG_GPIO_28_IE_MSK \
- (((1 << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
-#define GLB_REG_GPIO_28_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
-#define GLB_REG_GPIO_28_SMT GLB_REG_GPIO_28_SMT
-#define GLB_REG_GPIO_28_SMT_POS (1)
-#define GLB_REG_GPIO_28_SMT_LEN (1)
-#define GLB_REG_GPIO_28_SMT_MSK \
- (((1 << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
-#define GLB_REG_GPIO_28_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
-#define GLB_REG_GPIO_28_DRV GLB_REG_GPIO_28_DRV
-#define GLB_REG_GPIO_28_DRV_POS (2)
-#define GLB_REG_GPIO_28_DRV_LEN (2)
-#define GLB_REG_GPIO_28_DRV_MSK \
- (((1 << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
-#define GLB_REG_GPIO_28_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
-#define GLB_REG_GPIO_28_PU GLB_REG_GPIO_28_PU
-#define GLB_REG_GPIO_28_PU_POS (4)
-#define GLB_REG_GPIO_28_PU_LEN (1)
-#define GLB_REG_GPIO_28_PU_MSK \
- (((1 << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
-#define GLB_REG_GPIO_28_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
-#define GLB_REG_GPIO_28_PD GLB_REG_GPIO_28_PD
-#define GLB_REG_GPIO_28_PD_POS (5)
-#define GLB_REG_GPIO_28_PD_LEN (1)
-#define GLB_REG_GPIO_28_PD_MSK \
- (((1 << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
-#define GLB_REG_GPIO_28_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
-
-/* 0x180 : GPIO_CFGCTL30 */
-
-#define GLB_GPIO_CFGCTL30_OFFSET (0x180)
-#define GLB_REG_GPIO_0_I GLB_REG_GPIO_0_I
-#define GLB_REG_GPIO_0_I_POS (0)
-#define GLB_REG_GPIO_0_I_LEN (1)
-#define GLB_REG_GPIO_0_I_MSK \
- (((1 << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
-#define GLB_REG_GPIO_0_I_UMSK \
- (~(((1 << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
-#define GLB_REG_GPIO_1_I GLB_REG_GPIO_1_I
-#define GLB_REG_GPIO_1_I_POS (1)
-#define GLB_REG_GPIO_1_I_LEN (1)
-#define GLB_REG_GPIO_1_I_MSK \
- (((1 << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
-#define GLB_REG_GPIO_1_I_UMSK \
- (~(((1 << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
-#define GLB_REG_GPIO_2_I GLB_REG_GPIO_2_I
-#define GLB_REG_GPIO_2_I_POS (2)
-#define GLB_REG_GPIO_2_I_LEN (1)
-#define GLB_REG_GPIO_2_I_MSK \
- (((1 << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
-#define GLB_REG_GPIO_2_I_UMSK \
- (~(((1 << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
-#define GLB_REG_GPIO_3_I GLB_REG_GPIO_3_I
-#define GLB_REG_GPIO_3_I_POS (3)
-#define GLB_REG_GPIO_3_I_LEN (1)
-#define GLB_REG_GPIO_3_I_MSK \
- (((1 << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
-#define GLB_REG_GPIO_3_I_UMSK \
- (~(((1 << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
-#define GLB_REG_GPIO_4_I GLB_REG_GPIO_4_I
-#define GLB_REG_GPIO_4_I_POS (4)
-#define GLB_REG_GPIO_4_I_LEN (1)
-#define GLB_REG_GPIO_4_I_MSK \
- (((1 << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
-#define GLB_REG_GPIO_4_I_UMSK \
- (~(((1 << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
-#define GLB_REG_GPIO_5_I GLB_REG_GPIO_5_I
-#define GLB_REG_GPIO_5_I_POS (5)
-#define GLB_REG_GPIO_5_I_LEN (1)
-#define GLB_REG_GPIO_5_I_MSK \
- (((1 << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
-#define GLB_REG_GPIO_5_I_UMSK \
- (~(((1 << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
-#define GLB_REG_GPIO_6_I GLB_REG_GPIO_6_I
-#define GLB_REG_GPIO_6_I_POS (6)
-#define GLB_REG_GPIO_6_I_LEN (1)
-#define GLB_REG_GPIO_6_I_MSK \
- (((1 << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
-#define GLB_REG_GPIO_6_I_UMSK \
- (~(((1 << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
-#define GLB_REG_GPIO_7_I GLB_REG_GPIO_7_I
-#define GLB_REG_GPIO_7_I_POS (7)
-#define GLB_REG_GPIO_7_I_LEN (1)
-#define GLB_REG_GPIO_7_I_MSK \
- (((1 << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
-#define GLB_REG_GPIO_7_I_UMSK \
- (~(((1 << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
-#define GLB_REG_GPIO_8_I GLB_REG_GPIO_8_I
-#define GLB_REG_GPIO_8_I_POS (8)
-#define GLB_REG_GPIO_8_I_LEN (1)
-#define GLB_REG_GPIO_8_I_MSK \
- (((1 << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
-#define GLB_REG_GPIO_8_I_UMSK \
- (~(((1 << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
-#define GLB_REG_GPIO_9_I GLB_REG_GPIO_9_I
-#define GLB_REG_GPIO_9_I_POS (9)
-#define GLB_REG_GPIO_9_I_LEN (1)
-#define GLB_REG_GPIO_9_I_MSK \
- (((1 << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
-#define GLB_REG_GPIO_9_I_UMSK \
- (~(((1 << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
-#define GLB_REG_GPIO_10_I GLB_REG_GPIO_10_I
-#define GLB_REG_GPIO_10_I_POS (10)
-#define GLB_REG_GPIO_10_I_LEN (1)
-#define GLB_REG_GPIO_10_I_MSK \
- (((1 << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
-#define GLB_REG_GPIO_10_I_UMSK \
- (~(((1 << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
-#define GLB_REG_GPIO_11_I GLB_REG_GPIO_11_I
-#define GLB_REG_GPIO_11_I_POS (11)
-#define GLB_REG_GPIO_11_I_LEN (1)
-#define GLB_REG_GPIO_11_I_MSK \
- (((1 << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
-#define GLB_REG_GPIO_11_I_UMSK \
- (~(((1 << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
-#define GLB_REG_GPIO_12_I GLB_REG_GPIO_12_I
-#define GLB_REG_GPIO_12_I_POS (12)
-#define GLB_REG_GPIO_12_I_LEN (1)
-#define GLB_REG_GPIO_12_I_MSK \
- (((1 << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
-#define GLB_REG_GPIO_12_I_UMSK \
- (~(((1 << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
-#define GLB_REG_GPIO_13_I GLB_REG_GPIO_13_I
-#define GLB_REG_GPIO_13_I_POS (13)
-#define GLB_REG_GPIO_13_I_LEN (1)
-#define GLB_REG_GPIO_13_I_MSK \
- (((1 << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
-#define GLB_REG_GPIO_13_I_UMSK \
- (~(((1 << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
-#define GLB_REG_GPIO_14_I GLB_REG_GPIO_14_I
-#define GLB_REG_GPIO_14_I_POS (14)
-#define GLB_REG_GPIO_14_I_LEN (1)
-#define GLB_REG_GPIO_14_I_MSK \
- (((1 << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
-#define GLB_REG_GPIO_14_I_UMSK \
- (~(((1 << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
-#define GLB_REG_GPIO_15_I GLB_REG_GPIO_15_I
-#define GLB_REG_GPIO_15_I_POS (15)
-#define GLB_REG_GPIO_15_I_LEN (1)
-#define GLB_REG_GPIO_15_I_MSK \
- (((1 << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
-#define GLB_REG_GPIO_15_I_UMSK \
- (~(((1 << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
-#define GLB_REG_GPIO_16_I GLB_REG_GPIO_16_I
-#define GLB_REG_GPIO_16_I_POS (16)
-#define GLB_REG_GPIO_16_I_LEN (1)
-#define GLB_REG_GPIO_16_I_MSK \
- (((1 << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
-#define GLB_REG_GPIO_16_I_UMSK \
- (~(((1 << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
-#define GLB_REG_GPIO_17_I GLB_REG_GPIO_17_I
-#define GLB_REG_GPIO_17_I_POS (17)
-#define GLB_REG_GPIO_17_I_LEN (1)
-#define GLB_REG_GPIO_17_I_MSK \
- (((1 << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
-#define GLB_REG_GPIO_17_I_UMSK \
- (~(((1 << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
-#define GLB_REG_GPIO_18_I GLB_REG_GPIO_18_I
-#define GLB_REG_GPIO_18_I_POS (18)
-#define GLB_REG_GPIO_18_I_LEN (1)
-#define GLB_REG_GPIO_18_I_MSK \
- (((1 << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
-#define GLB_REG_GPIO_18_I_UMSK \
- (~(((1 << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
-#define GLB_REG_GPIO_19_I GLB_REG_GPIO_19_I
-#define GLB_REG_GPIO_19_I_POS (19)
-#define GLB_REG_GPIO_19_I_LEN (1)
-#define GLB_REG_GPIO_19_I_MSK \
- (((1 << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
-#define GLB_REG_GPIO_19_I_UMSK \
- (~(((1 << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
-#define GLB_REG_GPIO_20_I GLB_REG_GPIO_20_I
-#define GLB_REG_GPIO_20_I_POS (20)
-#define GLB_REG_GPIO_20_I_LEN (1)
-#define GLB_REG_GPIO_20_I_MSK \
- (((1 << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
-#define GLB_REG_GPIO_20_I_UMSK \
- (~(((1 << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
-#define GLB_REG_GPIO_21_I GLB_REG_GPIO_21_I
-#define GLB_REG_GPIO_21_I_POS (21)
-#define GLB_REG_GPIO_21_I_LEN (1)
-#define GLB_REG_GPIO_21_I_MSK \
- (((1 << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
-#define GLB_REG_GPIO_21_I_UMSK \
- (~(((1 << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
-#define GLB_REG_GPIO_22_I GLB_REG_GPIO_22_I
-#define GLB_REG_GPIO_22_I_POS (22)
-#define GLB_REG_GPIO_22_I_LEN (1)
-#define GLB_REG_GPIO_22_I_MSK \
- (((1 << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
-#define GLB_REG_GPIO_22_I_UMSK \
- (~(((1 << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
-
-/* 0x184 : GPIO_CFGCTL31 */
-
-#define GLB_GPIO_CFGCTL31_OFFSET (0x184)
-
-/* 0x188 : GPIO_CFGCTL32 */
-
-#define GLB_GPIO_CFGCTL32_OFFSET (0x188)
-#define GLB_REG_GPIO_0_O GLB_REG_GPIO_0_O
-#define GLB_REG_GPIO_0_O_POS (0)
-#define GLB_REG_GPIO_0_O_LEN (1)
-#define GLB_REG_GPIO_0_O_MSK \
- (((1 << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
-#define GLB_REG_GPIO_0_O_UMSK \
- (~(((1 << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
-#define GLB_REG_GPIO_1_O GLB_REG_GPIO_1_O
-#define GLB_REG_GPIO_1_O_POS (1)
-#define GLB_REG_GPIO_1_O_LEN (1)
-#define GLB_REG_GPIO_1_O_MSK \
- (((1 << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
-#define GLB_REG_GPIO_1_O_UMSK \
- (~(((1 << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
-#define GLB_REG_GPIO_2_O GLB_REG_GPIO_2_O
-#define GLB_REG_GPIO_2_O_POS (2)
-#define GLB_REG_GPIO_2_O_LEN (1)
-#define GLB_REG_GPIO_2_O_MSK \
- (((1 << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
-#define GLB_REG_GPIO_2_O_UMSK \
- (~(((1 << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
-#define GLB_REG_GPIO_3_O GLB_REG_GPIO_3_O
-#define GLB_REG_GPIO_3_O_POS (3)
-#define GLB_REG_GPIO_3_O_LEN (1)
-#define GLB_REG_GPIO_3_O_MSK \
- (((1 << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
-#define GLB_REG_GPIO_3_O_UMSK \
- (~(((1 << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
-#define GLB_REG_GPIO_4_O GLB_REG_GPIO_4_O
-#define GLB_REG_GPIO_4_O_POS (4)
-#define GLB_REG_GPIO_4_O_LEN (1)
-#define GLB_REG_GPIO_4_O_MSK \
- (((1 << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
-#define GLB_REG_GPIO_4_O_UMSK \
- (~(((1 << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
-#define GLB_REG_GPIO_5_O GLB_REG_GPIO_5_O
-#define GLB_REG_GPIO_5_O_POS (5)
-#define GLB_REG_GPIO_5_O_LEN (1)
-#define GLB_REG_GPIO_5_O_MSK \
- (((1 << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
-#define GLB_REG_GPIO_5_O_UMSK \
- (~(((1 << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
-#define GLB_REG_GPIO_6_O GLB_REG_GPIO_6_O
-#define GLB_REG_GPIO_6_O_POS (6)
-#define GLB_REG_GPIO_6_O_LEN (1)
-#define GLB_REG_GPIO_6_O_MSK \
- (((1 << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
-#define GLB_REG_GPIO_6_O_UMSK \
- (~(((1 << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
-#define GLB_REG_GPIO_7_O GLB_REG_GPIO_7_O
-#define GLB_REG_GPIO_7_O_POS (7)
-#define GLB_REG_GPIO_7_O_LEN (1)
-#define GLB_REG_GPIO_7_O_MSK \
- (((1 << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
-#define GLB_REG_GPIO_7_O_UMSK \
- (~(((1 << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
-#define GLB_REG_GPIO_8_O GLB_REG_GPIO_8_O
-#define GLB_REG_GPIO_8_O_POS (8)
-#define GLB_REG_GPIO_8_O_LEN (1)
-#define GLB_REG_GPIO_8_O_MSK \
- (((1 << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
-#define GLB_REG_GPIO_8_O_UMSK \
- (~(((1 << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
-#define GLB_REG_GPIO_9_O GLB_REG_GPIO_9_O
-#define GLB_REG_GPIO_9_O_POS (9)
-#define GLB_REG_GPIO_9_O_LEN (1)
-#define GLB_REG_GPIO_9_O_MSK \
- (((1 << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
-#define GLB_REG_GPIO_9_O_UMSK \
- (~(((1 << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
-#define GLB_REG_GPIO_10_O GLB_REG_GPIO_10_O
-#define GLB_REG_GPIO_10_O_POS (10)
-#define GLB_REG_GPIO_10_O_LEN (1)
-#define GLB_REG_GPIO_10_O_MSK \
- (((1 << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
-#define GLB_REG_GPIO_10_O_UMSK \
- (~(((1 << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
-#define GLB_REG_GPIO_11_O GLB_REG_GPIO_11_O
-#define GLB_REG_GPIO_11_O_POS (11)
-#define GLB_REG_GPIO_11_O_LEN (1)
-#define GLB_REG_GPIO_11_O_MSK \
- (((1 << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
-#define GLB_REG_GPIO_11_O_UMSK \
- (~(((1 << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
-#define GLB_REG_GPIO_12_O GLB_REG_GPIO_12_O
-#define GLB_REG_GPIO_12_O_POS (12)
-#define GLB_REG_GPIO_12_O_LEN (1)
-#define GLB_REG_GPIO_12_O_MSK \
- (((1 << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
-#define GLB_REG_GPIO_12_O_UMSK \
- (~(((1 << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
-#define GLB_REG_GPIO_13_O GLB_REG_GPIO_13_O
-#define GLB_REG_GPIO_13_O_POS (13)
-#define GLB_REG_GPIO_13_O_LEN (1)
-#define GLB_REG_GPIO_13_O_MSK \
- (((1 << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
-#define GLB_REG_GPIO_13_O_UMSK \
- (~(((1 << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
-#define GLB_REG_GPIO_14_O GLB_REG_GPIO_14_O
-#define GLB_REG_GPIO_14_O_POS (14)
-#define GLB_REG_GPIO_14_O_LEN (1)
-#define GLB_REG_GPIO_14_O_MSK \
- (((1 << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
-#define GLB_REG_GPIO_14_O_UMSK \
- (~(((1 << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
-#define GLB_REG_GPIO_15_O GLB_REG_GPIO_15_O
-#define GLB_REG_GPIO_15_O_POS (15)
-#define GLB_REG_GPIO_15_O_LEN (1)
-#define GLB_REG_GPIO_15_O_MSK \
- (((1 << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
-#define GLB_REG_GPIO_15_O_UMSK \
- (~(((1 << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
-#define GLB_REG_GPIO_16_O GLB_REG_GPIO_16_O
-#define GLB_REG_GPIO_16_O_POS (16)
-#define GLB_REG_GPIO_16_O_LEN (1)
-#define GLB_REG_GPIO_16_O_MSK \
- (((1 << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
-#define GLB_REG_GPIO_16_O_UMSK \
- (~(((1 << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
-#define GLB_REG_GPIO_17_O GLB_REG_GPIO_17_O
-#define GLB_REG_GPIO_17_O_POS (17)
-#define GLB_REG_GPIO_17_O_LEN (1)
-#define GLB_REG_GPIO_17_O_MSK \
- (((1 << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
-#define GLB_REG_GPIO_17_O_UMSK \
- (~(((1 << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
-#define GLB_REG_GPIO_18_O GLB_REG_GPIO_18_O
-#define GLB_REG_GPIO_18_O_POS (18)
-#define GLB_REG_GPIO_18_O_LEN (1)
-#define GLB_REG_GPIO_18_O_MSK \
- (((1 << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
-#define GLB_REG_GPIO_18_O_UMSK \
- (~(((1 << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
-#define GLB_REG_GPIO_19_O GLB_REG_GPIO_19_O
-#define GLB_REG_GPIO_19_O_POS (19)
-#define GLB_REG_GPIO_19_O_LEN (1)
-#define GLB_REG_GPIO_19_O_MSK \
- (((1 << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
-#define GLB_REG_GPIO_19_O_UMSK \
- (~(((1 << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
-#define GLB_REG_GPIO_20_O GLB_REG_GPIO_20_O
-#define GLB_REG_GPIO_20_O_POS (20)
-#define GLB_REG_GPIO_20_O_LEN (1)
-#define GLB_REG_GPIO_20_O_MSK \
- (((1 << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
-#define GLB_REG_GPIO_20_O_UMSK \
- (~(((1 << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
-#define GLB_REG_GPIO_21_O GLB_REG_GPIO_21_O
-#define GLB_REG_GPIO_21_O_POS (21)
-#define GLB_REG_GPIO_21_O_LEN (1)
-#define GLB_REG_GPIO_21_O_MSK \
- (((1 << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
-#define GLB_REG_GPIO_21_O_UMSK \
- (~(((1 << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
-#define GLB_REG_GPIO_22_O GLB_REG_GPIO_22_O
-#define GLB_REG_GPIO_22_O_POS (22)
-#define GLB_REG_GPIO_22_O_LEN (1)
-#define GLB_REG_GPIO_22_O_MSK \
- (((1 << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
-#define GLB_REG_GPIO_22_O_UMSK \
- (~(((1 << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
-
-/* 0x18C : GPIO_CFGCTL33 */
-
-#define GLB_GPIO_CFGCTL33_OFFSET (0x18C)
-
-/* 0x190 : GPIO_CFGCTL34 */
-
-#define GLB_GPIO_CFGCTL34_OFFSET (0x190)
-#define GLB_REG_GPIO_0_OE GLB_REG_GPIO_0_OE
-#define GLB_REG_GPIO_0_OE_POS (0)
-#define GLB_REG_GPIO_0_OE_LEN (1)
-#define GLB_REG_GPIO_0_OE_MSK \
- (((1 << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
-#define GLB_REG_GPIO_0_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
-#define GLB_REG_GPIO_1_OE GLB_REG_GPIO_1_OE
-#define GLB_REG_GPIO_1_OE_POS (1)
-#define GLB_REG_GPIO_1_OE_LEN (1)
-#define GLB_REG_GPIO_1_OE_MSK \
- (((1 << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
-#define GLB_REG_GPIO_1_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
-#define GLB_REG_GPIO_2_OE GLB_REG_GPIO_2_OE
-#define GLB_REG_GPIO_2_OE_POS (2)
-#define GLB_REG_GPIO_2_OE_LEN (1)
-#define GLB_REG_GPIO_2_OE_MSK \
- (((1 << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
-#define GLB_REG_GPIO_2_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
-#define GLB_REG_GPIO_3_OE GLB_REG_GPIO_3_OE
-#define GLB_REG_GPIO_3_OE_POS (3)
-#define GLB_REG_GPIO_3_OE_LEN (1)
-#define GLB_REG_GPIO_3_OE_MSK \
- (((1 << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
-#define GLB_REG_GPIO_3_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
-#define GLB_REG_GPIO_4_OE GLB_REG_GPIO_4_OE
-#define GLB_REG_GPIO_4_OE_POS (4)
-#define GLB_REG_GPIO_4_OE_LEN (1)
-#define GLB_REG_GPIO_4_OE_MSK \
- (((1 << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
-#define GLB_REG_GPIO_4_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
-#define GLB_REG_GPIO_5_OE GLB_REG_GPIO_5_OE
-#define GLB_REG_GPIO_5_OE_POS (5)
-#define GLB_REG_GPIO_5_OE_LEN (1)
-#define GLB_REG_GPIO_5_OE_MSK \
- (((1 << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
-#define GLB_REG_GPIO_5_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
-#define GLB_REG_GPIO_6_OE GLB_REG_GPIO_6_OE
-#define GLB_REG_GPIO_6_OE_POS (6)
-#define GLB_REG_GPIO_6_OE_LEN (1)
-#define GLB_REG_GPIO_6_OE_MSK \
- (((1 << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
-#define GLB_REG_GPIO_6_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
-#define GLB_REG_GPIO_7_OE GLB_REG_GPIO_7_OE
-#define GLB_REG_GPIO_7_OE_POS (7)
-#define GLB_REG_GPIO_7_OE_LEN (1)
-#define GLB_REG_GPIO_7_OE_MSK \
- (((1 << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
-#define GLB_REG_GPIO_7_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
-#define GLB_REG_GPIO_8_OE GLB_REG_GPIO_8_OE
-#define GLB_REG_GPIO_8_OE_POS (8)
-#define GLB_REG_GPIO_8_OE_LEN (1)
-#define GLB_REG_GPIO_8_OE_MSK \
- (((1 << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
-#define GLB_REG_GPIO_8_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
-#define GLB_REG_GPIO_9_OE GLB_REG_GPIO_9_OE
-#define GLB_REG_GPIO_9_OE_POS (9)
-#define GLB_REG_GPIO_9_OE_LEN (1)
-#define GLB_REG_GPIO_9_OE_MSK \
- (((1 << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
-#define GLB_REG_GPIO_9_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
-#define GLB_REG_GPIO_10_OE GLB_REG_GPIO_10_OE
-#define GLB_REG_GPIO_10_OE_POS (10)
-#define GLB_REG_GPIO_10_OE_LEN (1)
-#define GLB_REG_GPIO_10_OE_MSK \
- (((1 << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
-#define GLB_REG_GPIO_10_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
-#define GLB_REG_GPIO_11_OE GLB_REG_GPIO_11_OE
-#define GLB_REG_GPIO_11_OE_POS (11)
-#define GLB_REG_GPIO_11_OE_LEN (1)
-#define GLB_REG_GPIO_11_OE_MSK \
- (((1 << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
-#define GLB_REG_GPIO_11_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
-#define GLB_REG_GPIO_12_OE GLB_REG_GPIO_12_OE
-#define GLB_REG_GPIO_12_OE_POS (12)
-#define GLB_REG_GPIO_12_OE_LEN (1)
-#define GLB_REG_GPIO_12_OE_MSK \
- (((1 << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
-#define GLB_REG_GPIO_12_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
-#define GLB_REG_GPIO_13_OE GLB_REG_GPIO_13_OE
-#define GLB_REG_GPIO_13_OE_POS (13)
-#define GLB_REG_GPIO_13_OE_LEN (1)
-#define GLB_REG_GPIO_13_OE_MSK \
- (((1 << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
-#define GLB_REG_GPIO_13_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
-#define GLB_REG_GPIO_14_OE GLB_REG_GPIO_14_OE
-#define GLB_REG_GPIO_14_OE_POS (14)
-#define GLB_REG_GPIO_14_OE_LEN (1)
-#define GLB_REG_GPIO_14_OE_MSK \
- (((1 << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
-#define GLB_REG_GPIO_14_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
-#define GLB_REG_GPIO_15_OE GLB_REG_GPIO_15_OE
-#define GLB_REG_GPIO_15_OE_POS (15)
-#define GLB_REG_GPIO_15_OE_LEN (1)
-#define GLB_REG_GPIO_15_OE_MSK \
- (((1 << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
-#define GLB_REG_GPIO_15_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
-#define GLB_REG_GPIO_16_OE GLB_REG_GPIO_16_OE
-#define GLB_REG_GPIO_16_OE_POS (16)
-#define GLB_REG_GPIO_16_OE_LEN (1)
-#define GLB_REG_GPIO_16_OE_MSK \
- (((1 << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
-#define GLB_REG_GPIO_16_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
-#define GLB_REG_GPIO_17_OE GLB_REG_GPIO_17_OE
-#define GLB_REG_GPIO_17_OE_POS (17)
-#define GLB_REG_GPIO_17_OE_LEN (1)
-#define GLB_REG_GPIO_17_OE_MSK \
- (((1 << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
-#define GLB_REG_GPIO_17_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
-#define GLB_REG_GPIO_18_OE GLB_REG_GPIO_18_OE
-#define GLB_REG_GPIO_18_OE_POS (18)
-#define GLB_REG_GPIO_18_OE_LEN (1)
-#define GLB_REG_GPIO_18_OE_MSK \
- (((1 << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
-#define GLB_REG_GPIO_18_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
-#define GLB_REG_GPIO_19_OE GLB_REG_GPIO_19_OE
-#define GLB_REG_GPIO_19_OE_POS (19)
-#define GLB_REG_GPIO_19_OE_LEN (1)
-#define GLB_REG_GPIO_19_OE_MSK \
- (((1 << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
-#define GLB_REG_GPIO_19_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
-#define GLB_REG_GPIO_20_OE GLB_REG_GPIO_20_OE
-#define GLB_REG_GPIO_20_OE_POS (20)
-#define GLB_REG_GPIO_20_OE_LEN (1)
-#define GLB_REG_GPIO_20_OE_MSK \
- (((1 << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
-#define GLB_REG_GPIO_20_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
-#define GLB_REG_GPIO_21_OE GLB_REG_GPIO_21_OE
-#define GLB_REG_GPIO_21_OE_POS (21)
-#define GLB_REG_GPIO_21_OE_LEN (1)
-#define GLB_REG_GPIO_21_OE_MSK \
- (((1 << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
-#define GLB_REG_GPIO_21_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
-#define GLB_REG_GPIO_22_OE GLB_REG_GPIO_22_OE
-#define GLB_REG_GPIO_22_OE_POS (22)
-#define GLB_REG_GPIO_22_OE_LEN (1)
-#define GLB_REG_GPIO_22_OE_MSK \
- (((1 << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
-#define GLB_REG_GPIO_22_OE_UMSK \
- (~(((1 << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
-
-/* 0x194 : GPIO_CFGCTL35 */
-
-#define GLB_GPIO_CFGCTL35_OFFSET (0x194)
-
-/* 0x1A0 : GPIO_INT_MASK1 */
-
-#define GLB_GPIO_INT_MASK1_OFFSET (0x1A0)
-#define GLB_REG_GPIO_INT_MASK1 GLB_REG_GPIO_INT_MASK1
-#define GLB_REG_GPIO_INT_MASK1_POS (0)
-#define GLB_REG_GPIO_INT_MASK1_LEN (32)
-#define GLB_REG_GPIO_INT_MASK1_MSK \
- (((1 << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)
-#define GLB_REG_GPIO_INT_MASK1_UMSK \
- (~(((1 << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS))
-
-/* 0x1A8 : GPIO_INT_STAT1 */
-
-#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8)
-#define GLB_GPIO_INT_STAT1 GLB_GPIO_INT_STAT1
-#define GLB_GPIO_INT_STAT1_POS (0)
-#define GLB_GPIO_INT_STAT1_LEN (32)
-#define GLB_GPIO_INT_STAT1_MSK \
- (((1 << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)
-#define GLB_GPIO_INT_STAT1_UMSK \
- (~(((1 << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS))
-
-/* 0x1B0 : GPIO_INT_CLR1 */
-
-#define GLB_GPIO_INT_CLR1_OFFSET (0x1B0)
-#define GLB_REG_GPIO_INT_CLR1 GLB_REG_GPIO_INT_CLR1
-#define GLB_REG_GPIO_INT_CLR1_POS (0)
-#define GLB_REG_GPIO_INT_CLR1_LEN (32)
-#define GLB_REG_GPIO_INT_CLR1_MSK \
- (((1 << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)
-#define GLB_REG_GPIO_INT_CLR1_UMSK \
- (~(((1 << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS))
-
-/* 0x1C0 : GPIO_INT_MODE_SET1 */
-
-#define GLB_GPIO_INT_MODE_SET1_OFFSET (0x1C0)
-#define GLB_REG_GPIO_INT_MODE_SET1 GLB_REG_GPIO_INT_MODE_SET1
-#define GLB_REG_GPIO_INT_MODE_SET1_POS (0)
-#define GLB_REG_GPIO_INT_MODE_SET1_LEN (32)
-#define GLB_REG_GPIO_INT_MODE_SET1_MSK \
- (((1 << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \
- << GLB_REG_GPIO_INT_MODE_SET1_POS)
-#define GLB_REG_GPIO_INT_MODE_SET1_UMSK \
- (~(((1 << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \
- << GLB_REG_GPIO_INT_MODE_SET1_POS))
-
-/* 0x1C4 : GPIO_INT_MODE_SET2 */
-
-#define GLB_GPIO_INT_MODE_SET2_OFFSET (0x1C4)
-#define GLB_REG_GPIO_INT_MODE_SET2 GLB_REG_GPIO_INT_MODE_SET2
-#define GLB_REG_GPIO_INT_MODE_SET2_POS (0)
-#define GLB_REG_GPIO_INT_MODE_SET2_LEN (32)
-#define GLB_REG_GPIO_INT_MODE_SET2_MSK \
- (((1 << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \
- << GLB_REG_GPIO_INT_MODE_SET2_POS)
-#define GLB_REG_GPIO_INT_MODE_SET2_UMSK \
- (~(((1 << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \
- << GLB_REG_GPIO_INT_MODE_SET2_POS))
-
-/* 0x1C8 : GPIO_INT_MODE_SET3 */
-
-#define GLB_GPIO_INT_MODE_SET3_OFFSET (0x1C8)
-#define GLB_REG_GPIO_INT_MODE_SET3 GLB_REG_GPIO_INT_MODE_SET3
-#define GLB_REG_GPIO_INT_MODE_SET3_POS (0)
-#define GLB_REG_GPIO_INT_MODE_SET3_LEN (32)
-#define GLB_REG_GPIO_INT_MODE_SET3_MSK \
- (((1 << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \
- << GLB_REG_GPIO_INT_MODE_SET3_POS)
-#define GLB_REG_GPIO_INT_MODE_SET3_UMSK \
- (~(((1 << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \
- << GLB_REG_GPIO_INT_MODE_SET3_POS))
-
-/* 0x224 : led_driver */
-
-#define GLB_LED_DRIVER_OFFSET (0x224)
-#define GLB_LED_DIN_REG GLB_LED_DIN_REG
-#define GLB_LED_DIN_REG_POS (0)
-#define GLB_LED_DIN_REG_LEN (1)
-#define GLB_LED_DIN_REG_MSK \
- (((1 << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
-#define GLB_LED_DIN_REG_UMSK \
- (~(((1 << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
-#define GLB_LED_DIN_SEL GLB_LED_DIN_SEL
-#define GLB_LED_DIN_SEL_POS (1)
-#define GLB_LED_DIN_SEL_LEN (1)
-#define GLB_LED_DIN_SEL_MSK \
- (((1 << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
-#define GLB_LED_DIN_SEL_UMSK \
- (~(((1 << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
-#define GLB_LED_DIN_POLARITY_SEL GLB_LED_DIN_POLARITY_SEL
-#define GLB_LED_DIN_POLARITY_SEL_POS (2)
-#define GLB_LED_DIN_POLARITY_SEL_LEN (1)
-#define GLB_LED_DIN_POLARITY_SEL_MSK \
- (((1 << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
-#define GLB_LED_DIN_POLARITY_SEL_UMSK \
- (~(((1 << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) \
- << GLB_LED_DIN_POLARITY_SEL_POS))
-#define GLB_LEDDRV_IBIAS GLB_LEDDRV_IBIAS
-#define GLB_LEDDRV_IBIAS_POS (4)
-#define GLB_LEDDRV_IBIAS_LEN (4)
-#define GLB_LEDDRV_IBIAS_MSK \
- (((1 << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
-#define GLB_LEDDRV_IBIAS_UMSK \
- (~(((1 << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
-#define GLB_IR_RX_GPIO_SEL GLB_IR_RX_GPIO_SEL
-#define GLB_IR_RX_GPIO_SEL_POS (8)
-#define GLB_IR_RX_GPIO_SEL_LEN (2)
-#define GLB_IR_RX_GPIO_SEL_MSK \
- (((1 << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
-#define GLB_IR_RX_GPIO_SEL_UMSK \
- (~(((1 << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
-#define GLB_PU_LEDDRV GLB_PU_LEDDRV
-#define GLB_PU_LEDDRV_POS (31)
-#define GLB_PU_LEDDRV_LEN (1)
-#define GLB_PU_LEDDRV_MSK \
- (((1 << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
-#define GLB_PU_LEDDRV_UMSK \
- (~(((1 << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))
-
-/* 0x308 : gpdac_ctrl */
-
-#define GLB_GPDAC_CTRL_OFFSET (0x308)
-#define GLB_GPDACA_RSTN_ANA GLB_GPDACA_RSTN_ANA
-#define GLB_GPDACA_RSTN_ANA_POS (0)
-#define GLB_GPDACA_RSTN_ANA_LEN (1)
-#define GLB_GPDACA_RSTN_ANA_MSK \
- (((1 << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
-#define GLB_GPDACA_RSTN_ANA_UMSK \
- (~(((1 << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
-#define GLB_GPDACB_RSTN_ANA GLB_GPDACB_RSTN_ANA
-#define GLB_GPDACB_RSTN_ANA_POS (1)
-#define GLB_GPDACB_RSTN_ANA_LEN (1)
-#define GLB_GPDACB_RSTN_ANA_MSK \
- (((1 << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
-#define GLB_GPDACB_RSTN_ANA_UMSK \
- (~(((1 << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
-#define GLB_GPDAC_TEST_EN GLB_GPDAC_TEST_EN
-#define GLB_GPDAC_TEST_EN_POS (7)
-#define GLB_GPDAC_TEST_EN_LEN (1)
-#define GLB_GPDAC_TEST_EN_MSK \
- (((1 << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
-#define GLB_GPDAC_TEST_EN_UMSK \
- (~(((1 << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
-#define GLB_GPDAC_REF_SEL GLB_GPDAC_REF_SEL
-#define GLB_GPDAC_REF_SEL_POS (8)
-#define GLB_GPDAC_REF_SEL_LEN (1)
-#define GLB_GPDAC_REF_SEL_MSK \
- (((1 << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
-#define GLB_GPDAC_REF_SEL_UMSK \
- (~(((1 << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
-#define GLB_GPDAC_TEST_SEL GLB_GPDAC_TEST_SEL
-#define GLB_GPDAC_TEST_SEL_POS (9)
-#define GLB_GPDAC_TEST_SEL_LEN (3)
-#define GLB_GPDAC_TEST_SEL_MSK \
- (((1 << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
-#define GLB_GPDAC_TEST_SEL_UMSK \
- (~(((1 << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
-#define GLB_GPDAC_RESERVED GLB_GPDAC_RESERVED
-#define GLB_GPDAC_RESERVED_POS (24)
-#define GLB_GPDAC_RESERVED_LEN (8)
-#define GLB_GPDAC_RESERVED_MSK \
- (((1 << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
-#define GLB_GPDAC_RESERVED_UMSK \
- (~(((1 << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
-
-/* 0x30C : gpdac_actrl */
-
-#define GLB_GPDAC_ACTRL_OFFSET (0x30C)
-#define GLB_GPDAC_A_EN GLB_GPDAC_A_EN
-#define GLB_GPDAC_A_EN_POS (0)
-#define GLB_GPDAC_A_EN_LEN (1)
-#define GLB_GPDAC_A_EN_MSK \
- (((1 << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
-#define GLB_GPDAC_A_EN_UMSK \
- (~(((1 << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
-#define GLB_GPDAC_IOA_EN GLB_GPDAC_IOA_EN
-#define GLB_GPDAC_IOA_EN_POS (1)
-#define GLB_GPDAC_IOA_EN_LEN (1)
-#define GLB_GPDAC_IOA_EN_MSK \
- (((1 << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
-#define GLB_GPDAC_IOA_EN_UMSK \
- (~(((1 << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
-#define GLB_GPDAC_A_RNG GLB_GPDAC_A_RNG
-#define GLB_GPDAC_A_RNG_POS (18)
-#define GLB_GPDAC_A_RNG_LEN (2)
-#define GLB_GPDAC_A_RNG_MSK \
- (((1 << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
-#define GLB_GPDAC_A_RNG_UMSK \
- (~(((1 << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
-#define GLB_GPDAC_A_OUTMUX GLB_GPDAC_A_OUTMUX
-#define GLB_GPDAC_A_OUTMUX_POS (20)
-#define GLB_GPDAC_A_OUTMUX_LEN (3)
-#define GLB_GPDAC_A_OUTMUX_MSK \
- (((1 << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
-#define GLB_GPDAC_A_OUTMUX_UMSK \
- (~(((1 << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
-
-/* 0x310 : gpdac_bctrl */
-
-#define GLB_GPDAC_BCTRL_OFFSET (0x310)
-#define GLB_GPDAC_B_EN GLB_GPDAC_B_EN
-#define GLB_GPDAC_B_EN_POS (0)
-#define GLB_GPDAC_B_EN_LEN (1)
-#define GLB_GPDAC_B_EN_MSK \
- (((1 << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
-#define GLB_GPDAC_B_EN_UMSK \
- (~(((1 << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
-#define GLB_GPDAC_IOB_EN GLB_GPDAC_IOB_EN
-#define GLB_GPDAC_IOB_EN_POS (1)
-#define GLB_GPDAC_IOB_EN_LEN (1)
-#define GLB_GPDAC_IOB_EN_MSK \
- (((1 << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
-#define GLB_GPDAC_IOB_EN_UMSK \
- (~(((1 << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
-#define GLB_GPDAC_B_RNG GLB_GPDAC_B_RNG
-#define GLB_GPDAC_B_RNG_POS (18)
-#define GLB_GPDAC_B_RNG_LEN (2)
-#define GLB_GPDAC_B_RNG_MSK \
- (((1 << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
-#define GLB_GPDAC_B_RNG_UMSK \
- (~(((1 << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
-#define GLB_GPDAC_B_OUTMUX GLB_GPDAC_B_OUTMUX
-#define GLB_GPDAC_B_OUTMUX_POS (20)
-#define GLB_GPDAC_B_OUTMUX_LEN (3)
-#define GLB_GPDAC_B_OUTMUX_MSK \
- (((1 << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
-#define GLB_GPDAC_B_OUTMUX_UMSK \
- (~(((1 << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
-
-/* 0x314 : gpdac_data */
-
-#define GLB_GPDAC_DATA_OFFSET (0x314)
-#define GLB_GPDAC_B_DATA GLB_GPDAC_B_DATA
-#define GLB_GPDAC_B_DATA_POS (0)
-#define GLB_GPDAC_B_DATA_LEN (10)
-#define GLB_GPDAC_B_DATA_MSK \
- (((1 << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
-#define GLB_GPDAC_B_DATA_UMSK \
- (~(((1 << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
-#define GLB_GPDAC_A_DATA GLB_GPDAC_A_DATA
-#define GLB_GPDAC_A_DATA_POS (16)
-#define GLB_GPDAC_A_DATA_LEN (10)
-#define GLB_GPDAC_A_DATA_MSK \
- (((1 << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
-#define GLB_GPDAC_A_DATA_UMSK \
- (~(((1 << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
-
-/* 0xF00 : tzc_glb_ctrl_0 */
-
-#define GLB_TZC_GLB_CTRL_0_OFFSET (0xF00)
-#define GLB_TZC_GLB_SWRST_S00_LOCK GLB_TZC_GLB_SWRST_S00_LOCK
-#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0)
-#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S00_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S00_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S01_LOCK GLB_TZC_GLB_SWRST_S01_LOCK
-#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1)
-#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S01_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S01_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S30_LOCK GLB_TZC_GLB_SWRST_S30_LOCK
-#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8)
-#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S30_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S30_LOCK_POS))
-#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK GLB_TZC_GLB_CTRL_PWRON_RST_LOCK
-#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12)
-#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1)
-#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK \
- (((1 << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)
-#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS))
-#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK GLB_TZC_GLB_CTRL_CPU_RESET_LOCK
-#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13)
-#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1)
-#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK \
- (((1 << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)
-#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS))
-#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK GLB_TZC_GLB_CTRL_SYS_RESET_LOCK
-#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14)
-#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1)
-#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK \
- (((1 << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)
-#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS))
-#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK
-#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15)
-#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1)
-#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK \
- (((1 << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)
-#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS))
-#define GLB_TZC_GLB_MISC_LOCK GLB_TZC_GLB_MISC_LOCK
-#define GLB_TZC_GLB_MISC_LOCK_POS (25)
-#define GLB_TZC_GLB_MISC_LOCK_LEN (1)
-#define GLB_TZC_GLB_MISC_LOCK_MSK \
- (((1 << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
-#define GLB_TZC_GLB_MISC_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
-#define GLB_TZC_GLB_SRAM_LOCK GLB_TZC_GLB_SRAM_LOCK
-#define GLB_TZC_GLB_SRAM_LOCK_POS (26)
-#define GLB_TZC_GLB_SRAM_LOCK_LEN (1)
-#define GLB_TZC_GLB_SRAM_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
-#define GLB_TZC_GLB_SRAM_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
-#define GLB_TZC_GLB_L2C_LOCK GLB_TZC_GLB_L2C_LOCK
-#define GLB_TZC_GLB_L2C_LOCK_POS (27)
-#define GLB_TZC_GLB_L2C_LOCK_LEN (1)
-#define GLB_TZC_GLB_L2C_LOCK_MSK \
- (((1 << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)
-#define GLB_TZC_GLB_L2C_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS))
-#define GLB_TZC_GLB_BMX_LOCK GLB_TZC_GLB_BMX_LOCK
-#define GLB_TZC_GLB_BMX_LOCK_POS (28)
-#define GLB_TZC_GLB_BMX_LOCK_LEN (1)
-#define GLB_TZC_GLB_BMX_LOCK_MSK \
- (((1 << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
-#define GLB_TZC_GLB_BMX_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
-#define GLB_TZC_GLB_DBG_LOCK GLB_TZC_GLB_DBG_LOCK
-#define GLB_TZC_GLB_DBG_LOCK_POS (29)
-#define GLB_TZC_GLB_DBG_LOCK_LEN (1)
-#define GLB_TZC_GLB_DBG_LOCK_MSK \
- (((1 << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
-#define GLB_TZC_GLB_DBG_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
-#define GLB_TZC_GLB_MBIST_LOCK GLB_TZC_GLB_MBIST_LOCK
-#define GLB_TZC_GLB_MBIST_LOCK_POS (30)
-#define GLB_TZC_GLB_MBIST_LOCK_LEN (1)
-#define GLB_TZC_GLB_MBIST_LOCK_MSK \
- (((1 << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
-#define GLB_TZC_GLB_MBIST_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
-#define GLB_TZC_GLB_CLK_LOCK GLB_TZC_GLB_CLK_LOCK
-#define GLB_TZC_GLB_CLK_LOCK_POS (31)
-#define GLB_TZC_GLB_CLK_LOCK_LEN (1)
-#define GLB_TZC_GLB_CLK_LOCK_MSK \
- (((1 << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
-#define GLB_TZC_GLB_CLK_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
-
-/* 0xF04 : tzc_glb_ctrl_1 */
-
-#define GLB_TZC_GLB_CTRL_1_OFFSET (0xF04)
-#define GLB_TZC_GLB_SWRST_S20_LOCK GLB_TZC_GLB_SWRST_S20_LOCK
-#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0)
-#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S20_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S20_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S21_LOCK GLB_TZC_GLB_SWRST_S21_LOCK
-#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1)
-#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S21_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S21_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S22_LOCK GLB_TZC_GLB_SWRST_S22_LOCK
-#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2)
-#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S22_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S22_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S23_LOCK GLB_TZC_GLB_SWRST_S23_LOCK
-#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3)
-#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S23_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S23_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S24_LOCK GLB_TZC_GLB_SWRST_S24_LOCK
-#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4)
-#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S24_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S24_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S25_LOCK GLB_TZC_GLB_SWRST_S25_LOCK
-#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5)
-#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S25_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S25_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S26_LOCK GLB_TZC_GLB_SWRST_S26_LOCK
-#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6)
-#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S26_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S26_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S27_LOCK GLB_TZC_GLB_SWRST_S27_LOCK
-#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7)
-#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S27_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S27_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S28_LOCK GLB_TZC_GLB_SWRST_S28_LOCK
-#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8)
-#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S28_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S28_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S29_LOCK GLB_TZC_GLB_SWRST_S29_LOCK
-#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9)
-#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S29_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S29_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S2A_LOCK GLB_TZC_GLB_SWRST_S2A_LOCK
-#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10)
-#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2A_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S2B_LOCK GLB_TZC_GLB_SWRST_S2B_LOCK
-#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11)
-#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2B_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S2C_LOCK GLB_TZC_GLB_SWRST_S2C_LOCK
-#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12)
-#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2C_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S2D_LOCK GLB_TZC_GLB_SWRST_S2D_LOCK
-#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13)
-#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2D_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S2E_LOCK GLB_TZC_GLB_SWRST_S2E_LOCK
-#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14)
-#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2E_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S2F_LOCK GLB_TZC_GLB_SWRST_S2F_LOCK
-#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15)
-#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S2F_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S10_LOCK GLB_TZC_GLB_SWRST_S10_LOCK
-#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16)
-#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S10_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S10_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S11_LOCK GLB_TZC_GLB_SWRST_S11_LOCK
-#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17)
-#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S11_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S11_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S12_LOCK GLB_TZC_GLB_SWRST_S12_LOCK
-#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18)
-#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S12_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S12_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S13_LOCK GLB_TZC_GLB_SWRST_S13_LOCK
-#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19)
-#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S13_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S13_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S14_LOCK GLB_TZC_GLB_SWRST_S14_LOCK
-#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20)
-#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S14_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S14_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S15_LOCK GLB_TZC_GLB_SWRST_S15_LOCK
-#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21)
-#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S15_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S15_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S16_LOCK GLB_TZC_GLB_SWRST_S16_LOCK
-#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22)
-#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S16_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S16_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S17_LOCK GLB_TZC_GLB_SWRST_S17_LOCK
-#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23)
-#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S17_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S17_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S18_LOCK GLB_TZC_GLB_SWRST_S18_LOCK
-#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24)
-#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S18_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S18_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S19_LOCK GLB_TZC_GLB_SWRST_S19_LOCK
-#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25)
-#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S19_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S19_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S1A_LOCK GLB_TZC_GLB_SWRST_S1A_LOCK
-#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26)
-#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1A_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S1B_LOCK GLB_TZC_GLB_SWRST_S1B_LOCK
-#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27)
-#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1B_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S1C_LOCK GLB_TZC_GLB_SWRST_S1C_LOCK
-#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28)
-#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1C_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S1D_LOCK GLB_TZC_GLB_SWRST_S1D_LOCK
-#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29)
-#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1D_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S1E_LOCK GLB_TZC_GLB_SWRST_S1E_LOCK
-#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30)
-#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1E_LOCK_POS))
-#define GLB_TZC_GLB_SWRST_S1F_LOCK GLB_TZC_GLB_SWRST_S1F_LOCK
-#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31)
-#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1)
-#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK \
- (((1 << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)
-#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_SWRST_S1F_LOCK_POS))
-
-/* 0xF08 : tzc_glb_ctrl_2 */
-
-#define GLB_TZC_GLB_CTRL_2_OFFSET (0xF08)
-#define GLB_TZC_GLB_GPIO_0_LOCK GLB_TZC_GLB_GPIO_0_LOCK
-#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0)
-#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_0_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_1_LOCK GLB_TZC_GLB_GPIO_1_LOCK
-#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1)
-#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_1_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_2_LOCK GLB_TZC_GLB_GPIO_2_LOCK
-#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2)
-#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_2_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_3_LOCK GLB_TZC_GLB_GPIO_3_LOCK
-#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3)
-#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_3_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_4_LOCK GLB_TZC_GLB_GPIO_4_LOCK
-#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4)
-#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_4_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_5_LOCK GLB_TZC_GLB_GPIO_5_LOCK
-#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5)
-#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_5_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_6_LOCK GLB_TZC_GLB_GPIO_6_LOCK
-#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6)
-#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_6_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_7_LOCK GLB_TZC_GLB_GPIO_7_LOCK
-#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7)
-#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_7_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_8_LOCK GLB_TZC_GLB_GPIO_8_LOCK
-#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8)
-#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_8_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_9_LOCK GLB_TZC_GLB_GPIO_9_LOCK
-#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9)
-#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_9_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_10_LOCK GLB_TZC_GLB_GPIO_10_LOCK
-#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10)
-#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_10_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_10_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_11_LOCK GLB_TZC_GLB_GPIO_11_LOCK
-#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11)
-#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_11_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_11_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_12_LOCK GLB_TZC_GLB_GPIO_12_LOCK
-#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12)
-#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_12_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_12_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_13_LOCK GLB_TZC_GLB_GPIO_13_LOCK
-#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13)
-#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_13_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_13_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_14_LOCK GLB_TZC_GLB_GPIO_14_LOCK
-#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14)
-#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_14_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_14_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_15_LOCK GLB_TZC_GLB_GPIO_15_LOCK
-#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15)
-#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_15_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_15_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_16_LOCK GLB_TZC_GLB_GPIO_16_LOCK
-#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16)
-#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_16_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_16_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_17_LOCK GLB_TZC_GLB_GPIO_17_LOCK
-#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17)
-#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_17_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_17_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_18_LOCK GLB_TZC_GLB_GPIO_18_LOCK
-#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18)
-#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_18_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_18_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_19_LOCK GLB_TZC_GLB_GPIO_19_LOCK
-#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19)
-#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_19_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_19_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_20_LOCK GLB_TZC_GLB_GPIO_20_LOCK
-#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20)
-#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_20_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_20_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_21_LOCK GLB_TZC_GLB_GPIO_21_LOCK
-#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21)
-#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_21_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_21_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_22_LOCK GLB_TZC_GLB_GPIO_22_LOCK
-#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22)
-#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_22_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_22_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_23_LOCK GLB_TZC_GLB_GPIO_23_LOCK
-#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23)
-#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_23_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_23_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_24_LOCK GLB_TZC_GLB_GPIO_24_LOCK
-#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24)
-#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_24_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_24_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_25_LOCK GLB_TZC_GLB_GPIO_25_LOCK
-#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25)
-#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_25_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_25_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_26_LOCK GLB_TZC_GLB_GPIO_26_LOCK
-#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26)
-#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_26_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_26_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_27_LOCK GLB_TZC_GLB_GPIO_27_LOCK
-#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27)
-#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_27_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_27_LOCK_POS))
-#define GLB_TZC_GLB_GPIO_28_LOCK GLB_TZC_GLB_GPIO_28_LOCK
-#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28)
-#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1)
-#define GLB_TZC_GLB_GPIO_28_LOCK_MSK \
- (((1 << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)
-#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK \
- (~(((1 << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_28_LOCK_POS))
-
-/* 0xF0C : tzc_glb_ctrl_3 */
-
-#define GLB_TZC_GLB_CTRL_3_OFFSET (0xF0C)
-
-/* 0x0 : GPIO_CFGCTL */
-
-#define GLB_GPIO_CFGCTL_OFFSET (0x0)
-#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE
-#define GLB_REG_GPIO_0_IE_POS (0)
-#define GLB_REG_GPIO_0_IE_LEN (1)
-#define GLB_REG_GPIO_0_IE_MSK \
- (((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
-#define GLB_REG_GPIO_0_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
-#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT
-#define GLB_REG_GPIO_0_SMT_POS (1)
-#define GLB_REG_GPIO_0_SMT_LEN (1)
-#define GLB_REG_GPIO_0_SMT_MSK \
- (((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
-#define GLB_REG_GPIO_0_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
-#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV
-#define GLB_REG_GPIO_0_DRV_POS (2)
-#define GLB_REG_GPIO_0_DRV_LEN (2)
-#define GLB_REG_GPIO_0_DRV_MSK \
- (((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
-#define GLB_REG_GPIO_0_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
-#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU
-#define GLB_REG_GPIO_0_PU_POS (4)
-#define GLB_REG_GPIO_0_PU_LEN (1)
-#define GLB_REG_GPIO_0_PU_MSK \
- (((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
-#define GLB_REG_GPIO_0_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
-#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD
-#define GLB_REG_GPIO_0_PD_POS (5)
-#define GLB_REG_GPIO_0_PD_LEN (1)
-#define GLB_REG_GPIO_0_PD_MSK \
- (((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
-#define GLB_REG_GPIO_0_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
-#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL
-#define GLB_REG_GPIO_0_FUNC_SEL_POS (8)
-#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_0_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
-#define GLB_REG_GPIO_0_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
-#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL
-#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12)
-#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4)
-#define GLB_REAL_GPIO_0_FUNC_SEL_MSK \
- (((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
-#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK \
- (~(((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \
- << GLB_REAL_GPIO_0_FUNC_SEL_POS))
-#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE
-#define GLB_REG_GPIO_1_IE_POS (16)
-#define GLB_REG_GPIO_1_IE_LEN (1)
-#define GLB_REG_GPIO_1_IE_MSK \
- (((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
-#define GLB_REG_GPIO_1_IE_UMSK \
- (~(((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
-#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT
-#define GLB_REG_GPIO_1_SMT_POS (17)
-#define GLB_REG_GPIO_1_SMT_LEN (1)
-#define GLB_REG_GPIO_1_SMT_MSK \
- (((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
-#define GLB_REG_GPIO_1_SMT_UMSK \
- (~(((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
-#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV
-#define GLB_REG_GPIO_1_DRV_POS (18)
-#define GLB_REG_GPIO_1_DRV_LEN (2)
-#define GLB_REG_GPIO_1_DRV_MSK \
- (((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
-#define GLB_REG_GPIO_1_DRV_UMSK \
- (~(((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
-#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU
-#define GLB_REG_GPIO_1_PU_POS (20)
-#define GLB_REG_GPIO_1_PU_LEN (1)
-#define GLB_REG_GPIO_1_PU_MSK \
- (((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
-#define GLB_REG_GPIO_1_PU_UMSK \
- (~(((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
-#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD
-#define GLB_REG_GPIO_1_PD_POS (21)
-#define GLB_REG_GPIO_1_PD_LEN (1)
-#define GLB_REG_GPIO_1_PD_MSK \
- (((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
-#define GLB_REG_GPIO_1_PD_UMSK \
- (~(((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
-#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL
-#define GLB_REG_GPIO_1_FUNC_SEL_POS (24)
-#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4)
-#define GLB_REG_GPIO_1_FUNC_SEL_MSK \
- (((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
-#define GLB_REG_GPIO_1_FUNC_SEL_UMSK \
- (~(((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
-#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL
-#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28)
-#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4)
-#define GLB_REAL_GPIO_1_FUNC_SEL_MSK \
- (((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
-#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK \
- (~(((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \
- << GLB_REAL_GPIO_1_FUNC_SEL_POS))
-
-#define GLB_GPIO_OFFSET 0x100
-#define GLB_GPIO_INPUT_OFFSET 0x180
-#define GLB_GPIO_OUTPUT_OFFSET 0x188
-#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190
-
-/* GLB root clock type definition */
-
-#define GLB_ROOT_CLK_RC32M 0 /* root clock select RC32M */
-#define GLB_ROOT_CLK_XTAL 1 /* root clock select XTAL */
-#define GLB_ROOT_CLK_PLL 2 /* root clock select PLL others */
-
-/* GLB system clock type definition */
-
-#define GLB_SYS_CLK_RC32M 0 /* use RC32M as system clock frequency */
-#define GLB_SYS_CLK_XTAL 1 /* use XTAL as system clock */
-#define GLB_SYS_CLK_PLL48M 2 /* use PLL output 48M as system clock */
-#define GLB_SYS_CLK_PLL120M 3 /* use PLL output 120M as system clock */
-#define GLB_SYS_CLK_PLL160M 4 /* use PLL output 160M as system clock */
-#define GLB_SYS_CLK_PLL192M 5 /* use PLL output 192M as system clock */
-
-/* GLB DMA clock ID type definition */
-
-#define GLB_DMA_CLK_DMA0_CH0 0 /* DMA clock ID:channel 0 */
-#define GLB_DMA_CLK_DMA0_CH1 1 /* DMA clock ID:channel 1 */
-#define GLB_DMA_CLK_DMA0_CH2 2 /* DMA clock ID:channel 2 */
-#define GLB_DMA_CLK_DMA0_CH3 3 /* DMA clock ID:channel 3 */
-
-/* GLB clock source type definition */
-
-#define GLB_IR_CLK_SRC_XCLK 0 /* IR clock source select XCLK */
-
-/* GLB flash clock type definition */
-
-#define GLB_SFLASH_CLK_120M 0 /* Select 120M as flash clock */
-#define GLB_SFLASH_CLK_XTAL 1 /* Select XTAL as flash clock */
-#define GLB_SFLASH_CLK_48M 2 /* Select 48M as flash clock */
-#define GLB_SFLASH_CLK_80M 3 /* Select 80M as flash clock */
-#define GLB_SFLASH_CLK_BCLK 4 /* Select BCLK as flash clock */
-#define GLB_SFLASH_CLK_96M 5 /* Select 96M as flash clock */
-
-/* GLB SPI pad action type definition */
-
-#define GLB_SPI_PAD_ACT_AS_SLAVE 0 /* SPI pad act as slave */
-#define GLB_SPI_PAD_ACT_AS_MASTER 1 /* SPI pad act as master */
-
-/* GLB PKA clock type definition */
-
-#define GLB_PKA_CLK_HCLK 0 /* Select HCLK as PKA clock */
-#define GLB_PKA_CLK_PLL120M 1 /* Select PLL 120M as PKA clock */
-
-/* BMX arb mode type definition */
-
-#define BMX_ARB_FIX 0 /* 0->fix */
-#define BMX_ARB_ROUND_ROBIN 1 /* 2->round-robin */
-#define BMX_ARB_RANDOM 2 /* 3->random */
-
-/* BMX bus err type definition */
-
-#define BMX_BUS_ERR_TRUSTZONE_DECODE 0 /* Bus trustzone decode error */
-#define BMX_BUS_ERR_ADDR_DECODE 1 /* Bus addr decode error */
-
-/* BMX bus err interrupt type definition */
-
-#define BMX_ERR_INT_ERR 0 /* BMX bus err interrupt */
-#define BMX_ERR_INT_ALL 1 /* BMX bus err interrupt max num */
-
-/* BMX time out interrupt type definition */
-
-#define BMX_TO_INT_TIMEOUT 0 /* BMX timeout interrupt */
-#define BMX_TO_INT_ALL 1 /* BMX timeout interrupt max num */
-
-/* GLB EM type definition */
-
-#define GLB_EM_0KB 0x0 /* 0x0 --> 0KB */
-#define GLB_EM_8KB 0x3 /* 0x3 --> 8KB */
-#define GLB_EM_16KB 0xF /* 0xF --> 16KB */
-
-/* GLB RTC clock type definition */
-
-#define GLB_MTIMER_CLK_BCLK 0 /* BUS clock */
-#define GLB_MTIMER_CLK_32K 1 /* 32KHz */
-
-/* GLB ADC clock type definition */
-
-#define GLB_ADC_CLK_96M 0 /* use 96M as ADC clock */
-#define GLB_ADC_CLK_XCLK 1 /* use XCLK as ADC clock */
-
-/* GLB DAC clock type definition */
-
-#define GLB_DAC_CLK_32M 0 /* use 32M as DAC clock */
-#define GLB_DAC_CLK_XCLK 1 /* use XCLK as DAC clock */
-
-/* GLB DIG clock source select type definition */
-
-#define GLB_DIG_CLK_PLL_32M 0 /* select PLL 32M as DIG clock source */
-#define GLB_DIG_CLK_XCLK 1 /* select XCLK as DIG clock source */
-
-/* GLB 512K clock out select type definition */
-
-#define GLB_512K_CLK_OUT_512K 0 /* select 512K clock out */
-#define GLB_512K_CLK_OUT_256K 1 /* select 256K clock out */
-#define GLB_512K_CLK_OUT_128K 2 /* select 128K clock out */
-
-/* GLB BT bandwidth type definition */
-
-#define GLB_BT_BANDWIDTH_1M 0 /* BT bandwidth 1MHz */
-#define GLB_BT_BANDWIDTH_2M 1 /* BT bandwidth 2MHz */
-
-/* GLB UART signal type definition */
-
-#define GLB_UART_SIG_0 0 /* UART signal 0 */
-#define GLB_UART_SIG_1 1 /* UART signal 1 */
-#define GLB_UART_SIG_2 2 /* UART signal 2 */
-#define GLB_UART_SIG_3 3 /* UART signal 3 */
-#define GLB_UART_SIG_4 4 /* UART signal 4 */
-#define GLB_UART_SIG_5 5 /* UART signal 5 */
-#define GLB_UART_SIG_6 6 /* UART signal 6 */
-#define GLB_UART_SIG_7 7 /* UART signal 7 */
-
-/* GLB UART signal function type definition */
-
-#define GLB_UART_SIG_FUN_UART0_RTS 0 /* UART funtion: UART 0 RTS */
-#define GLB_UART_SIG_FUN_UART0_CTS 1 /* UART funtion: UART 0 CTS */
-#define GLB_UART_SIG_FUN_UART0_TXD 2 /* UART funtion: UART 0 TXD */
-#define GLB_UART_SIG_FUN_UART0_RXD 3 /* UART funtion: UART 0 RXD */
-#define GLB_UART_SIG_FUN_UART1_RTS 4 /* UART funtion: UART 1 RTS */
-#define GLB_UART_SIG_FUN_UART1_CTS 5 /* UART funtion: UART 1 CTS */
-#define GLB_UART_SIG_FUN_UART1_TXD 6 /* UART funtion: UART 1 TXD */
-#define GLB_UART_SIG_FUN_UART1_RXD 7 /* UART funtion: UART 1 RXD */
-
-/* GLB GPIO real mode type definition */
-
-#define GLB_GPIO_REAL_MODE_REG \
- 0 /* GPIO real function is reg_gpio_x_func_sel */
-
-#define GLB_GPIO_REAL_MODE_SDIO 1 /* GPIO real function is SDIO */
-#define GLB_GPIO_REAL_MODE_RF 2 /* GPIO real function is RF */
-#define GLB_GPIO_REAL_MODE_JTAG 3 /* GPIO real function is JTAG */
-#define GLB_GPIO_REAL_MODE_CCI 4 /* GPIO real function is CCI */
-
-/* GLB GPIO interrupt trigger mode type definition */
-
-#define GLB_GPIO_INT_TRIG_NEG_PULSE \
- 0 /* GPIO negedge pulse trigger interrupt */
-
-#define GLB_GPIO_INT_TRIG_POS_PULSE \
- 1 /* GPIO posedge pulse trigger interrupt */
-
-#define GLB_GPIO_INT_TRIG_NEG_LEVEL \
- 2 /* GPIO negedge level trigger interrupt (32k 3T) */
-
-#define GLB_GPIO_INT_TRIG_POS_LEVEL \
- 3 /* GPIO posedge level trigger interrupt (32k 3T) */
-
-/* GLB GPIO interrupt control mode type definition */
-
-#define GLB_GPIO_INT_CONTROL_SYNC 0 /* GPIO interrupt sync mode */
-#define GLB_GPIO_INT_CONTROL_ASYNC 1 /* GPIO interrupt async mode */
-
-/* PLL XTAL type definition */
-
-#define GLB_PLL_XTAL_NONE 0 /* XTAL is none */
-#define GLB_PLL_XTAL_24M 1 /* XTAL is 24M */
-#define GLB_PLL_XTAL_32M 2 /* XTAL is 32M */
-#define GLB_PLL_XTAL_38P4M 3 /* XTAL is 38.4M */
-#define GLB_PLL_XTAL_40M 4 /* XTAL is 40M */
-#define GLB_PLL_XTAL_26M 5 /* XTAL is 26M */
-#define GLB_PLL_XTAL_RC32M 6 /* XTAL is RC32M */
-
-/* PLL output clock type definition */
-
-#define GLB_PLL_CLK_480M 0 /* PLL output clock:480M */
-#define GLB_PLL_CLK_240M 1 /* PLL output clock:240M */
-#define GLB_PLL_CLK_192M 2 /* PLL output clock:192M */
-#define GLB_PLL_CLK_160M 3 /* PLL output clock:160M */
-#define GLB_PLL_CLK_120M 4 /* PLL output clock:120M */
-#define GLB_PLL_CLK_96M 5 /* PLL output clock:96M */
-#define GLB_PLL_CLK_80M 6 /* PLL output clock:80M */
-#define GLB_PLL_CLK_48M 7 /* PLL output clock:48M */
-#define GLB_PLL_CLK_32M 8 /* PLL output clock:32M */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************
- * Name: bl602_glb_uart_fun_sel
- *
- * Description:
- * Select UART signal function.
- *
- * Input Parameters:
- * sig: UART signal
- * fun: UART function
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
-void bl602_glb_uart_fun_sel(int sig, int fun);
-
-/****************************************************************************
- * Name: bl602_glb_ahb_slave1_reset
- *
- * Description:
- * Select UART signal function.
- *
- * Input Parameters:
- * sig: UART signal
- * fun: UART function
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
-void bl602_glb_ahb_slave1_reset(uint32_t slave1);
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GLB_H */
+/* Register offsets *********************************************************/
+
+#define BL602_CLK_CFG0_OFFSET 0x000000 /* clk_cfg0 */
+#define BL602_CLK_CFG1_OFFSET 0x000004 /* clk_cfg1 */
+#define BL602_CLK_CFG2_OFFSET 0x000008 /* clk_cfg2 */
+#define BL602_CLK_CFG3_OFFSET 0x00000c /* clk_cfg3 */
+#define BL602_SWRST_CFG0_OFFSET 0x000010 /* swrst_cfg0 */
+#define BL602_SWRST_CFG1_OFFSET 0x000014 /* swrst_cfg1 */
+#define BL602_SWRST_CFG2_OFFSET 0x000018 /* swrst_cfg2 */
+#define BL602_SWRST_CFG3_OFFSET 0x00001c /* swrst_cfg3 */
+#define BL602_CGEN_CFG0_OFFSET 0x000020 /* cgen_cfg0 */
+#define BL602_CGEN_CFG1_OFFSET 0x000024 /* cgen_cfg1 */
+#define BL602_CGEN_CFG2_OFFSET 0x000028 /* cgen_cfg2 */
+#define BL602_CGEN_CFG3_OFFSET 0x00002c /* cgen_cfg3 */
+#define BL602_MBIST_CTL_OFFSET 0x000030 /* mbist_ctl */
+#define BL602_MBIST_STAT_OFFSET 0x000034 /* mbist_stat */
+#define BL602_BMX_CFG1_OFFSET 0x000050 /* bmx_cfg1 */
+#define BL602_BMX_CFG2_OFFSET 0x000054 /* bmx_cfg2 */
+#define BL602_BMX_ERR_ADDR_OFFSET 0x000058 /* bmx_err_addr */
+#define BL602_BMX_DBG_OUT_OFFSET 0x00005c /* bmx_dbg_out */
+#define BL602_GLB_RSV0_OFFSET 0x000060 /* rsv0 */
+#define BL602_GLB_RSV1_OFFSET 0x000064 /* rsv1 */
+#define BL602_GLB_RSV2_OFFSET 0x000068 /* rsv2 */
+#define BL602_GLB_RSV3_OFFSET 0x00006c /* rsv3 */
+#define BL602_SRAM_RET_OFFSET 0x000070 /* sram_ret */
+#define BL602_SRAM_SLP_OFFSET 0x000074 /* sram_slp */
+#define BL602_SRAM_PARM_OFFSET 0x000078 /* sram_parm */
+#define BL602_SEAM_MISC_OFFSET 0x00007c /* seam_misc */
+#define BL602_GLB_PARM_OFFSET 0x000080 /* glb_parm */
+#define BL602_CPU_CLK_CFG_OFFSET 0x000090 /* cpu_clk_cfg */
+#define BL602_GPADC_32M_SRC_CTRL_OFFSET 0x0000a4 /* gpadc_32m_src_ctrl */
+#define BL602_DIG32K_WAKEUP_CTRL_OFFSET 0x0000a8 /* dig32k_wakeup_ctrl */
+#define BL602_WIFI_BT_COEX_CTRL_OFFSET 0x0000ac /* wifi_bt_coex_ctrl */
+#define BL602_UART_SIG_SEL_0_OFFSET 0x0000c0 /* uart_sig_sel_0 */
+#define BL602_GLB_DBG_SEL_LL_OFFSET 0x0000d0 /* dbg_sel_ll */
+#define BL602_GLB_DBG_SEL_LH_OFFSET 0x0000d4 /* dbg_sel_lh */
+#define BL602_GLB_DBG_SEL_HL_OFFSET 0x0000d8 /* dbg_sel_hl */
+#define BL602_GLB_DBG_SEL_HH_OFFSET 0x0000dc /* dbg_sel_hh */
+#define BL602_GLB_DEBUG_OFFSET 0x0000e0 /* debug */
+#define BL602_GPIO_CFGCTL0_OFFSET 0x000100 /* gpio_cfgctl0 */
+#define BL602_GPIO_CFGCTL1_OFFSET 0x000104 /* gpio_cfgctl1 */
+#define BL602_GPIO_CFGCTL2_OFFSET 0x000108 /* gpio_cfgctl2 */
+#define BL602_GPIO_CFGCTL3_OFFSET 0x00010c /* gpio_cfgctl3 */
+#define BL602_GPIO_CFGCTL4_OFFSET 0x000110 /* gpio_cfgctl4 */
+#define BL602_GPIO_CFGCTL5_OFFSET 0x000114 /* gpio_cfgctl5 */
+#define BL602_GPIO_CFGCTL6_OFFSET 0x000118 /* gpio_cfgctl6 */
+#define BL602_GPIO_CFGCTL7_OFFSET 0x00011c /* gpio_cfgctl7 */
+#define BL602_GPIO_CFGCTL8_OFFSET 0x000120 /* gpio_cfgctl8 */
+#define BL602_GPIO_CFGCTL9_OFFSET 0x000124 /* gpio_cfgctl9 */
+#define BL602_GPIO_CFGCTL10_OFFSET 0x000128 /* gpio_cfgctl10 */
+#define BL602_GPIO_CFGCTL11_OFFSET 0x00012c /* gpio_cfgctl11 */
+#define BL602_GPIO_CFGCTL12_OFFSET 0x000130 /* gpio_cfgctl12 */
+#define BL602_GPIO_CFGCTL13_OFFSET 0x000134 /* gpio_cfgctl13 */
+#define BL602_GPIO_CFGCTL14_OFFSET 0x000138 /* gpio_cfgctl14 */
+#define BL602_GPIO_CFGCTL30_OFFSET 0x000180 /* gpio_cfgctl30 */
+#define BL602_GPIO_CFGCTL31_OFFSET 0x000184 /* gpio_cfgctl31 */
+#define BL602_GPIO_CFGCTL32_OFFSET 0x000188 /* gpio_cfgctl32 */
+#define BL602_GPIO_CFGCTL33_OFFSET 0x00018c /* gpio_cfgctl33 */
+#define BL602_GPIO_CFGCTL34_OFFSET 0x000190 /* gpio_cfgctl34 */
+#define BL602_GPIO_CFGCTL35_OFFSET 0x000194 /* gpio_cfgctl35 */
+#define BL602_GPIO_INT_MASK1_OFFSET 0x0001a0 /* gpio_int_mask1 */
+#define BL602_GPIO_INT_STAT1_OFFSET 0x0001a8 /* gpio_int_stat1 */
+#define BL602_GPIO_INT_CLR1_OFFSET 0x0001b0 /* gpio_int_clr1 */
+#define BL602_GPIO_INT_MODE_SET1_OFFSET 0x0001c0 /* gpio_int_mode_set1 */
+#define BL602_GPIO_INT_MODE_SET2_OFFSET 0x0001c4 /* gpio_int_mode_set2 */
+#define BL602_GPIO_INT_MODE_SET3_OFFSET 0x0001c8 /* gpio_int_mode_set3 */
+#define BL602_LED_DRIVER_OFFSET 0x000224 /* led_driver */
+#define BL602_GPDAC_CTRL_OFFSET 0x000308 /* gpdac_ctrl */
+#define BL602_GPDAC_ACTRL_OFFSET 0x00030c /* gpdac_actrl */
+#define BL602_GPDAC_BCTRL_OFFSET 0x000310 /* gpdac_bctrl */
+#define BL602_GPDAC_DATA_OFFSET 0x000314 /* gpdac_data */
+#define BL602_TZC_GLB_CTRL_0_OFFSET 0x000f00 /* tzc_glb_ctrl_0 */
+#define BL602_TZC_GLB_CTRL_1_OFFSET 0x000f04 /* tzc_glb_ctrl_1 */
+#define BL602_TZC_GLB_CTRL_2_OFFSET 0x000f08 /* tzc_glb_ctrl_2 */
+#define BL602_TZC_GLB_CTRL_3_OFFSET 0x000f0c /* tzc_glb_ctrl_3 */
+
+/* Register definitions *****************************************************/
+
+#define BL602_CLK_CFG0 (BL602_GLB_BASE + BL602_CLK_CFG0_OFFSET)
+#define BL602_CLK_CFG1 (BL602_GLB_BASE + BL602_CLK_CFG1_OFFSET)
+#define BL602_CLK_CFG2 (BL602_GLB_BASE + BL602_CLK_CFG2_OFFSET)
+#define BL602_CLK_CFG3 (BL602_GLB_BASE + BL602_CLK_CFG3_OFFSET)
+#define BL602_SWRST_CFG0 (BL602_GLB_BASE + BL602_SWRST_CFG0_OFFSET)
+#define BL602_SWRST_CFG1 (BL602_GLB_BASE + BL602_SWRST_CFG1_OFFSET)
+#define BL602_SWRST_CFG2 (BL602_GLB_BASE + BL602_SWRST_CFG2_OFFSET)
+#define BL602_SWRST_CFG3 (BL602_GLB_BASE + BL602_SWRST_CFG3_OFFSET)
+#define BL602_CGEN_CFG0 (BL602_GLB_BASE + BL602_CGEN_CFG0_OFFSET)
+#define BL602_CGEN_CFG1 (BL602_GLB_BASE + BL602_CGEN_CFG1_OFFSET)
+#define BL602_CGEN_CFG2 (BL602_GLB_BASE + BL602_CGEN_CFG2_OFFSET)
+#define BL602_CGEN_CFG3 (BL602_GLB_BASE + BL602_CGEN_CFG3_OFFSET)
+#define BL602_MBIST_CTL (BL602_GLB_BASE + BL602_MBIST_CTL_OFFSET)
+#define BL602_MBIST_STAT (BL602_GLB_BASE + BL602_MBIST_STAT_OFFSET)
+#define BL602_BMX_CFG1 (BL602_GLB_BASE + BL602_BMX_CFG1_OFFSET)
+#define BL602_BMX_CFG2 (BL602_GLB_BASE + BL602_BMX_CFG2_OFFSET)
+#define BL602_BMX_ERR_ADDR (BL602_GLB_BASE + BL602_BMX_ERR_ADDR_OFFSET)
+#define BL602_BMX_DBG_OUT (BL602_GLB_BASE + BL602_BMX_DBG_OUT_OFFSET)
+#define BL602_GLB_RSV0 (BL602_GLB_BASE + BL602_GLB_RSV0_OFFSET)
+#define BL602_GLB_RSV1 (BL602_GLB_BASE + BL602_GLB_RSV1_OFFSET)
+#define BL602_GLB_RSV2 (BL602_GLB_BASE + BL602_GLB_RSV2_OFFSET)
+#define BL602_GLB_RSV3 (BL602_GLB_BASE + BL602_GLB_RSV3_OFFSET)
+#define BL602_SRAM_RET (BL602_GLB_BASE + BL602_SRAM_RET_OFFSET)
+#define BL602_SRAM_SLP (BL602_GLB_BASE + BL602_SRAM_SLP_OFFSET)
+#define BL602_SRAM_PARM (BL602_GLB_BASE + BL602_SRAM_PARM_OFFSET)
+#define BL602_SEAM_MISC (BL602_GLB_BASE + BL602_SEAM_MISC_OFFSET)
+#define BL602_GLB_GLB_PARM (BL602_GLB_BASE + BL602_GLB_PARM_OFFSET)
+#define BL602_CPU_CLK_CFG (BL602_GLB_BASE + BL602_CPU_CLK_CFG_OFFSET)
+#define BL602_GPADC_32M_SRC_CTRL (BL602_GLB_BASE + BL602_GPADC_32M_SRC_CTRL_OFFSET)
+#define BL602_DIG32K_WAKEUP_CTRL (BL602_GLB_BASE + BL602_DIG32K_WAKEUP_CTRL_OFFSET)
+#define BL602_WIFI_BT_COEX_CTRL (BL602_GLB_BASE + BL602_WIFI_BT_COEX_CTRL_OFFSET)
+#define BL602_UART_SIG_SEL_0 (BL602_GLB_BASE + BL602_UART_SIG_SEL_0_OFFSET)
+#define BL602_GLB_DBG_SEL_LL (BL602_GLB_BASE + BL602_GLB_DBG_SEL_LL_OFFSET)
+#define BL602_GLB_DBG_SEL_LH (BL602_GLB_BASE + BL602_GLB_DBG_SEL_LH_OFFSET)
+#define BL602_GLB_DBG_SEL_HL (BL602_GLB_BASE + BL602_GLB_DBG_SEL_HL_OFFSET)
+#define BL602_GLB_DBG_SEL_HH (BL602_GLB_BASE + BL602_GLB_DBG_SEL_HH_OFFSET)
+#define BL602_GLB_DEBUG (BL602_GLB_BASE + BL602_GLB_DEBUG_OFFSET)
+#define BL602_GPIO_CFGCTL0 (BL602_GLB_BASE + BL602_GPIO_CFGCTL0_OFFSET)
+#define BL602_GPIO_CFGCTL1 (BL602_GLB_BASE + BL602_GPIO_CFGCTL1_OFFSET)
+#define BL602_GPIO_CFGCTL2 (BL602_GLB_BASE + BL602_GPIO_CFGCTL2_OFFSET)
+#define BL602_GPIO_CFGCTL3 (BL602_GLB_BASE + BL602_GPIO_CFGCTL3_OFFSET)
+#define BL602_GPIO_CFGCTL4 (BL602_GLB_BASE + BL602_GPIO_CFGCTL4_OFFSET)
+#define BL602_GPIO_CFGCTL5 (BL602_GLB_BASE + BL602_GPIO_CFGCTL5_OFFSET)
+#define BL602_GPIO_CFGCTL6 (BL602_GLB_BASE + BL602_GPIO_CFGCTL6_OFFSET)
+#define BL602_GPIO_CFGCTL7 (BL602_GLB_BASE + BL602_GPIO_CFGCTL7_OFFSET)
+#define BL602_GPIO_CFGCTL8 (BL602_GLB_BASE + BL602_GPIO_CFGCTL8_OFFSET)
+#define BL602_GPIO_CFGCTL9 (BL602_GLB_BASE + BL602_GPIO_CFGCTL9_OFFSET)
+#define BL602_GPIO_CFGCTL10 (BL602_GLB_BASE + BL602_GPIO_CFGCTL10_OFFSET)
+#define BL602_GPIO_CFGCTL11 (BL602_GLB_BASE + BL602_GPIO_CFGCTL11_OFFSET)
+#define BL602_GPIO_CFGCTL12 (BL602_GLB_BASE + BL602_GPIO_CFGCTL12_OFFSET)
+#define BL602_GPIO_CFGCTL13 (BL602_GLB_BASE + BL602_GPIO_CFGCTL13_OFFSET)
+#define BL602_GPIO_CFGCTL14 (BL602_GLB_BASE + BL602_GPIO_CFGCTL14_OFFSET)
+#define BL602_GPIO_CFGCTL30 (BL602_GLB_BASE + BL602_GPIO_CFGCTL30_OFFSET)
+#define BL602_GPIO_CFGCTL31 (BL602_GLB_BASE + BL602_GPIO_CFGCTL31_OFFSET)
+#define BL602_GPIO_CFGCTL32 (BL602_GLB_BASE + BL602_GPIO_CFGCTL32_OFFSET)
+#define BL602_GPIO_CFGCTL33 (BL602_GLB_BASE + BL602_GPIO_CFGCTL33_OFFSET)
+#define BL602_GPIO_CFGCTL34 (BL602_GLB_BASE + BL602_GPIO_CFGCTL34_OFFSET)
+#define BL602_GPIO_CFGCTL35 (BL602_GLB_BASE + BL602_GPIO_CFGCTL35_OFFSET)
+#define BL602_GPIO_INT_MASK1 (BL602_GLB_BASE + BL602_GPIO_INT_MASK1_OFFSET)
+#define BL602_GPIO_INT_STAT1 (BL602_GLB_BASE + BL602_GPIO_INT_STAT1_OFFSET)
+#define BL602_GPIO_INT_CLR1 (BL602_GLB_BASE + BL602_GPIO_INT_CLR1_OFFSET)
+#define BL602_GPIO_INT_MODE_SET1 (BL602_GLB_BASE + BL602_GPIO_INT_MODE_SET1_OFFSET)
+#define BL602_GPIO_INT_MODE_SET2 (BL602_GLB_BASE + BL602_GPIO_INT_MODE_SET2_OFFSET)
+#define BL602_GPIO_INT_MODE_SET3 (BL602_GLB_BASE + BL602_GPIO_INT_MODE_SET3_OFFSET)
+#define BL602_LED_DRIVER (BL602_GLB_BASE + BL602_LED_DRIVER_OFFSET)
+#define BL602_GPDAC_CTRL (BL602_GLB_BASE + BL602_GPDAC_CTRL_OFFSET)
+#define BL602_GPDAC_ACTRL (BL602_GLB_BASE + BL602_GPDAC_ACTRL_OFFSET)
+#define BL602_GPDAC_BCTRL (BL602_GLB_BASE + BL602_GPDAC_BCTRL_OFFSET)
+#define BL602_GPDAC_DATA (BL602_GLB_BASE + BL602_GPDAC_DATA_OFFSET)
+#define BL602_TZC_GLB_CTRL_0 (BL602_GLB_BASE + BL602_TZC_GLB_CTRL_0_OFFSET)
+#define BL602_TZC_GLB_CTRL_1 (BL602_GLB_BASE + BL602_TZC_GLB_CTRL_1_OFFSET)
+#define BL602_TZC_GLB_CTRL_2 (BL602_GLB_BASE + BL602_TZC_GLB_CTRL_2_OFFSET)
+#define BL602_TZC_GLB_CTRL_3 (BL602_GLB_BASE + BL602_TZC_GLB_CTRL_3_OFFSET)
+
+/* Register bit definitions *************************************************/
+
+#define CLK_CFG0_GLB_ID_SHIFT (28)
+#define CLK_CFG0_GLB_ID_MASK (0x0f << CLK_CFG0_GLB_ID_SHIFT)
+#define CLK_CFG0_CHIP_RDY (1 << 27)
+#define CLK_CFG0_FCLK_SW_STATE_SHIFT (24)
+#define CLK_CFG0_FCLK_SW_STATE_MASK (0x07 << CLK_CFG0_FCLK_SW_STATE_SHIFT)
+#define CLK_CFG0_REG_BCLK_DIV_SHIFT (16)
+#define CLK_CFG0_REG_BCLK_DIV_MASK (0xff << CLK_CFG0_REG_BCLK_DIV_SHIFT)
+#define CLK_CFG0_REG_HCLK_DIV_SHIFT (8)
+#define CLK_CFG0_REG_HCLK_DIV_MASK (0xff << CLK_CFG0_REG_HCLK_DIV_SHIFT)
+#define CLK_CFG0_HBN_ROOT_CLK_SEL_SHIFT (6)
+#define CLK_CFG0_HBN_ROOT_CLK_SEL_MASK (0x03 << CLK_CFG0_HBN_ROOT_CLK_SEL_SHIFT)
+#define CLK_CFG0_REG_PLL_SEL_SHIFT (4)
+#define CLK_CFG0_REG_PLL_SEL_MASK (0x03 << CLK_CFG0_REG_PLL_SEL_SHIFT)
+#define CLK_CFG0_REG_BCLK_EN (1 << 3)
+#define CLK_CFG0_REG_HCLK_EN (1 << 2)
+#define CLK_CFG0_REG_FCLK_EN (1 << 1)
+#define CLK_CFG0_REG_PLL_EN (1 << 0)
+
+#define CLK_CFG1_BLE_EN (1 << 24)
+#define CLK_CFG1_BLE_CLK_SEL_SHIFT (16)
+#define CLK_CFG1_BLE_CLK_SEL_MASK (0x3f << CLK_CFG1_BLE_CLK_SEL_SHIFT)
+#define CLK_CFG1_WIFI_MAC_WT_DIV_SHIFT (4)
+#define CLK_CFG1_WIFI_MAC_WT_DIV_MASK (0x0f << CLK_CFG1_WIFI_MAC_WT_DIV_SHIFT)
+#define CLK_CFG1_WIFI_MAC_CORE_DIV_MASK (0x0f)
+
+#define CLK_CFG2_DMA_CLK_EN_SHIFT (24)
+#define CLK_CFG2_DMA_CLK_EN_MASK (0xff << CLK_CFG2_DMA_CLK_EN_SHIFT)
+#define CLK_CFG2_IR_CLK_EN (1 << 23)
+#define CLK_CFG2_IR_CLK_DIV_SHIFT (16)
+#define CLK_CFG2_IR_CLK_DIV_MASK (0x3f << CLK_CFG2_IR_CLK_DIV_SHIFT)
+#define CLK_CFG2_SF_CLK_SEL2_SHIFT (14)
+#define CLK_CFG2_SF_CLK_SEL2_MASK (0x03 << CLK_CFG2_SF_CLK_SEL2_SHIFT)
+#define CLK_CFG2_SF_CLK_SEL_SHIFT (12)
+#define CLK_CFG2_SF_CLK_SEL_MASK (0x03 << CLK_CFG2_SF_CLK_SEL_SHIFT)
+#define CLK_CFG2_SF_CLK_EN (1 << 11)
+#define CLK_CFG2_SF_CLK_DIV_SHIFT (8)
+#define CLK_CFG2_SF_CLK_DIV_MASK (0x07 << CLK_CFG2_SF_CLK_DIV_SHIFT)
+#define CLK_CFG2_HBN_UART_CLK_SEL (1 << 7)
+#define CLK_CFG2_UART_CLK_EN (1 << 4)
+#define CLK_CFG2_UART_CLK_DIV_MASK (0x07)
+
+#define CLK_CFG3_I2C_CLK_EN (1 << 24)
+#define CLK_CFG3_I2C_CLK_DIV_SHIFT (16)
+#define CLK_CFG3_I2C_CLK_DIV_MASK (0xff << CLK_CFG3_I2C_CLK_DIV_SHIFT)
+#define CLK_CFG3_SPI_CLK_EN (1 << 8)
+#define CLK_CFG3_SPI_CLK_DIV_MASK (0x1f)
+
+#define SWRST_CFG0_SWRST_S30 (1 << 8)
+#define SWRST_CFG0_SWRST_S20 (1 << 4)
+#define SWRST_CFG0_SWRST_S01 (1 << 1)
+#define SWRST_CFG0_SWRST_S00 (1 << 0)
+
+#define SWRST_CFG1_SWRST_S1A7 (1 << 23)
+#define SWRST_CFG1_SWRST_S1A6 (1 << 22)
+#define SWRST_CFG1_SWRST_S1A5 (1 << 21)
+#define SWRST_CFG1_SWRST_S1A4 (1 << 20)
+#define SWRST_CFG1_SWRST_S1A3 (1 << 19)
+#define SWRST_CFG1_SWRST_S1A2 (1 << 18)
+#define SWRST_CFG1_SWRST_S1A1 (1 << 17)
+#define SWRST_CFG1_SWRST_S1A0 (1 << 16)
+#define SWRST_CFG1_SWRST_S1F (1 << 15)
+#define SWRST_CFG1_SWRST_S1E (1 << 14)
+#define SWRST_CFG1_SWRST_S1D (1 << 13)
+#define SWRST_CFG1_SWRST_S1C (1 << 12)
+#define SWRST_CFG1_SWRST_S1B (1 << 11)
+#define SWRST_CFG1_SWRST_S1A (1 << 10)
+#define SWRST_CFG1_SWRST_S19 (1 << 9)
+#define SWRST_CFG1_SWRST_S18 (1 << 8)
+#define SWRST_CFG1_SWRST_S17 (1 << 7)
+#define SWRST_CFG1_SWRST_S16 (1 << 6)
+#define SWRST_CFG1_SWRST_S15 (1 << 5)
+#define SWRST_CFG1_SWRST_S14 (1 << 4)
+#define SWRST_CFG1_SWRST_S13 (1 << 3)
+#define SWRST_CFG1_SWRST_S12 (1 << 2)
+#define SWRST_CFG1_SWRST_S11 (1 << 1)
+#define SWRST_CFG1_SWRST_S10 (1 << 0)
+
+#define SWRST_CFG2_PKA_CLK_SEL (1 << 24)
+#define SWRST_CFG2_CTRL_RESET_DUMMY_SHIFT (4)
+#define SWRST_CFG2_CTRL_RESET_DUMMY_MASK (0x0f << SWRST_CFG2_CTRL_RESET_DUMMY_SHIFT)
+#define SWRST_CFG2_CTRL_SYS_RESET (1 << 2)
+#define SWRST_CFG2_CTRL_CPU_RESET (1 << 1)
+#define SWRST_CFG2_CTRL_PWRON_RST (1 << 0)
+
+#define CGEN_CFG0_CGEN_M_MASK (0xff)
+
+#define CGEN_CFG1_CGEN_S1A_SHIFT (16)
+#define CGEN_CFG1_CGEN_S1A_MASK (0xff << CGEN_CFG1_CGEN_S1A_SHIFT)
+#define CGEN_CFG1_CGEN_S1_MASK (0xffff)
+
+#define CGEN_CFG2_CGEN_S3 (1 << 4)
+#define CGEN_CFG2_CGEN_S2 (1 << 0)
+
+#define MBIST_CTL_REG_MBIST_RST_N (1 << 31)
+#define MBIST_CTL_WIFI_MBIST_MODE (1 << 4)
+#define MBIST_CTL_OCRAM_MBIST_MODE (1 << 3)
+#define MBIST_CTL_TAG_MBIST_MODE (1 << 2)
+#define MBIST_CTL_HSRAM_MBIST_MODE (1 << 1)
+#define MBIST_CTL_IROM_MBIST_MODE (1 << 0)
+
+#define MBIST_STAT_WIFI_MBIST_FAIL (1 << 20)
+#define MBIST_STAT_OCRAM_MBIST_FAIL (1 << 19)
+#define MBIST_STAT_TAG_MBIST_FAIL (1 << 18)
+#define MBIST_STAT_HSRAM_MBIST_FAIL (1 << 17)
+#define MBIST_STAT_IROM_MBIST_FAIL (1 << 16)
+#define MBIST_STAT_WIFI_MBIST_DONE (1 << 4)
+#define MBIST_STAT_OCRAM_MBIST_DONE (1 << 3)
+#define MBIST_STAT_TAG_MBIST_DONE (1 << 2)
+#define MBIST_STAT_HSRAM_MBIST_DONE (1 << 1)
+#define MBIST_STAT_IROM_MBIST_DONE (1 << 0)
+
+#define BMX_CFG1_HBN_APB_CFG_SHIFT (24)
+#define BMX_CFG1_HBN_APB_CFG_MASK (0xff << BMX_CFG1_HBN_APB_CFG_SHIFT)
+#define BMX_CFG1_PDS_APB_CFG_SHIFT (16)
+#define BMX_CFG1_PDS_APB_CFG_MASK (0xff << BMX_CFG1_PDS_APB_CFG_SHIFT)
+#define BMX_CFG1_HSEL_OPTION_SHIFT (12)
+#define BMX_CFG1_HSEL_OPTION_MASK (0x0f << BMX_CFG1_HSEL_OPTION_SHIFT)
+#define BMX_CFG1_BMX_GATING_DIS (1 << 10)
+#define BMX_CFG1_BMX_BUSY_OPTION_DIS (1 << 9)
+#define BMX_CFG1_BMX_ERR_EN (1 << 8)
+#define BMX_CFG1_BMX_ARB_MODE_SHIFT (4)
+#define BMX_CFG1_BMX_ARB_MODE_MASK (0x03 << BMX_CFG1_BMX_ARB_MODE_SHIFT)
+#define BMX_CFG1_BMX_TIMEOUT_EN_MASK (0x0f)
+
+#define BMX_CFG2_BMX_DBG_SEL_SHIFT (28)
+#define BMX_CFG2_BMX_DBG_SEL_MASK (0x0f << BMX_CFG2_BMX_DBG_SEL_SHIFT)
+#define BMX_CFG2_BMX_ERR_TZ (1 << 5)
+#define BMX_CFG2_BMX_ERR_DEC (1 << 4)
+#define BMX_CFG2_BMX_ERR_ADDR_DIS (1 << 0)
+
+#define SEAM_MISC_EM_SEL_MASK (0x0f)
+
+#define GLB_PARM_UART_SWAP_SET_SHIFT (24)
+#define GLB_PARM_UART_SWAP_SET_MASK (0x07 << GLB_PARM_UART_SWAP_SET_SHIFT)
+#define GLB_PARM_P7_JTAG_USE_IO_2_5 (1 << 23)
+#define GLB_PARM_P6_SDIO_USE_IO_0_5 (1 << 22)
+#define GLB_PARM_P5_DAC_TEST_WITH_JTAG (1 << 21)
+#define GLB_PARM_P4_ADC_TEST_WITH_JTAG (1 << 20)
+#define GLB_PARM_P3_CCI_USE_IO_2_5 (1 << 19)
+#define GLB_PARM_P2_DAC_TEST_WITH_CCI (1 << 18)
+#define GLB_PARM_P1_ADC_TEST_WITH_CCI (1 << 17)
+#define GLB_PARM_REG_CCI_USE_SDIO_PIN (1 << 16)
+#define GLB_PARM_REG_CCI_USE_JTAG_PIN (1 << 15)
+#define GLB_PARM_REG_SPI_0_SWAP (1 << 13)
+#define GLB_PARM_REG_SPI_0_MASTER_MODE (1 << 12)
+#define GLB_PARM_SEL_EMBEDDED_SFLASH (1 << 9)
+#define GLB_PARM_SWAP_SFLASH_IO_3_IO_0 (1 << 8)
+#define GLB_PARM_JTAG_SWAP_SET_SHIFT (2)
+#define GLB_PARM_JTAG_SWAP_SET_MASK (0x3f << GLB_PARM_JTAG_SWAP_SET_SHIFT)
+#define GLB_PARM_REG_EXT_RST_SMT (1 << 1)
+#define GLB_PARM_REG_BD_EN (1 << 0)
+
+#define CPU_CLK_CFG_DEBUG_NDRESET_GATE (1 << 20)
+#define CPU_CLK_CFG_CPU_RTC_SEL (1 << 19)
+#define CPU_CLK_CFG_CPU_RTC_EN (1 << 18)
+#define CPU_CLK_CFG_CPU_RTC_DIV_MASK (0x1ffff)
+
+#define GPADC_32M_SRC_CTRL_GPADC_32M_DIV_EN (1 << 8)
+#define GPADC_32M_SRC_CTRL_GPADC_32M_CLK_SEL (1 << 7)
+#define GPADC_32M_SRC_CTRL_GPADC_32M_CLK_DIV_MASK (0x3f)
+
+#define DIG32K_WAKEUP_CTRL_REG_EN_PLATFORM_WAKEUP (1 << 31)
+#define DIG32K_WAKEUP_CTRL_DIG_CLK_SRC_SEL (1 << 28)
+#define DIG32K_WAKEUP_CTRL_DIG_512K_COMP (1 << 25)
+#define DIG32K_WAKEUP_CTRL_DIG_512K_EN (1 << 24)
+#define DIG32K_WAKEUP_CTRL_DIG_512K_DIV_SHIFT (16)
+#define DIG32K_WAKEUP_CTRL_DIG_512K_DIV_MASK (0x7f << DIG32K_WAKEUP_CTRL_DIG_512K_DIV_SHIFT)
+#define DIG32K_WAKEUP_CTRL_DIG_32K_COMP (1 << 13)
+#define DIG32K_WAKEUP_CTRL_DIG_32K_EN (1 << 12)
+#define DIG32K_WAKEUP_CTRL_DIG_32K_DIV_MASK (0x7ff)
+
+#define WIFI_BT_COEX_CTRL_EN_GPIO_BT_COEX (1 << 12)
+#define WIFI_BT_COEX_CTRL_COEX_BT_BW (1 << 11)
+#define WIFI_BT_COEX_CTRL_COEX_BT_PTI_SHIFT (7)
+#define WIFI_BT_COEX_CTRL_COEX_BT_PTI_MASK (0x0f << WIFI_BT_COEX_CTRL_COEX_BT_PTI_SHIFT)
+#define WIFI_BT_COEX_CTRL_COEX_BT_CHANNEL_MASK (0x7f)
+
+#define UART_SIG_SEL_0_UART_SIG_7_SEL_SHIFT (28)
+#define UART_SIG_SEL_0_UART_SIG_7_SEL_MASK (0x0f << UART_SIG_SEL_0_UART_SIG_7_SEL_SHIFT)
+#define UART_SIG_SEL_0_UART_SIG_6_SEL_SHIFT (24)
+#define UART_SIG_SEL_0_UART_SIG_6_SEL_MASK (0x0f << UART_SIG_SEL_0_UART_SIG_6_SEL_SHIFT)
+#define UART_SIG_SEL_0_UART_SIG_5_SEL_SHIFT (20)
+#define UART_SIG_SEL_0_UART_SIG_5_SEL_MASK (0x0f << UART_SIG_SEL_0_UART_SIG_5_SEL_SHIFT)
+#define UART_SIG_SEL_0_UART_SIG_4_SEL_SHIFT (16)
+#define UART_SIG_SEL_0_UART_SIG_4_SEL_MASK (0x0f << UART_SIG_SEL_0_UART_SIG_4_SEL_SHIFT)
+#define UART_SIG_SEL_0_UART_SIG_3_SEL_SHIFT (12)
+#define UART_SIG_SEL_0_UART_SIG_3_SEL_MASK (0x0f << UART_SIG_SEL_0_UART_SIG_3_SEL_SHIFT)
+#define UART_SIG_SEL_0_UART_SIG_2_SEL_SHIFT (8)
+#define UART_SIG_SEL_0_UART_SIG_2_SEL_MASK (0x0f << UART_SIG_SEL_0_UART_SIG_2_SEL_SHIFT)
+#define UART_SIG_SEL_0_UART_SIG_1_SEL_SHIFT (4)
+#define UART_SIG_SEL_0_UART_SIG_1_SEL_MASK (0x0f << UART_SIG_SEL_0_UART_SIG_1_SEL_SHIFT)
+#define UART_SIG_SEL_0_UART_SIG_0_SEL_MASK (0x0f)
+
+#define UART_SIG_SEL_UART0_RTS (0)
+#define UART_SIG_SEL_UART0_CTS (1)
+#define UART_SIG_SEL_UART0_TXD (2)
+#define UART_SIG_SEL_UART0_RXD (3)
+#define UART_SIG_SEL_UART1_RTS (4)
+#define UART_SIG_SEL_UART1_CTS (5)
+#define UART_SIG_SEL_UART1_TXD (6)
+#define UART_SIG_SEL_UART1_RXD (7)
+
+#define GLB_DEBUG_I_SHIFT (1)
+#define GLB_DEBUG_I_MASK (0x7fffffff << GLB_DEBUG_I_SHIFT)
+#define GLB_DEBUG_OE (1 << 0)
+
+#define GPIO_CFGCTL0_REAL_GPIO_1_FUNC_SEL_SHIFT (28)
+#define GPIO_CFGCTL0_REAL_GPIO_1_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL0_REAL_GPIO_1_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL0_GPIO_1_FUNC_SEL_SHIFT (24)
+#define GPIO_CFGCTL0_GPIO_1_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL0_GPIO_1_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL0_GPIO_1_PD (1 << 21)
+#define GPIO_CFGCTL0_GPIO_1_PU (1 << 20)
+#define GPIO_CFGCTL0_GPIO_1_DRV_SHIFT (18)
+#define GPIO_CFGCTL0_GPIO_1_DRV_MASK (0x03 << GPIO_CFGCTL0_GPIO_1_DRV_SHIFT)
+#define GPIO_CFGCTL0_GPIO_1_SMT (1 << 17)
+#define GPIO_CFGCTL0_GPIO_1_IE (1 << 16)
+#define GPIO_CFGCTL0_REAL_GPIO_0_FUNC_SEL_SHIFT (12)
+#define GPIO_CFGCTL0_REAL_GPIO_0_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL0_REAL_GPIO_0_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL0_GPIO_0_FUNC_SEL_SHIFT (8)
+#define GPIO_CFGCTL0_GPIO_0_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL0_GPIO_0_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL0_GPIO_0_PD (1 << 5)
+#define GPIO_CFGCTL0_GPIO_0_PU (1 << 4)
+#define GPIO_CFGCTL0_GPIO_0_DRV_SHIFT (2)
+#define GPIO_CFGCTL0_GPIO_0_DRV_MASK (0x03 << GPIO_CFGCTL0_GPIO_0_DRV_SHIFT)
+#define GPIO_CFGCTL0_GPIO_0_SMT (1 << 1)
+#define GPIO_CFGCTL0_GPIO_0_IE (1 << 0)
+
+#define GPIO_CFGCTL1_REAL_GPIO_3_FUNC_SEL_SHIFT (28)
+#define GPIO_CFGCTL1_REAL_GPIO_3_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL1_REAL_GPIO_3_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL1_GPIO_3_FUNC_SEL_SHIFT (24)
+#define GPIO_CFGCTL1_GPIO_3_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL1_GPIO_3_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL1_GPIO_3_PD (1 << 21)
+#define GPIO_CFGCTL1_GPIO_3_PU (1 << 20)
+#define GPIO_CFGCTL1_GPIO_3_DRV_SHIFT (18)
+#define GPIO_CFGCTL1_GPIO_3_DRV_MASK (0x03 << GPIO_CFGCTL1_GPIO_3_DRV_SHIFT)
+#define GPIO_CFGCTL1_GPIO_3_SMT (1 << 17)
+#define GPIO_CFGCTL1_GPIO_3_IE (1 << 16)
+#define GPIO_CFGCTL1_REAL_GPIO_2_FUNC_SEL_SHIFT (12)
+#define GPIO_CFGCTL1_REAL_GPIO_2_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL1_REAL_GPIO_2_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL1_GPIO_2_FUNC_SEL_SHIFT (8)
+#define GPIO_CFGCTL1_GPIO_2_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL1_GPIO_2_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL1_GPIO_2_PD (1 << 5)
+#define GPIO_CFGCTL1_GPIO_2_PU (1 << 4)
+#define GPIO_CFGCTL1_GPIO_2_DRV_SHIFT (2)
+#define GPIO_CFGCTL1_GPIO_2_DRV_MASK (0x03 << GPIO_CFGCTL1_GPIO_2_DRV_SHIFT)
+#define GPIO_CFGCTL1_GPIO_2_SMT (1 << 1)
+#define GPIO_CFGCTL1_GPIO_2_IE (1 << 0)
+
+#define GPIO_CFGCTL2_REAL_GPIO_5_FUNC_SEL_SHIFT (28)
+#define GPIO_CFGCTL2_REAL_GPIO_5_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL2_REAL_GPIO_5_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL2_GPIO_5_FUNC_SEL_SHIFT (24)
+#define GPIO_CFGCTL2_GPIO_5_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL2_GPIO_5_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL2_GPIO_5_PD (1 << 21)
+#define GPIO_CFGCTL2_GPIO_5_PU (1 << 20)
+#define GPIO_CFGCTL2_GPIO_5_DRV_SHIFT (18)
+#define GPIO_CFGCTL2_GPIO_5_DRV_MASK (0x03 << GPIO_CFGCTL2_GPIO_5_DRV_SHIFT)
+#define GPIO_CFGCTL2_GPIO_5_SMT (1 << 17)
+#define GPIO_CFGCTL2_GPIO_5_IE (1 << 16)
+#define GPIO_CFGCTL2_REAL_GPIO_4_FUNC_SEL_SHIFT (12)
+#define GPIO_CFGCTL2_REAL_GPIO_4_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL2_REAL_GPIO_4_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL2_GPIO_4_FUNC_SEL_SHIFT (8)
+#define GPIO_CFGCTL2_GPIO_4_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL2_GPIO_4_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL2_GPIO_4_PD (1 << 5)
+#define GPIO_CFGCTL2_GPIO_4_PU (1 << 4)
+#define GPIO_CFGCTL2_GPIO_4_DRV_SHIFT (2)
+#define GPIO_CFGCTL2_GPIO_4_DRV_MASK (0x03 << GPIO_CFGCTL2_GPIO_4_DRV_SHIFT)
+#define GPIO_CFGCTL2_GPIO_4_SMT (1 << 1)
+#define GPIO_CFGCTL2_GPIO_4_IE (1 << 0)
+
+#define GPIO_CFGCTL3_GPIO_7_FUNC_SEL_SHIFT (24)
+#define GPIO_CFGCTL3_GPIO_7_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL3_GPIO_7_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL3_GPIO_7_PD (1 << 21)
+#define GPIO_CFGCTL3_GPIO_7_PU (1 << 20)
+#define GPIO_CFGCTL3_GPIO_7_DRV_SHIFT (18)
+#define GPIO_CFGCTL3_GPIO_7_DRV_MASK (0x03 << GPIO_CFGCTL3_GPIO_7_DRV_SHIFT)
+#define GPIO_CFGCTL3_GPIO_7_SMT (1 << 17)
+#define GPIO_CFGCTL3_GPIO_7_IE (1 << 16)
+#define GPIO_CFGCTL3_GPIO_6_FUNC_SEL_SHIFT (8)
+#define GPIO_CFGCTL3_GPIO_6_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL3_GPIO_6_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL3_GPIO_6_PD (1 << 5)
+#define GPIO_CFGCTL3_GPIO_6_PU (1 << 4)
+#define GPIO_CFGCTL3_GPIO_6_DRV_SHIFT (2)
+#define GPIO_CFGCTL3_GPIO_6_DRV_MASK (0x03 << GPIO_CFGCTL3_GPIO_6_DRV_SHIFT)
+#define GPIO_CFGCTL3_GPIO_6_SMT (1 << 1)
+#define GPIO_CFGCTL3_GPIO_6_IE (1 << 0)
+
+#define GPIO_CFGCTL4_GPIO_9_FUNC_SEL_SHIFT (24)
+#define GPIO_CFGCTL4_GPIO_9_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL4_GPIO_9_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL4_GPIO_9_PD (1 << 21)
+#define GPIO_CFGCTL4_GPIO_9_PU (1 << 20)
+#define GPIO_CFGCTL4_GPIO_9_DRV_SHIFT (18)
+#define GPIO_CFGCTL4_GPIO_9_DRV_MASK (0x03 << GPIO_CFGCTL4_GPIO_9_DRV_SHIFT)
+#define GPIO_CFGCTL4_GPIO_9_SMT (1 << 17)
+#define GPIO_CFGCTL4_GPIO_9_IE (1 << 16)
+#define GPIO_CFGCTL4_GPIO_8_FUNC_SEL_SHIFT (8)
+#define GPIO_CFGCTL4_GPIO_8_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL4_GPIO_8_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL4_GPIO_8_PD (1 << 5)
+#define GPIO_CFGCTL4_GPIO_8_PU (1 << 4)
+#define GPIO_CFGCTL4_GPIO_8_DRV_SHIFT (2)
+#define GPIO_CFGCTL4_GPIO_8_DRV_MASK (0x03 << GPIO_CFGCTL4_GPIO_8_DRV_SHIFT)
+#define GPIO_CFGCTL4_GPIO_8_SMT (1 << 1)
+#define GPIO_CFGCTL4_GPIO_8_IE (1 << 0)
+
+#define GPIO_CFGCTL5_GPIO_11_FUNC_SEL_SHIFT (24)
+#define GPIO_CFGCTL5_GPIO_11_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL5_GPIO_11_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL5_GPIO_11_PD (1 << 21)
+#define GPIO_CFGCTL5_GPIO_11_PU (1 << 20)
+#define GPIO_CFGCTL5_GPIO_11_DRV_SHIFT (18)
+#define GPIO_CFGCTL5_GPIO_11_DRV_MASK (0x03 << GPIO_CFGCTL5_GPIO_11_DRV_SHIFT)
+#define GPIO_CFGCTL5_GPIO_11_SMT (1 << 17)
+#define GPIO_CFGCTL5_GPIO_11_IE (1 << 16)
+#define GPIO_CFGCTL5_GPIO_10_FUNC_SEL_SHIFT (8)
+#define GPIO_CFGCTL5_GPIO_10_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL5_GPIO_10_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL5_GPIO_10_PD (1 << 5)
+#define GPIO_CFGCTL5_GPIO_10_PU (1 << 4)
+#define GPIO_CFGCTL5_GPIO_10_DRV_SHIFT (2)
+#define GPIO_CFGCTL5_GPIO_10_DRV_MASK (0x03 << GPIO_CFGCTL5_GPIO_10_DRV_SHIFT)
+#define GPIO_CFGCTL5_GPIO_10_SMT (1 << 1)
+#define GPIO_CFGCTL5_GPIO_10_IE (1 << 0)
+
+#define GPIO_CFGCTL6_GPIO_13_FUNC_SEL_SHIFT (24)
+#define GPIO_CFGCTL6_GPIO_13_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL6_GPIO_13_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL6_GPIO_13_PD (1 << 21)
+#define GPIO_CFGCTL6_GPIO_13_PU (1 << 20)
+#define GPIO_CFGCTL6_GPIO_13_DRV_SHIFT (18)
+#define GPIO_CFGCTL6_GPIO_13_DRV_MASK (0x03 << GPIO_CFGCTL6_GPIO_13_DRV_SHIFT)
+#define GPIO_CFGCTL6_GPIO_13_SMT (1 << 17)
+#define GPIO_CFGCTL6_GPIO_13_IE (1 << 16)
+#define GPIO_CFGCTL6_GPIO_12_FUNC_SEL_SHIFT (8)
+#define GPIO_CFGCTL6_GPIO_12_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL6_GPIO_12_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL6_GPIO_12_PD (1 << 5)
+#define GPIO_CFGCTL6_GPIO_12_PU (1 << 4)
+#define GPIO_CFGCTL6_GPIO_12_DRV_SHIFT (2)
+#define GPIO_CFGCTL6_GPIO_12_DRV_MASK (0x03 << GPIO_CFGCTL6_GPIO_12_DRV_SHIFT)
+#define GPIO_CFGCTL6_GPIO_12_SMT (1 << 1)
+#define GPIO_CFGCTL6_GPIO_12_IE (1 << 0)
+
+#define GPIO_CFGCTL7_GPIO_15_FUNC_SEL_SHIFT (24)
+#define GPIO_CFGCTL7_GPIO_15_FUNC_SEL_MASK (0x0f << GPIO_CFGCTL7_GPIO_15_FUNC_SEL_SHIFT)
+#define GPIO_CFGCTL7_GPIO_15_PD (1 << 21)
+#define GPIO_CFGCTL7_GPIO_15_PU (1 << 20)
+#define GPIO_CFGCTL7_GPIO_15_DRV_SHIFT (18)
+#define GPIO_CFGCTL7_GPIO_15_DRV_MASK (0x03 << GPIO_CFGCTL7_GPIO_15_DRV_SHIFT)
+#define GPIO_CFGCTL7_GPIO_15_SMT (1 << 17)
+#define GPIO_CFGCTL7_GPIO_15_IE (1 << 16)
+#define GPIO_CFGCTL7_GPIO_14_FUNC_SEL_SHIFT (8)
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