You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/06/06 19:21:04 UTC
[incubator-nuttx] 02/05: board: nucleo-l432kc: Add missing TIM1 CH3, CH4 pin definition
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit f7295dd43406c011f46377163c5093abe1b13b9d
Author: Jeonghyun Kim <ki...@gmail.com>
AuthorDate: Fri Apr 9 19:59:34 2021 +0900
board: nucleo-l432kc: Add missing TIM1 CH3, CH4 pin definition
---
boards/arm/stm32l4/nucleo-l432kc/include/board.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h
index 46daa2d4f1..53e92e6de9 100644
--- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h
+++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h
@@ -227,14 +227,20 @@
/* PWM output for full bridge, uses config 1, because port E is N/A on QFP64
* CH1 | 1(A8) 2(E9)
* CH2 | 1(A9) 2(E11)
+ * CH3 | 1(A10) 2(E10)
+ * CH4 | 1(A11) 2(E14)
* CHN1 | 1(A7) 2(B13) 3(E8)
* CHN2 | 1(B0) 2(B14) 3(E10)
+ * CHN3 | 1(B1) 2(B15) 3(E12)
*/
#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1
#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1
#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_1
#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1
+#define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_1
+#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3OUT_1
+#define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1
/* LPTIM2 PWM output
* REVISIT : Add support for the other clock sources, LSE, LSI and HSI