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Posted to commits@nuttx.apache.org by xi...@apache.org on 2021/06/23 17:14:44 UTC
[incubator-nuttx] 05/05: boards/xtensa/esp32: Change the name of
the flash segment to irom_0_0 instead of iram_0_2.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit c4b0a85841c61ebccb2ac329c6409461248d3354
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Jun 23 12:32:46 2021 +0100
boards/xtensa/esp32: Change the name of the flash segment to irom_0_0
instead of iram_0_2.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld | 9 ++++-----
boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld | 9 ++++-----
boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld | 9 ++++-----
3 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld
index bd9ba49..ac974b3 100644
--- a/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld
+++ b/boards/xtensa/esp32/esp32-devkitc/scripts/esp32.template.ld
@@ -28,17 +28,16 @@ MEMORY
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
- /* Even though the segment name is iram, it is actually mapped to flash.
+ /* Flash mapped instruction data.
*
- * NOTE: (0x20 offset above is a convenience for the app binary image
- * generation.
+ * The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).)
*/
- iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
+ irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@@ -79,7 +78,7 @@ MEMORY
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
- REGION_ALIAS("default_code_seg", iram0_2_seg);
+ REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */
/* Heap ends at top of dram0_0_seg */
diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld
index f664cc7..fa3459a 100644
--- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld
+++ b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/esp32.template.ld
@@ -28,17 +28,16 @@ MEMORY
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
- /* Even though the segment name is iram, it is actually mapped to flash.
+ /* Flash mapped instruction data.
*
- * NOTE: (0x20 offset above is a convenience for the app binary image
- * generation.
+ * The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).)
*/
- iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
+ irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@@ -79,7 +78,7 @@ MEMORY
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
- REGION_ALIAS("default_code_seg", iram0_2_seg);
+ REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */
/* Heap ends at top of dram0_0_seg */
diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld
index 0b49074..8e5d98c 100644
--- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld
+++ b/boards/xtensa/esp32/esp32-wrover-kit/scripts/esp32.template.ld
@@ -28,17 +28,16 @@ MEMORY
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
- /* Even though the segment name is iram, it is actually mapped to flash.
+ /* Flash mapped instruction data.
*
- * NOTE: (0x20 offset above is a convenience for the app binary image
- * generation.
+ * The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).)
*/
- iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
+ irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@@ -79,7 +78,7 @@ MEMORY
REGION_ALIAS("default_code_seg", iram0_0_seg);
#else
REGION_ALIAS("default_rodata_seg", drom0_0_seg);
- REGION_ALIAS("default_code_seg", iram0_2_seg);
+ REGION_ALIAS("default_code_seg", irom0_0_seg);
#endif /* CONFIG_ESP32_DEVKIT_RUN_IRAM */
/* Heap ends at top of dram0_0_seg */