[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #5192: arch/risc-v: Merge rv32im and rv64gc into common

[GitBox <gi...@apache.org>]

xiaoxiang781216 commented on a change in pull request #5192:
URL: https://github.com/apache/incubator-nuttx/pull/5192#discussion_r780346942



##########
File path: arch/risc-v/include/common/irq.h
##########
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/include/rv64gc/irq.h
+ * arch/risc-v/include/common/irq.h

Review comment:
       move to the upper level

##########
File path: arch/risc-v/include/common/irq.h
##########
@@ -121,7 +121,13 @@
   #define INT_XCPT_REGS     33
 #endif
 
-#define INT_XCPT_SIZE       (8 * INT_XCPT_REGS)
+#ifdef CONFIG_ARCH_RV32
+#define INT_REG_SIZE        4
+#else
+#define INT_REG_SIZE        8
+#endif

Review comment:
       #define INT_REG_SIZE sizeof(uinptr_t)

##########
File path: arch/risc-v/src/k210/k210_irq.c
##########
@@ -46,9 +46,9 @@
  * such value for each processor that can receive an interrupt.
  */
 
-volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS];

Review comment:
       let define CURRENT_REG macro like arm to simplify SMP/UP handing

##########
File path: arch/risc-v/src/k210/k210_irq.c
##########
@@ -46,9 +46,9 @@
  * such value for each processor that can receive an interrupt.
  */
 
-volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
+volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS];
 #else
-volatile uint64_t *g_current_regs[1];
+volatile uintptr_t *g_current_regs;

Review comment:
       keep [1] to unify SMP and UP

##########
File path: arch/risc-v/src/qemu-rv32/Make.defs
##########
@@ -25,7 +25,7 @@ HEAD_ASRC = qemu_rv32_head.S
 # Specify our general Assembly files
 CHIP_ASRCS = qemu_rv32_vectors.S
 
-CMN_ASRCS += riscv_testset.S
+# CMN_ASRCS += riscv_testset.S

Review comment:
       why comment out




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