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Posted to commits@nuttx.apache.org by da...@apache.org on 2021/05/19 17:41:31 UTC
[incubator-nuttx] 03/03: Try to address CI build error and a few
macro fixes.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit e37ce7677babc56e760595b96af8bfb7efe8a12d
Author: Anthony Merlino <an...@vergeaero.com>
AuthorDate: Sun May 16 12:04:43 2021 -0400
Try to address CI build error and a few macro fixes.
---
arch/arm/src/stm32/hardware/stm32_tim_v1v2.h | 1 -
arch/arm/src/stm32/stm32_pwm.c | 6 ++---
arch/arm/src/stm32f0l0g0/stm32_pwm.c | 38 ++++++++++++++--------------
arch/arm/src/stm32h7/stm32_pwm.c | 6 ++---
arch/arm/src/stm32l4/stm32l4_pwm.c | 6 ++---
5 files changed, 28 insertions(+), 29 deletions(-)
diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h
index 138cd37..a1ffa58 100644
--- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h
+++ b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h
@@ -1199,7 +1199,6 @@
#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */
-#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */
#ifdef HAVE_GTIM_CCXNP
# define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */
#endif
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 1439e33..93607dc 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -2975,11 +2975,11 @@ static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
/* Get outputs configuration */
regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0);
- regval |= ((outputs & STM32_PWM_OUT1N) ? GTIM_CCER_CC1NE : 0);
+ regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0);
regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0);
- regval |= ((outputs & STM32_PWM_OUT2N) ? GTIM_CCER_CC2NE : 0);
+ regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0);
regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0);
- regval |= ((outputs & STM32_PWM_OUT3N) ? GTIM_CCER_CC3NE : 0);
+ regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0);
regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0);
/* NOTE: CC4N doesn't exist, but some docs show configuration bits for it */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/stm32f0l0g0/stm32_pwm.c
index f63cb6f..8efb04b 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.c
@@ -1296,27 +1296,27 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
{
/* Set the CCMR2 mode values (leave CCMR1 zero) */
- ocmode2 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR2_CC3S_SHIFT) |
- (chanmode << GTIM_CCMR2_OC3M_SHIFT) |
- GTIM_CCMR2_OC3PE;
+ ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) |
+ (chanmode << ATIM_CCMR2_OC3M_SHIFT) |
+ ATIM_CCMR2_OC3PE;
if (ocmbit)
{
- ocmode2 |= GTIM_CCMR2_OC3M;
+ ocmode2 |= ATIM_CCMR2_OC3M;
}
/* Set the duty cycle by writing to the CCR register for this
* channel.
*/
- stm32pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, ccr);
+ stm32pwm_putreg(priv, STM32_ATIM_CCR3_OFFSET, ccr);
/* Reset the Output Compare Mode Bits and set the select
* output compare mode.
*/
- ccmr2 &= ~(GTIM_CCMR2_CC3S_MASK | GTIM_CCMR2_OC3M_MASK |
- GTIM_CCMR2_OC3PE | GTIM_CCMR2_OC3M);
+ ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK |
+ ATIM_CCMR2_OC3PE | ATIM_CCMR2_OC3M);
stm32pwm_output_configure(priv, channel);
}
break;
@@ -1325,27 +1325,27 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
{
/* Set the CCMR2 mode values (leave CCMR1 zero) */
- ocmode2 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR2_CC4S_SHIFT) |
- (chanmode << GTIM_CCMR2_OC4M_SHIFT) |
- GTIM_CCMR2_OC4PE;
+ ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) |
+ (chanmode << ATIM_CCMR2_OC4M_SHIFT) |
+ ATIM_CCMR2_OC4PE;
if (ocmbit)
{
- ocmode2 |= GTIM_CCMR2_OC4M;
+ ocmode2 |= ATIM_CCMR2_OC4M;
}
/* Set the duty cycle by writing to the CCR register for this
* channel.
*/
- stm32pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, ccr);
+ stm32pwm_putreg(priv, STM32_ATIM_CCR4_OFFSET, ccr);
/* Reset the Output Compare Mode Bits and set the select
* output compare mode.
*/
- ccmr2 &= ~(GTIM_CCMR2_CC4S_MASK | GTIM_CCMR2_OC4M_MASK |
- GTIM_CCMR2_OC4PE | GTIM_CCMR2_OC4M);
+ ccmr2 &= ~(ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK |
+ ATIM_CCMR2_OC4PE | ATIM_CCMR2_OC4M);
stm32pwm_output_configure(priv, channel);
}
break;
@@ -1371,14 +1371,14 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
/* Get current register state */
- bdtr = stm32pwm_getreg(priv, STM32_GTIM_BDTR_OFFSET);
+ bdtr = stm32pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET);
/* Update deadtime */
- bdtr &= ~(GTIM_BDTR_OSSI | GTIM_BDTR_OSSR);
- bdtr |= GTIM_BDTR_MOE;
+ bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR);
+ bdtr |= ATIM_BDTR_MOE;
- stm32pwm_putreg(priv, STM32_GTIM_BDTR_OFFSET, bdtr);
+ stm32pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr);
}
#endif
@@ -1386,7 +1386,7 @@ static int stm32pwm_timer(FAR struct stm32_pwmtimer_s *priv,
putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET);
#if defined(HAVE_CCMR2)
- putreg32(ccmr2, priv->base + STM32_GTIM_CCMR2_OFFSET);
+ putreg32(ccmr2, priv->base + STM32_ATIM_CCMR2_OFFSET);
#endif
/* Set the ARR Preload Bit */
diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c
index be0741e..5fcaa2e 100644
--- a/arch/arm/src/stm32h7/stm32_pwm.c
+++ b/arch/arm/src/stm32h7/stm32_pwm.c
@@ -2652,11 +2652,11 @@ static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
/* Get outputs configuration */
regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0);
- regval |= ((outputs & STM32_PWM_OUT1N) ? GTIM_CCER_CC1NE : 0);
+ regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0);
regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0);
- regval |= ((outputs & STM32_PWM_OUT2N) ? GTIM_CCER_CC2NE : 0);
+ regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0);
regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0);
- regval |= ((outputs & STM32_PWM_OUT3N) ? GTIM_CCER_CC3NE : 0);
+ regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0);
regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0);
/* NOTE: CC4N doesn't exist, but some docs show configuration bits for it */
diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c
index 397803f..04ed374 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwm.c
+++ b/arch/arm/src/stm32l4/stm32l4_pwm.c
@@ -2551,11 +2551,11 @@ static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
/* Get outputs configuration */
regval |= ((outputs & STM32L4_PWM_OUT1) ? GTIM_CCER_CC1E : 0);
- regval |= ((outputs & STM32L4_PWM_OUT1N) ? GTIM_CCER_CC1NE : 0);
+ regval |= ((outputs & STM32L4_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0);
regval |= ((outputs & STM32L4_PWM_OUT2) ? GTIM_CCER_CC2E : 0);
- regval |= ((outputs & STM32L4_PWM_OUT2N) ? GTIM_CCER_CC2NE : 0);
+ regval |= ((outputs & STM32L4_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0);
regval |= ((outputs & STM32L4_PWM_OUT3) ? GTIM_CCER_CC3E : 0);
- regval |= ((outputs & STM32L4_PWM_OUT3N) ? GTIM_CCER_CC3NE : 0);
+ regval |= ((outputs & STM32L4_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0);
regval |= ((outputs & STM32L4_PWM_OUT4) ? GTIM_CCER_CC4E : 0);
/* NOTE: CC4N does not exist, but some docs show configuration bits for it