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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/01/03 15:27:46 UTC
[incubator-nuttx] branch netlink_crypto updated (176eb02 -> a1e27bf)
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a change to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 176eb02 Add files missed in last commit
new 5b28367 net: tcp: Fix compile error in tcp.h
new 13d8cb1 Squashed commit of the following:
new 933a466 Minor fix (#23)
new a3704e7 Fix wait loop and void cast (#24)
new fc3bd5b Author: Gregory Nutt <gn...@nuttx.org>
new ad806a5 Squashed commit of the following:
new 4feda07 arch/arm/src/stm32/stm32_fmc.c: fix compilation error (#27)
new 5e243f5 net/icmp/icmp_netpoll.c: Fix warning: implicit declaration of nxsem_post(). This appeared after include of nuttx/kmalloc.h was removed recently.
new ff4ebe2 net/icmp/icmp_netpoll.c: Fix return of uninitialized 'ret' when no error occurs. That is, on what should be a successful return from this function, an uninitialized value was returned, which may indicate an undeserved error.
new b278aba Author: Gregory Nutt <gn...@nuttx.org>
new 54c1b49 drivers/modem/altair/altmdm_sys.c: Fix modem/altair semaphore related compiler warning
new 3125960 Documentation/NuttXCCodingStandard.html: Remove requirement to decorate ignored returned values with (void). (#31)
new a1e27bf drivers/sensors/lsm6dsl.c: fix various compiler warnings
The 13 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
Documentation/NuttXCCodingStandard.html | 7 +-
arch/arm/include/samd5e5/irq.h | 2 +-
arch/arm/include/stm32h7/chip.h | 7 +-
arch/arm/src/a1x/a1x_irq.c | 4 +-
arch/arm/src/a1x/a1x_pio.c | 2 +-
arch/arm/src/a1x/a1x_serial.c | 18 +-
arch/arm/src/a1x/a1x_timerisr.c | 2 +-
arch/arm/src/am335x/am335x_gpioirq.c | 8 +-
arch/arm/src/am335x/am335x_irq.c | 6 +-
arch/arm/src/am335x/am335x_lcdc.c | 2 +-
arch/arm/src/am335x/am335x_serial.c | 14 +-
arch/arm/src/am335x/am335x_timerisr.c | 4 +-
arch/arm/src/arm/up_assert.c | 10 +-
arch/arm/src/arm/up_blocktask.c | 2 +-
arch/arm/src/arm/up_doirq.c | 2 +-
arch/arm/src/arm/up_releasepending.c | 2 +-
arch/arm/src/arm/up_reprioritizertr.c | 2 +-
arch/arm/src/arm/up_sigdeliver.c | 2 +-
arch/arm/src/arm/up_unblocktask.c | 2 +-
arch/arm/src/armv6-m/up_assert.c | 10 +-
arch/arm/src/armv6-m/up_hardfault.c | 2 +-
arch/arm/src/armv6-m/up_sigdeliver.c | 2 +-
arch/arm/src/armv6-m/up_signal_dispatch.c | 4 +-
arch/arm/src/armv7-a/arm_assert.c | 12 +-
arch/arm/src/armv7-a/arm_blocktask.c | 2 +-
arch/arm/src/armv7-a/arm_doirq.c | 2 +-
arch/arm/src/armv7-a/arm_pgalloc.c | 2 +-
arch/arm/src/armv7-a/arm_releasepending.c | 2 +-
arch/arm/src/armv7-a/arm_reprioritizertr.c | 2 +-
arch/arm/src/armv7-a/arm_sigdeliver.c | 6 +-
arch/arm/src/armv7-a/arm_signal_dispatch.c | 4 +-
arch/arm/src/armv7-a/arm_unblocktask.c | 2 +-
arch/arm/src/armv7-m/up_assert.c | 12 +-
arch/arm/src/armv7-m/up_hardfault.c | 2 +-
arch/arm/src/armv7-m/up_itm_syslog.c | 2 +-
arch/arm/src/armv7-m/up_memfault.c | 2 +-
arch/arm/src/armv7-m/up_sigdeliver.c | 6 +-
arch/arm/src/armv7-m/up_signal_dispatch.c | 4 +-
arch/arm/src/armv7-r/arm_assert.c | 10 +-
arch/arm/src/armv7-r/arm_sigdeliver.c | 2 +-
arch/arm/src/armv7-r/arm_signal_dispatch.c | 4 +-
arch/arm/src/c5471/c5471_ethernet.c | 22 +-
arch/arm/src/c5471/c5471_serial.c | 6 +-
arch/arm/src/common/up_exit.c | 6 +-
arch/arm/src/common/up_initialize.c | 8 +-
arch/arm/src/common/up_lwl_console.c | 2 +-
arch/arm/src/cxd56xx/cxd56_adc.c | 10 +-
arch/arm/src/cxd56xx/cxd56_charger.c | 9 +-
arch/arm/src/cxd56xx/cxd56_clock.c | 4 +-
arch/arm/src/cxd56xx/cxd56_cpuidlestack.c | 2 +-
arch/arm/src/cxd56xx/cxd56_cpustart.c | 2 +-
arch/arm/src/cxd56xx/cxd56_dmac.c | 12 +-
arch/arm/src/cxd56xx/cxd56_emmc.c | 11 +-
arch/arm/src/cxd56xx/cxd56_farapi.c | 14 +-
arch/arm/src/cxd56xx/cxd56_gauge.c | 9 +-
arch/arm/src/cxd56xx/cxd56_ge2d.c | 18 +-
arch/arm/src/cxd56xx/cxd56_geofence.c | 12 +-
arch/arm/src/cxd56xx/cxd56_gnss.c | 57 +-
arch/arm/src/cxd56xx/cxd56_i2c.c | 30 +-
arch/arm/src/cxd56xx/cxd56_icc.c | 13 +-
arch/arm/src/cxd56xx/cxd56_idle.c | 4 +-
arch/arm/src/cxd56xx/cxd56_irq.c | 12 +-
arch/arm/src/cxd56xx/cxd56_powermgr.c | 38 +-
arch/arm/src/cxd56xx/cxd56_rtc.c | 2 +-
arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c | 2 +-
arch/arm/src/cxd56xx/cxd56_scu.c | 32 +-
arch/arm/src/cxd56xx/cxd56_sdhci.c | 72 +-
arch/arm/src/cxd56xx/cxd56_serial.c | 9 +-
arch/arm/src/cxd56xx/cxd56_sph.c | 10 +-
arch/arm/src/cxd56xx/cxd56_spi.c | 35 +-
arch/arm/src/cxd56xx/cxd56_sysctl.c | 13 +-
arch/arm/src/cxd56xx/cxd56_timer.c | 4 +-
arch/arm/src/cxd56xx/cxd56_timerisr.c | 2 +-
arch/arm/src/cxd56xx/cxd56_uart0.c | 12 +-
arch/arm/src/cxd56xx/cxd56_udmac.c | 24 +-
arch/arm/src/cxd56xx/cxd56_usbdev.c | 4 +-
arch/arm/src/cxd56xx/cxd56_wdt.c | 4 +-
arch/arm/src/dm320/dm320_decodeirq.c | 2 +-
arch/arm/src/dm320/dm320_serial.c | 6 +-
arch/arm/src/dm320/dm320_usbdev.c | 6 +-
arch/arm/src/efm32/efm32_dma.c | 31 +-
arch/arm/src/efm32/efm32_i2c.c | 27 +-
arch/arm/src/efm32/efm32_idle.c | 4 +-
arch/arm/src/efm32/efm32_irq.c | 12 +-
arch/arm/src/efm32/efm32_leserial.c | 6 +-
arch/arm/src/efm32/efm32_pwm.c | 2 +-
arch/arm/src/efm32/efm32_serial.c | 12 +-
arch/arm/src/efm32/efm32_spi.c | 58 +-
arch/arm/src/efm32/efm32_timerisr.c | 2 +-
arch/arm/src/efm32/efm32_usbdev.c | 22 +-
arch/arm/src/efm32/efm32_usbhost.c | 24 +-
arch/arm/src/imx1/imx_decodeirq.c | 2 +-
arch/arm/src/imx1/imx_serial.c | 8 +-
arch/arm/src/imx1/imx_spi.c | 31 +-
arch/arm/src/imx6/imx_cpuboot.c | 2 +-
arch/arm/src/imx6/imx_ecspi.c | 31 +-
arch/arm/src/imx6/imx_irq.c | 2 +-
arch/arm/src/imx6/imx_lowputc.c | 42 +-
arch/arm/src/imx6/imx_serial.c | 14 +-
arch/arm/src/imx6/imx_timerisr.c | 4 +-
arch/arm/src/imxrt/imxrt_edma.c | 72 +-
arch/arm/src/imxrt/imxrt_ehci.c | 18 +-
arch/arm/src/imxrt/imxrt_enc.c | 16 +-
arch/arm/src/imxrt/imxrt_enet.c | 91 +-
arch/arm/src/imxrt/imxrt_idle.c | 4 +-
arch/arm/src/imxrt/imxrt_irq.c | 12 +-
arch/arm/src/imxrt/imxrt_lowputc.c | 66 +-
arch/arm/src/imxrt/imxrt_lpi2c.c | 31 +-
arch/arm/src/imxrt/imxrt_lpspi.c | 41 +-
arch/arm/src/imxrt/imxrt_serial.c | 18 +-
arch/arm/src/imxrt/imxrt_timerisr.c | 2 +-
arch/arm/src/imxrt/imxrt_usdhc.c | 64 +-
arch/arm/src/kinetis/kinetis_enet.c | 30 +-
arch/arm/src/kinetis/kinetis_i2c.c | 22 +-
arch/arm/src/kinetis/kinetis_irq.c | 12 +-
arch/arm/src/kinetis/kinetis_lpserial.c | 24 +-
arch/arm/src/kinetis/kinetis_pinirq.c | 12 +-
arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c | 10 +-
arch/arm/src/kinetis/kinetis_sdhc.c | 22 +-
arch/arm/src/kinetis/kinetis_serial.c | 16 +-
arch/arm/src/kinetis/kinetis_spi.c | 17 +-
arch/arm/src/kinetis/kinetis_timerisr.c | 2 +-
arch/arm/src/kinetis/kinetis_usbdev.c | 20 +-
arch/arm/src/kl/kl_gpioirq.c | 6 +-
arch/arm/src/kl/kl_idle.c | 4 +-
arch/arm/src/kl/kl_irq.c | 6 +-
arch/arm/src/kl/kl_serial.c | 14 +-
arch/arm/src/kl/kl_spi.c | 17 +-
arch/arm/src/kl/kl_timerisr.c | 2 +-
arch/arm/src/lc823450/lc823450_adc.c | 34 +-
arch/arm/src/lc823450/lc823450_cpuidlestack.c | 2 +-
arch/arm/src/lc823450/lc823450_cpustart.c | 2 +-
arch/arm/src/lc823450/lc823450_i2c.c | 25 +-
arch/arm/src/lc823450/lc823450_i2s.c | 24 +-
arch/arm/src/lc823450/lc823450_ipl2.c | 12 +-
arch/arm/src/lc823450/lc823450_irq.c | 12 +-
arch/arm/src/lc823450/lc823450_mtd.c | 18 +-
arch/arm/src/lc823450/lc823450_procfs_dvfs.c | 2 +-
arch/arm/src/lc823450/lc823450_rtc.c | 14 +-
arch/arm/src/lc823450/lc823450_sdc.c | 22 +-
arch/arm/src/lc823450/lc823450_sddrv_dep.c | 18 +-
arch/arm/src/lc823450/lc823450_serial.c | 10 +-
arch/arm/src/lc823450/lc823450_spi.c | 21 +-
arch/arm/src/lc823450/lc823450_start.c | 2 +-
arch/arm/src/lc823450/lc823450_timer.c | 10 +-
arch/arm/src/lc823450/lc823450_usbdev.c | 4 +-
arch/arm/src/lc823450/lc823450_wdt.c | 6 +-
arch/arm/src/lpc17xx_40xx/Kconfig | 30 +
arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c | 6 +-
arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c | 2 +-
arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c | 6 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c | 36 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c | 8 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c | 4 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c | 4 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c | 12 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c | 44 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c | 22 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c | 234 ++++-
arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h | 4 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c | 23 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c | 23 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c | 2 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c | 14 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c | 20 +-
arch/arm/src/lpc214x/lpc214x_serial.c | 6 +-
arch/arm/src/lpc214x/lpc214x_timerisr.c | 2 +-
arch/arm/src/lpc214x/lpc214x_usbdev.c | 14 +-
arch/arm/src/lpc2378/lpc23xx_i2c.c | 4 +-
arch/arm/src/lpc2378/lpc23xx_serial.c | 6 +-
arch/arm/src/lpc2378/lpc23xx_spi.c | 23 +-
arch/arm/src/lpc2378/lpc23xx_timerisr.c | 2 +-
arch/arm/src/lpc31xx/lpc31_decodeirq.c | 2 +-
arch/arm/src/lpc31xx/lpc31_ehci.c | 18 +-
arch/arm/src/lpc31xx/lpc31_i2c.c | 2 +-
arch/arm/src/lpc31xx/lpc31_resetclks.c | 2 +-
arch/arm/src/lpc31xx/lpc31_serial.c | 4 +-
arch/arm/src/lpc31xx/lpc31_spi.c | 17 +-
arch/arm/src/lpc31xx/lpc31_timerisr.c | 2 +-
arch/arm/src/lpc43xx/lpc43_ehci.c | 18 +-
arch/arm/src/lpc43xx/lpc43_ethernet.c | 22 +-
arch/arm/src/lpc43xx/lpc43_gpdma.c | 8 +-
arch/arm/src/lpc43xx/lpc43_i2c.c | 4 +-
arch/arm/src/lpc43xx/lpc43_idle.c | 4 +-
arch/arm/src/lpc43xx/lpc43_irq.c | 12 +-
arch/arm/src/lpc43xx/lpc43_rtc.c | 2 +-
arch/arm/src/lpc43xx/lpc43_sdmmc.c | 23 +-
arch/arm/src/lpc43xx/lpc43_serial.c | 10 +-
arch/arm/src/lpc43xx/lpc43_spi.c | 23 +-
arch/arm/src/lpc43xx/lpc43_ssp.c | 21 +-
arch/arm/src/lpc43xx/lpc43_timer.c | 4 +-
arch/arm/src/lpc43xx/lpc43_timerisr.c | 2 +-
arch/arm/src/lpc43xx/lpc43_uart.c | 15 +-
arch/arm/src/lpc43xx/lpc43_wwdt.c | 4 +-
arch/arm/src/lpc54xx/lpc54_ethernet.c | 20 +-
arch/arm/src/lpc54xx/lpc54_i2c_master.c | 8 +-
arch/arm/src/lpc54xx/lpc54_idle.c | 4 +-
arch/arm/src/lpc54xx/lpc54_irq.c | 12 +-
arch/arm/src/lpc54xx/lpc54_rng.c | 4 +-
arch/arm/src/lpc54xx/lpc54_rtc.c | 2 +-
arch/arm/src/lpc54xx/lpc54_sdmmc.c | 23 +-
arch/arm/src/lpc54xx/lpc54_serial.c | 22 +-
arch/arm/src/lpc54xx/lpc54_spi_master.c | 21 +-
arch/arm/src/lpc54xx/lpc54_timerisr.c | 2 +-
arch/arm/src/lpc54xx/lpc54_usb0_ohci.c | 20 +-
arch/arm/src/lpc54xx/lpc54_wwdt.c | 4 +-
arch/arm/src/max326xx/common/max326_idle.c | 4 +-
arch/arm/src/max326xx/common/max326_irq.c | 12 +-
.../arm/src/max326xx/common/max326_rtc_lowerhalf.c | 4 +-
arch/arm/src/max326xx/common/max326_timerisr.c | 2 +-
arch/arm/src/max326xx/max32660/max32660_rtc.c | 2 +-
arch/arm/src/max326xx/max32660/max32660_serial.c | 6 +-
arch/arm/src/max326xx/max32660/max32660_spim.c | 17 +-
arch/arm/src/max326xx/max32660/max32660_wdt.c | 2 +-
arch/arm/src/nrf52/nrf52_idle.c | 4 +-
arch/arm/src/nrf52/nrf52_irq.c | 12 +-
arch/arm/src/nrf52/nrf52_rng.c | 23 +-
arch/arm/src/nrf52/nrf52_serial.c | 6 +-
arch/arm/src/nrf52/nrf52_timerisr.c | 2 +-
arch/arm/src/nuc1xx/nuc_idle.c | 4 +-
arch/arm/src/nuc1xx/nuc_irq.c | 6 +-
arch/arm/src/nuc1xx/nuc_serial.c | 32 +-
arch/arm/src/nuc1xx/nuc_timerisr.c | 2 +-
arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c | 6 +-
arch/arm/src/s32k1xx/s32k11x/s32k11x_timerisr.c | 2 +-
arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c | 12 +-
arch/arm/src/s32k1xx/s32k14x/s32k14x_timerisr.c | 2 +-
arch/arm/src/s32k1xx/s32k1xx_edma.c | 72 +-
arch/arm/src/s32k1xx/s32k1xx_enet.c | 36 +-
arch/arm/src/s32k1xx/s32k1xx_lowputc.c | 26 +-
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c | 31 +-
arch/arm/src/s32k1xx/s32k1xx_lpspi.c | 35 +-
arch/arm/src/s32k1xx/s32k1xx_pinirq.c | 12 +-
arch/arm/src/s32k1xx/s32k1xx_serial.c | 8 +-
arch/arm/src/s32k1xx/s32k1xx_wdog.h | 2 +-
arch/arm/src/sam34/sam4cm_cpuidlestack.c | 2 +-
arch/arm/src/sam34/sam4cm_cpustart.c | 2 +-
arch/arm/src/sam34/sam4cm_freerun.c | 4 +-
arch/arm/src/sam34/sam4cm_oneshot.c | 6 +-
arch/arm/src/sam34/sam4cm_tc.c | 24 +-
arch/arm/src/sam34/sam_dmac.c | 44 +-
arch/arm/src/sam34/sam_emac.c | 20 +-
arch/arm/src/sam34/sam_gpioirq.c | 24 +-
arch/arm/src/sam34/sam_hsmci.c | 28 +-
arch/arm/src/sam34/sam_irq.c | 12 +-
arch/arm/src/sam34/sam_lowputc.c | 40 +-
arch/arm/src/sam34/sam_rtc.c | 4 +-
arch/arm/src/sam34/sam_rtt.c | 4 +-
arch/arm/src/sam34/sam_serial.c | 14 +-
arch/arm/src/sam34/sam_spi.c | 37 +-
arch/arm/src/sam34/sam_tc.c | 4 +-
arch/arm/src/sam34/sam_timerisr.c | 2 +-
arch/arm/src/sam34/sam_twi.c | 20 +-
arch/arm/src/sam34/sam_udp.c | 14 +-
arch/arm/src/sam34/sam_wdt.c | 4 +-
arch/arm/src/sama5/sam_adc.c | 15 +-
arch/arm/src/sama5/sam_can.c | 14 +-
arch/arm/src/sama5/sam_dbgu.c | 8 +-
arch/arm/src/sama5/sam_dmac.c | 46 +-
arch/arm/src/sama5/sam_ehci.c | 18 +-
arch/arm/src/sama5/sam_emaca.c | 20 +-
arch/arm/src/sama5/sam_emacb.c | 20 +-
arch/arm/src/sama5/sam_flexcom_serial.c | 12 +-
arch/arm/src/sama5/sam_freerun.c | 4 +-
arch/arm/src/sama5/sam_gmac.c | 20 +-
arch/arm/src/sama5/sam_hsmci.c | 26 +-
arch/arm/src/sama5/sam_irq.c | 2 +-
arch/arm/src/sama5/sam_isi.c | 30 +-
arch/arm/src/sama5/sam_lowputc.c | 100 +-
arch/arm/src/sama5/sam_nand.c | 38 +-
arch/arm/src/sama5/sam_ohci.c | 20 +-
arch/arm/src/sama5/sam_oneshot.c | 6 +-
arch/arm/src/sama5/sam_pck.c | 6 +-
arch/arm/src/sama5/sam_pioirq.c | 24 +-
arch/arm/src/sama5/sam_pmecc.c | 9 +-
arch/arm/src/sama5/sam_pwm.c | 16 +-
arch/arm/src/sama5/sam_rtc.c | 4 +-
arch/arm/src/sama5/sam_serial.c | 22 +-
arch/arm/src/sama5/sam_spi.c | 37 +-
arch/arm/src/sama5/sam_ssc.c | 38 +-
arch/arm/src/sama5/sam_tc.c | 24 +-
arch/arm/src/sama5/sam_timerisr.c | 2 +-
arch/arm/src/sama5/sam_trng.c | 4 +-
arch/arm/src/sama5/sam_tsd.c | 13 +-
arch/arm/src/sama5/sam_twi.c | 26 +-
arch/arm/src/sama5/sam_udphs.c | 20 +-
arch/arm/src/sama5/sam_wdt.c | 6 +-
arch/arm/src/sama5/sam_xdmac.c | 46 +-
arch/arm/src/sama5/sama5d2x_pio.c | 2 +-
arch/arm/src/sama5/sama5d3x4x_pio.c | 2 +-
arch/arm/src/samd2l2/sam_dmac.c | 38 +-
arch/arm/src/samd2l2/sam_i2c_master.c | 22 +-
arch/arm/src/samd2l2/sam_idle.c | 4 +-
arch/arm/src/samd2l2/sam_irq.c | 6 +-
arch/arm/src/samd2l2/sam_serial.c | 16 +-
arch/arm/src/samd2l2/sam_spi.c | 28 +-
arch/arm/src/samd2l2/sam_timerisr.c | 2 +-
arch/arm/src/samd2l2/sam_usb.c | 15 +-
arch/arm/src/samd5e5/Kconfig | 115 +++
arch/arm/src/samd5e5/Make.defs | 1 +
arch/arm/src/samd5e5/hardware/sam_gmac.h | 1015 ++++++++++++++++++++
arch/arm/src/samd5e5/hardware/sam_memorymap.h | 2 +-
arch/arm/src/samd5e5/hardware/sam_pinmap.h | 2 +-
arch/arm/src/samd5e5/sam_dmac.c | 46 +-
.../arm/src/samd5e5/sam_ethernet.c | 106 +-
.../{stm32/stm32_fmc.h => samd5e5/sam_ethernet.h} | 148 +--
arch/arm/src/{sama5 => samd5e5}/sam_gmac.c | 318 +++---
arch/arm/src/samd5e5/sam_i2c_master.c | 22 +-
arch/arm/src/samd5e5/sam_idle.c | 4 +-
arch/arm/src/samd5e5/sam_irq.c | 12 +-
arch/arm/src/samd5e5/sam_serial.c | 18 +-
arch/arm/src/samd5e5/sam_spi.c | 28 +-
arch/arm/src/samd5e5/sam_timerisr.c | 2 +-
arch/arm/src/samd5e5/sam_usb.c | 15 +-
arch/arm/src/samv7/sam_emac.c | 24 +-
arch/arm/src/samv7/sam_freerun.c | 4 +-
arch/arm/src/samv7/sam_gpioirq.c | 20 +-
arch/arm/src/samv7/sam_hsmci.c | 26 +-
arch/arm/src/samv7/sam_irq.c | 12 +-
arch/arm/src/samv7/sam_lowputc.c | 44 +-
arch/arm/src/samv7/sam_mcan.c | 27 +-
arch/arm/src/samv7/sam_oneshot.c | 6 +-
arch/arm/src/samv7/sam_pck.c | 14 +-
arch/arm/src/samv7/sam_progmem.c | 20 +-
arch/arm/src/samv7/sam_qspi.c | 39 +-
arch/arm/src/samv7/sam_rswdt.c | 6 +-
arch/arm/src/samv7/sam_serial.c | 18 +-
arch/arm/src/samv7/sam_spi.c | 37 +-
arch/arm/src/samv7/sam_spi_slave.c | 18 +-
arch/arm/src/samv7/sam_ssc.c | 38 +-
arch/arm/src/samv7/sam_tc.c | 24 +-
arch/arm/src/samv7/sam_timerisr.c | 2 +-
arch/arm/src/samv7/sam_trng.c | 2 +-
arch/arm/src/samv7/sam_twihs.c | 28 +-
arch/arm/src/samv7/sam_usbdevhs.c | 22 +-
arch/arm/src/samv7/sam_wdt.c | 6 +-
arch/arm/src/samv7/sam_xdmac.c | 44 +-
arch/arm/src/stm32/stm32_1wire.c | 24 +-
arch/arm/src/stm32/stm32_adc.c | 21 +-
arch/arm/src/stm32/stm32_aes.c | 2 -
arch/arm/src/stm32/stm32_bbsram.c | 16 +-
arch/arm/src/stm32/stm32_can.c | 6 +-
arch/arm/src/stm32/stm32_dma2d.c | 2 +-
arch/arm/src/stm32/stm32_dma_v1.c | 20 +-
arch/arm/src/stm32/stm32_dma_v2.c | 20 +-
arch/arm/src/stm32/stm32_eth.c | 24 +-
arch/arm/src/stm32/stm32_fmc.c | 24 +-
arch/arm/src/stm32/stm32_fmc.h | 12 +-
arch/arm/src/stm32/stm32_hciuart.c | 10 +-
arch/arm/src/stm32/stm32_i2c.c | 23 +-
arch/arm/src/stm32/stm32_i2c_alt.c | 23 +-
arch/arm/src/stm32/stm32_i2c_v2.c | 23 +-
arch/arm/src/stm32/stm32_i2s.c | 36 +-
arch/arm/src/stm32/stm32_idle.c | 4 +-
arch/arm/src/stm32/stm32_irq.c | 12 +-
arch/arm/src/stm32/stm32_iwdg.c | 2 +-
arch/arm/src/stm32/stm32_ltdc.c | 2 +-
arch/arm/src/stm32/stm32_oneshot.c | 2 +-
arch/arm/src/stm32/stm32_otgfsdev.c | 22 +-
arch/arm/src/stm32/stm32_otgfshost.c | 24 +-
arch/arm/src/stm32/stm32_otghsdev.c | 22 +-
arch/arm/src/stm32/stm32_otghshost.c | 24 +-
arch/arm/src/stm32/stm32_pwm.c | 2 +-
arch/arm/src/stm32/stm32_qencoder.c | 2 +-
arch/arm/src/stm32/stm32_rng.c | 4 +-
arch/arm/src/stm32/stm32_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32/stm32_rtcc.c | 2 +-
arch/arm/src/stm32/stm32_sdio.c | 32 +-
arch/arm/src/stm32/stm32_serial.c | 8 +-
arch/arm/src/stm32/stm32_spi.c | 57 +-
arch/arm/src/stm32/stm32_tickless.c | 2 +-
arch/arm/src/stm32/stm32_timerisr.c | 2 +-
arch/arm/src/stm32/stm32_usbdev.c | 18 +-
arch/arm/src/stm32/stm32_wwdg.c | 4 +-
arch/arm/src/stm32/stm32f10xxf30xx_flash.c | 16 +-
arch/arm/src/stm32/stm32f20xxf40xx_flash.c | 16 +-
arch/arm/src/stm32/stm32f40xxx_i2c.c | 23 +-
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 4 +-
arch/arm/src/stm32/stm32l15xx_flash.c | 16 +-
arch/arm/src/stm32/stm32l15xxx_rtcc.c | 6 +-
arch/arm/src/stm32f0l0g0/stm32_adc.c | 19 +-
arch/arm/src/stm32f0l0g0/stm32_aes.c | 2 -
arch/arm/src/stm32f0l0g0/stm32_dma_v1.c | 20 +-
arch/arm/src/stm32f0l0g0/stm32_i2c.c | 23 +-
arch/arm/src/stm32f0l0g0/stm32_irq.c | 6 +-
arch/arm/src/stm32f0l0g0/stm32_pwm.c | 2 +-
arch/arm/src/stm32f0l0g0/stm32_rng.c | 4 +-
arch/arm/src/stm32f0l0g0/stm32_serial_v1.c | 6 +-
arch/arm/src/stm32f0l0g0/stm32_serial_v2.c | 6 +-
arch/arm/src/stm32f0l0g0/stm32_spi.c | 45 +-
arch/arm/src/stm32f0l0g0/stm32_timerisr.c | 2 +-
arch/arm/src/stm32f0l0g0/stm32_usbdev.c | 18 +-
arch/arm/src/stm32f7/stm32_bbsram.c | 16 +-
arch/arm/src/stm32f7/stm32_can.c | 6 +-
arch/arm/src/stm32f7/stm32_dma.c | 20 +-
arch/arm/src/stm32f7/stm32_dma2d.c | 2 +-
arch/arm/src/stm32f7/stm32_ethernet.c | 22 +-
arch/arm/src/stm32f7/stm32_flash.c | 18 +-
arch/arm/src/stm32f7/stm32_i2c.c | 23 +-
arch/arm/src/stm32f7/stm32_irq.c | 12 +-
arch/arm/src/stm32f7/stm32_ltdc.c | 2 +-
arch/arm/src/stm32f7/stm32_otgdev.c | 22 +-
arch/arm/src/stm32f7/stm32_otghost.c | 24 +-
arch/arm/src/stm32f7/stm32_pwm.c | 2 +-
arch/arm/src/stm32f7/stm32_qencoder.c | 2 +-
arch/arm/src/stm32f7/stm32_qspi.c | 46 +-
arch/arm/src/stm32f7/stm32_rng.c | 4 +-
arch/arm/src/stm32f7/stm32_rtc.c | 12 +-
arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32f7/stm32_sdmmc.c | 32 +-
arch/arm/src/stm32f7/stm32_serial.c | 6 +-
arch/arm/src/stm32f7/stm32_spi.c | 45 +-
arch/arm/src/stm32f7/stm32_tickless.c | 2 +-
arch/arm/src/stm32f7/stm32_timerisr.c | 2 +-
arch/arm/src/stm32h7/Kconfig | 19 +
arch/arm/src/stm32h7/Make.defs | 4 +
arch/arm/src/stm32h7/hardware/stm32_fmc.h | 390 ++++++++
arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h | 224 ++---
arch/arm/src/stm32h7/stm32.h | 1 +
arch/arm/src/stm32h7/stm32_bbsram.c | 16 +-
arch/arm/src/stm32h7/stm32_dma.c | 4 +-
arch/arm/src/stm32h7/stm32_ethernet.c | 26 +-
arch/arm/src/stm32h7/stm32_flash.c | 18 +-
arch/arm/src/{stm32 => stm32h7}/stm32_fmc.c | 103 +-
arch/arm/src/{stm32 => stm32h7}/stm32_fmc.h | 30 +-
arch/arm/src/stm32h7/stm32_i2c.c | 23 +-
arch/arm/src/stm32h7/stm32_irq.c | 12 +-
arch/arm/src/stm32h7/stm32_otgdev.c | 22 +-
arch/arm/src/stm32h7/stm32_otghost.c | 24 +-
arch/arm/src/stm32h7/stm32_pwm.c | 2 +-
arch/arm/src/stm32h7/stm32_qencoder.c | 2 +-
arch/arm/src/stm32h7/stm32_rtc.c | 12 +-
arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32h7/stm32_sdmmc.c | 40 +-
arch/arm/src/stm32h7/stm32_serial.c | 6 +-
arch/arm/src/stm32h7/stm32_spi.c | 51 +-
arch/arm/src/stm32h7/stm32_timerisr.c | 2 +-
arch/arm/src/stm32l4/stm32l4_1wire.c | 22 +-
arch/arm/src/stm32l4/stm32l4_can.c | 6 +-
arch/arm/src/stm32l4/stm32l4_flash.c | 16 +-
arch/arm/src/stm32l4/stm32l4_i2c.c | 23 +-
arch/arm/src/stm32l4/stm32l4_idle.c | 4 +-
arch/arm/src/stm32l4/stm32l4_irq.c | 12 +-
arch/arm/src/stm32l4/stm32l4_iwdg.c | 2 +-
arch/arm/src/stm32l4/stm32l4_lse.c | 2 +-
arch/arm/src/stm32l4/stm32l4_oneshot.c | 2 +-
arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 22 +-
arch/arm/src/stm32l4/stm32l4_otgfshost.c | 25 +-
arch/arm/src/stm32l4/stm32l4_pwm.c | 2 +-
arch/arm/src/stm32l4/stm32l4_qencoder.c | 2 +-
arch/arm/src/stm32l4/stm32l4_qspi.c | 46 +-
arch/arm/src/stm32l4/stm32l4_rcc.c | 4 +-
arch/arm/src/stm32l4/stm32l4_rng.c | 4 +-
arch/arm/src/stm32l4/stm32l4_rtc.c | 28 +-
arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32l4/stm32l4_sai.c | 32 +-
arch/arm/src/stm32l4/stm32l4_sdmmc.c | 32 +-
arch/arm/src/stm32l4/stm32l4_serial.c | 12 +-
arch/arm/src/stm32l4/stm32l4_spi.c | 51 +-
arch/arm/src/stm32l4/stm32l4_timerisr.c | 2 +-
arch/arm/src/stm32l4/stm32l4_usbdev.c | 14 +-
arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 20 +-
arch/arm/src/stm32l4/stm32l4xrxx_dma.c | 4 +-
arch/arm/src/str71x/str71x_serial.c | 10 +-
arch/arm/src/str71x/str71x_timerisr.c | 2 +-
arch/arm/src/tiva/cc13xx/cc13x0_rom.c | 8 +-
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c | 12 +-
arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c | 14 +-
arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c | 2 +-
arch/arm/src/tiva/common/tiva_adclow.c | 26 +-
arch/arm/src/tiva/common/tiva_hciuart.c | 8 +-
arch/arm/src/tiva/common/tiva_i2c.c | 27 +-
arch/arm/src/tiva/common/tiva_irq.c | 12 +-
arch/arm/src/tiva/common/tiva_pwm.c | 4 +-
arch/arm/src/tiva/common/tiva_serial.c | 18 +-
arch/arm/src/tiva/common/tiva_ssi.c | 37 +-
arch/arm/src/tiva/common/tiva_timerisr.c | 2 +-
arch/arm/src/tiva/common/tiva_timerlib.c | 8 +-
arch/arm/src/tiva/lm/lm3s_ethernet.c | 26 +-
arch/arm/src/tiva/tm4c/tm4c_ethernet.c | 26 +-
arch/arm/src/tms570/tms570_irq.c | 4 +-
arch/arm/src/tms570/tms570_serial.c | 6 +-
arch/arm/src/xmc4/xmc4_irq.c | 12 +-
arch/arm/src/xmc4/xmc4_lowputc.c | 24 +-
arch/arm/src/xmc4/xmc4_serial.c | 14 +-
arch/arm/src/xmc4/xmc4_spi.c | 67 +-
arch/arm/src/xmc4/xmc4_timerisr.c | 2 +-
arch/avr/src/at32uc3/at32uc3_irq.c | 2 +-
arch/avr/src/at32uc3/at32uc3_serial.c | 8 +-
arch/avr/src/at32uc3/at32uc3_timerisr.c | 2 +-
arch/avr/src/at90usb/at90usb_serial.c | 12 +-
arch/avr/src/at90usb/at90usb_timerisr.c | 2 +-
arch/avr/src/at90usb/at90usb_usbdev.c | 8 +-
arch/avr/src/atmega/atmega_serial.c | 22 +-
arch/avr/src/atmega/atmega_timerisr.c | 4 +-
arch/avr/src/avr/up_sigdeliver.c | 2 +-
arch/avr/src/avr/up_spi.c | 19 +-
arch/avr/src/avr32/up_blocktask.c | 2 +-
arch/avr/src/avr32/up_doirq.c | 2 +-
arch/avr/src/avr32/up_releasepending.c | 2 +-
arch/avr/src/avr32/up_reprioritizertr.c | 2 +-
arch/avr/src/avr32/up_sigdeliver.c | 2 +-
arch/avr/src/avr32/up_unblocktask.c | 2 +-
arch/avr/src/common/up_assert.c | 10 +-
arch/avr/src/common/up_exit.c | 6 +-
arch/avr/src/common/up_initialize.c | 8 +-
arch/hc/src/common/up_blocktask.c | 2 +-
arch/hc/src/common/up_doirq.c | 2 +-
arch/hc/src/common/up_exit.c | 6 +-
arch/hc/src/common/up_initialize.c | 8 +-
arch/hc/src/common/up_releasepending.c | 2 +-
arch/hc/src/common/up_reprioritizertr.c | 2 +-
arch/hc/src/common/up_unblocktask.c | 2 +-
arch/hc/src/m9s12/m9s12_assert.c | 10 +-
arch/hc/src/m9s12/m9s12_ethernet.c | 16 +-
arch/hc/src/m9s12/m9s12_serial.c | 6 +-
arch/hc/src/m9s12/m9s12_timerisr.c | 2 +-
arch/mips/include/mips32/syscall.h | 4 +-
arch/mips/src/common/up_exit.c | 6 +-
arch/mips/src/common/up_initialize.c | 8 +-
arch/mips/src/mips32/up_assert.c | 10 +-
arch/mips/src/mips32/up_blocktask.c | 2 +-
arch/mips/src/mips32/up_doirq.c | 2 +-
arch/mips/src/mips32/up_releasepending.c | 2 +-
arch/mips/src/mips32/up_reprioritizertr.c | 2 +-
arch/mips/src/mips32/up_sigdeliver.c | 2 +-
arch/mips/src/mips32/up_unblocktask.c | 2 +-
arch/mips/src/pic32mx/pic32mx-decodeirq.c | 2 +-
arch/mips/src/pic32mx/pic32mx-ethernet.c | 26 +-
arch/mips/src/pic32mx/pic32mx-irq.c | 2 +-
arch/mips/src/pic32mx/pic32mx-serial.c | 6 +-
arch/mips/src/pic32mx/pic32mx-spi.c | 17 +-
arch/mips/src/pic32mx/pic32mx-timerisr.c | 4 +-
arch/mips/src/pic32mx/pic32mx-usbdev.c | 20 +-
arch/mips/src/pic32mz/pic32mz-decodeirq.c | 2 +-
arch/mips/src/pic32mz/pic32mz-dma.c | 20 +-
arch/mips/src/pic32mz/pic32mz-ethernet.c | 26 +-
arch/mips/src/pic32mz/pic32mz-i2c.c | 23 +-
arch/mips/src/pic32mz/pic32mz-irq.c | 2 +-
arch/mips/src/pic32mz/pic32mz-oneshot.c | 2 +-
arch/mips/src/pic32mz/pic32mz-serial.c | 16 +-
arch/mips/src/pic32mz/pic32mz-spi.c | 17 +-
arch/mips/src/pic32mz/pic32mz-timerisr.c | 2 +-
arch/misoc/include/lm32/syscall.h | 4 +-
arch/misoc/include/minerva/syscall.h | 6 +-
arch/misoc/src/common/misoc_net.c | 28 +-
arch/misoc/src/common/misoc_serial.c | 6 +-
arch/misoc/src/common/misoc_timerisr.c | 2 +-
arch/misoc/src/lm32/lm32_assert.c | 10 +-
arch/misoc/src/lm32/lm32_blocktask.c | 2 +-
arch/misoc/src/lm32/lm32_doirq.c | 2 +-
arch/misoc/src/lm32/lm32_exit.c | 6 +-
arch/misoc/src/lm32/lm32_irq.c | 2 +-
arch/misoc/src/lm32/lm32_releasepending.c | 2 +-
arch/misoc/src/lm32/lm32_reprioritizertr.c | 2 +-
arch/misoc/src/lm32/lm32_sigdeliver.c | 2 +-
arch/misoc/src/lm32/lm32_swint.c | 2 +-
arch/misoc/src/lm32/lm32_unblocktask.c | 2 +-
arch/misoc/src/minerva/minerva_assert.c | 10 +-
arch/misoc/src/minerva/minerva_blocktask.c | 2 +-
arch/misoc/src/minerva/minerva_doirq.c | 2 +-
arch/misoc/src/minerva/minerva_exit.c | 6 +-
arch/misoc/src/minerva/minerva_irq.c | 2 +-
arch/misoc/src/minerva/minerva_releasepending.c | 2 +-
arch/misoc/src/minerva/minerva_reprioritizertr.c | 2 +-
arch/misoc/src/minerva/minerva_sigdeliver.c | 2 +-
arch/misoc/src/minerva/minerva_swint.c | 2 +-
arch/misoc/src/minerva/minerva_unblocktask.c | 2 +-
arch/or1k/src/common/up_assert.c | 10 +-
arch/or1k/src/common/up_blocktask.c | 2 +-
arch/or1k/src/common/up_exit.c | 6 +-
arch/or1k/src/common/up_initialize.c | 8 +-
arch/or1k/src/common/up_releasepending.c | 2 +-
arch/or1k/src/common/up_reprioritizertr.c | 2 +-
arch/or1k/src/common/up_unblocktask.c | 2 +-
arch/or1k/src/mor1kx/mor1kx_serial.c | 2 +-
arch/renesas/src/common/up_assert.c | 10 +-
arch/renesas/src/common/up_blocktask.c | 2 +-
arch/renesas/src/common/up_doirq.c | 2 +-
arch/renesas/src/common/up_exit.c | 6 +-
arch/renesas/src/common/up_initialize.c | 8 +-
arch/renesas/src/common/up_releasepending.c | 2 +-
arch/renesas/src/common/up_reprioritizertr.c | 2 +-
arch/renesas/src/common/up_unblocktask.c | 2 +-
arch/renesas/src/m16c/m16c_serial.c | 14 +-
arch/renesas/src/m16c/m16c_sigdeliver.c | 2 +-
arch/renesas/src/rx65n/rx65n_eth.c | 10 +-
arch/renesas/src/rx65n/rx65n_serial.c | 36 +-
arch/renesas/src/rx65n/rx65n_sigdeliver.c | 2 +-
arch/renesas/src/sh1/sh1_serial.c | 16 +-
arch/renesas/src/sh1/sh1_sigdeliver.c | 2 +-
arch/risc-v/include/rv32im/syscall.h | 4 +-
arch/risc-v/src/common/up_exit.c | 6 +-
arch/risc-v/src/common/up_initialize.c | 2 +-
arch/risc-v/src/gap8/gap8_uart.c | 4 +-
arch/risc-v/src/nr5m100/nr5_irq_dispatch.c | 2 +-
arch/risc-v/src/nr5m100/nr5_serial.c | 6 +-
arch/risc-v/src/nr5m100/nr5_timerisr.c | 2 +-
arch/risc-v/src/rv32im/up_assert.c | 10 +-
arch/risc-v/src/rv32im/up_blocktask.c | 2 +-
arch/risc-v/src/rv32im/up_doirq.c | 2 +-
arch/risc-v/src/rv32im/up_releasepending.c | 2 +-
arch/risc-v/src/rv32im/up_reprioritizertr.c | 2 +-
arch/risc-v/src/rv32im/up_sigdeliver.c | 2 +-
arch/risc-v/src/rv32im/up_unblocktask.c | 2 +-
arch/sim/src/sim/up_critmon.c | 2 +-
arch/sim/src/sim/up_devconsole.c | 2 +-
arch/sim/src/sim/up_deviceimage.c | 4 +-
arch/sim/src/sim/up_exit.c | 2 +-
arch/sim/src/sim/up_idle.c | 2 +-
arch/sim/src/sim/up_initialize.c | 8 +-
arch/sim/src/sim/up_ioexpander.c | 4 +-
arch/sim/src/sim/up_netdev.c | 2 +-
arch/sim/src/sim/up_netdriver.c | 6 +-
arch/sim/src/sim/up_simsmp.c | 10 +-
arch/sim/src/sim/up_simuart.c | 8 +-
arch/sim/src/sim/up_testset.c | 4 +-
arch/sim/src/sim/up_touchscreen.c | 30 +-
arch/sim/src/sim/up_wpcap.c | 2 +-
arch/sim/src/sim/up_x11framebuffer.c | 8 +-
arch/x86/src/common/up_assert.c | 10 +-
arch/x86/src/common/up_blocktask.c | 2 +-
arch/x86/src/common/up_exit.c | 6 +-
arch/x86/src/common/up_initialize.c | 8 +-
arch/x86/src/common/up_releasepending.c | 2 +-
arch/x86/src/common/up_reprioritizertr.c | 2 +-
arch/x86/src/common/up_unblocktask.c | 2 +-
arch/x86/src/i486/up_sigdeliver.c | 2 +-
arch/x86/src/qemu/qemu_handlers.c | 2 +-
arch/x86/src/qemu/qemu_keypad.c | 2 +-
arch/x86/src/qemu/qemu_timerisr.c | 2 +-
arch/x86/src/qemu/qemu_vga.c | 2 +-
arch/xtensa/src/common/xtensa_assert.c | 12 +-
arch/xtensa/src/common/xtensa_blocktask.c | 2 +-
arch/xtensa/src/common/xtensa_cpupause.c | 2 +-
arch/xtensa/src/common/xtensa_exit.c | 6 +-
arch/xtensa/src/common/xtensa_initialize.c | 8 +-
arch/xtensa/src/common/xtensa_irqdispatch.c | 2 +-
arch/xtensa/src/common/xtensa_releasepending.c | 2 +-
arch/xtensa/src/common/xtensa_reprioritizertr.c | 2 +-
arch/xtensa/src/common/xtensa_sigdeliver.c | 6 +-
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arch/xtensa/src/esp32/esp32_cpuint.c | 8 +-
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arch/xtensa/src/esp32/esp32_irq.c | 4 +-
arch/xtensa/src/esp32/esp32_serial.c | 8 +-
arch/xtensa/src/esp32/esp32_timerisr.c | 2 +-
arch/z16/src/common/up_assert.c | 10 +-
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arch/z80/src/ez80/ez80_emac.c | 24 +-
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arch/z80/src/z180/z180_timerisr.c | 8 +-
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boards/Kconfig | 13 +
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boards/arm/cxd56xx/common/src/cxd56_crashdump.c | 2 +-
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boards/arm/cxd56xx/common/src/cxd56_lpm013m091a.c | 10 +-
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boards/arm/cxd56xx/drivers/sensors/rpr0521rs_scu.c | 12 +-
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boards/arm/kinetis/freedom-k28f/src/k28_boot.c | 2 +-
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boards/arm/kinetis/freedom-k64f/src/k64_boot.c | 2 +-
boards/arm/kinetis/freedom-k64f/src/k64_sdhc.c | 2 +-
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boards/arm/kinetis/freedom-k66f/src/k66_boot.c | 2 +-
boards/arm/kinetis/freedom-k66f/src/k66_sdhc.c | 2 +-
boards/arm/kinetis/kwikstik-k40/src/k40_appinit.c | 2 +-
boards/arm/kinetis/twr-k60n512/src/k60_appinit.c | 2 +-
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boards/arm/kinetis/twr-k64f120m/src/k64_sdhc.c | 2 +-
boards/arm/kl/freedom-kl25z/src/kl_adxl345.c | 6 +-
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boards/arm/kl/freedom-kl26z/src/kl_tsi.c | 2 +-
boards/arm/kl/teensy-lc/src/kl_boardinitialize.c | 2 +-
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.../lpcxpresso-lpc1768/src/lpc17_40_oled.c | 10 +-
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boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_nsh.c | 4 +-
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.../olimex-lpc1766stk/src/lpc17_40_boot.c | 2 +-
.../olimex-lpc1766stk/src/lpc17_40_bringup.c | 2 +-
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.../lpc17xx_40xx/u-blox-c027/src/lpc17_40_ubxmdm.c | 2 +-
.../zkit-arm-1769/src/lpc17_40_buttons.c | 2 +-
.../lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_lcd.c | 2 +-
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.../arm/lpc214x/mcu123-lpc214x/src/lpc2148_spi1.c | 23 +-
boards/arm/lpc214x/zp214xpa/src/lpc2148_spi1.c | 23 +-
.../lpc214x/zp214xpa/src/lpc2148_ug2864ambag01.c | 2 +-
boards/arm/lpc31xx/ea3131/src/lpc31_mem.c | 2 +-
boards/arm/lpc31xx/ea3131/src/lpc31_usbhost.c | 2 +-
boards/arm/lpc31xx/ea3152/src/lpc31_mem.c | 2 +-
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boards/arm/lpc43xx/lpc4357-evb/src/lpc43_buttons.c | 4 +-
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boards/arm/nrf52/nrf52-feather/src/nrf52_boot.c | 2 +-
boards/arm/s32k1xx/s32k118evb/src/s32k118_boot.c | 2 +-
boards/arm/s32k1xx/s32k146evb/src/s32k146_boot.c | 2 +-
boards/arm/s32k1xx/s32k148evb/src/s32k148_boot.c | 2 +-
boards/arm/sam34/arduino-due/src/sam_boot.c | 2 +-
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boards/arm/sam34/flipnclick-sam3x/src/sam_boot.c | 2 +-
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boards/arm/sam34/sam3u-ek/src/sam_buttons.c | 8 +-
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boards/arm/sam34/sam4e-ek/src/sam_ads7843e.c | 4 +-
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boards/arm/sam34/sam4e-ek/src/sam_buttons.c | 12 +-
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boards/arm/sam34/sam4e-ek/src/sam_leds.c | 6 +-
boards/arm/sam34/sam4l-xplained/src/sam_autoleds.c | 2 +-
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boards/arm/sam34/sam4s-xplained/src/sam_buttons.c | 6 +-
boards/arm/sama5/sama5d2-xult/src/sam_boot.c | 2 +-
boards/arm/sama5/sama5d2-xult/src/sam_buttons.c | 6 +-
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boards/arm/sama5/sama5d3x-ek/src/sam_wm8904.c | 8 +-
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boards/arm/sama5/sama5d4-ek/src/sam_pmic.c | 6 +-
boards/arm/sama5/sama5d4-ek/src/sam_usb.c | 4 +-
boards/arm/sama5/sama5d4-ek/src/sam_wm8904.c | 8 +-
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boards/arm/samd2l2/arduino-m0/src/sam_userleds.c | 2 +-
.../arm/samd2l2/samd20-xplained/src/sam_autoleds.c | 2 +-
.../arm/samd2l2/samd20-xplained/src/sam_buttons.c | 4 +-
boards/arm/samd2l2/samd20-xplained/src/sam_spi.c | 4 +-
.../samd20-xplained/src/sam_ug2832hsweg04.c | 4 +-
.../arm/samd2l2/samd20-xplained/src/sam_userleds.c | 2 +-
.../arm/samd2l2/samd21-xplained/src/sam_autoleds.c | 2 +-
.../arm/samd2l2/samd21-xplained/src/sam_buttons.c | 4 +-
boards/arm/samd2l2/samd21-xplained/src/sam_spi.c | 4 +-
.../samd21-xplained/src/sam_ug2832hsweg04.c | 4 +-
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.../arm/samd2l2/saml21-xplained/src/sam_autoleds.c | 2 +-
.../arm/samd2l2/saml21-xplained/src/sam_buttons.c | 4 +-
boards/arm/samd2l2/saml21-xplained/src/sam_spi.c | 4 +-
.../saml21-xplained/src/sam_ug2832hsweg04.c | 4 +-
.../arm/samd2l2/saml21-xplained/src/sam_userleds.c | 2 +-
boards/arm/samd5e5/metro-m4/src/sam_autoleds.c | 2 +-
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boards/arm/samd5e5/same54-xplained-pro/Kconfig | 50 +
boards/arm/samd5e5/same54-xplained-pro/README.txt | 160 +++
.../same54-xplained-pro/configs/nsh/defconfig | 55 ++
.../samd5e5/same54-xplained-pro/include/board.h | 503 ++++++++++
.../samd5e5/same54-xplained-pro/scripts/Make.defs | 128 +++
.../samd5e5/same54-xplained-pro/scripts/flash.ld | 123 +++
.../arm/samd5e5/same54-xplained-pro/scripts/nvm.c | 55 +-
.../scripts/nvm.srec | 0
.../samd5e5/same54-xplained-pro/scripts/sram.ld | 122 +++
.../arm/samd5e5/same54-xplained-pro/src/Makefile | 55 ++
.../same54-xplained-pro/src/sam_appinit.c} | 70 +-
.../src/sam_autoleds.c | 26 +-
.../src/sam_boot.c | 4 +-
.../same54-xplained-pro/src/sam_bringup.c} | 44 +-
.../samd5e5/same54-xplained-pro/src/sam_phyinit.c | 41 +-
.../src/sam_userleds.c | 19 +-
.../same54-xplained-pro/src/same54-xplained-pro.h} | 128 ++-
.../arm/samv7/same70-xplained/src/sam_at24config.c | 4 +-
boards/arm/samv7/same70-xplained/src/sam_boot.c | 4 +-
boards/arm/samv7/same70-xplained/src/sam_buttons.c | 6 +-
.../arm/samv7/same70-xplained/src/sam_ethernet.c | 10 +-
boards/arm/samv7/same70-xplained/src/sam_hsmci.c | 2 +-
.../arm/samv7/same70-xplained/src/sam_mrf24j40.c | 4 +-
boards/arm/samv7/same70-xplained/src/sam_spi.c | 4 +-
boards/arm/samv7/samv71-xult/src/sam_at24config.c | 4 +-
boards/arm/samv7/samv71-xult/src/sam_boot.c | 4 +-
boards/arm/samv7/samv71-xult/src/sam_buttons.c | 8 +-
boards/arm/samv7/samv71-xult/src/sam_ethernet.c | 10 +-
boards/arm/samv7/samv71-xult/src/sam_hsmci.c | 2 +-
boards/arm/samv7/samv71-xult/src/sam_ili9488.c | 8 +-
boards/arm/samv7/samv71-xult/src/sam_maxtouch.c | 4 +-
boards/arm/samv7/samv71-xult/src/sam_mrf24j40.c | 4 +-
boards/arm/samv7/samv71-xult/src/sam_spi.c | 6 +-
boards/arm/samv7/samv71-xult/src/sam_wm8904.c | 8 +-
boards/arm/stm32/axoloti/src/stm32_boot.c | 2 +-
boards/arm/stm32/axoloti/src/stm32_sdio.c | 4 +-
boards/arm/stm32/axoloti/src/stm32_usbhost.c | 2 +-
.../arm/stm32/clicker2-stm32/src/stm32_automount.c | 4 +-
boards/arm/stm32/clicker2-stm32/src/stm32_boot.c | 2 +-
.../arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c | 8 +-
boards/arm/stm32/clicker2-stm32/src/stm32_spi.c | 4 +-
boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c | 8 +-
boards/arm/stm32/cloudctrl/src/stm32_usb.c | 2 +-
boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c | 8 +-
boards/arm/stm32/hymini-stm32v/src/stm32_appinit.c | 2 +-
boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c | 2 +-
boards/arm/stm32/hymini-stm32v/src/stm32_ts.c | 6 +-
boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c | 2 +-
boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c | 4 +-
boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c | 12 +-
.../stm32/mikroe-stm32f4/src/stm32_touchscreen.c | 24 +-
boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c | 2 +-
boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c | 8 +-
boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c | 2 +-
boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c | 2 +-
boards/arm/stm32/nucleo-f303re/src/stm32_spi.c | 6 +-
boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c | 4 +-
boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c | 2 +-
boards/arm/stm32/nucleo-f303ze/src/stm32_ssd1306.c | 2 +-
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boards/arm/str71x/olimex-strp711/src/str71_spi.c | 21 +-
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drivers/sensors/adxl345_base.c | 4 -
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drivers/sensors/bmg160.c | 2 -
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drivers/sensors/bmp280.c | 2 +-
drivers/sensors/dhtxx.c | 15 +-
drivers/sensors/hc_sr04.c | 87 +-
drivers/sensors/hts221.c | 63 +-
drivers/sensors/kxtj9.c | 21 +-
drivers/sensors/l3gd20.c | 1 -
drivers/sensors/lis2dh.c | 12 +-
drivers/sensors/lps25h.c | 115 +--
drivers/sensors/lsm6dsl.c | 161 ++--
drivers/sensors/max31855.c | 6 +-
drivers/sensors/max44009.c | 65 +-
drivers/sensors/max6675.c | 6 +-
drivers/sensors/mpl115a.c | 10 +-
drivers/sensors/scd30.c | 72 +-
drivers/sensors/sgp30.c | 66 +-
drivers/sensors/sht21.c | 65 +-
drivers/sensors/sht3x.c | 53 +-
drivers/sensors/sps30.c | 64 +-
drivers/sensors/t67xx.c | 24 +-
drivers/sensors/xen1210.c | 19 +-
drivers/serial/lowconsole.c | 2 +-
drivers/serial/ptmx.c | 16 +-
drivers/serial/pty.c | 40 +-
drivers/serial/serial.c | 54 +-
drivers/serial/uart_16550.c | 10 +-
drivers/spi/spi_bitbang.c | 17 +-
drivers/spi/spi_driver.c | 4 -
drivers/spi/spi_transfer.c | 2 +-
drivers/syslog/syslog_chardev.c | 2 +-
drivers/syslog/syslog_console.c | 2 +-
drivers/syslog/syslog_device.c | 8 +-
drivers/syslog/syslog_filechannel.c | 6 +-
drivers/syslog/syslog_flush.c | 2 +-
drivers/syslog/syslog_force.c | 2 +-
drivers/syslog/syslog_putc.c | 2 +-
drivers/syslog/syslog_write.c | 2 +-
drivers/timers/pwm.c | 3 +-
drivers/timers/rpmsg_rtc.c | 13 +-
drivers/timers/rtc.c | 6 +-
drivers/timers/timer.c | 4 +-
drivers/timers/watchdog.c | 4 +-
drivers/usbdev/cdcacm.c | 26 +-
drivers/usbdev/cdcecm.c | 20 +-
drivers/usbdev/pl2303.c | 2 +-
drivers/usbdev/rndis.c | 8 +-
drivers/usbdev/usbdev_trace.c | 2 +-
drivers/usbdev/usbmsc.c | 11 +-
drivers/usbdev/usbmsc_scsi.c | 28 +-
drivers/usbhost/usbhost_cdcacm.c | 52 +-
drivers/usbhost/usbhost_devaddr.c | 16 +-
drivers/usbhost/usbhost_enumerate.c | 2 +-
drivers/usbhost/usbhost_hidkbd.c | 28 +-
drivers/usbhost/usbhost_hidmouse.c | 27 +-
drivers/usbhost/usbhost_hub.c | 16 +-
drivers/usbhost/usbhost_max3421e.c | 42 +-
drivers/usbhost/usbhost_skeleton.c | 22 +-
drivers/usbhost/usbhost_storage.c | 24 +-
drivers/usbhost/usbhost_xboxcontroller.c | 33 +-
drivers/usbmisc/fusb301.c | 4 +-
drivers/usbmisc/fusb303.c | 4 +-
drivers/usbmonitor/usbmonitor.c | 4 +-
drivers/video/fb.c | 4 +-
drivers/video/ov2640.c | 2 +-
drivers/video/video.c | 52 +-
drivers/video/video_framebuff.c | 12 +-
drivers/wireless/bluetooth/bt_uart.c | 2 +-
drivers/wireless/bluetooth/bt_uart_bcm4343x.c | 38 +-
drivers/wireless/cc1101.c | 47 +-
drivers/wireless/gs2200m.c | 30 +-
drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c | 4 +-
drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c | 20 +-
drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c | 8 +-
drivers/wireless/ieee80211/bcm43xxx/bcmf_utils.c | 2 +-
drivers/wireless/ieee802154/xbee/xbee.c | 10 +-
drivers/wireless/ieee802154/xbee/xbee_mac.c | 10 +-
drivers/wireless/ieee802154/xbee/xbee_netdev.c | 19 +-
drivers/wireless/lpwan/sx127x/sx127x.c | 31 +-
drivers/wireless/nrf24l01.c | 39 +-
drivers/wireless/spirit/drivers/spirit_netdev.c | 56 +-
drivers/wireless/spirit/lib/spirit_calibration.c | 12 +-
drivers/wireless/spirit/lib/spirit_csma.c | 16 +-
drivers/wireless/spirit/lib/spirit_directrf.c | 4 +-
drivers/wireless/spirit/lib/spirit_general.c | 12 +-
drivers/wireless/spirit/lib/spirit_gpio.c | 8 +-
drivers/wireless/spirit/lib/spirit_linearfifo.c | 12 +-
drivers/wireless/spirit/lib/spirit_pktbasic.c | 6 +-
drivers/wireless/spirit/lib/spirit_pktcommon.c | 56 +-
drivers/wireless/spirit/lib/spirit_pktmbus.c | 8 +-
drivers/wireless/spirit/lib/spirit_pktstack.c | 6 +-
drivers/wireless/spirit/lib/spirit_qi.c | 20 +-
drivers/wireless/spirit/lib/spirit_radio.c | 72 +-
drivers/wireless/spirit/lib/spirit_spi.c | 10 +-
drivers/wireless/spirit/lib/spirit_timer.c | 4 +-
fs/aio/aio_cancel.c | 6 +-
fs/aio/aio_fsync.c | 2 +-
fs/aio/aio_initialize.c | 37 +-
fs/aio/aio_read.c | 2 +-
fs/aio/aio_write.c | 2 +-
fs/driver/fs_blockproxy.c | 14 +-
fs/driver/fs_mtdproxy.c | 12 +-
fs/fat/fs_fat32.c | 8 +-
fs/fat/fs_fat32dirent.c | 2 +-
fs/fat/fs_fat32util.c | 16 +-
fs/hostfs/hostfs.c | 16 +-
fs/hostfs/hostfs_rpmsg.c | 14 +-
fs/inode/fs_filedetach.c | 16 +-
fs/inode/fs_fileopen.c | 2 +-
fs/inode/fs_files.c | 22 +-
fs/inode/fs_inode.c | 16 +-
fs/inode/fs_inodesearch.c | 4 +-
fs/littlefs/lfs_vfs.c | 16 +-
fs/mount/fs_automount.c | 10 +-
fs/mount/fs_procfs_mount.c | 2 +-
fs/nfs/nfs_util.c | 16 +-
fs/nfs/nfs_vfsops.c | 2 +-
fs/nfs/rpc_clnt.c | 2 +-
fs/procfs/fs_procfsmeminfo.c | 4 +-
fs/procfs/fs_procfsproc.c | 4 +-
fs/romfs/fs_romfs.c | 2 +-
fs/romfs/fs_romfsutil.c | 16 +-
fs/smartfs/smartfs_utils.c | 24 +-
fs/spiffs/src/spiffs_core.c | 2 +-
fs/spiffs/src/spiffs_vfs.c | 16 +-
fs/tmpfs/fs_tmpfs.c | 14 +-
fs/unionfs/fs_unionfs.c | 35 +-
fs/userfs/fs_userfs.c | 128 +--
fs/vfs/fs_close.c | 2 +-
fs/vfs/fs_fcntl.c | 2 +-
fs/vfs/fs_fdopen.c | 2 +-
fs/vfs/fs_fsync.c | 2 +-
fs/vfs/fs_open.c | 2 +-
fs/vfs/fs_poll.c | 21 +-
fs/vfs/fs_pread.c | 2 +-
fs/vfs/fs_pwrite.c | 2 +-
fs/vfs/fs_read.c | 2 +-
fs/vfs/fs_readlink.c | 2 +-
fs/vfs/fs_rename.c | 14 +-
fs/vfs/fs_select.c | 2 +-
fs/vfs/fs_write.c | 2 +-
graphics/nxglib/lcd/nxglib_copyrectangle.c | 4 +-
graphics/nxglib/lcd/nxglib_fillrectangle.c | 2 +-
graphics/nxglib/lcd/nxglib_filltrapezoid.c | 2 +-
graphics/nxglib/lcd/nxglib_getrectangle.c | 2 +-
graphics/nxglib/lcd/nxglib_moverectangle.c | 8 +-
graphics/nxglib/lcd/nxglib_setpixel.c | 6 +-
graphics/nxmu/nxmu_kbdin.c | 2 +-
graphics/nxmu/nxmu_redraw.c | 4 +-
graphics/nxmu/nxmu_server.c | 4 +-
graphics/nxmu/nxmu_start.c | 2 +-
graphics/nxterm/nxterm_putc.c | 2 +-
graphics/nxterm/nxterm_redraw.c | 13 +-
graphics/nxterm/nxterm_resize.c | 7 +-
graphics/nxterm/nxterm_unregister.c | 2 +-
graphics/vnc/server/vnc_fbdev.c | 33 +-
graphics/vnc/server/vnc_keymap.c | 2 +-
graphics/vnc/server/vnc_receiver.c | 2 +-
graphics/vnc/server/vnc_updater.c | 45 +-
include/nuttx/net/net.h | 38 +
include/nuttx/semaphore.h | 80 +-
include/strings.h | 4 +-
libs/libc/aio/lio_listio.c | 12 +-
libs/libc/dlfcn/lib_dlclose.c | 2 +-
libs/libc/dlfcn/lib_dlopen.c | 2 +-
libs/libc/math/lib_floor.c | 2 +-
libs/libc/math/lib_floorf.c | 2 +-
libs/libc/math/lib_floorl.c | 2 +-
libs/libc/math/lib_trunc.c | 2 +-
libs/libc/math/lib_truncf.c | 2 +-
libs/libc/math/lib_truncl.c | 2 +-
libs/libc/misc/lib_filesem.c | 2 +-
libs/libc/misc/lib_stream.c | 6 +-
libs/libc/misc/lib_streamsem.c | 2 +-
libs/libc/modlib/modlib_registry.c | 2 +-
libs/libc/net/lib_inetpton.c | 4 +-
libs/libc/netdb/lib_dnscache.c | 2 +-
libs/libc/netdb/lib_getnameinfo.c | 2 +-
libs/libc/netdb/lib_parsehostfile.c | 6 +-
libs/libc/pthread/pthread_barrierwait.c | 4 +-
libs/libc/pthread/pthread_rwlock_rdlock.c | 2 +-
libs/libc/pthread/pthread_rwlock_wrlock.c | 4 +-
libs/libc/pthread/pthread_yield.c | 2 +-
libs/libc/signal/sig_hold.c | 2 +-
libs/libc/signal/sig_psignal.c | 8 +-
libs/libc/signal/sig_relse.c | 2 +-
libs/libc/signal/sig_set.c | 6 +-
libs/libc/signal/sig_signal.c | 2 +-
libs/libc/stdio/legacy_libvsprintf.c | 2 +-
libs/libc/stdio/lib_fopen.c | 2 +-
libs/libc/stdio/lib_freopen.c | 2 +-
libs/libc/stdio/lib_libvsprintf.c | 2 +-
libs/libc/stdio/lib_perror.c | 4 +-
libs/libc/stdio/lib_setbuf.c | 2 +-
libs/libc/stdio/lib_tempnam.c | 2 +-
libs/libc/stdio/lib_tmpnam.c | 2 +-
libs/libc/stdio/lib_vasprintf.c | 2 +-
libs/libc/stdlib/lib_mkstemp.c | 2 +-
libs/libc/stdlib/lib_srand.c | 4 +-
libs/libc/string/lib_strerrorr.c | 2 +-
libs/libc/time/lib_localtime.c | 12 +-
libs/libc/uio/lib_writev.c | 2 +-
libs/libc/unistd/lib_daemon.c | 20 +-
libs/libc/wqueue/work_lock.c | 4 +-
libs/libc/wqueue/work_usrthread.c | 18 +-
libs/libnx/nxfonts/nxfonts_cache.c | 2 +-
libs/libnx/nxmu/nx_bitmap.c | 4 +-
libs/libnx/nxmu/nx_disconnect.c | 2 +-
libs/libnx/nxmu/nx_eventhandler.c | 4 +-
libs/libnx/nxmu/nx_getrectangle.c | 2 +-
libs/libnx/nxtk/nxtk_closetoolbar.c | 2 +-
libs/libnx/nxtk/nxtk_opentoolbar.c | 2 +-
libs/libnx/nxtk/nxtk_setsize.c | 2 +-
mm/iob/iob_alloc.c | 22 +-
mm/iob/iob_alloc_qentry.c | 22 +-
mm/iob/iob_trimhead.c | 2 +-
mm/mm_gran/mm_grancritical.c | 14 +-
mm/mm_heap/mm_sem.c | 2 +-
net/arp/arp_notify.c | 18 +-
net/arp/arp_poll.c | 2 +-
net/arp/arp_send.c | 4 +-
net/arp/arp_table.c | 2 +-
net/bluetooth/bluetooth_input.c | 2 +-
net/bluetooth/bluetooth_poll.c | 2 +-
net/bluetooth/bluetooth_recvfrom.c | 6 +-
net/bluetooth/bluetooth_sendto.c | 4 +-
net/icmp/icmp_conn.c | 13 +-
net/icmp/icmp_input.c | 2 +-
net/icmp/icmp_netpoll.c | 3 +-
net/icmp/icmp_poll.c | 2 +-
net/icmp/icmp_recvfrom.c | 2 +-
net/icmpv6/icmpv6_autoconfig.c | 4 +-
net/icmpv6/icmpv6_conn.c | 13 +-
net/icmpv6/icmpv6_input.c | 2 +-
net/icmpv6/icmpv6_neighbor.c | 4 +-
net/icmpv6/icmpv6_notify.c | 8 +-
net/icmpv6/icmpv6_recvfrom.c | 2 +-
net/icmpv6/icmpv6_rnotify.c | 8 +-
net/ieee802154/ieee802154_input.c | 6 +-
net/ieee802154/ieee802154_poll.c | 2 +-
net/ieee802154/ieee802154_recvfrom.c | 6 +-
net/ieee802154/ieee802154_sendto.c | 4 +-
net/igmp/igmp_group.c | 2 +-
net/igmp/igmp_initialize.c | 2 +-
net/igmp/igmp_msg.c | 15 +-
net/inet/inet_close.c | 2 +-
net/inet/inet_recvfrom.c | 16 +-
net/ipforward/ipv4_forward.c | 2 +-
net/ipforward/ipv6_forward.c | 2 +-
net/local/local_accept.c | 1 -
net/local/local_bind.c | 2 +-
net/local/local_connect.c | 20 +-
net/local/local_fifo.c | 20 +-
net/local/local_netpoll.c | 3 +-
net/local/local_recvfrom.c | 4 +-
net/local/local_sendto.c | 2 +-
net/local/local_sockif.c | 2 +-
net/mld/mld_group.c | 4 +-
net/mld/mld_initialize.c | 2 +-
net/mld/mld_msg.c | 15 +-
net/netdev/netdev_ioctl.c | 2 +-
net/netdev/netdev_txnotify.c | 6 +-
net/netlink/netlink_conn.c | 15 +-
net/pkt/pkt_conn.c | 15 +-
net/pkt/pkt_poll.c | 2 +-
net/pkt/pkt_recvfrom.c | 4 +-
net/pkt/pkt_send.c | 4 +-
net/procfs/net_procfs_route.c | 16 +-
net/route/net_add_fileroute.c | 4 +-
net/route/net_cacheroute.c | 22 +-
net/route/net_del_fileroute.c | 8 +-
net/route/net_del_ramroute.c | 12 +-
net/route/net_fileroute.c | 12 +-
net/route/net_foreach_fileroute.c | 4 +-
net/route/net_router.c | 4 +-
net/sixlowpan/sixlowpan_framelist.c | 2 +-
net/sixlowpan/sixlowpan_icmpv6send.c | 2 +-
net/sixlowpan/sixlowpan_send.c | 2 +-
net/sixlowpan/sixlowpan_tcpsend.c | 4 +-
net/sixlowpan/sixlowpan_udpsend.c | 2 +-
net/socket/accept.c | 2 +-
net/socket/connect.c | 2 +-
net/socket/net_clone.c | 2 +-
net/socket/net_sockets.c | 21 +-
net/socket/recvfrom.c | 2 +-
net/socket/send.c | 2 +-
net/socket/sendto.c | 2 +-
net/tcp/tcp.h | 2 +-
net/tcp/tcp_backlog.c | 4 +-
net/tcp/tcp_callback.c | 4 +-
net/tcp/tcp_connect.c | 6 +-
net/tcp/tcp_input.c | 12 +-
net/tcp/tcp_listen.c | 2 +-
net/tcp/tcp_monitor.c | 4 +-
net/tcp/tcp_netpoll.c | 2 +-
net/tcp/tcp_send_unbuffered.c | 4 +-
net/tcp/tcp_txdrain.c | 6 +-
net/udp/udp_callback.c | 8 +-
net/udp/udp_conn.c | 15 +-
net/udp/udp_devpoll.c | 2 +-
net/udp/udp_netpoll.c | 2 +-
net/udp/udp_psock_sendto_buffered.c | 2 +-
net/udp/udp_txdrain.c | 6 +-
net/usrsock/usrsock_accept.c | 6 +-
net/usrsock/usrsock_bind.c | 6 +-
net/usrsock/usrsock_close.c | 5 +-
net/usrsock/usrsock_conn.c | 17 +-
net/usrsock/usrsock_connect.c | 2 -
net/usrsock/usrsock_dev.c | 38 +-
net/usrsock/usrsock_event.c | 2 +-
net/usrsock/usrsock_getpeername.c | 6 +-
net/usrsock/usrsock_getsockname.c | 6 +-
net/usrsock/usrsock_getsockopt.c | 6 +-
net/usrsock/usrsock_ioctl.c | 6 +-
net/usrsock/usrsock_listen.c | 2 -
net/usrsock/usrsock_recvfrom.c | 6 +-
net/usrsock/usrsock_sendto.c | 6 +-
net/usrsock/usrsock_setsockopt.c | 6 +-
net/usrsock/usrsock_socket.c | 6 +-
net/utils/net_lock.c | 150 ++-
sched/clock/clock_initialize.c | 4 +-
sched/clock/clock_settime.c | 2 +-
sched/clock/clock_systimer.c | 4 +-
sched/environ/env_setenv.c | 2 +-
sched/environ/env_unsetenv.c | 2 +-
sched/group/group_create.c | 6 +-
sched/group/group_leave.c | 4 +-
sched/group/group_setupidlefiles.c | 6 +-
sched/group/group_setupstreams.c | 6 +-
sched/group/group_setuptaskfiles.c | 4 +-
sched/init/nx_bringup.c | 10 +-
sched/init/nx_smpstart.c | 2 +-
sched/irq/irq_procfs.c | 2 +-
sched/irq/irq_unexpectedisr.c | 2 +-
sched/module/mod_insmod.c | 2 +-
sched/module/mod_rmmod.c | 2 +-
sched/mqueue/mq_receive.c | 2 +-
sched/mqueue/mq_release.c | 2 +-
sched/mqueue/mq_send.c | 2 +-
sched/mqueue/mq_setattr.c | 2 +-
sched/mqueue/mq_timedreceive.c | 6 +-
sched/mqueue/mq_timedsend.c | 6 +-
sched/paging/pg_miss.c | 4 +-
sched/paging/pg_worker.c | 12 +-
sched/pthread/pthread_cancel.c | 2 +-
sched/pthread/pthread_completejoin.c | 14 +-
sched/pthread/pthread_condtimedwait.c | 16 +-
sched/pthread/pthread_condwait.c | 2 +-
sched/pthread/pthread_create.c | 18 +-
sched/pthread/pthread_detach.c | 4 +-
sched/pthread/pthread_exit.c | 2 +-
sched/pthread/pthread_initialize.c | 63 +-
sched/pthread/pthread_join.c | 18 +-
sched/pthread/pthread_mutexinconsistent.c | 2 +-
sched/pthread/pthread_release.c | 6 +-
sched/sched/sched_addreadytorun.c | 4 +-
sched/sched/sched_lock.c | 6 +-
sched/sched/sched_processtimer.c | 2 +-
sched/sched/sched_releasetcb.c | 2 +-
sched/sched/sched_setparam.c | 4 +-
sched/sched/sched_setscheduler.c | 4 +-
sched/sched/sched_sporadic.c | 2 +-
sched/sched/sched_timerexpiration.c | 8 +-
sched/sched/sched_waitid.c | 8 +-
sched/sched/sched_waitpid.c | 14 +-
sched/semaphore/sem_holder.c | 28 +-
sched/semaphore/sem_tickwait.c | 4 +-
sched/semaphore/sem_timedwait.c | 6 +-
sched/signal/sig_action.c | 2 +-
sched/signal/sig_default.c | 10 +-
sched/signal/sig_nanosleep.c | 10 +-
sched/signal/sig_pause.c | 4 +-
sched/signal/sig_suspend.c | 2 +-
sched/signal/sig_timedwait.c | 6 +-
sched/signal/sig_waitinfo.c | 2 +-
sched/task/task_create.c | 2 +-
sched/task/task_exit.c | 4 +-
sched/task/task_exithook.c | 8 +-
sched/task/task_init.c | 2 +-
sched/task/task_posixspawn.c | 2 +-
sched/task/task_restart.c | 4 +-
sched/task/task_setup.c | 8 +-
sched/task/task_spawn.c | 2 +-
sched/task/task_spawnparms.c | 15 +-
sched/task/task_testcancel.c | 2 +-
sched/task/task_vfork.c | 2 +-
sched/timer/timer_gettime.c | 4 +-
sched/timer/timer_release.c | 2 +-
sched/timer/timer_settime.c | 12 +-
sched/wdog/wd_cancel.c | 4 +-
sched/wdog/wd_recover.c | 4 +-
sched/wdog/wd_start.c | 2 +-
sched/wqueue/kwork_inherit.c | 8 +-
sched/wqueue/kwork_notifier.c | 18 +-
sched/wqueue/kwork_process.c | 2 +-
tools/configure.c | 2 +-
tools/convert-comments.c | 12 +-
tools/gencromfs.c | 8 +-
tools/initialconfig.c | 4 +-
tools/kconfig2html.c | 14 +-
tools/lowhex.c | 2 +-
tools/mksyscall.c | 2 +-
tools/rmcr.c | 2 +-
wireless/bluetooth/bt_conn.c | 24 +-
wireless/bluetooth/bt_hcicore.c | 18 +-
wireless/bluetooth/bt_ioctl.c | 11 +-
wireless/bluetooth/bt_netdev.c | 12 +-
wireless/ieee802154/mac802154.c | 4 +-
wireless/ieee802154/mac802154.h | 2 +-
wireless/ieee802154/mac802154_data.c | 4 +-
wireless/ieee802154/mac802154_device.c | 17 +-
wireless/ieee802154/mac802154_internal.h | 25 +-
wireless/ieee802154/mac802154_loopback.c | 14 +-
wireless/ieee802154/mac802154_netdev.c | 31 +-
wireless/ieee802154/mac802154_scan.c | 2 -
wireless/pktradio/pktradio_loopback.c | 14 +-
wireless/pktradio/pktradio_metadata.c | 31 +-
1650 files changed, 10106 insertions(+), 11736 deletions(-)
create mode 100644 arch/arm/src/samd5e5/hardware/sam_gmac.h
copy boards/arm/stm32/nucleo-f303ze/src/stm32_ssd1306.c => arch/arm/src/samd5e5/sam_ethernet.c (68%)
copy arch/arm/src/{stm32/stm32_fmc.h => samd5e5/sam_ethernet.h} (55%)
copy arch/arm/src/{sama5 => samd5e5}/sam_gmac.c (93%)
create mode 100644 arch/arm/src/stm32h7/hardware/stm32_fmc.h
copy arch/arm/src/{stm32 => stm32h7}/stm32_fmc.c (77%)
copy arch/arm/src/{stm32 => stm32h7}/stm32_fmc.h (89%)
create mode 100644 boards/arm/samd5e5/same54-xplained-pro/Kconfig
create mode 100644 boards/arm/samd5e5/same54-xplained-pro/README.txt
create mode 100644 boards/arm/samd5e5/same54-xplained-pro/configs/nsh/defconfig
create mode 100644 boards/arm/samd5e5/same54-xplained-pro/include/board.h
create mode 100644 boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs
create mode 100644 boards/arm/samd5e5/same54-xplained-pro/scripts/flash.ld
copy drivers/bch/bchlib_sem.c => boards/arm/samd5e5/same54-xplained-pro/scripts/nvm.c (74%)
copy boards/arm/samd5e5/{metro-m4 => same54-xplained-pro}/scripts/nvm.srec (100%)
create mode 100644 boards/arm/samd5e5/same54-xplained-pro/scripts/sram.ld
create mode 100644 boards/arm/samd5e5/same54-xplained-pro/src/Makefile
copy boards/arm/{nrf52/nrf52-feather/src/nrf52_boot.c => samd5e5/same54-xplained-pro/src/sam_appinit.c} (65%)
copy boards/arm/samd5e5/{metro-m4 => same54-xplained-pro}/src/sam_autoleds.c (94%)
copy boards/arm/samd5e5/{metro-m4 => same54-xplained-pro}/src/sam_boot.c (97%)
copy boards/arm/{stm32f7/stm32f769i-disco/src/stm32_bringup.c => samd5e5/same54-xplained-pro/src/sam_bringup.c} (77%)
copy libs/libc/stdio/lib_perror.c => boards/arm/samd5e5/same54-xplained-pro/src/sam_phyinit.c (77%)
copy boards/arm/samd5e5/{metro-m4 => same54-xplained-pro}/src/sam_userleds.c (93%)
copy boards/arm/{stm32/stm32f103-minimum/src/stm32_ssd1306.c => samd5e5/same54-xplained-pro/src/same54-xplained-pro.h} (62%)
[incubator-nuttx] 02/13: Squashed commit of the following:
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 13d8cb1b4bcff0eaaeadeb85cc269f896864810a
Author: Minamiya_Natsuki <yu...@gmail.com>
AuthorDate: Thu Jan 2 12:17:16 2020 -0300
Squashed commit of the following:
Author: Alan Carvalho de Assis <ac...@gmail.com>
Run all .h and .c files modified in last PR through nxstyle.
Author: Minamiya_Natsuki <yu...@gmail.com>
Add FMC SDRAM for STM32H7x3 chip (#22)
* Add FMC SDRAM for STM32H7x3 chip
* Add FMC SDRAM for STM32H7x7
* Nuttx Coding Standard requires one declaration per line
* should be __ARCH_ARM_SRC_STM32H7_STM32_FMC_H
* fix bad alignment
* fix typo
* fix typo
* people can't live in furture
* fix comment line length
* fix more comment line length
* fix aligenment
* fix typo
---
arch/arm/include/stm32h7/chip.h | 7 +-
arch/arm/src/stm32/stm32_fmc.c | 24 +-
arch/arm/src/stm32/stm32_fmc.h | 12 +-
arch/arm/src/stm32h7/Kconfig | 19 +
arch/arm/src/stm32h7/Make.defs | 4 +
arch/arm/src/stm32h7/hardware/stm32_fmc.h | 390 +++++++++++++++++++++
arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h | 224 ++++++------
arch/arm/src/stm32h7/stm32.h | 1 +
arch/arm/src/{stm32 => stm32h7}/stm32_fmc.c | 103 +++---
arch/arm/src/{stm32 => stm32h7}/stm32_fmc.h | 30 +-
10 files changed, 610 insertions(+), 204 deletions(-)
diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h
index 8ca3f90..078a1f2 100644
--- a/arch/arm/include/stm32h7/chip.h
+++ b/arch/arm/include/stm32h7/chip.h
@@ -166,13 +166,14 @@
# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */
#endif
-#if defined(CONFIG_STM32F7_HAVE_FMC)
-# define STM32F7_NFMC 1 /* Have FMC memory controller */
+#if defined(CONFIG_STM32H7_HAVE_FMC)
+# define STM32H7_NFMC 1 /* Have FMC memory controller */
#else
-# define STM32F7_NFMC 0 /* No FMC memory controller */
+# define STM32H7_NFMC 0 /* No FMC memory controller */
#endif
/* NVIC priority levels **************************************************************/
+
/* 16 Programmable interrupt levels */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/stm32/stm32_fmc.c
index 9180bf7..d13f3de 100644
--- a/arch/arm/src/stm32/stm32_fmc.c
+++ b/arch/arm/src/stm32/stm32_fmc.c
@@ -1,7 +1,7 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/stm32/stm32_fmc.c
*
- * Copyright (C) 20019 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Jason T. Harris <si...@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
@@ -31,11 +31,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
@@ -43,9 +43,9 @@
#if defined(CONFIG_STM32_FMC)
-/************************************************************************************
+/****************************************************************************
* Public Functions
- ************************************************************************************/
+ ****************************************************************************/
/****************************************************************************
* Name: stm32_fmc_sdram_wait
@@ -64,6 +64,7 @@ void stm32_fmc_sdram_wait(void)
{
break;
}
+
timeout--;
}
@@ -106,7 +107,8 @@ void stm32_fmc_disable(void)
void stm32_fmc_sdram_write_protect(int bank, bool state)
{
- uint32_t val, sdcr;
+ uint32_t val;
+ uint32_t sdcr;
DEBUGASSERT(bank == 1 || bank == 2);
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
@@ -158,7 +160,8 @@ void stm32_fmc_sdram_set_refresh_rate(int count)
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
{
- uint32_t val, sdtr;
+ uint32_t val
+ uint32_t sdtr;
DEBUGASSERT((bank == 1) || (bank == 2));
DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
@@ -180,7 +183,8 @@ void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
{
- uint32_t val, sdcr;
+ uint32_t val
+ uint32_t sdcr;
DEBUGASSERT((bank == 1) || (bank == 2));
DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
diff --git a/arch/arm/src/stm32/stm32_fmc.h b/arch/arm/src/stm32/stm32_fmc.h
index 1884500..4729461 100644
--- a/arch/arm/src/stm32/stm32_fmc.h
+++ b/arch/arm/src/stm32/stm32_fmc.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/stm32/stm32_fmc.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
@@ -31,23 +31,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H
#define __ARCH_ARM_STC_STM32_STM32_FMC_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/stm32_fmc.h"
-/************************************************************************************
+/****************************************************************************
* Public Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index 3fabadb..788056a 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -41,6 +41,7 @@ config STM32H7_STM32H7X3XX
select ARMV7M_HAVE_ITCM
select ARMV7M_HAVE_DTCM
select STM32H7_HAVE_ETHERNET
+ select STM32H7_HAVE_FMC
select STM32H7_HAVE_SPI4
select STM32H7_HAVE_SPI5
select STM32H7_HAVE_SPI6
@@ -58,6 +59,7 @@ config STM32H7_STM32H7X7XX
select ARMV7M_HAVE_ITCM
select ARMV7M_HAVE_DTCM
select STM32H7_HAVE_ETHERNET
+ select STM32H7_HAVE_FMC
select STM32H7_HAVE_SPI4
select STM32H7_HAVE_SPI5
select STM32H7_HAVE_SPI6
@@ -148,6 +150,10 @@ config STM32H7_HAVE_ETHERNET
bool
default n
+config STM32H7_HAVE_FMC
+ bool
+ default n
+
config STM32H7_HAVE_SPI4
bool
default n
@@ -274,6 +280,11 @@ config STM32H7_ETHMAC
select NETDEVICES
select ARCH_HAVE_PHY
+config STM32H7_FMC
+ bool "FMC"
+ default n
+ depends on STM32H7_HAVE_FMC
+
config STM32H7_OTGFS
bool "OTG FS"
default n
@@ -1143,6 +1154,14 @@ config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
endif # STM32H7_RTC_LSECLOCK
+config STM32H7_EXTERNAL_RAM
+ bool "External RAM on FMC"
+ default n
+ depends on STM32H7_FMC
+ select ARCH_HAVE_HEAP2
+ ---help---
+ In addition to internal SDRAM, external RAM may be available through the FMC.
+
endmenu # RTC Configuration
config STM32H7_CUSTOM_CLOCKCONFIG
diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs
index 5a13230..90921db 100644
--- a/arch/arm/src/stm32h7/Make.defs
+++ b/arch/arm/src/stm32h7/Make.defs
@@ -141,6 +141,10 @@ ifeq ($(CONFIG_STM32H7_DMA),y)
CHIP_CSRCS += stm32_dma.c
endif
+ifeq ($(CONFIG_STM32H7_FMC),y)
+CHIP_CSRCS += stm32_fmc.c
+endif
+
ifeq ($(filter y,$(CONFIG_STM32H7_IWDG) $(CONFIG_STM32H7_RTC_LSICLOCK)),y)
CHIP_CSRCS += stm32_lsi.c
endif
diff --git a/arch/arm/src/stm32h7/hardware/stm32_fmc.h b/arch/arm/src/stm32h7/hardware/stm32_fmc.h
new file mode 100644
index 0000000..31f726f
--- /dev/null
+++ b/arch/arm/src/stm32h7/hardware/stm32_fmc.h
@@ -0,0 +1,390 @@
+/************************************************************************************
+ * arch/arm/src/stm32h7/hardware/stm32_fmc.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1))
+#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
+#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
+#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
+#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
+
+#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004)
+#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
+#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
+#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
+#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
+
+#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104)
+#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
+#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
+#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
+#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
+
+#define STM32_FMC_PCR_OFFSET(n) (0x0020*((n)-1)+0x0040)
+#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */
+#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */
+#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */
+
+#define STM32_FMC_SR_OFFSET(n) (0x0020*((n)-1)+0x0044)
+#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */
+#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */
+#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */
+
+#define STM32_FMC_PMEM_OFFSET(n) (0x0020*((n)-1)+0x0048)
+#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */
+#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */
+#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */
+
+#define STM32_FMC_PATT_OFFSET(n) (0x0020*((n)-1)+0x004c)
+#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */
+#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */
+#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */
+
+#define STM32_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */
+
+#define STM32_FMC_ECCR_OFFSET(n) (0x0020*((n)-1)+0x003c)
+#define STM32_FMC_ECCR2_OFFSET 0x0054 /* ECC result register 2 */
+#define STM32_FMC_ECCR3_OFFSET 0x0074 /* ECC result register 3 */
+
+#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */
+#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
+
+#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */
+#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */
+
+#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */
+#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */
+#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n))
+#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET )
+#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET )
+#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET )
+#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET )
+
+#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n))
+#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET )
+#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET )
+#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET )
+#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET )
+
+#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n))
+#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET )
+#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET )
+#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET )
+#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET )
+
+#define STM32_FMC_PCR(n) (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET(n))
+#define STM32_FMC_PCR2 (STM32_FMC_BASE+STM32_FMC_PCR2_OFFSET )
+#define STM32_FMC_PCR3 (STM32_FMC_BASE+STM32_FMC_PCR3_OFFSET )
+#define STM32_FMC_PCR4 (STM32_FMC_BASE+STM32_FMC_PCR4_OFFSET )
+
+#define STM32_FMC_SR(n) (STM32_FMC_BASE+STM32_FMC_SR_OFFSET(n))
+#define STM32_FMC_SR2 (STM32_FMC_BASE+STM32_FMC_SR2_OFFSET )
+#define STM32_FMC_SR3 (STM32_FMC_BASE+STM32_FMC_SR3_OFFSET )
+#define STM32_FMC_SR4 (STM32_FMC_BASE+STM32_FMC_SR4_OFFSET )
+
+#define STM32_FMC_PMEM(n) (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET(n))
+#define STM32_FMC_PMEM2 (STM32_FMC_BASE+STM32_FMC_PMEM2_OFFSET )
+#define STM32_FMC_PMEM3 (STM32_FMC_BASE+STM32_FMC_PMEM3_OFFSET )
+#define STM32_FMC_PMEM4 (STM32_FMC_BASE+STM32_FMC_PMEM4_OFFSET )
+
+#define STM32_FMC_PATT(n) (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET(n))
+#define STM32_FMC_PATT2 (STM32_FMC_BASE+STM32_FMC_PATT2_OFFSET )
+#define STM32_FMC_PATT3 (STM32_FMC_BASE+STM32_FMC_PATT3_OFFSET )
+#define STM32_FMC_PATT4 (STM32_FMC_BASE+STM32_FMC_PATT4_OFFSET )
+
+#define STM32_PIO4 (STM32_FMC_BASE+STM32_FMC_PIO4_OFFSET )
+
+#define STM32_FMC_ECCR(n) (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET(n))
+#define STM32_FMC_ECCR2 (STM32_FMC_BASE+STM32_FMC_ECCR2_OFFSET )
+#define STM32_FMC_ECCR3 (STM32_FMC_BASE+STM32_FMC_ECCR3_OFFSET )
+
+#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET)
+#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET)
+
+#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET)
+#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET)
+
+#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET)
+#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET)
+#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
+#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
+#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */
+#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT)
+# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT)
+# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT)
+# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT)
+# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT)
+# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT)
+#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
+#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT)
+# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT)
+# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT)
+#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */
+#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
+#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
+#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */
+#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
+#define FMC_BCR_WREN (1 << 12) /* Write enable bit */
+#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
+#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
+#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
+#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
+#define FMC_BCR_BMAP_SHIFT (24)
+# define FMC_BCR_BMAP_0 (0 << FMC_BCR_BMAP_SHIFT)
+# define FMC_BCR_BMAP_1 (1 << FMC_BCR_BMAP_SHIFT)
+# define FMC_BCR_BMAP_2 (2 << FMC_BCR_BMAP_SHIFT)
+
+#define FMC_BCR_FMCEN (1 << 31) /* Write burst enable */
+
+#define FMC_BCR_RSTVALUE 0x000003d2
+
+#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
+#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT)
+# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
+#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
+#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT)
+# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
+#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
+#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT)
+# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
+#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
+#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT)
+# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
+#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
+#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT)
+# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
+#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */
+#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT)
+# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
+#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
+#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT)
+# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT)
+# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT)
+# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT)
+# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
+
+#define FMC_BTR_RSTVALUE 0xffffffff
+
+#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
+#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT)
+# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
+#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
+#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT)
+# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
+#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
+#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT)
+# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
+#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
+#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT)
+# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
+#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
+#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT)
+# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
+#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
+#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT)
+# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT)
+# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT)
+# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT)
+# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
+
+#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
+#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP (1 << 3) /* Memory type */
+#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
+#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT)
+# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT)
+# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT)
+#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
+#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
+#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT)
+# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
+#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
+#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK)
+# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
+#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
+#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT)
+# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */
+# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */
+# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
+# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
+# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
+# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
+
+#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
+#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */
+#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
+#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */
+
+#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
+#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT)
+# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
+#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT)
+# define FMC_PMEM_MEMWAIT(n) ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
+#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT)
+# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
+#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT)
+# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
+#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT)
+# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
+#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT)
+# define FMC_PATT_ATTWAIT(n) ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
+#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT)
+# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
+#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT)
+# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#define FMC_PIO4_IOSET_SHIFT (0) /* IOribute memory setup time */
+#define FMC_PIO4_IOSET_MASK (255 << FMC_PIO4_IOSET_SHIFT)
+# define FMC_PIO4_IOSET(n) ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FMC_PIO4_IOWAIT_SHIFT (8) /* IOribute memory wait time */
+#define FMC_PIO4_IOWAIT_MASK (255 << FMC_PIO4_IOWAIT_SHIFT)
+# define FMC_PIO4_IOWAIT(n) ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FMC_PIO4_IOHOLD_SHIFT (16) /* IOribute memory hold time */
+#define FMC_PIO4_IOHOLD_MASK (255 << FMC_PIO4_IOHOLD_SHIFT)
+# define FMC_PIO4_IOHOLD(n) ((n) << FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FMC_PIO4_IOHIZ_SHIFT (24) /* IOribute memory databus HiZ time */
+#define FMC_PIO4_IOHIZ_MASK (255 << FMC_PIO4_IOHIZ_SHIFT)
+# define FMC_PIO4_IOHIZ(n) ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#define FMC_SDCMR_RESERVED (0x3ff << 22) /* reserved bits */
+#define FMC_SDCMR_CMD_LOAD_MODE (4 << 0)
+
+# define FMC_SDRAM_CR_COLBITS_8 0x00000000
+# define FMC_SDRAM_CR_COLBITS_9 0x00000001
+# define FMC_SDRAM_CR_COLBITS_10 0x00000002
+# define FMC_SDRAM_CR_COLBITS_11 0x00000003
+
+# define FMC_SDRAM_CR_ROWBITS_11 0x00000000
+# define FMC_SDRAM_CR_ROWBITS_12 0x00000004
+# define FMC_SDRAM_CR_ROWBITS_13 0x00000008
+
+# define FMC_SDRAM_CR_WIDTH_8 0x00000000
+# define FMC_SDRAM_CR_WIDTH_16 0x00000010
+# define FMC_SDRAM_CR_WIDTH_32 0x00000020
+
+# define FMC_SDRAM_CR_BANKS_2 0x00000000
+# define FMC_SDRAM_CR_BANKS_4 0x00000040
+
+# define FMC_SDRAM_CR_CASLAT_1 0x00000080
+# define FMC_SDRAM_CR_CASLAT_2 0x00000100
+# define FMC_SDRAM_CR_CASLAT_3 0x00000180
+
+# define FMC_SDRAM_CR_WRITE_PROTECT 0x00000200
+
+# define FMC_SDRAM_CR_SDCLK_DISABLE 0x00000000
+# define FMC_SDRAM_CR_SDCLK_2X 0x00000800
+# define FMC_SDRAM_CR_SDCLK_3X 0x00000C00
+
+# define FMC_SDRAM_CR_BURST_READ 0x00001000
+
+# define FMC_SDRAM_CR_RPIPE_0 0x00000000
+# define FMC_SDRAM_CR_RPIPE_1 0x00002000
+# define FMC_SDRAM_CR_RPIPE_2 0x00004000
+
+# define FMC_SDRAM_CR_RESERVED (0x1FFFF << 15) /* reserved bits */
+
+# define FMC_SDRAM_TR_TMRD_SHIFT 0
+# define FMC_SDRAM_TR_TXSR_SHIFT 4
+# define FMC_SDRAM_TR_TRAS_SHIFT 8
+# define FMC_SDRAM_TR_TRC_SHIFT 12
+# define FMC_SDRAM_TR_TWR_SHIFT 16
+# define FMC_SDRAM_TR_TRP_SHIFT 20
+# define FMC_SDRAM_TR_TRCD_SHIFT 24
+
+# define FMC_SDRAM_TR_RESERVED (0xF << 28) /* reserved bits */
+
+# define FMC_SDRAM_MODE_CMD_NORMAL 0
+# define FMC_SDRAM_MODE_CMD_CLK_ENABLE 1
+# define FMC_SDRAM_MODE_CMD_PALL 2
+# define FMC_SDRAM_MODE_CMD_AUTO_REFRESH 3
+# define FMC_SDRAM_MODE_CMD_LOAD_MODE 4
+# define FMC_SDRAM_MODE_CMD_SELF_REFRESH 5
+# define FMC_SDRAM_MODE_CMD_POWER_DOWN 6
+
+# define FMC_SDRAM_CMD_BANK_1 0x00000010
+# define FMC_SDRAM_CMD_BANK_2 0x00000008
+# define FMC_SDRAM_CMD_RESERVED (0x200 << 23) /* reserved bits */
+
+# define FMC_SDRAM_AUTO_REFRESH_SHIFT 5
+# define FMC_SDRAM_MODEREG_SHIFT 9
+
+# define FMC_SDRAM_MODEREG_BURST_LENGTH_1 (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_BURST_LENGTH_2 (0x0001 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_BURST_LENGTH_4 (0x0002 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_BURST_LENGTH_8 (0x0004 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_CAS_LATENCY_2 (0x0020 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_CAS_LATENCY_3 (0x0030 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
+# define FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200 << FMC_SDRAM_MODEREG_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H */
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
index 5ddd010..a99c2e6 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
@@ -319,118 +319,118 @@
/* Flexible memory controller (FMC) */
-#define GPIO_FMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
-#define GPIO_FMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
-#define GPIO_FMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
-#define GPIO_FMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
-#define GPIO_FMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
-#define GPIO_FMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
-#define GPIO_FMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
-#define GPIO_FMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
-#define GPIO_FMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
-#define GPIO_FMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
-#define GPIO_FMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
-#define GPIO_FMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
-#define GPIO_FMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
-#define GPIO_FMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
-#define GPIO_FMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
-#define GPIO_FMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
-#define GPIO_FMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
-#define GPIO_FMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
-#define GPIO_FMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
-#define GPIO_FMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
-#define GPIO_FMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
-#define GPIO_FMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
-#define GPIO_FMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
-#define GPIO_FMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
-#define GPIO_FMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
-#define GPIO_FMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
-#define GPIO_FMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
-#define GPIO_FMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
-#define GPIO_FMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
-#define GPIO_FMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
-#define GPIO_FMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
-#define GPIO_FMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
-#define GPIO_FMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
-#define GPIO_FMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
-#define GPIO_FMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
-#define GPIO_FMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
-#define GPIO_FMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
-#define GPIO_FMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
-#define GPIO_FMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
-#define GPIO_FMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
-#define GPIO_FMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
-#define GPIO_FMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
-#define GPIO_FMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
-#define GPIO_FMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
-#define GPIO_FMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
-#define GPIO_FMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
-#define GPIO_FMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
-#define GPIO_FMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
-#define GPIO_FMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
-#define GPIO_FMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
-#define GPIO_FMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
-#define GPIO_FMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
-#define GPIO_FMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
-#define GPIO_FMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
-#define GPIO_FMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
-#define GPIO_FMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
-#define GPIO_FMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
-#define GPIO_FMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
-#define GPIO_FMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
-#define GPIO_FMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
-#define GPIO_FMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
-#define GPIO_FMC_DA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
-#define GPIO_FMC_DA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
-#define GPIO_FMC_DA2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
-#define GPIO_FMC_DA3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
-#define GPIO_FMC_DA4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
-#define GPIO_FMC_DA5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
-#define GPIO_FMC_DA6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
-#define GPIO_FMC_DA7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
-#define GPIO_FMC_DA8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
-#define GPIO_FMC_DA9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
-#define GPIO_FMC_DA10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
-#define GPIO_FMC_DA11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
-#define GPIO_FMC_DA12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
-#define GPIO_FMC_DA13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
-#define GPIO_FMC_DA14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
-#define GPIO_FMC_DA15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
-#define GPIO_FMC_INT (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN7)
-#define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
-#define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
-#define GPIO_FMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
-#define GPIO_FMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
-#define GPIO_FMC_NCE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
-#define GPIO_FMC_NCE_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8)
-#define GPIO_FMC_NE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
-#define GPIO_FMC_NE1_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN7)
-#define GPIO_FMC_NE2_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
-#define GPIO_FMC_NE2_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8)
-#define GPIO_FMC_NE3_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
-#define GPIO_FMC_NE3_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
-#define GPIO_FMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
-#define GPIO_FMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
-#define GPIO_FMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
-#define GPIO_FMC_NWAIT_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
-#define GPIO_FMC_NWAIT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN6)
-#define GPIO_FMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
-#define GPIO_FMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
-#define GPIO_FMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
-#define GPIO_FMC_SDCKE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
-#define GPIO_FMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
-#define GPIO_FMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
-#define GPIO_FMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
-#define GPIO_FMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
-#define GPIO_FMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_FMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_FMC_SDNE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
-#define GPIO_FMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
-#define GPIO_FMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
-#define GPIO_FMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
-#define GPIO_FMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_FMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
-#define GPIO_FMC_SDNWE_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
+#define GPIO_FMC_A0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_FMC_A1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
+#define GPIO_FMC_A2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
+#define GPIO_FMC_A3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
+#define GPIO_FMC_A4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
+#define GPIO_FMC_A5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
+#define GPIO_FMC_A6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
+#define GPIO_FMC_A7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
+#define GPIO_FMC_A8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
+#define GPIO_FMC_A9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
+#define GPIO_FMC_A10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
+#define GPIO_FMC_A11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
+#define GPIO_FMC_A12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
+#define GPIO_FMC_A13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
+#define GPIO_FMC_A14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
+#define GPIO_FMC_A15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
+#define GPIO_FMC_A16 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
+#define GPIO_FMC_A17 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
+#define GPIO_FMC_A18 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
+#define GPIO_FMC_A19 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
+#define GPIO_FMC_A20 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
+#define GPIO_FMC_A21 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
+#define GPIO_FMC_A22 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
+#define GPIO_FMC_A23 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
+#define GPIO_FMC_A24 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
+#define GPIO_FMC_A25 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
+#define GPIO_FMC_BA0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
+#define GPIO_FMC_BA1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
+#define GPIO_FMC_CLK (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
+#define GPIO_FMC_D0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
+#define GPIO_FMC_D1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
+#define GPIO_FMC_D2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
+#define GPIO_FMC_D3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
+#define GPIO_FMC_D4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
+#define GPIO_FMC_D5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
+#define GPIO_FMC_D6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
+#define GPIO_FMC_D7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
+#define GPIO_FMC_D8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
+#define GPIO_FMC_D9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
+#define GPIO_FMC_D10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
+#define GPIO_FMC_D11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
+#define GPIO_FMC_D12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
+#define GPIO_FMC_D13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
+#define GPIO_FMC_D14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
+#define GPIO_FMC_D15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
+#define GPIO_FMC_D16 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
+#define GPIO_FMC_D17 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
+#define GPIO_FMC_D18 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
+#define GPIO_FMC_D19 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
+#define GPIO_FMC_D20 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
+#define GPIO_FMC_D21 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
+#define GPIO_FMC_D22 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
+#define GPIO_FMC_D23 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
+#define GPIO_FMC_D24 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
+#define GPIO_FMC_D25 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
+#define GPIO_FMC_D26 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
+#define GPIO_FMC_D27 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
+#define GPIO_FMC_D28 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
+#define GPIO_FMC_D29 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
+#define GPIO_FMC_D30 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
+#define GPIO_FMC_D31 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
+#define GPIO_FMC_DA0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
+#define GPIO_FMC_DA1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
+#define GPIO_FMC_DA2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
+#define GPIO_FMC_DA3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
+#define GPIO_FMC_DA4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
+#define GPIO_FMC_DA5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
+#define GPIO_FMC_DA6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
+#define GPIO_FMC_DA7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
+#define GPIO_FMC_DA8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
+#define GPIO_FMC_DA9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
+#define GPIO_FMC_DA10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
+#define GPIO_FMC_DA11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
+#define GPIO_FMC_DA12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
+#define GPIO_FMC_DA13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
+#define GPIO_FMC_DA14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
+#define GPIO_FMC_DA15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
+#define GPIO_FMC_INT (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_PORTG|GPIO_PIN7)
+#define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
+#define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
+#define GPIO_FMC_NBL2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
+#define GPIO_FMC_NBL3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
+#define GPIO_FMC_NCE_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
+#define GPIO_FMC_NCE_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_FMC_NE1_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
+#define GPIO_FMC_NE1_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_FMC_NE2_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
+#define GPIO_FMC_NE2_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_FMC_NE3_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
+#define GPIO_FMC_NE3_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
+#define GPIO_FMC_NE4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
+#define GPIO_FMC_NL (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_FMC_NOE (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
+#define GPIO_FMC_NWAIT_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
+#define GPIO_FMC_NWAIT_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_FMC_NWE (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
+#define GPIO_FMC_SDCKE0_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_FMC_SDCKE0_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_FMC_SDCKE0_3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
+#define GPIO_FMC_SDCKE1_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_FMC_SDCKE1_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
+#define GPIO_FMC_SDCLK (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
+#define GPIO_FMC_SDNCAS (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
+#define GPIO_FMC_SDNE0_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_FMC_SDNE0_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_FMC_SDNE0_3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
+#define GPIO_FMC_SDNE1_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_FMC_SDNE1_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
+#define GPIO_FMC_SDNRAS (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
+#define GPIO_FMC_SDNWE_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_FMC_SDNWE_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_FMC_SDNWE_3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
/* HDMI-CEC Controller */
diff --git a/arch/arm/src/stm32h7/stm32.h b/arch/arm/src/stm32h7/stm32.h
index f13d38b..e17ad45 100644
--- a/arch/arm/src/stm32h7/stm32.h
+++ b/arch/arm/src/stm32h7/stm32.h
@@ -55,6 +55,7 @@
#include "chip.h"
#include "stm32_gpio.h"
+#include "stm32_fmc.h"
#include "stm32_i2c.h"
#include "stm32_spi.h"
#include "stm32_rcc.h"
diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/stm32h7/stm32_fmc.c
similarity index 77%
copy from arch/arm/src/stm32/stm32_fmc.c
copy to arch/arm/src/stm32h7/stm32_fmc.c
index 9180bf7..f40e0ca 100644
--- a/arch/arm/src/stm32/stm32_fmc.c
+++ b/arch/arm/src/stm32h7/stm32_fmc.c
@@ -1,7 +1,7 @@
-/************************************************************************************
- * arch/arm/src/stm32/stm32_fmc.c
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_fmc.c
*
- * Copyright (C) 20019 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Jason T. Harris <si...@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
@@ -31,45 +31,22 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "stm32.h"
-#if defined(CONFIG_STM32_FMC)
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+#if defined(CONFIG_STM32H7_FMC)
/****************************************************************************
- * Name: stm32_fmc_sdram_wait
- *
- * Description:
- * Wait for the SDRAM controller to be ready.
- *
+ * Public Functions
****************************************************************************/
-void stm32_fmc_sdram_wait(void)
-{
- int timeout = 0xffff;
- while (timeout > 0)
- {
- if ((getreg32(STM32_FMC_SDSR) & FMC_SDSR_BUSY) == 0)
- {
- break;
- }
- timeout--;
- }
-
- DEBUGASSERT(timeout > 0);
-}
-
/****************************************************************************
* Name: stm32_fmc_enable
*
@@ -78,7 +55,7 @@ void stm32_fmc_sdram_wait(void)
*
****************************************************************************/
-void stm32_fmc_enable(void)
+void stm32_fmc_enable_clk(void)
{
modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN);
}
@@ -106,21 +83,20 @@ void stm32_fmc_disable(void)
void stm32_fmc_sdram_write_protect(int bank, bool state)
{
- uint32_t val, sdcr;
+ uint32_t val;
+ uint32_t sdcr;
DEBUGASSERT(bank == 1 || bank == 2);
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
- stm32_fmc_sdram_wait();
-
val = getreg32(sdcr);
if (state)
{
- val |= FMC_SDCR_WP; /* wp == 1 */
+ val |= FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 1 */
}
else
{
- val &= ~FMC_SDCR_WP; /* wp == 0 */
+ val &= ~FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 0 */
}
putreg32(val, sdcr);
@@ -139,13 +115,7 @@ void stm32_fmc_sdram_set_refresh_rate(int count)
uint32_t val;
DEBUGASSERT(count <= 0x1fff && count >= 0x29);
-
- stm32_fmc_sdram_wait();
-
- val = getreg32(STM32_FMC_SDRTR);
- val &= ~(0x1fff << 1); /* preserve non-count bits */
- val |= (count << 1);
- putreg32(val, STM32_FMC_SDRTR);
+ putreg32(count << 1, STM32_FMC_SDRTR);
}
/****************************************************************************
@@ -158,19 +128,35 @@ void stm32_fmc_sdram_set_refresh_rate(int count)
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
{
- uint32_t val, sdtr;
+ uint32_t val;
+ uint32_t sdtr;
DEBUGASSERT((bank == 1) || (bank == 2));
- DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
+ DEBUGASSERT((timing & FMC_SDRAM_TR_RESERVED) == 0);
sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
val = getreg32(sdtr);
- val &= FMC_SDTR_RESERVED; /* preserve reserved bits */
+ val &= FMC_SDRAM_TR_RESERVED; /* preserve reserved bits */
val |= timing;
putreg32(val, sdtr);
}
/****************************************************************************
+ * Name: stm32_fmc_enable
+ *
+ * Description:
+ * Enable FMC SDRAM. Do this after issue refresh rate.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_enable(void)
+{
+ uint32_t val;
+ val = FMC_BCR_FMCEN | getreg32(STM32_FMC_BCR1);
+ putreg32(val, STM32_FMC_BCR1);
+}
+
+/****************************************************************************
* Name: stm32_fmc_sdram_set_control
*
* Description:
@@ -180,14 +166,15 @@ void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
{
- uint32_t val, sdcr;
+ uint32_t val;
+ uint32_t sdcr;
DEBUGASSERT((bank == 1) || (bank == 2));
- DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
+ DEBUGASSERT((ctrl & FMC_SDRAM_CR_RESERVED) == 0);
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
val = getreg32(sdcr);
- val &= FMC_SDCR_RESERVED; /* preserve reserved bits */
+ val &= FMC_SDRAM_CR_RESERVED; /* preserve reserved bits */
val |= ctrl;
putreg32(val, sdcr);
}
@@ -202,18 +189,8 @@ void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
void stm32_fmc_sdram_command(uint32_t cmd)
{
- uint32_t val;
-
- DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0);
-
- /* Wait for the controller to be ready */
-
- stm32_fmc_sdram_wait();
-
- val = getreg32(STM32_FMC_SDCMR);
- val &= FMC_SDCMR_RESERVED; /* Preserve reserved bits */
- val |= cmd;
- putreg32(val, STM32_FMC_SDCMR);
+ DEBUGASSERT((cmd & FMC_SDRAM_CMD_RESERVED) == 0);
+ putreg32(cmd, STM32_FMC_SDCMR);
}
-#endif /* CONFIG_STM32_FMC */
+#endif /* CONFIG_STM32H7_FMC */
diff --git a/arch/arm/src/stm32/stm32_fmc.h b/arch/arm/src/stm32h7/stm32_fmc.h
similarity index 89%
copy from arch/arm/src/stm32/stm32_fmc.h
copy to arch/arm/src/stm32h7/stm32_fmc.h
index 1884500..9f0ccea 100644
--- a/arch/arm/src/stm32/stm32_fmc.h
+++ b/arch/arm/src/stm32h7/stm32_fmc.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/stm32/stm32_fmc.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
@@ -31,23 +31,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H
-#define __ARCH_ARM_STC_STM32_STM32_FMC_H
+#ifndef __ARCH_ARM_SRC_STM32H7_STM32_FMC_H
+#define __ARCH_ARM_SRC_STM32H7_STM32_FMC_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/stm32_fmc.h"
-/************************************************************************************
+/****************************************************************************
* Public Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
@@ -78,7 +78,7 @@ void stm32_fmc_sdram_wait(void);
*
****************************************************************************/
-void stm32_fmc_enable(void);
+void stm32_fmc_enable_clk(void);
/****************************************************************************
* Name: stm32_fmc_disable
@@ -111,6 +111,16 @@ void stm32_fmc_sdram_write_protect(int bank, bool state);
void stm32_fmc_sdram_set_refresh_rate(int count);
/****************************************************************************
+ * Name: stm32_fmc_sdram_enable
+ *
+ * Description:
+ * Enable FMC SDRAM. Do this after issue refresh rate.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_enable(void);
+
+/****************************************************************************
* Name: stm32_fmc_sdram_set_timing
*
* Description:
@@ -146,4 +156,4 @@ void stm32_fmc_sdram_command(uint32_t cmd);
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_STC_STM32_STM32_FMC_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_STM32_FMC_H */
[incubator-nuttx] 03/13: Minor fix (#23)
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 933a466a52c95ce0bc096b490d44be7ced344752
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Thu Jan 2 08:52:28 2020 -0600
Minor fix (#23)
* fix ieee802154/ieee802154_input.c:179:7: error: too few arguments to function 'iob_free'
iob_free(container->ic_iob);
^~~~~~~~
ieee802154/ieee802154_input.c:180:7: error: too many arguments to function 'ieee802154_container_free'
ieee802154_container_free(container, IOBUSER_NET_SOCK_IEEE802154);
^~~~~~~~~~~~~~~~~~~~~~~~~
* fix udp/udp_netpoll.c:327:10: warning: 'ret' may be used uninitialized in this function [-Wmaybe-uninitialized]
* fix local/local_netpoll.c:154:15: warning: implicit declaration of function 'nxsem_post'; did you mean 'sem_post'? [-Wimplicit-function-declaration]
nxsem_post(fds->sem);
^~~~~~~~~~
sem_post
---
net/ieee802154/ieee802154_input.c | 4 ++--
net/local/local_netpoll.c | 1 +
net/tcp/tcp_netpoll.c | 2 +-
net/udp/udp_netpoll.c | 2 +-
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/net/ieee802154/ieee802154_input.c b/net/ieee802154/ieee802154_input.c
index 945ec0f..ae6ba95 100644
--- a/net/ieee802154/ieee802154_input.c
+++ b/net/ieee802154/ieee802154_input.c
@@ -176,8 +176,8 @@ static int ieee802154_queue_frame(FAR struct ieee802154_conn_s *conn,
/* Free both the IOB and the container */
- iob_free(container->ic_iob);
- ieee802154_container_free(container, IOBUSER_NET_SOCK_IEEE802154);
+ iob_free(container->ic_iob, IOBUSER_NET_SOCK_IEEE802154);
+ ieee802154_container_free(container);
}
else
{
diff --git a/net/local/local_netpoll.c b/net/local/local_netpoll.c
index ebcd978..bf038c3 100644
--- a/net/local/local_netpoll.c
+++ b/net/local/local_netpoll.c
@@ -44,6 +44,7 @@
#include <errno.h>
#include <debug.h>
+#include <nuttx/semaphore.h>
#include <nuttx/net/net.h>
#include <nuttx/fs/fs.h>
diff --git a/net/tcp/tcp_netpoll.c b/net/tcp/tcp_netpoll.c
index 3890d06..e883c97 100644
--- a/net/tcp/tcp_netpoll.c
+++ b/net/tcp/tcp_netpoll.c
@@ -232,7 +232,7 @@ int tcp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds)
FAR struct tcp_conn_s *conn = psock->s_conn;
FAR struct tcp_poll_s *info;
FAR struct devif_callback_s *cb;
- int ret;
+ int ret = OK;
/* Sanity check */
diff --git a/net/udp/udp_netpoll.c b/net/udp/udp_netpoll.c
index 0bf042b..c351ea5 100644
--- a/net/udp/udp_netpoll.c
+++ b/net/udp/udp_netpoll.c
@@ -204,7 +204,7 @@ int udp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds)
FAR struct udp_conn_s *conn = psock->s_conn;
FAR struct udp_poll_s *info;
FAR struct devif_callback_s *cb;
- int ret;
+ int ret = OK;
/* Sanity check */
[incubator-nuttx] 01/13: net: tcp: Fix compile error in tcp.h
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 5b28367583ee60da093838195f5f5c58056467d4
Author: Masayuki Ishikawa <ma...@gmail.com>
AuthorDate: Wed Jan 1 07:04:39 2020 +0900
net: tcp: Fix compile error in tcp.h
---
net/tcp/tcp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/tcp/tcp.h b/net/tcp/tcp.h
index f786d3d..5430bc4 100644
--- a/net/tcp/tcp.h
+++ b/net/tcp/tcp.h
@@ -1188,7 +1188,7 @@ int tcp_backlogadd(FAR struct tcp_conn_s *conn,
#ifdef CONFIG_NET_TCPBACKLOG
bool tcp_backlogavailable(FAR struct tcp_conn_s *conn);
#else
-# define tcp_backlogavailable(c) (false);
+# define tcp_backlogavailable(c) (false)
#endif
/****************************************************************************
[incubator-nuttx] 11/13: drivers/modem/altair/altmdm_sys.c: Fix
modem/altair semaphore related compiler warning
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 54c1b4927001f0bd09091686bd8228274113bdd3
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Fri Jan 3 10:11:36 2020 +0800
drivers/modem/altair/altmdm_sys.c: Fix modem/altair semaphore related compiler warning
---
boards/arm/cxd56xx/spresense/configs/lte/defconfig | 1 -
drivers/modem/altair/altmdm_sys.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/boards/arm/cxd56xx/spresense/configs/lte/defconfig b/boards/arm/cxd56xx/spresense/configs/lte/defconfig
index 987f31e..619f59f 100644
--- a/boards/arm/cxd56xx/spresense/configs/lte/defconfig
+++ b/boards/arm/cxd56xx/spresense/configs/lte/defconfig
@@ -71,7 +71,6 @@ CONFIG_SDCLONE_DISABLE=y
CONFIG_SMARTFS_ALIGNED_ACCESS=y
CONFIG_SMARTFS_MAXNAMLEN=30
CONFIG_SMARTFS_MULTI_ROOT_DIRS=y
-CONFIG_SPI=y
CONFIG_SPRESENSE_EXTENSION=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
diff --git a/drivers/modem/altair/altmdm_sys.c b/drivers/modem/altair/altmdm_sys.c
index f4cb8e4..1cad10c 100644
--- a/drivers/modem/altair/altmdm_sys.c
+++ b/drivers/modem/altair/altmdm_sys.c
@@ -40,6 +40,7 @@
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
+#include <nuttx/semaphore.h>
#include <signal.h>
#include "altmdm_dev.h"
[incubator-nuttx] 04/13: Fix wait loop and void cast (#24)
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a3704e765585844c558650cfc6c46c4182b3f437
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Thu Jan 2 10:49:34 2020 -0600
Fix wait loop and void cast (#24)
* Simplify EINTR/ECANCEL error handling
1. Add semaphore uninterruptible wait function
2 .Replace semaphore wait loop with a single uninterruptible wait
3. Replace all sem_xxx to nxsem_xxx
* Unify the void cast usage
1. Remove void cast for function because many place ignore the returned value witout cast
2. Replace void cast for variable with UNUSED macro
---
arch/arm/src/a1x/a1x_irq.c | 4 +-
arch/arm/src/a1x/a1x_pio.c | 2 +-
arch/arm/src/a1x/a1x_serial.c | 18 +--
arch/arm/src/a1x/a1x_timerisr.c | 2 +-
arch/arm/src/am335x/am335x_gpioirq.c | 8 +-
arch/arm/src/am335x/am335x_irq.c | 6 +-
arch/arm/src/am335x/am335x_lcdc.c | 2 +-
arch/arm/src/am335x/am335x_serial.c | 14 +-
arch/arm/src/am335x/am335x_timerisr.c | 4 +-
arch/arm/src/arm/up_assert.c | 10 +-
arch/arm/src/arm/up_blocktask.c | 2 +-
arch/arm/src/arm/up_doirq.c | 2 +-
arch/arm/src/arm/up_releasepending.c | 2 +-
arch/arm/src/arm/up_reprioritizertr.c | 2 +-
arch/arm/src/arm/up_sigdeliver.c | 2 +-
arch/arm/src/arm/up_unblocktask.c | 2 +-
arch/arm/src/armv6-m/up_assert.c | 10 +-
arch/arm/src/armv6-m/up_hardfault.c | 2 +-
arch/arm/src/armv6-m/up_sigdeliver.c | 2 +-
arch/arm/src/armv6-m/up_signal_dispatch.c | 4 +-
arch/arm/src/armv7-a/arm_assert.c | 12 +-
arch/arm/src/armv7-a/arm_blocktask.c | 2 +-
arch/arm/src/armv7-a/arm_doirq.c | 2 +-
arch/arm/src/armv7-a/arm_pgalloc.c | 2 +-
arch/arm/src/armv7-a/arm_releasepending.c | 2 +-
arch/arm/src/armv7-a/arm_reprioritizertr.c | 2 +-
arch/arm/src/armv7-a/arm_sigdeliver.c | 6 +-
arch/arm/src/armv7-a/arm_signal_dispatch.c | 4 +-
arch/arm/src/armv7-a/arm_unblocktask.c | 2 +-
arch/arm/src/armv7-m/up_assert.c | 12 +-
arch/arm/src/armv7-m/up_hardfault.c | 2 +-
arch/arm/src/armv7-m/up_itm_syslog.c | 2 +-
arch/arm/src/armv7-m/up_memfault.c | 2 +-
arch/arm/src/armv7-m/up_sigdeliver.c | 6 +-
arch/arm/src/armv7-m/up_signal_dispatch.c | 4 +-
arch/arm/src/armv7-r/arm_assert.c | 10 +-
arch/arm/src/armv7-r/arm_sigdeliver.c | 2 +-
arch/arm/src/armv7-r/arm_signal_dispatch.c | 4 +-
arch/arm/src/c5471/c5471_ethernet.c | 22 +--
arch/arm/src/c5471/c5471_serial.c | 6 +-
arch/arm/src/common/up_exit.c | 6 +-
arch/arm/src/common/up_initialize.c | 8 +-
arch/arm/src/common/up_lwl_console.c | 2 +-
arch/arm/src/cxd56xx/cxd56_adc.c | 10 +-
arch/arm/src/cxd56xx/cxd56_charger.c | 9 +-
arch/arm/src/cxd56xx/cxd56_clock.c | 4 +-
arch/arm/src/cxd56xx/cxd56_cpuidlestack.c | 2 +-
arch/arm/src/cxd56xx/cxd56_cpustart.c | 2 +-
arch/arm/src/cxd56xx/cxd56_dmac.c | 12 +-
arch/arm/src/cxd56xx/cxd56_emmc.c | 11 +-
arch/arm/src/cxd56xx/cxd56_farapi.c | 14 +-
arch/arm/src/cxd56xx/cxd56_gauge.c | 9 +-
arch/arm/src/cxd56xx/cxd56_ge2d.c | 18 +--
arch/arm/src/cxd56xx/cxd56_geofence.c | 12 +-
arch/arm/src/cxd56xx/cxd56_gnss.c | 57 ++++----
arch/arm/src/cxd56xx/cxd56_i2c.c | 30 ++--
arch/arm/src/cxd56xx/cxd56_icc.c | 13 +-
arch/arm/src/cxd56xx/cxd56_idle.c | 4 +-
arch/arm/src/cxd56xx/cxd56_irq.c | 12 +-
arch/arm/src/cxd56xx/cxd56_powermgr.c | 38 ++---
arch/arm/src/cxd56xx/cxd56_rtc.c | 2 +-
arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c | 2 +-
arch/arm/src/cxd56xx/cxd56_scu.c | 32 ++---
arch/arm/src/cxd56xx/cxd56_sdhci.c | 72 ++++------
arch/arm/src/cxd56xx/cxd56_serial.c | 9 +-
arch/arm/src/cxd56xx/cxd56_sph.c | 10 +-
arch/arm/src/cxd56xx/cxd56_spi.c | 35 ++---
arch/arm/src/cxd56xx/cxd56_sysctl.c | 13 +-
arch/arm/src/cxd56xx/cxd56_timer.c | 4 +-
arch/arm/src/cxd56xx/cxd56_timerisr.c | 2 +-
arch/arm/src/cxd56xx/cxd56_uart0.c | 12 +-
arch/arm/src/cxd56xx/cxd56_udmac.c | 24 +---
arch/arm/src/cxd56xx/cxd56_usbdev.c | 4 +-
arch/arm/src/cxd56xx/cxd56_wdt.c | 4 +-
arch/arm/src/dm320/dm320_decodeirq.c | 2 +-
arch/arm/src/dm320/dm320_serial.c | 6 +-
arch/arm/src/dm320/dm320_usbdev.c | 6 +-
arch/arm/src/efm32/efm32_dma.c | 31 +---
arch/arm/src/efm32/efm32_i2c.c | 27 +---
arch/arm/src/efm32/efm32_idle.c | 4 +-
arch/arm/src/efm32/efm32_irq.c | 12 +-
arch/arm/src/efm32/efm32_leserial.c | 6 +-
arch/arm/src/efm32/efm32_pwm.c | 2 +-
arch/arm/src/efm32/efm32_serial.c | 12 +-
arch/arm/src/efm32/efm32_spi.c | 58 ++------
arch/arm/src/efm32/efm32_timerisr.c | 2 +-
arch/arm/src/efm32/efm32_usbdev.c | 22 +--
arch/arm/src/efm32/efm32_usbhost.c | 24 +---
arch/arm/src/imx1/imx_decodeirq.c | 2 +-
arch/arm/src/imx1/imx_serial.c | 8 +-
arch/arm/src/imx1/imx_spi.c | 31 ++--
arch/arm/src/imx6/imx_cpuboot.c | 2 +-
arch/arm/src/imx6/imx_ecspi.c | 31 ++--
arch/arm/src/imx6/imx_irq.c | 2 +-
arch/arm/src/imx6/imx_lowputc.c | 42 +++---
arch/arm/src/imx6/imx_serial.c | 14 +-
arch/arm/src/imx6/imx_timerisr.c | 4 +-
arch/arm/src/imxrt/imxrt_edma.c | 72 +++-------
arch/arm/src/imxrt/imxrt_ehci.c | 18 +--
arch/arm/src/imxrt/imxrt_enc.c | 16 +--
arch/arm/src/imxrt/imxrt_enet.c | 36 ++---
arch/arm/src/imxrt/imxrt_idle.c | 4 +-
arch/arm/src/imxrt/imxrt_irq.c | 12 +-
arch/arm/src/imxrt/imxrt_lowputc.c | 66 ++++-----
arch/arm/src/imxrt/imxrt_lpi2c.c | 31 ++--
arch/arm/src/imxrt/imxrt_lpspi.c | 41 ++----
arch/arm/src/imxrt/imxrt_serial.c | 18 +--
arch/arm/src/imxrt/imxrt_timerisr.c | 2 +-
arch/arm/src/imxrt/imxrt_usdhc.c | 64 ++++-----
arch/arm/src/kinetis/kinetis_enet.c | 30 ++--
arch/arm/src/kinetis/kinetis_i2c.c | 22 +--
arch/arm/src/kinetis/kinetis_irq.c | 12 +-
arch/arm/src/kinetis/kinetis_lpserial.c | 24 ++--
arch/arm/src/kinetis/kinetis_pinirq.c | 12 +-
arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c | 10 +-
arch/arm/src/kinetis/kinetis_sdhc.c | 22 +--
arch/arm/src/kinetis/kinetis_serial.c | 16 +--
arch/arm/src/kinetis/kinetis_spi.c | 17 +--
arch/arm/src/kinetis/kinetis_timerisr.c | 2 +-
arch/arm/src/kinetis/kinetis_usbdev.c | 20 +--
arch/arm/src/kl/kl_gpioirq.c | 6 +-
arch/arm/src/kl/kl_idle.c | 4 +-
arch/arm/src/kl/kl_irq.c | 6 +-
arch/arm/src/kl/kl_serial.c | 14 +-
arch/arm/src/kl/kl_spi.c | 17 +--
arch/arm/src/kl/kl_timerisr.c | 2 +-
arch/arm/src/lc823450/lc823450_adc.c | 34 +----
arch/arm/src/lc823450/lc823450_cpuidlestack.c | 2 +-
arch/arm/src/lc823450/lc823450_cpustart.c | 2 +-
arch/arm/src/lc823450/lc823450_i2c.c | 25 +---
arch/arm/src/lc823450/lc823450_i2s.c | 24 +---
arch/arm/src/lc823450/lc823450_ipl2.c | 12 +-
arch/arm/src/lc823450/lc823450_irq.c | 12 +-
arch/arm/src/lc823450/lc823450_mtd.c | 18 +--
arch/arm/src/lc823450/lc823450_procfs_dvfs.c | 2 +-
arch/arm/src/lc823450/lc823450_rtc.c | 14 +-
arch/arm/src/lc823450/lc823450_sdc.c | 22 +--
arch/arm/src/lc823450/lc823450_sddrv_dep.c | 18 +--
arch/arm/src/lc823450/lc823450_serial.c | 10 +-
arch/arm/src/lc823450/lc823450_spi.c | 21 +--
arch/arm/src/lc823450/lc823450_start.c | 2 +-
arch/arm/src/lc823450/lc823450_timer.c | 10 +-
arch/arm/src/lc823450/lc823450_usbdev.c | 4 +-
arch/arm/src/lc823450/lc823450_wdt.c | 6 +-
arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c | 6 +-
arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c | 2 +-
arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c | 6 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c | 36 ++---
arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c | 8 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c | 4 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c | 4 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c | 12 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c | 22 +--
arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c | 10 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c | 23 +--
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c | 23 +--
arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c | 2 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c | 14 +-
arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c | 20 +--
arch/arm/src/lpc214x/lpc214x_serial.c | 6 +-
arch/arm/src/lpc214x/lpc214x_timerisr.c | 2 +-
arch/arm/src/lpc214x/lpc214x_usbdev.c | 14 +-
arch/arm/src/lpc2378/lpc23xx_i2c.c | 4 +-
arch/arm/src/lpc2378/lpc23xx_serial.c | 6 +-
arch/arm/src/lpc2378/lpc23xx_spi.c | 23 +--
arch/arm/src/lpc2378/lpc23xx_timerisr.c | 2 +-
arch/arm/src/lpc31xx/lpc31_decodeirq.c | 2 +-
arch/arm/src/lpc31xx/lpc31_ehci.c | 18 +--
arch/arm/src/lpc31xx/lpc31_i2c.c | 2 +-
arch/arm/src/lpc31xx/lpc31_resetclks.c | 2 +-
arch/arm/src/lpc31xx/lpc31_serial.c | 4 +-
arch/arm/src/lpc31xx/lpc31_spi.c | 17 +--
arch/arm/src/lpc31xx/lpc31_timerisr.c | 2 +-
arch/arm/src/lpc43xx/lpc43_ehci.c | 18 +--
arch/arm/src/lpc43xx/lpc43_ethernet.c | 22 +--
arch/arm/src/lpc43xx/lpc43_gpdma.c | 8 +-
arch/arm/src/lpc43xx/lpc43_i2c.c | 4 +-
arch/arm/src/lpc43xx/lpc43_idle.c | 4 +-
arch/arm/src/lpc43xx/lpc43_irq.c | 12 +-
arch/arm/src/lpc43xx/lpc43_rtc.c | 2 +-
arch/arm/src/lpc43xx/lpc43_sdmmc.c | 23 +--
arch/arm/src/lpc43xx/lpc43_serial.c | 10 +-
arch/arm/src/lpc43xx/lpc43_spi.c | 23 +--
arch/arm/src/lpc43xx/lpc43_ssp.c | 21 +--
arch/arm/src/lpc43xx/lpc43_timer.c | 4 +-
arch/arm/src/lpc43xx/lpc43_timerisr.c | 2 +-
arch/arm/src/lpc43xx/lpc43_wwdt.c | 4 +-
arch/arm/src/lpc54xx/lpc54_ethernet.c | 20 +--
arch/arm/src/lpc54xx/lpc54_i2c_master.c | 8 +-
arch/arm/src/lpc54xx/lpc54_idle.c | 4 +-
arch/arm/src/lpc54xx/lpc54_irq.c | 12 +-
arch/arm/src/lpc54xx/lpc54_rng.c | 4 +-
arch/arm/src/lpc54xx/lpc54_rtc.c | 2 +-
arch/arm/src/lpc54xx/lpc54_sdmmc.c | 23 +--
arch/arm/src/lpc54xx/lpc54_serial.c | 22 +--
arch/arm/src/lpc54xx/lpc54_spi_master.c | 21 +--
arch/arm/src/lpc54xx/lpc54_timerisr.c | 2 +-
arch/arm/src/lpc54xx/lpc54_usb0_ohci.c | 20 +--
arch/arm/src/lpc54xx/lpc54_wwdt.c | 4 +-
arch/arm/src/max326xx/common/max326_idle.c | 4 +-
arch/arm/src/max326xx/common/max326_irq.c | 12 +-
.../arm/src/max326xx/common/max326_rtc_lowerhalf.c | 4 +-
arch/arm/src/max326xx/common/max326_timerisr.c | 2 +-
arch/arm/src/max326xx/max32660/max32660_rtc.c | 2 +-
arch/arm/src/max326xx/max32660/max32660_serial.c | 6 +-
arch/arm/src/max326xx/max32660/max32660_spim.c | 17 +--
arch/arm/src/max326xx/max32660/max32660_wdt.c | 2 +-
arch/arm/src/nrf52/nrf52_idle.c | 4 +-
arch/arm/src/nrf52/nrf52_irq.c | 12 +-
arch/arm/src/nrf52/nrf52_rng.c | 23 ++-
arch/arm/src/nrf52/nrf52_serial.c | 6 +-
arch/arm/src/nrf52/nrf52_timerisr.c | 2 +-
arch/arm/src/nuc1xx/nuc_idle.c | 4 +-
arch/arm/src/nuc1xx/nuc_irq.c | 6 +-
arch/arm/src/nuc1xx/nuc_serial.c | 32 ++---
arch/arm/src/nuc1xx/nuc_timerisr.c | 2 +-
arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c | 6 +-
arch/arm/src/s32k1xx/s32k11x/s32k11x_timerisr.c | 2 +-
arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c | 12 +-
arch/arm/src/s32k1xx/s32k14x/s32k14x_timerisr.c | 2 +-
arch/arm/src/s32k1xx/s32k1xx_edma.c | 72 +++-------
arch/arm/src/s32k1xx/s32k1xx_enet.c | 36 ++---
arch/arm/src/s32k1xx/s32k1xx_lowputc.c | 26 ++--
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c | 31 ++--
arch/arm/src/s32k1xx/s32k1xx_lpspi.c | 35 ++---
arch/arm/src/s32k1xx/s32k1xx_pinirq.c | 12 +-
arch/arm/src/s32k1xx/s32k1xx_serial.c | 8 +-
arch/arm/src/s32k1xx/s32k1xx_wdog.h | 2 +-
arch/arm/src/sam34/sam4cm_cpuidlestack.c | 2 +-
arch/arm/src/sam34/sam4cm_cpustart.c | 2 +-
arch/arm/src/sam34/sam4cm_freerun.c | 4 +-
arch/arm/src/sam34/sam4cm_oneshot.c | 6 +-
arch/arm/src/sam34/sam4cm_tc.c | 24 +---
arch/arm/src/sam34/sam_dmac.c | 44 ++----
arch/arm/src/sam34/sam_emac.c | 20 +--
arch/arm/src/sam34/sam_gpioirq.c | 24 ++--
arch/arm/src/sam34/sam_hsmci.c | 28 +---
arch/arm/src/sam34/sam_irq.c | 12 +-
arch/arm/src/sam34/sam_lowputc.c | 40 +++---
arch/arm/src/sam34/sam_rtc.c | 4 +-
arch/arm/src/sam34/sam_rtt.c | 4 +-
arch/arm/src/sam34/sam_serial.c | 14 +-
arch/arm/src/sam34/sam_spi.c | 37 ++---
arch/arm/src/sam34/sam_tc.c | 4 +-
arch/arm/src/sam34/sam_timerisr.c | 2 +-
arch/arm/src/sam34/sam_twi.c | 20 +--
arch/arm/src/sam34/sam_udp.c | 14 +-
arch/arm/src/sam34/sam_wdt.c | 4 +-
arch/arm/src/sama5/sam_adc.c | 15 +-
arch/arm/src/sama5/sam_can.c | 14 +-
arch/arm/src/sama5/sam_dbgu.c | 8 +-
arch/arm/src/sama5/sam_dmac.c | 46 ++----
arch/arm/src/sama5/sam_ehci.c | 18 +--
arch/arm/src/sama5/sam_emaca.c | 20 +--
arch/arm/src/sama5/sam_emacb.c | 20 +--
arch/arm/src/sama5/sam_flexcom_serial.c | 12 +-
arch/arm/src/sama5/sam_freerun.c | 4 +-
arch/arm/src/sama5/sam_gmac.c | 20 +--
arch/arm/src/sama5/sam_hsmci.c | 26 +---
arch/arm/src/sama5/sam_irq.c | 2 +-
arch/arm/src/sama5/sam_isi.c | 30 ++--
arch/arm/src/sama5/sam_lowputc.c | 100 ++++++-------
arch/arm/src/sama5/sam_nand.c | 38 ++---
arch/arm/src/sama5/sam_ohci.c | 20 +--
arch/arm/src/sama5/sam_oneshot.c | 6 +-
arch/arm/src/sama5/sam_pck.c | 6 +-
arch/arm/src/sama5/sam_pioirq.c | 24 ++--
arch/arm/src/sama5/sam_pmecc.c | 9 +-
arch/arm/src/sama5/sam_pwm.c | 16 +--
arch/arm/src/sama5/sam_rtc.c | 4 +-
arch/arm/src/sama5/sam_serial.c | 22 +--
arch/arm/src/sama5/sam_spi.c | 37 ++---
arch/arm/src/sama5/sam_ssc.c | 38 +----
arch/arm/src/sama5/sam_tc.c | 24 +---
arch/arm/src/sama5/sam_timerisr.c | 2 +-
arch/arm/src/sama5/sam_trng.c | 4 +-
arch/arm/src/sama5/sam_tsd.c | 13 +-
arch/arm/src/sama5/sam_twi.c | 26 +---
arch/arm/src/sama5/sam_udphs.c | 20 +--
arch/arm/src/sama5/sam_wdt.c | 6 +-
arch/arm/src/sama5/sam_xdmac.c | 46 ++----
arch/arm/src/sama5/sama5d2x_pio.c | 2 +-
arch/arm/src/sama5/sama5d3x4x_pio.c | 2 +-
arch/arm/src/samd2l2/sam_dmac.c | 38 +----
arch/arm/src/samd2l2/sam_i2c_master.c | 22 +--
arch/arm/src/samd2l2/sam_idle.c | 4 +-
arch/arm/src/samd2l2/sam_irq.c | 6 +-
arch/arm/src/samd2l2/sam_serial.c | 16 +--
arch/arm/src/samd2l2/sam_spi.c | 28 +---
arch/arm/src/samd2l2/sam_timerisr.c | 2 +-
arch/arm/src/samd2l2/sam_usb.c | 15 +-
arch/arm/src/samd5e5/sam_dmac.c | 46 ++----
arch/arm/src/samd5e5/sam_i2c_master.c | 22 +--
arch/arm/src/samd5e5/sam_idle.c | 4 +-
arch/arm/src/samd5e5/sam_irq.c | 12 +-
arch/arm/src/samd5e5/sam_serial.c | 18 +--
arch/arm/src/samd5e5/sam_spi.c | 28 +---
arch/arm/src/samd5e5/sam_timerisr.c | 2 +-
arch/arm/src/samd5e5/sam_usb.c | 15 +-
arch/arm/src/samv7/sam_emac.c | 24 ++--
arch/arm/src/samv7/sam_freerun.c | 4 +-
arch/arm/src/samv7/sam_gpioirq.c | 20 +--
arch/arm/src/samv7/sam_hsmci.c | 26 +---
arch/arm/src/samv7/sam_irq.c | 12 +-
arch/arm/src/samv7/sam_lowputc.c | 44 +++---
arch/arm/src/samv7/sam_mcan.c | 27 +---
arch/arm/src/samv7/sam_oneshot.c | 6 +-
arch/arm/src/samv7/sam_pck.c | 14 +-
arch/arm/src/samv7/sam_progmem.c | 20 +--
arch/arm/src/samv7/sam_qspi.c | 39 ++---
arch/arm/src/samv7/sam_rswdt.c | 6 +-
arch/arm/src/samv7/sam_serial.c | 18 +--
arch/arm/src/samv7/sam_spi.c | 37 ++---
arch/arm/src/samv7/sam_spi_slave.c | 18 +--
arch/arm/src/samv7/sam_ssc.c | 38 +----
arch/arm/src/samv7/sam_tc.c | 24 +---
arch/arm/src/samv7/sam_timerisr.c | 2 +-
arch/arm/src/samv7/sam_trng.c | 2 +-
arch/arm/src/samv7/sam_twihs.c | 28 +---
arch/arm/src/samv7/sam_usbdevhs.c | 22 +--
arch/arm/src/samv7/sam_wdt.c | 6 +-
arch/arm/src/samv7/sam_xdmac.c | 44 ++----
arch/arm/src/stm32/stm32_1wire.c | 24 +---
arch/arm/src/stm32/stm32_adc.c | 21 +--
arch/arm/src/stm32/stm32_aes.c | 2 -
arch/arm/src/stm32/stm32_bbsram.c | 16 +--
arch/arm/src/stm32/stm32_can.c | 6 +-
arch/arm/src/stm32/stm32_dma2d.c | 2 +-
arch/arm/src/stm32/stm32_dma_v1.c | 20 +--
arch/arm/src/stm32/stm32_dma_v2.c | 20 +--
arch/arm/src/stm32/stm32_eth.c | 24 ++--
arch/arm/src/stm32/stm32_hciuart.c | 10 +-
arch/arm/src/stm32/stm32_i2c.c | 23 +--
arch/arm/src/stm32/stm32_i2c_alt.c | 23 +--
arch/arm/src/stm32/stm32_i2c_v2.c | 23 +--
arch/arm/src/stm32/stm32_i2s.c | 36 +----
arch/arm/src/stm32/stm32_idle.c | 4 +-
arch/arm/src/stm32/stm32_irq.c | 12 +-
arch/arm/src/stm32/stm32_iwdg.c | 2 +-
arch/arm/src/stm32/stm32_ltdc.c | 2 +-
arch/arm/src/stm32/stm32_oneshot.c | 2 +-
arch/arm/src/stm32/stm32_otgfsdev.c | 22 +--
arch/arm/src/stm32/stm32_otgfshost.c | 24 +---
arch/arm/src/stm32/stm32_otghsdev.c | 22 +--
arch/arm/src/stm32/stm32_otghshost.c | 24 +---
arch/arm/src/stm32/stm32_pwm.c | 2 +-
arch/arm/src/stm32/stm32_qencoder.c | 2 +-
arch/arm/src/stm32/stm32_rng.c | 4 +-
arch/arm/src/stm32/stm32_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32/stm32_rtcc.c | 2 +-
arch/arm/src/stm32/stm32_sdio.c | 32 ++---
arch/arm/src/stm32/stm32_serial.c | 8 +-
arch/arm/src/stm32/stm32_spi.c | 57 +-------
arch/arm/src/stm32/stm32_tickless.c | 2 +-
arch/arm/src/stm32/stm32_timerisr.c | 2 +-
arch/arm/src/stm32/stm32_usbdev.c | 18 +--
arch/arm/src/stm32/stm32_wwdg.c | 4 +-
arch/arm/src/stm32/stm32f10xxf30xx_flash.c | 16 +--
arch/arm/src/stm32/stm32f20xxf40xx_flash.c | 16 +--
arch/arm/src/stm32/stm32f40xxx_i2c.c | 23 +--
arch/arm/src/stm32/stm32f40xxx_rtcc.c | 4 +-
arch/arm/src/stm32/stm32l15xx_flash.c | 16 +--
arch/arm/src/stm32/stm32l15xxx_rtcc.c | 6 +-
arch/arm/src/stm32f0l0g0/stm32_adc.c | 19 +--
arch/arm/src/stm32f0l0g0/stm32_aes.c | 2 -
arch/arm/src/stm32f0l0g0/stm32_dma_v1.c | 20 +--
arch/arm/src/stm32f0l0g0/stm32_i2c.c | 23 +--
arch/arm/src/stm32f0l0g0/stm32_irq.c | 6 +-
arch/arm/src/stm32f0l0g0/stm32_pwm.c | 2 +-
arch/arm/src/stm32f0l0g0/stm32_rng.c | 4 +-
arch/arm/src/stm32f0l0g0/stm32_serial_v1.c | 6 +-
arch/arm/src/stm32f0l0g0/stm32_serial_v2.c | 6 +-
arch/arm/src/stm32f0l0g0/stm32_spi.c | 45 ++----
arch/arm/src/stm32f0l0g0/stm32_timerisr.c | 2 +-
arch/arm/src/stm32f0l0g0/stm32_usbdev.c | 18 +--
arch/arm/src/stm32f7/stm32_bbsram.c | 16 +--
arch/arm/src/stm32f7/stm32_can.c | 6 +-
arch/arm/src/stm32f7/stm32_dma.c | 20 +--
arch/arm/src/stm32f7/stm32_dma2d.c | 2 +-
arch/arm/src/stm32f7/stm32_ethernet.c | 22 +--
arch/arm/src/stm32f7/stm32_flash.c | 18 +--
arch/arm/src/stm32f7/stm32_i2c.c | 23 +--
arch/arm/src/stm32f7/stm32_irq.c | 12 +-
arch/arm/src/stm32f7/stm32_ltdc.c | 2 +-
arch/arm/src/stm32f7/stm32_otgdev.c | 22 +--
arch/arm/src/stm32f7/stm32_otghost.c | 24 +---
arch/arm/src/stm32f7/stm32_pwm.c | 2 +-
arch/arm/src/stm32f7/stm32_qencoder.c | 2 +-
arch/arm/src/stm32f7/stm32_qspi.c | 46 ++----
arch/arm/src/stm32f7/stm32_rng.c | 4 +-
arch/arm/src/stm32f7/stm32_rtc.c | 12 +-
arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32f7/stm32_sdmmc.c | 32 ++---
arch/arm/src/stm32f7/stm32_serial.c | 6 +-
arch/arm/src/stm32f7/stm32_spi.c | 45 ++----
arch/arm/src/stm32f7/stm32_tickless.c | 2 +-
arch/arm/src/stm32f7/stm32_timerisr.c | 2 +-
arch/arm/src/stm32h7/stm32_bbsram.c | 16 +--
arch/arm/src/stm32h7/stm32_dma.c | 4 +-
arch/arm/src/stm32h7/stm32_ethernet.c | 26 ++--
arch/arm/src/stm32h7/stm32_flash.c | 18 +--
arch/arm/src/stm32h7/stm32_i2c.c | 23 +--
arch/arm/src/stm32h7/stm32_irq.c | 12 +-
arch/arm/src/stm32h7/stm32_otgdev.c | 22 +--
arch/arm/src/stm32h7/stm32_otghost.c | 24 +---
arch/arm/src/stm32h7/stm32_pwm.c | 2 +-
arch/arm/src/stm32h7/stm32_qencoder.c | 2 +-
arch/arm/src/stm32h7/stm32_rtc.c | 12 +-
arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32h7/stm32_sdmmc.c | 40 ++----
arch/arm/src/stm32h7/stm32_serial.c | 6 +-
arch/arm/src/stm32h7/stm32_spi.c | 51 +------
arch/arm/src/stm32h7/stm32_timerisr.c | 2 +-
arch/arm/src/stm32l4/stm32l4_1wire.c | 22 +--
arch/arm/src/stm32l4/stm32l4_can.c | 6 +-
arch/arm/src/stm32l4/stm32l4_flash.c | 16 +--
arch/arm/src/stm32l4/stm32l4_i2c.c | 23 +--
arch/arm/src/stm32l4/stm32l4_idle.c | 4 +-
arch/arm/src/stm32l4/stm32l4_irq.c | 12 +-
arch/arm/src/stm32l4/stm32l4_iwdg.c | 2 +-
arch/arm/src/stm32l4/stm32l4_lse.c | 2 +-
arch/arm/src/stm32l4/stm32l4_oneshot.c | 2 +-
arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 22 +--
arch/arm/src/stm32l4/stm32l4_otgfshost.c | 25 +---
arch/arm/src/stm32l4/stm32l4_pwm.c | 2 +-
arch/arm/src/stm32l4/stm32l4_qencoder.c | 2 +-
arch/arm/src/stm32l4/stm32l4_qspi.c | 46 ++----
arch/arm/src/stm32l4/stm32l4_rcc.c | 4 +-
arch/arm/src/stm32l4/stm32l4_rng.c | 4 +-
arch/arm/src/stm32l4/stm32l4_rtc.c | 28 ++--
arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c | 2 +-
arch/arm/src/stm32l4/stm32l4_sai.c | 32 +----
arch/arm/src/stm32l4/stm32l4_sdmmc.c | 32 ++---
arch/arm/src/stm32l4/stm32l4_serial.c | 12 +-
arch/arm/src/stm32l4/stm32l4_spi.c | 51 +------
arch/arm/src/stm32l4/stm32l4_timerisr.c | 2 +-
arch/arm/src/stm32l4/stm32l4_usbdev.c | 14 +-
arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 20 +--
arch/arm/src/stm32l4/stm32l4xrxx_dma.c | 4 +-
arch/arm/src/str71x/str71x_serial.c | 10 +-
arch/arm/src/str71x/str71x_timerisr.c | 2 +-
arch/arm/src/tiva/cc13xx/cc13x0_rom.c | 8 +-
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c | 12 +-
arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c | 14 +-
arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c | 2 +-
arch/arm/src/tiva/common/tiva_adclow.c | 26 +---
arch/arm/src/tiva/common/tiva_hciuart.c | 8 +-
arch/arm/src/tiva/common/tiva_i2c.c | 27 +---
arch/arm/src/tiva/common/tiva_irq.c | 12 +-
arch/arm/src/tiva/common/tiva_pwm.c | 4 +-
arch/arm/src/tiva/common/tiva_serial.c | 18 +--
arch/arm/src/tiva/common/tiva_ssi.c | 37 ++---
arch/arm/src/tiva/common/tiva_timerisr.c | 2 +-
arch/arm/src/tiva/common/tiva_timerlib.c | 8 +-
arch/arm/src/tiva/lm/lm3s_ethernet.c | 26 ++--
arch/arm/src/tiva/tm4c/tm4c_ethernet.c | 26 ++--
arch/arm/src/tms570/tms570_irq.c | 4 +-
arch/arm/src/tms570/tms570_serial.c | 6 +-
arch/arm/src/xmc4/xmc4_irq.c | 12 +-
arch/arm/src/xmc4/xmc4_lowputc.c | 24 ++--
arch/arm/src/xmc4/xmc4_serial.c | 14 +-
arch/arm/src/xmc4/xmc4_spi.c | 67 ++++-----
arch/arm/src/xmc4/xmc4_timerisr.c | 2 +-
arch/avr/src/at32uc3/at32uc3_irq.c | 2 +-
arch/avr/src/at32uc3/at32uc3_serial.c | 8 +-
arch/avr/src/at32uc3/at32uc3_timerisr.c | 2 +-
arch/avr/src/at90usb/at90usb_serial.c | 12 +-
arch/avr/src/at90usb/at90usb_timerisr.c | 2 +-
arch/avr/src/at90usb/at90usb_usbdev.c | 8 +-
arch/avr/src/atmega/atmega_serial.c | 22 +--
arch/avr/src/atmega/atmega_timerisr.c | 4 +-
arch/avr/src/avr/up_sigdeliver.c | 2 +-
arch/avr/src/avr/up_spi.c | 19 +--
arch/avr/src/avr32/up_blocktask.c | 2 +-
arch/avr/src/avr32/up_doirq.c | 2 +-
arch/avr/src/avr32/up_releasepending.c | 2 +-
arch/avr/src/avr32/up_reprioritizertr.c | 2 +-
arch/avr/src/avr32/up_sigdeliver.c | 2 +-
arch/avr/src/avr32/up_unblocktask.c | 2 +-
arch/avr/src/common/up_assert.c | 10 +-
arch/avr/src/common/up_exit.c | 6 +-
arch/avr/src/common/up_initialize.c | 8 +-
arch/hc/src/common/up_blocktask.c | 2 +-
arch/hc/src/common/up_doirq.c | 2 +-
arch/hc/src/common/up_exit.c | 6 +-
arch/hc/src/common/up_initialize.c | 8 +-
arch/hc/src/common/up_releasepending.c | 2 +-
arch/hc/src/common/up_reprioritizertr.c | 2 +-
arch/hc/src/common/up_unblocktask.c | 2 +-
arch/hc/src/m9s12/m9s12_assert.c | 10 +-
arch/hc/src/m9s12/m9s12_ethernet.c | 16 +--
arch/hc/src/m9s12/m9s12_serial.c | 6 +-
arch/hc/src/m9s12/m9s12_timerisr.c | 2 +-
arch/mips/include/mips32/syscall.h | 4 +-
arch/mips/src/common/up_exit.c | 6 +-
arch/mips/src/common/up_initialize.c | 8 +-
arch/mips/src/mips32/up_assert.c | 10 +-
arch/mips/src/mips32/up_blocktask.c | 2 +-
arch/mips/src/mips32/up_doirq.c | 2 +-
arch/mips/src/mips32/up_releasepending.c | 2 +-
arch/mips/src/mips32/up_reprioritizertr.c | 2 +-
arch/mips/src/mips32/up_sigdeliver.c | 2 +-
arch/mips/src/mips32/up_unblocktask.c | 2 +-
arch/mips/src/pic32mx/pic32mx-decodeirq.c | 2 +-
arch/mips/src/pic32mx/pic32mx-ethernet.c | 26 ++--
arch/mips/src/pic32mx/pic32mx-irq.c | 2 +-
arch/mips/src/pic32mx/pic32mx-serial.c | 6 +-
arch/mips/src/pic32mx/pic32mx-spi.c | 17 +--
arch/mips/src/pic32mx/pic32mx-timerisr.c | 4 +-
arch/mips/src/pic32mx/pic32mx-usbdev.c | 20 +--
arch/mips/src/pic32mz/pic32mz-decodeirq.c | 2 +-
arch/mips/src/pic32mz/pic32mz-dma.c | 20 +--
arch/mips/src/pic32mz/pic32mz-ethernet.c | 26 ++--
arch/mips/src/pic32mz/pic32mz-i2c.c | 23 +--
arch/mips/src/pic32mz/pic32mz-irq.c | 2 +-
arch/mips/src/pic32mz/pic32mz-oneshot.c | 2 +-
arch/mips/src/pic32mz/pic32mz-serial.c | 16 +--
arch/mips/src/pic32mz/pic32mz-spi.c | 17 +--
arch/mips/src/pic32mz/pic32mz-timerisr.c | 2 +-
arch/misoc/include/lm32/syscall.h | 4 +-
arch/misoc/include/minerva/syscall.h | 6 +-
arch/misoc/src/common/misoc_net.c | 28 ++--
arch/misoc/src/common/misoc_serial.c | 6 +-
arch/misoc/src/common/misoc_timerisr.c | 2 +-
arch/misoc/src/lm32/lm32_assert.c | 10 +-
arch/misoc/src/lm32/lm32_blocktask.c | 2 +-
arch/misoc/src/lm32/lm32_doirq.c | 2 +-
arch/misoc/src/lm32/lm32_exit.c | 6 +-
arch/misoc/src/lm32/lm32_irq.c | 2 +-
arch/misoc/src/lm32/lm32_releasepending.c | 2 +-
arch/misoc/src/lm32/lm32_reprioritizertr.c | 2 +-
arch/misoc/src/lm32/lm32_sigdeliver.c | 2 +-
arch/misoc/src/lm32/lm32_swint.c | 2 +-
arch/misoc/src/lm32/lm32_unblocktask.c | 2 +-
arch/misoc/src/minerva/minerva_assert.c | 10 +-
arch/misoc/src/minerva/minerva_blocktask.c | 2 +-
arch/misoc/src/minerva/minerva_doirq.c | 2 +-
arch/misoc/src/minerva/minerva_exit.c | 6 +-
arch/misoc/src/minerva/minerva_irq.c | 2 +-
arch/misoc/src/minerva/minerva_releasepending.c | 2 +-
arch/misoc/src/minerva/minerva_reprioritizertr.c | 2 +-
arch/misoc/src/minerva/minerva_sigdeliver.c | 2 +-
arch/misoc/src/minerva/minerva_swint.c | 2 +-
arch/misoc/src/minerva/minerva_unblocktask.c | 2 +-
arch/or1k/src/common/up_assert.c | 10 +-
arch/or1k/src/common/up_blocktask.c | 2 +-
arch/or1k/src/common/up_exit.c | 6 +-
arch/or1k/src/common/up_initialize.c | 8 +-
arch/or1k/src/common/up_releasepending.c | 2 +-
arch/or1k/src/common/up_reprioritizertr.c | 2 +-
arch/or1k/src/common/up_unblocktask.c | 2 +-
arch/or1k/src/mor1kx/mor1kx_serial.c | 2 +-
arch/renesas/src/common/up_assert.c | 10 +-
arch/renesas/src/common/up_blocktask.c | 2 +-
arch/renesas/src/common/up_doirq.c | 2 +-
arch/renesas/src/common/up_exit.c | 6 +-
arch/renesas/src/common/up_initialize.c | 8 +-
arch/renesas/src/common/up_releasepending.c | 2 +-
arch/renesas/src/common/up_reprioritizertr.c | 2 +-
arch/renesas/src/common/up_unblocktask.c | 2 +-
arch/renesas/src/m16c/m16c_serial.c | 14 +-
arch/renesas/src/m16c/m16c_sigdeliver.c | 2 +-
arch/renesas/src/rx65n/rx65n_eth.c | 10 +-
arch/renesas/src/rx65n/rx65n_serial.c | 36 ++---
arch/renesas/src/rx65n/rx65n_sigdeliver.c | 2 +-
arch/renesas/src/sh1/sh1_serial.c | 16 +--
arch/renesas/src/sh1/sh1_sigdeliver.c | 2 +-
arch/risc-v/include/rv32im/syscall.h | 4 +-
arch/risc-v/src/common/up_exit.c | 6 +-
arch/risc-v/src/common/up_initialize.c | 2 +-
arch/risc-v/src/gap8/gap8_uart.c | 4 +-
arch/risc-v/src/nr5m100/nr5_irq_dispatch.c | 2 +-
arch/risc-v/src/nr5m100/nr5_serial.c | 6 +-
arch/risc-v/src/nr5m100/nr5_timerisr.c | 2 +-
arch/risc-v/src/rv32im/up_assert.c | 10 +-
arch/risc-v/src/rv32im/up_blocktask.c | 2 +-
arch/risc-v/src/rv32im/up_doirq.c | 2 +-
arch/risc-v/src/rv32im/up_releasepending.c | 2 +-
arch/risc-v/src/rv32im/up_reprioritizertr.c | 2 +-
arch/risc-v/src/rv32im/up_sigdeliver.c | 2 +-
arch/risc-v/src/rv32im/up_unblocktask.c | 2 +-
arch/sim/src/sim/up_critmon.c | 2 +-
arch/sim/src/sim/up_devconsole.c | 2 +-
arch/sim/src/sim/up_deviceimage.c | 4 +-
arch/sim/src/sim/up_exit.c | 2 +-
arch/sim/src/sim/up_idle.c | 2 +-
arch/sim/src/sim/up_initialize.c | 8 +-
arch/sim/src/sim/up_ioexpander.c | 4 +-
arch/sim/src/sim/up_netdev.c | 2 +-
arch/sim/src/sim/up_netdriver.c | 6 +-
arch/sim/src/sim/up_simsmp.c | 10 +-
arch/sim/src/sim/up_simuart.c | 8 +-
arch/sim/src/sim/up_testset.c | 4 +-
arch/sim/src/sim/up_touchscreen.c | 30 +---
arch/sim/src/sim/up_wpcap.c | 2 +-
arch/sim/src/sim/up_x11framebuffer.c | 8 +-
arch/x86/src/common/up_assert.c | 10 +-
arch/x86/src/common/up_blocktask.c | 2 +-
arch/x86/src/common/up_exit.c | 6 +-
arch/x86/src/common/up_initialize.c | 8 +-
arch/x86/src/common/up_releasepending.c | 2 +-
arch/x86/src/common/up_reprioritizertr.c | 2 +-
arch/x86/src/common/up_unblocktask.c | 2 +-
arch/x86/src/i486/up_sigdeliver.c | 2 +-
arch/x86/src/qemu/qemu_handlers.c | 2 +-
arch/x86/src/qemu/qemu_keypad.c | 2 +-
arch/x86/src/qemu/qemu_timerisr.c | 2 +-
arch/x86/src/qemu/qemu_vga.c | 2 +-
arch/xtensa/src/common/xtensa_assert.c | 12 +-
arch/xtensa/src/common/xtensa_blocktask.c | 2 +-
arch/xtensa/src/common/xtensa_cpupause.c | 2 +-
arch/xtensa/src/common/xtensa_exit.c | 6 +-
arch/xtensa/src/common/xtensa_initialize.c | 8 +-
arch/xtensa/src/common/xtensa_irqdispatch.c | 2 +-
arch/xtensa/src/common/xtensa_releasepending.c | 2 +-
arch/xtensa/src/common/xtensa_reprioritizertr.c | 2 +-
arch/xtensa/src/common/xtensa_sigdeliver.c | 6 +-
arch/xtensa/src/common/xtensa_unblocktask.c | 2 +-
arch/xtensa/src/esp32/esp32_cpuint.c | 8 +-
arch/xtensa/src/esp32/esp32_cpustart.c | 4 +-
arch/xtensa/src/esp32/esp32_irq.c | 4 +-
arch/xtensa/src/esp32/esp32_serial.c | 8 +-
arch/xtensa/src/esp32/esp32_timerisr.c | 2 +-
arch/z16/src/common/up_assert.c | 10 +-
arch/z16/src/common/up_exit.c | 4 +-
arch/z16/src/common/up_initialize.c | 8 +-
arch/z16/src/common/up_sigdeliver.c | 2 +-
arch/z16/src/z16f/z16f_espi.c | 21 +--
arch/z16/src/z16f/z16f_serial.c | 12 +-
arch/z80/src/common/up_assert.c | 10 +-
arch/z80/src/common/up_blocktask.c | 2 +-
arch/z80/src/common/up_exit.c | 6 +-
arch/z80/src/common/up_initialize.c | 10 +-
arch/z80/src/common/up_releasepending.c | 2 +-
arch/z80/src/common/up_reprioritizertr.c | 2 +-
arch/z80/src/common/up_unblocktask.c | 2 +-
arch/z80/src/common/z80_doirq.c | 2 +-
arch/z80/src/ez80/ez80_emac.c | 24 ++--
arch/z80/src/ez80/ez80_i2c.c | 16 +--
arch/z80/src/ez80/ez80_rtc.c | 2 +-
arch/z80/src/ez80/ez80_rtc_lowerhalf.c | 2 +-
arch/z80/src/ez80/ez80_serial.c | 6 +-
arch/z80/src/ez80/ez80_sigdeliver.c | 2 +-
arch/z80/src/ez80/ez80_spi.c | 17 +--
arch/z80/src/ez80/ez80_timerisr.c | 8 +-
arch/z80/src/z180/z180_scc.c | 6 +-
arch/z80/src/z180/z180_sigdeliver.c | 2 +-
arch/z80/src/z180/z180_timerisr.c | 8 +-
arch/z80/src/z8/z8_i2c.c | 16 +--
arch/z80/src/z8/z8_serial.c | 12 +-
arch/z80/src/z8/z8_sigdeliver.c | 2 +-
arch/z80/src/z80/z80_sigdeliver.c | 2 +-
audio/audio.c | 12 +-
binfmt/binfmt_exec.c | 2 +-
binfmt/binfmt_execmodule.c | 2 +-
binfmt/builtin.c | 2 +-
binfmt/elf.c | 2 +-
binfmt/libelf/libelf_bind.c | 2 +-
binfmt/libelf/libelf_load.c | 2 +-
binfmt/libnxflat/libnxflat_addrenv.c | 2 +-
binfmt/libnxflat/libnxflat_bind.c | 2 +-
binfmt/libnxflat/libnxflat_load.c | 4 +-
binfmt/nxflat.c | 2 +-
boards/arm/a1x/pcduino-a10/src/a1x_buttons.c | 2 +-
.../am335x/beaglebone-black/src/am335x_buttons.c | 2 +-
boards/arm/cxd56xx/common/src/cxd56_crashdump.c | 2 +-
boards/arm/cxd56xx/common/src/cxd56_gs2200m.c | 12 +-
boards/arm/cxd56xx/common/src/cxd56_ili9340.c | 10 +-
boards/arm/cxd56xx/common/src/cxd56_imageproc.c | 43 +++---
boards/arm/cxd56xx/common/src/cxd56_lpm013m091a.c | 10 +-
boards/arm/cxd56xx/drivers/sensors/ak09912_scu.c | 6 +-
boards/arm/cxd56xx/drivers/sensors/apds9930_scu.c | 12 +-
boards/arm/cxd56xx/drivers/sensors/bh1721fvc_scu.c | 6 +-
boards/arm/cxd56xx/drivers/sensors/bh1745nuc_scu.c | 6 +-
boards/arm/cxd56xx/drivers/sensors/bm1383glv_scu.c | 6 +-
boards/arm/cxd56xx/drivers/sensors/bm1422gmv_scu.c | 6 +-
boards/arm/cxd56xx/drivers/sensors/bmi160_scu.c | 10 +-
boards/arm/cxd56xx/drivers/sensors/bmp280_scu.c | 8 +-
boards/arm/cxd56xx/drivers/sensors/kx022_scu.c | 6 +-
boards/arm/cxd56xx/drivers/sensors/lt1pa01_scu.c | 12 +-
boards/arm/cxd56xx/drivers/sensors/rpr0521rs_scu.c | 12 +-
boards/arm/cxd56xx/spresense/src/cxd56_power.c | 8 +-
.../olimex-efm32g880f128-stk/src/efm32_buttons.c | 6 +-
boards/arm/imx6/sabre-6quad/src/imx_boardinit.c | 2 +-
boards/arm/imxrt/imxrt1020-evk/src/imxrt_boot.c | 2 +-
.../arm/imxrt/imxrt1020-evk/src/imxrt_ethernet.c | 4 +-
boards/arm/imxrt/imxrt1020-evk/src/imxrt_gpio.c | 4 +-
boards/arm/imxrt/imxrt1020-evk/src/imxrt_spi.c | 6 +-
boards/arm/imxrt/imxrt1020-evk/src/imxrt_usbhost.c | 2 +-
boards/arm/imxrt/imxrt1050-evk/src/imxrt_boot.c | 2 +-
.../arm/imxrt/imxrt1050-evk/src/imxrt_ethernet.c | 4 +-
boards/arm/imxrt/imxrt1050-evk/src/imxrt_gpio.c | 4 +-
boards/arm/imxrt/imxrt1050-evk/src/imxrt_spi.c | 6 +-
boards/arm/imxrt/imxrt1060-evk/src/imxrt_boot.c | 2 +-
.../arm/imxrt/imxrt1060-evk/src/imxrt_ethernet.c | 4 +-
boards/arm/imxrt/imxrt1060-evk/src/imxrt_ft5x06.c | 2 +-
boards/arm/imxrt/imxrt1060-evk/src/imxrt_gpio.c | 4 +-
boards/arm/imxrt/imxrt1060-evk/src/imxrt_spi.c | 6 +-
boards/arm/kinetis/freedom-k28f/src/k28_boot.c | 2 +-
.../arm/kinetis/freedom-k64f/src/k64_automount.c | 4 +-
boards/arm/kinetis/freedom-k64f/src/k64_boot.c | 2 +-
boards/arm/kinetis/freedom-k64f/src/k64_sdhc.c | 2 +-
.../arm/kinetis/freedom-k66f/src/k66_automount.c | 4 +-
boards/arm/kinetis/freedom-k66f/src/k66_boot.c | 2 +-
boards/arm/kinetis/freedom-k66f/src/k66_sdhc.c | 2 +-
boards/arm/kinetis/kwikstik-k40/src/k40_appinit.c | 2 +-
boards/arm/kinetis/twr-k60n512/src/k60_appinit.c | 2 +-
.../arm/kinetis/twr-k64f120m/src/k64_automount.c | 4 +-
boards/arm/kinetis/twr-k64f120m/src/k64_sdhc.c | 2 +-
boards/arm/kl/freedom-kl25z/src/kl_adxl345.c | 6 +-
.../arm/kl/freedom-kl25z/src/kl_boardinitialize.c | 2 +-
boards/arm/kl/freedom-kl25z/src/kl_tsi.c | 2 +-
.../arm/kl/freedom-kl26z/src/kl_boardinitialize.c | 2 +-
boards/arm/kl/freedom-kl26z/src/kl_tsi.c | 2 +-
boards/arm/kl/teensy-lc/src/kl_boardinitialize.c | 2 +-
.../lc823450/lc823450-xgevk/src/lc823450_boot.c | 2 +-
.../lc823450/lc823450-xgevk/src/lc823450_bringup.c | 2 +-
.../lc823450/lc823450-xgevk/src/lc823450_st7565.c | 4 +-
.../lpc17xx_40xx/lincoln60/src/lpc17_40_buttons.c | 4 +-
.../lpc4088-devkit/src/lpc17_40_boardinitialize.c | 2 +-
.../lpc4088-devkit/src/lpc17_40_bringup.c | 2 +-
.../lpc4088-devkit/src/lpc17_40_buttons.c | 4 +-
.../lpc4088-devkit/src/lpc17_40_djoystick.c | 4 +-
.../lpc4088-devkit/src/lpc17_40_sdraminitialize.c | 4 +-
.../lpc4088-devkit/src/lpc17_40_touchscreen.c | 6 +-
.../src/lpc17_40_boardinitialize.c | 2 +-
.../lpc4088-quickstart/src/lpc17_40_bringup.c | 4 +-
.../lpc4088-quickstart/src/lpc17_40_buttons.c | 4 +-
.../src/lpc17_40_sdraminitialize.c | 4 +-
.../lpcxpresso-lpc1768/src/lpc17_40_oled.c | 10 +-
.../lpcxpresso-lpc1768/src/lpc17_40_ssp.c | 10 +-
.../lx_cpu/src/lpc17_40_boardinitialize.c | 2 +-
.../arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_bringup.c | 4 +-
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_nsh.c | 4 +-
.../arm/lpc17xx_40xx/mcb1700/src/lpc17_40_boot.c | 2 +-
.../lpc17xx_40xx/mcb1700/src/lpc17_40_bringup.c | 2 +-
.../olimex-lpc1766stk/src/lpc17_40_boot.c | 2 +-
.../olimex-lpc1766stk/src/lpc17_40_bringup.c | 2 +-
.../olimex-lpc1766stk/src/lpc17_40_buttons.c | 4 +-
.../olimex-lpc1766stk/src/lpc17_40_ssp.c | 4 +-
.../open1788/src/lpc17_40_boardinitialize.c | 2 +-
.../lpc17xx_40xx/open1788/src/lpc17_40_bringup.c | 4 +-
.../lpc17xx_40xx/open1788/src/lpc17_40_buttons.c | 4 +-
.../lpc17xx_40xx/open1788/src/lpc17_40_djoystick.c | 4 +-
.../open1788/src/lpc17_40_sdraminitialize.c | 4 +-
.../open1788/src/lpc17_40_touchscreen.c | 6 +-
.../arm/lpc17xx_40xx/pnev5180b/src/lpc17_40_boot.c | 2 +-
.../lpc17xx_40xx/u-blox-c027/src/lpc17_40_ssp.c | 8 +-
.../lpc17xx_40xx/u-blox-c027/src/lpc17_40_ubxmdm.c | 2 +-
.../zkit-arm-1769/src/lpc17_40_buttons.c | 2 +-
.../lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_lcd.c | 2 +-
.../lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_spi.c | 6 +-
.../lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_ssp.c | 4 +-
.../arm/lpc214x/mcu123-lpc214x/src/lpc2148_spi1.c | 23 +--
boards/arm/lpc214x/zp214xpa/src/lpc2148_spi1.c | 23 +--
.../lpc214x/zp214xpa/src/lpc2148_ug2864ambag01.c | 2 +-
boards/arm/lpc31xx/ea3131/src/lpc31_mem.c | 2 +-
boards/arm/lpc31xx/ea3131/src/lpc31_usbhost.c | 2 +-
boards/arm/lpc31xx/ea3152/src/lpc31_mem.c | 2 +-
.../arm/lpc31xx/olimex-lpc-h3131/src/lpc31_mem.c | 2 +-
.../lpc31xx/olimex-lpc-h3131/src/lpc31_usbhost.c | 2 +-
.../arm/lpc43xx/bambino-200e/src/lpc43_appinit.c | 2 +-
.../arm/lpc43xx/bambino-200e/src/lpc43_buttons.c | 4 +-
.../lpc43xx/lpc4330-xplorer/src/lpc43_buttons.c | 4 +-
boards/arm/lpc43xx/lpc4357-evb/src/lpc43_buttons.c | 4 +-
.../lpc54xx/lpcxpresso-lpc54628/src/lpc54_boot.c | 2 +-
.../lpcxpresso-lpc54628/src/lpc54_buttons.c | 4 +-
.../lpc54xx/lpcxpresso-lpc54628/src/lpc54_ft5x06.c | 2 +-
.../arm/max326xx/max32660-evsys/src/max326_boot.c | 2 +-
.../max326xx/max32660-evsys/src/max326_button.c | 6 +-
boards/arm/nrf52/nrf52-feather/src/nrf52_boot.c | 2 +-
boards/arm/s32k1xx/s32k118evb/src/s32k118_boot.c | 2 +-
boards/arm/s32k1xx/s32k146evb/src/s32k146_boot.c | 2 +-
boards/arm/s32k1xx/s32k148evb/src/s32k148_boot.c | 2 +-
boards/arm/sam34/arduino-due/src/sam_boot.c | 2 +-
boards/arm/sam34/arduino-due/src/sam_touchscreen.c | 2 +-
boards/arm/sam34/flipnclick-sam3x/src/sam_boot.c | 2 +-
.../arm/sam34/flipnclick-sam3x/src/sam_ssd1306.c | 2 +-
boards/arm/sam34/sam3u-ek/src/sam_buttons.c | 8 +-
boards/arm/sam34/sam3u-ek/src/sam_leds.c | 6 +-
boards/arm/sam34/sam3u-ek/src/sam_touchscreen.c | 4 +-
boards/arm/sam34/sam4cmp-db/src/sam_boot.c | 2 +-
boards/arm/sam34/sam4e-ek/src/sam_ads7843e.c | 4 +-
boards/arm/sam34/sam4e-ek/src/sam_boot.c | 6 +-
boards/arm/sam34/sam4e-ek/src/sam_buttons.c | 12 +-
boards/arm/sam34/sam4e-ek/src/sam_ethernet.c | 4 +-
boards/arm/sam34/sam4e-ek/src/sam_hsmci.c | 2 +-
boards/arm/sam34/sam4e-ek/src/sam_leds.c | 6 +-
boards/arm/sam34/sam4l-xplained/src/sam_autoleds.c | 2 +-
boards/arm/sam34/sam4l-xplained/src/sam_buttons.c | 6 +-
boards/arm/sam34/sam4l-xplained/src/sam_spi.c | 2 +-
.../sam34/sam4l-xplained/src/sam_ug2832hsweg04.c | 4 +-
boards/arm/sam34/sam4l-xplained/src/sam_userleds.c | 2 +-
.../arm/sam34/sam4s-xplained-pro/src/sam_buttons.c | 6 +-
.../arm/sam34/sam4s-xplained-pro/src/sam_hsmci.c | 2 +-
boards/arm/sam34/sam4s-xplained/src/sam_buttons.c | 6 +-
boards/arm/sama5/sama5d2-xult/src/sam_boot.c | 2 +-
boards/arm/sama5/sama5d2-xult/src/sam_buttons.c | 6 +-
.../arm/sama5/sama5d3-xplained/src/sam_ajoystick.c | 2 +-
boards/arm/sama5/sama5d3-xplained/src/sam_boot.c | 2 +-
.../arm/sama5/sama5d3-xplained/src/sam_buttons.c | 6 +-
.../arm/sama5/sama5d3-xplained/src/sam_ethernet.c | 4 +-
boards/arm/sama5/sama5d3-xplained/src/sam_hsmci.c | 2 +-
boards/arm/sama5/sama5d3-xplained/src/sam_usb.c | 4 +-
boards/arm/sama5/sama5d3x-ek/src/nor_main.c | 2 +-
boards/arm/sama5/sama5d3x-ek/src/sam_boot.c | 2 +-
boards/arm/sama5/sama5d3x-ek/src/sam_buttons.c | 6 +-
boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c | 4 +-
boards/arm/sama5/sama5d3x-ek/src/sam_hsmci.c | 2 +-
boards/arm/sama5/sama5d3x-ek/src/sam_usb.c | 4 +-
boards/arm/sama5/sama5d3x-ek/src/sam_wm8904.c | 8 +-
boards/arm/sama5/sama5d4-ek/src/dram_main.c | 2 +-
boards/arm/sama5/sama5d4-ek/src/sam_automount.c | 4 +-
boards/arm/sama5/sama5d4-ek/src/sam_boot.c | 2 +-
boards/arm/sama5/sama5d4-ek/src/sam_buttons.c | 6 +-
boards/arm/sama5/sama5d4-ek/src/sam_ethernet.c | 4 +-
boards/arm/sama5/sama5d4-ek/src/sam_hsmci.c | 2 +-
boards/arm/sama5/sama5d4-ek/src/sam_maxtouch.c | 4 +-
boards/arm/sama5/sama5d4-ek/src/sam_pmic.c | 6 +-
boards/arm/sama5/sama5d4-ek/src/sam_usb.c | 4 +-
boards/arm/sama5/sama5d4-ek/src/sam_wm8904.c | 8 +-
boards/arm/samd2l2/arduino-m0/src/sam_autoleds.c | 2 +-
boards/arm/samd2l2/arduino-m0/src/sam_userleds.c | 2 +-
.../arm/samd2l2/samd20-xplained/src/sam_autoleds.c | 2 +-
.../arm/samd2l2/samd20-xplained/src/sam_buttons.c | 4 +-
boards/arm/samd2l2/samd20-xplained/src/sam_spi.c | 4 +-
.../samd20-xplained/src/sam_ug2832hsweg04.c | 4 +-
.../arm/samd2l2/samd20-xplained/src/sam_userleds.c | 2 +-
.../arm/samd2l2/samd21-xplained/src/sam_autoleds.c | 2 +-
.../arm/samd2l2/samd21-xplained/src/sam_buttons.c | 4 +-
boards/arm/samd2l2/samd21-xplained/src/sam_spi.c | 4 +-
.../samd21-xplained/src/sam_ug2832hsweg04.c | 4 +-
.../arm/samd2l2/samd21-xplained/src/sam_userleds.c | 2 +-
.../arm/samd2l2/saml21-xplained/src/sam_autoleds.c | 2 +-
.../arm/samd2l2/saml21-xplained/src/sam_buttons.c | 4 +-
boards/arm/samd2l2/saml21-xplained/src/sam_spi.c | 4 +-
.../saml21-xplained/src/sam_ug2832hsweg04.c | 4 +-
.../arm/samd2l2/saml21-xplained/src/sam_userleds.c | 2 +-
boards/arm/samd5e5/metro-m4/src/sam_autoleds.c | 2 +-
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boards/arm/samd5e5/metro-m4/src/sam_userleds.c | 2 +-
.../arm/samv7/same70-xplained/src/sam_at24config.c | 4 +-
boards/arm/samv7/same70-xplained/src/sam_boot.c | 4 +-
boards/arm/samv7/same70-xplained/src/sam_buttons.c | 6 +-
.../arm/samv7/same70-xplained/src/sam_ethernet.c | 10 +-
boards/arm/samv7/same70-xplained/src/sam_hsmci.c | 2 +-
.../arm/samv7/same70-xplained/src/sam_mrf24j40.c | 4 +-
boards/arm/samv7/same70-xplained/src/sam_spi.c | 4 +-
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boards/arm/samv7/samv71-xult/src/sam_boot.c | 4 +-
boards/arm/samv7/samv71-xult/src/sam_buttons.c | 8 +-
boards/arm/samv7/samv71-xult/src/sam_ethernet.c | 10 +-
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boards/arm/samv7/samv71-xult/src/sam_ili9488.c | 8 +-
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boards/arm/samv7/samv71-xult/src/sam_mrf24j40.c | 4 +-
boards/arm/samv7/samv71-xult/src/sam_spi.c | 6 +-
boards/arm/samv7/samv71-xult/src/sam_wm8904.c | 8 +-
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boards/arm/stm32/axoloti/src/stm32_sdio.c | 4 +-
boards/arm/stm32/axoloti/src/stm32_usbhost.c | 2 +-
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.../arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c | 8 +-
boards/arm/stm32/clicker2-stm32/src/stm32_spi.c | 4 +-
boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c | 8 +-
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boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c | 2 +-
boards/arm/stm32/hymini-stm32v/src/stm32_ts.c | 6 +-
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boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c | 12 +-
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boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c | 8 +-
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boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c | 2 +-
boards/arm/stm32/nucleo-f303re/src/stm32_spi.c | 6 +-
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boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c | 2 +-
boards/arm/stm32/nucleo-f303ze/src/stm32_ssd1306.c | 2 +-
boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c | 2 +-
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.../arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c | 6 +-
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.../stm32/olimex-stm32-e407/src/stm32_mrf24j40.c | 8 +-
boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c | 18 +--
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boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c | 2 +-
.../stm32/olimex-stm32-p107/src/stm32_encx24j600.c | 8 +-
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boards/arm/stm32/omnibusf4/src/stm32_spi.c | 4 +-
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boards/arm/stm32/photon/src/stm32_rgbled.c | 2 +-
boards/arm/stm32/photon/src/stm32_wdt.c | 2 +-
boards/arm/stm32/shenzhou/src/stm32_touchscreen.c | 10 +-
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boards/arm/stm32/stm32_tiny/src/stm32_nrf24l01.c | 2 +-
boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c | 4 +-
.../arm/stm32/stm32butterfly2/src/stm32_usbhost.c | 1 -
.../stm32/stm32f103-minimum/src/stm32_apds9960.c | 2 +-
.../arm/stm32/stm32f103-minimum/src/stm32_boot.c | 2 +-
.../arm/stm32/stm32f103-minimum/src/stm32_gpio.c | 20 +--
.../arm/stm32/stm32f103-minimum/src/stm32_hcsr04.c | 10 +-
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.../arm/stm32/stm32f103-minimum/src/stm32_lm75.c | 4 +-
.../stm32/stm32f103-minimum/src/stm32_mcp2515.c | 6 +-
.../stm32/stm32f103-minimum/src/stm32_nrf24l01.c | 2 +-
.../stm32/stm32f103-minimum/src/stm32_pcd8544.c | 4 +-
boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c | 18 +--
.../stm32/stm32f103-minimum/src/stm32_ssd1306.c | 2 +-
.../stm32/stm32f103-minimum/src/stm32_zerocross.c | 6 +-
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boards/arm/stm32/stm32f3discovery/src/stm32_spi.c | 6 +-
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boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c | 2 +-
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.../stm32/stm32f429i-disco/src/stm32_ili93414ws.c | 20 +--
boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c | 12 +-
.../stm32/stm32f429i-disco/src/stm32_stmpe811.c | 10 +-
boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c | 2 +-
boards/arm/stm32/stm32f4discovery/src/stm32_boot.c | 2 +-
.../arm/stm32/stm32f4discovery/src/stm32_cs43l22.c | 2 +-
.../stm32/stm32f4discovery/src/stm32_ethernet.c | 8 +-
.../arm/stm32/stm32f4discovery/src/stm32_gs2200m.c | 8 +-
boards/arm/stm32/stm32f4discovery/src/stm32_idle.c | 4 +-
.../stm32/stm32f4discovery/src/stm32_pmbuttons.c | 2 +-
boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c | 4 +-
boards/arm/stm32/stm32f4discovery/src/stm32_spi.c | 22 +--
.../arm/stm32/stm32f4discovery/src/stm32_ssd1351.c | 4 +-
.../arm/stm32/stm32f4discovery/src/stm32_st7567.c | 4 +-
.../stm32f4discovery/src/stm32_ug2864ambag01.c | 4 +-
.../stm32f4discovery/src/stm32_ug2864hsweg01.c | 4 +-
boards/arm/stm32/stm32f4discovery/src/stm32_usb.c | 2 +-
.../arm/stm32/stm32f4discovery/src/stm32_xen1210.c | 12 +-
.../stm32/stm32f4discovery/src/stm32_zerocross.c | 6 +-
boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c | 2 +-
boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c | 6 +-
boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c | 2 +-
.../stm32/viewtool-stm32f107/src/stm32_ads7843e.c | 10 +-
.../arm/stm32/viewtool-stm32f107/src/stm32_boot.c | 2 +-
.../arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c | 12 +-
.../stm32/viewtool-stm32f107/src/stm32_max3421e.c | 14 +-
.../arm/stm32/viewtool-stm32f107/src/stm32_spi.c | 8 +-
.../stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c | 2 +-
.../stm32f0l0g0/b-l072z-lrwan1/src/stm32_ssd1306.c | 2 +-
.../stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c | 2 +-
.../arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c | 2 +-
.../arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c | 2 +-
.../stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c | 2 +-
.../arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c | 2 +-
.../arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c | 20 +--
.../arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c | 2 +-
.../arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c | 2 +-
.../stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c | 2 +-
.../arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c | 2 +-
.../stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c | 2 +-
.../stm32f051-discovery/src/stm32_boot.c | 2 +-
.../stm32f072-discovery/src/stm32_boot.c | 2 +-
.../stm32f7/nucleo-144/src/stm32_appinitialize.c | 2 +-
boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c | 4 +-
boards/arm/stm32f7/nucleo-144/src/stm32_boot.c | 2 +-
boards/arm/stm32f7/nucleo-144/src/stm32_gpio.c | 20 +--
boards/arm/stm32f7/nucleo-144/src/stm32_sdio.c | 4 +-
boards/arm/stm32f7/nucleo-144/src/stm32_usb.c | 2 +-
boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c | 2 +-
boards/arm/stm32f7/stm32f746-ws/src/stm32_sdmmc.c | 4 +-
boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c | 2 +-
.../arm/stm32f7/stm32f746g-disco/src/stm32_boot.c | 2 +-
.../stm32f7/stm32f746g-disco/src/stm32_bringup.c | 2 +-
.../stm32f746g-disco/src/stm32_touchscreen.c | 10 +-
.../arm/stm32f7/stm32f769i-disco/src/stm32_boot.c | 2 +-
.../stm32f7/stm32f769i-disco/src/stm32_bringup.c | 2 +-
boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c | 2 +-
.../arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c | 2 +-
boards/arm/stm32h7/nucleo-h743zi/src/stm32_gpio.c | 20 +--
.../arm/stm32h7/nucleo-h743zi/src/stm32_nrf24l01.c | 2 +-
.../arm/stm32h7/nucleo-h743zi/src/stm32_ssd1306.c | 2 +-
boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c | 2 +-
boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c | 2 +-
.../arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c | 8 +-
.../arm/stm32l4/nucleo-l432kc/src/stm32_appinit.c | 7 +-
.../arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c | 2 +-
boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c | 20 +--
.../arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c | 2 +-
.../arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c | 2 +-
boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c | 2 +-
.../stm32l4/nucleo-l432kc/src/stm32_zerocross.c | 6 +-
boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c | 2 +-
.../arm/stm32l4/nucleo-l452re/src/stm32_bringup.c | 4 +-
.../stm32l4/nucleo-l476rg/src/stm32_ajoystick.c | 6 +-
.../arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c | 7 +-
boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c | 20 +--
.../arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c | 4 +-
boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c | 4 +-
boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c | 2 +-
boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c | 4 +-
boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c | 2 +-
boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c | 2 +-
.../stm32l4/stm32l476vg-disco/src/stm32_appinit.c | 6 +-
.../stm32l4/stm32l476vg-disco/src/stm32_buttons.c | 2 +-
.../arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c | 4 +-
.../stm32l4/stm32l4r9ai-disco/src/stm32_appinit.c | 10 +-
.../stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c | 2 +-
.../arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c | 4 +-
boards/arm/str71x/olimex-strp711/src/str71_spi.c | 21 +--
boards/arm/tiva/dk-tm4c129x/src/tm4c_boot.c | 2 +-
boards/arm/tiva/dk-tm4c129x/src/tm4c_tmp100.c | 2 +-
.../arm/tiva/launchxl-cc1310/src/cc1310_autoleds.c | 4 +-
boards/arm/tiva/launchxl-cc1310/src/cc1310_boot.c | 2 +-
.../arm/tiva/launchxl-cc1310/src/cc1310_buttons.c | 4 +-
.../arm/tiva/launchxl-cc1310/src/cc1310_userleds.c | 4 +-
.../tiva/launchxl-cc1312r1/src/cc1312_autoleds.c | 4 +-
.../arm/tiva/launchxl-cc1312r1/src/cc1312_boot.c | 2 +-
.../tiva/launchxl-cc1312r1/src/cc1312_buttons.c | 4 +-
.../tiva/launchxl-cc1312r1/src/cc1312_userleds.c | 4 +-
boards/arm/tiva/lm3s6965-ek/src/lm_oled.c | 2 +-
boards/arm/tiva/lm3s8962-ek/src/lm_oled.c | 2 +-
boards/arm/tiva/tm4c123g-launchpad/src/tm4c_boot.c | 2 +-
.../arm/tiva/tm4c123g-launchpad/src/tm4c_buttons.c | 2 +-
.../arm/tiva/tm4c123g-launchpad/src/tm4c_mcp2515.c | 4 +-
boards/arm/tiva/tm4c123g-launchpad/src/tm4c_ssi.c | 2 +-
boards/arm/tiva/tm4c1294-launchpad/src/tm4c_boot.c | 2 +-
.../arm/tiva/tm4c1294-launchpad/src/tm4c_buttons.c | 2 +-
.../tms570/launchxl-tms57004/src/tms570_buttons.c | 6 +-
.../tms570ls31x-usb-kit/src/tms570_buttons.c | 6 +-
boards/arm/xmc4/xmc4500-relax/src/xmc4_autoleds.c | 4 +-
boards/arm/xmc4/xmc4500-relax/src/xmc4_boot.c | 2 +-
boards/arm/xmc4/xmc4500-relax/src/xmc4_spi.c | 2 +-
boards/arm/xmc4/xmc4500-relax/src/xmc4_userleds.c | 4 +-
boards/avr/at32uc3/avr32dev1/src/avr32_buttons.c | 4 +-
.../pic32mx-starterkit/src/pic32mx_appinit.c | 2 +-
boards/mips/pic32mx/pic32mx7mmb/src/pic32_boot.c | 2 +-
.../mips/pic32mx/pic32mx7mmb/src/pic32_bringup.c | 2 +-
.../pic32mx/pic32mx7mmb/src/pic32_touchscreen.c | 22 +--
.../pic32mx/sure-pic32mx/src/pic32mx_appinit.c | 2 +-
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include/nuttx/net/net.h | 38 +++++
include/nuttx/semaphore.h | 80 ++++++++++-
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libs/libc/wqueue/work_usrthread.c | 18 +--
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mm/iob/iob_alloc_qentry.c | 22 +--
mm/iob/iob_trimhead.c | 2 +-
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net/bluetooth/bluetooth_input.c | 2 +-
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net/bluetooth/bluetooth_sendto.c | 4 +-
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net/ipforward/ipv6_forward.c | 2 +-
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net/local/local_sendto.c | 2 +-
net/local/local_sockif.c | 2 +-
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net/netdev/netdev_txnotify.c | 6 +-
net/netlink/netlink_conn.c | 15 +-
net/pkt/pkt_conn.c | 15 +-
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net/route/net_router.c | 4 +-
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net/sixlowpan/sixlowpan_icmpv6send.c | 2 +-
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net/sixlowpan/sixlowpan_udpsend.c | 2 +-
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net/socket/connect.c | 2 +-
net/socket/net_clone.c | 2 +-
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net/usrsock/usrsock_connect.c | 2 -
net/usrsock/usrsock_dev.c | 38 ++---
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net/usrsock/usrsock_getsockname.c | 6 +-
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net/usrsock/usrsock_listen.c | 2 -
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net/usrsock/usrsock_sendto.c | 6 +-
net/usrsock/usrsock_setsockopt.c | 6 +-
net/usrsock/usrsock_socket.c | 6 +-
net/utils/net_lock.c | 150 ++++++++++++-------
sched/clock/clock_initialize.c | 4 +-
sched/clock/clock_settime.c | 2 +-
sched/clock/clock_systimer.c | 4 +-
sched/environ/env_setenv.c | 2 +-
sched/environ/env_unsetenv.c | 2 +-
sched/group/group_create.c | 6 +-
sched/group/group_leave.c | 4 +-
sched/group/group_setupidlefiles.c | 6 +-
sched/group/group_setupstreams.c | 6 +-
sched/group/group_setuptaskfiles.c | 4 +-
sched/init/nx_bringup.c | 10 +-
sched/init/nx_smpstart.c | 2 +-
sched/irq/irq_procfs.c | 2 +-
sched/irq/irq_unexpectedisr.c | 2 +-
sched/module/mod_insmod.c | 2 +-
sched/module/mod_rmmod.c | 2 +-
sched/mqueue/mq_receive.c | 2 +-
sched/mqueue/mq_release.c | 2 +-
sched/mqueue/mq_send.c | 2 +-
sched/mqueue/mq_setattr.c | 2 +-
sched/mqueue/mq_timedreceive.c | 6 +-
sched/mqueue/mq_timedsend.c | 6 +-
sched/paging/pg_miss.c | 4 +-
sched/paging/pg_worker.c | 12 +-
sched/pthread/pthread_cancel.c | 2 +-
sched/pthread/pthread_completejoin.c | 14 +-
sched/pthread/pthread_condtimedwait.c | 16 +--
sched/pthread/pthread_condwait.c | 2 +-
sched/pthread/pthread_create.c | 18 +--
sched/pthread/pthread_detach.c | 4 +-
sched/pthread/pthread_exit.c | 2 +-
sched/pthread/pthread_initialize.c | 63 +++-----
sched/pthread/pthread_join.c | 18 +--
sched/pthread/pthread_mutexinconsistent.c | 2 +-
sched/pthread/pthread_release.c | 6 +-
sched/sched/sched_addreadytorun.c | 4 +-
sched/sched/sched_lock.c | 6 +-
sched/sched/sched_processtimer.c | 2 +-
sched/sched/sched_releasetcb.c | 2 +-
sched/sched/sched_setparam.c | 4 +-
sched/sched/sched_setscheduler.c | 4 +-
sched/sched/sched_sporadic.c | 2 +-
sched/sched/sched_timerexpiration.c | 8 +-
sched/sched/sched_waitid.c | 8 +-
sched/sched/sched_waitpid.c | 14 +-
sched/semaphore/sem_holder.c | 28 ++--
sched/semaphore/sem_tickwait.c | 4 +-
sched/semaphore/sem_timedwait.c | 6 +-
sched/signal/sig_action.c | 2 +-
sched/signal/sig_default.c | 10 +-
sched/signal/sig_nanosleep.c | 10 +-
sched/signal/sig_pause.c | 4 +-
sched/signal/sig_suspend.c | 2 +-
sched/signal/sig_timedwait.c | 6 +-
sched/signal/sig_waitinfo.c | 2 +-
sched/task/task_create.c | 2 +-
sched/task/task_exit.c | 4 +-
sched/task/task_exithook.c | 8 +-
sched/task/task_init.c | 2 +-
sched/task/task_posixspawn.c | 2 +-
sched/task/task_restart.c | 4 +-
sched/task/task_setup.c | 8 +-
sched/task/task_spawn.c | 2 +-
sched/task/task_spawnparms.c | 15 +-
sched/task/task_testcancel.c | 2 +-
sched/task/task_vfork.c | 2 +-
sched/timer/timer_gettime.c | 4 +-
sched/timer/timer_release.c | 2 +-
sched/timer/timer_settime.c | 12 +-
sched/wdog/wd_cancel.c | 4 +-
sched/wdog/wd_recover.c | 4 +-
sched/wdog/wd_start.c | 2 +-
sched/wqueue/kwork_inherit.c | 8 +-
sched/wqueue/kwork_notifier.c | 18 +--
sched/wqueue/kwork_process.c | 2 +-
tools/configure.c | 2 +-
tools/convert-comments.c | 12 +-
tools/gencromfs.c | 8 +-
tools/initialconfig.c | 4 +-
tools/kconfig2html.c | 14 +-
tools/lowhex.c | 2 +-
tools/mksyscall.c | 2 +-
tools/rmcr.c | 2 +-
wireless/bluetooth/bt_conn.c | 24 +---
wireless/bluetooth/bt_hcicore.c | 18 +--
wireless/bluetooth/bt_ioctl.c | 11 +-
wireless/bluetooth/bt_netdev.c | 12 +-
wireless/ieee802154/mac802154.c | 4 +-
wireless/ieee802154/mac802154.h | 2 +-
wireless/ieee802154/mac802154_data.c | 4 +-
wireless/ieee802154/mac802154_device.c | 17 +--
wireless/ieee802154/mac802154_internal.h | 25 +---
wireless/ieee802154/mac802154_loopback.c | 14 +-
wireless/ieee802154/mac802154_netdev.c | 31 ++--
wireless/ieee802154/mac802154_scan.c | 2 -
wireless/pktradio/pktradio_loopback.c | 14 +-
wireless/pktradio/pktradio_metadata.c | 31 +---
1602 files changed, 6302 insertions(+), 10865 deletions(-)
diff --git a/arch/arm/src/a1x/a1x_irq.c b/arch/arm/src/a1x/a1x_irq.c
index 21c074d..800036d 100644
--- a/arch/arm/src/a1x/a1x_irq.c
+++ b/arch/arm/src/a1x/a1x_irq.c
@@ -156,7 +156,7 @@ void up_irqinitialize(void)
{
putreg32(0x00000000, A1X_INTC_EN(i)); /* 0 disables corresponding interrupt */
putreg32(0xffffffff, A1X_INTC_MASK(i)); /* 1 masks corresponding interrupt */
- (void)getreg32(A1X_INTC_IRQ_PEND(i)); /* Reading status clears pending interrupts */
+ getreg32(A1X_INTC_IRQ_PEND(i)); /* Reading status clears pending interrupts */
}
/* Set the interrupt base address to zero. We do not use the vectored
@@ -178,7 +178,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
- (void)up_irq_enable();
+ up_irq_enable();
#endif
a1x_dumpintc("initial", 0);
diff --git a/arch/arm/src/a1x/a1x_pio.c b/arch/arm/src/a1x/a1x_pio.c
index 5c5ba69..1f0585c 100644
--- a/arch/arm/src/a1x/a1x_pio.c
+++ b/arch/arm/src/a1x/a1x_pio.c
@@ -163,7 +163,7 @@ static int a1x_pio_interrupt(int irq, void *context)
{
/* Yes.. dispatch the interrupt */
- (void)arm_doirq(irq, regs);
+ arm_doirq(irq, regs);
}
irq++;
diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c
index a777866..3fc7455 100644
--- a/arch/arm/src/a1x/a1x_serial.c
+++ b/arch/arm/src/a1x/a1x_serial.c
@@ -1528,31 +1528,31 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#endif
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
- (void)uart_register("/dev/ttyS4", &TTYS4_DEV);
+ uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
#ifdef TTYS5_DEV
- (void)uart_register("/dev/ttyS5", &TTYS5_DEV);
+ uart_register("/dev/ttyS5", &TTYS5_DEV);
#endif
#ifdef TTYS6_DEV
- (void)uart_register("/dev/ttyS6", &TTYS6_DEV);
+ uart_register("/dev/ttyS6", &TTYS6_DEV);
#endif
#ifdef TTYS7_DEV
- (void)uart_register("/dev/ttyS7", &TTYS7_DEV);
+ uart_register("/dev/ttyS7", &TTYS7_DEV);
#endif
}
diff --git a/arch/arm/src/a1x/a1x_timerisr.c b/arch/arm/src/a1x/a1x_timerisr.c
index 071389e..0d62644 100644
--- a/arch/arm/src/a1x/a1x_timerisr.c
+++ b/arch/arm/src/a1x/a1x_timerisr.c
@@ -138,7 +138,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr, NULL);
+ irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr, NULL);
/* Enable interrupts from the TIMER 0 port */
diff --git a/arch/arm/src/am335x/am335x_gpioirq.c b/arch/arm/src/am335x/am335x_gpioirq.c
index 17f539f..b241c00 100644
--- a/arch/arm/src/am335x/am335x_gpioirq.c
+++ b/arch/arm/src/am335x/am335x_gpioirq.c
@@ -259,7 +259,7 @@ void am335x_gpio_irqinitialize(void)
/* Attach and enable the GPIO0 IRQ */
- (void)irq_attach(AM335X_IRQ_GPIO0A, am335x_gpio0_interrupt, NULL);
+ irq_attach(AM335X_IRQ_GPIO0A, am335x_gpio0_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO0A);
#endif
@@ -284,7 +284,7 @@ void am335x_gpio_irqinitialize(void)
/* Attach and enable the GPIO1 IRQ */
- (void)irq_attach(AM335X_IRQ_GPIO1A, am335x_gpio1_interrupt, NULL);
+ irq_attach(AM335X_IRQ_GPIO1A, am335x_gpio1_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO1A);
#endif
@@ -309,7 +309,7 @@ void am335x_gpio_irqinitialize(void)
/* Attach and enable the GPIO2 IRQ */
- (void)irq_attach(AM335X_IRQ_GPIO2A, am335x_gpio2_interrupt, NULL);
+ irq_attach(AM335X_IRQ_GPIO2A, am335x_gpio2_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO2A);
#endif
@@ -334,7 +334,7 @@ void am335x_gpio_irqinitialize(void)
/* Attach and enable the GPIO3 IRQ */
- (void)irq_attach(AM335X_IRQ_GPIO3A, am335x_gpio3_interrupt, NULL);
+ irq_attach(AM335X_IRQ_GPIO3A, am335x_gpio3_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO3A);
#endif
}
diff --git a/arch/arm/src/am335x/am335x_irq.c b/arch/arm/src/am335x/am335x_irq.c
index f80ba48..d6f20b8 100644
--- a/arch/arm/src/am335x/am335x_irq.c
+++ b/arch/arm/src/am335x/am335x_irq.c
@@ -131,8 +131,8 @@ void up_irqinitialize(void)
for (i = 0; i < AM335X_IRQ_NINT; i += 32)
{
putreg32(0xffffffff, AM335X_INTC_MIR_SET(i)); /* 1 masks corresponding interrupt */
- (void)getreg32(AM335X_INTC_PEND_IRQ(i)); /* Reading status clears pending interrupts */
- (void)getreg32(AM335X_INTC_PEND_FIQ(i)); /* Reading status clears pending interrupts */
+ getreg32(AM335X_INTC_PEND_IRQ(i)); /* Reading status clears pending interrupts */
+ getreg32(AM335X_INTC_PEND_FIQ(i)); /* Reading status clears pending interrupts */
}
/* currents_regs is non-NULL only while processing an interrupt */
@@ -150,7 +150,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
- (void)up_irq_enable();
+ up_irq_enable();
#endif
}
diff --git a/arch/arm/src/am335x/am335x_lcdc.c b/arch/arm/src/am335x/am335x_lcdc.c
index a6a60f8..b3cd35c 100644
--- a/arch/arm/src/am335x/am335x_lcdc.c
+++ b/arch/arm/src/am335x/am335x_lcdc.c
@@ -585,7 +585,7 @@ int am335x_lcd_initialize(FAR const struct am335x_panel_info_s *panel)
/* Initialize the device state singleton */
- sem_init(&priv->exclsem, 0, 1);
+ nxsem_init(&priv->exclsem, 0, 1);
memcpy(&priv->panel, panel, sizeof(struct am335x_panel_info_s));
/* Save framebuffer information */
diff --git a/arch/arm/src/am335x/am335x_serial.c b/arch/arm/src/am335x/am335x_serial.c
index 6cc3383..3260cb7 100644
--- a/arch/arm/src/am335x/am335x_serial.c
+++ b/arch/arm/src/am335x/am335x_serial.c
@@ -1347,25 +1347,25 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#endif
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
- (void)uart_register("/dev/ttyS4", &TTYS4_DEV);
+ uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
#ifdef TTYS5_DEV
- (void)uart_register("/dev/ttyS5", &TTYS5_DEV);
+ uart_register("/dev/ttyS5", &TTYS5_DEV);
#endif
}
diff --git a/arch/arm/src/am335x/am335x_timerisr.c b/arch/arm/src/am335x/am335x_timerisr.c
index 8db26df..7cddf0e 100644
--- a/arch/arm/src/am335x/am335x_timerisr.c
+++ b/arch/arm/src/am335x/am335x_timerisr.c
@@ -154,7 +154,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(AM335X_IRQ_TIMER1_1MS, (xcpt_t)am335x_timerisr, NULL);
+ irq_attach(AM335X_IRQ_TIMER1_1MS, (xcpt_t)am335x_timerisr, NULL);
/* Clear interrupt status */
@@ -193,7 +193,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(AM335X_IRQ_TIMER2, (xcpt_t)am335x_timerisr, NULL);
+ irq_attach(AM335X_IRQ_TIMER2, (xcpt_t)am335x_timerisr, NULL);
/* Enable overflow interrupt */
diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c
index 3dc165b..03d12f1 100644
--- a/arch/arm/src/arm/up_assert.c
+++ b/arch/arm/src/arm/up_assert.c
@@ -290,7 +290,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
- (void)usbtrace_enumerate(assert_tracecallback, NULL);
+ usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@@ -306,13 +306,13 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
- (void)syslog_flush();
+ syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || running_task()->flink == NULL)
{
- (void)up_irq_save();
+ up_irq_save();
for (; ; )
{
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@@ -353,7 +353,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
- (void)syslog_flush();
+ syslog_flush();
#if CONFIG_TASK_NAME_SIZE > 0
_alert("Assertion failed at file:%s line: %d task: %s\n",
@@ -367,7 +367,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
- (void)syslog_flush();
+ syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);
diff --git a/arch/arm/src/arm/up_blocktask.c b/arch/arm/src/arm/up_blocktask.c
index 3d0664a..e309c57 100644
--- a/arch/arm/src/arm/up_blocktask.c
+++ b/arch/arm/src/arm/up_blocktask.c
@@ -161,7 +161,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(rtcb);
+ group_addrenv(rtcb);
#endif
/* Reset scheduler parameters */
diff --git a/arch/arm/src/arm/up_doirq.c b/arch/arm/src/arm/up_doirq.c
index d13b04c..38512a3 100644
--- a/arch/arm/src/arm/up_doirq.c
+++ b/arch/arm/src/arm/up_doirq.c
@@ -119,7 +119,7 @@ void up_doirq(int irq, uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(NULL);
+ group_addrenv(NULL);
#endif
}
#endif
diff --git a/arch/arm/src/arm/up_releasepending.c b/arch/arm/src/arm/up_releasepending.c
index c0ee7e6..9b402a7 100644
--- a/arch/arm/src/arm/up_releasepending.c
+++ b/arch/arm/src/arm/up_releasepending.c
@@ -130,7 +130,7 @@ void up_release_pending(void)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(rtcb);
+ group_addrenv(rtcb);
#endif
/* Update scheduler parameters */
diff --git a/arch/arm/src/arm/up_reprioritizertr.c b/arch/arm/src/arm/up_reprioritizertr.c
index 693db73..1c577f0 100644
--- a/arch/arm/src/arm/up_reprioritizertr.c
+++ b/arch/arm/src/arm/up_reprioritizertr.c
@@ -183,7 +183,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(rtcb);
+ group_addrenv(rtcb);
#endif
/* Update scheduler parameters */
diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c
index 19419e1..8c3ecbb 100644
--- a/arch/arm/src/arm/up_sigdeliver.c
+++ b/arch/arm/src/arm/up_sigdeliver.c
@@ -107,7 +107,7 @@ void up_sigdeliver(void)
*/
sinfo("Resuming\n");
- (void)up_irq_save();
+ up_irq_save();
rtcb->pterrno = saved_errno;
/* Modify the saved return state with the actual saved values in the
diff --git a/arch/arm/src/arm/up_unblocktask.c b/arch/arm/src/arm/up_unblocktask.c
index 6203fc9..66b1b58 100644
--- a/arch/arm/src/arm/up_unblocktask.c
+++ b/arch/arm/src/arm/up_unblocktask.c
@@ -145,7 +145,7 @@ void up_unblock_task(struct tcb_s *tcb)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(rtcb);
+ group_addrenv(rtcb);
#endif
/* Update scheduler parameters */
diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c
index bbce7da..a335555 100644
--- a/arch/arm/src/armv6-m/up_assert.c
+++ b/arch/arm/src/armv6-m/up_assert.c
@@ -347,7 +347,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
- (void)usbtrace_enumerate(assert_tracecallback, NULL);
+ usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@@ -363,13 +363,13 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
- (void)syslog_flush();
+ syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || running_task()->flink == NULL)
{
- (void)up_irq_save();
+ up_irq_save();
for (; ; )
{
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@@ -410,7 +410,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
- (void)syslog_flush();
+ syslog_flush();
#if CONFIG_TASK_NAME_SIZE > 0
_alert("Assertion failed at file:%s line: %d task: %s\n",
@@ -424,7 +424,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
- (void)syslog_flush();
+ syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);
diff --git a/arch/arm/src/armv6-m/up_hardfault.c b/arch/arm/src/armv6-m/up_hardfault.c
index db092e9..ffe7e09 100644
--- a/arch/arm/src/armv6-m/up_hardfault.c
+++ b/arch/arm/src/armv6-m/up_hardfault.c
@@ -134,7 +134,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
getprimask(), getipsr());
#endif
- (void)up_irq_save();
+ up_irq_save();
hfalert("PANIC!!! Hard fault\n");
PANIC();
return OK; /* Won't get here */
diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c
index 834c163..0194f24 100644
--- a/arch/arm/src/armv6-m/up_sigdeliver.c
+++ b/arch/arm/src/armv6-m/up_sigdeliver.c
@@ -111,7 +111,7 @@ void up_sigdeliver(void)
*/
sinfo("Resuming\n");
- (void)up_irq_save();
+ up_irq_save();
rtcb->pterrno = saved_errno;
/* Modify the saved return state with the actual saved values in the
diff --git a/arch/arm/src/armv6-m/up_signal_dispatch.c b/arch/arm/src/armv6-m/up_signal_dispatch.c
index f69702f..e010875 100644
--- a/arch/arm/src/armv6-m/up_signal_dispatch.c
+++ b/arch/arm/src/armv6-m/up_signal_dispatch.c
@@ -84,8 +84,8 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
{
/* Let sys_call4() do all of the work */
- (void)sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
- (uintptr_t)info, (uintptr_t)ucontext);
+ sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
+ (uintptr_t)info, (uintptr_t)ucontext);
}
#endif /* (CONFIG_BUILD_PROTECTED || CONFIG_BUILD_KERNEL) && !CONFIG_DISABLE_PTHREAD */
diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c
index ef079dd..5f8f733 100644
--- a/arch/arm/src/armv7-a/arm_assert.c
+++ b/arch/arm/src/armv7-a/arm_assert.c
@@ -375,7 +375,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
- (void)usbtrace_enumerate(assert_tracecallback, NULL);
+ usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@@ -391,7 +391,7 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
- (void)syslog_flush();
+ syslog_flush();
/* Are we in an interrupt handler or the idle task? */
@@ -399,14 +399,14 @@ static void _up_assert(int errorcode)
{
/* Disable interrupts on this CPU */
- (void)up_irq_save();
+ up_irq_save();
for (; ; )
{
#ifdef CONFIG_SMP
/* Try (again) to stop activity on other CPUs */
- (void)spin_trylock(&g_cpu_irqlock);
+ spin_trylock(&g_cpu_irqlock);
#endif
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@@ -449,7 +449,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
- (void)syslog_flush();
+ syslog_flush();
#ifdef CONFIG_SMP
#if CONFIG_TASK_NAME_SIZE > 0
@@ -473,7 +473,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
- (void)syslog_flush();
+ syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);
diff --git a/arch/arm/src/armv7-a/arm_blocktask.c b/arch/arm/src/armv7-a/arm_blocktask.c
index 97d0ca2..ec0339a 100644
--- a/arch/arm/src/armv7-a/arm_blocktask.c
+++ b/arch/arm/src/armv7-a/arm_blocktask.c
@@ -182,7 +182,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(rtcb);
+ group_addrenv(rtcb);
#endif
/* Reset scheduler parameters */
diff --git a/arch/arm/src/armv7-a/arm_doirq.c b/arch/arm/src/armv7-a/arm_doirq.c
index 689e3fc..a5cd87d 100644
--- a/arch/arm/src/armv7-a/arm_doirq.c
+++ b/arch/arm/src/armv7-a/arm_doirq.c
@@ -118,7 +118,7 @@ static inline uint32_t *_arm_doirq(int irq, uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(NULL);
+ group_addrenv(NULL);
#endif
}
#endif
diff --git a/arch/arm/src/armv7-a/arm_pgalloc.c b/arch/arm/src/armv7-a/arm_pgalloc.c
index 8f94529..73de6eb 100644
--- a/arch/arm/src/armv7-a/arm_pgalloc.c
+++ b/arch/arm/src/armv7-a/arm_pgalloc.c
@@ -163,7 +163,7 @@ static int get_pgtable(FAR group_addrenv_t *addrenv, uintptr_t vaddr)
/* And instantiate the modified environment */
- (void)up_addrenv_select(addrenv, NULL);
+ up_addrenv_select(addrenv, NULL);
}
}
diff --git a/arch/arm/src/armv7-a/arm_releasepending.c b/arch/arm/src/armv7-a/arm_releasepending.c
index b4a811f..6a3638a 100644
--- a/arch/arm/src/armv7-a/arm_releasepending.c
+++ b/arch/arm/src/armv7-a/arm_releasepending.c
@@ -150,7 +150,7 @@ void up_release_pending(void)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(rtcb);
+ group_addrenv(rtcb);
#endif
/* Update scheduler parameters */
diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c
index 07582c0..2a2b837 100644
--- a/arch/arm/src/armv7-a/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c
@@ -204,7 +204,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(rtcb);
+ group_addrenv(rtcb);
#endif
/* Update scheduler parameters */
diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c
index 8ee5f4f..dff2f7f 100644
--- a/arch/arm/src/armv7-a/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-a/arm_sigdeliver.c
@@ -152,9 +152,9 @@ void up_sigdeliver(void)
*/
#ifdef CONFIG_SMP
- (void)enter_critical_section();
+ enter_critical_section();
#else
- (void)up_irq_save();
+ up_irq_save();
#endif
/* Restore the saved errno value */
@@ -187,7 +187,7 @@ void up_sigdeliver(void)
DEBUGASSERT(rtcb->irqcount == 1);
while (rtcb->irqcount < saved_irqcount)
{
- (void)enter_critical_section();
+ enter_critical_section();
}
#endif
diff --git a/arch/arm/src/armv7-a/arm_signal_dispatch.c b/arch/arm/src/armv7-a/arm_signal_dispatch.c
index ec1eb56..deff3c4 100644
--- a/arch/arm/src/armv7-a/arm_signal_dispatch.c
+++ b/arch/arm/src/armv7-a/arm_signal_dispatch.c
@@ -93,8 +93,8 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
{
/* Yes.. Let sys_call4() do all of the work to get us into user space */
- (void)sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
- (uintptr_t)info, (uintptr_t)ucontext);
+ sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
+ (uintptr_t)info, (uintptr_t)ucontext);
}
else
{
diff --git a/arch/arm/src/armv7-a/arm_unblocktask.c b/arch/arm/src/armv7-a/arm_unblocktask.c
index f932989..c2133aa 100644
--- a/arch/arm/src/armv7-a/arm_unblocktask.c
+++ b/arch/arm/src/armv7-a/arm_unblocktask.c
@@ -166,7 +166,7 @@ void up_unblock_task(struct tcb_s *tcb)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(rtcb);
+ group_addrenv(rtcb);
#endif
/* Update scheduler parameters */
diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c
index 573ea3b..ee2a96b 100644
--- a/arch/arm/src/armv7-m/up_assert.c
+++ b/arch/arm/src/armv7-m/up_assert.c
@@ -369,7 +369,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
- (void)usbtrace_enumerate(assert_tracecallback, NULL);
+ usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@@ -385,19 +385,19 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
- (void)syslog_flush();
+ syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || (running_task())->flink == NULL)
{
- (void)up_irq_save();
+ up_irq_save();
for (; ; )
{
#ifdef CONFIG_SMP
/* Try (again) to stop activity on other CPUs */
- (void)spin_trylock(&g_cpu_irqlock);
+ spin_trylock(&g_cpu_irqlock);
#endif
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@@ -438,7 +438,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
- (void)syslog_flush();
+ syslog_flush();
#ifdef CONFIG_SMP
#if CONFIG_TASK_NAME_SIZE > 0
@@ -462,7 +462,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
- (void)syslog_flush();
+ syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);
diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c
index e50f916..af6209f 100644
--- a/arch/arm/src/armv7-m/up_hardfault.c
+++ b/arch/arm/src/armv7-m/up_hardfault.c
@@ -143,7 +143,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
getreg32(NVIC_AFAULTS));
- (void)up_irq_save();
+ up_irq_save();
_alert("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
PANIC();
return OK;
diff --git a/arch/arm/src/armv7-m/up_itm_syslog.c b/arch/arm/src/armv7-m/up_itm_syslog.c
index dc1258b..6d81d19 100644
--- a/arch/arm/src/armv7-m/up_itm_syslog.c
+++ b/arch/arm/src/armv7-m/up_itm_syslog.c
@@ -186,7 +186,7 @@ void itm_syslog_initialize(void)
/* Setup the SYSLOG channel */
- (void)syslog_channel(&g_itm_channel);
+ syslog_channel(&g_itm_channel);
}
#endif /* CONFIG_ARMV7M_ITMSYSLOG */
diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c
index 702ebda..928922f 100644
--- a/arch/arm/src/armv7-m/up_memfault.c
+++ b/arch/arm/src/armv7-m/up_memfault.c
@@ -79,7 +79,7 @@ int up_memfault(int irq, FAR void *context, FAR void *arg)
{
/* Dump some memory management fault info */
- (void)up_irq_save();
+ up_irq_save();
_alert("PANIC!!! Memory Management Fault:\n");
mfinfo(" IRQ: %d context: %p\n", irq, context);
_alert(" CFAULTS: %08x MMFAR: %08x\n",
diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c
index 3ed0bbd..30c1c4c 100644
--- a/arch/arm/src/armv7-m/up_sigdeliver.c
+++ b/arch/arm/src/armv7-m/up_sigdeliver.c
@@ -156,9 +156,9 @@ void up_sigdeliver(void)
*/
#ifdef CONFIG_SMP
- (void)enter_critical_section();
+ enter_critical_section();
#else
- (void)up_irq_save();
+ up_irq_save();
#endif
/* Restore the saved errno value */
@@ -199,7 +199,7 @@ void up_sigdeliver(void)
DEBUGASSERT(rtcb->irqcount == 1);
while (rtcb->irqcount < saved_irqcount)
{
- (void)enter_critical_section();
+ enter_critical_section();
}
#endif
diff --git a/arch/arm/src/armv7-m/up_signal_dispatch.c b/arch/arm/src/armv7-m/up_signal_dispatch.c
index 54bc8e5..77f3303 100644
--- a/arch/arm/src/armv7-m/up_signal_dispatch.c
+++ b/arch/arm/src/armv7-m/up_signal_dispatch.c
@@ -84,8 +84,8 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
{
/* Let sys_call4() do all of the work */
- (void)sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
- (uintptr_t)info, (uintptr_t)ucontext);
+ sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
+ (uintptr_t)info, (uintptr_t)ucontext);
}
#endif /* (CONFIG_BUILD_PROTECTED || CONFIG_BUILD_KERNEL) && !CONFIG_DISABLE_PTHREAD */
diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c
index 843f362..7dbb045 100644
--- a/arch/arm/src/armv7-r/arm_assert.c
+++ b/arch/arm/src/armv7-r/arm_assert.c
@@ -354,7 +354,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
- (void)usbtrace_enumerate(assert_tracecallback, NULL);
+ usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@@ -370,13 +370,13 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
- (void)syslog_flush();
+ syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || (running_task())->flink == NULL)
{
- (void)up_irq_save();
+ up_irq_save();
for (; ; )
{
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@@ -417,7 +417,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
- (void)syslog_flush();
+ syslog_flush();
#if CONFIG_TASK_NAME_SIZE > 0
_alert("Assertion failed at file:%s line: %d task: %s\n",
@@ -431,7 +431,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
- (void)syslog_flush();
+ syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);
diff --git a/arch/arm/src/armv7-r/arm_sigdeliver.c b/arch/arm/src/armv7-r/arm_sigdeliver.c
index e6002fe..9b97901 100644
--- a/arch/arm/src/armv7-r/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-r/arm_sigdeliver.c
@@ -106,7 +106,7 @@ void up_sigdeliver(void)
*/
sinfo("Resuming\n");
- (void)up_irq_save();
+ up_irq_save();
rtcb->pterrno = saved_errno;
/* Modify the saved return state with the actual saved values in the
diff --git a/arch/arm/src/armv7-r/arm_signal_dispatch.c b/arch/arm/src/armv7-r/arm_signal_dispatch.c
index 2b4ed03..4f24c8a 100644
--- a/arch/arm/src/armv7-r/arm_signal_dispatch.c
+++ b/arch/arm/src/armv7-r/arm_signal_dispatch.c
@@ -93,8 +93,8 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
{
/* Yes.. Let sys_call4() do all of the work to get us into user space */
- (void)sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
- (uintptr_t)info, (uintptr_t)ucontext);
+ sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
+ (uintptr_t)info, (uintptr_t)ucontext);
}
else
{
diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c
index d7d6868..73ccaa6 100644
--- a/arch/arm/src/c5471/c5471_ethernet.c
+++ b/arch/arm/src/c5471/c5471_ethernet.c
@@ -989,8 +989,8 @@ static int c5471_transmit(struct c5471_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
- (void)wd_start(priv->c_txtimeout, C5471_TXTIMEOUT,
- c5471_txtimeout_expiry, 1, (wdparm_t)priv);
+ wd_start(priv->c_txtimeout, C5471_TXTIMEOUT,
+ c5471_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@@ -1539,7 +1539,7 @@ static void c5471_txdone(struct c5471_driver_s *priv)
/* Then poll the network for new XMIT data */
- (void)devif_poll(&priv->c_dev, c5471_txpoll);
+ devif_poll(&priv->c_dev, c5471_txpoll);
}
/****************************************************************************
@@ -1707,7 +1707,7 @@ static void c5471_txtimeout_work(FAR void *arg)
/* Then poll the network for new XMIT data */
- (void)devif_poll(&priv->c_dev, c5471_txpoll);
+ devif_poll(&priv->c_dev, c5471_txpoll);
net_unlock();
}
@@ -1778,13 +1778,13 @@ static void c5471_poll_work(FAR void *arg)
{
/* If so, update TCP timing states and poll the network for new XMIT data */
- (void)devif_timer(&priv->c_dev, C5471_WDDELAY, c5471_txpoll);
+ devif_timer(&priv->c_dev, C5471_WDDELAY, c5471_txpoll);
}
/* Setup the watchdog poll timer again */
- (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1,
- (wdparm_t)priv);
+ wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1,
+ (wdparm_t)priv);
net_unlock();
}
@@ -1870,8 +1870,8 @@ static int c5471_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
- (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry,
- 1, (wdparm_t)priv);
+ wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry,
+ 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@@ -1969,7 +1969,7 @@ static void c5471_txavail_work(FAR void *arg)
{
/* If so, then poll the network for new XMIT data */
- (void)devif_poll(&priv->c_dev, c5471_txpoll);
+ devif_poll(&priv->c_dev, c5471_txpoll);
}
}
@@ -2458,7 +2458,7 @@ void up_netinitialize(void)
/* Register the device with the OS so that socket IOCTLs can be performed */
- (void)netdev_register(&g_c5471[0].c_dev, NET_LL_ETHERNET);
+ netdev_register(&g_c5471[0].c_dev, NET_LL_ETHERNET);
}
#endif /* CONFIG_NET */
diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c
index 76baa88..66ce7b7 100644
--- a/arch/arm/src/c5471/c5471_serial.c
+++ b/arch/arm/src/c5471/c5471_serial.c
@@ -823,9 +823,9 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
- (void)uart_register("/dev/console", &CONSOLE_DEV);
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
}
/****************************************************************************
diff --git a/arch/arm/src/common/up_exit.c b/arch/arm/src/common/up_exit.c
index a9d2888..0e7be57 100644
--- a/arch/arm/src/common/up_exit.c
+++ b/arch/arm/src/common/up_exit.c
@@ -148,7 +148,7 @@ void _exit(int status)
* The IRQ state will be restored when the next task is started.
*/
- (void)enter_critical_section();
+ enter_critical_section();
sinfo("TCB=%p exiting\n", tcb);
@@ -163,7 +163,7 @@ void _exit(int status)
/* Destroy the task at the head of the ready to run list. */
- (void)nxtask_exit();
+ nxtask_exit();
/* Now, perform the context switch to the new ready-to-run task at the
* head of the list.
@@ -178,7 +178,7 @@ void _exit(int status)
* the ready-to-run list.
*/
- (void)group_addrenv(tcb);
+ group_addrenv(tcb);
#endif
/* Reset scheduler parameters */
diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c
index 7d354d1..14a287a 100644
--- a/arch/arm/src/common/up_initialize.c
+++ b/arch/arm/src/common/up_initialize.c
@@ -221,7 +221,7 @@ void up_initialize(void)
#ifdef CONFIG_PSEUDOTERM_SUSV1
/* Register the master pseudo-terminal multiplexor device */
- (void)ptmx_register();
+ ptmx_register();
#endif
/* Early initialization of the system logging device. Some SYSLOG channel
@@ -250,19 +250,19 @@ void up_initialize(void)
#ifdef CONFIG_NETDEV_LOOPBACK
/* Initialize the local loopback device */
- (void)localhost_initialize();
+ localhost_initialize();
#endif
#ifdef CONFIG_NET_TUN
/* Initialize the TUN device */
- (void)tun_initialize();
+ tun_initialize();
#endif
#ifdef CONFIG_NETDEV_TELNET
/* Initialize the Telnet session factory */
- (void)telnet_initialize();
+ telnet_initialize();
#endif
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
diff --git a/arch/arm/src/common/up_lwl_console.c b/arch/arm/src/common/up_lwl_console.c
index a915a38..609f458 100644
--- a/arch/arm/src/common/up_lwl_console.c
+++ b/arch/arm/src/common/up_lwl_console.c
@@ -323,5 +323,5 @@ static ssize_t lwlconsole_write(struct file *filep, const char *buffer,
void lwlconsole_init(void)
{
g_d.upword = 0;
- (void)register_driver("/dev/console", &g_consoleops, 0666, NULL);
+ register_driver("/dev/console", &g_consoleops, 0666, NULL);
}
diff --git a/arch/arm/src/cxd56xx/cxd56_adc.c b/arch/arm/src/cxd56xx/cxd56_adc.c
index 85cff79..418a2a1 100644
--- a/arch/arm/src/cxd56xx/cxd56_adc.c
+++ b/arch/arm/src/cxd56xx/cxd56_adc.c
@@ -585,7 +585,7 @@ static int adc_stop(adc_ch_t ch, FAR struct seq_s *seq)
return OK;
}
- (void) seq_ioctl(seq, 0, SCUIOC_STOP, 0);
+ seq_ioctl(seq, 0, SCUIOC_STOP, 0);
if (ch <= CH3)
{
@@ -1006,11 +1006,7 @@ void cxd56_adc_getinterval(int adctype, uint32_t *interval, uint16_t *adjust)
int cxd56_adcinitialize(void)
{
- int ret;
-
- /* Avoid warnings when no ADC options enabled */
-
- (void) ret;
+ int ret = OK;
#if defined (CONFIG_CXD56_LPADC0) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc0", &g_adcops, 0666, &g_lpadc0priv);
@@ -1061,5 +1057,5 @@ int cxd56_adcinitialize(void)
}
#endif
- return OK;
+ return ret;
}
diff --git a/arch/arm/src/cxd56xx/cxd56_charger.c b/arch/arm/src/cxd56xx/cxd56_charger.c
index 3a53cef..6163411 100644
--- a/arch/arm/src/cxd56xx/cxd56_charger.c
+++ b/arch/arm/src/cxd56xx/cxd56_charger.c
@@ -477,7 +477,7 @@ static int charger_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
FAR struct charger_dev_s *priv = inode->i_private;
int ret = -ENOTTY;
- sem_wait(&priv->batsem);
+ nxsem_wait(&priv->batsem);
switch (cmd)
{
@@ -621,7 +621,7 @@ static int charger_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
break;
}
- sem_post(&priv->batsem);
+ nxsem_post(&priv->batsem);
return ret;
}
@@ -650,7 +650,7 @@ int cxd56_charger_initialize(FAR const char *devpath)
/* Initialize the CXD5247 device structure */
- sem_init(&priv->batsem, 0, 1);
+ nxsem_init(&priv->batsem, 0, 1);
/* Register battery driver */
@@ -680,8 +680,7 @@ int cxd56_charger_initialize(FAR const char *devpath)
int cxd56_charger_uninitialize(FAR const char *devpath)
{
- (void) unregister_driver(devpath);
-
+ unregister_driver(devpath);
return OK;
}
diff --git a/arch/arm/src/cxd56xx/cxd56_clock.c b/arch/arm/src/cxd56xx/cxd56_clock.c
index 796f6fc..b88f995 100644
--- a/arch/arm/src/cxd56xx/cxd56_clock.c
+++ b/arch/arm/src/cxd56xx/cxd56_clock.c
@@ -235,7 +235,7 @@ static void clock_semtake(sem_t *id)
{
if (!up_interrupt_context())
{
- sem_wait(id);
+ nxsem_wait(id);
}
}
@@ -243,7 +243,7 @@ static void clock_semgive(sem_t *id)
{
if (!up_interrupt_context())
{
- sem_post(id);
+ nxsem_post(id);
}
}
diff --git a/arch/arm/src/cxd56xx/cxd56_cpuidlestack.c b/arch/arm/src/cxd56xx/cxd56_cpuidlestack.c
index b081e56..2f8f751 100644
--- a/arch/arm/src/cxd56xx/cxd56_cpuidlestack.c
+++ b/arch/arm/src/cxd56xx/cxd56_cpuidlestack.c
@@ -98,7 +98,7 @@
int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
{
#if CONFIG_SMP_NCPUS > 1
- (void)up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
+ up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
#endif
return OK;
}
diff --git a/arch/arm/src/cxd56xx/cxd56_cpustart.c b/arch/arm/src/cxd56xx/cxd56_cpustart.c
index f1b48cf..ed27019 100644
--- a/arch/arm/src/cxd56xx/cxd56_cpustart.c
+++ b/arch/arm/src/cxd56xx/cxd56_cpustart.c
@@ -137,7 +137,7 @@ static void appdsp_boot(void)
/* Then transfer control to the IDLE task */
- (void)nx_idle_task(0, NULL);
+ nx_idle_task(0, NULL);
}
/****************************************************************************
diff --git a/arch/arm/src/cxd56xx/cxd56_dmac.c b/arch/arm/src/cxd56xx/cxd56_dmac.c
index 5f1126a..b40d35d 100644
--- a/arch/arm/src/cxd56xx/cxd56_dmac.c
+++ b/arch/arm/src/cxd56xx/cxd56_dmac.c
@@ -677,7 +677,7 @@ void weak_function up_dma_initialize(void)
g_dmach[i].chan = i;
}
- sem_init(&g_dmaexc, 0, 1);
+ nxsem_init(&g_dmaexc, 0, 1);
}
/****************************************************************************
@@ -711,7 +711,7 @@ DMA_HANDLE cxd56_dmachannel(int ch, ssize_t maxsize)
/* Get exclusive access to allocate channel */
- sem_wait(&g_dmaexc);
+ nxsem_wait(&g_dmaexc);
if (ch < 0 || ch >= NCHANNELS)
{
@@ -754,12 +754,12 @@ DMA_HANDLE cxd56_dmachannel(int ch, ssize_t maxsize)
dmach->inuse = true;
- sem_post(&g_dmaexc);
+ nxsem_post(&g_dmaexc);
return (DMA_HANDLE)dmach;
err:
- sem_post(&g_dmaexc);
+ nxsem_post(&g_dmaexc);
return NULL;
}
@@ -793,7 +793,7 @@ void cxd56_dmafree(DMA_HANDLE handle)
return;
}
- sem_wait(&g_dmaexc);
+ nxsem_wait(&g_dmaexc);
if (!dmach->inuse)
{
@@ -811,7 +811,7 @@ void cxd56_dmafree(DMA_HANDLE handle)
dmach->inuse = false;
err:
- sem_post(&g_dmaexc);
+ nxsem_post(&g_dmaexc);
}
/****************************************************************************
diff --git a/arch/arm/src/cxd56xx/cxd56_emmc.c b/arch/arm/src/cxd56xx/cxd56_emmc.c
index 22db979..494649c 100644
--- a/arch/arm/src/cxd56xx/cxd56_emmc.c
+++ b/arch/arm/src/cxd56xx/cxd56_emmc.c
@@ -132,15 +132,12 @@ struct cxd56_emmc_state_s g_emmcdev;
static void emmc_takesem(FAR sem_t *sem)
{
- while (sem_wait(sem) != 0)
- {
- ASSERT(errno == EINTR);
- }
+ nxsem_wait_uninterruptible(sem);
}
static void emmc_givesem(FAR sem_t *sem)
{
- sem_post(sem);
+ nxsem_post(sem);
}
static void emmc_cmdstarted(void)
@@ -908,8 +905,8 @@ int cxd56_emmcinitialize(void)
priv = &g_emmcdev;
memset(priv, 0, sizeof(struct cxd56_emmc_state_s));
- sem_init(&priv->excsem, 0, 1);
- sem_init(&g_waitsem, 0, 0);
+ nxsem_init(&priv->excsem, 0, 1);
+ nxsem_init(&g_waitsem, 0, 0);
ret = emmc_hwinitialize();
if (ret != OK)
diff --git a/arch/arm/src/cxd56xx/cxd56_farapi.c b/arch/arm/src/cxd56xx/cxd56_farapi.c
index db0cd8a..f9b2d34 100644
--- a/arch/arm/src/cxd56xx/cxd56_farapi.c
+++ b/arch/arm/src/cxd56xx/cxd56_farapi.c
@@ -139,11 +139,7 @@ static struct pm_cpu_wakelock_s g_wlock = {
static int farapi_semtake(sem_t *id)
{
- while (sem_wait(id) != 0)
- {
- ASSERT(errno == EINTR);
- }
- return OK;
+ return nxsem_wait_uninterruptible(id);
}
#ifdef CONFIG_CXD56_FARAPI_DEBUG
@@ -188,7 +184,7 @@ static int cxd56_farapidonehandler(int cpuid, int protoid,
/* Send event flag response */
cxd56_sendmsg(cpuid, CXD56_PROTO_FLG, 5, pdata & 0xff00, 0);
- sem_post(&g_farwait);
+ nxsem_post(&g_farwait);
}
return OK;
@@ -258,7 +254,7 @@ void farapi_main(int id, void *arg, struct modulelist_s *mlist)
dump_farapi_message(&msg);
err:
- sem_post(&g_farlock);
+ nxsem_post(&g_farlock);
}
void cxd56_farapiinitialize(void)
@@ -274,8 +270,8 @@ void cxd56_farapiinitialize(void)
# endif
}
#endif
- sem_init(&g_farlock, 0, 1);
- sem_init(&g_farwait, 0, 0);
+ nxsem_init(&g_farlock, 0, 1);
+ nxsem_init(&g_farwait, 0, 0);
cxd56_iccinit(CXD56_PROTO_MBX);
cxd56_iccinit(CXD56_PROTO_FLG);
diff --git a/arch/arm/src/cxd56xx/cxd56_gauge.c b/arch/arm/src/cxd56xx/cxd56_gauge.c
index 6ddda2b..91ba738 100644
--- a/arch/arm/src/cxd56xx/cxd56_gauge.c
+++ b/arch/arm/src/cxd56xx/cxd56_gauge.c
@@ -334,7 +334,7 @@ static int gauge_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
FAR struct bat_gauge_dev_s *priv = inode->i_private;
int ret = -ENOTTY;
- sem_wait(&priv->batsem);
+ nxsem_wait(&priv->batsem);
switch (cmd)
{
@@ -372,7 +372,7 @@ static int gauge_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
break;
}
- sem_post(&priv->batsem);
+ nxsem_post(&priv->batsem);
return ret;
}
@@ -402,7 +402,7 @@ int cxd56_gauge_initialize(FAR const char *devpath)
/* Initialize the CXD5247 device structure */
- sem_init(&priv->batsem, 0, 1);
+ nxsem_init(&priv->batsem, 0, 1);
/* Register battery driver */
@@ -432,8 +432,7 @@ int cxd56_gauge_initialize(FAR const char *devpath)
int cxd56_gauge_uninitialize(FAR const char *devpath)
{
- (void) unregister_driver(devpath);
-
+ unregister_driver(devpath);
return OK;
}
diff --git a/arch/arm/src/cxd56xx/cxd56_ge2d.c b/arch/arm/src/cxd56xx/cxd56_ge2d.c
index 86ae1cc..b5e6e7f 100644
--- a/arch/arm/src/cxd56xx/cxd56_ge2d.c
+++ b/arch/arm/src/cxd56xx/cxd56_ge2d.c
@@ -98,11 +98,7 @@ static sem_t g_lock;
static int ge2d_semtake(sem_t *id)
{
- while (sem_wait(id) != 0)
- {
- ASSERT(errno == EINTR);
- }
- return OK;
+ return nxsem_wait_uninterruptible(id);
}
/****************************************************************************
@@ -111,7 +107,7 @@ static int ge2d_semtake(sem_t *id)
static void ge2d_semgive(sem_t *id)
{
- sem_post(id);
+ nxsem_post(id);
}
/****************************************************************************
@@ -243,9 +239,9 @@ int cxd56_ge2dinitialize(FAR const char *devname)
{
int ret;
- sem_init(&g_lock, 0, 1);
- sem_init(&g_wait, 0, 0);
- sem_setprotocol(&g_wait, SEM_PRIO_NONE);
+ nxsem_init(&g_lock, 0, 1);
+ nxsem_init(&g_wait, 0, 0);
+ nxsem_setprotocol(&g_wait, SEM_PRIO_NONE);
ret = register_driver(devname, &g_ge2dfops, 0666, NULL);
if (ret != 0)
@@ -276,8 +272,8 @@ void cxd56_ge2duninitialize(FAR const char *devname)
cxd56_img_ge2d_clock_disable();
- sem_destroy(&g_lock);
- sem_destroy(&g_wait);
+ nxsem_destroy(&g_lock);
+ nxsem_destroy(&g_wait);
unregister_driver(devname);
}
diff --git a/arch/arm/src/cxd56xx/cxd56_geofence.c b/arch/arm/src/cxd56xx/cxd56_geofence.c
index 8454bf0..f41a107 100644
--- a/arch/arm/src/cxd56xx/cxd56_geofence.c
+++ b/arch/arm/src/cxd56xx/cxd56_geofence.c
@@ -445,7 +445,7 @@ static void cxd56_geofence_sighandler(uint32_t data, FAR void *userdata)
int i;
int ret;
- ret = sem_wait(&priv->devsem);
+ ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return;
@@ -458,11 +458,11 @@ static void cxd56_geofence_sighandler(uint32_t data, FAR void *userdata)
{
fds->revents |= POLLIN;
gnssinfo("Report events: %02x\n", fds->revents);
- sem_post(fds->sem);
+ nxsem_post(fds->sem);
}
}
- sem_post(&priv->devsem);
+ nxsem_post(&priv->devsem);
}
/****************************************************************************
@@ -624,7 +624,7 @@ static int cxd56_geofence_poll(FAR struct file *filep, FAR struct pollfd *fds,
inode = filep->f_inode;
priv = (FAR struct cxd56_geofence_dev_s *)inode->i_private;
- ret = sem_wait(&priv->devsem);
+ ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@@ -675,7 +675,7 @@ static int cxd56_geofence_poll(FAR struct file *filep, FAR struct pollfd *fds,
}
errout:
- sem_post(&priv->devsem);
+ nxsem_post(&priv->devsem);
return ret;
}
#endif
@@ -708,7 +708,7 @@ static int cxd56_geofence_register(FAR const char *devpath)
}
memset(priv, 0, sizeof(struct cxd56_geofence_dev_s));
- sem_init(&priv->devsem, 0, 1);
+ nxsem_init(&priv->devsem, 0, 1);
ret = cxd56_geofence_initialize(priv);
if (ret < 0)
diff --git a/arch/arm/src/cxd56xx/cxd56_gnss.c b/arch/arm/src/cxd56xx/cxd56_gnss.c
index dba45bc..c16aef7 100644
--- a/arch/arm/src/cxd56xx/cxd56_gnss.c
+++ b/arch/arm/src/cxd56xx/cxd56_gnss.c
@@ -1443,7 +1443,7 @@ static int cxd56_gnss_set_signal(FAR struct file *filep, unsigned long arg)
inode = filep->f_inode;
priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private;
- ret = sem_wait(&priv->devsem);
+ ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@@ -1491,7 +1491,7 @@ static int cxd56_gnss_set_signal(FAR struct file *filep, unsigned long arg)
_success:
_err:
- sem_post(&priv->devsem);
+ nxsem_post(&priv->devsem);
#endif /* if !defined(CONFIG_DISABLE_SIGNAL) && \
(CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) */
return ret;
@@ -1949,7 +1949,7 @@ static int cxd56_gnss_wait_notify(FAR sem_t *sem, time_t waitsec)
timeout.tv_sec += waitsec; /* <waitsec> seconds timeout for wait */
- return sem_timedwait(sem, &timeout);
+ return nxsem_timedwait(sem, &timeout);
}
/****************************************************************************
@@ -2110,7 +2110,7 @@ static void cxd56_gnss_common_signalhandler(uint32_t data, FAR void *userdata)
int i;
int ret;
- ret = sem_wait(&priv->devsem);
+ ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return;
@@ -2124,9 +2124,9 @@ static void cxd56_gnss_common_signalhandler(uint32_t data, FAR void *userdata)
#ifdef CONFIG_CAN_PASS_STRUCTS
union sigval value;
value.sival_ptr = &sig->info;
- (void)sigqueue(sig->pid, sig->info.signo, value);
+ sigqueue(sig->pid, sig->info.signo, value);
#else
- (void)sigqueue(sig->pid, sig->info.signo, &sig->info);
+ sigqueue(sig->pid, sig->info.signo, &sig->info);
#endif
issetmask = 1;
}
@@ -2137,7 +2137,7 @@ static void cxd56_gnss_common_signalhandler(uint32_t data, FAR void *userdata)
GD_SetNotifyMask(sigtype, FALSE);
}
- sem_post(&priv->devsem);
+ nxsem_post(&priv->devsem);
}
#endif /* if !defined(CONFIG_DISABLE_SIGNAL) && \
@@ -2192,7 +2192,7 @@ static void cxd56_gnss_default_sighandler(uint32_t data, FAR void *userdata)
*/
priv->notify_data = dtype;
- sem_post(&priv->syncsem);
+ nxsem_post(&priv->syncsem);
}
return;
@@ -2220,7 +2220,7 @@ static void cxd56_gnss_default_sighandler(uint32_t data, FAR void *userdata)
break;
}
- ret = sem_wait(&priv->devsem);
+ ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return;
@@ -2233,11 +2233,11 @@ static void cxd56_gnss_default_sighandler(uint32_t data, FAR void *userdata)
{
fds->revents |= POLLIN;
gnssinfo("Report events: %02x\n", fds->revents);
- sem_post(fds->sem);
+ nxsem_post(fds->sem);
}
}
- sem_post(&priv->devsem);
+ nxsem_post(&priv->devsem);
#if !defined(CONFIG_DISABLE_SIGNAL) && \
(CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0)
@@ -2267,7 +2267,7 @@ static void cxd56_gnss_cpufifoapi_signalhandler(uint32_t data,
FAR struct cxd56_gnss_dev_s *priv = (FAR struct cxd56_gnss_dev_s *)userdata;
priv->apiret = CXD56_CPU1_GET_DATA((int)data);
- sem_post(&priv->apiwait);
+ nxsem_post(&priv->apiwait);
return;
}
@@ -2302,15 +2302,14 @@ static int cxd56_gnss_cpufifo_api(FAR struct file *filep, unsigned int api,
type = CXD56_GNSS_CPUFIFOAPI_SET_DATA(api, data);
cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_CPUFIFOAPI, type);
- ret = sem_wait(&priv->apiwait);
+ ret = nxsem_wait(&priv->apiwait);
if (ret < 0)
{
- /* If sem_wait returns -EINTR, there is a possibility that the signal
+ /* If nxsem_wait returns -EINTR, there is a possibility that the signal
* for GNSS set with CXD56_GNSS_IOCTL_SIGNAL_SET is unmasked
* by SIG_UNMASK in the signal mask.
*/
- ret = -errno;
_warn("Cannot wait GNSS semaphore %d\n", ret);
goto _err;
}
@@ -2438,7 +2437,7 @@ static int cxd56_gnss_open(FAR struct file *filep)
inode = filep->f_inode;
priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private;
- ret = sem_wait(&priv->devsem);
+ ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@@ -2446,7 +2445,7 @@ static int cxd56_gnss_open(FAR struct file *filep)
if (priv->num_open == 0)
{
- ret = sem_init(&priv->syncsem, 0, 0);
+ ret = nxsem_init(&priv->syncsem, 0, 0);
if (ret < 0)
{
goto _err0;
@@ -2485,7 +2484,7 @@ static int cxd56_gnss_open(FAR struct file *filep)
goto _err2;
}
- sem_destroy(&priv->syncsem);
+ nxsem_destroy(&priv->syncsem);
}
priv->num_open++;
@@ -2497,10 +2496,10 @@ _err2:
#endif
PM_SleepCpu(CXD56_GNSS_GPS_CPUID, PM_SLEEP_MODE_COLD);
_err1:
- sem_destroy(&priv->syncsem);
+ nxsem_destroy(&priv->syncsem);
_err0:
_success:
- sem_post(&priv->devsem);
+ nxsem_post(&priv->devsem);
return ret;
}
@@ -2527,7 +2526,7 @@ static int cxd56_gnss_close(FAR struct file *filep)
inode = filep->f_inode;
priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private;
- ret = sem_wait(&priv->devsem);
+ ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@@ -2548,7 +2547,7 @@ static int cxd56_gnss_close(FAR struct file *filep)
}
errout:
- sem_post(&priv->devsem);
+ nxsem_post(&priv->devsem);
return ret;
}
@@ -2674,7 +2673,7 @@ static int cxd56_gnss_ioctl(FAR struct file *filep, int cmd,
return -EINVAL;
}
- ret = sem_wait(&priv->ioctllock);
+ ret = nxsem_wait(&priv->ioctllock);
if (ret < 0)
{
return ret;
@@ -2682,7 +2681,7 @@ static int cxd56_gnss_ioctl(FAR struct file *filep, int cmd,
ret = g_cmdlist[cmd](filep, arg);
- sem_post(&priv->ioctllock);
+ nxsem_post(&priv->ioctllock);
return ret;
}
@@ -2715,7 +2714,7 @@ static int cxd56_gnss_poll(FAR struct file *filep, FAR struct pollfd *fds,
inode = filep->f_inode;
priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private;
- ret = sem_wait(&priv->devsem);
+ ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@@ -2766,7 +2765,7 @@ static int cxd56_gnss_poll(FAR struct file *filep, FAR struct pollfd *fds,
}
errout:
- sem_post(&priv->devsem);
+ nxsem_post(&priv->devsem);
return ret;
}
#endif
@@ -2848,21 +2847,21 @@ static int cxd56_gnss_register(FAR const char *devpath)
memset(priv, 0, sizeof(struct cxd56_gnss_dev_s));
- ret = sem_init(&priv->devsem, 0, 1);
+ ret = nxsem_init(&priv->devsem, 0, 1);
if (ret < 0)
{
gnsserr("Failed to initialize gnss devsem!\n");
goto _err0;
}
- ret = sem_init(&priv->apiwait, 0, 0);
+ ret = nxsem_init(&priv->apiwait, 0, 0);
if (ret < 0)
{
gnsserr("Failed to initialize gnss apiwait!\n");
goto _err0;
}
- ret = sem_init(&priv->ioctllock, 0, 1);
+ ret = nxsem_init(&priv->ioctllock, 0, 1);
if (ret < 0)
{
gnsserr("Failed to initialize gnss ioctllock!\n");
diff --git a/arch/arm/src/cxd56xx/cxd56_i2c.c b/arch/arm/src/cxd56xx/cxd56_i2c.c
index 16e67b3..da4b05b 100644
--- a/arch/arm/src/cxd56xx/cxd56_i2c.c
+++ b/arch/arm/src/cxd56xx/cxd56_i2c.c
@@ -365,7 +365,7 @@ static void cxd56_i2c_timeout(int argc, uint32_t arg, ...)
irqstate_t flags = enter_critical_section();
priv->error = -ENODEV;
- sem_post(&priv->wait);
+ nxsem_post(&priv->wait);
leave_critical_section(flags);
}
@@ -465,14 +465,14 @@ static int cxd56_i2c_interrupt(int irq, FAR void *context, FAR void *arg)
if ((priv->error) || (state & INTR_TX_EMPTY) || (state & INTR_RX_FULL))
{
/* Failure of wd_cancel() means that the timer expired.
- * In this case, sem_post() has already been called.
- * Therefore, call sem_post() only when wd_cancel() succeeds.
+ * In this case, nxsem_post() has already been called.
+ * Therefore, call nxsem_post() only when wd_cancel() succeeds.
*/
ret = wd_cancel(priv->timeout);
if (ret == OK)
{
- sem_post(&priv->wait);
+ nxsem_post(&priv->wait);
}
}
@@ -535,7 +535,7 @@ static int cxd56_i2c_receive(struct cxd56_i2cdev_s *priv, int last)
i2c_reg_rmw(priv, CXD56_IC_INTR_MASK, INTR_RX_FULL, INTR_RX_FULL);
leave_critical_section(flags);
- sem_wait(&priv->wait);
+ nxsem_wait(&priv->wait);
if (priv->error != OK)
{
@@ -581,7 +581,7 @@ static int cxd56_i2c_send(struct cxd56_i2cdev_s *priv, int last)
i2c_reg_rmw(priv, CXD56_IC_INTR_MASK, INTR_TX_EMPTY, INTR_TX_EMPTY);
leave_critical_section(flags);
- sem_wait(&priv->wait);
+ nxsem_wait(&priv->wait);
return 0;
}
@@ -610,13 +610,13 @@ static int cxd56_i2c_transfer(FAR struct i2c_master_s *dev,
/* Get exclusive access to the I2C bus */
- sem_wait(&priv->mutex);
+ nxsem_wait(&priv->mutex);
/* Check wait semaphore value. If the value is not 0, the transfer can not
* be performed normally.
*/
- ret = sem_getvalue(&priv->wait, &semval);
+ ret = nxsem_getvalue(&priv->wait, &semval);
DEBUGASSERT(ret == OK && semval == 0);
/* Disable clock gating (clock enable) */
@@ -688,7 +688,7 @@ static int cxd56_i2c_transfer(FAR struct i2c_master_s *dev,
cxd56_i2c_clock_gate_enable(priv->port);
- sem_post(&priv->mutex);
+ nxsem_post(&priv->mutex);
return ret;
}
@@ -828,7 +828,7 @@ static int cxd56_i2c_transfer_scu(FAR struct i2c_master_s *dev,
/* Get exclusive access to the I2C bus */
- sem_wait(&priv->mutex);
+ nxsem_wait(&priv->mutex);
/* Apply frequency for request msgs */
@@ -865,7 +865,7 @@ static int cxd56_i2c_transfer_scu(FAR struct i2c_master_s *dev,
}
}
- sem_post(&priv->mutex);
+ nxsem_post(&priv->mutex);
return ret;
}
@@ -1028,8 +1028,8 @@ struct i2c_master_s *cxd56_i2cbus_initialize(int port)
cxd56_i2c_pincontrol(port, true);
- sem_init(&priv->mutex, 0, 1);
- sem_init(&priv->wait, 0, 0);
+ nxsem_init(&priv->mutex, 0, 1);
+ nxsem_init(&priv->wait, 0, 0);
priv->timeout = wd_create();
@@ -1096,8 +1096,8 @@ int cxd56_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
wd_delete(priv->timeout);
priv->timeout = NULL;
- sem_destroy(&priv->mutex);
- sem_destroy(&priv->wait);
+ nxsem_destroy(&priv->mutex);
+ nxsem_destroy(&priv->wait);
return OK;
}
diff --git a/arch/arm/src/cxd56xx/cxd56_icc.c b/arch/arm/src/cxd56xx/cxd56_icc.c
index ac1bf27..802297a 100644
--- a/arch/arm/src/cxd56xx/cxd56_icc.c
+++ b/arch/arm/src/cxd56xx/cxd56_icc.c
@@ -159,15 +159,12 @@ static struct iccdev_s *g_cpumsg[NCPUS];
static void icc_semtake(sem_t *semid)
{
- while (sem_wait(semid) != 0)
- {
- ASSERT(errno == EINTR);
- }
+ nxsem_wait_uninterruptible(semid);
}
static void icc_semgive(sem_t *semid)
{
- sem_post(semid);
+ nxsem_post(semid);
}
static FAR struct iccdev_s *icc_getprotocol(int protoid)
@@ -254,9 +251,9 @@ static int icc_irqhandler(int cpuid, uint32_t word[2])
# ifdef CONFIG_CAN_PASS_STRUCTS
union sigval value;
value.sival_ptr = priv->sigdata;
- (void)sigqueue(priv->pid, priv->signo, value);
+ sigqueue(priv->pid, priv->signo, value);
# else
- (void)sigqueue(priv->pid, priv->signo, priv->sigdata);
+ sigqueue(priv->pid, priv->signo, priv->sigdata);
# endif
}
#endif
@@ -362,7 +359,7 @@ static FAR struct iccdev_s *icc_devnew(void)
priv->rxtimeout = wd_create();
- sem_init(&priv->rxwait, 0, 0);
+ nxsem_init(&priv->rxwait, 0, 0);
/* Initialize receive queue and free list */
diff --git a/arch/arm/src/cxd56xx/cxd56_idle.c b/arch/arm/src/cxd56xx/cxd56_idle.c
index b0655d0..ec55a81 100644
--- a/arch/arm/src/cxd56xx/cxd56_idle.c
+++ b/arch/arm/src/cxd56xx/cxd56_idle.c
@@ -111,7 +111,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
- (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+ pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@@ -135,7 +135,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
- (void)cxd56_pmsleep();
+ cxd56_pmsleep();
break;
default:
diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c
index 111d455..7ffabb9 100644
--- a/arch/arm/src/cxd56xx/cxd56_irq.c
+++ b/arch/arm/src/cxd56xx/cxd56_irq.c
@@ -173,7 +173,7 @@ static void cxd56_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int cxd56_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -181,7 +181,7 @@ static int cxd56_nmi(int irq, FAR void *context, FAR void *arg)
static int cxd56_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
@@ -189,7 +189,7 @@ static int cxd56_busfault(int irq, FAR void *context, FAR void *arg)
static int cxd56_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
@@ -197,7 +197,7 @@ static int cxd56_usagefault(int irq, FAR void *context, FAR void *arg)
static int cxd56_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -205,7 +205,7 @@ static int cxd56_pendsv(int irq, FAR void *context, FAR void *arg)
static int cxd56_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -213,7 +213,7 @@ static int cxd56_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int cxd56_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/cxd56xx/cxd56_powermgr.c b/arch/arm/src/cxd56xx/cxd56_powermgr.c
index dace666..5e6f819 100644
--- a/arch/arm/src/cxd56xx/cxd56_powermgr.c
+++ b/arch/arm/src/cxd56xx/cxd56_powermgr.c
@@ -177,15 +177,7 @@ static struct pm_cpu_wakelock_s g_wlock =
static int cxd56_pm_semtake(FAR sem_t *id)
{
- while (sem_wait(id) != 0)
- {
- if (errno != EINTR)
- {
- pmerr("ERR:sem_wait\n");
- return errno;
- }
- }
- return OK;
+ return nxsem_wait_uninterruptible(id);
}
static int cxd56_pm_needcallback(uint32_t target,
@@ -315,7 +307,7 @@ static void cxd56_pm_clkchange(struct cxd56_pm_message_s *message)
cxd56_pmsendmsg(mid, ret);
- sem_post(&g_regcblock);
+ nxsem_post(&g_regcblock);
}
static void cxd56_pm_checkfreqlock(void)
@@ -463,7 +455,7 @@ FAR void *cxd56_pm_register_callback(uint32_t target,
entry = (struct pm_cbentry_s *)kmm_malloc(sizeof(struct pm_cbentry_s));
if (entry == NULL)
{
- sem_post(&g_regcblock);
+ nxsem_post(&g_regcblock);
return NULL;
}
@@ -471,7 +463,7 @@ FAR void *cxd56_pm_register_callback(uint32_t target,
entry->callback = callback;
dq_addlast((FAR dq_entry_t *)entry, &g_cbqueue);
- sem_post(&g_regcblock);
+ nxsem_post(&g_regcblock);
return (void *)entry;
}
@@ -483,7 +475,7 @@ void cxd56_pm_unregister_callback(FAR void *handle)
dq_rem((FAR dq_entry_t *)handle, &g_cbqueue);
kmm_free(handle);
- sem_post(&g_regcblock);
+ nxsem_post(&g_regcblock);
}
static int cxd56_pmmsghandler(int cpuid, int protoid, uint32_t pdata,
@@ -517,7 +509,7 @@ static int cxd56_pmmsghandler(int cpuid, int protoid, uint32_t pdata,
}
else if (msgid == MSGID_FREQLOCK)
{
- sem_post(&g_freqlockwait);
+ nxsem_post(&g_freqlockwait);
}
else
{
@@ -573,7 +565,7 @@ void up_pm_acquire_freqlock(struct pm_cpu_freqlock_s *lock)
lock->count++;
- sem_post(&g_freqlock);
+ nxsem_post(&g_freqlock);
up_pm_release_wakelock(&g_wlock);
}
@@ -614,7 +606,7 @@ void up_pm_release_freqlock(struct pm_cpu_freqlock_s *lock)
}
}
- sem_post(&g_freqlock);
+ nxsem_post(&g_freqlock);
up_pm_release_wakelock(&g_wlock);
}
@@ -651,7 +643,7 @@ int up_pm_get_freqlock_count(struct pm_cpu_freqlock_s *lock)
}
}
- sem_post(&g_freqlock);
+ nxsem_post(&g_freqlock);
return count;
}
@@ -795,22 +787,22 @@ int cxd56_pm_initialize(void)
sq_init(&g_freqlockqueue);
sq_init(&g_wakelockqueue);
- ret = sem_init(&g_regcblock, 0, 1);
+ ret = nxsem_init(&g_regcblock, 0, 1);
if (ret < 0)
{
- return -EPERM;
+ return ret;
}
- ret = sem_init(&g_freqlock, 0, 1);
+ ret = nxsem_init(&g_freqlock, 0, 1);
if (ret < 0)
{
- return -EPERM;
+ return ret;
}
- ret = sem_init(&g_freqlockwait, 0, 0);
+ ret = nxsem_init(&g_freqlockwait, 0, 0);
if (ret < 0)
{
- return -EPERM;
+ return ret;
}
attr.mq_maxmsg = 8;
diff --git a/arch/arm/src/cxd56xx/cxd56_rtc.c b/arch/arm/src/cxd56xx/cxd56_rtc.c
index 1f04215..3339d57 100644
--- a/arch/arm/src/cxd56xx/cxd56_rtc.c
+++ b/arch/arm/src/cxd56xx/cxd56_rtc.c
@@ -160,7 +160,7 @@ static void rtc_dumptime(FAR const struct timespec *tp, FAR const char *msg)
{
FAR struct tm tm;
- (void)gmtime_r(&tp->tv_sec, &tm);
+ gmtime_r(&tp->tv_sec, &tm);
rtcinfo("%s:\n", msg);
rtcinfo("RTC %u.%09u\n", tp->tv_sec, tp->tv_nsec);
diff --git a/arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c b/arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c
index 2cd73d7..11b783b 100644
--- a/arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c
+++ b/arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c
@@ -417,7 +417,7 @@ static int cxd56_setrelative(FAR struct rtc_lowerhalf_s *lower,
seconds = ts.tv_sec + (alarminfo->reltime + 1);
- (void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
+ gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
/* The set the alarm using this absolute time */
diff --git a/arch/arm/src/cxd56xx/cxd56_scu.c b/arch/arm/src/cxd56xx/cxd56_scu.c
index 6a1b60c..9c14a14 100644
--- a/arch/arm/src/cxd56xx/cxd56_scu.c
+++ b/arch/arm/src/cxd56xx/cxd56_scu.c
@@ -374,11 +374,7 @@ static const struct coeff_addr_s g_caddrs[3][2] =
static int seq_semtake(sem_t *id)
{
- while (sem_wait(id) != 0)
- {
- ASSERT(errno == EINTR);
- }
- return OK;
+ return nxsem_wait_uninterruptible(id);
}
/****************************************************************************
@@ -387,7 +383,7 @@ static int seq_semtake(sem_t *id)
static void seq_semgive(sem_t *id)
{
- sem_post(id);
+ nxsem_post(id);
}
/****************************************************************************
@@ -1514,9 +1510,9 @@ static void seq_handlefifointr(FAR struct cxd56_scudev_s *priv, uint32_t intr)
# ifdef CONFIG_CAN_PASS_STRUCTS
value.sival_ptr = notify->ts;
- (void)sigqueue(notify->pid, notify->signo, value);
+ sigqueue(notify->pid, notify->signo, value);
# else
- (void)sigqueue(notify->pid, notify->signo, (FAR void *)notify->ts);
+ sigqueue(notify->pid, notify->signo, (FAR void *)notify->ts);
# endif
#endif
}
@@ -1606,9 +1602,9 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv,
# ifdef CONFIG_CAN_PASS_STRUCTS
union sigval value;
value.sival_ptr = notify->arg;
- (void)sigqueue(notify->pid, notify->signo, value);
+ sigqueue(notify->pid, notify->signo, value);
# else
- (void)sigqueue(notify->pid, notify->signo, (FAR void *)notify->arg);
+ sigqueue(notify->pid, notify->signo, (FAR void *)notify->arg);
# endif
detected = 0;
}
@@ -1999,7 +1995,7 @@ static int seq_fifoinit(FAR struct seq_s *seq, int fifoid, uint16_t fsize)
/* Initialize DMA done wait semaphore */
- sem_init(&fifo->dmawait, 0, 0);
+ nxsem_init(&fifo->dmawait, 0, 0);
fifo->dmaresult = -1;
#endif
@@ -2085,7 +2081,7 @@ static void seq_fifofree(FAR struct scufifo_s *fifo)
scufifo_memfree(fifo->start);
#ifdef CONFIG_CXD56_UDMAC
- sem_destroy(&fifo->dmawait);
+ nxsem_destroy(&fifo->dmawait);
#endif
kmm_free(fifo);
@@ -3422,12 +3418,12 @@ void scu_initialize(void)
memset(priv, 0, sizeof(struct cxd56_scudev_s));
- sem_init(&priv->syncwait, 0, 0);
- sem_init(&priv->syncexc, 0, 1);
+ nxsem_init(&priv->syncwait, 0, 0);
+ nxsem_init(&priv->syncexc, 0, 1);
for (i = 0; i < 3; i++)
{
- sem_init(&priv->oneshotwait[i], 0, 0);
+ nxsem_init(&priv->oneshotwait[i], 0, 0);
}
scufifo_initialize();
@@ -3489,11 +3485,11 @@ void scu_uninitialize(void)
cxd56_scuseq_clock_disable();
- sem_destroy(&priv->syncwait);
- sem_destroy(&priv->syncexc);
+ nxsem_destroy(&priv->syncwait);
+ nxsem_destroy(&priv->syncexc);
for (i = 0; i < 3; i++)
{
- sem_destroy(&priv->oneshotwait[i]);
+ nxsem_destroy(&priv->oneshotwait[i]);
}
}
diff --git a/arch/arm/src/cxd56xx/cxd56_sdhci.c b/arch/arm/src/cxd56xx/cxd56_sdhci.c
index d991b96..d48fa63 100644
--- a/arch/arm/src/cxd56xx/cxd56_sdhci.c
+++ b/arch/arm/src/cxd56xx/cxd56_sdhci.c
@@ -356,7 +356,7 @@ struct cxd56_sdhcregs_s
/* Low-level helpers ********************************************************/
static void cxd56_takesem(struct cxd56_sdiodev_s *priv);
-#define cxd56_givesem(priv) (sem_post(&(priv)->waitsem))
+#define cxd56_givesem(priv) (nxsem_post(&(priv)->waitsem))
static void cxd56_configwaitints(struct cxd56_sdiodev_s *priv,
uint32_t waitints, sdio_eventset_t waitevents,
sdio_eventset_t wkupevents);
@@ -570,16 +570,7 @@ static FAR uint32_t cxd56_sdhci_adma_dscr[CXD56_SDIO_MAX_LEN_ADMA_DSCR * 2];
static void cxd56_takesem(struct cxd56_sdiodev_s *priv)
{
- /* Take the semaphore (perhaps waiting) */
-
- while (sem_wait(&priv->waitsem) != 0)
- {
- /* The only case that an error should occr here is if the wait was
- * awakened by a signal.
- */
-
- ASSERT(errno == EINTR);
- }
+ nxsem_wait_uninterruptible(&priv->waitsem);
}
/****************************************************************************
@@ -1075,7 +1066,7 @@ static void cxd56_endwait(struct cxd56_sdiodev_s *priv,
{
/* Cancel the watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* Disable event-related interrupts */
@@ -1279,8 +1270,8 @@ static int cxd56_interrupt(int irq, FAR void *context, FAR void *arg)
putreg32(getreg32(CXD56_SDHCI_IRQSTATEN) & (~SDHCI_INT_CINT),
CXD56_SDHCI_IRQSTATEN);
work_cancel(HPWORK, &priv->cbwork);
- (void)work_queue(HPWORK, &priv->cbwork,
- (worker_t)cxd56_sdhci_irq_handler, &priv->dev, 0);
+ work_queue(HPWORK, &priv->cbwork,
+ (worker_t)cxd56_sdhci_irq_handler, &priv->dev, 0);
}
#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
@@ -1429,13 +1420,13 @@ static void cxd56_sdio_sdhci_reset(FAR struct sdio_dev_s *dev)
/* Initialize the SDHC slot structure data structure */
/* Initialize semaphores */
- sem_init(&priv->waitsem, 0, 0);
+ nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
- sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+ nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
@@ -2147,7 +2138,7 @@ static int cxd56_sdio_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@@ -3216,8 +3207,8 @@ static void cxd56_sdio_callback(void *arg)
work_cancel(HPWORK, &priv->cbwork);
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
- (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback,
- priv->cbarg, delay);
+ work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback,
+ priv->cbarg, delay);
}
else
{
@@ -3233,18 +3224,7 @@ static void cxd56_sdio_callback(void *arg)
#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
static void cxd56_sdio_takesem(FAR struct cxd56_sdiodev_s *priv)
{
- /* Take the semaphore, giving exclusive access to the driver (perhaps
- * waiting)
- */
-
- while (sem_wait(&priv->sc.sem) != 0)
- {
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- ASSERT(errno == EINTR);
- }
+ nxsem_wait_uninterruptible(&priv->sc.sem);
}
/****************************************************************************
@@ -3737,13 +3717,13 @@ static int cxd56_sdio_register_irq(FAR struct sdio_dev_s *dev, int func_num,
cxd56_sdio_writeb_internal(sf0, SDIO_CCCR_INTEN, regorg, NULL);
goto REG_IRQ_FAIL;
}
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return ret;
REG_IRQ_FAIL:
sf->irq_callback = NULL;
mcerr("ERROR: Ret: %d\n", ret);
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return ret;
}
@@ -3844,11 +3824,11 @@ static int cxd56_sdio_function_disable(FAR struct sdio_dev_s *dev,
{
goto FUNC_DIS_ERR;
}
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return 0;
FUNC_DIS_ERR:
mcerr("ERROR: Io fail ret %u\n", ret);
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return ret;
}
@@ -3908,12 +3888,12 @@ static int cxd56_sdio_function_enable(FAR struct sdio_dev_s *dev,
if (0 == ret)
{
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return 0;
}
FUNC_EN_ERR:
mcerr("ERROR: Io fail ret %u\n", ret);
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return -EIO;
}
@@ -3941,7 +3921,7 @@ static int cxd56_sdio_readb(FAR struct sdio_dev_s *dev, int func_num,
cxd56_sdio_takesem(priv);
ret = cxd56_sdio_readb_internal(priv->sc.fn[func_num], addr, rdata);
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return ret;
}
@@ -3969,7 +3949,7 @@ static int cxd56_sdio_writeb(FAR struct sdio_dev_s *dev, int func_num,
cxd56_sdio_takesem(priv);
ret = cxd56_sdio_writeb_internal(priv->sc.fn[func_num], addr, data, rdata);
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return ret;
}
@@ -4093,13 +4073,13 @@ static int cxd56_sdio_write(FAR struct sdio_dev_s *dev, int func_num,
data += size;
addr += size;
}
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return 0;
WRITE_TIME_OUT:
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return wkupevent & SDIOWAIT_TIMEOUT ? -ETIMEDOUT : -EIO;
WRITE_ERR:
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return ret;
}
@@ -4223,13 +4203,13 @@ static int cxd56_sdio_read(FAR struct sdio_dev_s *dev, int func_num,
data += size;
addr += size;
}
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return 0;
READ_TIME_OUT:
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return wkupevent & SDIOWAIT_TIMEOUT ? -ETIMEDOUT : -EIO;
READ_ERR:
- sem_post(&priv->sc.sem);
+ nxsem_post(&priv->sc.sem);
return ret;
}
@@ -4273,7 +4253,7 @@ static int cxd56_sdio_initialize(struct cxd56_sdiodev_s *priv)
priv->sc.full_speed = false;
priv->blocksize = SDIO_BLOCK_SIZE;
- sem_init(&priv->sc.sem, 0, 1);
+ nxsem_init(&priv->sc.sem, 0, 1);
#ifdef CONFIG_SDIO_DMA
priv->sc.dma = true;
#endif
diff --git a/arch/arm/src/cxd56xx/cxd56_serial.c b/arch/arm/src/cxd56xx/cxd56_serial.c
index 8c3811c..2a31811 100644
--- a/arch/arm/src/cxd56xx/cxd56_serial.c
+++ b/arch/arm/src/cxd56xx/cxd56_serial.c
@@ -543,10 +543,7 @@ static void up_detach(FAR struct uart_dev_s *dev)
static bool up_rxflowcontrol(FAR struct uart_dev_s *dev,
unsigned int nbuffered, bool upper)
{
- (void)nbuffered;
-
up_rxint(dev, !upper);
-
return true;
}
#endif /* CONFIG_SERIAL_IFLOWCONTROL */
@@ -924,13 +921,13 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
}
diff --git a/arch/arm/src/cxd56xx/cxd56_sph.c b/arch/arm/src/cxd56xx/cxd56_sph.c
index 5ee5376..c08a317 100644
--- a/arch/arm/src/cxd56xx/cxd56_sph.c
+++ b/arch/arm/src/cxd56xx/cxd56_sph.c
@@ -167,16 +167,12 @@ static int sph_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
static int sph_semtake(sem_t *id)
{
- while (sem_wait(id) != 0)
- {
- ASSERT(errno == EINTR);
- }
- return OK;
+ return nxsem_wait_uninterruptible(id);
}
static void sph_semgive(sem_t *id)
{
- sem_post(id);
+ nxsem_post(id);
}
static int sph_lock(FAR struct sph_dev_s *priv)
@@ -263,7 +259,7 @@ static inline int cxd56_sphdevinit(FAR const char *devname, int num)
return ERROR;
}
- sem_init(&priv->wait, 0, 0);
+ nxsem_init(&priv->wait, 0, 0);
priv->id = num;
irq_attach(CXD56_IRQ_SPH0 + num, cxd56_sphirqhandler, NULL);
diff --git a/arch/arm/src/cxd56xx/cxd56_spi.c b/arch/arm/src/cxd56xx/cxd56_spi.c
index fc9b52b..98a85c8 100644
--- a/arch/arm/src/cxd56xx/cxd56_spi.c
+++ b/arch/arm/src/cxd56xx/cxd56_spi.c
@@ -428,21 +428,12 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
{
/* Take the semaphore (perhaps waiting) */
- while (sem_wait(&priv->exclsem) != 0)
- {
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- ASSERT(errno == EINTR);
- }
+ return nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)sem_post(&priv->exclsem);
+ return nxsem_post(&priv->exclsem);
}
-
- return OK;
}
/****************************************************************************
@@ -1174,7 +1165,7 @@ FAR struct spi_dev_s *cxd56_spibus_initialize(int port)
return NULL;
}
#endif
- sem_init(&priv->dmasem, 0, 0);
+ nxsem_init(&priv->dmasem, 0, 0);
}
#endif
@@ -1199,7 +1190,7 @@ FAR struct spi_dev_s *cxd56_spibus_initialize(int port)
return NULL;
}
#endif
- sem_init(&priv->dmasem, 0, 0);
+ nxsem_init(&priv->dmasem, 0, 0);
}
#endif
@@ -1240,7 +1231,7 @@ FAR struct spi_dev_s *cxd56_spibus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
- sem_init(&priv->exclsem, 0, 1);
+ nxsem_init(&priv->exclsem, 0, 1);
#ifdef CONFIG_CXD56_SPI3_SCUSEQ
/* Enable the SPI, but not enable port 3 when SCU support enabled.
@@ -1258,7 +1249,7 @@ FAR struct spi_dev_s *cxd56_spibus_initialize(int port)
for (i = 0; i < CXD56_SPI_FIFOSZ; i++)
{
- (void)spi_getreg(priv, CXD56_SPI_DR_OFFSET);
+ spi_getreg(priv, CXD56_SPI_DR_OFFSET);
}
/* Enable clock gating (clock disable) */
@@ -1321,7 +1312,7 @@ void spi_flush(FAR struct spi_dev_s *dev)
do
{
- (void)spi_getreg(priv, CXD56_SPI_DR_OFFSET);
+ spi_getreg(priv, CXD56_SPI_DR_OFFSET);
}
while (spi_getreg(priv, CXD56_SPI_SR_OFFSET) & SPI_SR_RNE);
@@ -1471,7 +1462,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *data)
spierr("dma error\n");
}
- (void)sem_post(&priv->dmasem);
+ nxsem_post(&priv->dmasem);
}
/****************************************************************************
@@ -1493,7 +1484,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *data)
spierr("dma error\n");
}
- (void)sem_post(&priv->dmasem);
+ nxsem_post(&priv->dmasem);
}
/****************************************************************************
@@ -1554,7 +1545,7 @@ static void spi_dmatxwait(FAR struct cxd56_spidev_s *priv)
{
uint32_t val;
- if (sem_wait(&priv->dmasem) != OK)
+ if (nxsem_wait(&priv->dmasem) != OK)
{
spierr("dma error\n");
}
@@ -1578,7 +1569,7 @@ static void spi_dmarxwait(FAR struct cxd56_spidev_s *priv)
{
uint32_t val;
- if (sem_wait(&priv->dmasem) != OK)
+ if (nxsem_wait(&priv->dmasem) != OK)
{
spierr("dma error\n");
}
@@ -1602,12 +1593,12 @@ static void spi_dmatrxwait(FAR struct cxd56_spidev_s *priv)
{
uint32_t val;
- if (sem_wait(&priv->dmasem) != OK)
+ if (nxsem_wait(&priv->dmasem) != OK)
{
spierr("dma error\n");
}
- if (sem_wait(&priv->dmasem) != OK)
+ if (nxsem_wait(&priv->dmasem) != OK)
{
spierr("dma error\n");
}
diff --git a/arch/arm/src/cxd56xx/cxd56_sysctl.c b/arch/arm/src/cxd56xx/cxd56_sysctl.c
index 01c9e33..def7d5c 100644
--- a/arch/arm/src/cxd56xx/cxd56_sysctl.c
+++ b/arch/arm/src/cxd56xx/cxd56_sysctl.c
@@ -86,15 +86,12 @@ static int sysctl_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
static void sysctl_semtake(sem_t *semid)
{
- while (sem_wait(semid) != 0)
- {
- ASSERT(errno == EINTR);
- }
+ nxsem_wait_uninterruptible(semid);
}
static void sysctl_semgive(sem_t *semid)
{
- sem_post(semid);
+ nxsem_post(semid);
}
static int sysctl_rxhandler(int cpuid, int protoid,
@@ -150,10 +147,10 @@ void cxd56_sysctlinitialize(void)
{
cxd56_iccinit(CXD56_PROTO_SYSCTL);
- sem_init(&g_exc, 0, 1);
- sem_init(&g_sync, 0, 0);
+ nxsem_init(&g_exc, 0, 1);
+ nxsem_init(&g_sync, 0, 0);
cxd56_iccregisterhandler(CXD56_PROTO_SYSCTL, sysctl_rxhandler, NULL);
- (void)register_driver("/dev/sysctl", &g_sysctlfops, 0666, NULL);
+ register_driver("/dev/sysctl", &g_sysctlfops, 0666, NULL);
}
diff --git a/arch/arm/src/cxd56xx/cxd56_timer.c b/arch/arm/src/cxd56xx/cxd56_timer.c
index 9bd80da..405d81e 100644
--- a/arch/arm/src/cxd56xx/cxd56_timer.c
+++ b/arch/arm/src/cxd56xx/cxd56_timer.c
@@ -569,7 +569,7 @@ void cxd56_timer_initialize(FAR const char *devpath, int timer)
priv->ops = &g_tmrops;
- (void)irq_attach(irq, cxd56_timer_interrupt, priv);
+ irq_attach(irq, cxd56_timer_interrupt, priv);
/* Enable NVIC interrupt. */
@@ -577,7 +577,7 @@ void cxd56_timer_initialize(FAR const char *devpath, int timer)
/* Register the timer driver as /dev/timerX */
- (void)timer_register(devpath, (FAR struct timer_lowerhalf_s *)priv);
+ timer_register(devpath, (FAR struct timer_lowerhalf_s *)priv);
}
#endif /* CONFIG_TIMER */
diff --git a/arch/arm/src/cxd56xx/cxd56_timerisr.c b/arch/arm/src/cxd56xx/cxd56_timerisr.c
index d9312ea..41cf274 100644
--- a/arch/arm/src/cxd56xx/cxd56_timerisr.c
+++ b/arch/arm/src/cxd56xx/cxd56_timerisr.c
@@ -184,7 +184,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(CXD56_IRQ_SYSTICK, (xcpt_t)cxd56_timerisr, NULL);
+ irq_attach(CXD56_IRQ_SYSTICK, (xcpt_t)cxd56_timerisr, NULL);
/* Enable SysTick interrupts */
diff --git a/arch/arm/src/cxd56xx/cxd56_uart0.c b/arch/arm/src/cxd56xx/cxd56_uart0.c
index de7275b..3ca4943 100644
--- a/arch/arm/src/cxd56xx/cxd56_uart0.c
+++ b/arch/arm/src/cxd56xx/cxd56_uart0.c
@@ -128,11 +128,7 @@ static sem_t g_lock;
static int uart0_semtake(sem_t *id)
{
- while (sem_wait(id) != 0)
- {
- ASSERT(errno == EINTR);
- }
- return OK;
+ return nxsem_wait_uninterruptible(id);
}
/****************************************************************************
@@ -141,7 +137,7 @@ static int uart0_semtake(sem_t *id)
static void uart0_semgive(sem_t *id)
{
- sem_post(id);
+ nxsem_post(id);
}
/****************************************************************************
@@ -301,7 +297,7 @@ int cxd56_uart0initialize(FAR const char *devname)
{
int ret;
- sem_init(&g_lock, 0, 1);
+ nxsem_init(&g_lock, 0, 1);
ret = register_driver(devname, &g_uart0fops, 0666, NULL);
if (ret != 0)
@@ -319,7 +315,7 @@ int cxd56_uart0initialize(FAR const char *devname)
void cxd56_uart0uninitialize(FAR const char *devname)
{
unregister_driver(devname);
- sem_destroy(&g_lock);
+ nxsem_destroy(&g_lock);
}
#endif /* CONFIG_CXD56_UART0 */
diff --git a/arch/arm/src/cxd56xx/cxd56_udmac.c b/arch/arm/src/cxd56xx/cxd56_udmac.c
index 2cc4023..67f0f53 100644
--- a/arch/arm/src/cxd56xx/cxd56_udmac.c
+++ b/arch/arm/src/cxd56xx/cxd56_udmac.c
@@ -252,8 +252,8 @@ void cxd56_udmainitialize(void)
/* Initialize the channel list */
- sem_init(&g_dmac.exclsem, 0, 1);
- sem_init(&g_dmac.chansem, 0, CXD56_DMA_NCHANNELS);
+ nxsem_init(&g_dmac.exclsem, 0, 1);
+ nxsem_init(&g_dmac.chansem, 0, CXD56_DMA_NCHANNELS);
for (i = 0; i < CXD56_DMA_NCHANNELS; i++)
{
@@ -311,21 +311,11 @@ DMA_HANDLE cxd56_udmachannel(void)
* reserved for us.
*/
- while (sem_wait(&g_dmac.chansem) < 0)
- {
- /* sem_wait should fail only if it is awakened by a a signal */
-
- DEBUGASSERT(errno == EINTR);
- }
+ nxsem_wait_uninterruptible(&g_dmac.chansem);
/* Get exclusive access to the DMA channel list */
- while (sem_wait(&g_dmac.exclsem) < 0)
- {
- /* sem_wait should fail only if it is awakened by a a signal */
-
- DEBUGASSERT(errno == EINTR);
- }
+ nxsem_wait_uninterruptible(&g_dmac.exclsem);
/* Search for an available DMA channel */
@@ -346,11 +336,11 @@ DMA_HANDLE cxd56_udmachannel(void)
}
}
- sem_post(&g_dmac.exclsem);
+ nxsem_post(&g_dmac.exclsem);
/* Attach DMA interrupt vector */
- (void)irq_attach(CXD56_IRQ_DMA_A_0 + ch, cxd56_dmac_interrupt, NULL);
+ irq_attach(CXD56_IRQ_DMA_A_0 + ch, cxd56_dmac_interrupt, NULL);
/* Enable the IRQ at the AIC (still disabled at the DMA controller) */
@@ -405,7 +395,7 @@ void cxd56_udmafree(DMA_HANDLE handle)
* thread that may be waiting for a channel.
*/
- sem_post(&g_dmac.chansem);
+ nxsem_post(&g_dmac.chansem);
}
/****************************************************************************
diff --git a/arch/arm/src/cxd56xx/cxd56_usbdev.c b/arch/arm/src/cxd56xx/cxd56_usbdev.c
index 78b19bf..06b9eae 100644
--- a/arch/arm/src/cxd56xx/cxd56_usbdev.c
+++ b/arch/arm/src/cxd56xx/cxd56_usbdev.c
@@ -3348,9 +3348,9 @@ static void cxd56_notify_signal(uint16_t state, uint16_t power)
#ifdef CONFIG_CAN_PASS_STRUCTS
union sigval value;
value.sival_int = state << 16 | power;
- (void)sigqueue(priv->pid, priv->signo, value);
+ sigqueue(priv->pid, priv->signo, value);
#else
- (void)sigqueue(priv->pid, priv->signo, state << 16 | power);
+ sigqueue(priv->pid, priv->signo, state << 16 | power);
#endif
}
}
diff --git a/arch/arm/src/cxd56xx/cxd56_wdt.c b/arch/arm/src/cxd56xx/cxd56_wdt.c
index c655029..6d53ded 100644
--- a/arch/arm/src/cxd56xx/cxd56_wdt.c
+++ b/arch/arm/src/cxd56xx/cxd56_wdt.c
@@ -673,12 +673,12 @@ int cxd56_wdt_initialize(void)
#ifdef CONFIG_CXD56_WDT_INTERRUPT
/* Attach our WDT interrupt handler (But don't enable it yet) */
- (void)irq_attach(CXD56_IRQ_WDT_INT, cxd56_wdtinterrupt, priv);
+ irq_attach(CXD56_IRQ_WDT_INT, cxd56_wdtinterrupt, priv);
#endif
/* Register the watchdog driver as /dev/watchdog0 */
- (void)watchdog_register(DEVPATH, (FAR struct watchdog_lowerhalf_s *)priv);
+ watchdog_register(DEVPATH, (FAR struct watchdog_lowerhalf_s *)priv);
/* Register pm event callback */
diff --git a/arch/arm/src/dm320/dm320_decodeirq.c b/arch/arm/src/dm320/dm320_decodeirq.c
index 5d7e709..c621cf9 100644
--- a/arch/arm/src/dm320/dm320_decodeirq.c
+++ b/arch/arm/src/dm320/dm320_decodeirq.c
@@ -118,7 +118,7 @@ void up_decodeirq(uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(NULL);
+ group_addrenv(NULL);
#endif
}
#endif
diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c
index 10a2d15..a5d74e7 100644
--- a/arch/arm/src/dm320/dm320_serial.c
+++ b/arch/arm/src/dm320/dm320_serial.c
@@ -737,9 +737,9 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
- (void)uart_register("/dev/console", &CONSOLE_DEV);
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
}
/****************************************************************************
diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c
index 18dce86..8a93124 100644
--- a/arch/arm/src/dm320/dm320_usbdev.c
+++ b/arch/arm/src/dm320/dm320_usbdev.c
@@ -1304,7 +1304,7 @@ static inline void dm320_ep0setup(struct dm320_usbdev_s *priv)
/* Restart the write queue */
- (void)dm320_wrrequest(privep);
+ dm320_wrrequest(privep);
}
else
{
@@ -1581,7 +1581,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context, FAR void *arg)
if ((csr0 & USB_PERCSR0_RXPKTRDY) != 0)
{
usbtrace(TRACE_INTENTRY(DM320_TRACEINTID_RXPKTRDY), csr0);
- (void)dm320_getreg8(DM320_USB_COUNT0);
+ dm320_getreg8(DM320_USB_COUNT0);
dm320_ep0setup(priv);
}
else if ((csr0 & USB_PERCSR0_SENTST) != 0)
@@ -1643,7 +1643,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context, FAR void *arg)
if (!dm320_rqempty(privep))
{
- (void)dm320_wrrequest(privep);
+ dm320_wrrequest(privep);
}
}
break;
diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c
index ddb2e23..7afe854 100644
--- a/arch/arm/src/efm32/efm32_dma.c
+++ b/arch/arm/src/efm32/efm32_dma.c
@@ -297,7 +297,7 @@ void weak_function up_dma_initialize(void)
/* Attach DMA interrupt vector */
- (void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt, NULL);
+ irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt, NULL);
/* Enable the DMA controller */
@@ -336,7 +336,6 @@ DMA_HANDLE efm32_dmachannel(void)
struct dma_channel_s *dmach;
unsigned int chndx;
uint32_t bit;
- int ret;
/* Take a count from from the channel counting semaphore. We may block
* if there are no free channels. When we get the count, then we can
@@ -344,35 +343,11 @@ DMA_HANDLE efm32_dmachannel(void)
* reserved for us.
*/
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&g_dmac.chansem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&g_dmac.chansem);
/* Get exclusive access to the DMA channel list */
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&g_dmac.exclsem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&g_dmac.exclsem);
/* Search for an available DMA channel */
diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c
index 8f2e0e9..74f6c37 100644
--- a/arch/arm/src/efm32/efm32_i2c.c
+++ b/arch/arm/src/efm32/efm32_i2c.c
@@ -480,21 +480,7 @@ static const char *efm32_i2c_state_str(int i2c_state)
static inline void efm32_i2c_sem_wait(FAR struct efm32_i2c_priv_s *priv)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->sem_excl);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->sem_excl);
}
/****************************************************************************
@@ -544,7 +530,7 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
{
/* Get the current time */
- (void)clock_gettime(CLOCK_REALTIME, &abstime);
+ clock_gettime(CLOCK_REALTIME, &abstime);
/* Calculate a time in the future */
@@ -578,17 +564,16 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
/* Wait until either the transfer is complete or the timeout expires */
- ret = nxsem_timedwait(&priv->sem_isr, &abstime);
+ ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime);
/* Disable I2C interrupts */
efm32_i2c_putreg(priv, EFM32_I2C_IEN_OFFSET, 0);
- if (ret < 0 && ret != -EINTR)
+ if (ret < 0)
{
/* Break out of the loop on irrecoverable errors. This would include
- * timeouts and mystery errors reported by nxsem_timedwait. NOTE that
- * we try again if we are awakened by a signal (EINTR).
+ * timeouts and mystery errors reported by nxsem_timedwait.
*/
break;
@@ -1495,7 +1480,7 @@ static int efm32_i2c_transfer(FAR struct i2c_master_s *dev,
I2C_CMD_CLEARPC | I2C_CMD_CLEARTX);
if (efm32_i2c_getreg(priv, EFM32_I2C_IF_OFFSET) & I2C_IF_RXDATAV)
{
- (void)efm32_i2c_getreg(priv, EFM32_I2C_RXDATA_OFFSET);
+ efm32_i2c_getreg(priv, EFM32_I2C_RXDATA_OFFSET);
}
/* Clear all pending interrupts prior to starting transfer. */
diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c
index 9a6d9f7..4764a02 100644
--- a/arch/arm/src/efm32/efm32_idle.c
+++ b/arch/arm/src/efm32/efm32_idle.c
@@ -119,7 +119,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
- (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+ pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@@ -143,7 +143,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
- (void)efm32_pmstandby();
+ efm32_pmstandby();
break;
default:
diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c
index a2b25d8..d46722a 100644
--- a/arch/arm/src/efm32/efm32_irq.c
+++ b/arch/arm/src/efm32/efm32_irq.c
@@ -166,7 +166,7 @@ static void efm32_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int efm32_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -174,7 +174,7 @@ static int efm32_nmi(int irq, FAR void *context, FAR void *arg)
static int efm32_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
@@ -182,7 +182,7 @@ static int efm32_busfault(int irq, FAR void *context, FAR void *arg)
static int efm32_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
@@ -190,7 +190,7 @@ static int efm32_usagefault(int irq, FAR void *context, FAR void *arg)
static int efm32_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -198,7 +198,7 @@ static int efm32_pendsv(int irq, FAR void *context, FAR void *arg)
static int efm32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -206,7 +206,7 @@ static int efm32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int efm32_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c
index dee04ce..3c48b5c 100644
--- a/arch/arm/src/efm32/efm32_leserial.c
+++ b/arch/arm/src/efm32/efm32_leserial.c
@@ -794,14 +794,14 @@ void up_serialinit(void)
/* Register the console */
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
- (void)uart_register("/dev/ttyLE0", &TTYLE0_DEV);
+ uart_register("/dev/ttyLE0", &TTYLE0_DEV);
#ifdef TTYLE1_DEV
- (void)uart_register("/dev/ttyLE1", &TTYLE1_DEV);
+ uart_register("/dev/ttyLE1", &TTYLE1_DEV);
#endif
}
diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c
index 09f6dd7..251c144 100644
--- a/arch/arm/src/efm32/efm32_pwm.c
+++ b/arch/arm/src/efm32/efm32_pwm.c
@@ -481,7 +481,7 @@ static int pwm_interrupt(int irq, void *context, FAR void *arg)
/* Disable first interrupts, stop and reset the timer */
- (void)pwm_stop((FAR struct pwm_lowerhalf_s *)priv);
+ pwm_stop((FAR struct pwm_lowerhalf_s *)priv);
/* Then perform the callback into the upper half driver */
diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c
index 80eb14c..db5c48a7 100644
--- a/arch/arm/src/efm32/efm32_serial.c
+++ b/arch/arm/src/efm32/efm32_serial.c
@@ -1168,23 +1168,23 @@ void up_serialinit(void)
/* Register the console */
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
- (void)uart_register("/dev/ttyS4", &TTYS4_DEV);
+ uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
}
diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c
index 00564cd..929c84a 100644
--- a/arch/arm/src/efm32/efm32_spi.c
+++ b/arch/arm/src/efm32/efm32_spi.c
@@ -377,7 +377,7 @@ static void spi_rxflush(const struct efm32_spiconfig_s *config)
{
/* Read and discard the data */
- (void)spi_getreg(config, EFM32_USART_RXDATA_OFFSET);
+ spi_getreg(config, EFM32_USART_RXDATA_OFFSET);
}
}
@@ -437,24 +437,11 @@ static void spi_dma_timeout(int argc, uint32_t arg1, ...)
static void spi_dmarxwait(struct efm32_spidev_s *priv)
{
irqstate_t flags;
- int ret;
/* Take the semaphore (perhaps waiting). */
flags = enter_critical_section();
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->rxdmasem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->rxdmasem);
/* Cancel the timeout only if both the RX and TX transfers have completed */
@@ -480,24 +467,11 @@ static void spi_dmarxwait(struct efm32_spidev_s *priv)
static void spi_dmatxwait(struct efm32_spidev_s *priv)
{
irqstate_t flags;
- int ret;
/* Take the semaphore (perhaps waiting). */
flags = enter_critical_section();
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->txdmasem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->txdmasem);
/* Cancel the timeout only if both the RX and TX transfers have completed */
@@ -522,7 +496,7 @@ static void spi_dmatxwait(struct efm32_spidev_s *priv)
#ifdef CONFIG_EFM32_SPI_DMA
static inline void spi_dmarxwakeup(struct efm32_spidev_s *priv)
{
- (void)nxsem_post(&priv->rxdmasem);
+ nxsem_post(&priv->rxdmasem);
}
#endif
@@ -537,7 +511,7 @@ static inline void spi_dmarxwakeup(struct efm32_spidev_s *priv)
#ifdef CONFIG_EFM32_SPI_DMA
static inline void spi_dmatxwakeup(struct efm32_spidev_s *priv)
{
- (void)nxsem_post(&priv->txdmasem);
+ nxsem_post(&priv->txdmasem);
}
#endif
@@ -755,27 +729,15 @@ static inline void spi_dmatxstart(FAR struct efm32_spidev_s *priv)
static int spi_lock(struct spi_dev_s *dev, bool lock)
{
struct efm32_spidev_s *priv = (struct efm32_spidev_s *)dev;
+ int ret;
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -1655,8 +1617,8 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
/* Initialized semaphores used to wait for DMA completion */
- (void)nxsem_init(&priv->rxdmasem, 0, 0);
- (void)nxsem_init(&priv->txdmasem, 0, 0);
+ nxsem_init(&priv->rxdmasem, 0, 0);
+ nxsem_init(&priv->txdmasem, 0, 0);
/* These semaphores are used for signaling and, hence, should not have
* priority inheritance enabled.
diff --git a/arch/arm/src/efm32/efm32_timerisr.c b/arch/arm/src/efm32/efm32_timerisr.c
index a4728df..6fcea93 100644
--- a/arch/arm/src/efm32/efm32_timerisr.c
+++ b/arch/arm/src/efm32/efm32_timerisr.c
@@ -125,7 +125,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(EFM32_IRQ_SYSTICK, (xcpt_t)efm32_timerisr, NULL);
+ irq_attach(EFM32_IRQ_SYSTICK, (xcpt_t)efm32_timerisr, NULL);
/* Enable SysTick interrupts */
diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c
index e0de5b0..f9febfd 100644
--- a/arch/arm/src/efm32/efm32_usbdev.c
+++ b/arch/arm/src/efm32/efm32_usbdev.c
@@ -1452,7 +1452,7 @@ static void efm32_rxfifo_discard(FAR struct efm32_ep_s *privep, int len)
for (i = 0; i < len; i += 4)
{
volatile uint32_t data = efm32_getreg(regaddr);
- (void)data;
+ UNUSED(data);
}
}
}
@@ -2223,7 +2223,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
{
/* Actually, I think we could just stall here. */
- (void)efm32_req_dispatch(priv, &priv->ctrlreq);
+ efm32_req_dispatch(priv, &priv->ctrlreq);
}
}
else
@@ -2269,7 +2269,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
{
/* Actually, I think we could just stall here. */
- (void)efm32_req_dispatch(priv, &priv->ctrlreq);
+ efm32_req_dispatch(priv, &priv->ctrlreq);
}
else
{
@@ -2333,7 +2333,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_GETSETDESC), 0);
if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
{
- (void)efm32_req_dispatch(priv, &priv->ctrlreq);
+ efm32_req_dispatch(priv, &priv->ctrlreq);
}
else
{
@@ -2358,7 +2358,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
ctrlreq->index == 0 &&
ctrlreq->len == 1)
{
- (void)efm32_req_dispatch(priv, &priv->ctrlreq);
+ efm32_req_dispatch(priv, &priv->ctrlreq);
}
else
{
@@ -2430,7 +2430,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
{
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_GETSETIF), 0);
- (void)efm32_req_dispatch(priv, &priv->ctrlreq);
+ efm32_req_dispatch(priv, &priv->ctrlreq);
}
break;
@@ -2508,7 +2508,7 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv)
{
/* Dispatch any non-standard requests */
- (void)efm32_req_dispatch(priv, &priv->ctrlreq);
+ efm32_req_dispatch(priv, &priv->ctrlreq);
}
else
{
@@ -4007,10 +4007,10 @@ static void efm32_ep0_configure(FAR struct efm32_usbdev_s *priv)
{
/* Enable EP0 IN and OUT */
- (void)efm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL,
- CONFIG_USBDEV_EP0_MAXSIZE);
- (void)efm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL,
- CONFIG_USBDEV_EP0_MAXSIZE);
+ efm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL,
+ CONFIG_USBDEV_EP0_MAXSIZE);
+ efm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL,
+ CONFIG_USBDEV_EP0_MAXSIZE);
}
/****************************************************************************
diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c
index 03ce536..0dbe111 100644
--- a/arch/arm/src/efm32/efm32_usbhost.c
+++ b/arch/arm/src/efm32/efm32_usbhost.c
@@ -723,21 +723,7 @@ static inline void efm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t set
static void efm32_takesem(sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -1193,13 +1179,7 @@ static int efm32_chan_wait(FAR struct efm32_usbhost_s *priv,
* wait here.
*/
- ret = nxsem_wait(&chan->waitsem);
-
- /* nxsem_wait should succeed. But it is possible that we could be
- * awakened by a signal too.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
+ nxsem_wait_uninterruptible(&chan->waitsem);
}
while (chan->waiter);
diff --git a/arch/arm/src/imx1/imx_decodeirq.c b/arch/arm/src/imx1/imx_decodeirq.c
index 48164d9..d41e349 100644
--- a/arch/arm/src/imx1/imx_decodeirq.c
+++ b/arch/arm/src/imx1/imx_decodeirq.c
@@ -137,7 +137,7 @@ void up_decodeirq(uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(NULL);
+ group_addrenv(NULL);
#endif
}
#endif
diff --git a/arch/arm/src/imx1/imx_serial.c b/arch/arm/src/imx1/imx_serial.c
index de0af5b..94b7ef3 100644
--- a/arch/arm/src/imx1/imx_serial.c
+++ b/arch/arm/src/imx1/imx_serial.c
@@ -1141,15 +1141,15 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
# ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
# ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
# endif
# endif
#endif
diff --git a/arch/arm/src/imx1/imx_spi.c b/arch/arm/src/imx1/imx_spi.c
index c9af751..1374799 100644
--- a/arch/arm/src/imx1/imx_spi.c
+++ b/arch/arm/src/imx1/imx_spi.c
@@ -340,7 +340,7 @@ static void spi_txuint8(struct imx_spidev_s *priv)
static void spi_rxnull(struct imx_spidev_s *priv)
{
- (void)spi_getreg(priv, CSPI_RXD_OFFSET);
+ spi_getreg(priv, CSPI_RXD_OFFSET);
}
static void spi_rxuint16(struct imx_spidev_s *priv)
@@ -504,7 +504,6 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
#ifndef CONFIG_SPI_POLLWAIT
irqstate_t flags;
uint32_t regval;
- int ret;
#endif
int ntxd;
@@ -558,13 +557,9 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
* with the transfer, so it should be safe with no timeout.
*/
- do
- {
- /* Wait to be signaled from the interrupt handler */
+ /* Wait to be signaled from the interrupt handler */
- ret = nxsem_wait(&priv->waitsem);
- }
- while (ret < 0 && ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->waitsem);
#else
/* Perform the transfer using polling logic. This will totally
@@ -713,19 +708,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->exclsem);
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -919,7 +906,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
uint16_t response = 0;
- (void)spi_transfer(priv, &wd, &response, 1);
+ spi_transfer(priv, &wd, &response, 1);
return response;
}
@@ -948,7 +935,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
- (void)spi_transfer(priv, txbuffer, rxbuffer, nwords);
+ spi_transfer(priv, txbuffer, rxbuffer, nwords);
}
#endif
@@ -975,7 +962,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
- (void)spi_transfer(priv, buffer, NULL, nwords);
+ spi_transfer(priv, buffer, NULL, nwords);
}
#endif
@@ -1002,7 +989,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
- (void)spi_transfer(priv, NULL, buffer, nwords);
+ spi_transfer(priv, NULL, buffer, nwords);
}
#endif
diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c
index b92c3b1..42e5d4a 100644
--- a/arch/arm/src/imx6/imx_cpuboot.c
+++ b/arch/arm/src/imx6/imx_cpuboot.c
@@ -298,7 +298,7 @@ void arm_cpu_boot(int cpu)
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
- (void)up_irq_enable();
+ up_irq_enable();
#endif
/* The next thing that we expect to happen is for logic running on CPU0
diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c
index a679b4a..a1631e3 100644
--- a/arch/arm/src/imx6/imx_ecspi.c
+++ b/arch/arm/src/imx6/imx_ecspi.c
@@ -465,7 +465,7 @@ static void spi_txuint8(struct imx_spidev_s *priv)
static void spi_rxnull(struct imx_spidev_s *priv)
{
- (void)spi_getreg(priv, ECSPI_RXDATA_OFFSET);
+ spi_getreg(priv, ECSPI_RXDATA_OFFSET);
}
static void spi_rxuint16(struct imx_spidev_s *priv)
@@ -629,7 +629,6 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
#ifndef CONFIG_SPI_POLLWAIT
irqstate_t flags;
uint32_t regval;
- int ret;
#endif
int ntxd;
@@ -683,13 +682,9 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
* with the transfer, so it should be safe with no timeout.
*/
- do
- {
- /* Wait to be signaled from the interrupt handler */
+ /* Wait to be signaled from the interrupt handler */
- ret = nxsem_wait(&priv->waitsem);
- }
- while (ret < 0 && ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->waitsem);
#else
/* Perform the transfer using polling logic. This will totally
@@ -798,19 +793,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->exclsem);
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -1032,7 +1019,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
uint16_t response = 0;
- (void)spi_transfer(priv, &wd, &response, 1);
+ spi_transfer(priv, &wd, &response, 1);
return response;
}
@@ -1133,7 +1120,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
- (void)spi_transfer(priv, txbuffer, rxbuffer, nwords);
+ spi_transfer(priv, txbuffer, rxbuffer, nwords);
}
#endif
@@ -1160,7 +1147,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
- (void)spi_transfer(priv, buffer, NULL, nwords);
+ spi_transfer(priv, buffer, NULL, nwords);
}
#endif
@@ -1187,7 +1174,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
- (void)spi_transfer(priv, NULL, buffer, nwords);
+ spi_transfer(priv, NULL, buffer, nwords);
}
#endif
diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c
index 4b172aa..5006a1f 100644
--- a/arch/arm/src/imx6/imx_irq.c
+++ b/arch/arm/src/imx6/imx_irq.c
@@ -183,6 +183,6 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
- (void)up_irq_enable();
+ up_irq_enable();
#endif
}
diff --git a/arch/arm/src/imx6/imx_lowputc.c b/arch/arm/src/imx6/imx_lowputc.c
index 782861c..c3c3225 100644
--- a/arch/arm/src/imx6/imx_lowputc.c
+++ b/arch/arm/src/imx6/imx_lowputc.c
@@ -188,13 +188,13 @@ void imx_lowsetup(void)
* control is enabled. REVISIT: DTR, DCD, RI, and DSR -- not configured.
*/
- (void)imx_config_gpio(GPIO_UART1_RX_DATA);
- (void)imx_config_gpio(GPIO_UART1_TX_DATA);
+ imx_config_gpio(GPIO_UART1_RX_DATA);
+ imx_config_gpio(GPIO_UART1_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART1_CTS);
+ imx_config_gpio(GPIO_UART1_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART1_RTS);
+ imx_config_gpio(GPIO_UART1_RTS);
#endif
#endif
@@ -210,13 +210,13 @@ void imx_lowsetup(void)
* control is enabled.
*/
- (void)imx_config_gpio(GPIO_UART2_RX_DATA);
- (void)imx_config_gpio(GPIO_UART2_TX_DATA);
+ imx_config_gpio(GPIO_UART2_RX_DATA);
+ imx_config_gpio(GPIO_UART2_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART2_CTS);
+ imx_config_gpio(GPIO_UART2_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART2_RTS);
+ imx_config_gpio(GPIO_UART2_RTS);
#endif
#endif
@@ -232,13 +232,13 @@ void imx_lowsetup(void)
* control is enabled.
*/
- (void)imx_config_gpio(GPIO_UART3_RX_DATA);
- (void)imx_config_gpio(GPIO_UART3_TX_DATA);
+ imx_config_gpio(GPIO_UART3_RX_DATA);
+ imx_config_gpio(GPIO_UART3_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART3_CTS);
+ imx_config_gpio(GPIO_UART3_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART3_RTS);
+ imx_config_gpio(GPIO_UART3_RTS);
#endif
#endif
@@ -254,13 +254,13 @@ void imx_lowsetup(void)
* control is enabled.
*/
- (void)imx_config_gpio(GPIO_UART4_RX_DATA);
- (void)imx_config_gpio(GPIO_UART4_TX_DATA);
+ imx_config_gpio(GPIO_UART4_RX_DATA);
+ imx_config_gpio(GPIO_UART4_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART4_CTS);
+ imx_config_gpio(GPIO_UART4_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART4_RTS);
+ imx_config_gpio(GPIO_UART4_RTS);
#endif
#endif
@@ -276,20 +276,20 @@ void imx_lowsetup(void)
* control is enabled.
*/
- (void)imx_config_gpio(GPIO_UART5_RX_DATA);
- (void)imx_config_gpio(GPIO_UART5_TX_DATA);
+ imx_config_gpio(GPIO_UART5_RX_DATA);
+ imx_config_gpio(GPIO_UART5_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART5_CTS);
+ imx_config_gpio(GPIO_UART5_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
- (void)imx_config_gpio(GPIO_UART5_RTS);
+ imx_config_gpio(GPIO_UART5_RTS);
#endif
#endif
#ifdef IMX_HAVE_UART_CONSOLE
/* Configure the serial console for initial, non-interrupt driver mode */
- (void)imx_uart_configure(IMX_CONSOLE_VBASE, &g_console_config);
+ imx_uart_configure(IMX_CONSOLE_VBASE, &g_console_config);
#endif
#endif /* IMX_HAVE_UART */
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c
index 2155768..41bae86 100644
--- a/arch/arm/src/imx6/imx_serial.c
+++ b/arch/arm/src/imx6/imx_serial.c
@@ -601,7 +601,7 @@ static int imx_attach(struct uart_dev_s *dev)
{
/* Configure as a (high) level interrupt */
- (void)arm_gic_irq_trigger(priv->irq, false);
+ arm_gic_irq_trigger(priv->irq, false);
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the UART
@@ -922,19 +922,19 @@ void imx_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
# ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
# ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
# ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS2_DEV);
+ uart_register("/dev/ttyS3", &TTYS2_DEV);
# ifdef TTYS4_DEV
- (void)uart_register("/dev/ttyS4", &TTYS2_DEV);
+ uart_register("/dev/ttyS4", &TTYS2_DEV);
# endif
# endif
# endif
diff --git a/arch/arm/src/imx6/imx_timerisr.c b/arch/arm/src/imx6/imx_timerisr.c
index c9ee3ce..2f48358 100644
--- a/arch/arm/src/imx6/imx_timerisr.c
+++ b/arch/arm/src/imx6/imx_timerisr.c
@@ -256,11 +256,11 @@ void arm_timer_initialize(void)
/* Configure as a (rising) edge-triggered interrupt */
- (void)arm_gic_irq_trigger(IMX_IRQ_GPT, true);
+ arm_gic_irq_trigger(IMX_IRQ_GPT, true);
/* Attach the timer interrupt vector */
- (void)irq_attach(IMX_IRQ_GPT, (xcpt_t)imx_timerisr, NULL);
+ irq_attach(IMX_IRQ_GPT, (xcpt_t)imx_timerisr, NULL);
/* Enable all three GPT output compare interrupts */
diff --git a/arch/arm/src/imxrt/imxrt_edma.c b/arch/arm/src/imxrt/imxrt_edma.c
index 18c7901..932c1e7 100644
--- a/arch/arm/src/imxrt/imxrt_edma.c
+++ b/arch/arm/src/imxrt/imxrt_edma.c
@@ -185,26 +185,12 @@ static struct imxrt_edmatcd_s g_tcd_pool[CONFIG_IMXRT_EDMA_NTCD]
static void imxrt_takechsem(void)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&g_edma.chsem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR || ret == -ECANCELED);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&g_edma.chsem);
}
static inline void imxrt_givechsem(void)
{
- (void)nxsem_post(&g_edma.chsem);
+ nxsem_post(&g_edma.chsem);
}
/****************************************************************************
@@ -218,26 +204,12 @@ static inline void imxrt_givechsem(void)
#if CONFIG_IMXRT_EDMA_NTCD > 0
static void imxrt_takedsem(void)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&g_edma.dsem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR || ret == -ECANCELED);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&g_edma.dsem);
}
static inline void imxrt_givedsem(void)
{
- (void)nxsem_post(&g_edma.dsem);
+ nxsem_post(&g_edma.dsem);
}
#endif
@@ -296,7 +268,7 @@ static void imxrt_tcd_free(struct imxrt_edmatcd_s *tcd)
flags = spin_lock_irqsave();
sq_addlast((sq_entry_t *)tcd, &g_tcd_free);
- (void)imxrt_givedsem();
+ imxrt_givedsem();
spin_unlock_irqrestore(flags);
}
#endif
@@ -811,26 +783,26 @@ void weak_function up_dma_initialize(void)
* NOTE that there are only 16 vectors for 32 DMA channels.
*/
- (void)irq_attach(IMXRT_IRQ_EDMA0_16, imxrt_edma_interrupt, &g_edma.dmach[0]);
- (void)irq_attach(IMXRT_IRQ_EDMA1_17, imxrt_edma_interrupt, &g_edma.dmach[1]);
- (void)irq_attach(IMXRT_IRQ_EDMA2_18, imxrt_edma_interrupt, &g_edma.dmach[2]);
- (void)irq_attach(IMXRT_IRQ_EDMA3_19, imxrt_edma_interrupt, &g_edma.dmach[3]);
- (void)irq_attach(IMXRT_IRQ_EDMA4_20, imxrt_edma_interrupt, &g_edma.dmach[4]);
- (void)irq_attach(IMXRT_IRQ_EDMA5_21, imxrt_edma_interrupt, &g_edma.dmach[5]);
- (void)irq_attach(IMXRT_IRQ_EDMA6_22, imxrt_edma_interrupt, &g_edma.dmach[6]);
- (void)irq_attach(IMXRT_IRQ_EDMA7_23, imxrt_edma_interrupt, &g_edma.dmach[7]);
- (void)irq_attach(IMXRT_IRQ_EDMA8_24, imxrt_edma_interrupt, &g_edma.dmach[8]);
- (void)irq_attach(IMXRT_IRQ_EDMA9_25, imxrt_edma_interrupt, &g_edma.dmach[9]);
- (void)irq_attach(IMXRT_IRQ_EDMA10_26, imxrt_edma_interrupt, &g_edma.dmach[10]);
- (void)irq_attach(IMXRT_IRQ_EDMA11_27, imxrt_edma_interrupt, &g_edma.dmach[11]);
- (void)irq_attach(IMXRT_IRQ_EDMA12_28, imxrt_edma_interrupt, &g_edma.dmach[12]);
- (void)irq_attach(IMXRT_IRQ_EDMA13_29, imxrt_edma_interrupt, &g_edma.dmach[13]);
- (void)irq_attach(IMXRT_IRQ_EDMA14_30, imxrt_edma_interrupt, &g_edma.dmach[14]);
- (void)irq_attach(IMXRT_IRQ_EDMA15_31, imxrt_edma_interrupt, &g_edma.dmach[15]);
+ irq_attach(IMXRT_IRQ_EDMA0_16, imxrt_edma_interrupt, &g_edma.dmach[0]);
+ irq_attach(IMXRT_IRQ_EDMA1_17, imxrt_edma_interrupt, &g_edma.dmach[1]);
+ irq_attach(IMXRT_IRQ_EDMA2_18, imxrt_edma_interrupt, &g_edma.dmach[2]);
+ irq_attach(IMXRT_IRQ_EDMA3_19, imxrt_edma_interrupt, &g_edma.dmach[3]);
+ irq_attach(IMXRT_IRQ_EDMA4_20, imxrt_edma_interrupt, &g_edma.dmach[4]);
+ irq_attach(IMXRT_IRQ_EDMA5_21, imxrt_edma_interrupt, &g_edma.dmach[5]);
+ irq_attach(IMXRT_IRQ_EDMA6_22, imxrt_edma_interrupt, &g_edma.dmach[6]);
+ irq_attach(IMXRT_IRQ_EDMA7_23, imxrt_edma_interrupt, &g_edma.dmach[7]);
+ irq_attach(IMXRT_IRQ_EDMA8_24, imxrt_edma_interrupt, &g_edma.dmach[8]);
+ irq_attach(IMXRT_IRQ_EDMA9_25, imxrt_edma_interrupt, &g_edma.dmach[9]);
+ irq_attach(IMXRT_IRQ_EDMA10_26, imxrt_edma_interrupt, &g_edma.dmach[10]);
+ irq_attach(IMXRT_IRQ_EDMA11_27, imxrt_edma_interrupt, &g_edma.dmach[11]);
+ irq_attach(IMXRT_IRQ_EDMA12_28, imxrt_edma_interrupt, &g_edma.dmach[12]);
+ irq_attach(IMXRT_IRQ_EDMA13_29, imxrt_edma_interrupt, &g_edma.dmach[13]);
+ irq_attach(IMXRT_IRQ_EDMA14_30, imxrt_edma_interrupt, &g_edma.dmach[14]);
+ irq_attach(IMXRT_IRQ_EDMA15_31, imxrt_edma_interrupt, &g_edma.dmach[15]);
/* Attach the DMA error interrupt vector */
- (void)irq_attach(IMXRT_IRQ_EDMA_ERROR, imxrt_error_interrupt, NULL);
+ irq_attach(IMXRT_IRQ_EDMA_ERROR, imxrt_error_interrupt, NULL);
/* Disable and clear all error interrupts */
diff --git a/arch/arm/src/imxrt/imxrt_ehci.c b/arch/arm/src/imxrt/imxrt_ehci.c
index be5e7bef..2a98806 100644
--- a/arch/arm/src/imxrt/imxrt_ehci.c
+++ b/arch/arm/src/imxrt/imxrt_ehci.c
@@ -1022,21 +1022,7 @@ static int ehci_wait_usbsts(uint32_t maskbits, uint32_t donebits,
static void imxrt_takesem(sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -1652,7 +1638,7 @@ static void imxrt_qh_enqueue(struct imxrt_qh_s *qhead, struct imxrt_qh_s *qh)
*/
qh->fqp = qh->hw.overlay.nqp;
- (void)imxrt_qh_dump(qh, NULL, NULL);
+ imxrt_qh_dump(qh, NULL, NULL);
/* Add the new QH to the head of the asynchronous queue list.
*
diff --git a/arch/arm/src/imxrt/imxrt_enc.c b/arch/arm/src/imxrt/imxrt_enc.c
index 0b39c9b..b8463c1 100644
--- a/arch/arm/src/imxrt/imxrt_enc.c
+++ b/arch/arm/src/imxrt/imxrt_enc.c
@@ -560,21 +560,7 @@ void imxrt_enc_clock_disable (uint32_t base)
static inline void imxrt_enc_sem_wait(FAR struct imxrt_enc_lowerhalf_s *priv)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->sem_excl);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->sem_excl);
}
/************************************************************************************
diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c
index 423080f..c2c3a0f 100644
--- a/arch/arm/src/imxrt/imxrt_enet.c
+++ b/arch/arm/src/imxrt/imxrt_enet.c
@@ -563,8 +563,8 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
- (void)wd_start(priv->txtimeout, IMXRT_TXTIMEOUT, imxrt_txtimeout_expiry, 1,
- (wdparm_t)priv);
+ wd_start(priv->txtimeout, IMXRT_TXTIMEOUT, imxrt_txtimeout_expiry, 1,
+ (wdparm_t)priv);
/* Start the TX transfer (if it was not already waiting for buffers) */
@@ -964,7 +964,7 @@ static void imxrt_txdone(FAR struct imxrt_driver_s *priv)
* new XMIT data
*/
- (void)devif_poll(&priv->dev, imxrt_txpoll);
+ devif_poll(&priv->dev, imxrt_txpoll);
}
/****************************************************************************
@@ -1034,8 +1034,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
galrstore = getreg32(IMXRT_ENET_GALR);
#endif
- (void)imxrt_ifdown(&priv->dev);
- (void)imxrt_ifup_action(&priv->dev, false);
+ imxrt_ifdown(&priv->dev);
+ imxrt_ifup_action(&priv->dev, false);
#ifdef CONFIG_NET_MCASTGROUP
/* Now write the multicast table back */
@@ -1046,7 +1046,7 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
/* Then poll the network for new XMIT data */
- (void)devif_poll(&priv->dev, imxrt_txpoll);
+ devif_poll(&priv->dev, imxrt_txpoll);
}
else
{
@@ -1152,12 +1152,12 @@ static void imxrt_txtimeout_work(FAR void *arg)
* aggressive hardware reset.
*/
- (void)imxrt_ifdown(&priv->dev);
- (void)imxrt_ifup_action(&priv->dev, false);
+ imxrt_ifdown(&priv->dev);
+ imxrt_ifup_action(&priv->dev, false);
/* Then poll the network for new XMIT data */
- (void)devif_poll(&priv->dev, imxrt_txpoll);
+ devif_poll(&priv->dev, imxrt_txpoll);
net_unlock();
}
@@ -1231,13 +1231,13 @@ static void imxrt_poll_work(FAR void *arg)
* transmit in progress, we will missing TCP time state updates?
*/
- (void)devif_timer(&priv->dev, IMXRT_WDDELAY, imxrt_txpoll);
+ devif_timer(&priv->dev, IMXRT_WDDELAY, imxrt_txpoll);
}
/* Setup the watchdog poll timer again in any case */
- (void)wd_start(priv->txpoll, IMXRT_WDDELAY, imxrt_polltimer_expiry,
- 1, (wdparm_t)priv);
+ wd_start(priv->txpoll, IMXRT_WDDELAY, imxrt_polltimer_expiry,
+ 1, (wdparm_t)priv);
net_unlock();
}
@@ -1368,8 +1368,8 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy)
/* Set and activate a timer process */
- (void)wd_start(priv->txpoll, IMXRT_WDDELAY, imxrt_polltimer_expiry, 1,
- (wdparm_t)priv);
+ wd_start(priv->txpoll, IMXRT_WDDELAY, imxrt_polltimer_expiry, 1,
+ (wdparm_t)priv);
/* Clear all pending ENET interrupt */
@@ -1506,7 +1506,7 @@ static void imxrt_txavail_work(FAR void *arg)
* new XMIT data.
*/
- (void)devif_poll(&priv->dev, imxrt_txpoll);
+ devif_poll(&priv->dev, imxrt_txpoll);
}
}
@@ -2568,11 +2568,11 @@ int imxrt_netinitialize(int intf)
* the device and/or calling imxrt_ifdown().
*/
- (void)imxrt_ifdown(&priv->dev);
+ imxrt_ifdown(&priv->dev);
/* Register the device with the OS so that socket IOCTLs can be performed */
- (void)netdev_register(&priv->dev, NET_LL_ETHERNET);
+ netdev_register(&priv->dev, NET_LL_ETHERNET);
UNUSED(ret);
return OK;
@@ -2592,7 +2592,7 @@ int imxrt_netinitialize(int intf)
#if CONFIG_IMXRT_ENET_NETHIFS == 1 && !defined(CONFIG_NETDEV_LATEINIT)
void up_netinitialize(void)
{
- (void)imxrt_netinitialize(0);
+ imxrt_netinitialize(0);
}
#endif
diff --git a/arch/arm/src/imxrt/imxrt_idle.c b/arch/arm/src/imxrt/imxrt_idle.c
index 38620f7..0028633 100644
--- a/arch/arm/src/imxrt/imxrt_idle.c
+++ b/arch/arm/src/imxrt/imxrt_idle.c
@@ -108,7 +108,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
- (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+ pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@@ -132,7 +132,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
- (void)imxrt_pmstandby();
+ imxrt_pmstandby();
break;
default:
diff --git a/arch/arm/src/imxrt/imxrt_irq.c b/arch/arm/src/imxrt/imxrt_irq.c
index 60475b3..b3879b8 100644
--- a/arch/arm/src/imxrt/imxrt_irq.c
+++ b/arch/arm/src/imxrt/imxrt_irq.c
@@ -208,7 +208,7 @@ static void imxrt_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int imxrt_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -216,7 +216,7 @@ static int imxrt_nmi(int irq, FAR void *context, FAR void *arg)
static int imxrt_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
@@ -224,7 +224,7 @@ static int imxrt_busfault(int irq, FAR void *context, FAR void *arg)
static int imxrt_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
@@ -232,7 +232,7 @@ static int imxrt_usagefault(int irq, FAR void *context, FAR void *arg)
static int imxrt_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -240,7 +240,7 @@ static int imxrt_pendsv(int irq, FAR void *context, FAR void *arg)
static int imxrt_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -248,7 +248,7 @@ static int imxrt_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int imxrt_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/imxrt/imxrt_lowputc.c b/arch/arm/src/imxrt/imxrt_lowputc.c
index 7d88351..f49310b 100644
--- a/arch/arm/src/imxrt/imxrt_lowputc.c
+++ b/arch/arm/src/imxrt/imxrt_lowputc.c
@@ -230,14 +230,14 @@ void imxrt_lowsetup(void)
* control is enabled.
*/
- (void)imxrt_config_gpio(GPIO_LPUART1_RX);
- (void)imxrt_config_gpio(GPIO_LPUART1_TX);
+ imxrt_config_gpio(GPIO_LPUART1_RX);
+ imxrt_config_gpio(GPIO_LPUART1_TX);
#ifdef CONFIG_LPUART1_OFLOWCONTROL
- (void)imxrt_config_gpio(GPIO_LPUART1_CTS);
+ imxrt_config_gpio(GPIO_LPUART1_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
- (void)imxrt_config_gpio(GPIO_LPUART1_RTS);
+ imxrt_config_gpio(GPIO_LPUART1_RTS);
#endif
#endif
@@ -247,14 +247,14 @@ void imxrt_lowsetup(void)
* control is enabled.
*/
- (void)imxrt_config_gpio(GPIO_LPUART2_RX);
- (void)imxrt_config_gpio(GPIO_LPUART2_TX);
+ imxrt_config_gpio(GPIO_LPUART2_RX);
+ imxrt_config_gpio(GPIO_LPUART2_TX);
#ifdef CONFIG_LPUART2_OFLOWCONTROL
- (void)imxrt_config_gpio(GPIO_LPUART2_CTS);
+ imxrt_config_gpio(GPIO_LPUART2_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
- (void)imxrt_config_gpio(GPIO_LPUART2_RTS);
+ imxrt_config_gpio(GPIO_LPUART2_RTS);
#endif
#endif
@@ -264,14 +264,14 @@ void imxrt_lowsetup(void)
* control is enabled.
*/
- (void)imxrt_config_gpio(GPIO_LPUART3_RX);
- (void)imxrt_config_gpio(GPIO_LPUART3_TX);
+ imxrt_config_gpio(GPIO_LPUART3_RX);
+ imxrt_config_gpio(GPIO_LPUART3_TX);
#ifdef CONFIG_LPUART3_OFLOWCONTROL
- (void)imxrt_config_gpio(GPIO_LPUART3_CTS);
+ imxrt_config_gpio(GPIO_LPUART3_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
- (void)imxrt_config_gpio(GPIO_LPUART3_RTS);
+ imxrt_config_gpio(GPIO_LPUART3_RTS);
#endif
#endif
@@ -281,14 +281,14 @@ void imxrt_lowsetup(void)
* control is enabled.
*/
- (void)imxrt_config_gpio(GPIO_LPUART4_RX);
- (void)imxrt_config_gpio(GPIO_LPUART4_TX);
+ imxrt_config_gpio(GPIO_LPUART4_RX);
+ imxrt_config_gpio(GPIO_LPUART4_TX);
#ifdef CONFIG_LPUART4_OFLOWCONTROL
- (void)imxrt_config_gpio(GPIO_LPUART4_CTS);
+ imxrt_config_gpio(GPIO_LPUART4_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
- (void)imxrt_config_gpio(GPIO_LPUART4_RTS);
+ imxrt_config_gpio(GPIO_LPUART4_RTS);
#endif
#endif
@@ -298,14 +298,14 @@ void imxrt_lowsetup(void)
* control is enabled.
*/
- (void)imxrt_config_gpio(GPIO_LPUART5_RX);
- (void)imxrt_config_gpio(GPIO_LPUART5_TX);
+ imxrt_config_gpio(GPIO_LPUART5_RX);
+ imxrt_config_gpio(GPIO_LPUART5_TX);
#ifdef CONFIG_LPUART5_OFLOWCONTROL
- (void)imxrt_config_gpio(GPIO_LPUART5_CTS);
+ imxrt_config_gpio(GPIO_LPUART5_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
- (void)imxrt_config_gpio(GPIO_LPUART5_RTS);
+ imxrt_config_gpio(GPIO_LPUART5_RTS);
#endif
#endif
@@ -315,14 +315,14 @@ void imxrt_lowsetup(void)
* control is enabled.
*/
- (void)imxrt_config_gpio(GPIO_LPUART6_RX);
- (void)imxrt_config_gpio(GPIO_LPUART6_TX);
+ imxrt_config_gpio(GPIO_LPUART6_RX);
+ imxrt_config_gpio(GPIO_LPUART6_TX);
#ifdef CONFIG_LPUART6_OFLOWCONTROL
- (void)imxrt_config_gpio(GPIO_LPUART6_CTS);
+ imxrt_config_gpio(GPIO_LPUART6_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
- (void)imxrt_config_gpio(GPIO_LPUART6_RTS);
+ imxrt_config_gpio(GPIO_LPUART6_RTS);
#endif
#endif
@@ -332,14 +332,14 @@ void imxrt_lowsetup(void)
* control is enabled.
*/
- (void)imxrt_config_gpio(GPIO_LPUART7_RX);
- (void)imxrt_config_gpio(GPIO_LPUART7_TX);
+ imxrt_config_gpio(GPIO_LPUART7_RX);
+ imxrt_config_gpio(GPIO_LPUART7_TX);
#ifdef CONFIG_LPUART7_OFLOWCONTROL
- (void)imxrt_config_gpio(GPIO_LPUART7_CTS);
+ imxrt_config_gpio(GPIO_LPUART7_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
- (void)imxrt_config_gpio(GPIO_LPUART7_RTS);
+ imxrt_config_gpio(GPIO_LPUART7_RTS);
#endif
#endif
@@ -349,21 +349,21 @@ void imxrt_lowsetup(void)
* control is enabled.
*/
- (void)imxrt_config_gpio(GPIO_LPUART8_RX);
- (void)imxrt_config_gpio(GPIO_LPUART8_TX);
+ imxrt_config_gpio(GPIO_LPUART8_RX);
+ imxrt_config_gpio(GPIO_LPUART8_TX);
#ifdef CONFIG_LPUART8_OFLOWCONTROL
- (void)imxrt_config_gpio(GPIO_LPUART8_CTS);
+ imxrt_config_gpio(GPIO_LPUART8_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
- (void)imxrt_config_gpio(GPIO_LPUART8_RTS);
+ imxrt_config_gpio(GPIO_LPUART8_RTS);
#endif
#endif
#ifdef HAVE_LPUART_CONSOLE
/* Configure the serial console for initial, non-interrupt driver mode */
- (void)imxrt_lpuart_configure(IMXRT_CONSOLE_BASE, &g_console_config);
+ imxrt_lpuart_configure(IMXRT_CONSOLE_BASE, &g_console_config);
#endif
#endif /* HAVE_LPUART_DEVICE */
#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */
diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c
index 20c0f80..2209f82 100644
--- a/arch/arm/src/imxrt/imxrt_lpi2c.c
+++ b/arch/arm/src/imxrt/imxrt_lpi2c.c
@@ -518,21 +518,7 @@ static inline void imxrt_lpi2c_modifyreg(FAR struct imxrt_lpi2c_priv_s *priv,
static inline void imxrt_lpi2c_sem_wait(FAR struct imxrt_lpi2c_priv_s *priv)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->sem_excl);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->sem_excl);
}
/****************************************************************************
@@ -618,7 +604,7 @@ static inline int imxrt_lpi2c_sem_waitdone(FAR struct imxrt_lpi2c_priv_s *priv)
{
/* Get the current time */
- (void)clock_gettime(CLOCK_REALTIME, &abstime);
+ clock_gettime(CLOCK_REALTIME, &abstime);
/* Calculate a time in the future */
@@ -647,12 +633,11 @@ static inline int imxrt_lpi2c_sem_waitdone(FAR struct imxrt_lpi2c_priv_s *priv)
/* Wait until either the transfer is complete or the timeout expires */
- ret = nxsem_timedwait(&priv->sem_isr, &abstime);
- if (ret < 0 && ret != -EINTR)
+ ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime);
+ if (ret < 0)
{
/* Break out of the loop on irrecoverable errors. This would
* include timeouts and mystery errors reported by nxsem_timedwait.
- * NOTE that we try again if we are awakened by a signal (EINTR).
*/
break;
@@ -1378,7 +1363,7 @@ static int imxrt_lpi2c_isr_process(struct imxrt_lpi2c_priv_s *priv)
* and wake it up
*/
- sem_post(&priv->sem_isr);
+ nxsem_post(&priv->sem_isr);
priv->intstate = INTSTATE_DONE;
}
#else
@@ -1431,7 +1416,7 @@ static int imxrt_lpi2c_isr_process(struct imxrt_lpi2c_priv_s *priv)
* and wake it up
*/
- sem_post(&priv->sem_isr);
+ nxsem_post(&priv->sem_isr);
priv->intstate = INTSTATE_DONE;
}
#else
@@ -1531,8 +1516,8 @@ static int imxrt_lpi2c_init(FAR struct imxrt_lpi2c_priv_s *priv)
/* Configure pins */
- (void)imxrt_config_gpio(priv->config->scl_pin);
- (void)imxrt_config_gpio(priv->config->sda_pin);
+ imxrt_config_gpio(priv->config->scl_pin);
+ imxrt_config_gpio(priv->config->sda_pin);
/* Enable power and reset the peripheral */
diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c
index 341dd4f..b9e801d 100644
--- a/arch/arm/src/imxrt/imxrt_lpspi.c
+++ b/arch/arm/src/imxrt/imxrt_lpspi.c
@@ -857,24 +857,11 @@ static int imxrt_lpspi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -1577,9 +1564,9 @@ FAR struct spi_dev_s *imxrt_lpspibus_initialize(int bus)
{
/* Configure SPI1 pins: SCK, MISO, and MOSI */
- (void)imxrt_config_gpio(GPIO_LPSPI1_SCK);
- (void)imxrt_config_gpio(GPIO_LPSPI1_MISO);
- (void)imxrt_config_gpio(GPIO_LPSPI1_MOSI);
+ imxrt_config_gpio(GPIO_LPSPI1_SCK);
+ imxrt_config_gpio(GPIO_LPSPI1_MISO);
+ imxrt_config_gpio(GPIO_LPSPI1_MOSI);
/* Set up default configuration: Master, 8-bit, etc. */
@@ -1601,9 +1588,9 @@ FAR struct spi_dev_s *imxrt_lpspibus_initialize(int bus)
{
/* Configure SPI2 pins: SCK, MISO, and MOSI */
- (void)imxrt_config_gpio(GPIO_LPSPI2_SCK);
- (void)imxrt_config_gpio(GPIO_LPSPI2_MISO);
- (void)imxrt_config_gpio(GPIO_LPSPI2_MOSI);
+ imxrt_config_gpio(GPIO_LPSPI2_SCK);
+ imxrt_config_gpio(GPIO_LPSPI2_MISO);
+ imxrt_config_gpio(GPIO_LPSPI2_MOSI);
/* Set up default configuration: Master, 8-bit, etc. */
@@ -1625,9 +1612,9 @@ FAR struct spi_dev_s *imxrt_lpspibus_initialize(int bus)
{
/* Configure SPI3 pins: SCK, MISO, and MOSI */
- (void)imxrt_config_gpio(GPIO_LPSPI3_SCK);
- (void)imxrt_config_gpio(GPIO_LPSPI3_MISO);
- (void)imxrt_config_gpio(GPIO_LPSPI3_MOSI);
+ imxrt_config_gpio(GPIO_LPSPI3_SCK);
+ imxrt_config_gpio(GPIO_LPSPI3_MISO);
+ imxrt_config_gpio(GPIO_LPSPI3_MOSI);
/* Set up default configuration: Master, 8-bit, etc. */
@@ -1649,9 +1636,9 @@ FAR struct spi_dev_s *imxrt_lpspibus_initialize(int bus)
{
/* Configure SPI4 pins: SCK, MISO, and MOSI */
- (void)imxrt_config_gpio(GPIO_LPSPI4_SCK);
- (void)imxrt_config_gpio(GPIO_LPSPI4_MISO);
- (void)imxrt_config_gpio(GPIO_LPSPI4_MOSI);
+ imxrt_config_gpio(GPIO_LPSPI4_SCK);
+ imxrt_config_gpio(GPIO_LPSPI4_MISO);
+ imxrt_config_gpio(GPIO_LPSPI4_MOSI);
/* Set up default configuration: Master, 8-bit, etc. */
diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c
index aa2443d..9a5ed10 100644
--- a/arch/arm/src/imxrt/imxrt_serial.c
+++ b/arch/arm/src/imxrt/imxrt_serial.c
@@ -1682,32 +1682,32 @@ void up_serialinit(void)
#endif
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
- (void)uart_register("/dev/ttyS4", &TTYS4_DEV);
+ uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
#ifdef TTYS5_DEV
- (void)uart_register("/dev/ttyS5", &TTYS5_DEV);
+ uart_register("/dev/ttyS5", &TTYS5_DEV);
#endif
#ifdef TTYS6_DEV
- (void)uart_register("/dev/ttyS6", &TTYS6_DEV);
+ uart_register("/dev/ttyS6", &TTYS6_DEV);
#endif
#ifdef TTYS7_DEV
- (void)uart_register("/dev/ttyS7", &TTYS7_DEV);
+ uart_register("/dev/ttyS7", &TTYS7_DEV);
#endif
}
diff --git a/arch/arm/src/imxrt/imxrt_timerisr.c b/arch/arm/src/imxrt/imxrt_timerisr.c
index 616ca51..a62ded6 100644
--- a/arch/arm/src/imxrt/imxrt_timerisr.c
+++ b/arch/arm/src/imxrt/imxrt_timerisr.c
@@ -220,7 +220,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(IMXRT_IRQ_SYSTICK, (xcpt_t)imxrt_timerisr, NULL);
+ irq_attach(IMXRT_IRQ_SYSTICK, (xcpt_t)imxrt_timerisr, NULL);
/* Enable SysTick interrupts */
diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c
index 211635a..76e3bf8 100644
--- a/arch/arm/src/imxrt/imxrt_usdhc.c
+++ b/arch/arm/src/imxrt/imxrt_usdhc.c
@@ -517,21 +517,7 @@ static struct imxrt_sdhcregs_s g_sampleregs[DEBUG_NSAMPLES];
static void imxrt_takesem(struct imxrt_dev_s *priv)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->waitsem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->waitsem);
}
/****************************************************************************
@@ -1070,7 +1056,7 @@ static void imxrt_endwait(struct imxrt_dev_s *priv, sdio_eventset_t wkupevent)
{
/* Cancel the watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* Disable event-related interrupts */
@@ -2255,7 +2241,7 @@ static int imxrt_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@@ -2981,8 +2967,8 @@ static void imxrt_callback(void *arg)
/* Yes.. queue it */
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
- (void)work_queue(HPWORK, &priv->cbwork, (worker_t) priv->callback,
- priv->cbarg, 0);
+ work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback,
+ priv->cbarg, 0);
}
else
{
@@ -3088,24 +3074,24 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
#ifndef CONFIG_SDIO_MUXBUS
#if defined(CONFIG_IMXRT_USDHC1_WIDTH_D1_D4)
- (void)imxrt_config_gpio(PIN_USDHC1_D1);
- (void)imxrt_config_gpio(PIN_USDHC1_D2);
- (void)imxrt_config_gpio(PIN_USDHC1_D3);
+ imxrt_config_gpio(PIN_USDHC1_D1);
+ imxrt_config_gpio(PIN_USDHC1_D2);
+ imxrt_config_gpio(PIN_USDHC1_D3);
#endif
/* Clocking and CMD pins (all data widths) */
- (void)imxrt_config_gpio(PIN_USDHC1_D0);
- (void)imxrt_config_gpio(PIN_USDHC1_DCLK);
- (void)imxrt_config_gpio(PIN_USDHC1_CMD);
+ imxrt_config_gpio(PIN_USDHC1_D0);
+ imxrt_config_gpio(PIN_USDHC1_DCLK);
+ imxrt_config_gpio(PIN_USDHC1_CMD);
#endif
#if defined(CONFIG_MMCSD_HAVE_CARDDETECT)
# if defined(PIN_USDHC1_CD)
- (void)imxrt_config_gpio(PIN_USDHC1_CD);
+ imxrt_config_gpio(PIN_USDHC1_CD);
# else
if (priv->sw_cd_gpio != 0)
{
- (void)imxrt_config_gpio(priv->sw_cd_gpio);
+ imxrt_config_gpio(priv->sw_cd_gpio);
}
# endif
#endif
@@ -3115,30 +3101,30 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
#if defined(CONFIG_IMXRT_USDHC2)
case IMXRT_USDHC2_BASE:
- (void)imxrt_config_gpio(PIN_USDHC2_D0);
- (void)imxrt_config_gpio(PIN_USDHC2_DCLK);
- (void)imxrt_config_gpio(PIN_USDHC2_CMD);
+ imxrt_config_gpio(PIN_USDHC2_D0);
+ imxrt_config_gpio(PIN_USDHC2_DCLK);
+ imxrt_config_gpio(PIN_USDHC2_CMD);
# if defined(CONFIG_IMXRT_USDHC2_WIDTH_D1_D4) || defined(CONFIG_IMXRT_USDHC2_WIDTH_D1_D8)
- (void)imxrt_config_gpio(PIN_USDHC2_D1);
- (void)imxrt_config_gpio(PIN_USDHC2_D2);
- (void)imxrt_config_gpio(PIN_USDHC2_D3);
+ imxrt_config_gpio(PIN_USDHC2_D1);
+ imxrt_config_gpio(PIN_USDHC2_D2);
+ imxrt_config_gpio(PIN_USDHC2_D3);
# endif
# if defined(CONFIG_IMXRT_USDHC2_WIDTH_D1_D8)
- (void)imxrt_config_gpio(PIN_USDHC2_D4);
- (void)imxrt_config_gpio(PIN_USDHC2_D5);
- (void)imxrt_config_gpio(PIN_USDHC2_D6);
- (void)imxrt_config_gpio(PIN_USDHC2_D7);
+ imxrt_config_gpio(PIN_USDHC2_D4);
+ imxrt_config_gpio(PIN_USDHC2_D5);
+ imxrt_config_gpio(PIN_USDHC2_D6);
+ imxrt_config_gpio(PIN_USDHC2_D7);
# endif
# if defined(CONFIG_MMCSD_HAVE_CARDDETECT)
# if defined(PIN_USDHC2_CD)
- (void)imxrt_config_gpio(PIN_USDHC2_CD);
+ imxrt_config_gpio(PIN_USDHC2_CD);
# else
if (priv->sw_cd_gpio != 0)
{
- (void)imxrt_config_gpio(priv->sw_cd_gpio);
+ imxrt_config_gpio(priv->sw_cd_gpio);
}
# endif
# endif
diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c
index f90ac64..7f7d722 100644
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@@ -518,8 +518,8 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
- (void)wd_start(priv->txtimeout, KINETIS_TXTIMEOUT, kinetis_txtimeout_expiry,
- 1, (wdparm_t)priv);
+ wd_start(priv->txtimeout, KINETIS_TXTIMEOUT, kinetis_txtimeout_expiry,
+ 1, (wdparm_t)priv);
return OK;
}
@@ -831,7 +831,7 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
* new XMIT data
*/
- (void)devif_poll(&priv->dev, kinetis_txpoll);
+ devif_poll(&priv->dev, kinetis_txpoll);
}
/****************************************************************************
@@ -1001,12 +1001,12 @@ static void kinetis_txtimeout_work(FAR void *arg)
* hardware reset.
*/
- (void)kinetis_ifdown(&priv->dev);
- (void)kinetis_ifup(&priv->dev);
+ kinetis_ifdown(&priv->dev);
+ kinetis_ifup(&priv->dev);
/* Then poll the network for new XMIT data */
- (void)devif_poll(&priv->dev, kinetis_txpoll);
+ devif_poll(&priv->dev, kinetis_txpoll);
net_unlock();
}
@@ -1083,13 +1083,13 @@ static void kinetis_poll_work(FAR void *arg)
* in progress, we will missing TCP time state updates?
*/
- (void)devif_timer(&priv->dev, KINETIS_WDDELAY, kinetis_txpoll);
+ devif_timer(&priv->dev, KINETIS_WDDELAY, kinetis_txpoll);
}
/* Setup the watchdog poll timer again in any case */
- (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry,
- 1, (wdparm_t)priv);
+ wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry,
+ 1, (wdparm_t)priv);
net_unlock();
}
@@ -1231,8 +1231,8 @@ static int kinetis_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
- (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry, 1,
- (wdparm_t)priv);
+ wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry, 1,
+ (wdparm_t)priv);
/* Clear all pending ENET interrupt */
@@ -1347,7 +1347,7 @@ static void kinetis_txavail_work(FAR void *arg)
* XMIT data.
*/
- (void)devif_poll(&priv->dev, kinetis_txpoll);
+ devif_poll(&priv->dev, kinetis_txpoll);
}
}
@@ -2240,11 +2240,11 @@ int kinetis_netinitialize(int intf)
* the device and/or calling kinetis_ifdown().
*/
- (void)kinetis_ifdown(&priv->dev);
+ kinetis_ifdown(&priv->dev);
/* Register the device with the OS so that socket IOCTLs can be performed */
- (void)netdev_register(&priv->dev, NET_LL_ETHERNET);
+ netdev_register(&priv->dev, NET_LL_ETHERNET);
return OK;
}
@@ -2262,7 +2262,7 @@ int kinetis_netinitialize(int intf)
#if CONFIG_KINETIS_ENETNETHIFS == 1 && !defined(CONFIG_NETDEV_LATEINIT)
void up_netinitialize(void)
{
- (void)kinetis_netinitialize(0);
+ kinetis_netinitialize(0);
}
#endif
diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c
index 1e80fad..11ca2eb 100644
--- a/arch/arm/src/kinetis/kinetis_i2c.c
+++ b/arch/arm/src/kinetis/kinetis_i2c.c
@@ -350,21 +350,7 @@ static inline void kinetis_i2c_sem_destroy(FAR struct kinetis_i2cdev_s *priv)
static inline void kinetis_i2c_sem_wait(FAR struct kinetis_i2cdev_s *priv)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->mutex);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->mutex);
}
/****************************************************************************
@@ -390,7 +376,7 @@ static inline void kinetis_i2c_sem_post(struct kinetis_i2cdev_s *priv)
static inline void kinetis_i2c_wait(struct kinetis_i2cdev_s *priv)
{
- (void)nxsem_wait(&priv->wait);
+ nxsem_wait(&priv->wait);
}
/****************************************************************************
@@ -1207,8 +1193,8 @@ static int kinetis_i2c_transfer(struct i2c_master_s *dev,
/* Wait for transfer complete */
- (void)wd_start(priv->timeout, I2C_TIMEOUT, kinetis_i2c_timeout, 1,
- (uint32_t)priv);
+ wd_start(priv->timeout, I2C_TIMEOUT, kinetis_i2c_timeout, 1,
+ (uint32_t)priv);
kinetis_i2c_wait(priv);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c
index c1f3e30..3693dd8 100644
--- a/arch/arm/src/kinetis/kinetis_irq.c
+++ b/arch/arm/src/kinetis/kinetis_irq.c
@@ -173,7 +173,7 @@ static void kinetis_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int kinetis_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -181,7 +181,7 @@ static int kinetis_nmi(int irq, FAR void *context, FAR void *arg)
static int kinetis_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
@@ -189,7 +189,7 @@ static int kinetis_busfault(int irq, FAR void *context, FAR void *arg)
static int kinetis_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
@@ -197,7 +197,7 @@ static int kinetis_usagefault(int irq, FAR void *context, FAR void *arg)
static int kinetis_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -205,7 +205,7 @@ static int kinetis_pendsv(int irq, FAR void *context, FAR void *arg)
static int kinetis_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -213,7 +213,7 @@ static int kinetis_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int kinetis_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c
index 4690802..9c4d9dc 100644
--- a/arch/arm/src/kinetis/kinetis_lpserial.c
+++ b/arch/arm/src/kinetis/kinetis_lpserial.c
@@ -746,7 +746,7 @@ static int kinetis_interrupt(int irq, void *context, void *arg)
if ((stat & LPUART_STAT_OR) != LPUART_STAT_OR)
{
- (void) kinetis_serialin(priv, KINETIS_LPUART_DATA_OFFSET);
+ kinetis_serialin(priv, KINETIS_LPUART_DATA_OFFSET);
}
/* Reset any Errors */
@@ -1367,44 +1367,44 @@ unsigned int kinetis_lpuart_serialinit(unsigned int first)
/* Register the console */
#ifdef HAVE_LPUART_CONSOLE
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
#if !defined(CONFIG_KINETIS_MERGE_TTY)
/* Register all LPUARTs as LPn devices */
- (void)uart_register("/dev/ttyLP0", &TTYS0_DEV);
+ uart_register("/dev/ttyLP0", &TTYS0_DEV);
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyLP1", &TTYS1_DEV);
+ uart_register("/dev/ttyLP1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyLP2", &TTYS2_DEV);
+ uart_register("/dev/ttyLP2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyLP3", &TTYS3_DEV);
+ uart_register("/dev/ttyLP3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
- (void)uart_register("/dev/ttyLP4", &TTYS4_DEV);
+ uart_register("/dev/ttyLP4", &TTYS4_DEV);
#endif
#else
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS0_DEV);
+ uart_register(devname, &TTYS0_DEV);
#ifdef TTYS1_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS1_DEV);
+ uart_register(devname, &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS2_DEV);
+ uart_register(devname, &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS3_DEV);
+ uart_register(devname, &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS4_DEV);
+ uart_register(devname, &TTYS4_DEV);
#endif
#endif
diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c
index 5eed82f..e22840e 100644
--- a/arch/arm/src/kinetis/kinetis_pinirq.c
+++ b/arch/arm/src/kinetis/kinetis_pinirq.c
@@ -150,7 +150,7 @@ static int kinetis_portinterrupt(int irq, FAR void *context,
/* There is a registered interrupt handler... invoke it */
- (void)handler(irq, context, arg);
+ handler(irq, context, arg);
}
/* Writing a one to the ISFR register will clear the pending
@@ -225,27 +225,27 @@ static int kinetis_porteinterrupt(int irq, FAR void *context, FAR void *arg)
void kinetis_pinirqinitialize(void)
{
#ifdef CONFIG_KINETIS_PORTAINTS
- (void)irq_attach(KINETIS_IRQ_PORTA, kinetis_portainterrupt, NULL);
+ irq_attach(KINETIS_IRQ_PORTA, kinetis_portainterrupt, NULL);
putreg32(0xffffffff, KINETIS_PORTA_ISFR);
up_enable_irq(KINETIS_IRQ_PORTA);
#endif
#ifdef CONFIG_KINETIS_PORTBINTS
- (void)irq_attach(KINETIS_IRQ_PORTB, kinetis_portbinterrupt, NULL);
+ irq_attach(KINETIS_IRQ_PORTB, kinetis_portbinterrupt, NULL);
putreg32(0xffffffff, KINETIS_PORTB_ISFR);
up_enable_irq(KINETIS_IRQ_PORTB);
#endif
#ifdef CONFIG_KINETIS_PORTCINTS
- (void)irq_attach(KINETIS_IRQ_PORTC, kinetis_portcinterrupt, NULL);
+ irq_attach(KINETIS_IRQ_PORTC, kinetis_portcinterrupt, NULL);
putreg32(0xffffffff, KINETIS_PORTC_ISFR);
up_enable_irq(KINETIS_IRQ_PORTC);
#endif
#ifdef CONFIG_KINETIS_PORTDINTS
- (void)irq_attach(KINETIS_IRQ_PORTD, kinetis_portdinterrupt, NULL);
+ irq_attach(KINETIS_IRQ_PORTD, kinetis_portdinterrupt, NULL);
putreg32(0xffffffff, KINETIS_PORTD_ISFR);
up_enable_irq(KINETIS_IRQ_PORTD);
#endif
#ifdef CONFIG_KINETIS_PORTEINTS
- (void)irq_attach(KINETIS_IRQ_PORTE, kinetis_porteinterrupt, NULL);
+ irq_attach(KINETIS_IRQ_PORTE, kinetis_porteinterrupt, NULL);
putreg32(0xffffffff, KINETIS_PORTE_ISFR);
up_enable_irq(KINETIS_IRQ_PORTE);
#endif
diff --git a/arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c b/arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c
index ae42bc5..9fe1a90 100644
--- a/arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c
+++ b/arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c
@@ -431,7 +431,7 @@ static int kinetis_setrelative(FAR struct rtc_lowerhalf_s *lower,
/* And convert the time back to Julian/broken out format */
- (void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
+ gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
/* The set the alarm using this absolute time */
@@ -532,11 +532,11 @@ static int kinetis_rdalarm(FAR struct rtc_lowerhalf_s *lower,
ret = kinetis_rtc_rdalarm(&ts);
#ifdef CONFIG_LIBC_LOCALTIME
- (void)localtime_r((FAR const time_t *)&ts.tv_sec,
- (FAR struct tm *)alarminfo->time);
+ localtime_r((FAR const time_t *)&ts.tv_sec,
+ (FAR struct tm *)alarminfo->time);
#else
- (void)gmtime_r((FAR const time_t *)&ts.tv_sec,
- (FAR struct tm *)alarminfo->time);
+ gmtime_r((FAR const time_t *)&ts.tv_sec,
+ (FAR struct tm *)alarminfo->time);
#endif
sched_unlock();
}
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c
index 9820513..4ebcd4d 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -430,21 +430,7 @@ static struct kinetis_sdhcregs_s g_sampleregs[DEBUG_NSAMPLES];
static void kinetis_takesem(struct kinetis_dev_s *priv)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->waitsem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->waitsem);
}
/****************************************************************************
@@ -989,7 +975,7 @@ static void kinetis_endwait(struct kinetis_dev_s *priv, sdio_eventset_t wkupeven
{
/* Cancel the watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* Disable event-related interrupts */
@@ -2026,7 +2012,7 @@ static int kinetis_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@@ -2768,7 +2754,7 @@ static void kinetis_callback(void *arg)
/* Yes.. queue it */
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
- (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
+ work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c
index c9f4d94..b26eee2 100644
--- a/arch/arm/src/kinetis/kinetis_serial.c
+++ b/arch/arm/src/kinetis/kinetis_serial.c
@@ -881,7 +881,7 @@ static uint8_t get_and_clear_uart_status(struct up_dev_s *priv)
* discarding the data.
*/
- (void)up_serialin(priv, KINETIS_UART_D_OFFSET);
+ up_serialin(priv, KINETIS_UART_D_OFFSET);
}
return regval;
@@ -2032,7 +2032,7 @@ unsigned int kinetis_uart_serialinit(unsigned int first)
/* Register the console */
#ifdef HAVE_UART_CONSOLE
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
# ifdef SERIAL_HAVE_CONSOLE_DMA
/* If we need to re-initialise the console to enable DMA do that here. */
@@ -2044,26 +2044,26 @@ unsigned int kinetis_uart_serialinit(unsigned int first)
/* Register all UARTs */
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS0_DEV);
+ uart_register(devname, &TTYS0_DEV);
#ifdef TTYS1_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS1_DEV);
+ uart_register(devname, &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS2_DEV);
+ uart_register(devname, &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS3_DEV);
+ uart_register(devname, &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS4_DEV);
+ uart_register(devname, &TTYS4_DEV);
#endif
#ifdef TTYS5_DEV
devname[(sizeof(devname)/sizeof(devname[0]))-2] = '0' + first++;
- (void)uart_register(devname, &TTYS5_DEV);
+ uart_register(devname, &TTYS5_DEV);
#endif
return first;
}
diff --git a/arch/arm/src/kinetis/kinetis_spi.c b/arch/arm/src/kinetis/kinetis_spi.c
index 0768a31..4b0a75e 100644
--- a/arch/arm/src/kinetis/kinetis_spi.c
+++ b/arch/arm/src/kinetis/kinetis_spi.c
@@ -588,24 +588,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
diff --git a/arch/arm/src/kinetis/kinetis_timerisr.c b/arch/arm/src/kinetis/kinetis_timerisr.c
index 38cc865..41631ac 100644
--- a/arch/arm/src/kinetis/kinetis_timerisr.c
+++ b/arch/arm/src/kinetis/kinetis_timerisr.c
@@ -139,7 +139,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(KINETIS_IRQ_SYSTICK, (xcpt_t)kinetis_timerisr, NULL);
+ irq_attach(KINETIS_IRQ_SYSTICK, (xcpt_t)kinetis_timerisr, NULL);
/* Enable SysTick interrupts */
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
index 5ef6570..a6f7a49 100644
--- a/arch/arm/src/kinetis/kinetis_usbdev.c
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -1096,7 +1096,7 @@ static void khci_rqrestart(int argc, uint32_t arg1, ...)
#ifndef CONFIG_USBDEV_NOWRITEAHEAD
privreq->inflight[1] = 0;
#endif
- (void)khci_wrrequest(priv, privep);
+ khci_wrrequest(priv, privep);
}
}
}
@@ -1114,8 +1114,8 @@ static void khci_delayedrestart(struct khci_usbdev_s *priv, uint8_t epno)
/* And start (or re-start) the watchdog timer */
- (void)wd_start(priv->wdog, RESTART_DELAY, khci_rqrestart, 1,
- (uint32_t)priv);
+ wd_start(priv->wdog, RESTART_DELAY, khci_rqrestart, 1,
+ (uint32_t)priv);
}
/****************************************************************************
@@ -1366,7 +1366,7 @@ static int khci_wrrequest(struct khci_usbdev_s *priv, struct khci_ep_s *privep)
* queued
*/
- (void)khci_wrstart(priv, privep);
+ khci_wrstart(priv, privep);
}
#else
UNUSED(ret);
@@ -1840,7 +1840,7 @@ static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno,
{
/* If that succeeds, then try to set up another OUT transfer. */
- (void)khci_rdrequest(priv, privep);
+ khci_rdrequest(priv, privep);
}
#else
UNUSED(ret);
@@ -1860,7 +1860,7 @@ static void khci_eptransfer(struct khci_usbdev_s *priv, uint8_t epno,
/* Handle additional queued write requests */
- (void)khci_wrrequest(priv, privep);
+ khci_wrrequest(priv, privep);
}
}
@@ -2718,7 +2718,7 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat)
/* Stall EP0 */
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_EP0SETUPSTALLED), priv->ctrlstate);
- (void)khci_epstall(&priv->eplist[EP0].ep, false);
+ khci_epstall(&priv->eplist[EP0].ep, false);
}
}
@@ -3519,7 +3519,7 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!privep->stalled)
{
- (void)khci_wrrequest(priv, privep);
+ khci_wrrequest(priv, privep);
}
}
@@ -3538,7 +3538,7 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!privep->stalled)
{
- (void)khci_rdrequest(priv, privep);
+ khci_rdrequest(priv, privep);
}
}
@@ -3876,7 +3876,7 @@ static void khci_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
/* Disable the endpoint */
- (void)khci_epdisable(ep);
+ khci_epdisable(ep);
/* Mark the endpoint as available */
diff --git a/arch/arm/src/kl/kl_gpioirq.c b/arch/arm/src/kl/kl_gpioirq.c
index 6261065..38b105a 100644
--- a/arch/arm/src/kl/kl_gpioirq.c
+++ b/arch/arm/src/kl/kl_gpioirq.c
@@ -144,7 +144,7 @@ static int kl_portinterrupt(int irq, FAR void *context,
/* There is a registered interrupt handler... invoke it */
- (void)handler(irq, context, arg);
+ handler(irq, context, arg);
}
/* Writing a one to the ISFR register will clear the pending
@@ -202,13 +202,13 @@ static int kl_portdinterrupt(int irq, FAR void *context, FAR void *arg)
void kl_gpioirqinitialize(void)
{
#ifdef CONFIG_KL_PORTAINTS
- (void)irq_attach(KL_IRQ_PORTA, kl_portainterrupt, NULL);
+ irq_attach(KL_IRQ_PORTA, kl_portainterrupt, NULL);
putreg32(0xffffffff, KL_PORTA_ISFR);
up_enable_irq(KL_IRQ_PORTA);
#endif
#ifdef CONFIG_KL_PORTDINTS
- (void)irq_attach(KL_IRQ_PORTD, kl_portdinterrupt, NULL);
+ irq_attach(KL_IRQ_PORTD, kl_portdinterrupt, NULL);
putreg32(0xffffffff, KL_PORTD_ISFR);
up_enable_irq(KL_IRQ_PORTD);
#endif
diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c
index 7e83e47..01d2171 100644
--- a/arch/arm/src/kl/kl_idle.c
+++ b/arch/arm/src/kl/kl_idle.c
@@ -112,7 +112,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
- (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+ pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@@ -136,7 +136,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
- (void)kl_pmstandby();
+ kl_pmstandby();
break;
default:
diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c
index f8466ac..c27f41a 100644
--- a/arch/arm/src/kl/kl_irq.c
+++ b/arch/arm/src/kl/kl_irq.c
@@ -140,7 +140,7 @@ static void kl_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int kl_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -148,7 +148,7 @@ static int kl_nmi(int irq, FAR void *context, FAR void *arg)
static int kl_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -156,7 +156,7 @@ static int kl_pendsv(int irq, FAR void *context, FAR void *arg)
static int kl_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c
index 0b7d67d..7fa7afe 100644
--- a/arch/arm/src/kl/kl_serial.c
+++ b/arch/arm/src/kl/kl_serial.c
@@ -852,26 +852,26 @@ void up_serialinit(void)
/* Register the console */
#ifdef HAVE_SERIAL_CONSOLE
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
- (void)uart_register("/dev/ttyS4", &TTYS4_DEV);
+ uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
#ifdef TTYS5_DEV
- (void)uart_register("/dev/ttyS5", &TTYS5_DEV);
+ uart_register("/dev/ttyS5", &TTYS5_DEV);
#endif
}
diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c
index 09fd032..33baeff 100644
--- a/arch/arm/src/kl/kl_spi.c
+++ b/arch/arm/src/kl/kl_spi.c
@@ -241,24 +241,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
diff --git a/arch/arm/src/kl/kl_timerisr.c b/arch/arm/src/kl/kl_timerisr.c
index 09cd51d..11b2825 100644
--- a/arch/arm/src/kl/kl_timerisr.c
+++ b/arch/arm/src/kl/kl_timerisr.c
@@ -143,7 +143,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(KL_IRQ_SYSTICK, (xcpt_t)kl_timerisr, NULL);
+ irq_attach(KL_IRQ_SYSTICK, (xcpt_t)kl_timerisr, NULL);
/* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and
* Status register selects either the core clock (when CLKSOURCE = 1) or
diff --git a/arch/arm/src/lc823450/lc823450_adc.c b/arch/arm/src/lc823450/lc823450_adc.c
index 888bea2..518651d 100644
--- a/arch/arm/src/lc823450/lc823450_adc.c
+++ b/arch/arm/src/lc823450/lc823450_adc.c
@@ -226,9 +226,7 @@ static void lc823450_adc_start(FAR struct lc823450_adc_inst_s *inst)
uint8_t i;
uint32_t div;
-#ifndef CONFIG_ADC_POLLED
- int ret;
-#else
+#ifdef CONFIG_ADC_POLLED
irqstate_t flags;
flags = enter_critical_section();
@@ -263,19 +261,7 @@ static void lc823450_adc_start(FAR struct lc823450_adc_inst_s *inst)
while ((getreg32(rADCSTS) & rADCSTS_fADCMPL) == 0)
;
#else
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&inst->sem_isr);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&inst->sem_isr);
#endif
#ifdef CONFIG_ADC_POLLED
@@ -293,21 +279,7 @@ static void lc823450_adc_start(FAR struct lc823450_adc_inst_s *inst)
static inline void lc823450_adc_sem_wait(FAR struct lc823450_adc_inst_s *inst)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&inst->sem_excl);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&inst->sem_excl);
}
/****************************************************************************
diff --git a/arch/arm/src/lc823450/lc823450_cpuidlestack.c b/arch/arm/src/lc823450/lc823450_cpuidlestack.c
index 334b2c1..a75eb04 100644
--- a/arch/arm/src/lc823450/lc823450_cpuidlestack.c
+++ b/arch/arm/src/lc823450/lc823450_cpuidlestack.c
@@ -95,7 +95,7 @@
int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
{
#if CONFIG_SMP_NCPUS > 1
- (void)up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
+ up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
#endif
return OK;
}
diff --git a/arch/arm/src/lc823450/lc823450_cpustart.c b/arch/arm/src/lc823450/lc823450_cpustart.c
index e196ce0..4414f45 100644
--- a/arch/arm/src/lc823450/lc823450_cpustart.c
+++ b/arch/arm/src/lc823450/lc823450_cpustart.c
@@ -138,7 +138,7 @@ static void cpu1_boot(void)
/* Then transfer control to the IDLE task */
- (void)nx_idle_task(0, NULL);
+ nx_idle_task(0, NULL);
}
diff --git a/arch/arm/src/lc823450/lc823450_i2c.c b/arch/arm/src/lc823450/lc823450_i2c.c
index bf179e1..8d898d9 100644
--- a/arch/arm/src/lc823450/lc823450_i2c.c
+++ b/arch/arm/src/lc823450/lc823450_i2c.c
@@ -262,21 +262,7 @@ static struct lc823450_i2c_priv_s lc823450_i2c1_priv =
static inline void lc823450_i2c_sem_wait(FAR struct lc823450_i2c_priv_s *priv)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->sem_excl);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->sem_excl);
}
/****************************************************************************
@@ -310,7 +296,7 @@ static inline int lc823450_i2c_sem_waitdone(FAR struct lc823450_i2c_priv_s *priv
{
/* Get the current time */
- (void)clock_gettime(CLOCK_REALTIME, &abstime);
+ clock_gettime(CLOCK_REALTIME, &abstime);
/* Calculate a time in the future */
@@ -329,13 +315,12 @@ static inline int lc823450_i2c_sem_waitdone(FAR struct lc823450_i2c_priv_s *priv
/* Wait until either the transfer is complete or the timeout expires */
- ret = nxsem_timedwait(&priv->sem_isr, &abstime);
- if (ret < 0 && errno != -EINTR)
+ ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime);
+ if (ret < 0)
{
/* Break out of the loop on irrecoverable errors. This would
* include timeouts and mystery errors reported by nxsem_timedwait.
- * NOTE that we try again if we are awakened by a signal (EINTR).
*/
break;
}
@@ -1123,7 +1108,7 @@ FAR struct i2c_master_s *lc823450_i2cbus_initialize(int port)
#ifndef CONFIG_I2C_POLLED
nxsem_init(&priv->sem_isr, 0, 0);
#endif
- (void)lc823450_i2c_init(priv, port);
+ lc823450_i2c_init(priv, port);
}
leave_critical_section(flags);
diff --git a/arch/arm/src/lc823450/lc823450_i2s.c b/arch/arm/src/lc823450/lc823450_i2s.c
index bfa63d8..d55a61d 100644
--- a/arch/arm/src/lc823450/lc823450_i2s.c
+++ b/arch/arm/src/lc823450/lc823450_i2s.c
@@ -322,21 +322,7 @@ static void _setup_audio_pll(uint32_t freq)
static void _i2s_semtake(FAR sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -1010,7 +996,7 @@ FAR struct i2s_dev_s *lc823450_i2sdev_initialize(void)
priv->dev.ops = &g_i2sops;
- (void)lc823450_i2s_configure();
+ lc823450_i2s_configure();
#ifdef BEEP_TEST
lc823450_i2s_beeptest();
@@ -1039,11 +1025,11 @@ FAR struct i2s_dev_s *lc823450_i2sdev_initialize(void)
/* Backup the current affinity */
- (void)nxsched_getaffinity(getpid(), sizeof(cpuset0), &cpuset0);
+ nxsched_getaffinity(getpid(), sizeof(cpuset0), &cpuset0);
/* Set the new affinity which assigns to CPU0 */
- (void)nxsched_setaffinity(getpid(), sizeof(cpuset1), &cpuset1);
+ nxsched_setaffinity(getpid(), sizeof(cpuset1), &cpuset1);
nxsig_usleep(10 * 1000);
#endif
@@ -1056,7 +1042,7 @@ FAR struct i2s_dev_s *lc823450_i2sdev_initialize(void)
#ifdef CONFIG_SMP
/* Restore the original affinity */
- (void)nxsched_setaffinity(getpid(), sizeof(cpuset0), &cpuset0);
+ nxsched_setaffinity(getpid(), sizeof(cpuset0), &cpuset0);
nxsig_usleep(10 * 1000);
#endif
diff --git a/arch/arm/src/lc823450/lc823450_ipl2.c b/arch/arm/src/lc823450/lc823450_ipl2.c
index 8d528b9..715cee3 100644
--- a/arch/arm/src/lc823450/lc823450_ipl2.c
+++ b/arch/arm/src/lc823450/lc823450_ipl2.c
@@ -284,7 +284,7 @@ static void load_kernel(const char *name, const char *devname)
tmp = (void *)0x02040000;
- (void)blk_read(tmp, 512 * 1024, devname, 0);
+ blk_read(tmp, 512 * 1024, devname, 0);
/* disable all IRQ */
@@ -655,11 +655,11 @@ void check_lastkmsg(void)
/* log rotate */
- (void)unlink(LASTMSG_LOGPATH ".4");
- (void)rename(LASTMSG_LOGPATH ".3", LASTMSG_LOGPATH ".4");
- (void)rename(LASTMSG_LOGPATH ".2", LASTMSG_LOGPATH ".3");
- (void)rename(LASTMSG_LOGPATH ".1", LASTMSG_LOGPATH ".2");
- (void)rename(LASTMSG_LOGPATH ".0", LASTMSG_LOGPATH ".1");
+ unlink(LASTMSG_LOGPATH ".4");
+ rename(LASTMSG_LOGPATH ".3", LASTMSG_LOGPATH ".4");
+ rename(LASTMSG_LOGPATH ".2", LASTMSG_LOGPATH ".3");
+ rename(LASTMSG_LOGPATH ".1", LASTMSG_LOGPATH ".2");
+ rename(LASTMSG_LOGPATH ".0", LASTMSG_LOGPATH ".1");
fp = fopen(LASTMSG_LOGPATH ".0", "w");
diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c
index 33438d8..78a43a2 100644
--- a/arch/arm/src/lc823450/lc823450_irq.c
+++ b/arch/arm/src/lc823450/lc823450_irq.c
@@ -199,7 +199,7 @@ static void lc823450_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG
static int lc823450_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)enter_critical_section();
+ enter_critical_section();
irqinfo("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -207,7 +207,7 @@ static int lc823450_nmi(int irq, FAR void *context, FAR void *arg)
static int lc823450_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)enter_critical_section();
+ enter_critical_section();
irqinfo("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
@@ -215,7 +215,7 @@ static int lc823450_busfault(int irq, FAR void *context, FAR void *arg)
static int lc823450_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)enter_critical_section();
+ enter_critical_section();
irqinfo("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
@@ -223,7 +223,7 @@ static int lc823450_usagefault(int irq, FAR void *context, FAR void *arg)
static int lc823450_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)enter_critical_section();
+ enter_critical_section();
irqinfo("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -231,7 +231,7 @@ static int lc823450_pendsv(int irq, FAR void *context, FAR void *arg)
static int lc823450_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)enter_critical_section();
+ enter_critical_section();
irqinfo("PANIC!!! Debug Monitor receieved\n");
PANIC();
return 0;
@@ -239,7 +239,7 @@ static int lc823450_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int lc823450_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)enter_critical_section();
+ enter_critical_section();
irqinfo("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/lc823450/lc823450_mtd.c b/arch/arm/src/lc823450/lc823450_mtd.c
index f53448e..db4b499 100644
--- a/arch/arm/src/lc823450/lc823450_mtd.c
+++ b/arch/arm/src/lc823450/lc823450_mtd.c
@@ -140,21 +140,7 @@ static struct lc823450_partinfo_s partinfo[LC823450_NPARTS] =
static void mtd_semtake(FAR sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -490,7 +476,7 @@ get_card_size:
{
/* cache on */
- (void)lc823450_sdc_cachectl(dev->channel, 1);
+ lc823450_sdc_cachectl(dev->channel, 1);
}
finfo("ch=%d size=%lld \n", dev->channel, (uint64_t)blocksize * (uint64_t)nblocks);
diff --git a/arch/arm/src/lc823450/lc823450_procfs_dvfs.c b/arch/arm/src/lc823450/lc823450_procfs_dvfs.c
index e248c1a..9df85db 100644
--- a/arch/arm/src/lc823450/lc823450_procfs_dvfs.c
+++ b/arch/arm/src/lc823450/lc823450_procfs_dvfs.c
@@ -308,7 +308,7 @@ static ssize_t dvfs_write(FAR struct file *filep, FAR const char *buffer,
if (0 == strcmp(cmd, "cur_freq"))
{
tmp = atoi(line + (n + 1));
- (void)lc823450_dvfs_set_freq(tmp);
+ lc823450_dvfs_set_freq(tmp);
}
else if (0 == strcmp(cmd, "enable"))
{
diff --git a/arch/arm/src/lc823450/lc823450_rtc.c b/arch/arm/src/lc823450/lc823450_rtc.c
index 9876152..1ad62e9 100644
--- a/arch/arm/src/lc823450/lc823450_rtc.c
+++ b/arch/arm/src/lc823450/lc823450_rtc.c
@@ -216,7 +216,7 @@ static void rtc_pmnotify(struct pm_callback_s *cb, enum pm_state_e pmstate)
break;
}
- (void)up_rtc_getdatetime(&tm);
+ up_rtc_getdatetime(&tm);
up_rtc_set_default_datetime(&tm);
break;
@@ -728,8 +728,8 @@ void up_rtc_set_default_datetime(struct tm *tp)
return;
}
- (void)bchlib_write(handle, (void *)&rtc_def,
- CONFIG_RTC_SAVE_SECTOR_OFFSET * 512, sizeof(rtc_def));
+ bchlib_write(handle, (void *)&rtc_def,
+ CONFIG_RTC_SAVE_SECTOR_OFFSET * 512, sizeof(rtc_def));
bchlib_teardown(handle);
}
@@ -750,8 +750,8 @@ int up_rtc_get_default_datetime(struct tm *tp)
return -1;
}
- (void)bchlib_read(handle, (void *)&rtc_def,
- CONFIG_RTC_SAVE_SECTOR_OFFSET * 512, sizeof(rtc_def));
+ bchlib_read(handle, (void *)&rtc_def,
+ CONFIG_RTC_SAVE_SECTOR_OFFSET * 512, sizeof(rtc_def));
bchlib_teardown(handle);
if (rtc_def.sig != RTC_DEFAULT_SIGNATURE)
{
@@ -780,8 +780,8 @@ void up_rtc_clear_default(void)
}
memset(&rtc_def, 0, sizeof(rtc_def));
- (void)bchlib_write(handle, (void *)&rtc_def,
- CONFIG_RTC_SAVE_SECTOR_OFFSET * 512, sizeof(rtc_def));
+ bchlib_write(handle, (void *)&rtc_def,
+ CONFIG_RTC_SAVE_SECTOR_OFFSET * 512, sizeof(rtc_def));
bchlib_teardown(handle);
return;
}
diff --git a/arch/arm/src/lc823450/lc823450_sdc.c b/arch/arm/src/lc823450/lc823450_sdc.c
index e1b7277..4fa812a 100644
--- a/arch/arm/src/lc823450/lc823450_sdc.c
+++ b/arch/arm/src/lc823450/lc823450_sdc.c
@@ -138,21 +138,7 @@ extern SINT_T sddep_write(void *src, void *dst, UI_32 size, SINT_T type,
static void _sdc_semtake(FAR sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -189,12 +175,12 @@ static void lc823450_sdc_access_led(uint32_t ch, unsigned long sector)
{
if (sector >= CONFIG_MTD_CP_STARTBLOCK)
{
- (void)led_start_accled(false);
+ led_start_accled(false);
}
}
else
{
- (void)led_start_accled(false);
+ led_start_accled(false);
}
}
#else
@@ -657,7 +643,7 @@ int lc823450_sdc_locked(void)
for (i = 0; i < 2; i++)
{
- (void)nxsem_getvalue(&_sdc_sem[i], &val);
+ nxsem_getvalue(&_sdc_sem[i], &val);
if (1 != val)
{
ret = 1;
diff --git a/arch/arm/src/lc823450/lc823450_sddrv_dep.c b/arch/arm/src/lc823450/lc823450_sddrv_dep.c
index 7ead22c..06b27b3 100644
--- a/arch/arm/src/lc823450/lc823450_sddrv_dep.c
+++ b/arch/arm/src/lc823450/lc823450_sddrv_dep.c
@@ -134,21 +134,7 @@ static void dma_callback(DMA_HANDLE hdma, void *arg, int result)
static void _sddep_semtake(FAR sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -390,7 +376,7 @@ SINT_T sddep_wait_status(UI_32 req_status, UI_32 *status,
ret = -100;
break;
}
- (void)sched_yield();
+ sched_yield();
}
return ret;
diff --git a/arch/arm/src/lc823450/lc823450_serial.c b/arch/arm/src/lc823450/lc823450_serial.c
index 0277e40..a518ea7 100644
--- a/arch/arm/src/lc823450/lc823450_serial.c
+++ b/arch/arm/src/lc823450/lc823450_serial.c
@@ -1312,13 +1312,13 @@ void up_serialinit(void)
{
/* Register the console */
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
/* Register all UARTs */
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#ifdef CONFIG_HSUART
nxsem_init(&g_uart1priv.txdma_wait, 0, 1);
g_uart1priv.htxdma = lc823450_dmachannel(DMA_CHANNEL_UART1TX);
@@ -1330,11 +1330,11 @@ void up_serialinit(void)
lc823450_dmarequest(g_uart1priv.hrxdma, DMA_REQUEST_UART1RX);
up_serialout(&g_uart1priv, UART_UDMA, UART_UDMA_RREQ_EN | UART_UDMA_TREQ_EN);
- (void)hsuart_register("/dev/ttyHS1", &TTYS1_DEV);
+ hsuart_register("/dev/ttyHS1", &TTYS1_DEV);
#endif /* CONFIG_HSUART */
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
}
diff --git a/arch/arm/src/lc823450/lc823450_spi.c b/arch/arm/src/lc823450/lc823450_spi.c
index bdbed7c..df0aff7 100644
--- a/arch/arm/src/lc823450/lc823450_spi.c
+++ b/arch/arm/src/lc823450/lc823450_spi.c
@@ -153,24 +153,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -444,14 +431,14 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
{
for (i = 0; i < nwords; i++)
{
- (void)spi_send(dev, *buf16++);
+ spi_send(dev, *buf16++);
}
}
else
{
for (i = 0; i < nwords; i++)
{
- (void)spi_send(dev, *buf++);
+ spi_send(dev, *buf++);
}
}
#endif /* CONFIG_LC823450_SPI_DMA */
diff --git a/arch/arm/src/lc823450/lc823450_start.c b/arch/arm/src/lc823450/lc823450_start.c
index eb7e8d4..bdf2042 100644
--- a/arch/arm/src/lc823450/lc823450_start.c
+++ b/arch/arm/src/lc823450/lc823450_start.c
@@ -394,7 +394,7 @@ void __start(void)
showprogress('\r');
showprogress('\n');
- (void)get_cpu_ver();
+ get_cpu_ver();
/* run as interrupt context, before scheduler running */
diff --git a/arch/arm/src/lc823450/lc823450_timer.c b/arch/arm/src/lc823450/lc823450_timer.c
index 577a66d..188c766 100644
--- a/arch/arm/src/lc823450/lc823450_timer.c
+++ b/arch/arm/src/lc823450/lc823450_timer.c
@@ -500,7 +500,7 @@ void arm_timer_initialize(void)
modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0);
modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0);
- (void)irq_attach(LC823450_IRQ_MTIMER20, (xcpt_t)hrt_interrupt, NULL);
+ irq_attach(LC823450_IRQ_MTIMER20, (xcpt_t)hrt_interrupt, NULL);
up_enable_irq(LC823450_IRQ_MTIMER20);
#endif /* CONFIG_HRT_TIMER */
@@ -540,7 +540,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(LC823450_IRQ_MTIMER30, (xcpt_t)up_proftimerisr, NULL);
+ irq_attach(LC823450_IRQ_MTIMER30, (xcpt_t)up_proftimerisr, NULL);
/* And enable the system timer interrupt */
@@ -584,7 +584,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(LC823450_IRQ_MTIMER00, (xcpt_t)up_timerisr, NULL);
+ irq_attach(LC823450_IRQ_MTIMER00, (xcpt_t)up_timerisr, NULL);
/* And enable the system timer interrupt */
@@ -617,7 +617,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(LC823450_IRQ_SYSTICK, (xcpt_t)up_timerisr, NULL);
+ irq_attach(LC823450_IRQ_SYSTICK, (xcpt_t)up_timerisr, NULL);
/* Enable SysTick interrupts */
@@ -634,7 +634,7 @@ void arm_timer_initialize(void)
#ifdef CONFIG_DVFS
/* attach timer interrupt handler */
- (void)irq_attach(LC823450_IRQ_MTIMER01, (xcpt_t)lc823450_dvfs_oneshot, NULL);
+ irq_attach(LC823450_IRQ_MTIMER01, (xcpt_t)lc823450_dvfs_oneshot, NULL);
/* enable MTM0-ch1 */
diff --git a/arch/arm/src/lc823450/lc823450_usbdev.c b/arch/arm/src/lc823450/lc823450_usbdev.c
index 2e5c7dc..ef26dab 100644
--- a/arch/arm/src/lc823450/lc823450_usbdev.c
+++ b/arch/arm/src/lc823450/lc823450_usbdev.c
@@ -1821,7 +1821,7 @@ int usbdev_msc_epwrite(void *buf, int len)
USB_DMAC_START,
USB_DMAC1);
- (void)nxsem_wait(&dma_wait);
+ nxsem_wait(&dma_wait);
return 0;
}
@@ -1925,7 +1925,7 @@ int usbdev_msc_epread(void *buf, int len)
CONFIG_USBMSC_EPBULKOUT << USB_DMAC_DMAEP_SHIFT |
USB_DMAC_START,
USB_DMAC1);
- (void)nxsem_wait(&dma_wait);
+ nxsem_wait(&dma_wait);
return 0;
}
diff --git a/arch/arm/src/lc823450/lc823450_wdt.c b/arch/arm/src/lc823450/lc823450_wdt.c
index c1ef03a..05d813e 100644
--- a/arch/arm/src/lc823450/lc823450_wdt.c
+++ b/arch/arm/src/lc823450/lc823450_wdt.c
@@ -546,7 +546,7 @@ int lc823450_wdt_initialize(void)
#ifdef CONFIG_LC823450_WDT_INTERRUPT
/* Attach our WDT interrupt handler (But don't enable it yet) */
- (void)irq_attach(LC823450_IRQ_WDT0, lc823450_wdt_interrupt, NULL);
+ irq_attach(LC823450_IRQ_WDT0, lc823450_wdt_interrupt, NULL);
#else
if (getreg32(WDT_WT0RSTS) & (1 << WDT_WT0RSTS_RSTS))
{
@@ -556,8 +556,8 @@ int lc823450_wdt_initialize(void)
/* Register the watchdog driver as /dev/watchdog0 */
- (void)watchdog_register("/dev/watchdog0",
- (FAR struct watchdog_lowerhalf_s *)priv);
+ watchdog_register("/dev/watchdog0",
+ (FAR struct watchdog_lowerhalf_s *)priv);
return OK;
}
diff --git a/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c
index 4cf6b4e..f614f51 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc176x_gpio.c
@@ -448,7 +448,7 @@ static inline int lpc17_40_configinterrupt(lpc17_40_pinset_t cfgset, unsigned in
* starting point and consistent behavior during the re-configuration.
*/
- (void)lpc17_40_configinput(cfgset, port, pin);
+ lpc17_40_configinput(cfgset, port, pin);
/* Then just remember the rising/falling edge interrupt enabled */
@@ -477,7 +477,7 @@ static inline int lpc17_40_configoutput(lpc17_40_pinset_t cfgset, unsigned int p
* starting point and consistent behavior during the re-configuration.
*/
- (void)lpc17_40_configinput(DEFAULT_INPUT, port, pin);
+ lpc17_40_configinput(DEFAULT_INPUT, port, pin);
/* Check for open drain output */
@@ -525,7 +525,7 @@ static int lpc17_40_configalternate(lpc17_40_pinset_t cfgset, unsigned int port,
* starting point and consistent behavior during the re-configuration.
*/
- (void)lpc17_40_configinput(DEFAULT_INPUT, port, pin);
+ lpc17_40_configinput(DEFAULT_INPUT, port, pin);
/* Set up PINSEL registers */
/* Configure as GPIO */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c b/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c
index b56d73c..6a7282e 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc176x_rtc.c
@@ -362,7 +362,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
/* Break out the time values (not that the time is set only to units of seconds) */
- (void)gmtime_r(&tp->tv_sec, &newtime);
+ gmtime_r(&tp->tv_sec, &newtime);
rtc_dumptime(&newtime, "Setting time");
/* Then write the broken out values to the RTC */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c
index be114ca..600b6f7 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc178x_40xx_gpio.c
@@ -651,7 +651,7 @@ static inline int lpc17_40_configinterrupt(lpc17_40_pinset_t cfgset, unsigned in
* starting point and consistent behavior during the re-configuration.
*/
- (void)lpc17_40_configinput(cfgset, port, pin);
+ lpc17_40_configinput(cfgset, port, pin);
/* Then just remember the rising/falling edge interrupt enabled */
@@ -680,7 +680,7 @@ static inline int lpc17_40_configoutput(lpc17_40_pinset_t cfgset, unsigned int p
* starting point and consistent behavior during the re-configuration.
*/
- (void)lpc17_40_configinput(DEFAULT_INPUT, port, pin);
+ lpc17_40_configinput(DEFAULT_INPUT, port, pin);
/* Now, reconfigure the pin as an output */
@@ -733,7 +733,7 @@ static int lpc17_40_configalternate(lpc17_40_pinset_t cfgset, unsigned int port,
* starting point and consistent behavior during the re-configuration.
*/
- (void)lpc17_40_configinput(DEFAULT_INPUT, port, pin);
+ lpc17_40_configinput(DEFAULT_INPUT, port, pin);
/* Set pull-up mode */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c
index 6e8f02d..91321dd 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c
@@ -700,8 +700,8 @@ static int lpc17_40_transmit(struct lpc17_40_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
- (void)wd_start(priv->lp_txtimeout, LPC17_40_TXTIMEOUT,
- lpc17_40_txtimeout_expiry, 1, (uint32_t)priv);
+ wd_start(priv->lp_txtimeout, LPC17_40_TXTIMEOUT,
+ lpc17_40_txtimeout_expiry, 1, (uint32_t)priv);
return OK;
}
@@ -1152,7 +1152,7 @@ static void lpc17_40_txdone_work(FAR void *arg)
else
{
- (void)devif_poll(&priv->lp_dev, lpc17_40_txpoll);
+ devif_poll(&priv->lp_dev, lpc17_40_txpoll);
}
net_unlock();
@@ -1234,7 +1234,7 @@ static int lpc17_40_interrupt(int irq, void *context, FAR void *arg)
/* ifup() will reset the EMAC and bring it back up */
- (void)lpc17_40_ifup(&priv->lp_dev);
+ lpc17_40_ifup(&priv->lp_dev);
}
else
{
@@ -1393,11 +1393,11 @@ static void lpc17_40_txtimeout_work(FAR void *arg)
* it back up.
*/
- (void)lpc17_40_ifup(&priv->lp_dev);
+ lpc17_40_ifup(&priv->lp_dev);
/* Then poll the network layer for new XMIT data */
- (void)devif_poll(&priv->lp_dev, lpc17_40_txpoll);
+ devif_poll(&priv->lp_dev, lpc17_40_txpoll);
}
net_unlock();
@@ -1480,7 +1480,7 @@ static void lpc17_40_poll_work(FAR void *arg)
* transmit in progress, we will missing TCP time state updates?
*/
- (void)devif_timer(&priv->lp_dev, LPC17_40_WDDELAY, lpc17_40_txpoll);
+ devif_timer(&priv->lp_dev, LPC17_40_WDDELAY, lpc17_40_txpoll);
}
/* Simulate a fake receive to relaunch the data exchanges when a receive
@@ -1500,8 +1500,8 @@ static void lpc17_40_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
- (void)wd_start(priv->lp_txpoll, LPC17_40_WDDELAY, lpc17_40_poll_expiry,
- 1, priv);
+ wd_start(priv->lp_txpoll, LPC17_40_WDDELAY, lpc17_40_poll_expiry,
+ 1, priv);
net_unlock();
}
@@ -1584,7 +1584,7 @@ static void lpc17_40_ipv6multicast(FAR struct lpc17_40_driver_s *priv)
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- (void)lpc17_40_addmac(dev, mac);
+ lpc17_40_addmac(dev, mac);
#ifdef CONFIG_NET_ICMPv6_AUTOCONF
/* Add the IPv6 all link-local nodes Ethernet address. This is the
@@ -1592,7 +1592,7 @@ static void lpc17_40_ipv6multicast(FAR struct lpc17_40_driver_s *priv)
* packets.
*/
- (void)lpc17_40_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
+ lpc17_40_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
#endif /* CONFIG_NET_ICMPv6_AUTOCONF */
#ifdef CONFIG_NET_ICMPv6_ROUTER
@@ -1601,7 +1601,7 @@ static void lpc17_40_ipv6multicast(FAR struct lpc17_40_driver_s *priv)
* packets.
*/
- (void)lpc17_40_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
+ lpc17_40_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
#endif /* CONFIG_NET_ICMPv6_ROUTER */
}
@@ -1752,8 +1752,8 @@ static int lpc17_40_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
- (void)wd_start(priv->lp_txpoll, LPC17_40_WDDELAY, lpc17_40_poll_expiry, 1,
- (uint32_t)priv);
+ wd_start(priv->lp_txpoll, LPC17_40_WDDELAY, lpc17_40_poll_expiry, 1,
+ (uint32_t)priv);
/* Finally, make the interface up and enable the Ethernet interrupt at
* the interrupt controller
@@ -1839,7 +1839,7 @@ static void lpc17_40_txavail_work(FAR void *arg)
{
/* If so, then poll the network layer for new XMIT data */
- (void)devif_poll(&priv->lp_dev, lpc17_40_txpoll);
+ devif_poll(&priv->lp_dev, lpc17_40_txpoll);
}
}
@@ -3258,7 +3258,7 @@ static inline int lpc17_40_ethinitialize(int intf)
for (i = 0; i < GPIO_NENET_PINS; i++)
{
- (void)lpc17_40_configgpio(g_enetpins[i]);
+ lpc17_40_configgpio(g_enetpins[i]);
}
lpc17_40_showpins();
@@ -3317,7 +3317,7 @@ static inline int lpc17_40_ethinitialize(int intf)
/* Register the device with the OS so that socket IOCTLs can be performed */
- (void)netdev_register(&priv->lp_dev, NET_LL_ETHERNET);
+ netdev_register(&priv->lp_dev, NET_LL_ETHERNET);
return OK;
}
@@ -3335,7 +3335,7 @@ static inline int lpc17_40_ethinitialize(int intf)
#if CONFIG_LPC17_40_NINTERFACES == 1 && !defined(CONFIG_NETDEV_LATEINIT)
void up_netinitialize(void)
{
- (void)lpc17_40_ethinitialize(0);
+ lpc17_40_ethinitialize(0);
}
#endif
#endif /* LPC17_40_NETHCONTROLLERS > 0 */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
index 45b0980..0651bc6 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
@@ -389,17 +389,11 @@ void lpc17_40_dmaconfigure(uint8_t dmarequest, bool alternate)
DMA_HANDLE lpc17_40_dmachannel(void)
{
struct lpc17_40_dmach_s *dmach = NULL;
- int ret;
int i;
/* Get exclusive access to the GPDMA state structure */
- do
- {
- ret = nxsem_wait(&g_gpdma.exclsem);
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&g_gpdma.exclsem);
/* Find an available DMA channel */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c
index d621052..0b51bd9 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_gpioint.c
@@ -468,7 +468,7 @@ void lpc17_40_gpioirqinitialize(void)
* position in the NVIC with External Interrupt 3
*/
- (void)irq_attach(LPC17_40_IRQ_EINT3, lpc17_40_gpiointerrupt, NULL);
+ irq_attach(LPC17_40_IRQ_EINT3, lpc17_40_gpiointerrupt, NULL);
up_enable_irq(LPC17_40_IRQ_EINT3);
#elif defined(LPC178x_40xx)
@@ -476,7 +476,7 @@ void lpc17_40_gpioirqinitialize(void)
* GPIO2.
*/
- (void)irq_attach(LPC17_40_IRQ_GPIO, lpc17_40_gpiointerrupt, NULL);
+ irq_attach(LPC17_40_IRQ_GPIO, lpc17_40_gpiointerrupt, NULL);
up_enable_irq(LPC17_40_IRQ_GPIO);
#endif
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
index ba25a6a..c59fda0 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
@@ -238,8 +238,8 @@ static int lpc17_40_i2c_start(struct lpc17_40_i2cdev_s *priv)
priv->state = 0x00;
- (void)wd_start(priv->timeout, timeout, lpc17_40_i2c_timeout, 1,
- (uint32_t)priv);
+ wd_start(priv->timeout, timeout, lpc17_40_i2c_timeout, 1,
+ (uint32_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c
index a82cbcf..474826d 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_irq.c
@@ -152,7 +152,7 @@ static void lpc17_40_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int lpc17_40_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -160,7 +160,7 @@ static int lpc17_40_nmi(int irq, FAR void *context, FAR void *arg)
static int lpc17_40_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
@@ -168,7 +168,7 @@ static int lpc17_40_busfault(int irq, FAR void *context, FAR void *arg)
static int lpc17_40_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
@@ -176,7 +176,7 @@ static int lpc17_40_usagefault(int irq, FAR void *context, FAR void *arg)
static int lpc17_40_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -184,7 +184,7 @@ static int lpc17_40_pendsv(int irq, FAR void *context, FAR void *arg)
static int lpc17_40_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -192,7 +192,7 @@ static int lpc17_40_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int lpc17_40_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
index 03e084e..9bcd260 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
@@ -485,21 +485,7 @@ static struct lpc17_40_sampleregs_s g_sampleregs[DEBUG_NSAMPLES];
static void lpc17_40_takesem(struct lpc17_40_dev_s *priv)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(&priv->waitsem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(&priv->waitsem);
}
/****************************************************************************
@@ -1117,7 +1103,7 @@ static void lpc17_40_endwait(struct lpc17_40_dev_s *priv, sdio_eventset_t wkupev
{
/* Cancel the watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* Disable event-related interrupts */
@@ -1882,7 +1868,7 @@ static int lpc17_40_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@@ -2655,7 +2641,7 @@ static void lpc17_40_callback(void *arg)
/* Yes.. queue it */
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
- (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
+ work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c
index 7b3c920..c0b6e0a 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c
@@ -1487,19 +1487,19 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#endif
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
}
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
index 992ebeb..76f5cbb 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
@@ -187,24 +187,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -408,7 +395,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(LPC17_40_SPI_SR);
+ getreg32(LPC17_40_SPI_SR);
return (uint16_t)getreg32(LPC17_40_SPI_DR);
}
@@ -453,7 +440,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(LPC17_40_SPI_SR);
+ getreg32(LPC17_40_SPI_SR);
nwords--;
}
}
@@ -499,7 +486,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(LPC17_40_SPI_SR);
+ getreg32(LPC17_40_SPI_SR);
/* Read the received data from the SPI Data Register */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
index b0331c8..f6ab07c 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
@@ -334,24 +334,11 @@ static int ssp_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -670,7 +657,7 @@ static void ssp_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
{
/* Yes.. Read and discard */
- (void)ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET);
+ ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET);
}
/* There is a race condition where TFE may go true just before
@@ -996,7 +983,7 @@ FAR struct spi_dev_s *lpc17_40_sspbus_initialize(int port)
ssp_putreg(priv, LPC17_40_SSP_CR1_OFFSET, regval | SSP_CR1_SSE);
for (i = 0; i < LPC17_40_SSP_FIFOSZ; i++)
{
- (void)ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET);
+ ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET);
}
return &priv->spidev;
@@ -1038,7 +1025,7 @@ void ssp_flush(FAR struct spi_dev_s *dev)
do
{
- (void)ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET);
+ ssp_getreg(priv, LPC17_40_SSP_DR_OFFSET);
}
while (ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_RNE);
}
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c
index 9b1d9c3..ff9faa1 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_timerisr.c
@@ -135,7 +135,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(LPC17_40_IRQ_SYSTICK, (xcpt_t)lpc17_40_timerisr, NULL);
+ irq_attach(LPC17_40_IRQ_SYSTICK, (xcpt_t)lpc17_40_timerisr, NULL);
/* Enable SysTick interrupts */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c
index 9bd22b4..fe7b6a4 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c
@@ -896,8 +896,8 @@ static void lpc17_40_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes
/* Done */
lpc17_40_putreg(0, LPC17_40_USBDEV_CTRL);
- (void)lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0);
- (void)lpc17_40_usbcmd(CMD_USBDEV_EPVALIDATEBUFFER, 0);
+ lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0);
+ lpc17_40_usbcmd(CMD_USBDEV_EPVALIDATEBUFFER, 0);
}
/****************************************************************************
@@ -969,7 +969,7 @@ static int lpc17_40_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes)
/* Done */
lpc17_40_putreg(0, LPC17_40_USBDEV_CTRL);
- (void)lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0);
+ lpc17_40_usbcmd(CMD_USBDEV_EPSELECT | epphy, 0);
result = lpc17_40_usbcmd(CMD_USBDEV_EPCLRBUFFER, 0);
/* The packet overrun bit in the clear buffer response is applicable only
@@ -1719,7 +1719,7 @@ static inline void lpc17_40_ep0setup(struct lpc17_40_usbdev_s *priv)
(privep = lpc17_40_epfindbyaddr(priv, index)) != NULL)
{
privep->halted = 0;
- (void)lpc17_40_epstall(&privep->ep, true);
+ lpc17_40_epstall(&privep->ep, true);
lpc17_40_epwrite(LPC17_40_EP0_IN, NULL, 0);
priv->ep0state = LPC17_40_EP0STATUSIN;
}
@@ -2268,7 +2268,7 @@ static int lpc17_40_usbinterrupt(int irq, FAR void *context, FAR void *arg)
/* Clear the endpoint interrupt */
usbtrace(TRACE_INTDECODE(LPC17_40_TRACEINTID_EP0IN), priv->ep0state);
- (void)lpc17_40_epclrinterrupt(LPC17_40_CTRLEP_IN);
+ lpc17_40_epclrinterrupt(LPC17_40_CTRLEP_IN);
lpc17_40_ep0dataininterrupt(priv);
}
pending >>= 2;
@@ -2283,7 +2283,7 @@ static int lpc17_40_usbinterrupt(int irq, FAR void *context, FAR void *arg)
{
/* Yes.. clear the endpoint interrupt */
- (void)lpc17_40_epclrinterrupt(epphy);
+ lpc17_40_epclrinterrupt(epphy);
/* Get the endpoint sructure corresponding to the physical
* endpoint number.
@@ -2926,7 +2926,7 @@ static int lpc17_40_epstall(FAR struct usbdev_ep_s *ep, bool resume)
if (resume)
{
- (void)lpc17_40_wrrequest(privep);
+ lpc17_40_wrrequest(privep);
}
leave_critical_section(flags);
return OK;
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
index b2350d6..682c170 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
@@ -584,21 +584,7 @@ static void lpc17_40_putreg(uint32_t val, uint32_t addr)
static void lpc17_40_takesem(sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -2058,7 +2044,7 @@ static int lpc17_40_rh_enumerate(struct usbhost_connection_s *conn,
/* USB 2.0 spec says at least 50ms delay before port reset */
- (void)nxsig_usleep(100*1000);
+ nxsig_usleep(100*1000);
/* Put RH port 1 in reset (the LPC176x supports only a single downstream port) */
@@ -2071,7 +2057,7 @@ static int lpc17_40_rh_enumerate(struct usbhost_connection_s *conn,
/* Release RH port 1 from reset and wait a bit */
lpc17_40_putreg(OHCI_RHPORTST_PRSC, LPC17_40_USBHOST_RHPORTST1);
- (void)nxsig_usleep(200*1000);
+ nxsig_usleep(200*1000);
return OK;
}
diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c
index 719bc38..af29938 100644
--- a/arch/arm/src/lpc214x/lpc214x_serial.c
+++ b/arch/arm/src/lpc214x/lpc214x_serial.c
@@ -773,9 +773,9 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
- (void)uart_register("/dev/console", &CONSOLE_DEV);
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
}
/****************************************************************************
diff --git a/arch/arm/src/lpc214x/lpc214x_timerisr.c b/arch/arm/src/lpc214x/lpc214x_timerisr.c
index a129302..aa945f3 100644
--- a/arch/arm/src/lpc214x/lpc214x_timerisr.c
+++ b/arch/arm/src/lpc214x/lpc214x_timerisr.c
@@ -157,7 +157,7 @@ void arm_timer_initialize(void)
up_attach_vector(LPC214X_IRQ_SYSTIMER, LPC214X_SYSTIMER_VEC,
(vic_vector_t)lpc214x_timerisr);
#else
- (void)irq_attach(LPC214X_IRQ_SYSTIMER, (xcpt_t)lpc214x_timerisr, NULL);
+ irq_attach(LPC214X_IRQ_SYSTIMER, (xcpt_t)lpc214x_timerisr, NULL);
#endif
/* And enable the timer interrupt */
diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c
index c39324d..c34021a 100644
--- a/arch/arm/src/lpc214x/lpc214x_usbdev.c
+++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c
@@ -838,8 +838,8 @@ static void lpc214x_epwrite(uint8_t epphy, const uint8_t *data, uint32_t nbytes)
/* Done */
lpc214x_putreg(0, LPC214X_USBDEV_CTRL);
- (void)lpc214x_usbcmd(CMD_USB_EP_SELECT | epphy, 0);
- (void)lpc214x_usbcmd(CMD_USB_EP_VALIDATEBUFFER, 0);
+ lpc214x_usbcmd(CMD_USB_EP_SELECT | epphy, 0);
+ lpc214x_usbcmd(CMD_USB_EP_VALIDATEBUFFER, 0);
}
/****************************************************************************
@@ -911,7 +911,7 @@ static int lpc214x_epread(uint8_t epphy, uint8_t *data, uint32_t nbytes)
/* Done */
lpc214x_putreg(0, LPC214X_USBDEV_CTRL);
- (void)lpc214x_usbcmd(CMD_USB_EP_SELECT | epphy, 0);
+ lpc214x_usbcmd(CMD_USB_EP_SELECT | epphy, 0);
result = lpc214x_usbcmd(CMD_USB_EP_CLRBUFFER, 0);
/* The packet overrun bit in the clear buffer response is applicable only
@@ -1674,7 +1674,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
(privep = lpc214x_epfindbyaddr(priv, index)) != NULL)
{
privep->halted = 0;
- (void)lpc214x_epstall(&privep->ep, true);
+ lpc214x_epstall(&privep->ep, true);
lpc214x_epwrite(LPC214X_EP0_IN, NULL, 0);
priv->ep0state = LPC214X_EP0STATUSIN;
}
@@ -2231,7 +2231,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context, FAR void *arg)
/* Clear the endpoint interrupt */
usbtrace(TRACE_INTDECODE(LPC214X_TRACEINTID_EP0IN), priv->ep0state);
- (void)lpc214x_epclrinterrupt(LPC214X_CTRLEP_IN);
+ lpc214x_epclrinterrupt(LPC214X_CTRLEP_IN);
lpc214x_ep0dataininterrupt(priv);
}
pending >>= 2;
@@ -2246,7 +2246,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context, FAR void *arg)
{
/* Yes.. clear the endpoint interrupt */
- (void)lpc214x_epclrinterrupt(epphy);
+ lpc214x_epclrinterrupt(epphy);
/* Get the endpoint sructure corresponding to the physical
* endpoint number.
@@ -2884,7 +2884,7 @@ static int lpc214x_epstall(FAR struct usbdev_ep_s *ep, bool resume)
if (resume)
{
- (void)lpc214x_wrrequest(privep);
+ lpc214x_wrrequest(privep);
}
leave_critical_section(flags);
return OK;
diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c
index 5bb9b12..fc3a9b9 100644
--- a/arch/arm/src/lpc2378/lpc23xx_i2c.c
+++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c
@@ -220,8 +220,8 @@ static int lpc2378_i2c_start(struct lpc2378_i2cdev_s *priv)
priv->base + I2C_CONCLR_OFFSET);
putreg32(I2C_CONSET_STA, priv->base + I2C_CONSET_OFFSET);
- (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc2378_i2c_timeout, 1,
- (uint32_t)priv);
+ wd_start(priv->timeout, I2C_TIMEOUT, lpc2378_i2c_timeout, 1,
+ (uint32_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c
index 263400a..32c5c16 100644
--- a/arch/arm/src/lpc2378/lpc23xx_serial.c
+++ b/arch/arm/src/lpc2378/lpc23xx_serial.c
@@ -894,9 +894,9 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
- (void)uart_register("/dev/console", &CONSOLE_DEV);
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
}
/****************************************************************************
diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c
index 8602129..c1e3bfd 100644
--- a/arch/arm/src/lpc2378/lpc23xx_spi.c
+++ b/arch/arm/src/lpc2378/lpc23xx_spi.c
@@ -193,24 +193,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -415,7 +402,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(SPI_SR);
+ getreg32(SPI_SR);
return (uint16_t)getreg32(SPI_DR);
}
@@ -460,7 +447,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(SPI_SR);
+ getreg32(SPI_SR);
nwords--;
}
}
@@ -506,7 +493,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(SPI_SR);
+ getreg32(SPI_SR);
/* Read the received data from the SPI Data Register */
diff --git a/arch/arm/src/lpc2378/lpc23xx_timerisr.c b/arch/arm/src/lpc2378/lpc23xx_timerisr.c
index 455fd53..b403119 100644
--- a/arch/arm/src/lpc2378/lpc23xx_timerisr.c
+++ b/arch/arm/src/lpc2378/lpc23xx_timerisr.c
@@ -189,7 +189,7 @@ void arm_timer_initialize(void)
#ifdef CONFIG_VECTORED_INTERRUPTS
up_attach_vector(IRQ_SYSTIMER, ???, (vic_vector_t) lpc23xx_timerisr);
#else
- (void)irq_attach(IRQ_SYSTIMER, (xcpt_t)lpc23xx_timerisr, NULL);
+ irq_attach(IRQ_SYSTIMER, (xcpt_t)lpc23xx_timerisr, NULL);
#endif
/* And enable the system timer interrupt */
diff --git a/arch/arm/src/lpc31xx/lpc31_decodeirq.c b/arch/arm/src/lpc31xx/lpc31_decodeirq.c
index d091a35..8464ffb 100644
--- a/arch/arm/src/lpc31xx/lpc31_decodeirq.c
+++ b/arch/arm/src/lpc31xx/lpc31_decodeirq.c
@@ -126,7 +126,7 @@ void up_decodeirq(uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
- (void)group_addrenv(NULL);
+ group_addrenv(NULL);
#endif
}
#endif
diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c
index 2619f50..7e778e8 100644
--- a/arch/arm/src/lpc31xx/lpc31_ehci.c
+++ b/arch/arm/src/lpc31xx/lpc31_ehci.c
@@ -1012,21 +1012,7 @@ static int ehci_wait_usbsts(uint32_t maskbits, uint32_t donebits,
static void lpc31_takesem(sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -1649,7 +1635,7 @@ static void lpc31_qh_enqueue(struct lpc31_qh_s *qhead, struct lpc31_qh_s *qh)
*/
qh->fqp = qh->hw.overlay.nqp;
- (void)lpc31_qh_dump(qh, NULL, NULL);
+ lpc31_qh_dump(qh, NULL, NULL);
/* Add the new QH to the head of the asynchronous queue list.
*
diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.c b/arch/arm/src/lpc31xx/lpc31_i2c.c
index b4ff05c..c65d55c 100644
--- a/arch/arm/src/lpc31xx/lpc31_i2c.c
+++ b/arch/arm/src/lpc31xx/lpc31_i2c.c
@@ -490,7 +490,7 @@ static int i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs
/* Start a watchdog to timeout the transfer if the bus is locked up... */
- (void)wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
+ wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
/* Wait for the transfer to complete */
diff --git a/arch/arm/src/lpc31xx/lpc31_resetclks.c b/arch/arm/src/lpc31xx/lpc31_resetclks.c
index 4631f14..13465f3 100644
--- a/arch/arm/src/lpc31xx/lpc31_resetclks.c
+++ b/arch/arm/src/lpc31xx/lpc31_resetclks.c
@@ -137,7 +137,7 @@ void lpc31_resetclks(void)
* upon if the clock is needed by the board logic or not
*/
- (void)lpc31_defclk((enum lpc31_clockid_e)i);
+ lpc31_defclk((enum lpc31_clockid_e)i);
}
/* Disable all fractional dividers */
diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c
index b3ba526..a4f93d5 100644
--- a/arch/arm/src/lpc31xx/lpc31_serial.c
+++ b/arch/arm/src/lpc31xx/lpc31_serial.c
@@ -792,9 +792,9 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#if defined(CONFIG_UART_SERIAL_CONSOLE)
- (void)uart_register("/dev/console", &g_uartport);
+ uart_register("/dev/console", &g_uartport);
#endif
- (void)uart_register("/dev/ttyS0", &g_uartport);
+ uart_register("/dev/ttyS0", &g_uartport);
}
/****************************************************************************
diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c
index 8190a05..e9b4906 100644
--- a/arch/arm/src/lpc31xx/lpc31_spi.c
+++ b/arch/arm/src/lpc31xx/lpc31_spi.c
@@ -447,24 +447,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
diff --git a/arch/arm/src/lpc31xx/lpc31_timerisr.c b/arch/arm/src/lpc31xx/lpc31_timerisr.c
index 0120a67..206c251 100644
--- a/arch/arm/src/lpc31xx/lpc31_timerisr.c
+++ b/arch/arm/src/lpc31xx/lpc31_timerisr.c
@@ -135,7 +135,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(LPC31_IRQ_TMR0, (xcpt_t)lpc31_timerisr, NULL);
+ irq_attach(LPC31_IRQ_TMR0, (xcpt_t)lpc31_timerisr, NULL);
/* Clear any latched timer interrupt (Writing any value to the CLEAR register
* clears the latched interrupt generated by the counter timer)
diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c
index d7fa789..6999614 100644
--- a/arch/arm/src/lpc43xx/lpc43_ehci.c
+++ b/arch/arm/src/lpc43xx/lpc43_ehci.c
@@ -1005,21 +1005,7 @@ static int ehci_wait_usbsts(uint32_t maskbits, uint32_t donebits,
static void lpc43_takesem(sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -1549,7 +1535,7 @@ static void lpc43_qh_enqueue(struct lpc43_qh_s *qhead, struct lpc43_qh_s *qh)
*/
qh->fqp = qh->hw.overlay.nqp;
- (void)lpc43_qh_dump(qh, NULL, NULL);
+ lpc43_qh_dump(qh, NULL, NULL);
/* Add the new QH to the head of the asynchronous queue list.
*
diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c
index 76ada7c..e3f0b17 100644
--- a/arch/arm/src/lpc43xx/lpc43_ethernet.c
+++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c
@@ -1103,7 +1103,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
- (void)wd_start(priv->txtimeout, LPC43_TXTIMEOUT, lpc43_txtimeout_expiry, 1, (uint32_t)priv);
+ wd_start(priv->txtimeout, LPC43_TXTIMEOUT, lpc43_txtimeout_expiry, 1, (uint32_t)priv);
return OK;
}
@@ -1267,7 +1267,7 @@ static void lpc43_dopoll(FAR struct lpc43_ethmac_s *priv)
if (dev->d_buf)
{
- (void)devif_poll(dev, lpc43_txpoll);
+ devif_poll(dev, lpc43_txpoll);
/* We will, most likely end up with a buffer to be freed. But it
* might not be the same one that we allocated above.
@@ -2169,7 +2169,7 @@ static void lpc43_poll_work(FAR void *arg)
/* Update TCP timing states and poll for new XMIT data.
*/
- (void)devif_timer(dev, LPC43_WDDELAY, lpc43_txpoll);
+ devif_timer(dev, LPC43_WDDELAY, lpc43_txpoll);
/* We will, most likely end up with a buffer to be freed. But it
* might not be the same one that we allocated above.
@@ -2186,7 +2186,7 @@ static void lpc43_poll_work(FAR void *arg)
/* Setup the watchdog poll timer again */
- (void)wd_start(priv->txpoll, LPC43_WDDELAY, lpc43_poll_expiry, 1, priv);
+ wd_start(priv->txpoll, LPC43_WDDELAY, lpc43_poll_expiry, 1, priv);
net_unlock();
}
@@ -2261,8 +2261,8 @@ static int lpc43_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
- (void)wd_start(priv->txpoll, LPC43_WDDELAY, lpc43_poll_expiry, 1,
- (uint32_t)priv);
+ wd_start(priv->txpoll, LPC43_WDDELAY, lpc43_poll_expiry, 1,
+ (uint32_t)priv);
/* Enable the Ethernet interrupt */
@@ -3612,7 +3612,7 @@ static void lpc43_ipv6multicast(FAR struct lpc43_ethmac_s *priv)
ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- (void)lpc43_addmac(dev, mac);
+ lpc43_addmac(dev, mac);
#ifdef CONFIG_NET_ICMPv6_AUTOCONF
/* Add the IPv6 all link-local nodes Ethernet address. This is the
@@ -3620,7 +3620,7 @@ static void lpc43_ipv6multicast(FAR struct lpc43_ethmac_s *priv)
* packets.
*/
- (void)lpc43_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
+ lpc43_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
#endif /* CONFIG_NET_ICMPv6_AUTOCONF */
#ifdef CONFIG_NET_ICMPv6_ROUTER
@@ -3629,7 +3629,7 @@ static void lpc43_ipv6multicast(FAR struct lpc43_ethmac_s *priv)
* packets.
*/
- (void)lpc43_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
+ lpc43_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
#endif /* CONFIG_NET_ICMPv6_ROUTER */
}
@@ -3857,7 +3857,7 @@ static inline int lpc43_ethinitialize(void)
/* Register the device with the OS so that socket IOCTLs can be performed */
- (void)netdev_register(&priv->dev, NET_LL_ETHERNET);
+ netdev_register(&priv->dev, NET_LL_ETHERNET);
return OK;
}
@@ -3881,7 +3881,7 @@ static inline int lpc43_ethinitialize(void)
#ifndef CONFIG_NETDEV_LATEINIT
void up_netinitialize(void)
{
- (void)lpc43_ethinitialize();
+ lpc43_ethinitialize();
}
#endif
diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.c b/arch/arm/src/lpc43xx/lpc43_gpdma.c
index 0e4668e..784dca3 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpdma.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpdma.c
@@ -390,17 +390,11 @@ void lpc43_dmaconfigure(uint8_t dmarequest, uint8_t dmasrc)
DMA_HANDLE lpc43_dmachannel(void)
{
struct lpc43_dmach_s *dmach = NULL;
- int ret;
int i;
/* Get exclusive access to the GPDMA state structure */
- do
- {
- ret = nxsem_wait(&g_gpdma.exclsem);
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret < 0);
+ nxsem_wait_uninterruptible(&g_gpdma.exclsem);
/* Find an available DMA channel */
diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c
index 137a34f..5f0cf33 100644
--- a/arch/arm/src/lpc43xx/lpc43_i2c.c
+++ b/arch/arm/src/lpc43xx/lpc43_i2c.c
@@ -202,8 +202,8 @@ static int lpc43_i2c_start(struct lpc43_i2cdev_s *priv)
priv->base + LPC43_I2C_CONCLR_OFFSET);
putreg32(I2C_CONSET_STA, priv->base + LPC43_I2C_CONSET_OFFSET);
- (void)wd_start(priv->timeout, I2C_TIMEOUT, lpc43_i2c_timeout, 1,
- (uint32_t)priv);
+ wd_start(priv->timeout, I2C_TIMEOUT, lpc43_i2c_timeout, 1,
+ (uint32_t)priv);
nxsem_wait(&priv->wait);
wd_cancel(priv->timeout);
diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c
index 56e98d0..6bf7811 100644
--- a/arch/arm/src/lpc43xx/lpc43_idle.c
+++ b/arch/arm/src/lpc43xx/lpc43_idle.c
@@ -107,7 +107,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
- (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+ pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@@ -131,7 +131,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
- (void)lpc43_pmsleep();
+ lpc43_pmsleep();
break;
default:
diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c
index 94fbc94..6e041f2 100644
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -157,7 +157,7 @@ static void lpc43_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int lpc43_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -165,7 +165,7 @@ static int lpc43_nmi(int irq, FAR void *context, FAR void *arg)
static int lpc43_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
@@ -173,7 +173,7 @@ static int lpc43_busfault(int irq, FAR void *context, FAR void *arg)
static int lpc43_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
@@ -181,7 +181,7 @@ static int lpc43_usagefault(int irq, FAR void *context, FAR void *arg)
static int lpc43_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -189,7 +189,7 @@ static int lpc43_pendsv(int irq, FAR void *context, FAR void *arg)
static int lpc43_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -197,7 +197,7 @@ static int lpc43_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int lpc43_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/lpc43xx/lpc43_rtc.c b/arch/arm/src/lpc43xx/lpc43_rtc.c
index 291ba84..7275dbb 100644
--- a/arch/arm/src/lpc43xx/lpc43_rtc.c
+++ b/arch/arm/src/lpc43xx/lpc43_rtc.c
@@ -341,7 +341,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
/* Break out the time values (not that the time is set only to units of seconds) */
- (void)gmtime_r(&tp->tv_sec, &newtime);
+ gmtime_r(&tp->tv_sec, &newtime);
rtc_dumptime(&newtime, "Setting time");
/* Then write the broken out values to the RTC */
diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c
index 017dd72..ff5ce44 100644
--- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c
+++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c
@@ -270,7 +270,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr);
/* Low-level helpers ********************************************************/
static void lpc43_takesem(struct lpc43_dev_s *priv);
-#define lpc43_givesem(priv) (sem_post(&priv->waitsem))
+#define lpc43_givesem(priv) (nxsem_post(&priv->waitsem))
static inline void lpc43_setclock(uint32_t clkdiv);
static inline void lpc43_sdcard_clock(bool enable);
static int lpc43_ciu_sendcmd(uint32_t cmd, uint32_t arg);
@@ -526,16 +526,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr)
static void lpc43_takesem(struct lpc43_dev_s *priv)
{
- /* Take the semaphore (perhaps waiting) */
-
- while (sem_wait(&priv->waitsem) != 0)
- {
- /* The only case that an error should occr here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(errno == EINTR || errno == ECANCELED);
- }
+ nxsem_wait_uninterruptible(&priv->waitsem);
}
/****************************************************************************
@@ -882,7 +873,7 @@ static void lpc43_endwait(struct lpc43_dev_s *priv, sdio_eventset_t wkupevent)
/* Cancel the watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* Disable event-related interrupts */
@@ -1856,7 +1847,7 @@ static int lpc43_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* Mark no transfer in progress */
@@ -2770,7 +2761,7 @@ static void lpc43_callback(struct lpc43_dev_s *priv)
/* Yes.. queue it */
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
- (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
+ work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
@@ -2830,13 +2821,13 @@ FAR struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno)
/* Initialize semaphores */
- sem_init(&priv->waitsem, 0, 0);
+ nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
- sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+ nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c
index 73307f9..8df1f7e 100644
--- a/arch/arm/src/lpc43xx/lpc43_serial.c
+++ b/arch/arm/src/lpc43xx/lpc43_serial.c
@@ -1328,19 +1328,19 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#endif
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
}
diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c
index 108e20c..c8c5a96 100644
--- a/arch/arm/src/lpc43xx/lpc43_spi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spi.c
@@ -180,24 +180,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -399,7 +386,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(LPC43_SPI_SR);
+ getreg32(LPC43_SPI_SR);
return (uint16_t)getreg32(LPC43_SPI_DR);
}
@@ -444,7 +431,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(LPC43_SPI_SR);
+ getreg32(LPC43_SPI_SR);
nwords--;
}
}
@@ -490,7 +477,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw
/* Read the SPI Status Register again to clear the status bit */
- (void)getreg32(LPC43_SPI_SR);
+ getreg32(LPC43_SPI_SR);
/* Read the received data from the SPI Data Register */
diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c
index b105f6f..fe5433b 100644
--- a/arch/arm/src/lpc43xx/lpc43_ssp.c
+++ b/arch/arm/src/lpc43xx/lpc43_ssp.c
@@ -276,24 +276,11 @@ static int ssp_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
@@ -840,7 +827,7 @@ FAR struct spi_dev_s *lpc43_sspbus_initialize(int port)
ssp_putreg(priv, LPC43_SSP_CR1_OFFSET, regval | SSP_CR1_SSE);
for (i = 0; i < LPC43_SSP_FIFOSZ; i++)
{
- (void)ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
+ ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
}
return &priv->spidev;
@@ -882,7 +869,7 @@ void ssp_flush(FAR struct spi_dev_s *dev)
do
{
- (void)ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
+ ssp_getreg(priv, LPC43_SSP_DR_OFFSET);
}
while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE);
}
diff --git a/arch/arm/src/lpc43xx/lpc43_timer.c b/arch/arm/src/lpc43xx/lpc43_timer.c
index 7cfe3d2..c674e5b 100644
--- a/arch/arm/src/lpc43xx/lpc43_timer.c
+++ b/arch/arm/src/lpc43xx/lpc43_timer.c
@@ -757,7 +757,7 @@ void lpc43_tmrinitialize(FAR const char *devpath, int irq)
priv->ops = &g_tmrops;
- (void)irq_attach(irq, lpc43_interrupt, NULL);
+ irq_attach(irq, lpc43_interrupt, NULL);
/* Enable NVIC interrupt. */
@@ -765,7 +765,7 @@ void lpc43_tmrinitialize(FAR const char *devpath, int irq)
/* Register the timer driver as /dev/timerX */
- (void)timer_register(devpath, (FAR struct timer_lowerhalf_s *)priv);
+ timer_register(devpath, (FAR struct timer_lowerhalf_s *)priv);
}
#endif /* CONFIG_TIMER && CONFIG_LPC43_TMRx */
diff --git a/arch/arm/src/lpc43xx/lpc43_timerisr.c b/arch/arm/src/lpc43xx/lpc43_timerisr.c
index d797941..208c9df 100644
--- a/arch/arm/src/lpc43xx/lpc43_timerisr.c
+++ b/arch/arm/src/lpc43xx/lpc43_timerisr.c
@@ -134,7 +134,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(LPC43_IRQ_SYSTICK, (xcpt_t)lpc43_timerisr, NULL);
+ irq_attach(LPC43_IRQ_SYSTICK, (xcpt_t)lpc43_timerisr, NULL);
/* Enable SysTick interrupts */
diff --git a/arch/arm/src/lpc43xx/lpc43_wwdt.c b/arch/arm/src/lpc43xx/lpc43_wwdt.c
index 9e4414a..7dda509 100644
--- a/arch/arm/src/lpc43xx/lpc43_wwdt.c
+++ b/arch/arm/src/lpc43xx/lpc43_wwdt.c
@@ -644,7 +644,7 @@ void lpc43_wwdtinitialize(FAR const char *devpath)
/* Attach our watchdog interrupt handler (But don't enable it yet) */
- (void)irq_attach(LPC43M4_IRQ_WWDT, lpc43_interrupt, NULL);
+ irq_attach(LPC43M4_IRQ_WWDT, lpc43_interrupt, NULL);
/* Select an arbitrary initial timeout value. But don't start the watchdog
* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
@@ -656,7 +656,7 @@ void lpc43_wwdtinitialize(FAR const char *devpath)
/* Register the watchdog driver as /dev/watchdog0 */
- (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
+ watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
}
#endif /* CONFIG_WATCHDOG && CONFIG_LPC43_WWDT */
diff --git a/arch/arm/src/lpc54xx/lpc54_ethernet.c b/arch/arm/src/lpc54xx/lpc54_ethernet.c
index 7fb2d68..23b0d52 100644
--- a/arch/arm/src/lpc54xx/lpc54_ethernet.c
+++ b/arch/arm/src/lpc54xx/lpc54_ethernet.c
@@ -684,8 +684,8 @@ static int lpc54_eth_transmit(struct lpc54_ethdriver_s *priv,
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
- (void)wd_start(priv->eth_txtimeout, LPC54_TXTIMEOUT,
- lpc54_eth_txtimeout_expiry, 1, (wdparm_t)priv);
+ wd_start(priv->eth_txtimeout, LPC54_TXTIMEOUT,
+ lpc54_eth_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@@ -1633,8 +1633,8 @@ static void lpc54_eth_txtimeout_work(void *arg)
* again.
*/
- (void)lpc54_eth_ifdown(&priv->eth_dev);
- (void)lpc54_eth_ifup(&priv->eth_dev);
+ lpc54_eth_ifdown(&priv->eth_dev);
+ lpc54_eth_ifup(&priv->eth_dev);
/* Then poll the network for new XMIT data */
@@ -1731,7 +1731,7 @@ static void lpc54_eth_dotimer(struct lpc54_ethdriver_s *priv)
priv->eth_dev.d_buf = (uint8_t *)lpc54_pktbuf_alloc(priv);
if (priv->eth_dev.d_buf != NULL)
{
- (void)devif_timer(&priv->eth_dev, LPC54_WDDELAY, lpc54_eth_txpoll);
+ devif_timer(&priv->eth_dev, LPC54_WDDELAY, lpc54_eth_txpoll);
/* Make sure that the Tx buffer remaining after the poll is
* freed.
@@ -1798,7 +1798,7 @@ static void lpc54_eth_dopoll(struct lpc54_ethdriver_s *priv)
priv->eth_dev.d_buf = (uint8_t *)lpc54_pktbuf_alloc(priv);
if (priv->eth_dev.d_buf != NULL)
{
- (void)devif_poll(&priv->eth_dev, lpc54_eth_txpoll);
+ devif_poll(&priv->eth_dev, lpc54_eth_txpoll);
/* Make sure that the Tx buffer remaining after the poll is
* freed.
@@ -1848,8 +1848,8 @@ static void lpc54_eth_poll_work(void *arg)
/* Setup the watchdog poll timer again */
- (void)wd_start(priv->eth_txpoll, LPC54_WDDELAY, lpc54_eth_poll_expiry, 1,
- (wdparm_t)priv);
+ wd_start(priv->eth_txpoll, LPC54_WDDELAY, lpc54_eth_poll_expiry, 1,
+ (wdparm_t)priv);
net_unlock();
}
@@ -2156,8 +2156,8 @@ static int lpc54_eth_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
- (void)wd_start(priv->eth_txpoll, LPC54_WDDELAY, lpc54_eth_poll_expiry, 1,
- (wdparm_t)priv);
+ wd_start(priv->eth_txpoll, LPC54_WDDELAY, lpc54_eth_poll_expiry, 1,
+ (wdparm_t)priv);
/* Enable the Ethernet interrupt */
diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.c b/arch/arm/src/lpc54xx/lpc54_i2c_master.c
index a2fe531..80e0a24 100644
--- a/arch/arm/src/lpc54xx/lpc54_i2c_master.c
+++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.c
@@ -421,7 +421,7 @@ static void lpc54_i2c_xfrsetup(struct lpc54_i2cdev_s *priv)
if (msg->frequency > 0)
{
- (void)lpc54_i2c_setfrequency(priv, msg->frequency);
+ lpc54_i2c_setfrequency(priv, msg->frequency);
}
/* Clear error status bits */
@@ -766,8 +766,8 @@ static int lpc54_i2c_transfer(FAR struct i2c_master_s *dev,
/* Set up the transfer timeout */
- (void)wd_start(priv->timeout, priv->nmsgs * I2C_WDOG_TIMEOUT,
- lpc54_i2c_timeout, 1, (uint32_t)priv);
+ wd_start(priv->timeout, priv->nmsgs * I2C_WDOG_TIMEOUT,
+ lpc54_i2c_timeout, 1, (uint32_t)priv);
/* Initiate the transfer */
@@ -780,7 +780,7 @@ static int lpc54_i2c_transfer(FAR struct i2c_master_s *dev,
#ifndef CONFIG_I2C_POLLED
nxsem_wait(&priv->waitsem);
#else
- (void)lpc54_i2c_statemachine(priv);
+ lpc54_i2c_statemachine(priv);
#endif
}
while (priv->state != I2CSTATE_IDLE);
diff --git a/arch/arm/src/lpc54xx/lpc54_idle.c b/arch/arm/src/lpc54xx/lpc54_idle.c
index 21fbfba..45f7daa 100644
--- a/arch/arm/src/lpc54xx/lpc54_idle.c
+++ b/arch/arm/src/lpc54xx/lpc54_idle.c
@@ -107,7 +107,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
- (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+ pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@@ -131,7 +131,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
- (void)lpc54_pmsleep();
+ lpc54_pmsleep();
break;
default:
diff --git a/arch/arm/src/lpc54xx/lpc54_irq.c b/arch/arm/src/lpc54xx/lpc54_irq.c
index 2644380..286c02c 100644
--- a/arch/arm/src/lpc54xx/lpc54_irq.c
+++ b/arch/arm/src/lpc54xx/lpc54_irq.c
@@ -156,7 +156,7 @@ static void lpc54_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int lpc54_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -164,7 +164,7 @@ static int lpc54_nmi(int irq, FAR void *context, FAR void *arg)
static int lpc54_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
@@ -172,7 +172,7 @@ static int lpc54_busfault(int irq, FAR void *context, FAR void *arg)
static int lpc54_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
@@ -180,7 +180,7 @@ static int lpc54_usagefault(int irq, FAR void *context, FAR void *arg)
static int lpc54_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -188,7 +188,7 @@ static int lpc54_pendsv(int irq, FAR void *context, FAR void *arg)
static int lpc54_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -196,7 +196,7 @@ static int lpc54_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int lpc54_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/lpc54xx/lpc54_rng.c b/arch/arm/src/lpc54xx/lpc54_rng.c
index c61224d..65f35a8 100644
--- a/arch/arm/src/lpc54xx/lpc54_rng.c
+++ b/arch/arm/src/lpc54xx/lpc54_rng.c
@@ -159,7 +159,7 @@ static ssize_t lpc54_read(struct file *filep, char *buffer, size_t buflen)
void devrandom_register(void)
{
nxsem_init(&g_rngdev.rd_devsem, 0, 1);
- (void)register_driver("/dev/random", &g_rngops, 0444, NULL);
+ register_driver("/dev/random", &g_rngops, 0444, NULL);
}
#endif
@@ -183,7 +183,7 @@ void devurandom_register(void)
#ifndef CONFIG_DEV_RANDOM
nxsem_init(&g_rngdev.rd_devsem, 0, 1);
#endif
- (void)register_driver("/dev/urandom", &g_rngops, 0444, NULL);
+ register_driver("/dev/urandom", &g_rngops, 0444, NULL);
}
#endif
diff --git a/arch/arm/src/lpc54xx/lpc54_rtc.c b/arch/arm/src/lpc54xx/lpc54_rtc.c
index 90494c0..e08c180 100644
--- a/arch/arm/src/lpc54xx/lpc54_rtc.c
+++ b/arch/arm/src/lpc54xx/lpc54_rtc.c
@@ -322,7 +322,7 @@ int lpc54_rtc_rdalarm(FAR struct tm *time)
uint32_t match;
match = getreg32(LPC54_RTC_MATCH);
- (void)gmtime_r((time_t *)&match, time);
+ gmtime_r((time_t *)&match, time);
return OK;
}
#endif
diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c
index 6b389ec..bf3952d 100644
--- a/arch/arm/src/lpc54xx/lpc54_sdmmc.c
+++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c
@@ -274,7 +274,7 @@ static void lpc54_putreg(uint32_t val, uint32_t addr);
/* Low-level helpers ********************************************************/
static void lpc54_takesem(struct lpc54_dev_s *priv);
-#define lpc54_givesem(priv) (sem_post(&priv->waitsem))
+#define lpc54_givesem(priv) (nxsem_post(&priv->waitsem))
static inline void lpc54_setclock(uint32_t clkdiv);
static inline void lpc54_sdcard_clock(bool enable);
static int lpc54_ciu_sendcmd(uint32_t cmd, uint32_t arg);
@@ -530,16 +530,7 @@ static void lpc54_putreg(uint32_t val, uint32_t addr)
static void lpc54_takesem(struct lpc54_dev_s *priv)
{
- /* Take the semaphore (perhaps waiting) */
-
- while (sem_wait(&priv->waitsem) != 0)
- {
- /* The only case that an error should occr here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(errno == EINTR || errno == ECANCELED);
- }
+ nxsem_wait_uninterruptible(&priv->waitsem);
}
/****************************************************************************
@@ -882,7 +873,7 @@ static void lpc54_endwait(struct lpc54_dev_s *priv, sdio_eventset_t wkupevent)
/* Cancel the watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* Disable event-related interrupts */
@@ -1856,7 +1847,7 @@ static int lpc54_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
- (void)wd_cancel(priv->waitwdog);
+ wd_cancel(priv->waitwdog);
/* Mark no transfer in progress */
@@ -2770,7 +2761,7 @@ static void lpc54_callback(struct lpc54_dev_s *priv)
/* Yes.. queue it */
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
- (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
+ work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
{
@@ -2837,13 +2828,13 @@ FAR struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno)
/* Initialize semaphores */
- sem_init(&priv->waitsem, 0, 0);
+ nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
- sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+ nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c
index 7ea3b38..2c93bae 100644
--- a/arch/arm/src/lpc54xx/lpc54_serial.c
+++ b/arch/arm/src/lpc54xx/lpc54_serial.c
@@ -1431,38 +1431,38 @@ void up_serialinit(void)
#ifdef HAVE_USART_CONSOLE
/* Register the serial console */
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all USARTs */
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
- (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+ uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
- (void)uart_register("/dev/ttyS3", &TTYS3_DEV);
+ uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
- (void)uart_register("/dev/ttyS4", &TTYS4_DEV);
+ uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
#ifdef TTYS5_DEV
- (void)uart_register("/dev/ttyS5", &TTYS5_DEV);
+ uart_register("/dev/ttyS5", &TTYS5_DEV);
#endif
#ifdef TTYS6_DEV
- (void)uart_register("/dev/ttyS6", &TTYS6_DEV);
+ uart_register("/dev/ttyS6", &TTYS6_DEV);
#endif
#ifdef TTYS7_DEV
- (void)uart_register("/dev/ttyS7", &TTYS7_DEV);
+ uart_register("/dev/ttyS7", &TTYS7_DEV);
#endif
#ifdef TTYS8_DEV
- (void)uart_register("/dev/ttyS8", &TTYS8_DEV);
+ uart_register("/dev/ttyS8", &TTYS8_DEV);
#endif
#ifdef TTYS9_DEV
- (void)uart_register("/dev/ttyS9", &TTYS9_DEV);
+ uart_register("/dev/ttyS9", &TTYS9_DEV);
#endif
}
diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.c b/arch/arm/src/lpc54xx/lpc54_spi_master.c
index 40ba261..dd2755d 100644
--- a/arch/arm/src/lpc54xx/lpc54_spi_master.c
+++ b/arch/arm/src/lpc54xx/lpc54_spi_master.c
@@ -655,7 +655,7 @@ static void lpc54_spi_rxdiscard(FAR struct lpc54_spidev_s *priv)
{
while (lpc54_spi_rxavailable(priv))
{
- (void)lpc54_spi_getreg(priv, LPC54_SPI_FIFORD_OFFSET);
+ lpc54_spi_getreg(priv, LPC54_SPI_FIFORD_OFFSET);
}
}
@@ -1069,7 +1069,7 @@ static void lpc54_spi_sndblock8(FAR struct lpc54_spidev_s *priv,
* Tx FIFO.
*/
- (void)lpc54_spi_txtransfer8(priv, &txtransfer);
+ lpc54_spi_txtransfer8(priv, &txtransfer);
}
}
@@ -1266,24 +1266,11 @@ static int lpc54_spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
diff --git a/arch/arm/src/lpc54xx/lpc54_timerisr.c b/arch/arm/src/lpc54xx/lpc54_timerisr.c
index 8035d3c..c38a73a 100644
--- a/arch/arm/src/lpc54xx/lpc54_timerisr.c
+++ b/arch/arm/src/lpc54xx/lpc54_timerisr.c
@@ -160,7 +160,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(LPC54_IRQ_SYSTICK, (xcpt_t)lpc54_timerisr, NULL);
+ irq_attach(LPC54_IRQ_SYSTICK, (xcpt_t)lpc54_timerisr, NULL);
/* Enable SysTick interrupts */
diff --git a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
index 0a0b869..6582216 100644
--- a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
+++ b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
@@ -701,21 +701,7 @@ static void lpc54_putreg(uint32_t val, uint32_t addr)
static void lpc54_takesem(sem_t *sem)
{
- int ret;
-
- do
- {
- /* Take the semaphore (perhaps waiting) */
-
- ret = nxsem_wait(sem);
-
- /* The only case that an error should occur here is if the wait was
- * awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@@ -2175,7 +2161,7 @@ static int lpc54_rh_enumerate(struct usbhost_connection_s *conn,
/* USB 2.0 spec says at least 50ms delay before port reset */
- (void)nxsig_usleep(100*1000);
+ nxsig_usleep(100*1000);
/* Put RH port 1 in reset (the LPC546x supports only a single downstream port) */
@@ -2188,7 +2174,7 @@ static int lpc54_rh_enumerate(struct usbhost_connection_s *conn,
/* Release RH port 1 from reset and wait a bit */
lpc54_putreg(OHCI_RHPORTST_PRSC, LPC54_OHCI_RHPORTST1);
- (void)nxsig_usleep(200*1000);
+ nxsig_usleep(200*1000);
return OK;
}
diff --git a/arch/arm/src/lpc54xx/lpc54_wwdt.c b/arch/arm/src/lpc54xx/lpc54_wwdt.c
index 015e53a..ca720c3 100644
--- a/arch/arm/src/lpc54xx/lpc54_wwdt.c
+++ b/arch/arm/src/lpc54xx/lpc54_wwdt.c
@@ -663,7 +663,7 @@ void lpc54_wwdt_initialize(FAR const char *devpath)
/* Attach our watchdog interrupt handler (But don't enable it yet) */
- (void)irq_attach(LPC54_IRQ_WDT, lpc54_wwdt_interrupt);
+ irq_attach(LPC54_IRQ_WDT, lpc54_wwdt_interrupt);
/* Select an arbitrary initial timeout value. But don't start the watchdog
* yet. NOTE: If the "Hardware watchdog" feature is enabled through the
@@ -675,7 +675,7 @@ void lpc54_wwdt_initialize(FAR const char *devpath)
/* Register the watchdog driver as /dev/watchdog0 */
- (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
+ watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
}
#endif /* CONFIG_WATCHDOG && CONFIG_LPC54_WWDT */
diff --git a/arch/arm/src/max326xx/common/max326_idle.c b/arch/arm/src/max326xx/common/max326_idle.c
index 8aca772..50c50f0 100644
--- a/arch/arm/src/max326xx/common/max326_idle.c
+++ b/arch/arm/src/max326xx/common/max326_idle.c
@@ -107,7 +107,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
- (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+ pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@@ -131,7 +131,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
- (void)max326_pmsleep();
+ max326_pmsleep();
break;
default:
diff --git a/arch/arm/src/max326xx/common/max326_irq.c b/arch/arm/src/max326xx/common/max326_irq.c
index 058b62f..886b723 100644
--- a/arch/arm/src/max326xx/common/max326_irq.c
+++ b/arch/arm/src/max326xx/common/max326_irq.c
@@ -156,7 +156,7 @@ static void max326_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int max326_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -164,7 +164,7 @@ static int max326_nmi(int irq, FAR void *context, FAR void *arg)
static int max326_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
@@ -172,7 +172,7 @@ static int max326_busfault(int irq, FAR void *context, FAR void *arg)
static int max326_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
@@ -180,7 +180,7 @@ static int max326_usagefault(int irq, FAR void *context, FAR void *arg)
static int max326_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -188,7 +188,7 @@ static int max326_pendsv(int irq, FAR void *context, FAR void *arg)
static int max326_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -196,7 +196,7 @@ static int max326_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int max326_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c b/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c
index 6302799..f7078bb 100644
--- a/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c
+++ b/arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c
@@ -603,9 +603,9 @@ static int max326_rdalarm(FAR struct rtc_lowerhalf_s *lower,
/* Convert to struct rtc_time (aka struct tm) */
#ifdef CONFIG_LIBC_LOCALTIME
- (void)localtime_r(&sec, (FAR struct tm *)alarminfo->time);
+ localtime_r(&sec, (FAR struct tm *)alarminfo->time);
#else
- (void)gmtime_r(&sec, (FAR struct tm *)alarminfo->time);
+ gmtime_r(&sec, (FAR struct tm *)alarminfo->time);
#endif
ret = OK;
}
diff --git a/arch/arm/src/max326xx/common/max326_timerisr.c b/arch/arm/src/max326xx/common/max326_timerisr.c
index bc1e6f8..d05de6a 100644
--- a/arch/arm/src/max326xx/common/max326_timerisr.c
+++ b/arch/arm/src/max326xx/common/max326_timerisr.c
@@ -133,7 +133,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(MAX326_IRQ_SYSTICK, (xcpt_t)max326_timerisr, NULL);
+ irq_attach(MAX326_IRQ_SYSTICK, (xcpt_t)max326_timerisr, NULL);
/* Enable SysTick interrupts */
diff --git a/arch/arm/src/max326xx/max32660/max32660_rtc.c b/arch/arm/src/max326xx/max32660/max32660_rtc.c
index 9dd2a8c..e87e6e4 100644
--- a/arch/arm/src/max326xx/max32660/max32660_rtc.c
+++ b/arch/arm/src/max326xx/max32660/max32660_rtc.c
@@ -334,7 +334,7 @@ int up_rtc_initialize(void)
/* Attach the ALARM interrupt handler */
up_disable_irq(MAX326_IRQ_RTC);
- (void)irq_attach(MAX326_IRQ_RTC, max326_rtc_interrupt, NULL);
+ irq_attach(MAX326_IRQ_RTC, max326_rtc_interrupt, NULL);
#endif
/* Enable the RTC */
diff --git a/arch/arm/src/max326xx/max32660/max32660_serial.c b/arch/arm/src/max326xx/max32660/max32660_serial.c
index 236125b..c61f4dc 100644
--- a/arch/arm/src/max326xx/max32660/max32660_serial.c
+++ b/arch/arm/src/max326xx/max32660/max32660_serial.c
@@ -842,14 +842,14 @@ void up_serialinit(void)
#ifdef HAVE_UART_CONSOLE
/* Register the serial console */
- (void)uart_register("/dev/console", &CONSOLE_DEV);
+ uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
- (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
- (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
}
diff --git a/arch/arm/src/max326xx/max32660/max32660_spim.c b/arch/arm/src/max326xx/max32660/max32660_spim.c
index 2f5aa2a..cf7fbc2 100644
--- a/arch/arm/src/max326xx/max32660/max32660_spim.c
+++ b/arch/arm/src/max326xx/max32660/max32660_spim.c
@@ -829,24 +829,11 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
if (lock)
{
- /* Take the semaphore (perhaps waiting) */
-
- do
- {
- ret = nxsem_wait(&priv->exclsem);
-
- /* The only case that an error should occur here is if the wait
- * was awakened by a signal.
- */
-
- DEBUGASSERT(ret == OK || ret == -EINTR);
- }
- while (ret == -EINTR);
+ ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
- (void)nxsem_post(&priv->exclsem);
- ret = OK;
+ ret = nxsem_post(&priv->exclsem);
}
return ret;
diff --git a/arch/arm/src/max326xx/max32660/max32660_wdt.c b/arch/arm/src/max326xx/max32660/max32660_wdt.c
index 81286c4..74046f5 100644
--- a/arch/arm/src/max326xx/max32660/max32660_wdt.c
+++ b/arch/arm/src/max326xx/max32660/max32660_wdt.c
@@ -200,7 +200,7 @@ static void max326_int_enable(FAR struct max326_wdt_lowerhalf_s *priv)
{
/* Yes.. attach handler and enable the interrupt */
- (void)irq_attach(MAX326_IRQ_WDT0, priv->handler, priv);
+ irq_attach(MAX326_IRQ_WDT0, priv->handler, priv);
up_enable_irq(MAX326_IRQ_WDT0);
/* Select the interrupt behavior (de-selecting the reset behavior) */
diff --git a/arch/arm/src/nrf52/nrf52_idle.c b/arch/arm/src/nrf52/nrf52_idle.c
index c0c507c..fc94f40 100644
--- a/arch/arm/src/nrf52/nrf52_idle.c
+++ b/arch/arm/src/nrf52/nrf52_idle.c
@@ -107,7 +107,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
- (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+ pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@@ -131,7 +131,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
- (void)nrf52_pmsleep();
+ nrf52_pmsleep();
break;
default:
diff --git a/arch/arm/src/nrf52/nrf52_irq.c b/arch/arm/src/nrf52/nrf52_irq.c
index f282c22..384e7c5 100644
--- a/arch/arm/src/nrf52/nrf52_irq.c
+++ b/arch/arm/src/nrf52/nrf52_irq.c
@@ -156,7 +156,7 @@ static void nrf52_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int nrf52_nmi(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@@ -164,7 +164,7 @@ static int nrf52_nmi(int irq, FAR void *context, FAR void *arg)
static int nrf52_busfault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
@@ -172,7 +172,7 @@ static int nrf52_busfault(int irq, FAR void *context, FAR void *arg)
static int nrf52_usagefault(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
@@ -180,7 +180,7 @@ static int nrf52_usagefault(int irq, FAR void *context, FAR void *arg)
static int nrf52_pendsv(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@@ -188,7 +188,7 @@ static int nrf52_pendsv(int irq, FAR void *context, FAR void *arg)
static int nrf52_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@@ -196,7 +196,7 @@ static int nrf52_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int nrf52_reserved(int irq, FAR void *context, FAR void *arg)
{
- (void)up_irq_save();
+ up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
diff --git a/arch/arm/src/nrf52/nrf52_rng.c b/arch/arm/src/nrf52/nrf52_rng.c
index 0a120ea..d31a305 100644
--- a/arch/arm/src/nrf52/nrf52_rng.c
+++ b/arch/arm/src/nrf52/nrf52_rng.c
@@ -143,11 +143,11 @@ static int nrf52_rng_initialize(void)
memset(&g_rngdev, 0, sizeof(struct rng_dev_s));
- sem_init(&g_rngdev.rd_sem, 0, 0);
- sem_setprotocol(&g_rngdev.rd_sem, SEM_PRIO_NONE);
+ nxsem_init(&g_rngdev.rd_sem, 0, 0);
+ nxsem_setprotocol(&g_rngdev.rd_sem, SEM_PRIO_NONE);
- sem_init(&g_rngdev.excl_sem, 0, 1);
- sem_setprotocol(&g_rngdev.excl_sem, SEM_PRIO_NONE);
+ nxsem_init(&g_rngdev.excl_sem, 0, 1);
+ nxsem_setprotocol(&g_rngdev.excl_sem, SEM_PRIO_NONE);
_info("Ready to stop\n");
nrf52_rng_stop();
@@ -182,7 +182,7 @@ static int nrf52_rng_irqhandler(int irq, FAR void *context, FAR void *arg)
if (priv->rd_count == priv->buflen)
{
nrf52_rng_stop();
- sem_post(&priv->rd_sem);
+ nxsem_post(&priv->rd_sem);
}
}
@@ -216,10 +216,9 @@ static ssize_t nrf52_rng_read(FAR struct file *filep, FAR char *buffer,
FAR struct rng_dev_s *priv = (struct rng_dev_s *)&g_rngdev;
ssize_t read_len;
- if (sem_wait(&priv->excl_sem) != OK)
+ if (nxsem_wait(&priv->excl_sem) != OK)
{
- errno = EBUSY;
- return -errno;
+ return -EBUSY;
}
priv->rd_buf = (uint8_t *) buffer;
@@ -230,7 +229,7 @@ static ssize_t nrf52_rng_read(FAR struct file *filep, FAR char *buffer,
nrf52_rng_start();
- sem_wait(&priv->rd_sem);
+ nxsem_wait(&priv->rd_sem);
read_len = priv->rd_count;
if (priv->rd_count > priv->buflen)
@@ -241,7 +240,7 @@ static ssize_t nrf52_rng_read(FAR struct file *filep, FAR char *buffer,
/* Now , got data, and release rd_sem for next read */
- sem_post(&priv->excl_sem);
+ nxsem_post(&priv->excl_sem);
return read_len;
}
@@ -269,7 +268,7 @@ static ssize_t nrf52_rng_read(FAR struct file *filep, FAR char *buffer,
void devrandom_register(void)
{
nrf52_rng_initialize();
- (void)register_driver("/dev/random", FAR & g_rngops, 0444, NULL);
+ register_driver("/dev/random", FAR & g_rngops, 0444, NULL);
}
#endif
@@ -293,7 +292,7 @@ void devurandom_register(void)
#ifndef CONFIG_DEV_RANDOM
nrf52_rng_initialize();
... 48000 lines suppressed ...
[incubator-nuttx] 05/13: Author: Gregory Nutt
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit fc3bd5b3850349b40021286bf21c4bff55c4902e
Author: jjlange <jl...@2g-eng.com>
AuthorDate: Thu Jan 2 12:35:45 2020 -0600
Author: Gregory Nutt <gn...@nuttx.org>
Run all .c and .h files in last PR through nxstyle.
Author: macman88 <jj...@gmail.com>
SAME5x Ethernet Support (#25)
boards/arm/samd5e5/same54-xplained-pro/: Adds basic support for Microchip SAM E54 Xplained Pro board.
arch/arm/src/samd5e5/: Adds an Ethernet driver for the SAME5x family (based on the SAMA5 GMAC driver).
---
arch/arm/include/samd5e5/irq.h | 2 +-
arch/arm/src/samd5e5/Kconfig | 115 +
arch/arm/src/samd5e5/Make.defs | 1 +
arch/arm/src/samd5e5/hardware/sam_gmac.h | 1015 ++++++
arch/arm/src/samd5e5/hardware/sam_memorymap.h | 2 +-
arch/arm/src/samd5e5/hardware/sam_pinmap.h | 2 +-
.../samd5e5/irq.h => src/samd5e5/sam_ethernet.c} | 143 +-
arch/arm/src/samd5e5/sam_ethernet.h | 149 +
arch/arm/src/samd5e5/sam_gmac.c | 3831 ++++++++++++++++++++
boards/Kconfig | 13 +
boards/arm/samd5e5/same54-xplained-pro/Kconfig | 50 +
boards/arm/samd5e5/same54-xplained-pro/README.txt | 160 +
.../same54-xplained-pro/configs/nsh/defconfig | 55 +
.../samd5e5/same54-xplained-pro/include/board.h | 503 +++
.../samd5e5/same54-xplained-pro/scripts/Make.defs | 128 +
.../samd5e5/same54-xplained-pro/scripts/flash.ld | 123 +
.../arm/samd5e5/same54-xplained-pro/scripts/nvm.c | 56 +-
.../samd5e5/same54-xplained-pro/scripts/nvm.srec | 2 +
.../samd5e5/same54-xplained-pro/scripts/sram.ld | 122 +
.../arm/samd5e5/same54-xplained-pro/src/Makefile | 55 +
.../samd5e5/same54-xplained-pro/src/sam_appinit.c | 94 +
.../samd5e5/same54-xplained-pro/src/sam_autoleds.c | 295 ++
.../arm/samd5e5/same54-xplained-pro/src/sam_boot.c | 68 +-
.../samd5e5/same54-xplained-pro/src/sam_bringup.c | 67 +-
.../samd5e5/same54-xplained-pro/src/sam_phyinit.c | 47 +-
.../samd5e5/same54-xplained-pro/src/sam_userleds.c | 229 ++
.../same54-xplained-pro/src/same54-xplained-pro.h | 139 +-
27 files changed, 7276 insertions(+), 190 deletions(-)
diff --git a/arch/arm/include/samd5e5/irq.h b/arch/arm/include/samd5e5/irq.h
index 7807757..bd0b5ac 100644
--- a/arch/arm/include/samd5e5/irq.h
+++ b/arch/arm/include/samd5e5/irq.h
@@ -76,7 +76,7 @@
#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
+#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(CONFIG_ARCH_CHIP_SAME5X)
# include <arch/samd5e5/samd5e5_irq.h>
#else
# error "Unsupported SAMD5/E5 family"
diff --git a/arch/arm/src/samd5e5/Kconfig b/arch/arm/src/samd5e5/Kconfig
index 1462083..a0dba21 100644
--- a/arch/arm/src/samd5e5/Kconfig
+++ b/arch/arm/src/samd5e5/Kconfig
@@ -361,6 +361,13 @@ config SAMD5E5_DMAC
default n
select ARCH_DMA
+config SAMD5E5_GMAC
+ bool "Ethernet"
+ default n
+ depends on SAMD5E5_HAVE_ETHERNET
+ select NETDEVICES
+ select ARCH_HAVE_PHY
+
config SAMD5E5_EVSYS
bool "Event System"
default n
@@ -710,3 +717,111 @@ config SAMD5E5_USB_REGDEBUG
CONFIG_DEBUG_USB_INFO.
endmenu # USB options
+
+
+if SAMD5E5_GMAC
+
+menu "GMAC device driver options"
+
+config SAMD5E5_GMAC_NRXBUFFERS
+ int "Number of RX buffers"
+ default 16
+ ---help---
+ GMAC buffer memory is segmented into 128 byte units (not
+ configurable). This setting provides the number of such 128 byte
+ units used for reception. This is also equal to the number of RX
+ descriptors that will be allocated The selected value must be an
+ even power of 2.
+
+config SAMD5E5_GMAC_NTXBUFFERS
+ int "Number of TX buffers"
+ default 8
+ ---help---
+ GMAC buffer memory is segmented into full Ethernet packets (size
+ NET_BUFSIZE bytes). This setting provides the number of such packets
+ that can be in flight. This is also equal to the number of TX
+ descriptors that will be allocated.
+
+config SAMD5E5_GMAC_PREALLOCATE
+ bool "Preallocate buffers"
+ default n
+ ---help---
+ Buffer an descriptor many may either be allocated from the memory
+ pool or pre-allocated to lie in .bss. This options selected pre-
+ allocated buffer memory.
+
+config SAMD5E5_GMAC_NBC
+ bool "Disable Broadcast"
+ default n
+ ---help---
+ Select to disable receipt of broadcast packets.
+
+config SAMD5E5_GMAC_PHYADDR
+ int "PHY address"
+ default 1
+ ---help---
+ The 5-bit address of the PHY on the board. Default: 1
+
+config SAMD5E5_GMAC_PHYINIT
+ bool "Board-specific PHY Initialization"
+ default n
+ ---help---
+ Some boards require specialized initialization of the PHY before it can be used.
+ This may include such things as configuring GPIOs, resetting the PHY, etc. If
+ SAMD5E5_GMAC_PHYINIT is defined in the configuration then the board specific logic must
+ provide sam_phyinitialize(); The SAMD5E5 GMAC driver will call this function
+ one time before it first uses the PHY.
+
+config SAMD5E5_GMAC_AUTONEG
+ bool "Use autonegotiation"
+ default y
+ ---help---
+ Use PHY autonegotiation to determine speed and mode
+
+if !SAMD5E5_GMAC_AUTONEG
+
+config SAMD5E5_GMAC_ETHFD
+ bool "Full duplex"
+ default n
+ ---help---
+ If SAMD5E5_GMAC_AUTONEG is not defined, then this may be defined to
+ select full duplex mode. Default: half-duplex
+
+choice
+ prompt "GMAC Speed"
+ default SAMD5E5_GMAC_ETH100MBPS
+ ---help---
+ If autonegotiation is not used, then you must select the fixed speed
+ of the PHY
+
+config SAMD5E5_GMAC_ETH10MBPS
+ bool "10 Mbps"
+ ---help---
+ If SAMD5E5_GMAC_AUTONEG is not defined, then this may be defined to select 10 MBps
+ speed. Default: 100 Mbps
+
+config SAMD5E5_GMAC_ETH100MBPS
+ bool "100 Mbps"
+ ---help---
+ If SAMD5E5_GMAC_AUTONEG is not defined, then this may be defined to select 100 MBps
+ speed. Default: 100 Mbps
+
+endchoice # GMAC speed
+endif # !SAMD5E5_GMAC_AUTONEG
+
+config SAMD5E5_GMAC_REGDEBUG
+ bool "Register-Level Debug"
+ default n
+ depends on DEBUG_NET_INFO
+ ---help---
+ Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO.
+
+config SAMD5E5_GMAC_USE_MII
+ bool "Use MII interface for Ethernet"
+ default n
+ ---help---
+ If selected, use MII interface to Ethernet PHY. Otherwise, RMII will be used.
+
+endmenu # GMAC device driver options
+endif # SAMD5E5_GMAC
+
diff --git a/arch/arm/src/samd5e5/Make.defs b/arch/arm/src/samd5e5/Make.defs
index 82722da..71e5de2 100644
--- a/arch/arm/src/samd5e5/Make.defs
+++ b/arch/arm/src/samd5e5/Make.defs
@@ -154,6 +154,7 @@ endif
ifeq ($(CONFIG_SAMD5E5_GMAC),y)
CHIP_CSRCS += sam_gmac.c
+CHIP_CSRCS += sam_ethernet.c
endif
ifeq ($(CONFIG_SAMD5E5_USB),y)
diff --git a/arch/arm/src/samd5e5/hardware/sam_gmac.h b/arch/arm/src/samd5e5/hardware/sam_gmac.h
new file mode 100644
index 0000000..79815ed
--- /dev/null
+++ b/arch/arm/src/samd5e5/hardware/sam_gmac.h
@@ -0,0 +1,1015 @@
+/************************************************************************************
+ * arch/arm/src/same5d5/hardware/sam_gmac.h
+ *
+ * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GMAC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GMAC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/sam_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* GMAC Register Offsets ************************************************************/
+
+#define SAM_GMAC_NCR_OFFSET 0x0000 /* Network Control Register */
+#define SAM_GMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */
+#define SAM_GMAC_NSR_OFFSET 0x0008 /* Network Status Register */
+#define SAM_GMAC_UR_OFFSET 0x000c /* User Register */
+#define SAM_GMAC_DCFGR_OFFSET 0x0010 /* DMA Configuration Register */
+#define SAM_GMAC_TSR_OFFSET 0x0014 /* Transmit Status Register */
+#define SAM_GMAC_RBQB_OFFSET 0x0018 /* Receive Buffer Queue Base Address */
+#define SAM_GMAC_TBQB_OFFSET 0x001c /* Transmit Buffer Queue Base Address */
+#define SAM_GMAC_RSR_OFFSET 0x0020 /* Receive Status Register */
+#define SAM_GMAC_ISR_OFFSET 0x0024 /* Interrupt Status Register */
+#define SAM_GMAC_IER_OFFSET 0x0028 /* Interrupt Enable Register */
+#define SAM_GMAC_IDR_OFFSET 0x002c /* Interrupt Disable Register */
+#define SAM_GMAC_IMR_OFFSET 0x0030 /* Interrupt Mask Register */
+#define SAM_GMAC_MAN_OFFSET 0x0034 /* PHY Maintenance Register */
+#define SAM_GMAC_RPQ_OFFSET 0x0038 /* Received Pause Quantum Register */
+#define SAM_GMAC_TPQ_OFFSET 0x003c /* Transmit Pause Quantum Register */
+#define SAM_GMAC_TPSF_OFFSET 0x0040 /* TX Partial Store and Forward Register */
+#define SAM_GMAC_RPSF_OFFSET 0x0044 /* RX Partial Store and Forward Register */
+ /* 0x0048-0x007c Reserved */
+#define SAM_GMAC_HRB_OFFSET 0x0080 /* Hash Register Bottom [31:0] */
+#define SAM_GMAC_HRT_OFFSET 0x0084 /* Hash Register Top [63:32] */
+#define SAM_GMAC_SAB_OFFSET(n) (0x0088 + (((n)-1) << 3)) /* n=1..4 */
+#define SAM_GMAC_SAT_OFFSET(n) (0x008c + (((n)-1) << 3)) /* n=1..4 */
+#define SAM_GMAC_SAB1_OFFSET 0x0088 /* Specific Address 1 Bottom [31:0] Register */
+#define SAM_GMAC_SAT1_OFFSET 0x008c /* Specific Address 1 Top [47:32] Register */
+#define SAM_GMAC_SAB2_OFFSET 0x0090 /* Specific Address 2 Bottom [31:0] Register */
+#define SAM_GMAC_SAT2_OFFSET 0x0094 /* Specific Address 2 Top [47:32] Register */
+#define SAM_GMAC_SAB3_OFFSET 0x0098 /* Specific Address 3 Bottom [31:0] Register */
+#define SAM_GMAC_SAT3_OFFSET 0x009c /* Specific Address 3 Top [47:32] Register */
+#define SAM_GMAC_SAB4_OFFSET 0x00a0 /* Specific Address 4 Bottom [31:0] Register */
+#define SAM_GMAC_SAT4_OFFSET 0x00a4 /* Specific Address 4 Top [47:32] Register */
+#define SAM_GMAC_TIDM_OFFSET(n) (0x00a8 + (((n)-1) << 2)) /* n=1..4 */
+#define SAM_GMAC_TIDM1_OFFSET 0x00a8 /* Type ID Match 1 Register */
+#define SAM_GMAC_TIDM2_OFFSET 0x00ac /* Type ID Match 2 Register */
+#define SAM_GMAC_TIDM3_OFFSET 0x00b0 /* Type ID Match 3 Register */
+#define SAM_GMAC_TIDM4_OFFSET 0x00b4 /* Type ID Match 4 Register */
+#define SAM_GMAC_WOL_OFFSET 0x00b8 /* Wake on LAN Register */
+#define SAM_GMAC_IPGS_OFFSET 0x00bc /* IPG Stretch Register */
+#define SAM_GMAC_SVLAN_OFFSET 0x00c0 /* Stacked VLAN Register */
+#define SAM_GMAC_TPFCP_OFFSET 0x00c4 /* Transmit PFC Pause Register */
+#define SAM_GMAC_SAMB1_OFFSET 0x00c8 /* Specific Address 1 Mask Bottom [31:0] Register */
+#define SAM_GMAC_SAMT1_OFFSET 0x00cc /* Specific Address 1 Mask Top [47:32] Register */
+ /* 0x00fc Reserved */
+#define SAM_GMAC_OTLO_OFFSET 0x0100 /* Octets Transmitted [31:0] Register */
+#define SAM_GMAC_OTHI_OFFSET 0x0104 /* Octets Transmitted [47:32] Register */
+#define SAM_GMAC_FT_OFFSET 0x0108 /* Frames Transmitted Register */
+#define SAM_GMAC_BCFT_OFFSET 0x010c /* Broadcast Frames Transmitted Register */
+#define SAM_GMAC_MFT_OFFSET 0x0110 /* Multicast Frames Transmitted Register */
+#define SAM_GMAC_PFT_OFFSET 0x0114 /* Pause Frames Transmitted Register */
+#define SAM_GMAC_BFT64_OFFSET 0x0118 /* 64 Byte Frames Transmitted Register */
+#define SAM_GMAC_TBFT127_OFFSET 0x011c /* 65 to 127 Byte Frames Transmitted Register */
+#define SAM_GMAC_TBFT255_OFFSET 0x0120 /* 128 to 255 Byte Frames Transmitted Register */
+#define SAM_GMAC_TBFT511_OFFSET 0x0124 /* 256 to 511 Byte Frames Transmitted Register */
+#define SAM_GMAC_TBFT1023_OFFSET 0x0128 /* 512 to 1023 Byte Frames Transmitted Register */
+#define SAM_GMAC_TBFT1518_OFFSET 0x012c /* 1024 to 1518 Byte Frames Transmitted Register */
+#define SAM_GMAC_GTBFT1518_OFFSET 0x0130 /* Greater Than 1518 Byte Frames Transmitted Register */
+#define SAM_GMAC_TUR_OFFSET 0x0134 /* Transmit Under Runs Register */
+#define SAM_GMAC_SCF_OFFSET 0x0138 /* Single Collision Frames Register */
+#define SAM_GMAC_MCF_OFFSET 0x013c /* Multiple Collision Frames Register */
+#define SAM_GMAC_EC_OFFSET 0x0140 /* Excessive Collisions Register */
+#define SAM_GMAC_LC_OFFSET 0x0144 /* Late Collisions Register */
+#define SAM_GMAC_DTF_OFFSET 0x0148 /* Deferred Transmission Frames Register */
+#define SAM_GMAC_CSE_OFFSET 0x014c /* Carrier Sense Errors Register */
+#define SAM_GMAC_ORLO_OFFSET 0x0150 /* Octets Received [31:0] Received */
+#define SAM_GMAC_ORHI_OFFSET 0x0154 /* Octets Received [47:32] Received */
+#define SAM_GMAC_FR_OFFSET 0x0158 /* Frames Received Register */
+#define SAM_GMAC_BCFR_OFFSET 0x015c /* Broadcast Frames Received Register */
+#define SAM_GMAC_MFR_OFFSET 0x0160 /* Multicast Frames Received Register */
+#define SAM_GMAC_PFR_OFFSET 0x0164 /* Pause Frames Received Register */
+#define SAM_GMAC_BFR64_OFFSET 0x0168 /* 64 Byte Frames Received Register */
+#define SAM_GMAC_TBFR127_OFFSET 0x016c /* 65 to 127 Byte Frames Received Register */
+#define SAM_GMAC_TBFR255_OFFSET 0x0170 /* 128 to 255 Byte Frames Received Register */
+#define SAM_GMAC_TBFR511_OFFSET 0x0174 /* 256 to 511Byte Frames Received Register */
+#define SAM_GMAC_TBFR1023_OFFSET 0x0178 /* 512 to 1023 Byte Frames Received Register */
+#define SAM_GMAC_TBFR1518_OFFSET 0x017c /* 1024 to 1518 Byte Frames Received Register */
+#define SAM_GMAC_TMXBFR_OFFSET 0x0180 /* 1519 to Maximum Byte Frames Received Register */
+#define SAM_GMAC_UFR_OFFSET 0x0184 /* Undersize Frames Received Register */
+#define SAM_GMAC_OFR_OFFSET 0x0188 /* Oversize Frames Received Register */
+#define SAM_GMAC_JR_OFFSET 0x018c /* Jabbers Received Register */
+#define SAM_GMAC_FCSE_OFFSET 0x0190 /* Frame Check Sequence Errors Register */
+#define SAM_GMAC_LFFE_OFFSET 0x0194 /* Length Field Frame Errors Register */
+#define SAM_GMAC_RSE_OFFSET 0x0198 /* Receive Symbol Errors Register */
+#define SAM_GMAC_AE_OFFSET 0x019c /* Alignment Errors Register */
+#define SAM_GMAC_RRE_OFFSET 0x01a0 /* Receive Resource Errors Register */
+#define SAM_GMAC_ROE_OFFSET 0x01a4 /* Receive Overrun Register */
+#define SAM_GMAC_IHCE_OFFSET 0x01a8 /* IP Header Checksum Errors Register */
+#define SAM_GMAC_TCE_OFFSET 0x01ac /* TCP Checksum Errors Register */
+#define SAM_GMAC_UCE_OFFSET 0x01b0 /* UDP Checksum Errors Register */
+#define SAM_GMAC_TSSS_OFFSET 0x01c8 /* 1588 Timer Sync Strobe Seconds Register */
+#define SAM_GMAC_TSSN_OFFSET 0x01cc /* 1588 Timer Sync Strobe Nanoseconds Register */
+#define SAM_GMAC_TS_OFFSET 0x01d0 /* 1588 Timer Seconds Register */
+#define SAM_GMAC_TN_OFFSET 0x01d4 /* 1588 Timer Nanoseconds Register */
+#define SAM_GMAC_TA_OFFSET 0x01d8 /* 1588 Timer Adjust Register */
+#define SAM_GMAC_TI_OFFSET 0x01dc /* 1588 Timer Increment Register */
+#define SAM_GMAC_EFTS_OFFSET 0x01e0 /* PTP Event Frame Transmitted Seconds */
+#define SAM_GMAC_EFTN_OFFSET 0x01e4 /* PTP Event Frame Transmitted Nanoseconds */
+#define SAM_GMAC_EFRS_OFFSET 0x01e8 /* PTP Event Frame Received Seconds */
+#define SAM_GMAC_EFRN_OFFSET 0x01ec /* PTP Event Frame Received Nanoseconds */
+#define SAM_GMAC_PEFTS_OFFSET 0x01f0 /* PTP Peer Event Frame Transmitted Seconds */
+#define SAM_GMAC_PEFTN_OFFSET 0x01f4 /* PTP Peer Event Frame Transmitted Nanoseconds */
+#define SAM_GMAC_PEFRS_OFFSET 0x01f8 /* PTP Peer Event Frame Received Seconds */
+#define SAM_GMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */
+ /* 0x0200-0x023c Reserved */
+ /* 0x0280-0x0298 Reserved */
+#define SAM_GMAC_ISRPQ_OFFSET(n) (0x400 + ((n) << 2)) /* n=0..6 */
+#define SAM_GMAC_ISRPQ0_OFFSET 0x400 /* Interrupt Status Register Priority Queue 0 */
+#define SAM_GMAC_ISRPQ1_OFFSET 0x404 /* Interrupt Status Register Priority Queue 1 */
+#define SAM_GMAC_ISRPQ2_OFFSET 0x408 /* Interrupt Status Register Priority Queue 2 */
+#define SAM_GMAC_ISRPQ3_OFFSET 0x40c /* Interrupt Status Register Priority Queue 3 */
+#define SAM_GMAC_ISRPQ4_OFFSET 0x410 /* Interrupt Status Register Priority Queue 4 */
+#define SAM_GMAC_ISRPQ5_OFFSET 0x414 /* Interrupt Status Register Priority Queue 5 */
+#define SAM_GMAC_ISRPQ6_OFFSET 0x418 /* Interrupt Status Register Priority Queue 6 */
+#define SAM_GMAC_TBQBAPQ_OFFSET(n) (0x440 + ((n) << 2)) /* n=0..6 */
+#define SAM_GMAC_TBQBAPQ0_OFFSET 0x440 /* Transmit Buffer Queue Base Address Priority Queue 0 */
+#define SAM_GMAC_TBQBAPQ1_OFFSET 0x444 /* Transmit Buffer Queue Base Address Priority Queue 1 */
+#define SAM_GMAC_TBQBAPQ2_OFFSET 0x448 /* Transmit Buffer Queue Base Address Priority Queue 2 */
+#define SAM_GMAC_TBQBAPQ3_OFFSET 0x44c /* Transmit Buffer Queue Base Address Priority Queue 3 */
+#define SAM_GMAC_TBQBAPQ4_OFFSET 0x450 /* Transmit Buffer Queue Base Address Priority Queue 4 */
+#define SAM_GMAC_TBQBAPQ5_OFFSET 0x454 /* Transmit Buffer Queue Base Address Priority Queue 5 */
+#define SAM_GMAC_TBQBAPQ6_OFFSET 0x458 /* Transmit Buffer Queue Base Address Priority Queue 6 */
+#define SAM_GMAC_RBQBAPQ_OFFSET(n) (0x480 + ((n) << 2)) /* n=0..6 */
+#define SAM_GMAC_RBQBAPQ0_OFFSET 0x480 /* Receive Buffer Queue Base Address Priority Queue 0 */
+#define SAM_GMAC_RBQBAPQ1_OFFSET 0x484 /* Receive Buffer Queue Base Address Priority Queue 1 */
+#define SAM_GMAC_RBQBAPQ2_OFFSET 0x488 /* Receive Buffer Queue Base Address Priority Queue 2 */
+#define SAM_GMAC_RBQBAPQ3_OFFSET 0x48c /* Receive Buffer Queue Base Address Priority Queue 3 */
+#define SAM_GMAC_RBQBAPQ4_OFFSET 0x490 /* Receive Buffer Queue Base Address Priority Queue 4 */
+#define SAM_GMAC_RBQBAPQ5_OFFSET 0x494 /* Receive Buffer Queue Base Address Priority Queue 5 */
+#define SAM_GMAC_RBQBAPQ6_OFFSET 0x498 /* Receive Buffer Queue Base Address Priority Queue 6 */
+#define SAM_GMAC_RBSRPQ_OFFSET(n) (0x4a0 + ((n) << 2)) /* n=0..6 */
+#define SAM_GMAC_RBSRPQ0_OFFSET 0x4a0 /* Receive Buffer Size Register Priority Queue 0 */
+#define SAM_GMAC_RBSRPQ1_OFFSET 0x4a4 /* Receive Buffer Size Register Priority Queue 1 */
+#define SAM_GMAC_RBSRPQ2_OFFSET 0x4a8 /* Receive Buffer Size Register Priority Queue 2 */
+#define SAM_GMAC_RBSRPQ3_OFFSET 0x4ac /* Receive Buffer Size Register Priority Queue 3 */
+#define SAM_GMAC_RBSRPQ4_OFFSET 0x4b0 /* Receive Buffer Size Register Priority Queue 4 */
+#define SAM_GMAC_RBSRPQ5_OFFSET 0x4b4 /* Receive Buffer Size Register Priority Queue 5 */
+#define SAM_GMAC_RBSRPQ6_OFFSET 0x4b8 /* Receive Buffer Size Register Priority Queue 6 */
+#define SAM_GMAC_ST1RPQ_OFFSET(n) (0x500 + ((n) << 2)) /* n=0..15 */
+#define SAM_GMAC_ST1RPQ0_OFFSET 0x500 /* Screening Type1 Register Priority Queue 0 */
+#define SAM_GMAC_ST1RPQ1_OFFSET 0x504 /* Screening Type1 Register Priority Queue 1 */
+#define SAM_GMAC_ST1RPQ2_OFFSET 0x508 /* Screening Type1 Register Priority Queue 2 */
+#define SAM_GMAC_ST1RPQ3_OFFSET 0x50c /* Screening Type1 Register Priority Queue 3 */
+#define SAM_GMAC_ST1RPQ4_OFFSET 0x510 /* Screening Type1 Register Priority Queue 4 */
+#define SAM_GMAC_ST1RPQ5_OFFSET 0x514 /* Screening Type1 Register Priority Queue 5 */
+#define SAM_GMAC_ST1RPQ6_OFFSET 0x518 /* Screening Type1 Register Priority Queue 6 */
+#define SAM_GMAC_ST1RPQ7_OFFSET 0x51c /* Screening Type1 Register Priority Queue 7 */
+#define SAM_GMAC_ST1RPQ8_OFFSET 0x520 /* Screening Type1 Register Priority Queue 8 */
+#define SAM_GMAC_ST1RPQ9_OFFSET 0x524 /* Screening Type1 Register Priority Queue 9 */
+#define SAM_GMAC_ST1RPQ10_OFFSET 0x528 /* Screening Type1 Register Priority Queue 10 */
+#define SAM_GMAC_ST1RPQ11_OFFSET 0x52c /* Screening Type1 Register Priority Queue 11 */
+#define SAM_GMAC_ST1RPQ12_OFFSET 0x530 /* Screening Type1 Register Priority Queue 12 */
+#define SAM_GMAC_ST1RPQ13_OFFSET 0x534 /* Screening Type1 Register Priority Queue 13 */
+#define SAM_GMAC_ST1RPQ14_OFFSET 0x538 /* Screening Type1 Register Priority Queue 14 */
+#define SAM_GMAC_ST1RPQ15_OFFSET 0x53c /* Screening Type1 Register Priority Queue 15 */
+#define SAM_GMAC_ST2RPQ_OFFSET(n) (0x540 + ((n) << 2)) /* n=0..15 */
+#define SAM_GMAC_ST2RPQ0_OFFSET 0x540 /* Screening Type2 Register Priority Queue 0 */
+#define SAM_GMAC_ST2RPQ1_OFFSET 0x544 /* Screening Type2 Register Priority Queue 1 */
+#define SAM_GMAC_ST2RPQ2_OFFSET 0x548 /* Screening Type2 Register Priority Queue 2 */
+#define SAM_GMAC_ST2RPQ3_OFFSET 0x54c /* Screening Type2 Register Priority Queue 3 */
+#define SAM_GMAC_ST2RPQ4_OFFSET 0x550 /* Screening Type2 Register Priority Queue 4 */
+#define SAM_GMAC_ST2RPQ5_OFFSET 0x554 /* Screening Type2 Register Priority Queue 5 */
+#define SAM_GMAC_ST2RPQ6_OFFSET 0x558 /* Screening Type2 Register Priority Queue 6 */
+#define SAM_GMAC_ST2RPQ7_OFFSET 0x55c /* Screening Type2 Register Priority Queue 7 */
+#define SAM_GMAC_ST2RPQ8_OFFSET 0x560 /* Screening Type2 Register Priority Queue 8 */
+#define SAM_GMAC_ST2RPQ9_OFFSET 0x564 /* Screening Type2 Register Priority Queue 9 */
+#define SAM_GMAC_ST2RPQ10_OFFSET 0x568 /* Screening Type2 Register Priority Queue 10 */
+#define SAM_GMAC_ST2RPQ11_OFFSET 0x56c /* Screening Type2 Register Priority Queue 11 */
+#define SAM_GMAC_ST2RPQ12_OFFSET 0x570 /* Screening Type2 Register Priority Queue 12 */
+#define SAM_GMAC_ST2RPQ13_OFFSET 0x574 /* Screening Type2 Register Priority Queue 13 */
+#define SAM_GMAC_ST2RPQ14_OFFSET 0x578 /* Screening Type2 Register Priority Queue 14 */
+#define SAM_GMAC_ST2RPQ15_OFFSET 0x57c /* Screening Type2 Register Priority Queue 15 */
+#define SAM_GMAC_IERPQ_OFFSET(n) (0x600 + ((n) << 2)) /* n=0..6 */
+#define SAM_GMAC_IERPQ0_OFFSET 0x600 /* Interrupt Enable Register Priority Queue 0 */
+#define SAM_GMAC_IERPQ1_OFFSET 0x604 /* Interrupt Enable Register Priority Queue 1 */
+#define SAM_GMAC_IERPQ2_OFFSET 0x608 /* Interrupt Enable Register Priority Queue 2 */
+#define SAM_GMAC_IERPQ3_OFFSET 0x60c /* Interrupt Enable Register Priority Queue 3 */
+#define SAM_GMAC_IERPQ4_OFFSET 0x610 /* Interrupt Enable Register Priority Queue 4 */
+#define SAM_GMAC_IERPQ5_OFFSET 0x614 /* Interrupt Enable Register Priority Queue 5 */
+#define SAM_GMAC_IERPQ6_OFFSET 0x618 /* Interrupt Enable Register Priority Queue 6 */
+#define SAM_GMAC_IDRPQ_OFFSET(n) (0x620 + ((n) << 2)) /* n=0..6 */
+#define SAM_GMAC_IDRPQ0_OFFSET 0x620 /* Interrupt Disable Register Priority Queue 0 */
+#define SAM_GMAC_IDRPQ1_OFFSET 0x624 /* Interrupt Disable Register Priority Queue 1 */
+#define SAM_GMAC_IDRPQ2_OFFSET 0x628 /* Interrupt Disable Register Priority Queue 2 */
+#define SAM_GMAC_IDRPQ3_OFFSET 0x62c /* Interrupt Disable Register Priority Queue 3 */
+#define SAM_GMAC_IDRPQ4_OFFSET 0x630 /* Interrupt Disable Register Priority Queue 4 */
+#define SAM_GMAC_IDRPQ5_OFFSET 0x630 /* Interrupt Disable Register Priority Queue 5 */
+#define SAM_GMAC_IDRPQ6_OFFSET 0x638 /* Interrupt Disable Register Priority Queue 6 */
+#define SAM_GMAC_IMRPQ_OFFSET(n) (0x640 + ((n) << 2)) /* n=0..6 */
+#define SAM_GMAC_IMRPQ0_OFFSET 0x640 /* Interrupt Mask Register Priority Queue 0 */
+#define SAM_GMAC_IMRPQ1_OFFSET 0x644 /* Interrupt Mask Register Priority Queue 1 */
+#define SAM_GMAC_IMRPQ2_OFFSET 0x648 /* Interrupt Mask Register Priority Queue 2 */
+#define SAM_GMAC_IMRPQ3_OFFSET 0x64c /* Interrupt Mask Register Priority Queue 3 */
+#define SAM_GMAC_IMRPQ4_OFFSET 0x650 /* Interrupt Mask Register Priority Queue 4 */
+#define SAM_GMAC_IMRPQ5_OFFSET 0x654 /* Interrupt Mask Register Priority Queue 5 */
+#define SAM_GMAC_IMRPQ6_OFFSET 0x658 /* Interrupt Mask Register Priority Queue 6 */
+
+/* GMAC Register Addresses *********************************************************/
+
+#define SAM_GMAC_NCR (SAM_GMAC_BASE+SAM_GMAC_NCR_OFFSET)
+#define SAM_GMAC_NCFGR (SAM_GMAC_BASE+SAM_GMAC_NCFGR_OFFSET)
+#define SAM_GMAC_NSR (SAM_GMAC_BASE+SAM_GMAC_NSR_OFFSET)
+#define SAM_GMAC_UR (SAM_GMAC_BASE+SAM_GMAC_UR_OFFSET)
+#define SAM_GMAC_DCFGR (SAM_GMAC_BASE+SAM_GMAC_DCFGR_OFFSET)
+#define SAM_GMAC_TSR (SAM_GMAC_BASE+SAM_GMAC_TSR_OFFSET)
+#define SAM_GMAC_RBQB (SAM_GMAC_BASE+SAM_GMAC_RBQB_OFFSET)
+#define SAM_GMAC_TBQB (SAM_GMAC_BASE+SAM_GMAC_TBQB_OFFSET)
+#define SAM_GMAC_RSR (SAM_GMAC_BASE+SAM_GMAC_RSR_OFFSET)
+#define SAM_GMAC_ISR (SAM_GMAC_BASE+SAM_GMAC_ISR_OFFSET)
+#define SAM_GMAC_IER (SAM_GMAC_BASE+SAM_GMAC_IER_OFFSET)
+#define SAM_GMAC_IDR (SAM_GMAC_BASE+SAM_GMAC_IDR_OFFSET)
+#define SAM_GMAC_IMR (SAM_GMAC_BASE+SAM_GMAC_IMR_OFFSET)
+#define SAM_GMAC_MAN (SAM_GMAC_BASE+SAM_GMAC_MAN_OFFSET)
+#define SAM_GMAC_RPQ (SAM_GMAC_BASE+SAM_GMAC_RPQ_OFFSET)
+#define SAM_GMAC_TPQ (SAM_GMAC_BASE+SAM_GMAC_TPQ_OFFSET)
+#define SAM_GMAC_TPSF (SAM_GMAC_BASE+SAM_GMAC_TPSF_OFFSET)
+#define SAM_GMAC_RPSF (SAM_GMAC_BASE+SAM_GMAC_RPSF_OFFSET)
+#define SAM_GMAC_HRB (SAM_GMAC_BASE+SAM_GMAC_HRB_OFFSET)
+#define SAM_GMAC_HRT (SAM_GMAC_BASE+SAM_GMAC_HRT_OFFSET)
+#define SAM_GMAC_SAB(n) (SAM_GMAC_BASE+SAM_GMAC_SAB_OFFSET(n))
+#define SAM_GMAC_SAT(n) (SAM_GMAC_BASE+SAM_GMAC_SAT_OFFSET(n))
+#define SAM_GMAC_SAB1 (SAM_GMAC_BASE+SAM_GMAC_SAB1_OFFSET)
+#define SAM_GMAC_SAT1 (SAM_GMAC_BASE+SAM_GMAC_SAT1_OFFSET)
+#define SAM_GMAC_SAB2 (SAM_GMAC_BASE+SAM_GMAC_SAB2_OFFSET)
+#define SAM_GMAC_SAT2 (SAM_GMAC_BASE+SAM_GMAC_SAT2_OFFSET)
+#define SAM_GMAC_SAB3 (SAM_GMAC_BASE+SAM_GMAC_SAB3_OFFSET)
+#define SAM_GMAC_SAT3 (SAM_GMAC_BASE+SAM_GMAC_SAT3_OFFSET)
+#define SAM_GMAC_SAB4 (SAM_GMAC_BASE+SAM_GMAC_SAB4_OFFSET)
+#define SAM_GMAC_SAT4 (SAM_GMAC_BASE+SAM_GMAC_SAT4_OFFSET)
+#define SAM_GMAC_TIDM(n) (SAM_GMAC_BASE+SAM_GMAC_TIDM_OFFSET(n))
+#define SAM_GMAC_TIDM1 (SAM_GMAC_BASE+SAM_GMAC_TIDM1_OFFSET)
+#define SAM_GMAC_TIDM2 (SAM_GMAC_BASE+SAM_GMAC_TIDM2_OFFSET)
+#define SAM_GMAC_TIDM3 (SAM_GMAC_BASE+SAM_GMAC_TIDM3_OFFSET)
+#define SAM_GMAC_TIDM4 (SAM_GMAC_BASE+SAM_GMAC_TIDM4_OFFSET)
+#define SAM_GMAC_WOL (SAM_GMAC_BASE+SAM_GMAC_WOL_OFFSET)
+#define SAM_GMAC_IPGS (SAM_GMAC_BASE+SAM_GMAC_IPGS_OFFSET)
+#define SAM_GMAC_SVLAN (SAM_GMAC_BASE+SAM_GMAC_SVLAN_OFFSET)
+#define SAM_GMAC_TPFCP (SAM_GMAC_BASE+SAM_GMAC_TPFCP_OFFSET)
+#define SAM_GMAC_SAMB1 (SAM_GMAC_BASE+SAM_GMAC_SAMB1_OFFSET)
+#define SAM_GMAC_SAMT1 (SAM_GMAC_BASE+SAM_GMAC_SAMT1_OFFSET)
+#define SAM_GMAC_OTLO (SAM_GMAC_BASE+SAM_GMAC_OTLO_OFFSET)
+#define SAM_GMAC_OTHI (SAM_GMAC_BASE+SAM_GMAC_OTHI_OFFSET)
+#define SAM_GMAC_FT (SAM_GMAC_BASE+SAM_GMAC_FT_OFFSET)
+#define SAM_GMAC_BCFT (SAM_GMAC_BASE+SAM_GMAC_BCFT_OFFSET)
+#define SAM_GMAC_MFT (SAM_GMAC_BASE+SAM_GMAC_MFT_OFFSET)
+#define SAM_GMAC_PFT (SAM_GMAC_BASE+SAM_GMAC_PFT_OFFSET)
+#define SAM_GMAC_BFT64 (SAM_GMAC_BASE+SAM_GMAC_BFT64_OFFSET)
+#define SAM_GMAC_TBFT127 (SAM_GMAC_BASE+SAM_GMAC_TBFT127_OFFSET)
+#define SAM_GMAC_TBFT255 (SAM_GMAC_BASE+SAM_GMAC_TBFT255_OFFSET)
+#define SAM_GMAC_TBFT511 (SAM_GMAC_BASE+SAM_GMAC_TBFT511_OFFSET)
+#define SAM_GMAC_TBFT1023 (SAM_GMAC_BASE+SAM_GMAC_TBFT1023_OFFSET)
+#define SAM_GMAC_TBFT1518 (SAM_GMAC_BASE+SAM_GMAC_TBFT1518_OFFSET)
+#define SAM_GMAC_GTBFT1518 (SAM_GMAC_BASE+SAM_GMAC_GTBFT1518_OFFSET)
+#define SAM_GMAC_TUR (SAM_GMAC_BASE+SAM_GMAC_TUR_OFFSET)
+#define SAM_GMAC_SCF (SAM_GMAC_BASE+SAM_GMAC_SCF_OFFSET)
+#define SAM_GMAC_MCF (SAM_GMAC_BASE+SAM_GMAC_MCF_OFFSET)
+#define SAM_GMAC_EC (SAM_GMAC_BASE+SAM_GMAC_EC_OFFSET)
+#define SAM_GMAC_LC (SAM_GMAC_BASE+SAM_GMAC_LC_OFFSET)
+#define SAM_GMAC_DTF (SAM_GMAC_BASE+SAM_GMAC_DTF_OFFSET)
+#define SAM_GMAC_CSE (SAM_GMAC_BASE+SAM_GMAC_CSE_OFFSET)
+#define SAM_GMAC_ORLO (SAM_GMAC_BASE+SAM_GMAC_ORLO_OFFSET)
+#define SAM_GMAC_ORHI (SAM_GMAC_BASE+SAM_GMAC_ORHI_OFFSET)
+#define SAM_GMAC_FR (SAM_GMAC_BASE+SAM_GMAC_FR_OFFSET)
+#define SAM_GMAC_BCFR (SAM_GMAC_BASE+SAM_GMAC_BCFR_OFFSET)
+#define SAM_GMAC_MFR (SAM_GMAC_BASE+SAM_GMAC_MFR_OFFSET)
+#define SAM_GMAC_PFR (SAM_GMAC_BASE+SAM_GMAC_PFR_OFFSET)
+#define SAM_GMAC_BFR64 (SAM_GMAC_BASE+SAM_GMAC_BFR64_OFFSET)
+#define SAM_GMAC_TBFR127 (SAM_GMAC_BASE+SAM_GMAC_TBFR127_OFFSET)
+#define SAM_GMAC_TBFR255 (SAM_GMAC_BASE+SAM_GMAC_TBFR255_OFFSET)
+#define SAM_GMAC_TBFR511 (SAM_GMAC_BASE+SAM_GMAC_TBFR511_OFFSET)
+#define SAM_GMAC_TBFR1023 (SAM_GMAC_BASE+SAM_GMAC_TBFR1023_OFFSET)
+#define SAM_GMAC_TBFR1518 (SAM_GMAC_BASE+SAM_GMAC_TBFR1518_OFFSET)
+#define SAM_GMAC_TMXBFR (SAM_GMAC_BASE+SAM_GMAC_TMXBFR_OFFSET)
+#define SAM_GMAC_UFR (SAM_GMAC_BASE+SAM_GMAC_UFR_OFFSET)
+#define SAM_GMAC_OFR (SAM_GMAC_BASE+SAM_GMAC_OFR_OFFSET)
+#define SAM_GMAC_JR (SAM_GMAC_BASE+SAM_GMAC_JR_OFFSET)
+#define SAM_GMAC_FCSE (SAM_GMAC_BASE+SAM_GMAC_FCSE_OFFSET)
+#define SAM_GMAC_LFFE (SAM_GMAC_BASE+SAM_GMAC_LFFE_OFFSET)
+#define SAM_GMAC_RSE (SAM_GMAC_BASE+SAM_GMAC_RSE_OFFSET)
+#define SAM_GMAC_AE (SAM_GMAC_BASE+SAM_GMAC_AE_OFFSET)
+#define SAM_GMAC_RRE (SAM_GMAC_BASE+SAM_GMAC_RRE_OFFSET)
+#define SAM_GMAC_ROE (SAM_GMAC_BASE+SAM_GMAC_ROE_OFFSET)
+#define SAM_GMAC_IHCE (SAM_GMAC_BASE+SAM_GMAC_IHCE_OFFSET)
+#define SAM_GMAC_TCE (SAM_GMAC_BASE+SAM_GMAC_TCE_OFFSET)
+#define SAM_GMAC_UCE (SAM_GMAC_BASE+SAM_GMAC_UCE_OFFSET)
+#define SAM_GMAC_TSSS (SAM_GMAC_BASE+SAM_GMAC_TSSS_OFFSET)
+#define SAM_GMAC_TSSN (SAM_GMAC_BASE+SAM_GMAC_TSSN_OFFSET)
+#define SAM_GMAC_TS (SAM_GMAC_BASE+SAM_GMAC_TS_OFFSET)
+#define SAM_GMAC_TN (SAM_GMAC_BASE+SAM_GMAC_TN_OFFSET)
+#define SAM_GMAC_TA (SAM_GMAC_BASE+SAM_GMAC_TA_OFFSET)
+#define SAM_GMAC_TI (SAM_GMAC_BASE+SAM_GMAC_TI_OFFSET)
+#define SAM_GMAC_EFTS (SAM_GMAC_BASE+SAM_GMAC_EFTS_OFFSET)
+#define SAM_GMAC_EFTN (SAM_GMAC_BASE+SAM_GMAC_EFTN_OFFSET)
+#define SAM_GMAC_EFRS (SAM_GMAC_BASE+SAM_GMAC_EFRS_OFFSET)
+#define SAM_GMAC_EFRN (SAM_GMAC_BASE+SAM_GMAC_EFRN_OFFSET)
+#define SAM_GMAC_PEFTS (SAM_GMAC_BASE+SAM_GMAC_PEFTS_OFFSET)
+#define SAM_GMAC_PEFTN (SAM_GMAC_BASE+SAM_GMAC_PEFTN_OFFSET)
+#define SAM_GMAC_PEFRS (SAM_GMAC_BASE+SAM_GMAC_PEFRS_OFFSET)
+#define SAM_GMAC_PEFRN (SAM_GMAC_BASE+SAM_GMAC_PEFRN_OFFSET)
+#define SAM_GMAC_ISRPQ(n) (SAM_GMAC_BASE+SAM_GMAC_ISRPQ_OFFSET(n))
+#define SAM_GMAC_ISRPQ0 (SAM_GMAC_BASE+SAM_GMAC_ISRPQ0_OFFSET)
+#define SAM_GMAC_ISRPQ1 (SAM_GMAC_BASE+SAM_GMAC_ISRPQ1_OFFSET)
+#define SAM_GMAC_ISRPQ2 (SAM_GMAC_BASE+SAM_GMAC_ISRPQ2_OFFSET)
+#define SAM_GMAC_ISRPQ3 (SAM_GMAC_BASE+SAM_GMAC_ISRPQ3_OFFSET)
+#define SAM_GMAC_ISRPQ4 (SAM_GMAC_BASE+SAM_GMAC_ISRPQ4_OFFSET)
+#define SAM_GMAC_ISRPQ5 (SAM_GMAC_BASE+SAM_GMAC_ISRPQ5_OFFSET)
+#define SAM_GMAC_ISRPQ6 (SAM_GMAC_BASE+SAM_GMAC_ISRPQ6_OFFSET)
+#define SAM_GMAC_TBQBAPQ(n) (SAM_GMAC_BASE+SAM_GMAC_TBQBAPQ_OFFSET(n))
+#define SAM_GMAC_TBQBAPQ0 (SAM_GMAC_BASE+SAM_GMAC_TBQBAPQ0_OFFSET)
+#define SAM_GMAC_TBQBAPQ1 (SAM_GMAC_BASE+SAM_GMAC_TBQBAPQ1_OFFSET)
+#define SAM_GMAC_TBQBAPQ2 (SAM_GMAC_BASE+SAM_GMAC_TBQBAPQ2_OFFSET)
+#define SAM_GMAC_TBQBAPQ3 (SAM_GMAC_BASE+SAM_GMAC_TBQBAPQ3_OFFSET)
+#define SAM_GMAC_TBQBAPQ4 (SAM_GMAC_BASE+SAM_GMAC_TBQBAPQ4_OFFSET)
+#define SAM_GMAC_TBQBAPQ5 (SAM_GMAC_BASE+SAM_GMAC_TBQBAPQ5_OFFSET)
+#define SAM_GMAC_TBQBAPQ6 (SAM_GMAC_BASE+SAM_GMAC_TBQBAPQ6_OFFSET)
+#define SAM_GMAC_RBQBAPQ(n) (SAM_GMAC_BASE+SAM_GMAC_RBQBAPQ_OFFSET(n))
+#define SAM_GMAC_RBQBAPQ0 (SAM_GMAC_BASE+SAM_GMAC_RBQBAPQ0_OFFSET)
+#define SAM_GMAC_RBQBAPQ1 (SAM_GMAC_BASE+SAM_GMAC_RBQBAPQ1_OFFSET)
+#define SAM_GMAC_RBQBAPQ2 (SAM_GMAC_BASE+SAM_GMAC_RBQBAPQ2_OFFSET)
+#define SAM_GMAC_RBQBAPQ3 (SAM_GMAC_BASE+SAM_GMAC_RBQBAPQ3_OFFSET)
+#define SAM_GMAC_RBQBAPQ4 (SAM_GMAC_BASE+SAM_GMAC_RBQBAPQ4_OFFSET)
+#define SAM_GMAC_RBQBAPQ5 (SAM_GMAC_BASE+SAM_GMAC_RBQBAPQ5_OFFSET)
+#define SAM_GMAC_RBQBAPQ6 (SAM_GMAC_BASE+SAM_GMAC_RBQBAPQ6_OFFSET)
+#define SAM_GMAC_RBSRPQ(n) (SAM_GMAC_BASE+SAM_GMAC_RBSRPQ_OFFSET(n))
+#define SAM_GMAC_RBSRPQ0 (SAM_GMAC_BASE+SAM_GMAC_RBSRPQ0_OFFSET)
+#define SAM_GMAC_RBSRPQ1 (SAM_GMAC_BASE+SAM_GMAC_RBSRPQ1_OFFSET)
+#define SAM_GMAC_RBSRPQ2 (SAM_GMAC_BASE+SAM_GMAC_RBSRPQ2_OFFSET)
+#define SAM_GMAC_RBSRPQ3 (SAM_GMAC_BASE+SAM_GMAC_RBSRPQ3_OFFSET)
+#define SAM_GMAC_RBSRPQ4 (SAM_GMAC_BASE+SAM_GMAC_RBSRPQ4_OFFSET)
+#define SAM_GMAC_RBSRPQ5 (SAM_GMAC_BASE+SAM_GMAC_RBSRPQ5_OFFSET)
+#define SAM_GMAC_RBSRPQ6 (SAM_GMAC_BASE+SAM_GMAC_RBSRPQ6_OFFSET)
+#define SAM_GMAC_ST1RPQ(n) (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ_OFFSET(n))
+#define SAM_GMAC_ST1RPQ0 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ0_OFFSET)
+#define SAM_GMAC_ST1RPQ1 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ1_OFFSET)
+#define SAM_GMAC_ST1RPQ2 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ2_OFFSET)
+#define SAM_GMAC_ST1RPQ3 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ3_OFFSET)
+#define SAM_GMAC_ST1RPQ4 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ4_OFFSET)
+#define SAM_GMAC_ST1RPQ5 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ5_OFFSET)
+#define SAM_GMAC_ST1RPQ6 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ6_OFFSET)
+#define SAM_GMAC_ST1RPQ7 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ7_OFFSET)
+#define SAM_GMAC_ST1RPQ8 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ8_OFFSET)
+#define SAM_GMAC_ST1RPQ9 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ9_OFFSET)
+#define SAM_GMAC_ST1RPQ10 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ10_OFFSET)
+#define SAM_GMAC_ST1RPQ11 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ11_OFFSET)
+#define SAM_GMAC_ST1RPQ12 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ12_OFFSET)
+#define SAM_GMAC_ST1RPQ13 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ13_OFFSET)
+#define SAM_GMAC_ST1RPQ14 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ14_OFFSET)
+#define SAM_GMAC_ST1RPQ15 (SAM_GMAC_BASE+SAM_GMAC_ST1RPQ15_OFFSET)
+#define SAM_GMAC_ST2RPQ(n) (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ_OFFSET(n))
+#define SAM_GMAC_ST2RPQ0 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ0_OFFSET)
+#define SAM_GMAC_ST2RPQ1 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ1_OFFSET)
+#define SAM_GMAC_ST2RPQ2 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ2_OFFSET)
+#define SAM_GMAC_ST2RPQ3 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ3_OFFSET)
+#define SAM_GMAC_ST2RPQ4 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ4_OFFSET)
+#define SAM_GMAC_ST2RPQ5 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ5_OFFSET)
+#define SAM_GMAC_ST2RPQ6 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ6_OFFSET)
+#define SAM_GMAC_ST2RPQ7 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ7_OFFSET)
+#define SAM_GMAC_ST2RPQ8 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ8_OFFSET)
+#define SAM_GMAC_ST2RPQ9 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ9_OFFSET)
+#define SAM_GMAC_ST2RPQ10 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ10_OFFSET)
+#define SAM_GMAC_ST2RPQ11 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ11_OFFSET)
+#define SAM_GMAC_ST2RPQ12 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ12_OFFSET)
+#define SAM_GMAC_ST2RPQ13 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ13_OFFSET)
+#define SAM_GMAC_ST2RPQ14 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ14_OFFSET)
+#define SAM_GMAC_ST2RPQ15 (SAM_GMAC_BASE+SAM_GMAC_ST2RPQ15_OFFSET)
+#define SAM_GMAC_IERPQ(n) (SAM_GMAC_BASE+SAM_GMAC_IERPQ_OFFSET(n))
+#define SAM_GMAC_IERPQ0 (SAM_GMAC_BASE+SAM_GMAC_IERPQ0_OFFSET)
+#define SAM_GMAC_IERPQ1 (SAM_GMAC_BASE+SAM_GMAC_IERPQ1_OFFSET)
+#define SAM_GMAC_IERPQ2 (SAM_GMAC_BASE+SAM_GMAC_IERPQ2_OFFSET)
+#define SAM_GMAC_IERPQ3 (SAM_GMAC_BASE+SAM_GMAC_IERPQ3_OFFSET)
+#define SAM_GMAC_IERPQ4 (SAM_GMAC_BASE+SAM_GMAC_IERPQ4_OFFSET)
+#define SAM_GMAC_IERPQ5 (SAM_GMAC_BASE+SAM_GMAC_IERPQ5_OFFSET)
+#define SAM_GMAC_IERPQ6 (SAM_GMAC_BASE+SAM_GMAC_IERPQ6_OFFSET)
+#define SAM_GMAC_IDRPQ(n) (SAM_GMAC_BASE+SAM_GMAC_IDRPQ_OFFSET(n))
+#define SAM_GMAC_IDRPQ0 (SAM_GMAC_BASE+SAM_GMAC_IDRPQ0_OFFSET)
+#define SAM_GMAC_IDRPQ1 (SAM_GMAC_BASE+SAM_GMAC_IDRPQ1_OFFSET)
+#define SAM_GMAC_IDRPQ2 (SAM_GMAC_BASE+SAM_GMAC_IDRPQ2_OFFSET)
+#define SAM_GMAC_IDRPQ3 (SAM_GMAC_BASE+SAM_GMAC_IDRPQ3_OFFSET)
+#define SAM_GMAC_IDRPQ4 (SAM_GMAC_BASE+SAM_GMAC_IDRPQ4_OFFSET)
+#define SAM_GMAC_IDRPQ5 (SAM_GMAC_BASE+SAM_GMAC_IDRPQ5_OFFSET)
+#define SAM_GMAC_IDRPQ6 (SAM_GMAC_BASE+SAM_GMAC_IDRPQ6_OFFSET)
+#define SAM_GMAC_IMRPQ(n) (SAM_GMAC_BASE+SAM_GMAC_IMRPQ_OFFSET(n))
+#define SAM_GMAC_IMRPQ0 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ0_OFFSET)
+#define SAM_GMAC_IMRPQ1 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ1_OFFSET)
+#define SAM_GMAC_IMRPQ2 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ2_OFFSET)
+#define SAM_GMAC_IMRPQ3 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ3_OFFSET)
+#define SAM_GMAC_IMRPQ4 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ4_OFFSET)
+#define SAM_GMAC_IMRPQ5 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ5_OFFSET)
+#define SAM_GMAC_IMRPQ6 (SAM_GMAC_BASE+SAM_GMAC_IMRPQ6_OFFSET)
+
+/* GMAC Register Bit Definitions ***************************************************/
+
+/* Network Control Register */
+
+#define GMAC_NCR_LBL (1 << 1) /* Bit 1: Loopback local */
+#define GMAC_NCR_RXEN (1 << 2) /* Bit 2: Receive enable */
+#define GMAC_NCR_TXEN (1 << 3) /* Bit 3: Transmit enable */
+#define GMAC_NCR_MPE (1 << 4) /* Bit 4: Management port enable */
+#define GMAC_NCR_CLRSTAT (1 << 5) /* Bit 5: Clear statistics registers */
+#define GMAC_NCR_INCSTAT (1 << 6) /* Bit 6: Increment statistics registers */
+#define GMAC_NCR_WESTAT (1 << 7) /* Bit 7: Write enable for statistics registers */
+#define GMAC_NCR_BP (1 << 8) /* Bit 8: Back pressure */
+#define GMAC_NCR_TSTART (1 << 9) /* Bit 9: Start transmission */
+#define GMAC_NCR_THALT (1 << 10) /* Bit 10: Transmit halt */
+#define GMAC_NCR_TXPF (1 << 11) /* Bit 11: Transmit Pause Frame */
+#define GMAC_NCR_TXZQPF (1 << 12) /* Bit 12: Transmit Zero Quantum Pause Frame */
+#define GMAC_NCR_RDS (1 << 14) /* Bit 14: Read Snapshot */
+#define GMAC_NCR_SRTSM (1 << 15) /* Bit 15: Store Receive Time Stamp to Memory */
+#define GMAC_NCR_ENPBPR (1 << 16) /* Bit 16: Enable PFC Priority-based Pause Reception */
+#define GMAC_NCR_TXPBPF (1 << 17) /* Bit 17: Transmit PFC Priority-based Pause Frame */
+#define GMAC_NCR_FNP (1 << 18) /* Bit 18: Flush Next Packet */
+
+/* Network Configuration Register */
+
+#define GMAC_NCFGR_SPD (1 << 0) /* Bit 0: Speed */
+#define GMAC_NCFGR_FD (1 << 1) /* Bit 1: Full Duplex */
+#define GMAC_NCFGR_DNVLAN (1 << 2) /* Bit 2: Discard Non-VLAN FRAMES */
+#define GMAC_NCFGR_JFRAME (1 << 3) /* Bit 3: Jumbo Frames */
+#define GMAC_NCFGR_CAF (1 << 4) /* Bit 4: Copy All Frames */
+#define GMAC_NCFGR_NBC (1 << 5) /* Bit 5: No Broadcast */
+#define GMAC_NCFGR_MTIHEN (1 << 6) /* Bit 6: Multicast Hash Enable */
+#define GMAC_NCFGR_UNIHEN (1 << 7) /* Bit 7: Unicast Hash Enable */
+#define GMAC_NCFGR_MAXFS (1 << 8) /* Bit 8: Receive 1536 bytes frames */
+#define GMAC_NCFGR_RTY (1 << 12) /* Bit 12: Retry test */
+#define GMAC_NCFGR_PEN (1 << 13) /* Bit 13: Pause Enable */
+#define GMAC_NCFGR_RXBUFO_SHIFT (14) /* Bits 14-15: Receive Buffer Offset */
+#define GMAC_NCFGR_RXBUFO_MASK (3 << GMAC_NCFGR_RXBUFO_SHIFT)
+#define GMAC_NCFGR_LFERD (1 << 16) /* Bit 16: Length Field Error Frame Discard */
+#define GMAC_NCFGR_RFCS (1 << 17) /* Bit 17: Remove FCS */
+#define GMAC_NCFGR_CLK_SHIFT (18) /* Bits 18-20: MDC clock division */
+#define GMAC_NCFGR_CLK_MASK (7 << GMAC_NCFGR_CLK_SHIFT)
+# define GMAC_NCFGR_CLK_DIV8 (0 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 8 (MCK up to 20 MHz) */
+# define GMAC_NCFGR_CLK_DIV16 (1 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 16 (MCK up to 40 MHz) */
+# define GMAC_NCFGR_CLK_DIV32 (2 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 32 (MCK up to 80 MHz) */
+# define GMAC_NCFGR_CLK_DIV48 (3 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */
+# define GMAC_NCFGR_CLK_DIV64 (4 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */
+# define GMAC_NCFGR_CLK_DIV96 (5 << GMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */
+#define GMAC_NCFGR_DBW_SHIFT (21) /* Bits 21-22: Data Bus Width */
+#define GMAC_NCFGR_DBW_MASK (3 << GMAC_NCFGR_DBW_SHIFT)
+# define GMAC_NCFGR_DBW_32 (0 << GMAC_NCFGR_DBW_SHIFT) /* 32-bit data bus width */
+# define GMAC_NCFGR_DBW_64 (1 << GMAC_NCFGR_DBW_SHIFT) /* 64-bit data bus width */
+#define GMAC_NCFGR_DCPF (1 << 23) /* Bit 23: Disable Copy of Pause Frames */
+#define GMAC_NCFGR_RXCOEN (1 << 24) /* Bit 24: Receive Checksum Offload Enable */
+#define GMAC_NCFGR_EFRHD (1 << 25) /* Bit 25: Enable Frames Received in Half Duplex */
+#define GMAC_NCFGR_IRXFCS (1 << 26) /* Bit 26: Ignore RX FCS */
+#define GMAC_NCFGR_IPGSEN (1 << 28) /* Bit 28: IP Stretch Enable */
+#define GMAC_NCFGR_RXBP (1 << 29) /* Bit 29: Receive Bad Preamble */
+#define GMAC_NCFGR_IRXER (1 << 30) /* Bit 30: Ignore IPG GRXER */
+
+/* Network Status Register */
+
+#define GMAC_NSR_MDIO (1 << 1) /* Bit 1: MDIO Input Status */
+#define GMAC_NSR_IDLE (1 << 2) /* Bit 2: PHY management logic idle */
+
+/* User Register */
+
+#define GMAC_UR_MII (1 << 0) /* Bit 0: MII Mode */
+
+/* DMA Configuration Register */
+
+#define GMAC_DCFGR_FBLDO_SHIFT (0) /* Bits 0-4: Fixed Burst Length for DMA Data Operations */
+#define GMAC_DCFGR_FBLDO_MASK (31 << GMAC_DCFGR_FBLDO_SHIFT)
+# define GMAC_DCFGR_FBLDO_SINGLE (1 << GMAC_DCFGR_FBLDO_SHIFT) /* 00001: Always use SINGLE AHB bursts */
+# define GMAC_DCFGR_FBLDO_INCR4 (4 << GMAC_DCFGR_FBLDO_SHIFT) /* 001xx: Attempt to use INCR4 AHB bursts */
+# define GMAC_DCFGR_FBLDO_INCR8 (8 << GMAC_DCFGR_FBLDO_SHIFT) /* 01xxx: Attempt to use INCR8 AHB bursts */
+# define GMAC_DCFGR_FBLDO_INCR16 (16 << GMAC_DCFGR_FBLDO_SHIFT) /* 1xxxx: Attempt to use INCR16 AHB bursts */
+#define GMAC_DCFGR_ESMA (1 << 6) /* Bit 6: Endian Swap Mode Enable for Management Descriptor Accesses */
+#define GMAC_DCFGR_ESPA (1 << 7) /* Bit 7: Endian Swap Mode Enable for Packet Data Accesses */
+#define GMAC_DCFGR_RXBMS_SHIFT (8) /* Bits 8-9: Receiver Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_RXBMS_MASK (3 << GMAC_DCFGR_RXBMS_SHIFT)
+# define GMAC_DCFGR_RXBMS_EIGHTH (0 << GMAC_DCFGR_RXBMS_SHIFT) /* 1/2 Kbyte Memory Size */
+# define GMAC_DCFGR_RXBMS_QTR (1 << GMAC_DCFGR_RXBMS_SHIFT) /* 1Kbyte Memory Size */
+# define GMAC_DCFGR_RXBMS_HALF (2 << GMAC_DCFGR_RXBMS_SHIFT) /* 2 Kbytes Memory Size */
+# define GMAC_DCFGR_RXBMS_FULL (3 << GMAC_DCFGR_RXBMS_SHIFT) /* 4 Kbytes Memory Size */
+#define GMAC_DCFGR_TXPBMS (1 << 10) /* Bit 10: Transmitter Packet Buffer Memory Size Select */
+#define GMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */
+#define GMAC_DCFGR_DRBS_SHIFT (16) /* Bits 16-23: DMA Receive Buffer Size */
+#define GMAC_DCFGR_DRBS_MASK (0xff << GMAC_DCFGR_DRBS_SHIFT)
+# define GMAC_DCFGR_DRBS(n) ((uint32_t)(n) << GMAC_DCFGR_DRBS_SHIFT)
+#define GMAC_DCFGR_DDRP (1 << 24) /* Bit 24: DMA Discard Receive Packets */
+
+/* Transmit Status Register */
+
+#define GMAC_TSR_UBR (1 << 0) /* Bit 0: Used Bit Read */
+#define GMAC_TSR_COL (1 << 1) /* Bit 1: Collision Occurred */
+#define GMAC_TSR_RLE (1 << 2) /* Bit 2: Retry Limit exceeded */
+#define GMAC_TSR_TXGO (1 << 3) /* Bit 3: Transmit Go */
+#define GMAC_TSR_TFC (1 << 4) /* Bit 4: Transmit Frame Corruption due to AHB error */
+#define GMAC_TSR_TXCOMP (1 << 5) /* Bit 5: Transmit Complete */
+#define GMAC_TSR_UND (1 << 6) /* Bit 6: Transmit Underrun */
+#define GMAC_TSR_LCO (1 << 7) /* Bit 7: Late Collision Occurred */
+#define GMAC_TSR_HRESP (1 << 8) /* Bit 8: HRESP Not OK */
+
+/* Receive Buffer Queue Base Address */
+
+#define GMAC_RBQB_MASK (0xfffffffc) /* Bits 2-31: Receive buffer queue base address */
+
+/* Transmit Buffer Queue Base Address */
+
+#define GMAC_TBQB_MASK (0xfffffffc) /* Bits 2-31: Transmit buffer queue base address */
+
+/* Receive Status Register */
+
+#define GMAC_RSR_BNA (1 << 0) /* Bit 0: Buffer Not Available */
+#define GMAC_RSR_REC (1 << 1) /* Bit 1: Frame Received */
+#define GMAC_RSR_RXOVR (1 << 2) /* Bit 2: Receive Overrun */
+#define GMAC_RSR_HNO (1 << 3) /* Bit 3: HRESP Not OK */
+
+/* Interrupt Status Register, Interrupt Enable Register, Interrupt Disable Register */
+
+#define GMAC_INT_MFS (1 << 0) /* Bit 0: Management Frame Sent */
+#define GMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */
+#define GMAC_INT_RXUBR (1 << 2) /* Bit 2: Receive Used Bit Read */
+#define GMAC_INT_TXUBR (1 << 3) /* Bit 3: Transmit Used Bit Read */
+#define GMAC_INT_TUR (1 << 4) /* Bit 4: Transmit Under Run */
+#define GMAC_INT_RLEX (1 << 5) /* Bit 5: Retry Limit Exceeded or Late Collision */
+#define GMAC_INT_TFC (1 << 6) /* Bit 6: Transmit Frame Corruption due to AHB error */
+#define GMAC_INT_TCOMP (1 << 7) /* Bit 7: Transmit Complete */
+#define GMAC_INT_ROVR (1 << 10) /* Bit 10: Receive Overrun */
+#define GMAC_INT_HRESP (1 << 11) /* Bit 11: HRESP not OK */
+#define GMAC_INT_PFNZ (1 << 12) /* Bit 12: Pause Frame with Non-zero Pause Quantum */
+#define GMAC_INT_PTZ (1 << 13) /* Bit 13: Pause Time Zero */
+#define GMAC_INT_PFTR (1 << 14) /* Bit 14: Pause Frame Transmitted */
+#define GMAC_INT_EXINT (1 << 15) /* Bit 15: External Interrupt (not in ISR) */
+#define GMAC_INT_DRQFR (1 << 18) /* Bit 18: PTP Delay Request Frame Received */
+#define GMAC_INT_SFR (1 << 19) /* Bit 19: PTP Sync Frame Received */
+#define GMAC_INT_DRQFT (1 << 20) /* Bit 20: PTP Delay Request Frame Transmitted */
+#define GMAC_INT_SFT (1 << 21) /* Bit 21: PTP Sync Frame Transmitted */
+#define GMAC_INT_PDRQFR (1 << 22) /* Bit 22: PDelay Request Frame Received */
+#define GMAC_INT_PDRSFR (1 << 23) /* Bit 23: PDelay Response Frame Received */
+#define GMAC_INT_PDRQFT (1 << 24) /* Bit 24: PDelay Request Frame Transmitted */
+#define GMAC_INT_PDRSFT (1 << 25) /* Bit 25: PDelay Response Frame Transmitted */
+#define GMAC_INT_SRI (1 << 26) /* Bit 26: TSU Seconds Register Increment (not in IMR) */
+#define GMAC_INT_WOL (1 << 28) /* Bit 28: Wake On LAN (not in IMR) */
+
+#define GMAC_INT_ALL (0x17fcfcff)
+#define GMAC_INT_UNUSED (0xe8030300)
+
+/* PHY Maintenance Register */
+
+#define GMAC_MAN_DATA_SHIFT (0) /* Bits 0-15: PHY data */
+#define GMAC_MAN_DATA_MASK (0x0000ffff << GMAC_MAN_DATA_SHIFT)
+# define GMAC_MAN_DATA(n) ((uint32_t)(n) << GMAC_MAN_DATA_SHIFT)
+#define GMAC_MAN_WTN_SHIFT (16) /* Bits 16-17: Must be written to b10 */
+#define GMAC_MAN_WTN_MASK (3 << GMAC_MAN_WTN_SHIFT)
+# define GMAC_MAN_WTN (2 << GMAC_MAN_WTN_SHIFT)
+#define GMAC_MAN_REGA_SHIFT (18) /* Bits 18-22: Register Address */
+#define GMAC_MAN_REGA_MASK (31 << GMAC_MAN_REGA_SHIFT)
+# define GMAC_MAN_REGA(n) ((uint32_t)(n) << GMAC_MAN_REGA_SHIFT)
+#define GMAC_MAN_PHYA_SHIFT (23) /* Bits 23-27: PHY Address */
+#define GMAC_MAN_PHYA_MASK (31 << GMAC_MAN_PHYA_SHIFT)
+# define GMAC_MAN_PHYA(n) ((uint32_t)(n) << GMAC_MAN_PHYA_SHIFT)
+#define GMAC_MAN_OP_SHIFT (28) /* Bits 28-29: Operation */
+#define GMAC_MAN_OP_MASK (3 << GMAC_MAN_OP_SHIFT)
+# define GMAC_MAN_READ (2 << GMAC_MAN_OP_SHIFT)
+# define GMAC_MAN_WRITE (1 << GMAC_MAN_OP_SHIFT)
+#define GMAC_MAN_CLTTO (1 << 30) /* Bit 30: Clause 22 Operation */
+#define GMAC_MAN_WZO (1 << 31) /* Bit 31: Write ZERO */
+
+/* Received Pause Quantum Register */
+
+#define GMAC_RPQ_MASK (0x0000ffff) /* Bits 0-15: Received Pause Quantum */
+
+/* Transmit Pause Quantum Register */
+
+#define GMAC_TPQ_MASK (0x0000ffff) /* Bits 0-15: Transmit Pause Quantum */
+
+/* TX Partial Store and Forward Register */
+
+#define GMAC_TPSF_TPB1ADR_SHIFT (0) /* Bits 0-11: Transmit Partial Store and Forward Address */
+#define GMAC_TPSF_TPB1ADR_MASK (0xfff << GMAC_TPSF_TPB1ADR_SHIFT)
+# define GMAC_TPSF_TPB1ADR(n) ((uint32_t)(n) << GMAC_TPSF_TPB1ADR_SHIFT)
+#define GMAC_TPSF_ENTXP (1 << 31) /* Bit 31: Enable TX Partial Store and Forward Operation */
+
+/* RX Partial Store and Forward Register */
+
+#define GMAC_RPSF_RPB1ADR_SHIFT (0) /* Bits 0-11: Receive Partial Store and Forward Address */
+#define GMAC_RPSF_RPB1ADR_MASK (0xfff << GMAC_RPSF_RPB1ADR_SHIFT)
+# define GMAC_RPSF_RPB1ADR(n) ((uint32_t)(n) << GMAC_RPSF_RPB1ADR_SHIFT)
+#define GMAC_RPSF_ENRXP (1 << 31) /* Bit 31: Enable RX Partial Store and Forward Operation */
+
+/* Hash Register Bottom [31:0] (32-bit value) */
+/* Hash Register Top [63:32] (32-bit value) */
+
+/* Specific Address 1 Bottom [31:0] Register (32-bit value) */
+/* Specific Address 1 Top [47:32] Register */
+
+#define GMAC_SAT1_MASK (0x0000ffff) /* Bits 0-15: Specific Address 1 [47:32] */
+
+/* Specific Address 2 Bottom [31:0] Register (32-bit value) */
+/* Specific Address 2 Top [47:32] Register */
+
+#define GMAC_SAT2_MASK (0x0000ffff) /* Bits 0-15: Specific Address 2 [47:32] */
+
+/* Specific Address 3 Bottom [31:0] Register (32-bit value) */
+/* Specific Address 3 Top [47:32] Register */
+
+#define GMAC_SAT3_MASK (0x0000ffff) /* Bits 0-15: Specific Address 3 [47:32] */
+
+/* Specific Address 4 Bottom [31:0] Register (32-bit value) */
+/* Specific Address 4 Top [47:32] Register */
+
+#define GMAC_SAT4_MASK (0x0000ffff) /* Bits 0-15: Specific Address 4 [47:32] */
+
+/* Type ID Match 1 Register */
+
+#define GMAC_TIDM1_MASK (0x0000ffff) /* Bits 0-15: Type ID Match 1 */
+
+/* Type ID Match 2 Register */
+
+#define GMAC_TIDM2_MASK (0x0000ffff) /* Bits 0-15: Type ID Match 2 */
+
+/* Type ID Match 3 Register */
+
+#define GMAC_TIDM3_MASK (0x0000ffff) /* Bits 0-15: Type ID Match 3 */
+
+/* Type ID Match 4 Register */
+
+#define GMAC_TIDM4_MASK (0x0000ffff) /* Bits 0-15: Type ID Match 4 */
+
+/* Wake on LAN Register */
+
+#define GMAC_WOL_IP_SHIFT (0) /* Bits 0-15: ARP request IP address */
+#define GMAC_WOL_IP_MASK (0x0000ffff << GMAC_WOL_IP_SHIFT)
+#define GMAC_WOL_MAG (1 << 16) /* Bit 16: Magic packet event enable */
+#define GMAC_WOL_ARP (1 << 17) /* Bit 17: ARP request event enable */
+#define GMAC_WOL_SA1 (1 << 18) /* Bit 18: Specific address register 1 event enable */
+#define GMAC_WOL_MTI (1 << 19) /* Bit 19: Multicast hash event enable */
+
+/* IPG Stretch Register */
+
+#define GMAC_IPGS_MASK (0x0000ffff) /* Bits 0-15: Frame Length */
+
+/* Stacked VLAN Register */
+
+#define GMAC_SVLAN_VLANTYP_SHIFT (0) /* Bits 0-15: User Defined VLAN_TYPE Field */
+#define GMAC_SVLAN_VLANTYP_MASK (0xffff << GMAC_SVLAN_VLANTYP_SHIFT)
+# define GMAC_SVLAN_VLANTYP(n) ((uint32_t)(n) << GMAC_SVLAN_VLANTYP_SHIFT)
+#define GMAC_SVLAN_ESVLAN (1 << 31) /* Bit 31: Enable Stacked VLAN Processing Mode */
+
+/* Transmit PFC Pause Register */
+
+#define GMAC_TPFCP_PEV_SHIFT (0) /* Bits 0-7: Priority Enable Vector */
+#define GMAC_TPFCP_PEV_MASK (0xff << GMAC_TPFCP_PEV_SHIFT)
+#define GMAC_TPFCP_PQ_SHIFT (8) /* Bits 8-15: Pause Quantum */
+#define GMAC_TPFCP_PQ_MASK (0xff << GMAC_TPFCP_PQ_SHIFT)
+
+/* Specific Address 1 Mask Bottom [31:0] Register (32-bit mask) */
+/* Specific Address 1 Mask Top [47:32] Register */
+
+#define GMAC_SAMT1_MASK (0x0000ffff) /* Bits 0-15: Specific Address 1 Mask [47:32] */
+
+/* Octets Transmitted [31:0] Register (32-bit value) */
+/* Octets Transmitted [47:32] Register */
+
+#define GMAC_OTHI_MASK (0x0000ffff) /* Bits 0-15: Transmitted Octets [47:32] */
+
+/* Frames Transmitted Register (32-bit value) */
+/* Broadcast Frames Transmitted Register (32-bit value) */
+/* Multicast Frames Transmitted Register (32-bit value) */
+
+/* Pause Frames Transmitted Register */
+
+#define GMAC_PFT_MASK (0x0000ffff) /* Bits 0-15: Pause Frames Transmitted */
+
+/* 64 Byte Frames Transmitted Register (32-bit value) */
+/* 65 to 127 Byte Frames Transmitted Register (32-bit value) */
+/* 128 to 255 Byte Frames Transmitted Register (32-bit value) */
+/* 256 to 511 Byte Frames Transmitted Register (32-bit value) */
+/* 512 to 1023 Byte Frames Transmitted Register (32-bit value) */
+/* 1024 to 1518 Byte Frames Transmitted Register (32-bit value) */
+/* Greater Than 1518 Byte Frames Transmitted Register (32-bit value) */
+
+/* Transmit Under Runs Register */
+
+#define GMAC_TUR_MASK (0x000003ff) /* Bits 0-9: Transmit Under Runs */
+
+/* Single Collision Frames Register */
+
+#define GMAC_SCF_MASK (0x0003ffff) /* Bits 0-17: Single Collisions */
+
+/* Multiple Collision Frames Register */
+
+#define GMAC_MCF_MASK (0x0003ffff) /* Bits 0-17: Multiple Collisions */
+
+/* Excessive Collisions Register */
+
+#define GMAC_EC_MASK (0x000003ff) /* Bits 0-9: Excessive Collisions */
+
+/* Late Collisions Register */
+
+#define GMAC_LC_MASK (0x000003ff) /* Bits 0-9: Late Collisions */
+
+/* Deferred Transmission Frames Register */
+
+#define GMAC_DTF_MASK (0x0003ffff) /* Bits 0-17: Deferred Transmission */
+
+/* Carrier Sense Errors Register */
+
+#define GMAC_CSE_MASK (0x000003ff) /* Bits 0-9: Carrier Sense Error */
+
+/* Octets Received [31:0] Received (32-bit value) */
+/* Octets Received [47:32] Received */
+
+#define GMAC_ORHI_MASK (0x0000ffff) /* Bits 0-15: Received Octets [47:32] */
+
+/* Frames Received Register (32-bit value) */
+/* Broadcast Frames Received Register (32-bit value) */
+/* Multicast Frames Received Register (32-bit value) */
+/* Pause Frames Received Register */
+
+#define GMAC_PFR_MASK (0x0000ffff) /* Bits 0-15: Pause Frames Received */
+
+/* 64 Byte Frames Received Register (32-bit value) */
+/* 65 to 127 Byte Frames Received Register (32-bit value) */
+/* 128 to 255 Byte Frames Received Register (32-bit value) */
+/* 256 to 511Byte Frames Received Register (32-bit value) */
+/* 512 to 1023 Byte Frames Received Register (32-bit value) */
+/* 1024 to 1518 Byte Frames Received Register (32-bit value) */
+/* 1519 to Maximum Byte Frames Received Register (32-bit value) */
+
+/* Undersize Frames Received Register */
+
+#define GMAC_UFR_MASK (0x000003ff) /* Bits 0-9: Undersize Frames Received */
+
+/* Oversize Frames Received Register */
+
+#define GMAC_OFR_MASK (0x000003ff) /* Bits 0-9: Oversized Frames Received */
+
+/* Jabbers Received Register */
+
+#define GMAC_JR_MASK (0x000003ff) /* Bits 0-9: Jabbers Received */
+
+/* Frame Check Sequence Errors Register */
+
+#define GMAC_FCSE_MASK (0x000003ff) /* Bits 0-9: Frame Check Sequence Errors */
+
+/* Length Field Frame Errors Register */
+
+#define GMAC_LFFE_MASK (0x000003ff) /* Bits 0-9: Length Field Frame Errors */
+
+/* Receive Symbol Errors Register */
+
+#define GMAC_RSE_MASK (0x000003ff) /* Bits 0-9: Receive Symbol Errors */
+
+/* Alignment Errors Register */
+
+#define GMAC_AE_MASK (0x000003ff) /* Bits 0-9: Alignment Errors */
+
+/* Receive Resource Errors Register */
+
+#define GMAC_RRE_MASK (0x0003ffff) /* Bits 0-17: Receive Resource Errors */
+
+/* Receive Overrun Register */
+
+#define GMAC_ROE_MASK (0x000003ff) /* Bits 0-9: Receive Overruns */
+
+/* IP Header Checksum Errors Register */
+
+#define GMAC_IHCE_MASK (0x000000ff) /* Bits 0-7: IP Header Checksum Errors */
+
+/* TCP Checksum Errors Register */
+
+#define GMAC_TCE_MASK (0x000000ff) /* Bits 0-7: TCP Header Checksum Errors */
+
+/* UDP Checksum Errors Register */
+
+#define GMAC_UCE_MASK (0x000000ff) /* Bits 0-7: UDP Header Checksum Errors */
+
+/* 1588 Timer Sync Strobe Seconds Register (32-bit value) */
+/* 1588 Timer Sync Strobe Nanoseconds Register */
+
+#define GMAC_TSSN_MASK (0x3fffffff) /* Bits 0-29: Value Timer Nanoseconds Register Capture */
+
+/* 1588 Timer Seconds Register (32-bit value) */
+/* 1588 Timer Nanoseconds Register */
+
+#define GMAC_TN_MASK (0x3fffffff) /* Bits 0-29: Timer Count in Nanoseconds */
+
+/* 1588 Timer Adjust Register */
+
+#define GMAC_TA_ITDT_SHIFT (0) /* Bits 0-29: Increment/Decrement */
+#define GMAC_TA_ITDT_MASK (0x3fffffff)
+#define GMAC_TA_ADJ (1 << 31) /* Bit 31: Adjust 1588 Timer */
+
+/* 1588 Timer Increment Register */
+
+#define GMAC_TI_CNS_SHIFT (0) /* Bits 0-7: Count Nanoseconds */
+#define GMAC_TI_CNS_MASK (0xff << GMAC_TI_CNS_SHIFT)
+# define GMAC_TI_CNS(n) ((uint32_t)(n) << GMAC_TI_CNS_SHIFT)
+#define GMAC_TI_ACNS_SHIFT (8) /* Bits 8-15: Alternative Count Nanoseconds */
+#define GMAC_TI_ACNS_MASK (0xff << GMAC_TI_ACNS_SHIFT)
+# define GMAC_TI_ACNS(n) ((uint32_t)(n) << GMAC_TI_ACNS_SHIFT)
+#define GMAC_TI_NIT_SHIFT (16) /* Bits 16-23: Number of Increments */
+#define GMAC_TI_NIT_MASK (0xff << GMAC_TI_NIT_SHIFT)
+# define GMAC_TI_NIT(n) ((uint32_t)(n) << GMAC_TI_NIT_SHIFT)
+
+/* PTP Event Frame Transmitted Seconds (32-bit value) */
+/* PTP Event Frame Transmitted Nanoseconds */
+
+#define GMAC_EFTN_MASK (0x3fffffff) /* Bits 0-29: Register Update */
+
+/* PTP Event Frame Received Seconds (32-bit value) */
+/* PTP Event Frame Received Nanoseconds */
+
+#define GMAC_EFRN_MASK (0x3fffffff) /* Bits 0-29: Register Update */
+
+/* PTP Peer Event Frame Transmitted Seconds (32-bit value) */
+/* PTP Peer Event Frame Transmitted Nanoseconds */
+
+#define GMAC_PEFTN_MASK (0x3fffffff) /* Bits 0-29: Register Update */
+
+/* PTP Peer Event Frame Received Seconds (32-bit value) */
+/* PTP Peer Event Frame Received Nanoseconds */
+
+#define GMAC_PEFRS_MASK (0x3fffffff) /* Bits 0-29: Register Update */
+
+/* Interrupt Status Register Priority Queue 0-6
+ * Interrupt Enable Register Priority Queue 0-6
+ * Interrupt Disable Register Priority Queue 0-6
+ * Interrupt Mask Register Priority Queue 0-6
+ *
+ * Use these definitions:
+ *
+ * GMAC_INT_RCOMP Bit 1: Receive Complete
+ * GMAC_INT_RXUBR Bit 2: Receive Used Bit Read
+ * GMAC_INT_RLEX Bit 5: Retry Limit Exceeded or
+ * Late Collision
+ * GMAC_INT_TFC Bit 6: Transmit Frame Corruption
+ * due to AHB error
+ * GMAC_INT_TCOMP Bit 7: Transmit Complete
+ * GMAC_INT_ROVR Bit 10: Receive Overrun
+ * GMAC_INT_HRESP Bit 11: HRESP not OK
+ */
+
+/* Transmit Buffer Queue Base Address Priority Queue 0-6 */
+
+#define GMAC_TBQBAPQ0_MASK (0xfffffffc) /* Bits 2-31: Transmit Buffer Queue Base Address */
+
+/* Receive Buffer Queue Base Address Priority Queue 0-6 */
+
+#define GMAC_RBQBAPQ0_MASK (0xfffffffc) /* Bits 2-31: Receive Buffer Queue Base Address */
+
+/* Receive Buffer Size Register Priority Queue 0-6 */
+
+#define GMAC_RBSRPQ0_MASK (0x0000ffff) /* Bits 0-15: Receive Buffer Size */
+
+/* Screening Type1 Register Priority Queue 0-15 */
+
+#define GMAC_ST1RPQ0_QNB_SHIFT (0) /* Bits 0-3: Que Number (0->7) */
+#define GMAC_ST1RPQ0_QNB_MASK (15 << GMAC_ST1RPQ0_QNB_SHIFT)
+# define GMAC_ST1RPQ0_QNB(n) ((uint32_t)(n) << GMAC_ST1RPQ0_QNB_SHIFT)
+#define GMAC_ST1RPQ0_DSTCM_SHIFT (4) /* Bits 4-11: Differentiated Services or Traffic Class Match */
+#define GMAC_ST1RPQ0_DSTCM_MASK (0xff << GMAC_ST1RPQ0_DSTCM_SHIFT)
+# define GMAC_ST1RPQ0_DSTCM(n) ((uint32_t)(n) << GMAC_ST1RPQ0_DSTCM_SHIFT)
+#define GMAC_ST1RPQ0_UDPM_SHIFT (12) /* Bits 12-27: UDP Port Match */
+#define GMAC_ST1RPQ0_UDPM_MASK (0xffff << GMAC_ST1RPQ0_UDPM_SHIFT)
+# define GMAC_ST1RPQ0_UDPM(n) ((uint32_t)(n) << GMAC_ST1RPQ0_UDPM_SHIFT)
+#define GMAC_ST1RPQ0_DSTCE (1 << 28) /* Bit 28: Differentiated Services or Traffic Class Match Enable */
+#define GMAC_ST1RPQ0_UDPE (1 << 29) /* Bit 29: UDP Port Match Enable */
+
+/* Screening Type2 Register Priority Queue 0-15 */
+
+#define GMAC_ST2RPQ0_QNB_SHIFT (0) /* Bits 0-3: Que Number (0->7) */
+#define GMAC_ST2RPQ0_QNB_MASK (15 << GMAC_ST2RPQ0_QNB_SHIFT)
+# define GMAC_ST2RPQ0_QNB(n) ((uint32_t)(n) << GMAC_ST2RPQ0_QNB_SHIFT)
+#define GMAC_ST2RPQ0_VLANP_SHIFT (4) /* Bits 4-7: VLAN Priority */
+#define GMAC_ST2RPQ0_VLANP_MASK (15 << GMAC_ST2RPQ0_VLANP_SHIFT)
+# define GMAC_ST2RPQ0_VLANP(n) ((uint32_t)(n) << GMAC_ST2RPQ0_VLANP_SHIFT)
+#define GMAC_ST2RPQ0_VLANE (1 << 8) /* Bit 8: VLAN Enable */
+
+/* Descriptors **********************************************************************/
+
+/* Receive buffer descriptor: Address word */
+
+#define GMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=GMAC owns */
+#define GMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */
+#define GMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */
+
+/* Receive buffer descriptor: Control word */
+
+#define GMACRXD_STA_FRLEN_SHIFT (0) /* Bits 0-12: Length of frame */
+#define GMACRXD_STA_FRLEN_MASK (0x00000fff << GMACRXD_STA_FRLEN_SHIFT)
+#define GMACRXD_STA_JFRLEN_SHIFT (0) /* Bits 0-13: Length of jumbo frame */
+#define GMACRXD_STA_JFRLEN_MASK (0x00001fff << GMACRXD_STA_JFRLEN_SHIFT)
+#define GMACRXD_STA_BADFCS (1 << 13) /* Bit 13: Frame had bad FCS */
+#define GMACRXD_STA_SOF (1 << 14) /* Bit 14: Start of frame */
+#define GMACRXD_STA_EOF (1 << 15) /* Bit 15: End of frame */
+#define GMACRXD_STA_CFI (1 << 16) /* Bit 16: Canonical format indicator (CFI) bit */
+#define GMACRXD_STA_VLPRIO_SHIFT (17) /* Bits 17-19: VLAN priority */
+#define GMACRXD_STA_VLPRIO_MASK (7 << GMACRXD_STA_VLANPRIO_SHIFT)
+#define GMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */
+#define GMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */
+#define GMACRXD_STA_TYPID_SHIFT (22) /* Bits 22-23: Type ID register match */
+#define GMACRXD_STA_TYPID_MASK (3 << GMACRXD_STA_TYPID_SHIFT)
+# define GMACRXD_STA_TYPID1 (0 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 1 match */
+# define GMACRXD_STA_TYPID2 (1 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 2 match */
+# define GMACRXD_STA_TYPID3 (2 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 3 match */
+# define GMACRXD_STA_TYPID4 (3 << GMACRXD_STA_TYPID_SHIFT) /* Type ID register 4 match */
+#define GMACRXD_STA_SNAP_SHIFT (22) /* Bits 22-23: Specific Address Register match */
+#define GMACRXD_STA_SNAP_MASK (3 << GMACRXD_STA_SNAP_SHIFT)
+# define GMACRXD_STA_SNAP_NOCHK (0 << GMACRXD_STA_SNAP_SHIFT) /* Checksum not checked */
+# define GMACRXD_STA_SNAP_IPCHK (1 << GMACRXD_STA_SNAP_SHIFT) /* IP header checksum checked */
+# define GMACRXD_STA_SNAP_TCPCHK (2 << GMACRXD_STA_SNAP_SHIFT) /* IP header and TCP checksum checked */
+# define GMACRXD_STA_SNAP_UDPCHK (3 << GMACRXD_STA_SNAP_SHIFT) /* IP header and UDP checksum checked */
+#define GMACRXD_STA_TYPID (1 << 24) /* Bit 24: Type ID match found */
+#define GMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */
+#define GMACRXD_STA_ADDR_SHIFT (25) /* Bits 25-26: Specific Address Register match */
+#define GMACRXD_STA_ADDR_MASK (3 << GMACRXD_STA_ADDR_SHIFT)
+# define GMACRXD_STA_ADDR1_MATCH (0 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */
+# define GMACRXD_STA_ADDR2_MATCH (1 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */
+# define GMACRXD_STA_ADDR3_MATCH (2 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */
+# define GMACRXD_STA_ADDR4_MATCH (3 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */
+#define GMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific Address Register match found */
+ /* Bit 28: Reserved */
+#define GMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */
+#define GMACRXD_STA_MCAST (1 << 30) /* Bit 30: Multicast hash match */
+#define GMACRXD_STA_BCAST (1 << 31) /* Bit 31: Global all ones broadcast address detected */
+
+/* Transmit buffer descriptor: Address word (un-aligned, 32-bit address */
+
+/* Transmit buffer descriptor: Control word */
+
+#define GMACTXD_STA_BUFLEN_SHIFT (0) /* Bits 0-13: Length of buffer */
+#define GMACTXD_STA_BUFLEN_MASK (0x00003fff << GMACTXD_STA_BUFLEN_SHIFT)
+ /* Bit 14: Reserved */
+#define GMACTXD_STA_LAST (1 << 15) /* Bit 15: Last buffer in the current frame */
+#define GMACTXD_STA_NOCRC (1 << 16) /* Bit 16: No CRC */
+ /* Bits 17-19: Reserved */
+#define GMACTXD_STA_CKERR_SHIFT (20) /* Bits 20-22: Transmit checksum generation errors */
+#define GMACTXD_STA_CKERR_MASK (7 << GMACTXD_STA_CKERR_SHIFT)
+# define GMACTXD_STA_CKERR_OK (0 << GMACTXD_STA_CKERR_SHIFT) /* No Error */
+# define GMACTXD_STA_CKERR_VLAN (1 << GMACTXD_STA_CKERR_SHIFT) /* VLAN header error */
+# define GMACTXD_STA_CKERR_SNAP (2 << GMACTXD_STA_CKERR_SHIFT) /* SNAP header error */
+# define GMACTXD_STA_CKERR_IP (3 << GMACTXD_STA_CKERR_SHIFT) /* Bad IP type */
+# define GMACTXD_STA_CKERR_UNK (4 << GMACTXD_STA_CKERR_SHIFT) /* Not VLAN, SNAP or IP */
+# define GMACTXD_STA_CKERR_FRAG (5 << GMACTXD_STA_CKERR_SHIFT) /* Bad packet fragmentation */
+# define GMACTXD_STA_CKERR_PROTO (6 << GMACTXD_STA_CKERR_SHIFT) /* Not TCP or UDP */
+# define GMACTXD_STA_CKERR_END (7 << GMACTXD_STA_CKERR_SHIFT) /* Premature end of packet */
+ /* Bits 23-25: Reserved */
+#define GMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision */
+#define GMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit Frame Corruption due to AHB error */
+#define GMACTXD_STA_TXUR (1 << 28) /* Bit 28: Transmit underrun */
+#define GMACTXD_STA_TXERR (1 << 29) /* Bit 29: Retry limit exceeded, transmit error detected */
+#define GMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */
+#define GMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the GMAC to read from buffer */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+/* Receive buffer descriptor */
+
+struct gmac_rxdesc_s
+{
+ uint32_t addr; /* Buffer address */
+ uint32_t status; /* RX status and controls */
+};
+
+/* Transmit buffer descriptor */
+
+struct gmac_txdesc_s
+{
+ uint32_t addr; /* Buffer address */
+ uint32_t status; /* TX status and controls */
+};
+
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GMAC_H */
diff --git a/arch/arm/src/samd5e5/hardware/sam_memorymap.h b/arch/arm/src/samd5e5/hardware/sam_memorymap.h
index ef08130..e0814f1 100644
--- a/arch/arm/src/samd5e5/hardware/sam_memorymap.h
+++ b/arch/arm/src/samd5e5/hardware/sam_memorymap.h
@@ -42,7 +42,7 @@
#include <nuttx/config.h>
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
+#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(CONFIG_ARCH_CHIP_SAME5X)
# include "hardware/samd5e5_memorymap.h"
#else
# error "Unsupported SAMD5/E5 family"
diff --git a/arch/arm/src/samd5e5/hardware/sam_pinmap.h b/arch/arm/src/samd5e5/hardware/sam_pinmap.h
index ac72745..9f9189d 100644
--- a/arch/arm/src/samd5e5/hardware/sam_pinmap.h
+++ b/arch/arm/src/samd5e5/hardware/sam_pinmap.h
@@ -42,7 +42,7 @@
#include <nuttx/config.h>
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
+#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(CONFIG_ARCH_CHIP_SAME5X)
# include "hardware/samd5e5_pinmap.h"
#else
# error "Unsupported SAMD5/E5 family"
diff --git a/arch/arm/include/samd5e5/irq.h b/arch/arm/src/samd5e5/sam_ethernet.c
similarity index 50%
copy from arch/arm/include/samd5e5/irq.h
copy to arch/arm/src/samd5e5/sam_ethernet.c
index 7807757..d668911 100644
--- a/arch/arm/include/samd5e5/irq.h
+++ b/arch/arm/src/samd5e5/sam_ethernet.c
@@ -1,7 +1,7 @@
-/****************************************************************************************
- * arch/arm/include/samd5e5/irq.h
+/****************************************************************************
+ * arch/arm/src/samd5e5/sam_ethernet.c
*
- * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -31,83 +31,94 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ****************************************************************************************/
+ ****************************************************************************/
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H
-#define __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H
-
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-#include <arch/samd5e5/chip.h>
-/****************************************************************************************
+#include <debug.h>
+#include "sam_ethernet.h"
+
+#ifdef CONFIG_NET
+
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
-
-/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
- * bits in the NVIC. This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
- */
-
-/* Common Processor Exceptions (vectors 0-15) */
-
-#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
- /* Vector 0: Reset stack pointer value */
- /* Vector 1: Reset (not handler as an IRQ) */
-#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
-#define SAM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
-#define SAM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
-#define SAM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
-#define SAM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
-#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
-#define SAM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
- /* Vector 13: Reserved */
-#define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
-#define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */
-
-/* Chip-Specific External interrupts */
-
-#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
-
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
-# include <arch/samd5e5/samd5e5_irq.h>
-#else
-# error "Unsupported SAMD5/E5 family"
-#endif
+ ****************************************************************************/
-/****************************************************************************************
- * Public Types
- ****************************************************************************************/
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
-#ifndef __ASSEMBLY__
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: up_gmac_initialize
+ *
+ * Description:
+ * Initialize the GMAC driver
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
+#ifdef CONFIG_SAMD5E5_GMAC
+static inline void up_gmac_initialize(void)
{
+ int ret;
+
+ /* Initialize the GMAC driver */
+
+ ret = sam_gmac_initialize();
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_gmac_initialize failed: %d\n", ret);
+ }
+}
#else
-#define EXTERN extern
+# define up_gmac_initialize()
#endif
-/****************************************************************************************
- * Public Function Prototypes
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: up_netinitialize
+ *
+ * Description:
+ * This is the "standard" network initialization logic called from the
+ * low-level initialization logic in up_initialize.c.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
-#undef EXTERN
-#ifdef __cplusplus
+void up_netinitialize(void)
+{
+ up_gmac_initialize();
}
-#endif
-#endif
-#endif /* __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H */
+#endif /* CONFIG_NET */
diff --git a/arch/arm/src/samd5e5/sam_ethernet.h b/arch/arm/src/samd5e5/sam_ethernet.h
new file mode 100644
index 0000000..d9f6003
--- /dev/null
+++ b/arch/arm/src/samd5e5/sam_ethernet.h
@@ -0,0 +1,149 @@
+/****************************************************************************
+ * arch/arm/src/samd5e5/sam_ethernet.h
+ *
+ * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMD5E5_SAM_ETHERNET_H
+#define __ARCH_ARM_SRC_SAMD5E5_SAM_ETHERNET_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "hardware/sam_gmac.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Understood PHY types */
+
+#define SAMD5E5_PHY_DM9161 0
+#define SAMD5E5_PHY_LAN8700 1
+#define SAMD5E5_PHY_KSZ8051 2
+#define SAMD5E5_PHY_KSZ8081 3
+#define SAMD5E5_PHY_KSZ90x1 4
+
+/* Definitions for use with sam_phy_boardinitialize */
+
+# if defined(CONFIG_ETH0_PHY_DM9161)
+# define SAMD5E5_GMAC_PHY_DM9161 1
+# define SAMD5E5_GMAC_PHY_TYPE SAMD5E5_PHY_DM9161
+# elif defined(CONFIG_ETH0_PHY_LAN8700)
+# define SAMD5E5_GMAC_PHY_LAN8700 1
+# define SAMD5E5_GMAC_PHY_TYPE SAMD5E5_PHY_LAN8700
+# elif defined(CONFIG_ETH0_PHY_KSZ8051)
+# define SAMD5E5_GMAC_PHY_KSZ8051 1
+# define SAMD5E5_GMAC_PHY_TYPE SAMD5E5_PHY_KSZ8051
+# elif defined(CONFIG_ETH0_PHY_KSZ8081)
+# define SAMD5E5_GMAC_PHY_KSZ8081 1
+# define SAMD5E5_GMAC_PHY_TYPE SAMD5E5_PHY_KSZ8081
+# elif defined(CONFIG_ETH0_PHY_KSZ90x1)
+# define SAMD5E5_GMAC_PHY_KSZ90x1 1
+# define SAMD5E5_GMAC_PHY_TYPE SAMD5E5_PHY_KSZ90x1
+# else
+# error ETH0 PHY unrecognized
+# endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Function: sam_gmac_initialize
+ *
+ * Description:
+ * Initialize the GMAC driver.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ * Called very early in the initialization sequence.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMD5E5_GMAC
+int sam_gmac_initialize(void);
+#endif
+
+/****************************************************************************
+ * Function: sam_phy_boardinitialize
+ *
+ * Description:
+ * Some boards require specialized initialization of the PHY before it can
+ * be used. This may include such things as configuring GPIOs, resetting
+ * the PHY, etc. If CONFIG_SAMD5E5_GMAC_PHYINIT is defined in the
+ * configuration then the board specific logic must provide
+ * sam_phyinitialize(); The SAMD5E5 Ethernet driver will call this
+ * function one time before it first uses the PHY.
+ *
+ * Input Parameters:
+ * intf - Always zero for now.
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_SAMD5E5_GMAC_PHYINIT
+int sam_phy_boardinitialize(int intf);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_SAM_ETHERNET_H */
+
diff --git a/arch/arm/src/samd5e5/sam_gmac.c b/arch/arm/src/samd5e5/sam_gmac.c
new file mode 100644
index 0000000..8cc07e1
--- /dev/null
+++ b/arch/arm/src/samd5e5/sam_gmac.c
@@ -0,0 +1,3831 @@
+/****************************************************************************
+ * arch/arm/src/samd5e5/sam_gmac.c
+ *
+ * Copyright (C) 2013-2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * References:
+ * SAMD5E5D3 Series Data Sheet
+ * Atmel NoOS sample code.
+ *
+ * The Atmel sample code has a BSD compatible license that requires this
+ * copyright notice:
+ *
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the names NuttX nor Atmel nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <time.h>
+#include <string.h>
+#include <debug.h>
+#include <queue.h>
+#include <errno.h>
+
+#include <arpa/inet.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/wdog.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/wqueue.h>
+#include <nuttx/net/gmii.h>
+#include <nuttx/net/arp.h>
+#include <nuttx/net/netdev.h>
+#include <nuttx/net/phy.h>
+
+#ifdef CONFIG_NET_PKT
+# include <nuttx/net/pkt.h>
+#endif
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "chip.h"
+#include "hardware/sam_pinmap.h"
+#include "sam_periphclks.h"
+#include "sam_ethernet.h"
+#include "sam_port.h"
+#include <arch/board/board.h>
+
+#if defined(CONFIG_NET) && defined(CONFIG_SAMD5E5_GMAC)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* If processing is not done at the interrupt level, then work queue support
+ * is required.
+ */
+
+#if !defined(CONFIG_SCHED_WORKQUEUE)
+# error Work queue support is required
+#endif
+
+/* The low priority work queue is preferred. If it is not enabled, LPWORK
+ * will be the same as HPWORK.
+ *
+ * NOTE: However, the network should NEVER run on the high priority work
+ * queue! That queue is intended only to service short back end interrupt
+ * processing that never suspends. Suspending the high priority work queue
+ * may bring the system to its knees!
+ */
+
+#define ETHWORK LPWORK
+
+/* Number of buffer for RX */
+
+#ifndef CONFIG_SAMD5E5_GMAC_NRXBUFFERS
+# define CONFIG_SAMD5E5_GMAC_NRXBUFFERS 16
+#endif
+
+/* Number of buffer for TX */
+
+#ifndef CONFIG_SAMD5E5_GMAC_NTXBUFFERS
+# define CONFIG_SAMD5E5_GMAC_NTXBUFFERS 8
+#endif
+
+#undef CONFIG_SAMD5E5_GMAC_NBC
+
+#ifndef CONFIG_SAMD5E5_GMAC_PHYADDR
+# error "CONFIG_SAMD5E5_GMAC_PHYADDR must be defined in the NuttX configuration"
+#endif
+
+/* PHY definitions */
+
+#ifdef SAMD5E5_GMAC_PHY_KSZ8081
+# define GMII_OUI_MSB 0x0022
+# define GMII_OUI_LSB GMII_PHYID2_OUI(5)
+#else
+# error Unknown PHY
+#endif
+
+/* GMAC buffer sizes, number of buffers, and number of descriptors. *********/
+
+#define GMAC_RX_UNITSIZE 128 /* Fixed size for RX buffer */
+#define GMAC_TX_UNITSIZE CONFIG_NET_ETH_PKTSIZE /* MAX size for Ethernet packet */
+
+/* The MAC can support frame lengths up to 1536 bytes */
+
+#define GMAC_MAX_FRAMELEN 1536
+#if CONFIG_NET_ETH_PKTSIZE > GMAC_MAX_FRAMELEN
+# error CONFIG_NET_ETH_PKTSIZE is too large
+#endif
+
+/* We need at least one more free buffer than transmit buffers */
+
+#define SAM_GMAC_NFREEBUFFERS (CONFIG_SAMD5E5_GMAC_NTXBUFFERS+1)
+
+/* Extremely detailed register debug that you would normally never want
+ * enabled.
+ */
+
+#ifndef CONFIG_DEBUG_NET_INFO
+# undef CONFIG_SAMD5E5_GMAC_REGDEBUG
+#endif
+
+#ifdef CONFIG_NET_DUMPPACKET
+# define sam_dumppacket(m,a,n) lib_dumpbuffer(m,a,n)
+#else
+# define sam_dumppacket(m,a,n)
+#endif
+
+/* Timing *******************************************************************/
+
+/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
+ * second
+ */
+
+#define SAM_WDDELAY (1*CLK_TCK)
+
+/* TX timeout = 1 minute */
+
+#define SAM_TXTIMEOUT (60*CLK_TCK)
+
+/* PHY read/write delays in loop counts */
+
+#define PHY_RETRY_MAX 300000
+
+/* Helpers ******************************************************************/
+
+/* This is a helper pointer for accessing the contents of the GMAC
+ * header
+ */
+
+#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* The sam_gmac_s encapsulates all state information for the GMAC peripheral */
+
+struct sam_gmac_s
+{
+ uint8_t ifup : 1; /* true:ifup false:ifdown */
+ WDOG_ID txpoll; /* TX poll timer */
+ WDOG_ID txtimeout; /* TX timeout timer */
+ struct work_s irqwork; /* For deferring interrupt work to the work queue */
+ struct work_s pollwork; /* For deferring poll work to the work queue */
+
+ /* This holds the information visible to the NuttX network */
+
+ struct net_driver_s dev; /* Interface understood by the network */
+
+ /* Used to track transmit and receive descriptors */
+
+ uint8_t phyaddr; /* PHY address (pre-defined by pins on reset) */
+ uint16_t txhead; /* Circular buffer head index */
+ uint16_t txtail; /* Circualr buffer tail index */
+ uint16_t rxndx; /* RX index for current processing RX descriptor */
+
+ uint8_t *rxbuffer; /* Allocated RX buffers */
+ uint8_t *txbuffer; /* Allocated TX buffers */
+ struct gmac_rxdesc_s *rxdesc; /* Allocated RX descriptors */
+ struct gmac_txdesc_s *txdesc; /* Allocated TX descriptors */
+
+ /* Debug stuff */
+
+#ifdef CONFIG_SAMD5E5_GMAC_REGDEBUG
+ bool wrlast; /* Last was a write */
+ uintptr_t addrlast; /* Last address */
+ uint32_t vallast; /* Last value */
+ int ntimes; /* Number of times */
+#endif
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* The driver state singleton */
+
+static struct sam_gmac_s g_gmac;
+
+/* A single packet buffer is used
+ *
+ * REVISIT: It might be possible to use this option to send and receive
+ * messages directly into the DMA buffers, saving a copy. There might be
+ * complications on the receiving side, however, where buffers may wrap
+ * and where the size of the received frame will typically be smaller than
+ * a full packet.
+ */
+
+static uint8_t g_pktbuf[MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE];
+
+#ifdef CONFIG_SAMD5E5_GMAC_PREALLOCATE
+/* Preallocated data */
+
+/* TX descriptors list */
+
+static struct gmac_txdesc_s g_txdesc[CONFIG_SAMD5E5_GMAC_NTXBUFFERS]
+ __attribute__((aligned(8)));
+
+/* RX descriptors list */
+
+static struct gmac_rxdesc_s g_rxdesc[CONFIG_SAMD5E5_GMAC_NRXBUFFERS]
+ __attribute__((aligned(8)));
+
+/* Transmit Buffers
+ *
+ * Section 3.6 of AMBA 2.0 spec states that burst should not cross 1K Boundaries.
+ * Receive buffer manager writes are burst of 2 words => 3 lsb bits of the address
+ * shall be set to 0
+ */
+
+static uint8_t g_txbuffer[CONFIG_SAMD5E5_GMAC_NTXBUFFERS * GMAC_TX_UNITSIZE]
+ __attribute__((aligned(8)));
+
+/* Receive Buffers */
+
+static uint8_t g_rxbuffer[CONFIG_SAMD5E5_GMAC_NRXBUFFERS * GMAC_RX_UNITSIZE]
+ __attribute__((aligned(8)));
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Register operations ******************************************************/
+
+#if defined(CONFIG_SAMD5E5_GMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+static bool sam_checkreg(struct sam_gmac_s *priv, bool wr,
+ uint32_t regval, uintptr_t address);
+static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t addr);
+static void sam_putreg(struct sam_gmac_s *priv, uintptr_t addr, uint32_t val);
+#else
+# define sam_getreg(priv,addr) getreg32(addr)
+# define sam_putreg(priv,addr,val) putreg32(val,addr)
+#endif
+
+/* Buffer management */
+
+static uint16_t sam_txinuse(struct sam_gmac_s *priv);
+static uint16_t sam_txfree(struct sam_gmac_s *priv);
+static int sam_buffer_initialize(struct sam_gmac_s *priv);
+static void sam_buffer_free(struct sam_gmac_s *priv);
+
+/* Common TX logic */
+
+static int sam_transmit(struct sam_gmac_s *priv);
+static int sam_txpoll(struct net_driver_s *dev);
+static void sam_dopoll(struct sam_gmac_s *priv);
+
+/* Interrupt handling */
+
+static int sam_recvframe(struct sam_gmac_s *priv);
+static void sam_receive(struct sam_gmac_s *priv);
+static void sam_txdone(struct sam_gmac_s *priv);
+
+static void sam_interrupt_work(FAR void *arg);
+static int sam_gmac_interrupt(int irq, void *context, FAR void *arg);
+
+/* Watchdog timer expirations */
+
+static void sam_txtimeout_work(FAR void *arg);
+static void sam_txtimeout_expiry(int argc, uint32_t arg, ...);
+
+static void sam_poll_work(FAR void *arg);
+static void sam_poll_expiry(int argc, uint32_t arg, ...);
+
+/* NuttX callback functions */
+
+static int sam_ifup(struct net_driver_s *dev);
+static int sam_ifdown(struct net_driver_s *dev);
+
+static void sam_txavail_work(FAR void *arg);
+static int sam_txavail(struct net_driver_s *dev);
+
+#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
+static unsigned int sam_hashindx(const uint8_t *mac);
+static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac);
+#endif
+#ifdef CONFIG_NET_MCASTGROUP
+static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac);
+#endif
+
+#ifdef CONFIG_NETDEV_IOCTL
+static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg);
+#endif
+
+/* PHY Initialization */
+
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
+static void sam_phydump(struct sam_gmac_s *priv);
+#else
+# define sam_phydump(priv)
+#endif
+
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
+static int sam_phyintenable(struct sam_gmac_s *priv);
+#endif
+static void sam_enablemdio(struct sam_gmac_s *priv);
+static void sam_disablemdio(struct sam_gmac_s *priv);
+static int sam_phywait(struct sam_gmac_s *priv);
+static int sam_phyreset(struct sam_gmac_s *priv);
+static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr);
+static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
+ uint8_t regaddr, uint16_t *phyval);
+static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
+ uint8_t regaddr, uint16_t phyval);
+#ifdef CONFIG_SAMD5E5_GMAC_AUTONEG
+static int sam_autonegotiate(struct sam_gmac_s *priv);
+#else
+static void sam_linkspeed(struct sam_gmac_s *priv);
+#endif
+static void sam_mdcclock(struct sam_gmac_s *priv);
+static int sam_phyinit(struct sam_gmac_s *priv);
+
+/* GMAC Initialization */
+
+static void sam_txreset(struct sam_gmac_s *priv);
+static void sam_rxreset(struct sam_gmac_s *priv);
+static void sam_gmac_reset(struct sam_gmac_s *priv);
+static void sam_macaddress(struct sam_gmac_s *priv);
+#ifdef CONFIG_NET_ICMPv6
+static void sam_ipv6multicast(struct sam_gmac_s *priv);
+#endif
+static int sam_gmac_configure(struct sam_gmac_s *priv);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_checkreg
+ *
+ * Description:
+ * Check if the current register access is a duplicate of the preceding.
+ *
+ * Input Parameters:
+ * regval - The value to be written
+ * address - The address of the register to write to
+ *
+ * Returned Value:
+ * true: This is the first register access of this type.
+ * flase: This is the same as the preceding register access.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMD5E5_GMAC_REGDEBUG
+static bool sam_checkreg(struct sam_gmac_s *priv, bool wr, uint32_t regval,
+ uintptr_t address)
+{
+ if (wr == priv->wrlast && /* Same kind of access? */
+ regval == priv->vallast && /* Same value? */
+ address == priv->addrlast) /* Same address? */
+ {
+ /* Yes, then just keep a count of the number of times we did this. */
+
+ priv->ntimes++;
+ return false;
+ }
+ else
+ {
+ /* Did we do the previous operation more than once? */
+
+ if (priv->ntimes > 0)
+ {
+ /* Yes... show how many times we did it */
+
+ ninfo("...[Repeats %d times]...\n", priv->ntimes);
+ }
+
+ /* Save information about the new access */
+
+ priv->wrlast = wr;
+ priv->vallast = regval;
+ priv->addrlast = address;
+ priv->ntimes = 0;
+ }
+
+ /* Return true if this is the first time that we have done this operation */
+
+ return true;
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_getreg
+ *
+ * Description:
+ * Read any 32-bit register using an absolute
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMD5E5_GMAC_REGDEBUG
+static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t address)
+{
+ uint32_t regval = getreg32(address);
+
+ if (sam_checkreg(priv, false, regval, address))
+ {
+ ninfo("%08x->%08x\n", address, regval);
+ }
+
+ return regval;
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_putreg
+ *
+ * Description:
+ * Write to any 32-bit register using an absolute address
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMD5E5_GMAC_REGDEBUG
+static void sam_putreg(struct sam_gmac_s *priv, uintptr_t address,
+ uint32_t regval)
+{
+ if (sam_checkreg(priv, true, regval, address))
+ {
+ ninfo("%08x<-%08x\n", address, regval);
+ }
+
+ putreg32(regval, address);
+}
+#endif
+
+/****************************************************************************
+ * Function: sam_txinuse
+ *
+ * Description:
+ * Return the number of TX buffers in-use
+ *
+ * Input Parameters:
+ * priv - The GMAC driver state
+ *
+ * Returned Value:
+ * The number of TX buffers in-use
+ *
+ ****************************************************************************/
+
+static uint16_t sam_txinuse(struct sam_gmac_s *priv)
+{
+ uint32_t txhead32 = (uint32_t)priv->txhead;
+ if ((uint32_t)priv->txtail > txhead32)
+ {
+ txhead32 += CONFIG_SAMD5E5_GMAC_NTXBUFFERS;
+ }
+
+ return (uint16_t)(txhead32 - (uint32_t)priv->txtail);
+}
+
+/****************************************************************************
+ * Function: sam_txfree
+ *
+ * Description:
+ * Return the number of TX buffers available
+ *
+ * Input Parameters:
+ * priv - The GMAC driver state
+ *
+ * Returned Value:
+ * The number of TX buffers available
+ *
+ ****************************************************************************/
+
+static uint16_t sam_txfree(struct sam_gmac_s *priv)
+{
+ /* The number available is equal to the total number of buffers, minus the
+ * number of buffers in use. Notice that that actual number of buffers is
+ * the configured size minus 1.
+ */
+
+ return (CONFIG_SAMD5E5_GMAC_NTXBUFFERS - 1) - sam_txinuse(priv);
+}
+
+/****************************************************************************
+ * Function: sam_buffer_initialize
+ *
+ * Description:
+ * Allocate aligned TX and RX descriptors and buffers. For the case of
+ * pre-allocated structures, the function degenerates to a few assignements.
+ *
+ * Input Parameters:
+ * priv - The GMAC driver state
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ * Called very early in the initialization sequence.
+ *
+ ****************************************************************************/
+
+static int sam_buffer_initialize(struct sam_gmac_s *priv)
+{
+#ifdef CONFIG_SAMD5E5_GMAC_PREALLOCATE
+ /* Use pre-allocated buffers */
+
+ priv->txdesc = g_txdesc;
+ priv->rxdesc = g_rxdesc;
+ priv->txbuffer = g_txbuffer;
+ priv->rxbuffer = g_rxbuffer;
+
+#else
+ size_t allocsize;
+
+ /* Allocate buffers */
+
+ allocsize = CONFIG_SAMD5E5_GMAC_NTXBUFFERS * sizeof(struct gmac_txdesc_s);
+ priv->txdesc = (struct gmac_txdesc_s *)kmm_memalign(8, allocsize);
+ if (!priv->txdesc)
+ {
+ nerr("ERROR: Failed to allocate TX descriptors\n");
+ return -ENOMEM;
+ }
+
+ memset(priv->txdesc, 0, allocsize);
+
+ allocsize = CONFIG_SAMD5E5_GMAC_NRXBUFFERS * sizeof(struct gmac_rxdesc_s);
+ priv->rxdesc = (struct gmac_rxdesc_s *)kmm_memalign(8, allocsize);
+ if (!priv->rxdesc)
+ {
+ nerr("ERROR: Failed to allocate RX descriptors\n");
+ sam_buffer_free(priv);
+ return -ENOMEM;
+ }
+
+ memset(priv->rxdesc, 0, allocsize);
+
+ allocsize = CONFIG_SAMD5E5_GMAC_NTXBUFFERS * GMAC_TX_UNITSIZE;
+ priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
+ if (!priv->txbuffer)
+ {
+ nerr("ERROR: Failed to allocate TX buffer\n");
+ sam_buffer_free(priv);
+ return -ENOMEM;
+ }
+
+ allocsize = CONFIG_SAMD5E5_GMAC_NRXBUFFERS * GMAC_RX_UNITSIZE;
+ priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
+ if (!priv->rxbuffer)
+ {
+ nerr("ERROR: Failed to allocate RX buffer\n");
+ sam_buffer_free(priv);
+ return -ENOMEM;
+ }
+
+#endif
+
+ DEBUGASSERT(((uintptr_t)priv->rxdesc & 7) == 0 &&
+ ((uintptr_t)priv->rxbuffer & 7) == 0 &&
+ ((uintptr_t)priv->txdesc & 7) == 0 &&
+ ((uintptr_t)priv->txbuffer & 7) == 0);
+ return OK;
+}
+
+/****************************************************************************
+ * Function: sam_buffer_free
+ *
+ * Description:
+ * Free aligned TX and RX descriptors and buffers. For the case of
+ * pre-allocated structures, the function does nothing.
+ *
+ * Input Parameters:
+ * priv - The GMAC driver state
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_buffer_free(struct sam_gmac_s *priv)
+{
+#ifndef CONFIG_SAMD5E5_GMAC_PREALLOCATE
+ /* Free allocated buffers */
+
+ if (priv->txdesc)
+ {
+ kmm_free(priv->txdesc);
+ priv->txdesc = NULL;
+ }
+
+ if (priv->rxdesc)
+ {
+ kmm_free(priv->rxdesc);
+ priv->rxdesc = NULL;
+ }
+
+ if (priv->txbuffer)
+ {
+ kmm_free(priv->txbuffer);
+ priv->txbuffer = NULL;
+ }
+
+ if (priv->rxbuffer)
+ {
+ kmm_free(priv->rxbuffer);
+ priv->rxbuffer = NULL;
+ }
+#endif
+}
+
+/****************************************************************************
+ * Function: sam_transmit
+ *
+ * Description:
+ * Start hardware transmission. Called either from the TX done interrupt
+ * handling or from watchdog based polling.
+ *
+ * Input Parameters:
+ * priv - Reference to the driver state structure
+ *
+ * Returned Value:
+ * OK on success; a negated errno on failure
+ *
+ * Assumptions:
+ * May or may not be called from an interrupt handler. In either case,
+ * global interrupts are disabled, either explicitly or indirectly through
+ * interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static int sam_transmit(struct sam_gmac_s *priv)
+{
+ struct net_driver_s *dev = &priv->dev;
+ volatile struct gmac_txdesc_s *txdesc;
+ uintptr_t virtaddr;
+ uint32_t regval;
+ uint32_t status;
+
+ ninfo("d_len: %d txhead: %d txtail: %d\n",
+ dev->d_len, priv->txhead, priv->txtail);
+ sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
+
+ /* Check parameter */
+
+ if (dev->d_len > GMAC_TX_UNITSIZE)
+ {
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
+ return -EINVAL;
+ }
+
+ /* Pointer to the current TX descriptor */
+
+ txdesc = &priv->txdesc[priv->txhead];
+
+ /* If no free TX descriptor, buffer can't be sent */
+
+ if (sam_txfree(priv) < 1)
+ {
+ nerr("ERROR: No free TX descriptors\n");
+ return -EBUSY;
+ }
+
+ /* Setup/Copy data to transmition buffer */
+
+ if (dev->d_len > 0)
+ {
+ /* Driver managed the ring buffer */
+
+ virtaddr = txdesc->addr;
+ memcpy((void *)virtaddr, dev->d_buf, dev->d_len);
+ up_clean_dcache((uint32_t)virtaddr, (uint32_t)virtaddr + dev->d_len);
+ }
+
+ /* Update TX descriptor status. */
+
+ status = dev->d_len | GMACTXD_STA_LAST;
+ if (priv->txhead == CONFIG_SAMD5E5_GMAC_NTXBUFFERS - 1)
+ {
+ status |= GMACTXD_STA_WRAP;
+ }
+
+ /* Update the descriptor status and flush the updated value to RAM */
+
+ txdesc->status = status;
+ up_clean_dcache((uint32_t)txdesc,
+ (uint32_t)txdesc + sizeof(struct gmac_txdesc_s));
+
+ /* Increment the head index */
+
+ if (++priv->txhead >= CONFIG_SAMD5E5_GMAC_NTXBUFFERS)
+ {
+ priv->txhead = 0;
+ }
+
+ /* Now start transmission (if it is not already done) */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCR);
+ regval |= GMAC_NCR_TSTART;
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+ /* Setup the TX timeout watchdog (perhaps restarting the timer) */
+
+ (void)wd_start(priv->txtimeout, SAM_TXTIMEOUT, sam_txtimeout_expiry, 1,
+ (uint32_t)priv);
+
+ /* Set d_len to zero meaning that the d_buf[] packet buffer is again
+ * available.
+ */
+
+ dev->d_len = 0;
+
+ /* If we have no more available TX descriptors, then we must disable the
+ * RCOMP interrupt to stop further RX processing. Why? Because EACH RX
+ * packet that is dispatched is also an opportunity to reply with a TX
+ * packet. So, if we cannot handle an RX packet reply, then we disable
+ * all RX packet processing.
+ */
+
+ if (sam_txfree(priv) < 1)
+ {
+ ninfo("Disabling RX interrupts\n");
+ sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_RCOMP);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Function: sam_txpoll
+ *
+ * Description:
+ * The transmitter is available, check if the network has any outgoing packets ready
+ * to send. This is a callback from devif_poll(). devif_poll() may be called:
+ *
+ * 1. When the preceding TX packet send is complete,
+ * 2. When the preceding TX packet send timesout and the interface is reset
+ * 3. During normal TX polling
+ *
+ * Input Parameters:
+ * dev - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ * OK on success; a negated errno on failure
+ *
+ * Assumptions:
+ * May or may not be called from an interrupt handler. In either case,
+ * global interrupts are disabled, either explicitly or indirectly through
+ * interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static int sam_txpoll(struct net_driver_s *dev)
+{
+ struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
+
+ /* If the polling resulted in data that should be sent out on the network,
+ * the field d_len is set to a value > 0.
+ */
+
+ if (priv->dev.d_len > 0)
+ {
+ /* Look up the destination MAC address and add it to the Ethernet
+ * header.
+ */
+
+#ifdef CONFIG_NET_IPv4
+#ifdef CONFIG_NET_IPv6
+ if (IFF_IS_IPv4(priv->dev.d_flags))
+#endif
+ {
+ arp_out(&priv->dev);
+ }
+#endif /* CONFIG_NET_IPv4 */
+
+#ifdef CONFIG_NET_IPv6
+#ifdef CONFIG_NET_IPv4
+ else
+#endif
+ {
+ neighbor_out(&priv->dev);
+ }
+#endif /* CONFIG_NET_IPv6 */
+
+ if (!devif_loopback(&priv->dev))
+ {
+ /* Send the packet */
+
+ sam_transmit(priv);
+
+ /* Check if there are any free TX descriptors. We cannot perform
+ * the TX poll if we do not have buffering for another packet.
+ */
+
+ if (sam_txfree(priv) == 0)
+ {
+ /* We have to terminate the poll if we have no more descriptors
+ * available for another transfer.
+ */
+
+ return -EBUSY;
+ }
+ }
+ }
+
+ /* If zero is returned, the polling will continue until all connections have
+ * been examined.
+ */
+
+ return 0;
+}
+
+/****************************************************************************
+ * Function: sam_dopoll
+ *
+ * Description:
+ * The function is called in order to perform an out-of-sequence TX poll.
+ * This is done:
+ *
+ * 1. After completion of a transmission (sam_txdone),
+ * 2. When new TX data is available (sam_txavail), and
+ * 3. After a TX timeout to restart the sending process (sam_txtimeout_expiry).
+ *
+ * Input Parameters:
+ * priv - Reference to the driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static void sam_dopoll(struct sam_gmac_s *priv)
+{
+ struct net_driver_s *dev = &priv->dev;
+
+ /* Check if there are any free TX descriptors. We cannot perform the
+ * TX poll if we do not have buffering for another packet.
+ */
+
+ if (sam_txfree(priv) > 0)
+ {
+ /* If we have the descriptor, then poll the network for new XMIT data. */
+
+ (void)devif_poll(dev, sam_txpoll);
+ }
+}
+
+/****************************************************************************
+ * Function: sam_recvframe
+ *
+ * Description:
+ * The function is called when a frame is received. It scans the RX
+ * descriptors of the received frame and assembles the full packet/
+ *
+ * NOTE: This function will silently discard any packets containing errors.
+ *
+ * Input Parameters:
+ * priv - Reference to the driver state structure
+ *
+ * Returned Value:
+ * OK if a packet was successfully returned; -EAGAIN if there are no
+ * further packets available
+ *
+ * Assumptions:
+ * - Global interrupts are disabled by interrupt handling logic.
+ * - The RX descriptor D-cache list has been invalided to force fetching
+ * from RAM.
+ *
+ ****************************************************************************/
+
+static int sam_recvframe(struct sam_gmac_s *priv)
+{
+ volatile struct gmac_rxdesc_s *rxdesc;
+ struct net_driver_s *dev;
+ const uint8_t *src;
+ uint8_t *dest;
+ uintptr_t physaddr;
+ uint32_t rxndx;
+ uint32_t pktlen;
+ uint16_t copylen;
+ bool isframe;
+
+ /* Process received RX descriptor. The ownership bit is set by the GMAC
+ * once it has successfully written a frame to memory.
+ */
+
+ dev = &priv->dev;
+ dev->d_len = 0;
+
+ dest = dev->d_buf;
+ pktlen = 0;
+
+ rxndx = priv->rxndx;
+ rxdesc = &priv->rxdesc[rxndx];
+ isframe = false;
+
+ /* Invalidate the RX descriptor to force re-fetching from RAM */
+
+ up_invalidate_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
+
+ ninfo("rxndx: %d\n", rxndx);
+
+ while ((rxdesc->addr & GMACRXD_ADDR_OWNER) != 0)
+ {
+ /* The start of frame bit indicates the beginning of a frame. Discard
+ * any previous fragments.
+ */
+
+ if ((rxdesc->status & GMACRXD_STA_SOF) != 0)
+ {
+ /* Skip previous fragments */
+
+ while (rxndx != priv->rxndx)
+ {
+ /* Give ownership back to the GMAC */
+
+ rxdesc = &priv->rxdesc[priv->rxndx];
+ rxdesc->addr &= ~(GMACRXD_ADDR_OWNER);
+
+ /* Flush the modified RX descriptor to RAM */
+
+ up_clean_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc +
+ sizeof(struct gmac_rxdesc_s));
+
+ /* Increment the RX index */
+
+ if (++priv->rxndx >= CONFIG_SAMD5E5_GMAC_NRXBUFFERS)
+ {
+ priv->rxndx = 0;
+ }
+ }
+
+ /* Reset the packet data pointer and packet length */
+
+ dest = dev->d_buf;
+ pktlen = 0;
+
+ /* Start to gather buffers into the packet buffer */
+
+ isframe = true;
+ }
+
+ /* Increment the working index */
+
+ if (++rxndx >= CONFIG_SAMD5E5_GMAC_NRXBUFFERS)
+ {
+ rxndx = 0;
+ }
+
+ /* Copy data into the packet buffer */
+
+ if (isframe)
+ {
+ if (rxndx == priv->rxndx)
+ {
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
+ do
+ {
+ /* Give ownership back to the GMAC */
+
+ rxdesc = &priv->rxdesc[priv->rxndx];
+ rxdesc->addr &= ~(GMACRXD_ADDR_OWNER);
+
+ /* Flush the modified RX descriptor to RAM */
+
+ up_clean_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc +
+ sizeof(struct gmac_rxdesc_s));
+
+ /* Increment the RX index */
+
+ if (++priv->rxndx >= CONFIG_SAMD5E5_GMAC_NRXBUFFERS)
+ {
+ priv->rxndx = 0;
+ }
+ }
+ while (rxndx != priv->rxndx);
+ return -EIO;
+ }
+
+ /* Get the number of bytes to copy from the buffer */
+
+ copylen = GMAC_RX_UNITSIZE;
+ if ((pktlen + copylen) > CONFIG_NET_ETH_PKTSIZE)
+ {
+ copylen = CONFIG_NET_ETH_PKTSIZE - pktlen;
+ }
+
+ /* Get the data source. Invalidate the source memory region to
+ * force reload from RAM.
+ */
+
+ physaddr = (uintptr_t)(rxdesc->addr & GMACRXD_ADDR_MASK);
+ src = (const uint8_t *)physaddr;
+
+ up_invalidate_dcache((uintptr_t)src, (uintptr_t)src + copylen);
+
+ /* And do the copy */
+
+ memcpy(dest, src, copylen);
+ dest += copylen;
+ pktlen += copylen;
+
+ /* If the end of frame has been received, return the data */
+
+ if ((rxdesc->status & GMACRXD_STA_EOF) != 0)
+ {
+ /* Frame size from the GMAC */
+
+ dev->d_len = (rxdesc->status & GMACRXD_STA_FRLEN_MASK);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+
+ /* All data have been copied in the application frame buffer,
+ * release the RX descriptor
+ */
+
+ while (priv->rxndx != rxndx)
+ {
+ /* Give ownership back to the GMAC */
+
+ rxdesc = &priv->rxdesc[priv->rxndx];
+ rxdesc->addr &= ~(GMACRXD_ADDR_OWNER);
+
+ /* Flush the modified RX descriptor to RAM */
+
+ up_clean_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc +
+ sizeof(struct gmac_rxdesc_s));
+
+ /* Increment the RX index */
+
+ if (++priv->rxndx >= CONFIG_SAMD5E5_GMAC_NRXBUFFERS)
+ {
+ priv->rxndx = 0;
+ }
+ }
+
+ /* Check if the device packet buffer was large enough to accept
+ * all of the data.
+ */
+
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+
+ if (pktlen < dev->d_len)
+ {
+ nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+ return -E2BIG;
+ }
+
+ return OK;
+ }
+ }
+
+ /* We have not encount the SOF yet... discard this fragment and keep looking */
+
+ else
+ {
+ /* Give ownership back to the GMAC */
+
+ rxdesc->addr &= ~(GMACRXD_ADDR_OWNER);
+
+ /* Flush the modified RX descriptor to RAM */
+
+ up_clean_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc +
+ sizeof(struct gmac_rxdesc_s));
+
+ priv->rxndx = rxndx;
+ }
+
+ /* Process the next buffer */
+
+ rxdesc = &priv->rxdesc[rxndx];
+
+ /* Invalidate the RX descriptor to force re-fetching from RAM */
+
+ up_invalidate_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
+ }
+
+ /* isframe indicates that we have found a SOF. If we've received a SOF,
+ * but not an EOF in the sequential buffers we own, it must mean that we
+ * have a partial packet. This should only happen if there was a Buffer
+ * Not Available (BNA) error. When bursts of data come in, quickly
+ * filling the available buffers, before our interrupts can even service
+ * them. Eventually, the ring buffer loops back on itself and the
+ * peripheral sees it cannot write the next fragment of the packet.
+ *
+ * In this case, we keep the rxndx at the start of the last frame, since
+ * the peripheral will finish writing the packet there next.
+ */
+
+ if (!isframe)
+ {
+ priv->rxndx = rxndx;
+ }
+
+ ninfo("rxndx: %d\n", priv->rxndx);
+ return -EAGAIN;
+}
+
+/****************************************************************************
+ * Function: sam_receive
+ *
+ * Description:
+ * An interrupt was received indicating the availability of onr or more
+ * new RX packets in FIFO memory.
+ *
+ * Input Parameters:
+ * priv - Reference to the driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static void sam_receive(struct sam_gmac_s *priv)
+{
+ struct net_driver_s *dev = &priv->dev;
+
+ /* Loop while while sam_recvframe() successfully retrieves valid
+ * GMAC frames.
+ */
+
+ while (sam_recvframe(priv) == OK)
+ {
+ sam_dumppacket("Received packet", dev->d_buf, dev->d_len);
+
+ /* Check if the packet is a valid size for the network buffer configuration
+ * (this should not happen)
+ */
+
+ if (dev->d_len > CONFIG_NET_ETH_PKTSIZE)
+ {
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+ continue;
+ }
+
+#ifdef CONFIG_NET_PKT
+ /* When packet sockets are enabled, feed the frame into the packet tap */
+
+ pkt_input(&priv->dev);
+#endif
+
+ /* We only accept IP packets of the configured type and ARP packets */
+
+#ifdef CONFIG_NET_IPv4
+ if (BUF->type == HTONS(ETHTYPE_IP))
+ {
+ ninfo("IPv4 frame\n");
+
+ /* Handle ARP on input then give the IPv4 packet to the network
+ * layer
+ */
+
+ arp_ipin(&priv->dev);
+ ipv4_input(&priv->dev);
+
+ /* If the above function invocation resulted in data that should be
+ * sent out on the network, the field d_len will set to a value > 0.
+ */
+
+ if (priv->dev.d_len > 0)
+ {
+ /* Update the Ethernet header with the correct MAC address */
+
+#ifdef CONFIG_NET_IPv6
+ if (IFF_IS_IPv4(priv->dev.d_flags))
+#endif
+ {
+ arp_out(&priv->dev);
+ }
+#ifdef CONFIG_NET_IPv6
+ else
+ {
+ neighbor_out(&priv->dev);
+ }
+#endif
+
+ /* And send the packet */
+
+ sam_transmit(priv);
+ }
+ }
+ else
+#endif
+#ifdef CONFIG_NET_IPv6
+ if (BUF->type == HTONS(ETHTYPE_IP6))
+ {
+ ninfo("Iv6 frame\n");
+
+ /* Give the IPv6 packet to the network layer */
+
+ ipv6_input(&priv->dev);
+
+ /* If the above function invocation resulted in data that should be
+ * sent out on the network, the field d_len will set to a value > 0.
+ */
+
+ if (priv->dev.d_len > 0)
+ {
+ /* Update the Ethernet header with the correct MAC address */
+
+#ifdef CONFIG_NET_IPv4
+ if (IFF_IS_IPv4(priv->dev.d_flags))
+ {
+ arp_out(&priv->dev);
+ }
+ else
+#endif
+#ifdef CONFIG_NET_IPv6
+ {
+ neighbor_out(&priv->dev);
+ }
+#endif
+
+ /* And send the packet */
+
+ sam_transmit(priv);
+ }
+ }
+ else
+#endif
+#ifdef CONFIG_NET_ARP
+ if (BUF->type == htons(ETHTYPE_ARP))
+ {
+ ninfo("ARP frame\n");
+
+ /* Handle ARP packet */
+
+ arp_arpin(&priv->dev);
+
+ /* If the above function invocation resulted in data that should be
+ * sent out on the network, the field d_len will set to a value > 0.
+ */
+
+ if (priv->dev.d_len > 0)
+ {
+ sam_transmit(priv);
+ }
+ }
+ else
+#endif
+ {
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+ }
+ }
+}
+
+/****************************************************************************
+ * Function: sam_txdone
+ *
+ * Description:
+ * An interrupt was received indicating that one or more frames have
+ * completed transmission.
+ *
+ * Input Parameters:
+ * priv - Reference to the driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void sam_txdone(struct sam_gmac_s *priv)
+{
+ struct gmac_txdesc_s *txdesc;
+
+ /* Are there any outstanding transmissions? Loop until either (1) all of
+ * the TX descriptors have been examined, or (2) until we encounter the
+ * first descriptor that is still in use by the hardware.
+ */
+
+ while (priv->txhead != priv->txtail)
+ {
+ /* Yes.. check the next buffer at the tail of the list */
+
+ txdesc = &priv->txdesc[priv->txtail];
+ up_invalidate_dcache((uintptr_t)txdesc,
+ (uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
+
+ /* Is this TX descriptor still in use? */
+
+ if ((txdesc->status & GMACTXD_STA_USED) == 0)
+ {
+ /* Yes.. the descriptor is still in use. However, I have seen a
+ * case (only repeatable on start-up) where the USED bit is never
+ * set. Yikes! If we have encountered the first still busy
+ * descriptor, then we should also have TQBD equal to the descriptor
+ * address. If it is not, then treat is as used anyway.
+ */
+
+#warning REVISIT
+ if (priv->txtail == 0 &&
+ (uintptr_t)txdesc != sam_getreg(priv, SAM_GMAC_TBQB))
+ {
+ txdesc->status = (uint32_t)GMACTXD_STA_USED;
+ up_clean_dcache((uintptr_t)txdesc,
+ (uintptr_t)txdesc + sizeof(struct gmac_txdesc_s));
+ }
+ else
+ {
+ /* Otherwise, the descriptor is truly in use. Break out of the
+ * loop now.
+ */
+
+ break;
+ }
+ }
+
+ /* Increment the tail index */
+
+ if (++priv->txtail >= CONFIG_SAMD5E5_GMAC_NTXBUFFERS)
+ {
+ /* Wrap to the beginning of the TX descriptor list */
+
+ priv->txtail = 0;
+ }
+
+ /* At least one TX descriptor is available. Re-enable RX interrupts.
+ * RX interrupts may previously have been disabled when we ran out of
+ * TX descriptors (see comments in sam_transmit()).
+ */
+
+ sam_putreg(priv, SAM_GMAC_IER, GMAC_INT_RCOMP);
+ }
+
+ /* Then poll the network for new XMIT data */
+
+ sam_dopoll(priv);
+}
+
+/****************************************************************************
+ * Function: sam_interrupt_work
+ *
+ * Description:
+ * Perform interrupt related work from the worker thread
+ *
+ * Input Parameters:
+ * arg - The argument passed when work_queue() was called.
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ * Ethernet interrupts are disabled
+ *
+ ****************************************************************************/
+
+static void sam_interrupt_work(FAR void *arg)
+{
+ FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg;
+ uint32_t isr;
+ uint32_t rsr;
+ uint32_t tsr;
+ uint32_t imr;
+ uint32_t regval;
+ uint32_t pending;
+ uint32_t clrbits;
+
+ /* Process pending Ethernet interrupts */
+
+ net_lock();
+ isr = sam_getreg(priv, SAM_GMAC_ISR);
+ rsr = sam_getreg(priv, SAM_GMAC_RSR);
+ tsr = sam_getreg(priv, SAM_GMAC_TSR);
+ imr = sam_getreg(priv, SAM_GMAC_IMR);
+
+ pending = isr & ~(imr | GMAC_INT_UNUSED);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
+
+ /* Check for the completion of a transmission. This should be done before
+ * checking for received data (because receiving can cause another transmission
+ * before we had a chance to handle the last one).
+ *
+ * ISR:TCOMP is set when a frame has been transmitted. Cleared on read.
+ * TSR:COMP is set when a frame has been transmitted. Cleared by writing a
+ * one to this bit.
+ */
+
+ if ((pending & GMAC_INT_TCOMP) != 0 || (tsr & GMAC_TSR_TXCOMP) != 0)
+ {
+ /* A frame has been transmitted */
+
+ clrbits = GMAC_TSR_TXCOMP;
+
+ /* Check for Retry Limit Exceeded (RLE) */
+
+ if ((tsr & GMAC_TSR_RLE) != 0)
+ {
+ /* Status RLE & Number of discarded buffers */
+
+ clrbits = GMAC_TSR_RLE | sam_txinuse(priv);
+ sam_txreset(priv);
+
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+
+ regval = sam_getreg(priv, SAM_GMAC_NCR);
+ regval |= GMAC_NCR_TXEN;
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+ }
+
+ /* Check Collision Occurred (COL) */
+
+ if ((tsr & GMAC_TSR_COL) != 0)
+ {
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+ clrbits |= GMAC_TSR_COL;
+ }
+
+ /* Check for Transmit Frame Corruption due to AHB error (TFC) */
+
+ if ((tsr & GMAC_TSR_TFC) != 0)
+ {
+ nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
+ clrbits |= GMAC_TSR_TFC;
+ }
+
+ /* Check for Transmit Underrun (UND)
+ *
+ * ISR:UND is set transmit DMA was not able to read data from memory,
+ * either because the bus was not granted in time, because a not
+ * OK hresp(bus error) was returned or because a used bit was read
+ * midway through frame transmission. If this occurs, the
+ * transmitter forces bad CRC. Cleared by writing a one to this bit.
+ */
+
+ if ((tsr & GMAC_TSR_UND) != 0)
+ {
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ clrbits |= GMAC_TSR_UND;
+ }
+
+ /* Check for HRESP not OK */
+
+ if ((tsr & GMAC_TSR_HRESP) != 0)
+ {
+ nerr("ERROR: HRESP not OK: %08x\n", tsr);
+ clrbits |= GMAC_TSR_HRESP;
+ }
+
+ /* Check for Late Collitions (LCO) */
+
+ if ((tsr & GMAC_TSR_LCO) != 0)
+ {
+ nerr("ERROR: Late collision: %08x\n", tsr);
+ clrbits |= GMAC_TSR_LCO;
+ }
+
+ /* Clear status */
+
+ sam_putreg(priv, SAM_GMAC_TSR, clrbits);
+
+ /* And handle the TX done event */
+
+ sam_txdone(priv);
+ }
+
+ /* Check for the receipt of an RX packet.
+ *
+ * RXCOMP indicates that a packet has been received and stored in memory.
+ * The RXCOMP bit is cleared whent he interrupt status register was read.
+ * RSR:REC indicates that one or more frames have been received and placed
+ * in memory. This indication is cleared by writing a one to this bit.
+ */
+
+ if ((pending & GMAC_INT_RCOMP) != 0 || (rsr & GMAC_RSR_REC) != 0)
+ {
+ clrbits = GMAC_RSR_REC;
+
+ /* Check for Receive Overrun.
+ *
+ * RSR:RXOVR will be set if the RX FIFO is not able to store the
+ * receive frame due to a FIFO overflow, or if the receive status
+ * was not taken at the end of the frame. This bit is also set in
+ * DMA packet buffer mode if the packet buffer overflows. For DMA
+ * operation, the buffer will be recovered if an overrun occurs. This
+ * bit is cleared when set to 1.
+ */
+
+ if ((rsr & GMAC_RSR_RXOVR) != 0)
+ {
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ clrbits |= GMAC_RSR_RXOVR;
+ }
+
+ /* Check for buffer not available (BNA)
+ *
+ * RSR:BNA means that an attempt was made to get a new buffer and the
+ * pointer indicated that it was owned by the processor. The DMA will
+ * reread the pointer each time an end of frame is received until a
+ * valid pointer is found. This bit is set following each descriptor
+ * read attempt that fails, even if consecutive pointers are
+ * unsuccessful and software has in the mean time cleared the status
+ * flag. Cleared by writing a one to this bit.
+ */
+
+ if ((rsr & GMAC_RSR_BNA) != 0)
+ {
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+ clrbits |= GMAC_RSR_BNA;
+ }
+
+ /* Check for HRESP not OK (HNO) */
+
+ if ((rsr & GMAC_RSR_HNO) != 0)
+ {
+ nerr("ERROR: HRESP not OK: %08x\n", rsr);
+ clrbits |= GMAC_RSR_HNO;
+ }
+
+ /* Clear status */
+
+ sam_putreg(priv, SAM_GMAC_RSR, clrbits);
+
+ /* Handle the received packet */
+
+ sam_receive(priv);
+ }
+
+#ifdef CONFIG_DEBUG_NET
+ /* Check for PAUSE Frame received (PFRE).
+ *
+ * ISR:PFRE indicates that a pause frame has been received. Cleared on a read.
+ */
+
+ if ((pending & GMAC_INT_PFNZ) != 0)
+ {
+ nwarn("WARNING: Pause frame received\n");
+ }
+
+ /* Check for Pause Time Zero (PTZ)
+ *
+ * ISR:PTZ is set Pause Time Zero
+ */
+
+ if ((pending & GMAC_INT_PTZ) != 0)
+ {
+ nwarn("WARNING: Pause TO!\n");
+ }
+#endif
+
+ net_unlock();
+
+ /* Re-enable Ethernet interrupts */
+
+ up_enable_irq(SAM_IRQ_GMAL);
+}
+
+/****************************************************************************
+ * Function: sam_gmac_interrupt
+ *
+ * Description:
+ * Hardware interrupt handler
+ *
+ * Input Parameters:
+ * irq - Number of the IRQ that generated the interrupt
+ * context - Interrupt register state save info (architecture-specific)
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int sam_gmac_interrupt(int irq, void *context, FAR void *arg)
+{
+ struct sam_gmac_s *priv = &g_gmac;
+ uint32_t tsr;
+
+ /* Disable further Ethernet interrupts. Because Ethernet interrupts are
+ * also disabled if the TX timeout event occurs, there can be no race
+ * condition here.
+ */
+
+ up_disable_irq(SAM_IRQ_GMAL);
+
+ /* Check for the completion of a transmission. Careful:
+ *
+ * ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so
+ * we cannot read it here).
+ * TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a
+ * one to this bit.
+ */
+
+ tsr = sam_getreg(priv, SAM_GMAC_TSR_OFFSET);
+ if ((tsr & GMAC_TSR_TXCOMP) != 0)
+ {
+ /* If a TX transfer just completed, then cancel the TX timeout so
+ * there will be do race condition between any subsequent timeout
+ * expiration and the deferred interrupt processing.
+ */
+
+ wd_cancel(priv->txtimeout);
+ }
+
+ /* Schedule to perform the interrupt processing on the worker thread. */
+
+ work_queue(ETHWORK, &priv->irqwork, sam_interrupt_work, priv, 0);
+ return OK;
+}
+
+/****************************************************************************
+ * Function: sam_txtimeout_work
+ *
+ * Description:
+ * Perform TX timeout related work from the worker thread
+ *
+ * Input Parameters:
+ * arg - The argument passed when work_queue() as called.
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ * Ethernet interrupts are disabled
+ *
+ ****************************************************************************/
+
+static void sam_txtimeout_work(FAR void *arg)
+{
+ FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg;
+
+ nerr("ERROR: Timeout!\n");
+
+ /* Reset the hardware. Just take the interface down, then back up again. */
+
+ net_lock();
+ sam_ifdown(&priv->dev);
+ sam_ifup(&priv->dev);
+
+ /* Then poll the network for new XMIT data */
+
+ sam_dopoll(priv);
+ net_unlock();
+}
+
+/****************************************************************************
+ * Function: sam_txtimeout_expiry
+ *
+ * Description:
+ * Our TX watchdog timed out. Called from the timer interrupt handler.
+ * The last TX never completed. Reset the hardware and start again.
+ *
+ * Input Parameters:
+ * argc - The number of available arguments
+ * arg - The first argument
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void sam_txtimeout_expiry(int argc, uint32_t arg, ...)
+{
+ FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg;
+
+ /* Disable further Ethernet interrupts. This will prevent some race
+ * conditions with interrupt work. There is still a potential race
+ * condition with interrupt work that is already queued and in progress.
+ */
+
+ up_disable_irq(SAM_IRQ_GMAL);
+
+ /* Schedule to perform the TX timeout processing on the worker thread. */
+
+ work_queue(ETHWORK, &priv->irqwork, sam_txtimeout_work, priv, 0);
+}
+
+/****************************************************************************
+ * Function: sam_poll_work
+ *
+ * Description:
+ * Perform periodic polling from the worker thread
+ *
+ * Input Parameters:
+ * arg - The argument passed when work_queue() as called.
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ * Ethernet interrupts are disabled
+ *
+ ****************************************************************************/
+
+static void sam_poll_work(FAR void *arg)
+{
+ FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg;
+ struct net_driver_s *dev = &priv->dev;
+
+ /* Check if there are any free TX descriptors. We cannot perform the
+ * TX poll if we do not have buffering for another packet.
+ */
+
+ net_lock();
+ if (sam_txfree(priv) > 0)
+ {
+ /* Update TCP timing states and poll the network for new XMIT data. */
+
+ (void)devif_timer(dev, sam_txpoll);
+ }
+
+ /* Setup the watchdog poll timer again */
+
+ (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv);
+ net_unlock();
+}
+
+/****************************************************************************
+ * Function: sam_poll_expiry
+ *
+ * Description:
+ * Periodic timer handler. Called from the timer interrupt handler.
+ *
+ * Input Parameters:
+ * argc - The number of available arguments
+ * arg - The first argument
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void sam_poll_expiry(int argc, uint32_t arg, ...)
+{
+ FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg;
+
+ /* Schedule to perform the interrupt processing on the worker thread. */
+
+ work_queue(ETHWORK, &priv->pollwork, sam_poll_work, priv, 0);
+}
+
+/****************************************************************************
+ * Function: sam_ifup
+ *
+ * Description:
+ * NuttX Callback: Bring up the GMAC interface when an IP address is
+ * provided
+ *
+ * Input Parameters:
+ * dev - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int sam_ifup(struct net_driver_s *dev)
+{
+ struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
+ int ret;
+
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+
+ /* Configure the GMAC interface for normal operation. */
+
+ ninfo("Initialize the GMAC\n");
+ sam_gmac_configure(priv);
+
+ /* Set the MAC address (should have been configured while we were down) */
+
+ sam_macaddress(priv);
+
+#ifdef CONFIG_NET_ICMPv6
+ /* Set up IPv6 multicast address filtering */
+
+ sam_ipv6multicast(priv);
+#endif
+
+ /* Initialize for PHY access */
+
+ ret = sam_phyinit(priv);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
+ return ret;
+ }
+
+#ifdef CONFIG_SAMD5E5_GMAC_AUTONEG
+ /* Auto Negotiate, working in RMII mode */
+
+ ret = sam_autonegotiate(priv);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
+ return ret;
+ }
+#else
+ /* Just force the configured link speed */
+
+ sam_linkspeed(priv);
+#endif
+
+ /* Enable normal MAC operation */
+
+ ninfo("Enable normal operation\n");
+
+ /* Set and activate a timer process */
+
+ (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (uint32_t)priv);
+
+ /* Enable the GMAC interrupt */
+
+ priv->ifup = true;
+ up_enable_irq(SAM_IRQ_GMAL);
+ return OK;
+}
+
+/****************************************************************************
+ * Function: sam_ifdown
+ *
+ * Description:
+ * NuttX Callback: Stop the interface.
+ *
+ * Input Parameters:
+ * dev - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int sam_ifdown(struct net_driver_s *dev)
+{
+ struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
+ irqstate_t flags;
+
+ ninfo("Taking the network down\n");
+
+ /* Disable the GMAC interrupt */
+
+ flags = enter_critical_section();
+ up_disable_irq(SAM_IRQ_GMAL);
+
+ /* Cancel the TX poll timer and TX timeout timers */
+
+ wd_cancel(priv->txpoll);
+ wd_cancel(priv->txtimeout);
+
+ /* Put the GMAC in its reset, non-operational state. This should be
+ * a known configuration that will guarantee the sam_ifup() always
+ * successfully brings the interface back up.
+ */
+
+ sam_gmac_reset(priv);
+
+ /* Mark the device "down" */
+
+ priv->ifup = false;
+ leave_critical_section(flags);
+ return OK;
+}
+
+/****************************************************************************
+ * Function: sam_txavail_work
+ *
+ * Description:
+ * Perform an out-of-cycle poll on the worker thread.
+ *
+ * Input Parameters:
+ * arg - Reference to the NuttX driver state structure (cast to void*)
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Called on the higher priority worker thread.
+ *
+ ****************************************************************************/
+
+static void sam_txavail_work(FAR void *arg)
+{
+ FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg;
+
+ ninfo("ifup: %d\n", priv->ifup);
+
+ /* Ignore the notification if the interface is not yet up */
+
+ net_lock();
+ if (priv->ifup)
+ {
+ /* Poll the network for new XMIT data */
+
+ sam_dopoll(priv);
+ }
+
+ net_unlock();
+}
+
+/****************************************************************************
+ * Function: sam_txavail
+ *
+ * Description:
+ * Driver callback invoked when new TX data is available. This is a
+ * stimulus perform an out-of-cycle poll and, thereby, reduce the TX
+ * latency.
+ *
+ * Input Parameters:
+ * dev - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Called in normal user mode
+ *
+ ****************************************************************************/
+
+static int sam_txavail(struct net_driver_s *dev)
+{
+ FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)dev->d_private;
+
+ /* Is our single work structure available? It may not be if there are
+ * pending interrupt actions and we will have to ignore the Tx
+ * availability action.
+ */
+
+ if (work_available(&priv->pollwork))
+ {
+ /* Schedule to serialize the poll on the worker thread. */
+
+ work_queue(ETHWORK, &priv->pollwork, sam_txavail_work, priv, 0);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sam_hashindx
+ *
+ * Description:
+ * Cacuclate the hash address register index. The hash address register
+ * is 64 bits long and takes up two locations in the memory map. The
+ * destination address is reduced to a 6-bit index into the 64-bit Hash
+ * Register using the following hash function: The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * ndx:05 = da:05 ^ da:11 ^ da:17 ^ da:23 ^ da:29 ^ da:35 ^ da:41 ^ da:47
+ * ndx:04 = da:04 ^ da:10 ^ da:16 ^ da:22 ^ da:28 ^ da:34 ^ da:40 ^ da:46
+ * ndx:03 = da:03 ^ da:09 ^ da:15 ^ da:21 ^ da:27 ^ da:33 ^ da:39 ^ da:45
+ * ndx:02 = da:02 ^ da:08 ^ da:14 ^ da:20 ^ da:26 ^ da:32 ^ da:38 ^ da:44
+ * ndx:01 = da:01 ^ da:07 ^ da:13 ^ da:19 ^ da:25 ^ da:31 ^ da:37 ^ da:43
+ * ndx:00 = da:00 ^ da:06 ^ da:12 ^ da:18 ^ da:24 ^ da:30 ^ da:36 ^ da:42
+ *
+ * Where da:00 represents the least significant bit of the first byte
+ * received and da:47 represents the most significant bit of the last byte
+ * received.
+ *
+ * Input Parameters:
+ * mac - The multicast address to be hashed
+ *
+ * Returned Value:
+ * The 6-bit hash table index
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6)
+static unsigned int sam_hashindx(const uint8_t *mac)
+{
+ unsigned int ndx;
+
+ /* Isolate: mac[0]
+ * ... 05 04 03 02 01 00]
+ */
+
+ ndx = mac[0];
+
+ /* Isolate: mac[1] mac[0]
+ * ...11 10 09 08] [07 06 ...
+ *
+ * Accumulate: 05 04 03 02 01 00
+ * XOR: 11 10 09 08 07 06
+ */
+
+ ndx ^= (mac[1] << 2) | (mac[0] >> 6);
+
+ /* Isolate: mac[2] mac[1]
+ * ... 17 16] [15 14 13 12 ...
+ *
+ * Accumulate: 05 04 03 02 01 00
+ * XOR: 11 10 09 08 07 06
+ * XOR: 17 16 15 14 13 12
+ */
+
+ ndx ^= (mac[2] << 4) | (mac[1] >> 4);
+
+ /* Isolate: mac[2]
+ * [23 22 21 20 19 18 ...
+ *
+ * Accumulate: 05 04 03 02 01 00
+ * XOR: 11 10 09 08 07 06
+ * XOR: 17 16 15 14 13 12
+ * XOR: 23 22 21 20 19 18
+ */
+
+ ndx ^= (mac[2] >> 2);
+
+ /* Isolate: mac[3]
+ * ... 29 28 27 26 25 24]
+ *
+ * Accumulate: 05 04 03 02 01 00
+ * XOR: 11 10 09 08 07 06
+ * XOR: 17 16 15 14 13 12
+ * XOR: 23 22 21 20 19 18
+ * XOR: 29 28 27 26 25 24
+ */
+
+ ndx ^= mac[3];
+
+ /* Isolate: mac[4] mac[3]
+ * ... 35 34 33 32] [31 30 ...
+ *
+ * Accumulate: 05 04 03 02 01 00
+ * XOR: 11 10 09 08 07 06
+ * XOR: 17 16 15 14 13 12
+ * XOR: 23 22 21 20 19 18
+ * XOR: 29 28 27 26 25 24
+ * XOR: 35 34 33 32 31 30
+ */
+
+ ndx ^= (mac[4] << 2) | (mac[3] >> 6);
+
+ /* Isolate: mac[5] mac[4]
+ * ... 41 40] [39 38 37 36 ...
+ *
+ * Accumulate: 05 04 03 02 01 00
+ * XOR: 11 10 09 08 07 06
+ * XOR: 17 16 15 14 13 12
+ * XOR: 23 22 21 20 19 18
+ * XOR: 29 28 27 26 25 24
+ * XOR: 35 34 33 32 31 30
+ * XOR: 41 40 39 38 37 36
+ */
+
+ ndx ^= (mac[5] << 4) | (mac[4] >> 4);
+
+ /* Isolate: mac[5]
+ * [47 46 45 44 43 42 ...
+ *
+ * Accumulate: 05 04 03 02 01 00
+ * XOR: 11 10 09 08 07 06
+ * XOR: 17 16 15 14 13 12
+ * XOR: 23 22 21 20 19 18
+ * XOR: 29 28 27 26 25 24
+ * XOR: 35 34 33 32 31 30
+ * XOR: 41 40 39 38 37 36
+ * XOR: 47 46 45 44 43 42
+ */
+
+ ndx ^= (mac[5] >> 2);
+
+ /* Mask out the garbage bits and return the 6-bit index */
+
+ return ndx & 0x3f;
+}
+#endif /* CONFIG_NET_MCASTGROUP || CONFIG_NET_ICMPv6 */
+
+/****************************************************************************
+ * Function: sam_addmac
+ *
+ * Description:
+ * NuttX Callback: Add the specified MAC address to the hardware multicast
+ * address filtering
+ *
+ * Input Parameters:
+ * dev - Reference to the NuttX driver state structure
+ * mac - The MAC address to be added
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_MCASTGROUP
+static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
+{
+ struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
+ uintptr_t regaddr;
+ uint32_t regval;
+ unsigned int ndx;
+ unsigned int bit;
+ UNUSED(priv);
+
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+ /* Calculate the 6-bit has table index */
+
+ ndx = sam_hashindx(mac);
+
+ /* Add the multicast address to the hardware multicast hash table */
+
+ if (ndx >= 32)
+ {
+ regaddr = SAM_GMAC_HRT; /* Hash Register Top [63:32] Register */
+ bit = 1 << (ndx - 32); /* Bit 0-31 */
+ }
+ else
+ {
+ regaddr = SAM_GMAC_HRB; /* Hash Register Bottom [31:0] Register */
+ bit = 1 << ndx; /* Bit 0-31 */
+ }
+
+ regval = sam_getreg(priv, regaddr);
+ regval |= bit;
+ sam_putreg(priv, regaddr, regval);
+
+ /* The unicast hash enable and the multicast hash enable bits in the
+ * Network Configuration Register enable the reception of hash matched
+ * frames:
+ *
+ * - A multicast match will be signalled if the multicast hash enable bit
+ * is set, da:00 is logic 1 and the hash index points to a bit set in
+ * the Hash Register.
+ * - A unicast match will be signalled if the unicast hash enable bit is
+ * set, da:00 is logic 0 and the hash index points to a bit set in the
+ * Hash Register.
+ */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCFGR);
+ regval &= ~GMAC_NCFGR_UNIHEN; /* Disable unicast matching */
+ regval |= GMAC_NCFGR_MTIHEN; /* Enable multicast matching */
+ sam_putreg(priv, SAM_GMAC_NCFGR, regval);
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Function: sam_rmmac
+ *
+ * Description:
+ * NuttX Callback: Remove the specified MAC address from the hardware multicast
+ * address filtering
+ *
+ * Input Parameters:
+ * dev - Reference to the NuttX driver state structure
+ * mac - The MAC address to be removed
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_MCASTGROUP
+static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
+{
+ struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
+ uint32_t regval;
+ unsigned int regaddr1;
+ unsigned int regaddr2;
+ unsigned int ndx;
+ unsigned int bit;
+ UNUSED(priv);
+
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+ /* Calculate the 6-bit has table index */
+
+ ndx = sam_hashindx(mac);
+
+ /* Remove the multicast address to the hardware multicast hast table */
+
+ if (ndx >= 32)
+ {
+ regaddr1 = SAM_GMAC_HRT; /* Hash Register Top [63:32] Register */
+ regaddr2 = SAM_GMAC_HRB; /* Hash Register Bottom [31:0] Register */
+ bit = 1 << (ndx - 32); /* Bit 0-31 */
+ }
+ else
+ {
+ regaddr1 = SAM_GMAC_HRB; /* Hash Register Bottom [31:0] Register */
+ regaddr2 = SAM_GMAC_HRT; /* Hash Register Top [63:32] Register */
+ bit = 1 << ndx; /* Bit 0-31 */
+ }
+
+ regval = sam_getreg(priv, regaddr1);
+ regval &= ~bit;
+ sam_putreg(priv, regaddr1, regval);
+
+ /* The unicast hash enable and the multicast hash enable bits in the
+ * Network Configuration Register enable the reception of hash matched
+ * frames:
+ *
+ * - A multicast match will be signalled if the multicast hash enable bit
+ * is set, da:00 is logic 1 and the hash index points to a bit set in
+ * the Hash Register.
+ * - A unicast match will be signalled if the unicast hash enable bit is
+ * set, da:00 is logic 0 and the hash index points to a bit set in the
+ * Hash Register.
+ */
+
+ /* Are all multicast address matches disabled? */
+
+ if (regval == 0 && sam_getreg(priv, regaddr2) == 0)
+ {
+ /* Yes.. disable all address matching */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCFGR);
+ regval &= ~(GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN);
+ sam_putreg(priv, SAM_GMAC_NCFGR, regval);
+ }
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Function: sam_ioctl
+ *
+ * Description:
+ * Handles driver ioctl calls:
+ *
+ * SIOCMIINOTIFY - Set up to received notifications from PHY interrupting
+ * events.
+ *
+ * SIOCGMIIPHY, SIOCGMIIREG, and SIOCSMIIREG:
+ * Executes the SIOCxMIIxxx command and responds using the request struct
+ * that must be provided as its 2nd parameter.
+ *
+ * When called with SIOCGMIIPHY it will get the PHY address for the device
+ * and write it to the req->phy_id field of the request struct.
+ *
+ * When called with SIOCGMIIREG it will read a register of the PHY that is
+ * specified using the req->reg_no struct field and then write its output
+ * to the req->val_out field.
+ *
+ * When called with SIOCSMIIREG it will write to a register of the PHY that
+ * is specified using the req->reg_no struct field and use req->val_in as
+ * its input.
+ *
+ * Input Parameters:
+ * dev - Ethernet device structure
+ * cmd - SIOCxMIIxxx command code
+ * arg - Request structure also used to return values
+ *
+ * Returned Value: Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NETDEV_IOCTL
+static int sam_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
+{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+ struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
+#endif
+ int ret;
+
+ switch (cmd)
+ {
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+#ifdef CONFIG_ARCH_PHY_INTERRUPT
+ case SIOCMIINOTIFY: /* Set up for PHY event notifications */
+ {
+ struct mii_ioctl_notify_s *req =
+ (struct mii_ioctl_notify_s *)((uintptr_t)arg);
+
+ ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
+ if (ret == OK)
+ {
+ /* Enable PHY link up/down interrupts */
+
+ ret = sam_phyintenable(priv);
+ }
+ }
+ break;
+#endif
+
+ case SIOCGMIIPHY: /* Get MII PHY address */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+ req->phy_id = priv->phyaddr;
+ ret = OK;
+ }
+ break;
+
+ case SIOCGMIIREG: /* Get register from MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+
+ /* Enable the management port */
+
+ sam_enablemdio(priv);
+
+ /* Read from the requested register */
+
+ ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
+
+ /* Disable the management port */
+
+ sam_disablemdio(priv);
+ }
+ break;
+
+ case SIOCSMIIREG: /* Set register in MII PHY */
+ {
+ struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
+
+ /* Enable the management port */
+
+ sam_enablemdio(priv);
+
+ /* Write to the requested register */
+
+ ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
+
+ /* Disable the management port */
+
+ sam_disablemdio(priv);
+ }
+ break;
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
+
+ default:
+ ret = -ENOTTY;
+ break;
+ }
+
+ return ret;
+}
+#endif /* CONFIG_NETDEV_IOCTL */
+
+/****************************************************************************
+ * Function: sam_phydump
+ *
+ * Description:
+ * Dump the contents of PHY registers
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_DEBUG_NET) && defined(CONFIG_DEBUG_INFO)
+static void sam_phydump(struct sam_gmac_s *priv)
+{
+ uint16_t phyval;
+
+ /* Enable management port */
+
+ sam_enablemdio(priv);
+
+ ninfo("GMII Registers (Address %02x)\n", priv->phyaddr);
+ sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
+ ninfo(" MCR: %04x\n", phyval);
+ sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
+ ninfo(" MSR: %04x\n", phyval);
+ sam_phyread(priv, priv->phyaddr, GMII_ADVERTISE, &phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
+ sam_phyread(priv, priv->phyaddr, GMII_LPA, &phyval);
+ ninfo(" LPR: %04x\n", phyval);
+ sam_phyread(priv, priv->phyaddr, GMII_ESTATUS, &phyval);
+ ninfo(" ESTATUS: %04x\n", phyval);
+
+ /* Disable management port */
+
+ sam_disablemdio(priv);
+}
+#endif
+
+/****************************************************************************
+ * Function: sam_phyintenable
+ *
+ * Description:
+ * Enable link up/down PHY interrupts. The interrupt protocol is like this:
+ *
+ * - Interrupt status is cleared when the interrupt is enabled.
+ * - Interrupt occurs. Interrupt is disabled (at the processor level) when
+ * is received.
+ * - Interrupt status is cleared when the interrupt is re-enabled.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno (-ETIMEDOUT) on failure.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
+static int sam_phyintenable(struct sam_gmac_s *priv)
+{
+#if defined(SAMD5E5_GMAC_PHY_KSZ90x1)
+ uint16_t phyval;
+ int ret;
+
+ /* Enable the management port */
+
+ sam_enablemdio(priv);
+
+ /* Read the interrupt status register in order to clear any pending
+ * interrupts
+ */
+
+ ret = sam_phyread(priv, priv->phyaddr, GMII_KSZ90x1_ICS, &phyval);
+ if (ret == OK)
+ {
+ /* Enable link up/down interrupts */
+
+ ret = sam_phywrite(priv, priv->phyaddr, GMII_KSZ90x1_ICS,
+ (GMII_KSZ90x1_INT_LDEN | GMII_KSZ90x1_INT_LUEN));
+ }
+
+ /* Disable the management port */
+
+ sam_disablemdio(priv);
+ return ret;
+
+#else
+# warning Missing logic
+ return -ENOSYS;
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Function: sam_enablemdio
+ *
+ * Description:
+ * Enable the management port
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_enablemdio(struct sam_gmac_s *priv)
+{
+ uint32_t regval;
+ uint32_t enables;
+
+ /* Enable management port */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCR);
+ enables = regval & (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
+
+ regval &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
+ regval |= GMAC_NCR_MPE;
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+ regval |= enables;
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+}
+
+/****************************************************************************
+ * Function: sam_disablemdio
+ *
+ * Description:
+ * Disable the management port
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_disablemdio(struct sam_gmac_s *priv)
+{
+ uint32_t regval;
+ uint32_t enables;
+
+ /* Disable management port */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCR);
+ enables = regval & (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
+
+ regval &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+ regval &= ~GMAC_NCR_MPE;
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+ regval |= enables;
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+}
+
+/****************************************************************************
+ * Function: sam_phywait
+ *
+ * Description:
+ * Wait for the PHY to become IDLE
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno (-ETIMEDOUT) on failure.
+ *
+ ****************************************************************************/
+
+static int sam_phywait(struct sam_gmac_s *priv)
+{
+ volatile unsigned int retries;
+
+ /* Loop for the configured number of attempts */
+
+ for (retries = 0; retries < PHY_RETRY_MAX; retries++)
+ {
+ /* Is the PHY IDLE */
+
+ if ((sam_getreg(priv, SAM_GMAC_NSR) & GMAC_NSR_IDLE) != 0)
+ {
+ return OK;
+ }
+ }
+
+ return -ETIMEDOUT;
+}
+
+/****************************************************************************
+ * Function: sam_phyreset
+ *
+ * Description:
+ * Reset the PHY
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int sam_phyreset(struct sam_gmac_s *priv)
+{
+ uint16_t mcr;
+ int timeout;
+ int ret;
+
+ ninfo(" sam_phyreset\n");
+
+ /* Enable management port */
+
+ sam_enablemdio(priv);
+
+ /* Reset the PHY */
+
+ ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, GMII_MCR_RESET);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
+ }
+
+ /* Wait for the PHY reset to complete */
+
+ ret = -ETIMEDOUT;
+ for (timeout = 0; timeout < 10; timeout++)
+ {
+ mcr = GMII_MCR_RESET;
+ int result = sam_phyread(priv, priv->phyaddr, GMII_MCR, &mcr);
+ if (result < 0)
+ {
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
+ ret = result;
+ }
+ else if ((mcr & GMII_MCR_RESET) == 0)
+ {
+ ret = OK;
+ break;
+ }
+ }
+
+ /* Disable management port */
+
+ sam_disablemdio(priv);
+ return ret;
+}
+
+/****************************************************************************
+ * Function: sam_phyfind
+ *
+ * Description:
+ * Verify the PHY address and, if it is bad, try to one that works.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
+{
+ uint16_t phyval;
+ uint8_t candidate;
+ unsigned int offset;
+ int ret = -ESRCH;
+
+ ninfo("Find a valid PHY address\n");
+
+ /* Enable management port */
+
+ sam_enablemdio(priv);
+
+ /* Check initial candidate address */
+
+ candidate = *phyaddr;
+
+ ret = sam_phyread(priv, candidate, GMII_PHYID1, &phyval);
+ if (ret == OK && phyval == GMII_OUI_MSB)
+ {
+ *phyaddr = candidate;
+ ret = OK;
+ }
+
+ /* The current address does not work... try another */
+
+ else
+ {
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
+
+ for (offset = 0; offset < 32; offset++)
+ {
+ /* Get the next candidate PHY address */
+
+ candidate = (candidate + 1) & 0x1f;
+
+ /* Try reading the PHY ID from the candidate PHY address */
+
+ ret = sam_phyread(priv, candidate, GMII_PHYID1, &phyval);
+ if (ret == OK && phyval == GMII_OUI_MSB)
+ {
+ ret = OK;
+ break;
+ }
+ }
+ }
+
+ if (ret == OK)
+ {
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ *phyaddr = candidate;
+ }
+
+ /* Disable management port */
+
+ sam_disablemdio(priv);
+ return ret;
+}
+
+/****************************************************************************
+ * Function: sam_phyread
+ *
+ * Description:
+ * Read a PHY register.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ * phyaddr - The PHY device address
+ * regaddr - The PHY register address
+ * phyval - The location to return the 16-bit PHY register value.
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
+ uint8_t regaddr, uint16_t *phyval)
+{
+ uint32_t regval;
+ int ret;
+
+ /* Make sure that the PHY is idle */
+
+ ret = sam_phywait(priv);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Write the PHY Maintenance register */
+
+ regval = GMAC_MAN_DATA(0) | GMAC_MAN_WTN | GMAC_MAN_REGA(regaddr) |
+ GMAC_MAN_PHYA(phyaddr) | GMAC_MAN_READ | GMAC_MAN_CLTTO;
+ sam_putreg(priv, SAM_GMAC_MAN, regval);
+
+ /* Wait until the PHY is again idle */
+
+ ret = sam_phywait(priv);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Return the PHY data */
+
+ *phyval = (uint16_t)(sam_getreg(priv, SAM_GMAC_MAN) & GMAC_MAN_DATA_MASK);
+ return OK;
+}
+
+/****************************************************************************
+ * Function: sam_phywrite
+ *
+ * Description:
+ * Write to a PHY register.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ * phyaddr - The PHY device address
+ * regaddr - The PHY register address
+ * phyval - The 16-bit value to write to the PHY register.
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
+ uint8_t regaddr, uint16_t phyval)
+{
+ uint32_t regval;
+ int ret;
+
+ /* Make sure that the PHY is idle */
+
+ ret = sam_phywait(priv);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Write the PHY Maintenance register */
+
+ regval = GMAC_MAN_DATA(phyval) | GMAC_MAN_WTN | GMAC_MAN_REGA(regaddr) |
+ GMAC_MAN_PHYA(phyaddr) | GMAC_MAN_WRITE | GMAC_MAN_CLTTO;
+ sam_putreg(priv, SAM_GMAC_MAN, regval);
+
+ /* Wait until the PHY is again IDLE */
+
+ ret = sam_phywait(priv);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
+ return ret;
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Function: sam_autonegotiate
+ *
+ * Description:
+ * Autonegotiate speed and duplex.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMD5E5_GMAC_AUTONEG
+static int sam_autonegotiate(struct sam_gmac_s *priv)
+{
+ uint32_t regval;
+ uint32_t ncr;
+ uint32_t linkmode;
+ uint16_t phyval;
+ uint16_t phyid1;
+ uint16_t phyid2;
+ uint16_t advertise;
+ uint16_t lpa;
+ int timeout;
+ int ret;
+
+ /* Enable management port */
+
+ sam_enablemdio(priv);
+
+ /* Read the MS bits of the OUI from Pthe PHYID1 register */
+
+ ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID1, &phyid1);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to read PHYID1 register\n");
+ goto errout;
+ }
+
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+
+ /* Read the LS bits of the OUI from Pthe PHYID2 register */
+
+ ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID2, &phyid2);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to read PHYID2 register\n");
+ goto errout;
+ }
+
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+
+ if (phyid1 == GMII_OUI_MSB &&
+ (phyid2 & GMII_PHYID2_OUI_MASK) == GMII_OUI_LSB)
+ {
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
+ }
+ else
+ {
+ nerr("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
+ phyid1, phyid2);
+ }
+
+#ifdef SAMD5E5_GMAC_PHY_KSZ90x1
+ /* Set up the KSZ9020/31 PHY */
+
+ phyval = GMII_KSZ90x1_RCCPSR | GMII_ERCR_WRITE;
+ sam_phywrite(priv, priv->phyaddr, GMII_ERCR, phyval);
+ sam_phywrite(priv, priv->phyaddr, GMII_ERDWR, 0xf2f4);
+
+ phyval = GMII_KSZ90x1_RRDPSR | GMII_ERCR_WRITE;
+ sam_phywrite(priv, priv->phyaddr, GMII_ERCR, phyval);
+ sam_phywrite(priv, priv->phyaddr, GMII_ERDWR, 0x2222);
+
+ ret = sam_phywrite(priv, priv->phyaddr, GMII_KSZ90x1_ICS, 0xff00);
+#endif
+
+ /* Set the Auto_negotiation Advertisement Register, MII advertising for
+ * Next page 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3
+ */
+
+ advertise = GMII_ADVERTISE_100BASETXFULL | GMII_ADVERTISE_100BASETXHALF |
+ GMII_ADVERTISE_10BASETXFULL | GMII_ADVERTISE_10BASETXHALF |
+ GMII_ADVERTISE_8023;
+
+ ret = sam_phywrite(priv, priv->phyaddr, GMII_ADVERTISE, advertise);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to write ADVERTISE register\n");
+ goto errout;
+ }
+
+ /* Restart Auto_negotiation */
+
+ ret = sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to read MCR register: %d\n", ret);
+ goto errout;
+ }
+
+ phyval |= GMII_MCR_ANRESTART;
+
+ ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, phyval);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to write MCR register: %d\n", ret);
+ goto errout;
+ }
+
+ ninfo(" MCR: 0x%X\n", phyval);
+
+ /* Wait for autonegotion to complete */
+
+ timeout = 0;
+ for (; ; )
+ {
+ ret = sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to read MSR register: %d\n", ret);
+ goto errout;
+ }
+
+ /* Check for completion of autonegotiation */
+
+ if ((phyval & GMII_MSR_ANEGCOMPLETE) != 0)
+ {
+ /* Yes.. break out of the loop */
+
+ ninfo("AutoNegotiate complete\n");
+ break;
+ }
+
+ /* No.. check for a timeout */
+
+ if (++timeout >= PHY_RETRY_MAX)
+ {
+ nerr("ERROR: TimeOut\n");
+ sam_phydump(priv);
+ ret = -ETIMEDOUT;
+ goto errout;
+ }
+ }
+
+ /* Setup the GMAC local link speed */
+
+ linkmode = 0; /* 10Base-T Half-Duplex */
+ timeout = 0;
+
+ for (; ; )
+ {
+ /* Get the Autonegotiation Link partner base page */
+
+ ret = sam_phyread(priv, priv->phyaddr, GMII_LPA, &lpa);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to read LPA register: %d\n", ret);
+ goto errout;
+ }
+
+ /* Setup the GMAC link speed */
+
+ if ((advertise & GMII_ADVERTISE_100BASETXFULL) != 0 &&
+ (lpa & GMII_LPA_100BASETXFULL) != 0)
+ {
+ /* Set MII for 100BaseTX and Full Duplex */
+
+ linkmode = (GMAC_NCFGR_SPD | GMAC_NCFGR_FD);
+ break;
+ }
+ else if ((advertise & GMII_ADVERTISE_10BASETXFULL) != 0 &&
+ (lpa & GMII_LPA_10BASETXFULL) != 0)
+ {
+ /* Set MII for 10BaseT and Full Duplex */
+
+ linkmode = GMAC_NCFGR_FD;
+ break;
+ }
+ else if ((advertise & GMII_ADVERTISE_100BASETXHALF) != 0 &&
+ (lpa & GMII_LPA_100BASETXHALF) != 0)
+ {
+ /* Set MII for 100BaseTX and half Duplex */
+
+ linkmode = GMAC_NCFGR_SPD;
+ break;
+ }
+ else if ((advertise & GMII_ADVERTISE_10BASETXHALF) != 0 &&
+ (lpa & GMII_LPA_10BASETXHALF) != 0)
+ {
+ /* Set MII for 10BaseT and half Duplex */
+
+ break;
+ }
+
+ /* Check for a timeout */
+
+ if (++timeout >= PHY_RETRY_MAX)
+ {
+ nerr("ERROR: TimeOut\n");
+ sam_phydump(priv);
+ ret = -ETIMEDOUT;
+ goto errout;
+ }
+ }
+
+ /* Disable RX and TX momentarily */
+
+ ncr = sam_getreg(priv, SAM_GMAC_NCR);
+ sam_putreg(priv, SAM_GMAC_NCR, ncr & ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN));
+
+ /* Modify the NCFGR register based on the negotiated speed and duplex */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCFGR);
+ regval &= ~(GMAC_NCFGR_SPD | GMAC_NCFGR_FD);
+ regval |= linkmode;
+ sam_putreg(priv, SAM_GMAC_NCFGR, regval);
+ sam_putreg(priv, SAM_GMAC_NCR, ncr);
+
+ /* Enable MII or RMII */
+
+ regval = sam_getreg(priv, SAM_GMAC_UR);
+#ifdef CONFIG_SAMD5E5_GMAC_MII
+ regval |= GMAC_UR_MII;
+#else
+ regval &= ~GMAC_UR_MII;
+#endif
+ sam_putreg(priv, SAM_GMAC_UR, regval);
+
+errout:
+
+ /* Disable the management port */
+
+ sam_disablemdio(priv);
+ return ret;
+}
+#endif
+
+/****************************************************************************
+ * Function: sam_linkspeed
+ *
+ * Description:
+ * If autonegotiation is not configured, then just force the configuration
+ * mode
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SAMD5E5_GMAC_AUTONEG
+statoc void sam_linkspeed(struct sam_gmac_s *priv)
+{
+ uint32_t regval;
+ uint32_t ncr;
+
+ /* Disable RX and TX momentarily */
+
+ ncr = sam_getreg(priv, SAM_GMAC_NCR);
+ sam_putreg(priv, SAM_GMAC_NCR, ncr & ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN));
+
+ /* Modify the NCFGR register based on the configured speed and duplex */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCFGR);
+ regval &= ~(GMAC_NCFGR_SPD | GMAC_NCFGR_FD);
+
+#ifdef SAMD5E5_GMAC_ETHFD
+ regval |= GMAC_NCFGR_FD;
+#endif
+
+#if defined(SAMD5E5_GMAC_ETH100MBPS)
+ regval |= GMAC_NCFGR_SPD;
+#endif
+
+ sam_puttreg(priv, SAM_GMAC_NCFGR, regval);
+ sam_putreg(priv, SAM_GMAC_NCR, ncr);
+}
+#endif
+
+/****************************************************************************
+ * Function: sam_mdcclock
+ *
+ * Description:
+ * Configure the MDC clocking
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_mdcclock(struct sam_gmac_s *priv)
+{
+ uint32_t ncfgr;
+ uint32_t ncr;
+ uint32_t mck;
+
+ /* Disable RX and TX momentarily */
+
+ ncr = sam_getreg(priv, SAM_GMAC_NCR);
+ sam_putreg(priv, SAM_GMAC_NCR, ncr & ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN));
+
+ /* Modify the NCFGR register based on the configured board MCK frequency */
+
+ ncfgr = sam_getreg(priv, SAM_GMAC_NCFGR);
+ ncfgr &= ~GMAC_NCFGR_CLK_MASK;
+
+ mck = BOARD_MCK_FREQUENCY;
+ DEBUGASSERT(mck <= 240000000);
+
+ if (mck <= 20000000)
+ {
+ ncfgr |= GMAC_NCFGR_CLK_DIV8; /* MCK divided by 8 (MCK up to 20 MHz) */
+ }
+ else if (mck <= 40000000)
+ {
+ ncfgr |= GMAC_NCFGR_CLK_DIV16; /* MCK divided by 16 (MCK up to 40 MHz) */
+ }
+ else if (mck <= 80000000)
+ {
+ ncfgr |= GMAC_NCFGR_CLK_DIV32; /* MCK divided by 32 (MCK up to 80 MHz) */
+ }
+ else if (mck <= 120000000)
+ {
+ ncfgr |= GMAC_NCFGR_CLK_DIV48; /* MCK divided by 48 (MCK up to 120 MHz) */
+ }
+ else if (mck <= 160000000)
+ {
+ ncfgr |= GMAC_NCFGR_CLK_DIV64; /* MCK divided by 64 (MCK up to 160 MHz) */
+ }
+ else /* if (mck <= 240000000) */
+ {
+ ncfgr |= GMAC_NCFGR_CLK_DIV96; /* MCK divided by 64 (MCK up to 240 MHz) */
+ }
+
+ sam_putreg(priv, SAM_GMAC_NCFGR, ncfgr);
+
+ /* Restore RX and TX enable settings */
+
+ sam_putreg(priv, SAM_GMAC_NCR, ncr);
+}
+
+/****************************************************************************
+ * Function: sam_phyinit
+ *
+ * Description:
+ * Configure the PHY and determine the link speed/duplex.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ ****************************************************************************/
+
+static int sam_phyinit(struct sam_gmac_s *priv)
+{
+ int ret;
+
+ /* Configure PHY clocking */
+
+ sam_mdcclock(priv);
+
+#ifdef CONFIG_SAMD5E5_GMAC_PHYINIT
+ ret = sam_phy_boardinitialize(0);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to initialize the PHY: %d\n", ret);
+ return ret;
+ }
+#endif
+
+ /* Check the PHY Address */
+
+ priv->phyaddr = CONFIG_SAMD5E5_GMAC_PHYADDR;
+ ret = sam_phyfind(priv, &priv->phyaddr);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
+ return ret;
+ }
+
+ /* We have a PHY address. Reset the PHY */
+
+ sam_phyreset(priv);
+ return OK;
+}
+
+/****************************************************************************
+ * Function: sam_ethgpioconfig
+ *
+ * Description:
+ * Configure GPIOs for the GMAC interface.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static inline void sam_ethgpioconfig(struct sam_gmac_s *priv)
+{
+ /* Configure PIO pins to support GMAC in MII or RMII mode */
+
+ sam_portconfig(PORT_GMAC_GTX0);
+ sam_portconfig(PORT_GMAC_GTX1);
+#ifdef CONFIG_SAMD5E5_GMAC_MII
+ sam_portconfig(PORT_GMAC_GTX2);
+ sam_portconfig(PORT_GMAC_GTX3);
+#endif
+
+ sam_portconfig(PORT_GMAC_GRX0);
+ sam_portconfig(PORT_GMAC_GRX1);
+#ifdef CONFIG_SAMD5E5_GMAC_MII
+ sam_portconfig(PORT_GMAC_GRX1);
+ sam_portconfig(PORT_GMAC_GRX2);
+#endif
+
+ /* TXCK is REFCK in RMII mode */
+
+ sam_portconfig(PORT_GMAC_GTXCK);
+#ifdef CONFIG_SAMD5E5_GMAC_MII
+ sam_portconfig(PORT_GMAC_GRXCK);
+#endif
+
+ /* RXDV is CRSDV in RMII mode */
+
+ sam_portconfig(PORT_GMAC_GRXDV);
+ sam_portconfig(PORT_GMAC_GTXEN);
+ sam_portconfig(PORT_GMAC_GRXER);
+#ifdef CONFIG_SAMD5E5_GMAC_MII
+ sam_portconfig(PORT_GMAC_GTXER);
+ sam_portconfig(PORT_GMAC_GCOL);
+ sam_portconfig(PORT_GMAC_GCRS);
+#endif
+
+ sam_portconfig(BOARD_GMAC_GMDC);
+ sam_portconfig(BOARD_GMAC_GMDIO);
+}
+
+/****************************************************************************
+ * Function: sam_txreset
+ *
+ * Description:
+ * Reset the transmit logic
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void sam_txreset(struct sam_gmac_s *priv)
+{
+ uint8_t *txbuffer = priv->txbuffer;
+ struct gmac_txdesc_s *txdesc = priv->txdesc;
+ uintptr_t bufaddr;
+ uint32_t physaddr;
+ uint32_t regval;
+ int ndx;
+
+ /* Disable TX */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCR);
+ regval &= ~GMAC_NCR_TXEN;
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+ /* Configure the TX descriptors. */
+
+ priv->txhead = 0;
+ priv->txtail = 0;
+
+ for (ndx = 0; ndx < CONFIG_SAMD5E5_GMAC_NTXBUFFERS; ndx++)
+ {
+ bufaddr = (uintptr_t)(&(txbuffer[ndx * GMAC_TX_UNITSIZE]));
+
+ /* Set the buffer address and mark the descriptor as in used by
+ * firmware.
+ */
+
+ physaddr = bufaddr;
+ txdesc[ndx].addr = physaddr;
+ txdesc[ndx].status = (uint32_t)GMACTXD_STA_USED;
+ }
+
+ /* Mark the final descriptor in the list */
+
+ txdesc[CONFIG_SAMD5E5_GMAC_NTXBUFFERS - 1].status =
+ GMACTXD_STA_USED | GMACTXD_STA_WRAP;
+
+ /* Flush the entire TX descriptor table to RAM */
+
+ up_clean_dcache((uintptr_t)txdesc,
+ (uintptr_t)txdesc +
+ CONFIG_SAMD5E5_GMAC_NTXBUFFERS * sizeof(struct gmac_txdesc_s));
+
+ /* Set the Transmit Buffer Queue Base Register */
+
+ physaddr = (uintptr_t)txdesc;
+ sam_putreg(priv, SAM_GMAC_TBQB, physaddr);
+}
+
+/****************************************************************************
+ * Function: sam_rxreset
+ *
+ * Description:
+ * Reset the receive logic
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void sam_rxreset(struct sam_gmac_s *priv)
+{
+ struct gmac_rxdesc_s *rxdesc = priv->rxdesc;
+ uint8_t *rxbuffer = priv->rxbuffer;
+ uintptr_t bufaddr;
+ uint32_t physaddr;
+ uint32_t regval;
+ int ndx;
+
+ /* Disable RX */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCR);
+ regval &= ~GMAC_NCR_RXEN;
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+ /* Configure the RX descriptors. */
+
+ priv->rxndx = 0;
+ for (ndx = 0; ndx < CONFIG_SAMD5E5_GMAC_NRXBUFFERS; ndx++)
+ {
+ bufaddr = (uintptr_t)(&(rxbuffer[ndx * GMAC_RX_UNITSIZE]));
+ DEBUGASSERT((bufaddr & ~GMACRXD_ADDR_MASK) == 0);
+
+ /* Set the buffer address and remove GMACRXD_ADDR_OWNER and
+ * GMACRXD_ADDR_WRAP.
+ */
+
+ physaddr = bufaddr;
+ rxdesc[ndx].addr = physaddr;
+ rxdesc[ndx].status = 0;
+ }
+
+ /* Mark the final descriptor in the list */
+
+ rxdesc[CONFIG_SAMD5E5_GMAC_NRXBUFFERS - 1].addr |= GMACRXD_ADDR_WRAP;
+
+ /* Flush the entire RX descriptor table to RAM */
+
+ up_clean_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc +
+ CONFIG_SAMD5E5_GMAC_NRXBUFFERS * sizeof(struct gmac_rxdesc_s));
+
+ /* Set the Receive Buffer Queue Base Register */
+
+ physaddr = (uintptr_t)rxdesc;
+ sam_putreg(priv, SAM_GMAC_RBQB, physaddr);
+}
+
+/****************************************************************************
+ * Function: sam_gmac_reset
+ *
+ * Description:
+ * Reset the GMAC block.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * None.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void sam_gmac_reset(struct sam_gmac_s *priv)
+{
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+ /* We are supporting PHY IOCTLs, then do not reset the MAC. If we do,
+ * then we cannot communicate with the PHY. So, instead, just disable
+ * interrupts, cancel timers, and disable TX and RX.
+ */
+
+ sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
+
+ /* Reset RX and TX logic */
+
+ sam_rxreset(priv);
+ sam_txreset(priv);
+
+ /* Disable Rx and Tx, plus the statistics registers. */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCR);
+ regval &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN | GMAC_NCR_WESTAT);
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+#else
+ /* Disable all GMAC interrupts */
+
+ sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
+
+ /* Reset RX and TX logic */
+
+ sam_rxreset(priv);
+ sam_txreset(priv);
+
+ /* Make sure that RX and TX are disabled; clear statistics registers */
+
+ sam_putreg(priv, SAM_GMAC_NCR, GMAC_NCR_CLRSTAT);
+
+ /* Disable clocking to the GMAC peripheral */
+
+ sam_ahb_gmac_disableperiph();
+ sam_apb_gmac_disableperiph();
+
+#endif
+}
+
+/****************************************************************************
+ * Function: sam_macaddress
+ *
+ * Description:
+ * Configure the selected MAC address.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void sam_macaddress(struct sam_gmac_s *priv)
+{
+ struct net_driver_s *dev = &priv->dev;
+ uint32_t regval;
+
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
+ dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
+ dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
+
+ /* Set the MAC address */
+
+ regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[0] |
+ (uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8 |
+ (uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16 |
+ (uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24;
+ sam_putreg(priv, SAM_GMAC_SAB1, regval);
+
+ regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[4] |
+ (uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8;
+ sam_putreg(priv, SAM_GMAC_SAT1, regval);
+}
+
+/****************************************************************************
+ * Function: sam_ipv6multicast
+ *
+ * Description:
+ * Configure the IPv6 multicast MAC address.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_ICMPv6
+static void sam_ipv6multicast(struct sam_gmac_s *priv)
+{
+ struct net_driver_s *dev;
+ uint16_t tmp16;
+ uint8_t mac[6];
+
+ /* For ICMPv6, we need to add the IPv6 multicast address
+ *
+ * For IPv6 multicast addresses, the Ethernet MAC is derived by
+ * the four low-order octets OR'ed with the MAC 33:33:00:00:00:00,
+ * so for example the IPv6 address FF02:DEAD:BEEF::1:3 would map
+ * to the Ethernet MAC address 33:33:00:01:00:03.
+ *
+ * NOTES: This appears correct for the ICMPv6 Router Solicitation
+ * Message, but the ICMPv6 Neighbor Solicitation message seems to
+ * use 33:33:ff:01:00:03.
+ */
+
+ mac[0] = 0x33;
+ mac[1] = 0x33;
+
+ dev = &priv->dev;
+ tmp16 = dev->d_ipv6addr[6];
+ mac[2] = 0xff;
+ mac[3] = tmp16 >> 8;
+
+ tmp16 = dev->d_ipv6addr[7];
+ mac[4] = tmp16 & 0xff;
+ mac[5] = tmp16 >> 8;
+
+ ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+ (void)sam_addmac(dev, mac);
+
+#ifdef CONFIG_NET_ICMPv6_AUTOCONF
+ /* Add the IPv6 all link-local nodes Ethernet address. This is the
+ * address that we expect to receive ICMPv6 Router Advertisement
+ * packets.
+ */
+
+ (void)sam_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
+
+#endif /* CONFIG_NET_ICMPv6_AUTOCONF */
+#ifdef CONFIG_NET_ICMPv6_ROUTER
+ /* Add the IPv6 all link-local routers Ethernet address. This is the
+ * address that we expect to receive ICMPv6 Router Solicitation
+ * packets.
+ */
+
+ (void)sam_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
+
+#endif /* CONFIG_NET_ICMPv6_ROUTER */
+}
+#endif /* CONFIG_NET_ICMPv6 */
+
+/****************************************************************************
+ * Function: sam_gmac_configure
+ *
+ * Description:
+ * Configure the GMAC interface for normal operation.
+ *
+ * Input Parameters:
+ * priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int sam_gmac_configure(struct sam_gmac_s *priv)
+{
+ uint32_t regval;
+
+ ninfo("Entry\n");
+
+ /* Enable clocking to the GMAC peripheral */
+
+ sam_ahb_gmac_enableperiph();
+ sam_apb_gmac_enableperiph();
+
+ /* Disable TX, RX, clear statistics. Disable all interrupts. */
+
+ sam_putreg(priv, SAM_GMAC_NCR, GMAC_NCR_CLRSTAT);
+ sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_ALL);
+
+ /* Clear all status bits in the receive status register. */
+
+ regval = (GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA | GMAC_RSR_HNO);
+ sam_putreg(priv, SAM_GMAC_RSR, regval);
+
+ /* Clear all status bits in the transmit status register */
+
+ regval = GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE | GMAC_TSR_TXGO |
+ GMAC_TSR_TFC | GMAC_TSR_TXCOMP | GMAC_TSR_UND | GMAC_TSR_HRESP |
+ GMAC_TSR_LCO;
+ sam_putreg(priv, SAM_GMAC_TSR, regval);
+
+ /* Clear any pending interrupts */
+
+ (void)sam_getreg(priv, SAM_GMAC_ISR);
+
+ /* Initial configuration:
+ *
+ * SPD = 0 : Assuming 100Base-T full duplex
+ * FD = 1 : Assuming 100Base-T full duplex
+ * DNVLAN = 0 : Don't discard non-VLAN frames
+ * JFRAME = 0 : Disable jumbo frames
+ * CAF : Depends on CONFIG_NET_PROMISCUOUS
+ * NBC : Depends on CONFIG_SAMD5E5_GMAC_NBC
+ * MTIHEN = 0 : Multicast hash disabled
+ * UNIHEN = 0 : Unicast hash disabled
+ * MAXFS = 0 : Disable receive 1536 byte frames
+ * RTY = 0 : Disable retry test
+ * PEN = 1 : Pause frames disabled
+ * RXBUFO = 0 : No receive buffer offset
+ * LFERD = 0 : No length field error discard
+ * RFCS = 1 : Remove FCS
+ * CLK = 4 : Assuming MCK <= 160MHz
+ * DBW = 1 : 64-bit data bus with
+ * DCPF = 0 : Copy of pause frames not disabled
+ * RXCOEN = 0 : RX checksum offload disabled
+ * EFRHD = 0 : Disable frames received in half duple
+ * IRXFCS = 0 : Disable ignore RX FCX
+ * IPGSEN = 0 : IP stretch disabled
+ * RXBP = 0 : Receive bad pre-ambled disabled
+ * IRXER = 0 : Disable ignore IPG GXER
+ */
+
+ regval = GMAC_NCFGR_FD | GMAC_NCFGR_PEN |
+ GMAC_NCFGR_RFCS | GMAC_NCFGR_CLK_DIV64 | GMAC_NCFGR_DBW_64;
+
+#ifdef CONFIG_NET_PROMISCUOUS
+ regval |= GMAC_NCFGR_CAF;
+#endif
+
+#ifdef CONFIG_SAMD5E5_GMAC_NBC
+ regval |= GMAC_NCFGR_NBC;
+#endif
+
+ sam_putreg(priv, SAM_GMAC_NCFGR, regval);
+
+ /* Reset TX and RX */
+
+ sam_rxreset(priv);
+ sam_txreset(priv);
+
+ /* Enable Rx and Tx, plus the statistics registers. */
+
+ regval = sam_getreg(priv, SAM_GMAC_NCR);
+ regval |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN | GMAC_NCR_WESTAT);
+ sam_putreg(priv, SAM_GMAC_NCR, regval);
+
+ /* Setup the interrupts for TX events, RX events, and error events */
+
+ regval = GMAC_INT_MFS | GMAC_INT_RCOMP | GMAC_INT_RXUBR | GMAC_INT_TXUBR |
+ GMAC_INT_TUR | GMAC_INT_RLEX | GMAC_INT_TFC | GMAC_INT_TCOMP |
+ GMAC_INT_ROVR | GMAC_INT_HRESP | GMAC_INT_PFNZ | GMAC_INT_PTZ |
+ GMAC_INT_PFTR | GMAC_INT_EXINT | GMAC_INT_DRQFR | GMAC_INT_SFR |
+ GMAC_INT_DRQFT | GMAC_INT_SFT | GMAC_INT_PDRQFR | GMAC_INT_PDRSFR |
+ GMAC_INT_PDRQFT | GMAC_INT_PDRSFT;
+ sam_putreg(priv, SAM_GMAC_IER, regval);
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: sam_gmac_initialize
+ *
+ * Description:
+ * Initialize the GMAC driver.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ * Called very early in the initialization sequence.
+ *
+ ****************************************************************************/
+
+int sam_gmac_initialize(void)
+{
+ struct sam_gmac_s *priv = &g_gmac;
+ int ret;
+
+ /* Initialize the driver structure */
+
+ memset(priv, 0, sizeof(struct sam_gmac_s));
+ priv->dev.d_buf = g_pktbuf; /* Single packet buffer */
+ priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */
+ priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */
+ priv->dev.d_txavail = sam_txavail; /* New TX data callback */
+#ifdef CONFIG_NET_MCASTGROUP
+ priv->dev.d_addmac = sam_addmac; /* Add multicast MAC address */
+ priv->dev.d_rmmac = sam_rmmac; /* Remove multicast MAC address */
+#endif
+#ifdef CONFIG_NETDEV_IOCTL
+ priv->dev.d_ioctl = sam_ioctl; /* Support PHY ioctl() calls */
+#endif
+ priv->dev.d_private = (void *)&g_gmac; /* Used to recover private state from dev */
+
+ /* Create a watchdog for timing polling for and timing of transmissions */
+
+ priv->txpoll = wd_create();
+ if (!priv->txpoll)
+ {
+ nerr("ERROR: Failed to create periodic poll timer\n");
+ ret = -EAGAIN;
+ goto errout;
+ }
+
+ priv->txtimeout = wd_create(); /* Create TX timeout timer */
+ if (!priv->txtimeout)
+ {
+ nerr("ERROR: Failed to create periodic poll timer\n");
+ ret = -EAGAIN;
+ goto errout_with_txpoll;
+ }
+
+ /* Configure PIO pins to support GMAC */
+
+ sam_ethgpioconfig(priv);
+
+ /* Allocate buffers */
+
+ ret = sam_buffer_initialize(priv);
+ if (ret < 0)
+ {
+ nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
+ goto errout_with_txtimeout;
+ }
+
+ /* Attach the IRQ to the driver. It will not be enabled at the AIC until
+ * the interface is in the 'up' state.
+ */
+
+ ret = irq_attach(SAM_IRQ_GMAL, sam_gmac_interrupt, NULL);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAL);
+ goto errout_with_buffers;
+ }
+
+ /* Enable clocking to the GMAC peripheral (just for sam_ifdown()) */
+
+ sam_ahb_gmac_enableperiph();
+ sam_apb_gmac_enableperiph();
+
+ /* Put the interface in the down state (disabling clocking again). */
+
+ ret = sam_ifdown(&priv->dev);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
+ goto errout_with_buffers;
+ }
+
+ /* Register the device with the OS so that socket IOCTLs can be performed */
+
+ ret = netdev_register(&priv->dev, NET_LL_ETHERNET);
+ if (ret >= 0)
+ {
+ return ret;
+ }
+
+ nerr("ERROR: netdev_register() failed: %d\n", ret);
+
+errout_with_buffers:
+ sam_buffer_free(priv);
+errout_with_txtimeout:
+ wd_delete(priv->txtimeout);
+errout_with_txpoll:
+ wd_delete(priv->txpoll);
+errout:
+ return ret;
+}
+
+#endif /* CONFIG_NET && CONFIG_SAMD5E5_GMAC */
diff --git a/boards/Kconfig b/boards/Kconfig
index cb1b79b..aed15fd 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -1336,6 +1336,15 @@ config ARCH_BOARD_SAMD21_XPLAINED
This board features the ATSAMD21J18A MCU (Cortex-M0+ with 256KB of FLASH
and 32KB of SRAM).
+config ARCH_BOARD_SAME54_XPLAINED_PRO
+ bool "Atmel SAME54-Xplained Pro development board"
+ depends on ARCH_CHIP_SAME54P20
+ select ARCH_HAVE_LEDS
+ select ARCH_HAVE_BUTTONS
+ select ARCH_HAVE_IRQBUTTONS
+ ---help---
+ The port of NuttX to the Atmel SAME54-Xplained Pro development board.
+
config ARCH_BOARD_SAML21_XPLAINED
bool "Atmel SAML21-Xplained Pro development board"
depends on ARCH_CHIP_SAML21J18
@@ -2129,6 +2138,7 @@ config ARCH_BOARD
default "sama5d4-ek" if ARCH_BOARD_SAMA5D4_EK
default "samd20-xplained" if ARCH_BOARD_SAMD20_XPLAINED
default "samd21-xplained" if ARCH_BOARD_SAMD21_XPLAINED
+ default "same54-xplained-pro" if ARCH_BOARD_SAME54_XPLAINED_PRO
default "saml21-xplained" if ARCH_BOARD_SAML21_XPLAINED
default "sam3u-ek" if ARCH_BOARD_SAM3UEK
default "sam4cmp-db" if ARCH_BOARD_SAM4CMP_DB
@@ -2439,6 +2449,9 @@ endif
if ARCH_BOARD_SAMD21_XPLAINED
source "boards/arm/samd2l2/samd21-xplained/Kconfig"
endif
+if ARCH_BOARD_SAME54_XPLAINED_PRO
+source "boards/arm/samd5e5/same54-xplained-pro/Kconfig"
+endif
if ARCH_BOARD_SAML21_XPLAINED
source "boards/arm/samd2l2/saml21-xplained/Kconfig"
endif
diff --git a/boards/arm/samd5e5/same54-xplained-pro/Kconfig b/boards/arm/samd5e5/same54-xplained-pro/Kconfig
new file mode 100644
index 0000000..371357c
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/Kconfig
@@ -0,0 +1,50 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_SAME54_XPLAINED_PRO
+
+choice
+ prompt "Execution memory"
+ default SAME54_XPLAINED_PRO_RUNFROMFLASH
+
+config SAME54_XPLAINED_PRO_RUNFROMFLASH
+ bool "Run from FLASH"
+ select BOOT_RUNFROMFLASH
+ ---help---
+ This is the normal configuration for building SAM E54 Xplained
+ Pro code.
+
+config SAME54_XPLAINED_PRO_RUNFROMSRAM
+ bool "Run from SRAM"
+ select BOOT_RUNFROMISRAM
+ ---help---
+ During early bring-up, it is safer to execute entirely from
+ SRAM until you are confident in the initialization logic.
+ Then you can safely switch to FLASH.
+
+ REVISIT: This auto-selects CONFIG_BOOT_RUNFROMISRAM but I have
+ found, with some difficulty, that that choice still defaults to
+ CONFIG_BOOT_RUNFROMFLASH, causing link-time failures when running
+ from SRAM.
+
+endchoice # Execution memory
+
+config SAME54_XPLAINED_PRO_32KHZXTAL
+ bool "32.768 KHz XTAL"
+ default n
+ ---help---
+ According to the schematic, a 32.768 KHz crystal is installed on
+ board. However, I have been unable to use this crystal and thought
+ perhaps it is missing or defective on my board (there is a metal
+ package that could be a crystal on board, but I am not certain).
+ Another, more likely option is that there is a coding error on my
+ part that prevents the 32.768 KHz crystal from usable(?)
+
+ The configuration defaults to using the always-on OSCULP32 as the
+ slow clock source. This option will select instead XOSC32 as the
+ slow clock source.
+
+
+endif # ARCH_BOARD_SAME54_XPLAINED_PRO
diff --git a/boards/arm/samd5e5/same54-xplained-pro/README.txt b/boards/arm/samd5e5/same54-xplained-pro/README.txt
new file mode 100644
index 0000000..a844e01
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/README.txt
@@ -0,0 +1,160 @@
+README
+======
+
+ This directory contains the port of NuttX to the Microchip SAME54 Xplained
+ Pro board. This board is powered by an ATSAME54P20A:
+
+ o Cortex M4 core running at 120 MHz
+ o Hardware DSP and floating point support
+ o 1 MB flash, 256 KB RAM
+ o 32-bit, 3.3V logic and power
+ o Dual 1 MSPS DAC (A0 and A1)
+ o Dual 1 MSPS ADC (8 analog pins)
+ o 8 x hardware SERCOM (I2C, SPI or UART)
+ o 16 x PWM outputs
+ o Stereo I2S input/output with MCK pin
+ o 14-bit Parallel capture controller (for camera/video in)
+ o Built in crypto engines with AES (256 bit), true RNG, Pubkey controller
+ o 10/100 Ethernet MAC
+ o Dual SD/MMC controller
+ o Dual CAN bus interfaces
+ o 100-TQFP
+
+Contents
+========
+
+ o STATUS
+ o Serial Console
+ o LEDs
+ o Run from SRAM
+ o Configurations
+
+STATUS
+======
+
+ 2019-09-17: Board port started based on Metro M4 board.
+
+ WARNING: If you decide to invest the time to discover whey the XOSC32K
+ clock source is not working, be certain to use the SRAM configuration.
+ That configuration in FLASH is most likely lock up your board irrecoverably
+ is there are any start-up errors!
+
+
+Serial Console
+==============
+
+ The onboard debugger on the SAME54 Xplained Pro provides a virtual serial
+ interface over the DEBUG USB port. The pins on the SAME54 are as follows:
+
+ ----------------- -----------
+ SAMD5E5 FUNCTION
+ ----------------- -----------
+ PB24 SERCOM2 PAD1 RXD
+ PB25 SERCOM2 PAD0 TXD
+
+
+ An external RS-232 or serial-to-USB adapter can be connected on pins PA22
+ and PA23:
+
+ ----------------- ---------
+ SAMD5E5 FUNCTION
+ ----------------- ---------
+ PA23 SERCOM3 PAD1 RXD
+ PA22 SERCOM3 PAD0 TXD
+
+
+LEDs
+====
+
+ The SAME54 Xplained Pro has three LEDs, but only one is controllable by software:
+
+ 1. LED0 near the edge of the board
+
+
+ ----------------- -----------
+ SAMD5E5 FUNCTION
+ ----------------- -----------
+ PC18 GPIO output
+
+Run from SRAM
+=============
+
+ I bricked my first Metro M4 board because there were problems in the
+ bring-up logic. These problems left the chip in a bad state that was
+ repeated on each reset because the code was written into FLASH and I was
+ unable to ever connect to it again via SWD.
+
+ To make the bring-up less risky, I added a configuration option to build
+ the code to execution entirely out of SRAM. By default, the setting
+ CONFIG_SAME54_XPLAINED_PRO_RUNFROMFLASH=y is used and the code is built to run out of
+ FLASH. If CONFIG_SAME54_XPLAINED_PRO_RUNFROMSRAM=y is selected instead, then the
+ code is built to run out of SRAM.
+
+ To use the code in this configuration, the program must be started a
+ little differently:
+
+ gdb> mon reset
+ gdb> mon halt
+ gdb> load nuttx << Load NuttX into SRAM
+ gdb> file nuttx << Assuming debug symbols are enabled
+ gdb> mon memu32 0x20000000 << Get the address of initial stack
+ gdb> mon reg sp 0x200161c4 << Set the initial stack pointer using this address
+ gdb> mon memu32 0x20000004 << Get the address of __start entry point
+ gdb> mon reg pc 0x20000264 << Set the PC using this address (without bit 0 set)
+ gdb> si << Step in just to make sure everything is okay
+ gdb> [ set breakpoints ]
+ gdb> c << Then continue until you hit a breakpoint
+
+ Where 0x200161c4 and 0x20000264 are the values of the initial stack and
+ the __start entry point that I read from SRAM
+
+Configurations
+==============
+
+ Each SAME54 Xplained Pro configuration is maintained in a sub-directory and
+ can be selected as follow:
+
+ tools/configure.sh [OPTIONS] same54-xplained-pro:<subdir>
+
+ Do 'tools/configure.sh -h' for the list of options. If you are building
+ under Windows with Cygwin, you would need the -c option, for example.
+
+ Before building, make sure that the PATH environmental variable includes the
+ correct path to the directory than holds your toolchain binaries.
+
+ And then build NuttX by simply typing the following. At the conclusion of
+ the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
+
+ make
+
+ The <subdir> that is provided above as an argument to the tools/configure.sh
+ must be is one of configurations listed in the following paragraph.
+
+ NOTES:
+
+ 1. These configurations use the mconf-based configuration tool. To
+ change any of these configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+ 2. Unless stated otherwise, all configurations generate console
+ output on SERCOM2 which is available via USB debug.
+
+ 3. Unless otherwise stated, the configurations are setup build under
+ Linux with a generic ARM EABI toolchain:
+
+Configuration sub-directories
+-----------------------------
+
+ nsh:
+ This configuration directory will built the NuttShell. See NOTES for
+ common configuration above and the following:
+
+ NOTES:
+
+ 1. The CMCC (Cortex M Cache Controller) is enabled.
+
diff --git a/boards/arm/samd5e5/same54-xplained-pro/configs/nsh/defconfig b/boards/arm/samd5e5/same54-xplained-pro/configs/nsh/defconfig
new file mode 100644
index 0000000..2e1ee8c
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/configs/nsh/defconfig
@@ -0,0 +1,55 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_PS is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="same54-xplained-pro"
+CONFIG_ARCH_BOARD_SAME54_XPLAINED_PRO=y
+CONFIG_ARCH_CHIP="samd5e5"
+CONFIG_ARCH_CHIP_SAME54P20=y
+CONFIG_ARCH_CHIP_SAME5X=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=7225
+CONFIG_BUILTIN=y
+CONFIG_DISABLE_ENVIRON=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_PTHREAD_STACK_DEFAULT=1536
+CONFIG_RAM_SIZE=196608
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SAMD5E5_CMCC=y
+CONFIG_SAMD5E5_EIC=y
+CONFIG_SAMD5E5_SERCOM2=y
+CONFIG_SAMD5E5_SERCOM3=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=23
+CONFIG_START_MONTH=7
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
+CONFIG_USART2_SERIAL_CONSOLE=y
+CONFIG_USART3_RXBUFSIZE=64
+CONFIG_USART3_TXBUFSIZE=64
+CONFIG_USERMAIN_STACKSIZE=1536
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=0
diff --git a/boards/arm/samd5e5/same54-xplained-pro/include/board.h b/boards/arm/samd5e5/same54-xplained-pro/include/board.h
new file mode 100644
index 0000000..bb67025
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/include/board.h
@@ -0,0 +1,503 @@
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/include/board.h
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_ARM_SAMD5E5_SAME54_XPLAINED_PRO_INCLUDE_BOARD_H
+#define __BOARDS_ARM_SAMD5E5_SAME54_XPLAINED_PRO_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef TRUE
+# define TRUE 1
+#endif
+
+#ifndef FALSE
+# define FALSE 0
+#endif
+
+/* Clocking *****************************************************************/
+
+/* Overview
+ *
+ * Per the schematic Adafruit Metro M4 Pro has one on-board crystal:
+ *
+ * X4 32.768KHz XOSC32
+ *
+ * However, I have been unsuccessful using it and have fallen back to using
+ * OSCULP32K(Unless CONFIG_SAME54_XPLAINED_PRO_32KHZXTAL=y)
+ *
+ * Since there is no high speed crystal, we will run from the OSC16M clock
+ * source.
+ *
+ * OSC48M Output = 48Mhz
+ * |
+ * FDLL Input = 48MHz
+ * | Output = 48MHz
+ * GCLK5 Input = 48MHz
+ * | Output = 2MHz
+ * DPLL0 Input = 2MHz
+ * | Output = 120MHz
+ * GCLK0 Input = 120MHz
+ * | Output = 120MHz
+ * MCK Input = 120MHz
+ * | Output = 120MHz
+ * CPU Input = 120MHz
+ */
+
+#define BOARD_OSC32K_FREQUENCY 32768 /* OSCULP32K frequency 32.768 KHz (nominal) */
+#define BOARD_XOSC32K_FREQUENCY 32768 /* XOSC32K frequency 32.768 KHz */
+#define BOARD_DFLL_FREQUENCY 48000000 /* FDLL frequency 28MHz */
+#define BOARD_XOSC0_FREQUENCY 12000000 /* XOSC0 frequency 12MHz (disabled) */
+#define BOARD_XOSC1_FREQUENCY 12000000 /* XOSC0 frequency 12MHz (disabled)*/
+#define BOARD_DPLL0_FREQUENCY 120000000 /* DPLL0 output frueuency (120MHz) */
+#define BOARD_DPLL1_FREQUENCY 47985664 /* DPLL1 output frequency (disabled) */
+
+#define BOARD_GCLK0_FREQUENCY BOARD_DPLL0_FREQUENCY
+#define BOARD_GCLK1_FREQUENCY BOARD_DFLL_FREQUENCY
+#define BOARD_GCLK2_FREQUENCY (BOARD_XOSC32K_FREQUENCY / 4) /* Disabled */
+#ifdef CONFIG_SAME54_XPLAINED_PRO_32KHZXTAL
+# define BOARD_GCLK3_FREQUENCY BOARD_XOSC32K_FREQUENCY /* Enabled */
+#else
+# define BOARD_GCLK3_FREQUENCY BOARD_OSC32K_FREQUENCY /* Always-on */
+#endif
+#define BOARD_GCLK4_FREQUENCY BOARD_DPLL0_FREQUENCY
+#define BOARD_GCLK5_FREQUENCY (BOARD_DFLL_FREQUENCY / 24)
+#define BOARD_GCLK6_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
+#define BOARD_GCLK7_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
+#define BOARD_GCLK8_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
+#define BOARD_GCLK9_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
+#define BOARD_GCLK10_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
+#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
+
+#define BOARD_CPU_FREQUENCY BOARD_GCLK0_FREQUENCY /* CPU frequency 120MHz */
+
+/* XOSC32 */
+
+#ifdef CONFIG_SAME54_XPLAINED_PRO_32KHZXTAL
+# define BOARD_HAVE_XOSC32K 1 /* 32.768 KHz XOSC32 crystal installed */
+# define BOARD_XOSC32K_ENABLE TRUE /* Enable XOSC32 */
+#else
+# define BOARD_HAVE_XOSC32K 0 /* No 32.768 KHz XOSC32 crystal installed */
+# define BOARD_XOSC32K_ENABLE FALSE /* Disable XOSC32 */
+#endif
+#define BOARD_XOSC32K_XTALEN TRUE /* Crystal connected on XIN32 */
+#define BOARD_XOSC32K_EN32K FALSE /* No 32KHz output */
+#define BOARD_XOSC32K_EN1K FALSE /* No 1KHz output */
+#define BOARD_XOSC32K_HIGHSPEED TRUE /* High speed mode */
+#define BOARD_XOSC32K_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_XOSC32K_ONDEMAND TRUE /* Enable on-demand control */
+#define BOARD_XOSC32K_CFDEN FALSE /* Clock failure detector not enabled */
+#define BOARD_XOSC32K_CFDEO FALSE /* No clock failure event */
+#define BOARD_XOSC32K_CALIBEN FALSE /* No OSCULP32K calibration */
+#define BOARD_XOSC32K_STARTUP 0 /* Startup time: 62592us */
+#define BOARD_XOSC32K_CALIB 0 /* Dummy OSCULP32K calibration value */
+#define BOARD_XOSC32K_RTCSEL 0 /* RTC clock = ULP1K */
+
+/* XOSC0 */
+
+#define BOARD_HAVE_XOSC0 0 /* No XOSC0 clock/crystal installed */
+#define BOARD_XOSC0_ENABLE FALSE /* Don't enable XOSC0 */
+#define BOARD_XOSC0_XTALEN FALSE /* External clock connected */
+#define BOARD_XOSC0_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_XOSC0_ONDEMAND TRUE /* Disable on-demand control */
+#define BOARD_XOSC0_LOWGAIN FALSE /* Disable low buffer gain */
+#define BOARD_XOSC0_ENALC FALSE /* Disable automatic loop control */
+#define BOARD_XOSC0_CFDEN FALSE /* Clock failure detector not enabled */
+#define BOARD_XOSC0_SWBEN FALSE /* XOSC clock switch not enabled */
+#define BOARD_XOSC0_STARTUP 0 /* XOSC0 start-up time 31µs */
+
+/* XOSC1 */
+
+#define BOARD_HAVE_XOSC1 0 /* No XOSC0 clock/crystal installed */
+#define BOARD_XOSC1_ENABLE FALSE /* Don't enable XOSC1 */
+#define BOARD_XOSC1_XTALEN TRUE /* External crystal connected */
+#define BOARD_XOSC1_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_XOSC1_ONDEMAND TRUE /* Disable on-demand control */
+#define BOARD_XOSC1_LOWGAIN FALSE /* Disable low buffer gain */
+#define BOARD_XOSC1_ENALC FALSE /* Disable automatic loop control */
+#define BOARD_XOSC1_CFDEN FALSE /* Clock failure detector not enabled */
+#define BOARD_XOSC1_SWBEN FALSE /* XOSC clock switch not enabled */
+#define BOARD_XOSC1_STARTUP 0 /* XOSC0 start-up time 31µs */
+
+/* GCLK */
+
+#define BOARD_GCLK_SET1 0x0020 /* Pre-configure: GCLK5 needed by DPLL0 */
+#define BOARD_GCLK_SET2 0x0fdf /* Post-configure: All GCLKs except GCLK5 */
+
+#define BOARD_GCLK0_ENABLE TRUE /* Enable GCLK0 */
+#define BOARD_GCLK0_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK0_OE TRUE /* Generate output on GCLK_IO */
+#define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */
+#define BOARD_GCLK0_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK0_SOURCE 7 /* Select DPLL0 output as GCLK0 source */
+#define BOARD_GCLK0_DIV 1 /* Division factor */
+
+#define BOARD_GCLK1_ENABLE TRUE /* Enable GCLK1 */
+#define BOARD_GCLK1_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK1_OE TRUE /* Generate output on GCLK_IO */
+#define BOARD_GCLK1_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GCLK1 source */
+#define BOARD_GCLK1_DIV 1 /* Division factor */
+
+#define BOARD_GCLK2_ENABLE FALSE /* Don't enable GCLK2 */
+#define BOARD_GCLK2_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK2_OE FALSE /* No generator output of GCLK_IO */
+#define BOARD_GCLK2_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK2_SOURCE 1 /* Select XOSC1 as GCLK2 source */
+#define BOARD_GCLK2_DIV 1 /* Division factor */
+
+#define BOARD_GCLK3_ENABLE TRUE /* Enable GCLK3 */
+#define BOARD_GCLK3_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK3_OE FALSE /* No generator output of GCLK_IO */
+#define BOARD_GCLK3_RUNSTDBY FALSE /* Don't run in standby */
+#ifdef CONFIG_SAME54_XPLAINED_PRO_32KHZXTAL
+# define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
+#else
+# define BOARD_GCLK3_SOURCE 4 /* Select OSCULP32K as GCLK3 source */
+#endif
+#define BOARD_GCLK3_DIV 1 /* Division factor */
+
+#define BOARD_GCLK4_ENABLE TRUE /* Enable GCLK4 */
+#define BOARD_GCLK4_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK4_OE TRUE /* Generate output on GCLK_IO */
+#define BOARD_GCLK4_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GCLK4 source */
+#define BOARD_GCLK4_DIV 1 /* Division factor */
+
+#define BOARD_GCLK5_ENABLE TRUE /* Enable GCLK5 */
+#define BOARD_GCLK5_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK5_OE TRUE /* Generate output on GCLK_IO */
+#define BOARD_GCLK5_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GCLK5 source */
+#define BOARD_GCLK5_DIV 24 /* Division factor */
+
+#define BOARD_GCLK6_ENABLE FALSE /* Don't enable GCLK6 */
+#define BOARD_GCLK6_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK6_OE FALSE /* No generator output of GCLK_IO */
+#define BOARD_GCLK6_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GCLK6 source */
+#define BOARD_GCLK6_DIV 1 /* Division factor */
+
+#define BOARD_GCLK7_ENABLE FALSE /* Don't enable GCLK7 */
+#define BOARD_GCLK7_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK7_OE FALSE /* No generator output of GCLK_IO */
+#define BOARD_GCLK7_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GCLK7 source */
+#define BOARD_GCLK7_DIV 1 /* Division factor */
+
+#define BOARD_GCLK8_ENABLE FALSE /* Don't enable GCLK8 */
+#define BOARD_GCLK8_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK8_OE FALSE /* No generator output of GCLK_IO */
+#define BOARD_GCLK8_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GCLK8 source */
+#define BOARD_GCLK8_DIV 1 /* Division factor */
+
+#define BOARD_GCLK9_ENABLE FALSE /* Don't enable GCLK9 */
+#define BOARD_GCLK9_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK9_OE FALSE /* No generator output of GCLK_IO */
+#define BOARD_GCLK9_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GCLK9 source */
+#define BOARD_GCLK9_DIV 1 /* Division factor */
+
+#define BOARD_GCLK10_ENABLE FALSE /* Don't enable GCLK10 */
+#define BOARD_GCLK10_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK10_OE FALSE /* No generator output of GCLK_IO */
+#define BOARD_GCLK10_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GCLK10 source */
+#define BOARD_GCLK10_DIV 1 /* Division factor */
+
+#define BOARD_GCLK11_ENABLE FALSE /* Don't enable GCLK11 */
+#define BOARD_GCLK11_OOV FALSE /* Clock output will be LOW */
+#define BOARD_GCLK11_OE FALSE /* No generator output of GCLK_IO */
+#define BOARD_GCLK11_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GCLK11 source */
+#define BOARD_GCLK11_DIV 1 /* Division factor */
+#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY
+
+/* FDLL */
+
+#define BOARD_DFLL_ENABLE TRUE /* DFLL enable */
+#define BOARD_DFLL_RUNSTDBY FALSE /* Don't run in standby */
+#define BOARD_DFLL_ONDEMAND FALSE /* No n-demand control */
+#define BOARD_DFLL_MODE FALSE /* Open loop mode */
+#define BOARD_DFLL_STABLE FALSE /* No stable DFLL frequency */
+#define BOARD_DFLL_LLAW FALSE /* Don't ose lock after wake */
+#define BOARD_DFLL_USBCRM TRUE /* Use USB clock recovery mode */
+#define BOARD_DFLL_CCDIS TRUE /* Chill cycle disable */
+#define BOARD_DFLL_QLDIS FALSE /* No Quick Lock Disable */
+#define BOARD_DFLL_BPLCKC FALSE /* No ypass coarse clock */
+#define BOARD_DFLL_WAITLOCK TRUE /* Wait lock */
+#define BOARD_DFLL_CALIBEN FALSE /* Don't verwrite factory calibration */
+#define BOARD_DFLL_GCLKLOCK FALSE /* Don't lock the GCLK source */
+#define BOARD_DFLL_FCALIB 128 /* Coarse calibration value (if caliben) */
+#define BOARD_DFLL_CCALIB (31 / 4) /* Fine calibration value (if caliben) */
+#define BOARD_DFLL_FSTEP 1 /* Fine maximum step */
+#define BOARD_DFLL_CSTEP 1 /* Coarse maximum step */
+#define BOARD_DFLL_GCLK 3 /* GCLK source (if !usbcrm && !mode) */
+#define BOARD_DFLL_MUL 0 /* DFLL multiply factor */
+
+/* DPLL0/1
+ *
+ * Fckr is the frequency of the selected reference clock reference:
+ *
+ * BOARD_XOSC32K_FREQENCY,
+ * BOARD_XOSCn_FREQUENCY / DIV, or
+ * BOARD_GCLKn_FREQUENCY
+ *
+ * The DPLL output frequency is then given by:
+ *
+ * Fdpll = Fckr * (LDR + 1 + LDRFRAC / 32)
+ *
+ * DPLL0:
+ * Fckr = BOARD_GCLK5_FREQUENCY = BOARD_DFLL_FREQUENCY / 24 = 2MHz
+ * Fdpll = 2Mhz * (59 + 1 + 0 / 32) = 120MHz
+ *
+ * DPLL1: (not enabled)
+ * Fckr = BOARD_XOSCK32_FREQUENCY = 32.768KHz
+ * Fdpll = 32768 * (1463 + 1 + 13/32) = 47.986 MHz
+ */
+
+#define BOARD_DPLL0_ENABLE TRUE /* DPLL enable */
+#define BOARD_DPLL0_DCOEN FALSE /* DCO filter enable */
+#define BOARD_DPLL0_LBYPASS FALSE /* Lock bypass */
+#define BOARD_DPLL0_WUF FALSE /* Wake up fast */
+#define BOARD_DPLL0_RUNSTDBY FALSE /* Run in standby */
+#define BOARD_DPLL0_ONDEMAND FALSE /* On demand clock activation */
+#define BOARD_DPLL0_REFLOCK FALSE /* Do not lock reference clock section */
+#define BOARD_DPLL0_REFCLK 0 /* Reference clock selection */
+#define BOARD_DPLL0_LTIME 0 /* Lock time */
+#define BOARD_DPLL0_FILTER 0 /* Proportional integer filter selection */
+#define BOARD_DPLL0_DCOFILTER 0 /* Sigma-delta DCO filter selection */
+#define BOARD_DPLL0_GCLK 5 /* GCLK source (if refclock == 0) */
+#define BOARD_DPLL0_GCLKLOCK 0 /* Don't lock GCLK source clock configuration */
+#define BOARD_DPLL0_LDRFRAC 0 /* Loop divider fractional part */
+#define BOARD_DPLL0_LDRINT 59 /* Loop divider ratio */
+#define BOARD_DPLL0_DIV 0 /* Clock divider */
+
+#define BOARD_DPLL1_ENABLE FALSE /* DPLL enable */
+#define BOARD_DPLL1_DCOEN FALSE /* DCO filter enable */
+#define BOARD_DPLL1_LBYPASS FALSE /* Lock bypass */
+#define BOARD_DPLL1_WUF FALSE /* Wake up fast */
+#define BOARD_DPLL1_RUNSTDBY FALSE /* Run in standby */
+#define BOARD_DPLL1_ONDEMAND FALSE /* On demand clock activation */
+#define BOARD_DPLL1_REFLOCK FALSE /* Do not lock reference clock section */
+#define BOARD_DPLL1_REFCLK 1 /* Reference clock = XOSCK32 */
+#define BOARD_DPLL1_LTIME 0 /* Lock time */
+#define BOARD_DPLL1_FILTER 0 /* Sigma-delta DCO filter selection */
+#define BOARD_DPLL1_DCOFILTER 0 /* Sigma-delta DCO filter selection */
+#define BOARD_DPLL1_GCLK 0 /* GCLK source (if refclock == 0) */
+#define BOARD_DPLL1_GCLKLOCK 0 /* Don't lock GCLK source clock configuration */
+#define BOARD_DPLL1_LDRFRAC 13 /* Loop divider fractional part */
+#define BOARD_DPLL1_LDRINT 1463 /* Loop divider ratio */
+#define BOARD_DPLL1_DIV 0 /* Clock divider */
+
+/* Master Clock (MCLK)
+ *
+ * GCLK0 is always the direct source the GCLK_MAIN.
+ * CPU frequency = 120MHz / 1 = 120MHz
+ */
+
+#define BOARD_MCLK_CPUDIV 1 /* MCLK divder to get CPU frequency */
+
+#define BOARD_MCK_FREQUENCY BOARD_GCLK0_FREQUENCY
+
+/* Peripheral clocking */
+
+#define BOARD_GCLK_EIC 4 /* EIC GCLK index */
+
+/* FLASH wait states
+ *
+ * Vdd Range Wait states Maximum Operating Frequency
+ * --------- ----------- ---------------------------
+ * > 2.7V 0 24 MHz
+ * 1 51 MHz
+ * 2 77 MHz
+ * 3 101 MHz
+ * 4 119 MHz
+ * 5 120 MHz
+ * >1.71V 0 22 MHz
+ * 1 44 MHz
+ * 2 67 MHz
+ * 3 89 MHz
+ * 4 111 MHz
+ * 5 120 MHz
+ */
+
+#define BOARD_FLASH_WAITSTATES 6
+
+/* LED definitions **********************************************************/
+
+/* LEDs
+ *
+ * The SAME54 Xplained Pro has three LEDs, but only one is controllable by software:
+ *
+ * 1. LED0 near the edge of the board
+ *
+ *
+ * ----------------- -----------
+ * SAMD5E5 FUNCTION
+ * ----------------- -----------
+ * PC18 GPIO output
+ *
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED0 0
+#define BOARD_NLEDS 1
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED0_BIT (1 << BOARD_LED0)
+
+/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is
+ * defined. In that case, the usage by the board port is defined in
+ * include/board.h and src/sam_autoleds.c. The LEDs are used to encode
+ * OS-related events as follows:
+ *
+ * ------------------- ---------------------------- ------
+ * SYMBOL Meaning LED
+ * ------------------- ---------------------------- ------
+ */
+
+#define LED_STARTED 0 /* NuttX has been started OFF */
+#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */
+#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */
+#define LED_STACKCREATED 1 /* Idle stack created ON */
+#define LED_INIRQ 2 /* In an interrupt N/C */
+#define LED_SIGNAL 2 /* In a signal handler N/C */
+#define LED_ASSERTION 2 /* An assertion failed N/C */
+#define LED_PANIC 3 /* The system has crashed FLASH */
+#undef LED_IDLE /* MCU is is sleep mode Not used */
+
+/* Thus is LED is statically on, NuttX has successfully booted and is,
+ * apparently, running normally. If LED is flashing at approximately
+ * 2Hz, then a fatal error has been detected and the system has halted.
+ */
+
+/* Alternate function pin selections ****************************************/
+
+/* SERCOM definitions *******************************************************/
+
+/* The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the
+ * Main Clock Controller.
+ * The SERCOM uses two generic clocks: GCLK_SERCOMn_CORE and GCLK_SERCOM_SLOW.
+ * The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while
+ * working as a master. The slow clock (GCLK_SERCOM_SLOW) is only required
+ * for certain functions and is common to all SERCOM modules.
+ *
+ * These clocks must be configured and enabled in the Generic Clock
+ * Controller (GCLK) before using the SERCOM.
+ */
+
+#define BOARD_SERCOM_SLOWGEN 3 /* 32.768KHz, common to all SERCOMS */
+#define BOARD_SERCOM_SLOWLOCK FALSE /* Don't lock the SLOWCLOCK */
+#define BOARD_SLOWCLOCK_FREQUENCY BOARD_GCLK3_FREQUENCY
+
+/* SERCOM2
+ *
+ * Built-in virtual COM port using the EDBG chip on the board.
+ * DTR must be asserted by your console software in order to enable this port.
+ *
+ * ----------------- ---------
+ * SAMD5E5 FUNCTION
+ * ----------------- ---------
+ * PB24 SERCOM2 PAD1 RXD
+ * PB25 SERCOM2 PAD0 TXD
+ *
+ * NOTES:
+ * USART_CTRLA_TXPAD0_2: TxD=PAD0 XCK=N/A RTS/TE=PAD2 CTS=PAD3
+ * USART_CTRLA_RXPAD1: RxD=PAD1
+ */
+
+#define BOARD_SERCOM2_MUXCONFIG (USART_CTRLA_TXPAD0_2 | USART_CTRLA_RXPAD1)
+#define BOARD_SERCOM2_PINMAP_PAD0 PORT_SERCOM2_PAD0_4 /* PAD0: USART TX */
+#define BOARD_SERCOM2_PINMAP_PAD1 PORT_SERCOM2_PAD1_4 /* PAD1: USART RX */
+#define BOARD_SERCOM2_PINMAP_PAD2 0 /* PAD2: (not used) */
+#define BOARD_SERCOM2_PINMAP_PAD3 0 /* PAD3: (not used) */
+
+#define BOARD_TXIRQ_SERCOM2 SAM_IRQ_SERCOM2_0 /* INTFLAG[0] DRE */
+#define BOARD_RXIRQ_SERCOM2 SAM_IRQ_SERCOM2_2 /* INTFLAG[2] RXC */
+
+#define BOARD_SERCOM2_COREGEN 1 /* 48MHz Core clock */
+#define BOARD_SERCOM2_CORELOCK FALSE /* Don't lock the CORECLOCK */
+#define BOARD_SERCOM2_FREQUENCY BOARD_GCLK1_FREQUENCY
+
+/* SERCOM3
+ *
+ * An external RS-232 or serial-to-USB adapter can be connected on pins PA22
+ * and PA23:
+ *
+ * ----------------- ---------
+ * SAMD5E5 FUNCTION
+ * ----------------- ---------
+ * PA23 SERCOM3 PAD1 RXD
+ * PA22 SERCOM3 PAD0 TXD
+ *
+ * NOTES:
+ * USART_CTRLA_TXPAD0_2: TxD=PAD0 XCK=N/A RTS/TE=PAD2 CTS=PAD3
+ * USART_CTRLA_RXPAD1: RxD=PAD1
+ */
+
+#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_TXPAD0_2 | USART_CTRLA_RXPAD1)
+#define BOARD_SERCOM3_PINMAP_PAD0 PORT_SERCOM3_PAD0_1 /* PAD0: USART TX */
+#define BOARD_SERCOM3_PINMAP_PAD1 PORT_SERCOM3_PAD1_1 /* PAD1: USART RX */
+#define BOARD_SERCOM3_PINMAP_PAD2 0 /* PAD2: (not used) */
+#define BOARD_SERCOM3_PINMAP_PAD3 0 /* PAD3: (not used) */
+
+#define BOARD_TXIRQ_SERCOM3 SAM_IRQ_SERCOM3_0 /* INTFLAG[0] DRE */
+#define BOARD_RXIRQ_SERCOM3 SAM_IRQ_SERCOM3_2 /* INTFLAG[2] RXC */
+
+#define BOARD_SERCOM3_COREGEN 1 /* 48MHz Core clock */
+#define BOARD_SERCOM3_CORELOCK FALSE /* Don't lock the CORECLOCK */
+#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK1_FREQUENCY
+
+/* USB */
+
+#define BOARD_USB_GCLKGEN 1 /* GCLK1, 48MHz */
+
+/* Ethernet */
+
+#define BOARD_GMAC_GMDC PORT_GMAC_GMDC_3
+#define BOARD_GMAC_GMDIO PORT_GMAC_GMDIO_3
+
+#endif /* __BOARDS_ARM_SAMD5E5_SAME54_XPLAINED_PRO_INCLUDE_BOARD_H */
diff --git a/boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs b/boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs
new file mode 100644
index 0000000..f9ecb17
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs
@@ -0,0 +1,128 @@
+############################################################################
+# boards/arm/samd5e5/same54-xplained-pro/scripts/Make.defs
+#
+# Copyright (C) 2018 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gn...@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+ifeq ($(CONFIG_SAME54_XPLAINED_PRO_RUNFROMFLASH),y)
+ LDSCRIPT = flash.ld
+else ifeq ($(CONFIG_SAME54_XPLAINED_PRO_RUNFROMSRAM),y)
+ LDSCRIPT = sram.ld
+endif
+
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+# Loadable module definitions
+
+CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
+
+LDMODULEFLAGS = -r -e module_initialize
+ifeq ($(WINTOOL),y)
+ LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}"
+else
+ LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld
+endif
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
diff --git a/boards/arm/samd5e5/same54-xplained-pro/scripts/flash.ld b/boards/arm/samd5e5/same54-xplained-pro/scripts/flash.ld
new file mode 100644
index 0000000..4a4c9e2
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/scripts/flash.ld
@@ -0,0 +1,123 @@
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/scripts/flash.ld
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The ATSAME54P20A has 1024Kb of FLASH beginning at address 0x0000:0000 and
+ * 256Kb of SRAM at address 0x2000:0000.
+ */
+
+MEMORY
+{
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 1024K
+ sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+EXTERN(_vectors)
+SECTIONS
+{
+ .text :
+ {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > flash
+
+ .init_section :
+ {
+ _sinit = ABSOLUTE(.);
+ *(.init_array .init_array.*)
+ _einit = ABSOLUTE(.);
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } > flash
+
+ __exidx_start = ABSOLUTE(.);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } > flash
+ __exidx_end = ABSOLUTE(.);
+
+ _eronly = ABSOLUTE(.);
+
+ .data :
+ {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ . = ALIGN(4);
+ _edata = ABSOLUTE(.);
+ } > sram AT > flash
+
+ .bss :
+ {
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = ABSOLUTE(.);
+ } > sram
+
+ /* Stabs debugging sections. */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/arch/arm/src/samd5e5/hardware/sam_memorymap.h b/boards/arm/samd5e5/same54-xplained-pro/scripts/nvm.c
similarity index 62%
copy from arch/arm/src/samd5e5/hardware/sam_memorymap.h
copy to boards/arm/samd5e5/same54-xplained-pro/scripts/nvm.c
index ef08130..c30c14c 100644
--- a/arch/arm/src/samd5e5/hardware/sam_memorymap.h
+++ b/boards/arm/samd5e5/same54-xplained-pro/scripts/nvm.c
@@ -1,9 +1,8 @@
-/************************************************************************************
- * arch/arm/src/samd5e5/hardware/sam_memorymap.h
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/scripts/nvm.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
+ * Author: Gregory Nutt 9
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -31,22 +30,45 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
+
+#include <stdio.h>
+#include <stdint.h>
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const uint8_t nvm[20] =
+{
+ 0x14, /* Count 20 bytes */
+ 0x80, 0x40, 0x00, /* 24-address : 804000 */
+ 0x39, 0x92, 0x9a, 0xfe, 0x80, 0xff, 0xec, 0xae, /* 16-bytes of NVM data */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-#include <nuttx/config.h>
+int main(int argc, char **argv)
+{
+ unsigned int csum;
+ int i;
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
-# include "hardware/samd5e5_memorymap.h"
-#else
-# error "Unsupported SAMD5/E5 family"
-#endif
+ printf("S2");
-#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H */
+ for (i = 0, csum = 0; i < 20; i++)
+ {
+ csum += nvm[i];
+ printf("%02X", (unsigned int)nvm[i]);
+ }
+ printf("%02X\r\n", ~csum & 0xff);
+ printf("S9030000FC\r\n");
+ return 0;
+}
diff --git a/boards/arm/samd5e5/same54-xplained-pro/scripts/nvm.srec b/boards/arm/samd5e5/same54-xplained-pro/scripts/nvm.srec
new file mode 100644
index 0000000..dbe9523
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/scripts/nvm.srec
@@ -0,0 +1,2 @@
+S21480400039929AFE80FFECAEFFFFFFFFFFFFFFFFB7
+S9030000FC
diff --git a/boards/arm/samd5e5/same54-xplained-pro/scripts/sram.ld b/boards/arm/samd5e5/same54-xplained-pro/scripts/sram.ld
new file mode 100644
index 0000000..f7b19a4
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/scripts/sram.ld
@@ -0,0 +1,122 @@
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/scripts/sram.ld
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The ATSAME54P20A has 1024Kb of FLASH beginning at address 0x0000:0000 and
+ * 256Kb of SRAM at address 0x2000:0000. Only sram is used by this linker
+ * script.
+ */
+
+MEMORY
+{
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 1024K
+ sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+EXTERN(_vectors)
+SECTIONS
+{
+ .text :
+ {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > sram
+
+ .init_section :
+ {
+ _sinit = ABSOLUTE(.);
+ *(.init_array .init_array.*)
+ _einit = ABSOLUTE(.);
+ } > sram
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } > sram
+
+ __exidx_start = ABSOLUTE(.);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx*)
+ } > sram
+ __exidx_end = ABSOLUTE(.);
+
+ .data :
+ {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ . = ALIGN(4);
+ _edata = ABSOLUTE(.);
+ } > sram
+
+ .bss :
+ {
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = ABSOLUTE(.);
+ } > sram
+
+ /* Stabs debugging sections. */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/boards/arm/samd5e5/same54-xplained-pro/src/Makefile b/boards/arm/samd5e5/same54-xplained-pro/src/Makefile
new file mode 100644
index 0000000..f53cae7
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/src/Makefile
@@ -0,0 +1,55 @@
+############################################################################
+# boards/arm/samd5e5/same54-xplained-pro/src/Makefile
+#
+# Copyright (C) 2018 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gn...@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+ASRCS =
+CSRCS = sam_boot.c sam_bringup.c
+
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
+CSRCS += sam_appinit.c
+endif
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += sam_autoleds.c
+else
+CSRCS += sam_userleds.c
+endif
+
+ifeq ($(CONFIG_SAMD5E5_GMAC_PHYINIT), y)
+CSRCS += sam_phyinit.c
+endif
+
+include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/samd5e5/same54-xplained-pro/src/sam_appinit.c b/boards/arm/samd5e5/same54-xplained-pro/src/sam_appinit.c
new file mode 100644
index 0000000..261a846
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/src/sam_appinit.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/src/sam_appinit.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/board.h>
+
+#include "same54-xplained-pro.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef OK
+# define OK 0
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value cold be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
+
+ return OK;
+#else
+ /* Perform board-specific initialization */
+
+ return sam_bringup();
+#endif
+}
diff --git a/boards/arm/samd5e5/same54-xplained-pro/src/sam_autoleds.c b/boards/arm/samd5e5/same54-xplained-pro/src/sam_autoleds.c
new file mode 100644
index 0000000..5ebec70
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/src/sam_autoleds.c
@@ -0,0 +1,295 @@
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/src/sam_autoleds.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The SAME54 Xplained Pro has three LEDs, but only one is controllable by software:
+ *
+ * 1. LED0 near the edge of the board
+ *
+ * ----------------- -----------
+ * SAMD5E5 FUNCTION
+ * ----------------- -----------
+ * PC18 GPIO output
+ *
+ * This LED is not used by the board port unless CONFIG_ARCH_LEDS is
+ * defined. In that case, the usage by the board port is defined in
+ * include/board.h and src/sam_autoleds.c. The LEDs are used to encode
+ * OS-related events as follows:
+ *
+ * ------------------- ---------------------------- ------
+ * SYMBOL Meaning LED
+ * ------------------- ---------------------------- ------
+ *
+ * LED_STARTED NuttX has been started OFF
+ * LED_HEAPALLOCATE Heap has been allocated OFF
+ * LED_IRQSENABLED Interrupts enabled OFF
+ * LED_STACKCREATED Idle stack created ON
+ * LED_INIRQ In an interrupt N/C
+ * LED_SIGNAL In a signal handler N/C
+ * LED_ASSERTION An assertion failed N/C
+ * LED_PANIC The system has crashed FLASH
+ * LED_IDLE MCU is is sleep mode Not used
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/power/pm.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "sam_port.h"
+#include "same54-xplained-pro.h"
+
+#include <arch/board/board.h>
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* LED Power Management */
+
+#ifdef CONFIG_PM
+static void led_pm_notify(struct pm_callback_s *cb, int domain,
+ enum pm_state_e pmstate);
+static int led_pm_prepare(struct pm_callback_s *cb, int domain,
+ enum pm_state_e pmstate);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static struct pm_callback_s g_ledscb =
+{
+ .notify = led_pm_notify,
+ .prepare = led_pm_prepare,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: led_pm_notify
+ *
+ * Description:
+ * Notify the driver of new power state. This callback is called after
+ * all drivers have had the opportunity to prepare for the new power state.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static void led_pm_notify(struct pm_callback_s *cb, int domain,
+ enum pm_state_e pmstate)
+{
+ switch (pmstate)
+ {
+ case(PM_NORMAL):
+ {
+ /* Restore normal LEDs operation */
+ }
+ break;
+
+ case(PM_IDLE):
+ {
+ /* Entering IDLE mode - Turn leds off */
+ }
+ break;
+
+ case(PM_STANDBY):
+ {
+ /* Entering STANDBY mode - Logic for PM_STANDBY goes here */
+ }
+ break;
+
+ case(PM_SLEEP):
+ {
+ /* Entering SLEEP mode - Logic for PM_SLEEP goes here */
+ }
+ break;
+
+ default:
+ {
+ /* Should not get here */
+ }
+ break;
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: led_pm_prepare
+ *
+ * Description:
+ * Request the driver to prepare for a new power state. This is a warning
+ * that the system is about to enter into a new power state. The driver
+ * should begin whatever operations that may be required to enter power
+ * state. The driver may abort the state change mode by returning a
+ * non-zero value from the callback function.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static int led_pm_prepare(struct pm_callback_s *cb, int domain,
+ enum pm_state_e pmstate)
+{
+ /* No preparation to change power modes is required by the LEDs driver.
+ * We always accept the state change by returning OK.
+ */
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+ (void)sam_portconfig(PORT_LED0);
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+ bool ledstate = true;
+
+ switch (led)
+ {
+ case 0: /* LED_STARTED: NuttX has been started STATUS LED=OFF
+ * LED_HEAPALLOCATE: Heap has been allocated STATUS LED=OFF
+ * LED_IRQSENABLED: Interrupts enabled STATUS LED=OFF
+ */
+
+ break; /* Leave ledstate == true to turn OFF */
+
+ default:
+ case 2: /* LED_INIRQ: In an interrupt STATUS LED=N/C
+ * LED_SIGNAL: In a signal handler STATUS LED=N/C
+ * LED_ASSERTION: An assertion failed STATUS LED=N/C
+ */
+
+ return; /* Return to leave STATUS LED unchanged */
+
+ case 3: /* LED_PANIC: The system has crashed STATUS LED=FLASH */
+ case 1: /* LED_STACKCREATED: Idle stack created STATUS LED=ON */
+ ledstate = false; /* Set ledstate == false to turn ON */
+ break;
+ }
+
+ sam_portwrite(PORT_LED0, ledstate);
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+ switch (led)
+ {
+ /* These should not happen and are ignored */
+
+ default:
+ case 0: /* LED_STARTED: NuttX has been started STATUS LED=OFF
+ * LED_HEAPALLOCATE: Heap has been allocated STATUS LED=OFF
+ * LED_IRQSENABLED: Interrupts enabled STATUS LED=OFF
+ */
+
+ case 1: /* LED_STACKCREATED: Idle stack created STATUS LED=ON */
+
+ /* These result in no-change */
+
+ case 2: /* LED_INIRQ: In an interrupt STATUS LED=N/C
+ * LED_SIGNAL: In a signal handler STATUS LED=N/C
+ * LED_ASSERTION: An assertion failed STATUS LED=N/C
+ */
+
+ return; /* Return to leave STATUS LED unchanged */
+
+ /* Turn STATUS LED off set driving the output high */
+
+ case 3: /* LED_PANIC: The system has crashed STATUS LED=FLASH */
+ sam_portwrite(PORT_LED0, true);
+ break;
+ }
+}
+
+/****************************************************************************
+ * Name: sam_led_pminitialize
+ *
+ * Description:
+ * Register LED power management features.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+void sam_led_pminitialize(void)
+{
+ /* Register to receive power management callbacks */
+
+ int ret = pm_register(&g_ledscb);
+ if (ret != OK)
+ {
+ board_autoled_on(LED_ASSERTION);
+ }
+}
+#endif /* CONFIG_PM */
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/arch/arm/src/samd5e5/hardware/sam_memorymap.h b/boards/arm/samd5e5/same54-xplained-pro/src/sam_boot.c
similarity index 51%
copy from arch/arm/src/samd5e5/hardware/sam_memorymap.h
copy to boards/arm/samd5e5/same54-xplained-pro/src/sam_boot.c
index ef08130..8e713a6 100644
--- a/arch/arm/src/samd5e5/hardware/sam_memorymap.h
+++ b/boards/arm/samd5e5/same54-xplained-pro/src/sam_boot.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/samd5e5/hardware/sam_memorymap.h
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/src/sam_boot.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,22 +31,64 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
-# include "hardware/samd5e5_memorymap.h"
-#else
-# error "Unsupported SAMD5/E5 family"
+#include <debug.h>
+
+#include <nuttx/board.h>
+
+#include "same54-xplained-pro.h"
+
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_board_initialize
+ *
+ * Description:
+ * All SAMD5/E5 architectures must provide the following entry point.
+ * This entry point is called early in the initialization -- after all
+ * memory has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
+
+void sam_board_initialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected. */
+
+ board_autoled_initialize();
#endif
+}
-#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H */
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will be
+ * called immediately after up_initialize() is called and just before the
+ * initial application is started. This additional initialization phase
+ * may be used, for example, to initialize board-specific device drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
+ (void)sam_bringup();
+}
+#endif
diff --git a/arch/arm/src/samd5e5/hardware/sam_memorymap.h b/boards/arm/samd5e5/same54-xplained-pro/src/sam_bringup.c
similarity index 57%
copy from arch/arm/src/samd5e5/hardware/sam_memorymap.h
copy to boards/arm/samd5e5/same54-xplained-pro/src/sam_bringup.c
index ef08130..b2ea8a3 100644
--- a/arch/arm/src/samd5e5/hardware/sam_memorymap.h
+++ b/boards/arm/samd5e5/same54-xplained-pro/src/sam_bringup.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/samd5e5/hardware/sam_memorymap.h
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/src/sam_bringup.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,22 +31,61 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
-# include "hardware/samd5e5_memorymap.h"
-#else
-# error "Unsupported SAMD5/E5 family"
-#endif
+#include <sys/mount.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include "same54-xplained-pro.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PROCFS_MOUNTPOINT "/proc"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
-#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H */
+int sam_bringup(void)
+{
+ int ret = OK;
+
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = mount(NULL, PROCFS_MOUNTPOINT, "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslot(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n",
+ PROCFS_MOUNTPOINT, ret);
+ }
+#endif
+ UNUSED(ret);
+ return OK;
+}
diff --git a/arch/arm/src/samd5e5/hardware/sam_memorymap.h b/boards/arm/samd5e5/same54-xplained-pro/src/sam_phyinit.c
similarity index 63%
copy from arch/arm/src/samd5e5/hardware/sam_memorymap.h
copy to boards/arm/samd5e5/same54-xplained-pro/src/sam_phyinit.c
index ef08130..cd42075 100644
--- a/arch/arm/src/samd5e5/hardware/sam_memorymap.h
+++ b/boards/arm/samd5e5/same54-xplained-pro/src/sam_phyinit.c
@@ -1,8 +1,9 @@
-/************************************************************************************
- * arch/arm/src/samd5e5/hardware/sam_memorymap.h
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/src/sam_phyinit.c
*
- * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
+ * Darcy Gong <da...@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -31,22 +32,38 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
-# include "hardware/samd5e5_memorymap.h"
-#else
-# error "Unsupported SAMD5/E5 family"
-#endif
+#include "sam_port.h"
+#include "sam_ethernet.h"
+
+#include "same54-xplained-pro.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
-#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H */
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#if defined(CONFIG_ETH0_PHY_KSZ8081) && defined(CONFIG_SAMD5E5_GMAC_PHYINIT)
+int sam_phy_boardinitialize(int intf)
+{
+ /* Configure the KSZ8081 PHY reset pin and take it out of reset */
+
+ sam_portconfig(PORT_PHY_RESET);
+ return 0;
+}
+#endif
diff --git a/boards/arm/samd5e5/same54-xplained-pro/src/sam_userleds.c b/boards/arm/samd5e5/same54-xplained-pro/src/sam_userleds.c
new file mode 100644
index 0000000..36d3c20
--- /dev/null
+++ b/boards/arm/samd5e5/same54-xplained-pro/src/sam_userleds.c
@@ -0,0 +1,229 @@
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/src/sam_userleds.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The SAME54 Xplained Pro has three LEDs, but only one is controllable by software:
+ *
+ * 1. LED0 near the edge of the board
+ *
+ * ----------------- -----------
+ * SAMD5E5 FUNCTION
+ * ----------------- -----------
+ * PC18 GPIO output
+ *
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/power/pm.h>
+
+#include "up_arch.h"
+#include "sam_port.h"
+
+#include "same54-xplained-pro.h"
+
+#include <arch/board/board.h>
+
+#ifndef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* LED Power Management */
+
+#ifdef CONFIG_PM
+static void led_pm_notify(struct pm_callback_s *cb, int domain,
+ enum pm_state_e pmstate);
+static int led_pm_prepare(struct pm_callback_s *cb, int domain,
+ enum pm_state_e pmstate);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static struct pm_callback_s g_ledscb =
+{
+ .notify = led_pm_notify,
+ .prepare = led_pm_prepare,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: led_pm_notify
+ *
+ * Description:
+ * Notify the driver of new power state. This callback is called after
+ * all drivers have had the opportunity to prepare for the new power state.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static void led_pm_notify(struct pm_callback_s *cb, int domain,
+ enum pm_state_e pmstate)
+{
+ switch (pmstate)
+ {
+ case(PM_NORMAL):
+ {
+ /* Restore normal LEDs operation */
+ }
+ break;
+
+ case(PM_IDLE):
+ {
+ /* Entering IDLE mode - Turn leds off */
+ }
+ break;
+
+ case(PM_STANDBY):
+ {
+ /* Entering STANDBY mode - Logic for PM_STANDBY goes here */
+ }
+ break;
+
+ case(PM_SLEEP):
+ {
+ /* Entering SLEEP mode - Logic for PM_SLEEP goes here */
+ }
+ break;
+
+ default:
+ {
+ /* Should not get here */
+ }
+ break;
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: led_pm_prepare
+ *
+ * Description:
+ * Request the driver to prepare for a new power state. This is a warning
+ * that the system is about to enter into a new power state. The driver
+ * should begin whatever operations that may be required to enter power
+ * state. The driver may abort the state change mode by returning a
+ * non-zero value from the callback function.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static int led_pm_prepare(struct pm_callback_s *cb, int domain,
+ enum pm_state_e pmstate)
+{
+ /* No preparation to change power modes is required by the LEDs driver.
+ * We always accept the state change by returning OK.
+ */
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+void board_userled_initialize(void)
+{
+ (void)sam_portconfig(PORT_STATUS_LED);
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+ if (led == BOARD_STATUS_LED)
+ {
+ sam_portwrite(PORT_STATUS_LED, !ledon);
+ }
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint8_t ledset)
+{
+ board_userled(BOARD_STATUS_LED, (ledset & BOARD_STATUS_LED_BIT) != 0);
+}
+
+/****************************************************************************
+ * Name: sam_led_pminitialize
+ *
+ * Description:
+ * Register LED power management features.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+void sam_led_pminitialize(void)
+{
+ /* Register to receive power management callbacks */
+
+ int ret = pm_register(&g_ledscb);
+ if (ret != OK)
+ {
+ board_autoled_on(LED_ASSERTION);
+ }
+}
+#endif /* CONFIG_PM */
+
+#endif /* !CONFIG_ARCH_LEDS */
diff --git a/arch/arm/include/samd5e5/irq.h b/boards/arm/samd5e5/same54-xplained-pro/src/same54-xplained-pro.h
similarity index 52%
copy from arch/arm/include/samd5e5/irq.h
copy to boards/arm/samd5e5/same54-xplained-pro/src/same54-xplained-pro.h
index 7807757..e467c66 100644
--- a/arch/arm/include/samd5e5/irq.h
+++ b/boards/arm/samd5e5/same54-xplained-pro/src/same54-xplained-pro.h
@@ -1,5 +1,5 @@
-/****************************************************************************************
- * arch/arm/include/samd5e5/irq.h
+/****************************************************************************
+ * boards/arm/samd5e5/same54-xplained-pro/src/same54-xplained-pro.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,83 +31,98 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ****************************************************************************************/
+ ****************************************************************************/
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
- */
-
-#ifndef __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H
-#define __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H
+#ifndef __BOARDS_ARM_SAMD5E5_SAME54_XPLAINED_PRO_SRC_SAME54_XPLAINED_PRO_H
+#define __BOARDS_ARM_SAMD5E5_SAME54_XPLAINED_PRO_SRC_SAME54_XPLAINED_PRO_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-#include <arch/samd5e5/chip.h>
-/****************************************************************************************
+#include <stdint.h>
+
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
-/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
- * bits in the NVIC. This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
+/* Metro-M4 GPIOs ***********************************************************/
+
+/* LEDs
+ *
+ * The SAME54 Xplained Pro has three LEDs, but only one is controllable by software:
+ *
+ * 1. LED0 near the edge of the board
+ *
+ *
+ * ----------------- -----------
+ * SAMD5E5 FUNCTION
+ * ----------------- -----------
+ * PC18 GPIO output
+ *
*/
-/* Common Processor Exceptions (vectors 0-15) */
-
-#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
- /* Vector 0: Reset stack pointer value */
- /* Vector 1: Reset (not handler as an IRQ) */
-#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
-#define SAM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
-#define SAM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
-#define SAM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
-#define SAM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
-#define SAM_IRQ_SVCALL (11) /* Vector 11: SVC call */
-#define SAM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
- /* Vector 13: Reserved */
-#define SAM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
-#define SAM_IRQ_SYSTICK (15) /* Vector 15: System tick */
-
-/* Chip-Specific External interrupts */
-
-#define SAM_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
-
-#if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
-# include <arch/samd5e5/samd5e5_irq.h>
-#else
-# error "Unsupported SAMD5/E5 family"
-#endif
+#define PORT_LED0 (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \
+ PORTC | PORT_PIN18)
+/* Ethernet *****************************************************************/
-/****************************************************************************************
+/* PHY pins:
+ *
+ * -------- ----------------- -----------
+ * PHY SAMD5E5 FUNCTION
+ * -------- ----------------- -----------
+ * Reset PD12 GPIO output
+ * IRQ PC21 GPIO input
+ */
+
+#define PORT_PHY_RESET (PORT_OUTPUT | PORT_PULL_NONE | PORT_OUTPUT_SET | \
+ PORTD | PORT_PIN12)
+
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/****************************************************************************************
- * Public Data
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
+/****************************************************************************
+ * Name: sam_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
-/****************************************************************************************
- * Public Function Prototypes
- ****************************************************************************************/
+int sam_bringup(void);
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
+/****************************************************************************
+ * Name: sam_led_pminitialize
+ *
+ * Description:
+ * Register LED power management features.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+void sam_led_pminitialize(void);
#endif
-#endif /* __ARCH_ARM_INCLUDE_SAMD5E5_IRQ_H */
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_ARM_SAMD5E5_SAME54_XPLAINED_PRO_SRC_SAME54_XPLAINED_PRO_H */
[incubator-nuttx] 12/13: Documentation/NuttXCCodingStandard.html:
Remove requirement to decorate ignored returned values with (void). (#31)
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 312596049c8d075c2ee633f00261444a19ba3458
Author: Gregory Nutt <sp...@gmail.com>
AuthorDate: Fri Jan 3 09:55:10 2020 -0300
Documentation/NuttXCCodingStandard.html: Remove requirement to decorate ignored returned values with (void). (#31)
Co-authored-by: Gregory Nutt <gn...@nuttx.org>
---
Documentation/NuttXCCodingStandard.html | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/Documentation/NuttXCCodingStandard.html b/Documentation/NuttXCCodingStandard.html
index 2b187b5..74522f2 100644
--- a/Documentation/NuttXCCodingStandard.html
+++ b/Documentation/NuttXCCodingStandard.html
@@ -87,7 +87,7 @@
<h1><big><font color="#3c34ec">
<i>NuttX C Coding Standard</i>
</font></big></h1>
- <p>Last Updated: July 6, 2019</p>
+ <p>Last Updated: January 2, 2020</p>
</td>
</tr>
</table>
@@ -2182,9 +2182,8 @@ ptr = (FAR struct somestruct_s *)value;
<b>Checking Return Values</b>.
Callers of internal OS functions should always check return values for an error.
At a minimum, a debug statement should indicate that an error has occurred.
- The calling logic intentionally ignores the returned value, then the function return value should be explicitly cast to <code>(void)</code> to indicate that the return value is intentionally ignored.
- An exception of for standard functions for which people have historically ignored the returned values, such as <code>printf()</code> or <code>close</code>.
- All calls to <code>malloc</code> or <code>realloc</code> must be checked for failures to allocate memory.
+ Ignored return values are always suspicious.
+ All calls to <code>malloc</code> or <code>realloc</code>, in particular, must be checked for failures to allocate memory to avoid use of NULL pointers.
</p>
<table width ="100%">
[incubator-nuttx] 09/13: net/icmp/icmp_netpoll.c: Fix return of
uninitialized 'ret' when no error occurs. That is,
on what should be a successful return from this function,
an uninitialized value was returned, which may indicate an undeserved error.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit ff4ebe2ff9c02d940b7c414284a81d1c088de979
Author: Nathan Hartman <ha...@gmail.com>
AuthorDate: Thu Jan 2 14:40:08 2020 -0600
net/icmp/icmp_netpoll.c: Fix return of uninitialized 'ret' when no error occurs. That is, on what should be a successful return from this function, an uninitialized value was returned, which may indicate an undeserved error.
---
net/icmp/icmp_netpoll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/icmp/icmp_netpoll.c b/net/icmp/icmp_netpoll.c
index 2981891..9ed239f 100644
--- a/net/icmp/icmp_netpoll.c
+++ b/net/icmp/icmp_netpoll.c
@@ -159,7 +159,7 @@ int icmp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds)
FAR struct icmp_conn_s *conn = psock->s_conn;
FAR struct icmp_poll_s *info;
FAR struct devif_callback_s *cb;
- int ret;
+ int ret = OK;
DEBUGASSERT(conn != NULL && fds != NULL);
[incubator-nuttx] 13/13: drivers/sensors/lsm6dsl.c: fix various
compiler warnings
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a1e27bfbc8ca578fb96b959ff045d4230d4e0f88
Author: raiden00pl <ra...@gmail.com>
AuthorDate: Fri Jan 3 13:54:59 2020 +0100
drivers/sensors/lsm6dsl.c: fix various compiler warnings
---
drivers/sensors/lsm6dsl.c | 161 ++++++++++++++++++++++++++--------------------
1 file changed, 92 insertions(+), 69 deletions(-)
diff --git a/drivers/sensors/lsm6dsl.c b/drivers/sensors/lsm6dsl.c
index 677c051..b09f8bc5 100644
--- a/drivers/sensors/lsm6dsl.c
+++ b/drivers/sensors/lsm6dsl.c
@@ -416,8 +416,6 @@ static bool lsm6dsl_isbitset(int8_t b, int8_t m)
static int lsm6dsl_sensor_start(FAR struct lsm6dsl_dev_s *priv)
{
- uint8_t value;
-
/* Enable the accelerometer */
/* Reset values */
@@ -519,13 +517,6 @@ static int lsm6dsl_selftest(FAR struct lsm6dsl_dev_s *priv, uint32_t mode)
int16_t OUTY_ST[samples];
int16_t OUTZ_ST[samples];
- int16_t AVR_OUTX_NOST[samples];
- int16_t AVR_OUTY_NOST[samples];
- int16_t AVR_OUTZ_NOST[samples];
- int16_t AVR_OUTX_ST[samples];
- int16_t AVR_OUTY_ST[samples];
- int16_t AVR_OUTZ_ST[samples];
-
int16_t avr_x = 0;
int16_t avr_y = 0;
int16_t avr_z = 0;
@@ -547,11 +538,6 @@ static int lsm6dsl_selftest(FAR struct lsm6dsl_dev_s *priv, uint32_t mode)
int16_t max_yst = 0;
int16_t max_zst = 0;
- int16_t ltemp = 0;
- int16_t htemp = 0;
- int16_t tempi = 0;
- int16_t temp = 0;
-
int16_t raw_x = 0;
int16_t raw_y = 0;
int16_t raw_z = 0;
@@ -626,14 +612,26 @@ static int lsm6dsl_selftest(FAR struct lsm6dsl_dev_s *priv, uint32_t mode)
/* Read OUT registers Gyro is starting at 22h and Accelero at 28h */
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_L_G + registershift, &lox);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_H_G + registershift, &hix);
-
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_L_G + registershift, &loy);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_H_G + registershift, &hiy);
-
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_L_G + registershift, &loz);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_H_G + registershift, &hiz);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTX_L_G + registershift,
+ (FAR uint8_t *)&lox);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTX_H_G + registershift,
+ (FAR uint8_t *)&hix);
+
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTY_L_G + registershift,
+ (FAR uint8_t *)&loy);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTY_H_G + registershift,
+ (FAR uint8_t *)&hiy);
+
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTZ_L_G + registershift,
+ (FAR uint8_t *)&loz);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTZ_H_G + registershift,
+ (FAR uint8_t *)&hiz);
/* check XLDA 5 times */
@@ -653,16 +651,28 @@ static int lsm6dsl_selftest(FAR struct lsm6dsl_dev_s *priv, uint32_t mode)
* http://ozzmaker.com/accelerometer-to-g/
*/
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_L_G + registershift, &lox);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_H_G + registershift, &hix);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTX_L_G + registershift,
+ (FAR uint8_t *)&lox);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTX_H_G + registershift,
+ (FAR uint8_t *)&hix);
raw_x = (int16_t) (((uint16_t) hix << 8U) | (uint16_t) lox);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_L_G + registershift, &loy);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_H_G + registershift, &hiy);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTY_L_G + registershift,
+ (FAR uint8_t *)&loy);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTY_H_G + registershift,
+ (FAR uint8_t *)&hiy);
raw_y = (int16_t) (((uint16_t) hiy << 8U) | (uint16_t) loy);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_L_G + registershift, &loz);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_H_G + registershift, &hiz);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTZ_L_G + registershift,
+ (FAR uint8_t *)&loz);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTZ_H_G + registershift,
+ (FAR uint8_t *)&hiz);
raw_z = (int16_t) (((uint16_t) hiz << 8U) | (uint16_t) loz);
/* Selftest only uses raw values */
@@ -704,14 +714,26 @@ static int lsm6dsl_selftest(FAR struct lsm6dsl_dev_s *priv, uint32_t mode)
/* Now do all the ST values */
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_L_G + registershift, &loxst);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_H_G + registershift, &hixst);
-
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_L_G + registershift, &loyst);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_H_G + registershift, &hiyst);
-
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_L_G + registershift, &lozst);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_H_G + registershift, &hizst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTX_L_G + registershift,
+ (FAR uint8_t *)&loxst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTX_H_G + registershift,
+ (FAR uint8_t *)&hixst);
+
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTY_L_G + registershift,
+ (FAR uint8_t *)&loyst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTY_H_G + registershift,
+ (FAR uint8_t *)&hiyst);
+
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTZ_L_G + registershift,
+ (FAR uint8_t *)&lozst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTZ_H_G + registershift,
+ (FAR uint8_t *)&hizst);
for (i2 = 0; i2 < samples; i2++)
{
@@ -727,16 +749,28 @@ static int lsm6dsl_selftest(FAR struct lsm6dsl_dev_s *priv, uint32_t mode)
nxsig_usleep(100000); /* 100ms */
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_L_G + registershift, &loxst);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_H_G + registershift, &hixst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTX_L_G + registershift,
+ (FAR uint8_t *)&loxst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTX_H_G + registershift,
+ (FAR uint8_t *)&hixst);
raw_xst = (int16_t) (((uint16_t) hixst << 8U) | (uint16_t) loxst);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_L_G + registershift, &loyst);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_H_G + registershift, &hiyst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTY_L_G + registershift,
+ (FAR uint8_t *)&loyst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTY_H_G + registershift,
+ (FAR uint8_t *)&hiyst);
raw_yst = (int16_t) (((uint16_t) hiyst << 8U) | (uint16_t) loyst);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_L_G + registershift, &lozst);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_H_G + registershift, &hizst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTZ_L_G + registershift,
+ (FAR uint8_t *)&lozst);
+ lsm6dsl_readreg8(priv,
+ LSM6DSL_OUTZ_H_G + registershift,
+ (FAR uint8_t *)&hizst);
raw_zst = (int16_t) (((uint16_t) hizst << 8U) | (uint16_t) lozst);
/* Selftest only uses raw values */
@@ -897,10 +931,8 @@ static int lsm6dsl_selftest(FAR struct lsm6dsl_dev_s *priv, uint32_t mode)
static int lsm6dsl_sensor_read(FAR struct lsm6dsl_dev_s *priv,
FAR struct lsm6dsl_sensor_data_s *sensor_data)
{
- int16_t lo = 0;
int16_t lox = 0;
int16_t loxg = 0;
- int16_t hi = 0;
int16_t hix = 0;
int16_t hixg = 0;
int16_t loy = 0;
@@ -915,21 +947,11 @@ static int lsm6dsl_sensor_read(FAR struct lsm6dsl_dev_s *priv,
int16_t templ = 0;
int16_t temph = 0;
- uint8_t status1 = 0;
- uint8_t status2 = 0;
- uint8_t status3 = 0;
- uint8_t status4 = 0;
- uint8_t value = 0;
-
uint8_t tstamp0 = 0;
uint8_t tstamp1 = 0;
uint8_t tstamp2 = 0;
- uint8_t tstamp3 = 0;
uint32_t ts = 0;
- int16_t x_val = 0;
- int16_t y_val = 0;
- int16_t z_val = 0;
int16_t tempi = 0;
int16_t temp_val = 0;
@@ -943,25 +965,25 @@ static int lsm6dsl_sensor_read(FAR struct lsm6dsl_dev_s *priv,
/* Accelerometer */
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_L_XL, &lox);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_H_XL, &hix);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTX_L_XL, (FAR uint8_t *)&lox);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTX_H_XL, (FAR uint8_t *)&hix);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_L_XL, &loy);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_H_XL, &hiy);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTY_L_XL, (FAR uint8_t *)&loy);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTY_H_XL, (FAR uint8_t *)&hiy);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_L_XL, &loz);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_H_XL, &hiz);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_L_XL, (FAR uint8_t *)&loz);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_H_XL, (FAR uint8_t *)&hiz);
/* Gyro */
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_L_G, &loxg);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTX_H_G, &hixg);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTX_L_G, (FAR uint8_t *)&loxg);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTX_H_G, (FAR uint8_t *)&hixg);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_L_G, &loyg);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTY_H_G, &hiyg);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTY_L_G, (FAR uint8_t *)&loyg);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTY_H_G, (FAR uint8_t *)&hiyg);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_L_G, &lozg);
- lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_H_G, &hizg);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_L_G, (FAR uint8_t *)&lozg);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUTZ_H_G, (FAR uint8_t *)&hizg);
/* Timestamp */
@@ -973,8 +995,8 @@ static int lsm6dsl_sensor_read(FAR struct lsm6dsl_dev_s *priv,
/* Temperature */
- lsm6dsl_readreg8(priv, LSM6DSL_OUT_TEMP_L, &templ);
- lsm6dsl_readreg8(priv, LSM6DSL_OUT_TEMP_H, &temph);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUT_TEMP_L, (FAR uint8_t *)&templ);
+ lsm6dsl_readreg8(priv, LSM6DSL_OUT_TEMP_H, (FAR uint8_t *)&temph);
xf_val = (int16_t) ((hix << 8) | lox);
yf_val = (int16_t) ((hiy << 8) | loy);
@@ -1211,7 +1233,8 @@ static int lsm6dsl_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
break;
case SNIOC_LSM6DSLSENSORREAD:
- ret = priv->ops->sensor_read(priv, (FAR struct lsm6dsl_sensor_data_s *) arg);
+ ret = priv->ops->sensor_read(priv,
+ (FAR struct lsm6dsl_sensor_data_s *) arg);
break;
case SNIOC_START_SELFTEST:
[incubator-nuttx] 07/13: arch/arm/src/stm32/stm32_fmc.c: fix
compilation error (#27)
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4feda07b11bd19fed0ec39a9600873802118ab8e
Author: Mateusz Szafoni <ra...@users.noreply.github.com>
AuthorDate: Thu Jan 2 20:48:03 2020 +0100
arch/arm/src/stm32/stm32_fmc.c: fix compilation error (#27)
arch/arm/src/stm32/stm32_fmc.c: Missing semicolons caused compilation errors.
---
arch/arm/src/stm32/stm32_fmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/stm32/stm32_fmc.c
index d13f3de..a81a3a8 100644
--- a/arch/arm/src/stm32/stm32_fmc.c
+++ b/arch/arm/src/stm32/stm32_fmc.c
@@ -160,7 +160,7 @@ void stm32_fmc_sdram_set_refresh_rate(int count)
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
{
- uint32_t val
+ uint32_t val;
uint32_t sdtr;
DEBUGASSERT((bank == 1) || (bank == 2));
@@ -183,7 +183,7 @@ void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
{
- uint32_t val
+ uint32_t val;
uint32_t sdcr;
DEBUGASSERT((bank == 1) || (bank == 2));
[incubator-nuttx] 06/13: Squashed commit of the following:
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit ad806a550168ab6bec7ae64d746c8fed4d946d45
Author: Gregory Nutt <sp...@gmail.com>
AuthorDate: Thu Jan 2 16:40:06 2020 -0300
Squashed commit of the following:
Author: patacongo <sp...@yahoo.com>
arch/arm/src/imxrt/imxrt_enet.c: Fix some warnings found in build testing.
Also fix coding standard problems reported by nxstyle. (#26)
Co-authored-by: Gregory Nutt <gn...@nuttx.org>
---
arch/arm/src/imxrt/imxrt_enet.c | 55 ++++++++++++++++++++---------------------
1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c
index c2c3a0f..7296396 100644
--- a/arch/arm/src/imxrt/imxrt_enet.c
+++ b/arch/arm/src/imxrt/imxrt_enet.c
@@ -538,17 +538,17 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
buf = (uint8_t *)imxrt_swap32((uint32_t)priv->dev.d_buf);
if (priv->rxdesc[priv->rxtail].data == buf)
{
- struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail];
+ struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail];
- /* Data was written into the RX buffer, so swap the TX and RX buffers */
+ /* Data was written into the RX buffer, so swap the TX and RX buffers */
- DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0);
- rxdesc->data = txdesc->data;
- txdesc->data = buf;
+ DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0);
+ rxdesc->data = txdesc->data;
+ txdesc->data = buf;
}
else
{
- DEBUGASSERT(txdesc->data == buf);
+ DEBUGASSERT(txdesc->data == buf);
}
/* Make the following operations atomic */
@@ -637,8 +637,8 @@ static int imxrt_txpoll(struct net_driver_s *dev)
/* Send the packet */
imxrt_transmit(priv);
- priv->dev.d_buf =
- (uint8_t *)imxrt_swap32((uint32_t)priv->txdesc[priv->txhead].data);
+ priv->dev.d_buf = (uint8_t *)
+ imxrt_swap32((uint32_t)priv->txdesc[priv->txhead].data);
/* Check if there is room in the device to hold another packet. If
* not, return a non-zero value to terminate the poll.
@@ -648,7 +648,7 @@ static int imxrt_txpoll(struct net_driver_s *dev)
{
return -EBUSY;
}
- }
+ }
}
/* If zero is returned, the polling will continue until all connections have
@@ -685,7 +685,7 @@ static inline void imxrt_dispatch(FAR struct imxrt_driver_s *priv)
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
- pkt_input(&priv->dev);
+ pkt_input(&priv->dev);
#endif
#ifdef CONFIG_NET_IPv4
@@ -863,8 +863,8 @@ static void imxrt_receive(FAR struct imxrt_driver_s *priv)
* queue is not full.
*/
- priv->dev.d_buf =
- (uint8_t *)imxrt_swap32((uint32_t)priv->txdesc[priv->txhead].data);
+ priv->dev.d_buf = (uint8_t *)
+ imxrt_swap32((uint32_t)priv->txdesc[priv->txhead].data);
rxdesc->status1 |= RXDESC_E;
/* Update the index to the next descriptor */
@@ -1551,6 +1551,7 @@ static int imxrt_txavail(struct net_driver_s *dev)
return OK;
}
+
/****************************************************************************
* Function: imxrt_calcethcrc
*
@@ -1598,7 +1599,7 @@ static uint32_t imxrt_calcethcrc(const uint8_t *data, size_t length)
}
return crc;
- }
+}
#endif
/****************************************************************************
@@ -1654,7 +1655,6 @@ static uint32_t imxrt_enet_hash_index(const uint8_t *mac)
#ifdef CONFIG_NET_MCASTGROUP
static int imxrt_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
{
- uint32_t crc;
uint32_t hashindex;
uint32_t temp;
uint32_t registeraddress;
@@ -1702,7 +1702,6 @@ static int imxrt_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
#ifdef CONFIG_NET_MCASTGROUP
static int imxrt_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
{
- uint32_t crc;
uint32_t hashindex;
uint32_t temp;
uint32_t registeraddress;
@@ -2062,7 +2061,8 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
if (retries >= 3)
{
- nerr("ERROR: Failed to read %s PHYID1 at address %d\n", BOARD_PHY_NAME, phyaddr);
+ nerr("ERROR: Failed to read %s PHYID1 at address %d\n",
+ BOARD_PHY_NAME, phyaddr);
return -ENOENT;
}
@@ -2145,16 +2145,15 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
(phydata | (1 << 4)));
#elif defined (CONFIG_ETH0_PHY_LAN8720)
+ /* Make sure that PHY comes up in correct mode when it's reset */
- /* Make sure that PHY comes up in correct mode when it's reset */
-
- imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES,
- MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL |
- MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR));
+ imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES,
+ MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL |
+ MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR));
- /* ...and reset PHY */
+ /* ...and reset PHY */
- imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
+ imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
#endif
/* Start auto negotiation */
@@ -2228,17 +2227,17 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
{
if (renogphy == false)
{
- /* Give things one more chance with renegociation turned on */
+ /* Give things one more chance with renegotiation turned on */
return imxrt_initphy(priv, true);
}
else
{
- /* That didn't end well, just give up */
+ /* That didn't end well, just give up */
- nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n",
- BOARD_PHY_NAME, BOARD_PHY_STATUS, ret);
- return ret;
+ nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n",
+ BOARD_PHY_NAME, BOARD_PHY_STATUS, ret);
+ return ret;
}
}
[incubator-nuttx] 10/13: Author: Gregory Nutt
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit b278abacadfc2817cdace8817aab438d33ae6b34
Author: jjlange <jl...@2g-eng.com>
AuthorDate: Thu Jan 2 15:56:27 2020 -0600
Author: Gregory Nutt <gn...@nuttx.org>
Run all .c and .h files in last PR through tools/nxstyle and fix all complaints.
Author: macman88 <jj...@gmail.com>
LPC17xx serial updates (#29)
* Save CONFIG_ARCH_BOARD_CUSTOM when running 'make savedefconfig'
* Don't compile up_earlyserialinit if USE_EARLYSERIALINIT is not defined
* Added support for RS485 direction control on LPC17xx UART1
* First pass at fractional baud rate divider on LPC17xx/40xx
* Added support for fractional divider to console UART
---
arch/arm/src/lpc17xx_40xx/Kconfig | 30 ++++
arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c | 44 +++---
arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c | 224 ++++++++++++++++++++++++---
arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h | 4 +-
arch/arm/src/lpc43xx/lpc43_uart.c | 15 +-
5 files changed, 266 insertions(+), 51 deletions(-)
diff --git a/arch/arm/src/lpc17xx_40xx/Kconfig b/arch/arm/src/lpc17xx_40xx/Kconfig
index ec9a595..c6de373 100644
--- a/arch/arm/src/lpc17xx_40xx/Kconfig
+++ b/arch/arm/src/lpc17xx_40xx/Kconfig
@@ -561,6 +561,36 @@ config LPC17_40_UART1_RINGINDICATOR
---help---
Enable UART1 ring indicator
+config LPC17_40_UART1_RS485
+ bool "RS-485 on UART1"
+ default n
+ depends on LPC17_40_UART1
+ ---help---
+ Enable RS-485 interface on UART1. Your board config will have to
+ provide GPIO_UART1_RS485_DIR pin definition.
+
+config LPC17_40_RS485_DIR_POLARITY
+ int "UART1 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on LPC17_40_UART1_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART1. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config LPC17_40_UART1_RS485_DIR_DTR
+ bool "UART1 RS-485 DIR pin use DTR"
+ default n
+ depends on LPC17_40_UART1_RS485
+ ---help---
+ Selects between RTS and DTR pins for RS485 DIR. This must correspond to
+ the GPIO_USART1_RS485_DIR pin specified in your board config. The DTR pin
+ will be used if selected, the RTS pin will be used otherwise.
+
+config LPC17_40_UART_USE_FRACTIONAL_DIVIDER
+ bool "Use fractional divider for UART baud rate"
+ default n
+
endmenu
menu "ADC driver options"
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c
index 166050b..f055bdb 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c
*
- * Copyright (C) 2010-2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2010-2013, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -154,9 +154,6 @@
* And for the LPC178x/40xx, the PCLK is determined by the global divisor setting in
* the PLKSEL register.
*
- * Ignoring the fractional divider for now. (If you want to extend this driver
- * to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses
- * the same peripheral and that logic could easily leveraged here).
*/
#ifdef LPC178x_40xx
@@ -165,6 +162,10 @@
# define CONSOLE_NUMERATOR BOARD_PCLK_FREQUENCY
#else
+# ifdef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
+# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK
+# define CONSOLE_NUMERATOR (LPC17_40_CCLK)
+# else
/* Calculate and optimal PCLKSEL0/1 divisor.
* First, check divisor == 1. This works if the upper limit is met:
*
@@ -181,9 +182,9 @@
* BAUD <= CCLK / 16 / MinDL
*/
-# if CONSOLE_BAUD < (LPC17_40_CCLK / 16 / UART_MINDL)
-# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK
-# define CONSOLE_NUMERATOR (LPC17_40_CCLK)
+# if CONSOLE_BAUD < (LPC17_40_CCLK / 16 / UART_MINDL)
+# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK
+# define CONSOLE_NUMERATOR (LPC17_40_CCLK)
/* Check divisor == 2. This works if:
*
@@ -196,9 +197,9 @@
* BAUD <= CCLK / 8 / MinDL
*/
-# elif CONSOLE_BAUD < (LPC17_40_CCLK / 8 / UART_MINDL)
-# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK2
-# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 2)
+# elif CONSOLE_BAUD < (LPC17_40_CCLK / 8 / UART_MINDL)
+# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK2
+# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 2)
/* Check divisor == 4. This works if:
*
@@ -211,9 +212,9 @@
* BAUD <= CCLK / 4 / MinDL
*/
-# elif CONSOLE_BAUD < (LPC17_40_CCLK / 4 / UART_MINDL)
-# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK4
-# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 4)
+# elif CONSOLE_BAUD < (LPC17_40_CCLK / 4 / UART_MINDL)
+# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK4
+# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 4)
/* Check divisor == 8. This works if:
*
@@ -226,9 +227,10 @@
* BAUD <= CCLK / 2 / MinDL
*/
-# else /* if CONSOLE_BAUD < (LPC17_40_CCLK / 2 / UART_MINDL) */
-# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK8
-# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 8)
+# else /* if CONSOLE_BAUD < (LPC17_40_CCLK / 2 / UART_MINDL) */
+# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK8
+# define CONSOLE_NUMERATOR (LPC17_40_CCLK / 8)
+# endif
# endif
#endif /* LPC178x_40xx */
@@ -273,11 +275,11 @@ void up_lowputc(char ch)
#if defined HAVE_UART && defined HAVE_CONSOLE
/* Wait for the transmitter to be available */
- while ((getreg32(CONSOLE_BASE+LPC17_40_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
+ while ((getreg32(CONSOLE_BASE + LPC17_40_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
/* Send the character */
- putreg32((uint32_t)ch, CONSOLE_BASE+LPC17_40_UART_THR_OFFSET);
+ putreg32((uint32_t)ch, CONSOLE_BASE + LPC17_40_UART_THR_OFFSET);
#endif
}
@@ -396,6 +398,7 @@ void lpc17_40_lowsetup(void)
putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8,
CONSOLE_BASE + LPC17_40_UART_FCR_OFFSET);
+#ifndef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
/* Disable FDR (fractional divider),
* ignored by baudrate calculation => has to be disabled
*/
@@ -403,15 +406,20 @@ void lpc17_40_lowsetup(void)
putreg32((1 << UART_FDR_MULVAL_SHIFT) + (0 << UART_FDR_DIVADDVAL_SHIFT),
CONSOLE_BASE + LPC17_40_UART_FDR_OFFSET);
+#endif
/* Set up the LCR and set DLAB=1 */
putreg32(CONSOLE_LCR_VALUE | UART_LCR_DLAB,
CONSOLE_BASE + LPC17_40_UART_LCR_OFFSET);
+#ifdef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
+ up_setbaud(CONSOLE_BASE, CONSOLE_NUMERATOR, CONSOLE_BAUD);
+#else
/* Set the BAUD divisor */
putreg32(CONSOLE_DL >> 8, CONSOLE_BASE + LPC17_40_UART_DLM_OFFSET);
putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE + LPC17_40_UART_DLL_OFFSET);
+#endif
/* Clear DLAB */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c
index c0b6e0a..26c1689 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc17xx_40xx/lpc17_40_serial.c
*
- * Copyright (C) 2010-2013, 2017-2018 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2010-2013, 2017-2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -547,20 +547,156 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
up_serialout(priv, LPC17_40_UART_LCR_OFFSET, lcr);
}
+#ifdef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
+/****************************************************************************
+ * Name: lpc17_40_setbaud
+ *
+ * Description:
+ * Configure the UART divisors to accomplish the desired BAUD given the
+ * UART base frequency.
+ *
+ * This computationally intensive algorithm is based on the same logic
+ * used in the NXP sample code.
+ *
+ ****************************************************************************/
+
+void up_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
+{
+ uint32_t lcr; /* Line control register value */
+ uint32_t dl; /* Best DLM/DLL full value */
+ uint32_t mul; /* Best FDR MULVALL value */
+ uint32_t divadd; /* Best FDR DIVADDVAL value */
+ uint32_t best; /* Error value associated with best {dl, mul, divadd} */
+ uint32_t cdl; /* Candidate DLM/DLL full value */
+ uint32_t cmul; /* Candidate FDR MULVALL value */
+ uint32_t cdivadd; /* Candidate FDR DIVADDVAL value */
+ uint32_t errval; /* Error value associated with the candidate */
+
+ /* The UART buad is given by:
+ *
+ * Fbaud = Fbase * mul / (mul + divadd) / (16 * dl)
+ * dl = Fbase * mul / (mul + divadd) / Fbaud / 16
+ * = Fbase * mul / ((mul + divadd) * Fbaud * 16)
+ * = ((Fbase * mul) >> 4) / ((mul + divadd) * Fbaud)
+ *
+ * Where the value of MULVAL and DIVADDVAL comply with:
+ *
+ * 0 < mul < 16
+ * 0 <= divadd < mul
+ */
+
+ best = UINT32_MAX;
+ divadd = 0;
+ mul = 0;
+ dl = 0;
+
+ /* Try each multiplier value in the valid range */
+
+ for (cmul = 1 ; cmul < 16; cmul++)
+ {
+ /* Try each divider value in the valid range */
+
+ for (cdivadd = 0 ; cdivadd < cmul ; cdivadd++)
+ {
+ /* Candidate:
+ * dl = ((Fbase * mul) >> 4) / ((mul + cdivadd) * Fbaud)
+ * (dl << 32) = (Fbase << 28) * cmul / ((mul + cdivadd) * Fbaud)
+ */
+
+ uint64_t dl64 = ((uint64_t)basefreq << 28) * cmul /
+ ((cmul + cdivadd) * baud);
+
+ /* The lower 32-bits of this value is the error */
+
+ errval = (uint32_t)(dl64 & 0x00000000ffffffffull);
+
+ /* The upper 32-bits is the candidate DL value */
+
+ cdl = (uint32_t)(dl64 >> 32);
+
+ /* Round up */
+
+ if (errval > (1 << 31))
+ {
+ errval = -errval;
+ cdl++;
+ }
+
+ /* Check if the resulting candidate DL value is within range */
+
+ if (cdl < 1 || cdl > 65536)
+ {
+ /* No... try a different divadd value */
+
+ continue;
+ }
+
+ /* Is this the best combination that we have seen so far? */
+
+ if (errval < best)
+ {
+ /* Yes.. then the candidate is out best guess so far */
+
+ best = errval;
+ dl = cdl;
+ divadd = cdivadd;
+ mul = cmul;
+
+ /* If the new best guess is exact (within our precision), then
+ * we are finished.
+ */
+
+ if (best == 0)
+ {
+ break;
+ }
+ }
+ }
+ }
+
+ DEBUGASSERT(dl > 0);
+
+ /* Enter DLAB=1 */
+
+ lcr = getreg32(uartbase + LPC17_40_UART_LCR_OFFSET);
+ putreg32(lcr | UART_LCR_DLAB, uartbase + LPC17_40_UART_LCR_OFFSET);
+
+ /* Save the divider values */
+
+ putreg32(dl >> 8, uartbase + LPC17_40_UART_DLM_OFFSET);
+ putreg32(dl & 0xff, uartbase + LPC17_40_UART_DLL_OFFSET);
+
+ /* Clear DLAB */
+
+ putreg32(lcr & ~UART_LCR_DLAB, uartbase + LPC17_40_UART_LCR_OFFSET);
+
+ /* Then save the fractional divider values */
+
+ putreg32((mul << UART_FDR_MULVAL_SHIFT) | (divadd << UART_FDR_DIVADDVAL_SHIFT),
+ uartbase + LPC17_40_UART_FDR_OFFSET);
+}
+# ifdef LPC176x
+static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud)
+{
+ /* If we're using the fractional divider, assume that the full PCLK speed
+ * will be acceptable.
+ */
+
+ return SYSCON_PCLKSEL_CCLK;
+}
+# endif
+#else
/************************************************************************************
* Name: lpc17_40_uartcclkdiv
*
* Description:
- * Select a CCLK divider to produce the UART PCLK. The stratey is to select the
+ * Select a CCLK divider to produce the UART PCLK. The strategy is to select the
* smallest divisor that results in an solution within range of the 16-bit
* DLM and DLL divisor:
*
* PCLK = CCLK / divisor
* BAUD = PCLK / (16 * DL)
*
- * Ignoring the fractional divider for now. (If you want to extend this driver
- * to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses
- * the same peripheral and that logic could easily leveraged here).
*
* For the LPC176x the PCLK is determined by the UART-specific divisor in
* PCLKSEL0 or PCLKSEL1:
@@ -576,7 +712,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
*
************************************************************************************/
-#ifdef LPC176x
+# ifdef LPC176x
static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud)
{
/* Ignoring the fractional divider, the BAUD is given by:
@@ -662,8 +798,8 @@ static inline uint32_t lpc17_40_uartcclkdiv(uint32_t baud)
return SYSCON_PCLKSEL_CCLK8;
}
}
-#endif /* LPC176x */
-
+# endif /* LPC176x */
+#endif /* CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER */
/************************************************************************************
* Name: lpc17_40_uart0config, uart1config, uart2config, and uart3config
*
@@ -734,7 +870,21 @@ static inline void lpc17_40_uart1config(void)
putreg32(regval, LPC17_40_SYSCON_PCLKSEL0);
#endif
- /* Step 3: Configure I/O pins */
+ /* Step 3: Configure RS-485 control register */
+
+#ifdef CONFIG_LPC17_40_UART1_RS485
+ regval = getreg32(LPC17_40_UART1_RS485CTRL);
+ regval |= UART_RS485CTRL_DCTRL;
+#if (CONFIG_LPC17_40_RS485_DIR_POLARITY == 1)
+ regval |= UART_RS485CTRL_OINV;
+#endif
+#ifdef CONFIG_LPC17_40_UART1_RS485_DIR_DTR
+ regval |= UART_RS485CTRL_SEL;
+#endif
+ putreg32(regval, LPC17_40_UART1_RS485CTRL);
+#endif
+
+ /* Step 4: Configure I/O pins */
lpc17_40_configgpio(GPIO_UART1_TXD);
lpc17_40_configgpio(GPIO_UART1_RXD);
@@ -748,6 +898,11 @@ static inline void lpc17_40_uart1config(void)
lpc17_40_configgpio(GPIO_UART1_RI);
#endif
#endif
+
+#ifdef CONFIG_LPC17_40_UART1_RS485
+ lpc17_40_configgpio(GPIO_UART1_RS485_DIR);
+#endif
+
leave_critical_section(flags);
};
#endif
@@ -821,13 +976,10 @@ static inline void lpc17_40_uart3config(void)
* BAUD = PCLK / (16 * DL), or
* DL = PCLK / BAUD / 16
*
- * Ignoring the fractional divider for now. (If you want to extend this driver
- * to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses
- * the same peripheral and that logic could easily leveraged here).
- *
************************************************************************************/
-#ifdef LPC176x
+#ifndef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
+# ifdef LPC176x
static inline uint32_t lpc17_40_uartdl(uint32_t baud, uint8_t divcode)
{
uint32_t num;
@@ -859,6 +1011,7 @@ static inline uint32_t lpc17_40_uartdl(uint32_t baud)
{
return (uint32_t)BOARD_PCLK_FREQUENCY / (baud << 4);
}
+# endif
#endif
/****************************************************************************
@@ -878,16 +1031,20 @@ static int up_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+# ifndef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
uint16_t dl;
+# endif
uint32_t lcr;
/* Clear fifos */
- up_serialout(priv, LPC17_40_UART_FCR_OFFSET, (UART_FCR_RXRST | UART_FCR_TXRST));
+ up_serialout(priv, LPC17_40_UART_FCR_OFFSET,
+ (UART_FCR_RXRST | UART_FCR_TXRST));
/* Set trigger */
- up_serialout(priv, LPC17_40_UART_FCR_OFFSET, (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8));
+ up_serialout(priv, LPC17_40_UART_FCR_OFFSET,
+ (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8));
/* Set up the IER */
@@ -920,12 +1077,14 @@ static int up_setup(struct uart_dev_s *dev)
lcr |= (UART_LCR_PE | UART_LCR_PS_EVEN);
}
+#ifndef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
/* Disable FDR (fractional divider),
* ignored by baudrate calculation => has to be disabled
*/
up_serialout(priv, LPC17_40_UART_FDR_OFFSET,
(1 << UART_FDR_MULVAL_SHIFT) + (0 << UART_FDR_DIVADDVAL_SHIFT));
+#endif
/* Enter DLAB=1 */
@@ -933,13 +1092,17 @@ static int up_setup(struct uart_dev_s *dev)
/* Set the BAUD divisor */
-#ifdef LPC176x
- dl = lpc17_40_uartdl(priv->baud, priv->cclkdiv);
+#ifdef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
+ up_setbaud(priv->uartbase, LPC17_40_CCLK / priv->cclkdiv, priv->baud);
#else
+# ifdef LPC176x
+ dl = lpc17_40_uartdl(priv->baud, priv->cclkdiv);
+# else
dl = lpc17_40_uartdl(priv->baud);
-#endif
+# endif
up_serialout(priv, LPC17_40_UART_DLM_OFFSET, dl >> 8);
up_serialout(priv, LPC17_40_UART_DLL_OFFSET, dl & 0xff);
+#endif
/* Clear DLAB */
@@ -1135,7 +1298,8 @@ static int up_interrupt(int irq, void *context, void *arg)
}
}
}
- return OK;
+
+ return OK;
}
/****************************************************************************
@@ -1212,8 +1376,10 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
case TCSETS:
{
struct termios *termiosp = (struct termios *)arg;
+# ifndef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
uint32_t lcr; /* Holds current values of line control register */
uint16_t dl; /* Divisor latch */
+# endif
if (!termiosp)
{
@@ -1234,10 +1400,14 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
* and reset the divider in the CLKSEL0/1 register.
*/
-#if 0 /* ifdef LPC176x */
+# ifdef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER
+ up_setbaud(priv->uartbase, LPC17_40_CCLK / priv->cclkdiv, priv->baud);
+# else
+# if 0 /* ifdef LPC176x */
priv->cclkdiv = lpc17_40_uartcclkdiv(priv->baud);
-#endif
+# endif
/* DLAB open latch */
+
/* REVISIT: Shouldn't we just call up_setup() to do all of the following? */
lcr = getreg32(priv->uartbase + LPC17_40_UART_LCR_OFFSET);
@@ -1245,17 +1415,18 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Set the BAUD divisor */
-#ifdef LPC176x
+# ifdef LPC176x
dl = lpc17_40_uartdl(priv->baud, priv->cclkdiv);
-#else
+# else
dl = lpc17_40_uartdl(priv->baud);
-#endif
+# endif
up_serialout(priv, LPC17_40_UART_DLM_OFFSET, dl >> 8);
up_serialout(priv, LPC17_40_UART_DLL_OFFSET, dl & 0xff);
/* Clear DLAB */
up_serialout(priv, LPC17_40_UART_LCR_OFFSET, lcr);
+# endif
}
break;
#endif
@@ -1422,6 +1593,7 @@ static bool up_txempty(struct uart_dev_s *dev)
*
****************************************************************************/
+#ifdef USE_EARLYSERIALINIT
void up_earlyserialinit(void)
{
/* Configure all UARTs (except the CONSOLE UART) and disable interrupts */
@@ -1475,6 +1647,8 @@ void up_earlyserialinit(void)
#endif
}
+#endif
+
/****************************************************************************
* Name: up_serialinit
*
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h
index 624deaa..bb7fa57 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/lpc17xx_40xx/lpc17_40_serial.h
*
- * Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2010, 2013, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -130,4 +130,6 @@
* Public Functions
************************************************************************************/
+void up_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud);
+
#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_LPC17_40_SERIAL_H */
diff --git a/arch/arm/src/lpc43xx/lpc43_uart.c b/arch/arm/src/lpc43xx/lpc43_uart.c
index 766edc9..e653772 100644
--- a/arch/arm/src/lpc43xx/lpc43_uart.c
+++ b/arch/arm/src/lpc43xx/lpc43_uart.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43xx/lpc43_uart.c
*
- * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2017, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -159,11 +159,11 @@ void up_lowputc(char ch)
#ifdef HAVE_SERIAL_CONSOLE
/* Wait for the transmitter to be available */
- while ((getreg32(CONSOLE_BASE+LPC43_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
+ while ((getreg32(CONSOLE_BASE + LPC43_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
/* Send the character */
- putreg32((uint32_t)ch, CONSOLE_BASE+LPC43_UART_THR_OFFSET);
+ putreg32((uint32_t)ch, CONSOLE_BASE + LPC43_UART_THR_OFFSET);
#endif
}
@@ -175,7 +175,9 @@ void up_lowputc(char ch)
* console. Its purpose is to get the console output available as soon
* as possible.
*
- * The USART0/2/3 and UART1 peripherals are configured using the following registers:
+ * The USART0/2/3 and UART1 peripherals are configured using the following
+ * registers:
+ *
* 1. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
* to registers DLL and DLM for setting the baud rate. Also, if needed,
* set the fractional baud rate in the fractional divider
@@ -457,7 +459,6 @@ void lpc43_usart2_setup(void)
regval |= CCU_CLK_CFG_RUN;
putreg32(regval, LPC43_CCU2_APB2_USART2_CFG);
-
/* Configure I/O pins. NOTE that multiple pin configuration options must
* be disambiguated by defining the pin configuration in the board.h
* header file.
@@ -619,7 +620,7 @@ void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
mul = 0;
dl = 0;
- /* Try each mulitplier value in the valid range */
+ /* Try each multiplier value in the valid range */
for (cmul = 1 ; cmul < 16; cmul++)
{
@@ -690,7 +691,7 @@ void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
lcr = getreg32(uartbase + LPC43_UART_LCR_OFFSET);
putreg32(lcr | UART_LCR_DLAB, uartbase + LPC43_UART_LCR_OFFSET);
- /* Save then divider values */
+ /* Save the divider values */
putreg32(dl >> 8, uartbase + LPC43_UART_DLM_OFFSET);
putreg32(dl & 0xff, uartbase + LPC43_UART_DLL_OFFSET);
[incubator-nuttx] 08/13: net/icmp/icmp_netpoll.c: Fix warning:
implicit declaration of nxsem_post(). This appeared after include of
nuttx/kmalloc.h was removed recently.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch netlink_crypto
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 5e243f53a5a223341cee5bac3e47d2d8f8f6e076
Author: Nathan Hartman <ha...@gmail.com>
AuthorDate: Thu Jan 2 14:37:14 2020 -0600
net/icmp/icmp_netpoll.c: Fix warning: implicit declaration of nxsem_post(). This appeared after include of nuttx/kmalloc.h was removed recently.
---
net/icmp/icmp_netpoll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/icmp/icmp_netpoll.c b/net/icmp/icmp_netpoll.c
index 99b299d..2981891 100644
--- a/net/icmp/icmp_netpoll.c
+++ b/net/icmp/icmp_netpoll.c
@@ -43,6 +43,7 @@
#include <poll.h>
#include <debug.h>
+#include <nuttx/semaphore.h>
#include <nuttx/net/net.h>
#include "devif/devif.h"