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Posted to commits@tvm.apache.org by tq...@apache.org on 2020/05/23 15:55:23 UTC
[incubator-tvm-site] branch asf-site updated (71a3f12 -> e039225)
This is an automated email from the ASF dual-hosted git repository.
tqchen pushed a change to branch asf-site
in repository https://gitbox.apache.org/repos/asf/incubator-tvm-site.git.
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new e039225 Docs build at Sat May 23 08:42:38 PDT 2020
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Summary of changes:
[incubator-tvm-site] 01/01: Docs build at Sat May 23 08:42:38 PDT
2020
Posted by tq...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
tqchen pushed a commit to branch asf-site
in repository https://gitbox.apache.org/repos/asf/incubator-tvm-site.git
commit e039225f725cd5e0d71fe10151486a360793e3dc
Author: tqchen <tq...@gmail.com>
AuthorDate: Mon Nov 25 21:30:46 2019 -0800
Docs build at Sat May 23 08:42:38 PDT 2020
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+ <h1>TVM: An End to End IR Stack for Deploying Deep Learning Workloads on Hardware Platforms </h1>
+ <p class="post-meta">
+ <time datetime="2017-08-17T12:00:00-07:00" itemprop="datePublished">
+ Aug 17, 2017
+ </time>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p style="text-align: center">Tianqi Chen(project lead), Thierry Moreau(hardware stack), Ziheng Jiang†(graph compilation), Haichen Shen(gpu optimization)</p>
+<p style="text-align: center">Advisors: Luis Ceze, Carlos Guestrin, Arvind Krishnamurthy</p>
+<p style="text-align: center">Paul G. Allen School of Computer Science & Engineering, University of Washington</p>
+<p style="text-align: center">DMLC open-source community</p>
+<p style="text-align: center">†Amazon Web Service</p>
+
+<p>Deep learning has become ubiquitous and indispensable. Part of this revolution has been fueled by scalable deep learning systems, such as TensorFlow, MXNet, Caffe and PyTorch. Most existing systems are optimized for a narrow range of server-class GPUs, and require significant effort be deployed on other platforms such as mobile phones, IoT devices and specialized accelerators (FPGAs, ASICs). As the number of deep learning frameworks and hardware backends increase, we propose a unifie [...]
+
+<p style="text-align: center"><img src="/images/release/gap.png" alt="image" width="512px" /></p>
+<p>We are excited to announce the launch of TVM as solution to this problem. TVM is a novel framework that can:</p>
+
+<ul>
+ <li>Represent and optimize the common deep learning computation workloads for CPUs, GPUs and other specialized hardware</li>
+ <li>Automatically transform the computation graph to minimize memory utilization, optimize data layout and fuse computation patterns</li>
+ <li>Provide an end-to-end compilation from existing front-end frameworks down to bare-metal hardware, all the way up to browser executable javascripts.</li>
+</ul>
+
+<p>With the help of TVM, we can easily run deep learning workloads on mobile phones, embedded devices and even the browser with little additional effort. TVM also provides a unified optimization framework for deep learning workloads on a multitude of hardware platforms, including specialized accelerators that rely on novel computational primitives.</p>
+
+<p style="text-align: center"><img src="/images/release/end_to_end_stack.png" alt="image" width="512px" /></p>
+
+<p>We adopt a common philosophy from the compiler community and provide two intermediate representation layers to efficiently lower high-level deep learning algorithms down to a multitude of hardware back-ends.</p>
+
+<p>In today’s release, we open-source TVM package that contains optimization primitives for x86, ARM, OpenCL, Metal, CUDA and Javascript. We are actively working on adding support for specialized hardware acceleration and Nvidia’s GEMM-optimized Volta architecture.</p>
+
+<h2 id="technical-details">Technical Details</h2>
+
+<p>The goal of TVM stack is to provide a reusable toolchain to compile high-level neural network descriptions from deep learning framework frontends down to low-level machine code for multiple hardware backends. Take Apache MXNet as a front-end example, the following code snippet demonstrates how can TVM be used to compile a high-level description of a deep learning model to an optimized executable module tailored to the target hardware.</p>
+
+<p style="text-align: center"><img src="/images/release/code_highlevel.png" alt="image" width="800px" /></p>
+
+<p>The challenge lies in enabling support for multiple hardware back-ends while keeping compute, memory and energy footprints at their lowest. We borrow wisdom from the compiler community in order to bridge the gap between the multitude of deep learning frameworks and hardware back-ends: we build a two-level intermediate layer composed of NNVM, a high-level intermediate representation (IR) for task scheduling and memory management, and TVM, an expressive low-level IR for optimizing compu [...]
+
+<p>The first level of the stack is a computational graph based representation. A computation graph is a directed acyclic graph that represent computation as nodes and dataflow dependency as edges. This representation is very powerful: it allows us to bake operation attributes into the computation graph and specify transformation rules to iteratively optimize a computation graph. This is a common approach taken by most of the existing deep learning frameworks, including the NNVM graph rep [...]
+
+<p style="text-align: center"><img src="/images/release/computational_graph.png" alt="image" width="300px" /></p>
+
+<p>A lot of powerful optimizations can be supported by the graph optimization framework. For example, we provided a sublinear memory optimization functionality that allows user to train 1000 layers of ImageNet ResNet on a single GPU.</p>
+
+<p style="text-align: center"><img src="/images/release/nnvm_gap.png" alt="image" width="512px" /></p>
+
+<p>However, we find that the computational graph based IR alone is not enough to solve the challenge of supporting different hardware backends. The reason being that a single graph operator like convolution or matrix multiplication may be mapped and optimized in very different ways for each hardware back-end. These hardware-specific optimizations can vary drastically in terms of memory layout, parallelization threading patterns, caching access patterns and choice of hardware primitives. [...]
+
+<p>We build a low level representation to solve this problem. This representation is based on index formula, with additional support for recurrence computation.</p>
+
+<p style="text-align: center"><img src="/images/release/tvm_dsl.png" alt="image" width="700px" /></p>
+
+<p>The low level IR adopt principles from existing image processing languages like Halide or darkroom to formulate an expressive deep learning DSL. TVM builds low level optimizations inspired by loop transformation tools like loopy and polyhedra-based analysis. We also draw inspiration from the dataflow description languages used in deep learning frameworks like MXNet, TensorFlow, Theano. The algorithms described in TVM are then processed in a scheduling phase to apply transformations th [...]
+
+<p style="text-align: center"><img src="/images/release/tvm_backends.png" alt="image" width="600px" /></p>
+
+<p>TVM includes standard transformation primitives commonly found in CPU optimization frameworks. More importantly, TVM incorporates novel optimization primitives targeted at GPUs, by exploiting thread cooperation patterns, data layout transformations and powerful new compute primitives. Using TVM in combination with NNVM provides an rich opportunity to optimize deep learning workloads across the software stack, enabling joint compute graph-level and operator-level optimizations.</p>
+
+<h3 id="multi-language-and-platform-support">Multi-language and Platform Support</h3>
+
+<p>One of the many strength of TVM lies in its rich support for multiple platforms and languages. We present two components of the framework: the compiler stack which contains complete optimization libraries to produce optimized machine code, and the runtime which is lightweight and offers the portability required to deploy the compiled modules on different platforms.</p>
+
+<p style="text-align: center"><img src="/images/release/tvm_flexible.png" alt="image" width="600px" /></p>
+
+<p>TVM currently support a python and C++ interface to the embedded compiler stack. We design the framework with maximum re-use in mind, so that the compiler stack improvements can be applied interchangeably between the Python and C++ components.</p>
+
+<p>We also provide a lightweight runtime that can directly run TVM compiled code in languages such as javascript, java, python, and c++ on platforms including android, iOS, raspberry pi and web browsers.</p>
+
+<h3 id="remote-deployment-and-execution">Remote Deployment and Execution</h3>
+
+<p style="text-align: center"><img src="/images/release/tvm_rpc.png" alt="image" width="500px" /></p>
+
+<p>TVM supports cross-compilation for and testing embedded devices with TVM RPC, a lightweight interface to deploy and execute TVM cross-compiled modules on a remote embedded device. This provides a familiar high-level Python interface to the TVM user to compile, optimize and test deep learning algorithms remotely on various low-level embedded devices.</p>
+
+<h2 id="performance">Performance</h2>
+
+<p>TVM is still in an early stage of development and we can expect more improvements to come, but we have started to see very promising results, which are discussed in this section.</p>
+
+<p>TVM gives us the flexibility to explore the rich optimization space of various deep learning kernels, for multiple hardware platforms. For instance, TVM allows us to tailor data layout and fused pattern requirements for the kernels and platforms that we most care about. Please note that the baseline libraries are created for more general purpose problems, while TVM’s optimized kernels are heavily tuned for the workloads we evaluated via an auto-tuning process. TVM serves as a bridge [...]
+
+<p>The results listed in this section are still work in progress, and there is room for improvement.</p>
+
+<h3 id="raspberry-pi">Raspberry Pi</h3>
+
+<p>In the first part of result we compared the TVM CPU schedule to nnpack on a raspberry Pi 3B executing a resnet workload. Due to limited time, we utilized TVM to implemented the direct convolution while nnpack was used to perform winograd conv for 3x3 kernels.</p>
+
+<p style="text-align: center"><img src="/images/release/resnet_rasp.png" alt="image" width="500px" /></p>
+
+<p>We can find that with TVM’s autotuned kernels, we can obtain performance similar to the hand-optimized kernels in nnpack for the raspberry pi experiments.</p>
+
+<h3 id="gpu-results">GPU Results</h3>
+<p><strong>Author Credit</strong> These benchmarks and corresponding schedule optimizations are created by our contributors: <a href="http://www.ece.ucdavis.edu/~laurawly/">Leyuan Wang</a> (AWS / UCDavis), <a href="http://huyuwei.github.io">Yuwei Hu</a>(TuSimple) and Weitang Liu (AWS/ UCDavis). They deserve all the credits.</p>
+
+<p>As a proof of concept, we created an end to end compilation pipeline that can compile MxNet models down to TVM execution graphs. We apply optimization within and between graph nodes by automatically fusing operators together and letting TVM generate the fused kernels.
+We benchmarked the mobilenet ImageNet workload, and discuss the results below:</p>
+
+<p style="text-align: center"><img src="/images/release/gpu_mobilenet.png" alt="image" width="600px" /></p>
+
+<p>We can find that TVM can outperform our baseline method in terms of speed. More interestingly, the kernel fusion brings additional speedup. It is worth mentioning that TVM generates all the optimized GPU kernels on its own without relying on external libraries like CuDNN.</p>
+
+<p>We are working on more experiments and will release new results as they are obtained.</p>
+
+<h2 id="open-source-effort">Open Source Effort</h2>
+<p>TVM started as a research project of Paul G. Allen School Computer Science and Engineering at University of Washington. The TVM stack is designed to support <a href="https://github.com/dmlc/dlpack">DLPack</a>, a consensus on tensor data structure by multiple major deep learning frameworks. We have received early contributions from from UW, AWS, Qiho 360, Facebook, HKUST, TuSimple, UCDavis, SJTU as well members of DMLC open-source community and DLPack initiative. Going forward, the pro [...]
+
+<h2 id="acknowledgement">Acknowledgement</h2>
+<p>This project wouldn’t become possible without our early contributors. We would like to thank Yizhi Liu(Qihoo 360), Yuwei Hu(TuSimple),
+Xingjian Shi(HKUST), Leyuan Wang(AWS/UCDavis), Nicolas Vasilache(Facebook), Jian Weng(UCLA), Weitang Liu(AWS/UCDavis), Edward Z. Yang(Facebook),
+Lianmin Zheng(SJTU), Qiao Zhang(UW), William Moses(Facebook/MIT) and Hu Shiwen. The author would also like to thank Xianyi Zhang(PerfXLab) for helpful discussions.</p>
+
+<p>We also learnt a lot from the following projects when building TVM.</p>
+<ul>
+ <li><a href="https://github.com/halide/Halide">Halide</a>: TVM uses <a href="https://github.com/dmlc/HalideIR">HalideIR</a> as data structure for
+arithematic simplification and low level lowering. HalideIR is derived from Halide.
+We also learns from Halide when implementing the lowering pipeline in TVM.</li>
+ <li><a href="https://github.com/inducer/loopy">Loopy</a>: use of integer set analysis and its loop transformation primitives.</li>
+ <li><a href="https://github.com/Theano/Theano">Theano</a>: the design inspiration of symbolic scan operator for recurrence.</li>
+</ul>
+
+<h2 id="source-code">Source code</h2>
+<ul>
+ <li>Github page can be found here: <a href="https://github.com/dmlc/tvm">https://github.com/dmlc/tvm</a></li>
+ <li>TVM is <a href="https://github.com/dmlc/dlpack">DLPack</a> compatible, which makes it easy to support frameworks
+that adopts the standard, such as MXNet, PyTorch, Caffe2 and tiny-dnn.</li>
+</ul>
+
+ </div>
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+ or stability of the code, it does indicate that the project has yet to be fully endorsed by the ASF.
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+ Copyright © 2020 The Apache Software Foundation. Apache TVM, Apache,
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diff --git a/2017/08/22/Optimize-Deep-Learning-GPU-Operators-with-TVM-A-Depthwise-Convolution-Example.html b/2017/08/22/Optimize-Deep-Learning-GPU-Operators-with-TVM-A-Depthwise-Convolution-Example.html
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@@ -0,0 +1,775 @@
+
+<!DOCTYPE html>
+<html lang="en">
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+ <meta charset="utf-8">
+ <title>Optimize Deep Learning GPU Operators with TVM: A Depthwise Convolution Example</title>
+
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+
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+ <h1>Optimize Deep Learning GPU Operators with TVM: A Depthwise Convolution Example </h1>
+ <p class="post-meta">
+ <time datetime="2017-08-22T00:00:00-07:00" itemprop="datePublished">
+ Aug 22, 2017
+ </time>
+
+ • <span itemprop="author" itemscope itemtype="http://schema.org/Person">
+ <span itemprop="name">Yuwei Hu</span>
+ </span>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p>Efficient deep learning operators are at the core of deep learning systems.
+Usually these operators are hard to optimize and require great efforts of HPC experts.
+<a href="https://github.com/dmlc/tvm">TVM</a>, an end to end tensor IR/DSL stack, makes this much easier.</p>
+
+<p>This blog teaches you how to write high-performance GPU operator kernels with the help of TVM.
+We use depthwise convolution (i.e. <a href="http://docs.tvmlang.org/api/python/topi.html#topi.nn.depthwise_conv2d_nchw">topi.nn.depthwise_conv2d_nchw</a>) as an example,
+and demonstrate how we can improve over the already hand optimized CUDA kernel in tensorflow.
+Our final version is 2x-4x faster than the optimized kernel in tf-1.2 under different workloads, and 3x-7x faster with operator fusion enabled.
+Below is the result tested on GTX1080, with filter size = [1, 256, 3, 3], stride = [1, 1], padding = ‘SAME’:</p>
+
+<p style="text-align: center"><img src="/images/depthconv_tutorial/tf_compare.png" alt="image" width="95%" /></p>
+
+<h2 id="introduction-to-depthwise-convolution">Introduction to Depthwise Convolution</h2>
+
+<p>Depthwise convolution is an important building block of modern architectures, such as Xception [1] and MobileNet [2].
+It’s an effective method to reduce the computation complexity of deep neural networks.</p>
+
+<p style="text-align: center"><img src="/images/depthconv_tutorial/conv_and_depthconv.png" alt="image" width="80%" /></p>
+
+<p style="text-align: center">source: <a href="http://machinethink.net/blog/googles-mobile-net-architecture-on-iphone/">http://machinethink.net/blog/googles-mobile-net-architecture-on-iphone/</a></p>
+
+<p>In TVM, depthwise convolution can be declared as:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1"># padding stage
+</span><span class="n">PaddedInput</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">(</span>
+ <span class="p">(</span><span class="n">batch</span><span class="p">,</span> <span class="n">in_channel</span><span class="p">,</span> <span class="n">height_after_pad</span><span class="p">,</span> <span class="n">width_after_pad</span><span class="p">),</span>
+ <span class="k">lambda</span> <span class="n">b</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">:</span> <span class="n">tvm</span><span class="o">.</span><span class="n">select</span><span class="p">(</span>
+ <span class="n">tvm</span><span class="o">.</span><span class="nb">all</span><span class="p">(</span><span class="n">i</span> <span class="o">>=</span> <span class="n">pad_top</span><span class="p">,</span> <span class="n">i</span> <span class="o">-</span> <span class="n">pad_top</span> <span class="o"><</span> <span class="n">in_height</span><span class="p">,</span> <span class="n">j</span> <span class="o">>=</span> <span class="n">pad_left</span><span class="p">,</span [...]
+ <span class="n">Input</span><span class="p">[</span><span class="n">b</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">i</span> <span class="o">-</span> <span class="n">pad_top</span><span class="p">,</span> <span class="n">j</span> <span class="o">-</span> <span class="n">pad_left</span><span class="p">],</span> <span class="n">tvm</span><span class="o">.</span><span class="n">const</span><span class="p">(</span><span class="mf">0.0 [...]
+ <span class="n">name</span><span class="o">=</span><span class="s">"PaddedInput"</span><span class="p">)</span>
+<span class="c1"># depthconv stage
+</span><span class="n">di</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">filter_height</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'di'</span><span class="p">)</span>
+<span class="n">dj</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">filter_width</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'dj'</span><span class="p">)</span>
+<span class="n">Output</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">(</span>
+ <span class="p">(</span><span class="n">batch</span><span class="p">,</span> <span class="n">out_channel</span><span class="p">,</span> <span class="n">out_height</span><span class="p">,</span> <span class="n">out_width</span><span class="p">),</span>
+ <span class="k">lambda</span> <span class="n">b</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">:</span> <span class="n">tvm</span><span class="o">.</span><span class="nb">sum</span><span class="p">(</span>
+ <span class="n">PaddedInput</span><span class="p">[</span><span class="n">b</span><span class="p">,</span> <span class="n">c</span><span class="o">/</span><span class="n">channel_multiplier</span><span class="p">,</span> <span class="n">i</span><span class="o">*</span><span class="n">stride_h</span> <span class="o">+</span> <span class="n">di</span><span class="p">,</span> <span class="n">j</span><span class="o">*</span><span class="n">stride_w</span> <span class="o">+</span> <sp [...]
+ <span class="n">axis</span><span class="o">=</span><span class="p">[</span><span class="n">di</span><span class="p">,</span> <span class="n">dj</span><span class="p">]),</span>
+ <span class="n">name</span><span class="o">=</span><span class="s">'DepthwiseConv2d'</span><span class="p">)</span>
+</code></pre></div></div>
+
+<h2 id="general-gpu-optimization-guidelines">General GPU Optimization Guidelines</h2>
+
+<p>This part briefly talks about three concepts we should know when optimizing CUDA code: data reuse, shared memory and bank conflicts.
+It would be great if you already know them, then you may skip this part.</p>
+
+<h3 id="data-reuse">Data Reuse</h3>
+<p>In modern computing architectures, the cost of loading data from memory is much higher than doing a single floating point computation [3].
+Because of that, we always want to reuse the input data after they are loaded into registers or shared memory (cache).</p>
+
+<p>There are two forms of data reuse in depthwise convolution: filter reuse and input reuse. Filter reuse happens as the filter slides over the input channel and computes multiple times.
+Input reuse is realized through tiling, let’s take 3x3 depthwise conv as an example:</p>
+
+<p style="text-align: center"><img src="/images/depthconv_tutorial/no_tiling.png" alt="image" width="70%" /></p>
+
+<p>Without tiling, each thread computes 1 output element and loads 3x3 input data. 16 threads together have 9x16 loads.</p>
+
+<p style="text-align: center"><img src="/images/depthconv_tutorial/tiling.png" alt="image" width="70%" /></p>
+
+<p>With tiling, each thread computes 2x2 output elements and loads 4x4 input data. 4 threads together have 16x4 loads.</p>
+
+<h3 id="shared-memory-and-bank-conflicts">Shared Memory and Bank Conflicts</h3>
+<p>Shared memory can be seen as cache in GPU. It is on-chip and much faster than global memory.</p>
+
+<p style="text-align: center"><img src="/images/depthconv_tutorial/GPU_memory_hierarchy.png" alt="image" width="256px" /></p>
+
+<p>Shared memory is allocated per block. It’s common practice to load data from global memory into shared memory, and then all threads in the block read data from shared memory.</p>
+
+<p>The size of shared memory is limited (usually 48K), so we must be cautious of shared memory overflow.
+Besides, too much shared memory allocated to one block limits the number of active blocks per multiprocessor.</p>
+
+<p>Another performance issue with shared memory is bank conflicts. Shared memory is divided into equally sized memory modules (banks) that can be accessed simultaneously,
+however, if multiple threads access the same memory bank (causing bank conflicts), the accesses will be serialized, thus decreasing the effective bandwidth.</p>
+
+<p>Shared memory banks are organized such that successive addresses are assigned to successive banks.
+To avoid bank conflicts, it’s better that successive threads access successive memory addresses, as illustrated below (each color represents one shared memory bank):</p>
+
+<p style="text-align: center"><img src="/images/depthconv_tutorial/bank_conflicts.png" alt="image" width="95%" /></p>
+
+<p>For more details on shared memory and bank conflicts, please refer to <a href="https://devblogs.nvidia.com/parallelforall/using-shared-memory-cuda-cc/">this Nvidia’s blog</a>.</p>
+
+<p>Ok, now let’s start optimizing depthwise convolution in TVM.</p>
+
+<h2 id="schedule-optimization">Schedule Optimization</h2>
+
+<h3 id="compute-paddedinput-inline-to-save-memory-allocation">Compute PaddedInput Inline to Save Memory Allocation</h3>
+<p>As we see from part 1, padding is declared explicitly as a separate stage. We compute it inline to avoid redundant memory allocation:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">s</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">create_schedule</span><span class="p">(</span><span class="n">Output</span><span class="o">.</span><span class="n">op</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">PaddedInput</span><span class="p">]</span><span class="o">.</span><span class="n">compute_inline</span><span class="p">()</span>
+</code></pre></div></div>
+
+<h3 id="divide-one-large-channel-into-smaller-blocks">Divide One Large Channel into Smaller Blocks</h3>
+<p>One straightforward schedule for depthwise convolution is that one cuda block takes care of one input channel and corresponding filters, loading them into shared memory and then computing:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">IS</span> <span class="o">=</span> <span class="n">s</span><span class="o">.</span><span class="n">cache_read</span><span class="p">(</span><span class="n">PaddedInput</span><span class="p">,</span> <span class="s">"shared"</span><span class="p">,</span> <span class="p">[</span><span class="n">DepthwiseConv2d</span><span class="p">])</span>
+<span class="n">FS</span> <span class="o">=</span> <span class="n">s</span><span class="o">.</span><span class="n">cache_read</span><span class="p">(</span><span class="n">Filter</span><span class="p">,</span> <span class="s">"shared"</span><span class="p">,</span> <span class="p">[</span><span class="n">DepthwiseConv2d</span><span class="p">])</span>
+<span class="n">block_y</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"blockIdx.y"</span><span class="p">)</span>
+<span class="n">block_x</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"blockIdx.x"</span><span class="p">)</span>
+<span class="c1"># bind the dimension of batch (N in NCHW) with block_y
+</span><span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">Output</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span><span class="p">[</span><span class="mi">0</span><span class="p">],</span> <span class="n">block_y</span><span class="p">)</span>
+<span class="c1"># bind the dimension of channel (C in NCHW) with block_x
+</span><span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">Output</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span><span class="p">[</span><span class="mi">1</span><span class="p">],</span> <span class="n">block_x</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>We test the average time cost of 1000 runs on GTX 1080, and compare with <a href="https://www.tensorflow.org/versions/r0.12/api_docs/python/nn/convolution#depthwise_conv2d">depthwise_conv2d in tensorflow</a>.
+Here is the result:</p>
+
+<table>
+ <thead>
+ <tr>
+ <th style="text-align: center">Input</th>
+ <th style="text-align: center">Filter</th>
+ <th style="text-align: center">stride</th>
+ <th style="text-align: center">tf-1.2 SAME pad (us)</th>
+ <th style="text-align: center">TVM SAME pad (us)</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td style="text-align: center">[1, 256, 21, 21]</td>
+ <td style="text-align: center">[256, 1, 3, 3]</td>
+ <td style="text-align: center">[1, 1]</td>
+ <td style="text-align: center">16.1</td>
+ <td style="text-align: center">9.1</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">[1, 256, 32, 32]</td>
+ <td style="text-align: center">[256, 1, 3, 3]</td>
+ <td style="text-align: center">[1, 1]</td>
+ <td style="text-align: center">34.8</td>
+ <td style="text-align: center">14.5</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">[1, 256, 64, 64]</td>
+ <td style="text-align: center">[256, 1, 3, 3]</td>
+ <td style="text-align: center">[1, 1]</td>
+ <td style="text-align: center">130.9</td>
+ <td style="text-align: center">98.9</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">[256, 1, 3, 3]</td>
+ <td style="text-align: center">[1, 1]</td>
+ <td style="text-align: center">251.6</td>
+ <td style="text-align: center">387.4</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>As we can see, this schedule performs well with small channel size like 21 x 21 or 32 x 32, however, its performance drops seriously as the channel size increases to larger than 64 x 64.
+One main reason is that too much shared memory allocated to one block limits the number of active blocks per multiprocessor.</p>
+
+<p>We modify the schedule to divide one large channel into smaller blocks. For example, one channel (64 x 64 or 96 x 96) is divided into blocks of 32 x 32,
+and one cuda block takes care of one 32 x 32 block:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">blocking_h</span> <span class="o">=</span> <span class="mi">32</span>
+<span class="n">blocking_w</span> <span class="o">=</span> <span class="mi">32</span>
+<span class="c1"># split the dimension of height (H in NCHW)
+</span><span class="n">bx1</span><span class="p">,</span> <span class="n">_</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">Output</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span><span class="p">[</span><span class="mi">2</span><span class="p">],</span> <sp [...]
+<span class="c1"># split the dimension of width (W in NCHW)
+</span><span class="n">bx2</span><span class="p">,</span> <span class="n">_</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">Output</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span><span class="p">[</span><span class="mi">3</span><span class="p">],</span> <sp [...]
+<span class="c1"># assign one 32 x 32 block to one cuda block
+</span><span class="n">by</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">fuse</span><span class="p">(</span><span class="n">Output</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span><span class="p">[</span><span class="mi">0</span><span class="p">],</span> <span class="n">Output</span><span class="o">.</span>< [...]
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">by</span><span class="p">,</span> <span class="n">block_y</span><span class="p">)</span>
+<span class="n">bx</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">fuse</span><span class="p">(</span><span class="n">bx1</span><span class="p">,</span> <span class="n">bx2</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">bx</span><span class="p">,</span> <span class="n">block_x</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>Here is the new result:</p>
+
+<table>
+ <thead>
+ <tr>
+ <th style="text-align: center">Input</th>
+ <th style="text-align: center">[blocking_h, blocking_w]</th>
+ <th style="text-align: center">tf-1.2 SAME pad (us)</th>
+ <th style="text-align: center">TVM SAME pad (us)</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td style="text-align: center">[1, 256, 64, 64]</td>
+ <td style="text-align: center">[32, 32]</td>
+ <td style="text-align: center">130.9</td>
+ <td style="text-align: center">63.4</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">[32, 32]</td>
+ <td style="text-align: center">251.6</td>
+ <td style="text-align: center">132.5</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>Our blocking strategy works! For 64 x 64 channel size, it brings 1.6x acceleration (98.9us -> 63.4us); for 96 x 96 channel size, it brings 2.9x acceleration (387.4us -> 132.5us).</p>
+
+<h3 id="tuning-parameters-of-thread-numbers">Tuning Parameters of Thread Numbers</h3>
+
+<p>How to schedule the workload, say, 32x32 among the threads of one cuda block? Intuitively, it should be like this:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">num_thread_y</span> <span class="o">=</span> <span class="mi">8</span>
+<span class="n">num_thread_x</span> <span class="o">=</span> <span class="mi">8</span>
+<span class="n">thread_y</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">num_thread_y</span><span class="p">),</span> <span class="s">"threadIdx.y"</span><span class="p">)</span>
+<span class="n">thread_x</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">num_thread_x</span><span class="p">),</span> <span class="s">"threadIdx.x"</span><span class="p">)</span>
+<span class="n">ty</span><span class="p">,</span> <span class="n">yi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">h_dim</span><span class="p">,</span> <span class="n">nparts</span><span class="o">=</span><span class="n">num_thread_y</span><span class="p">)</span>
+<span class="n">tx</span><span class="p">,</span> <span class="n">xi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">w_dim</span><span class="p">,</span> <span class="n">nparts</span><span class="o">=</span><span class="n">num_thread_x</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">reorder</span><span class="p">(</span><span class="n">ty</span><span class="p">,</span> <span class="n">tx</span><span class="p">,</span> <span class="n">yi</span><span class="p">,</span> <span class="n">xi</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">ty</span><span class="p">,</span> <span class="n">thread_y</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">tx</span><span class="p">,</span> <span class="n">thread_x</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>There are two parameters in the schedule: <code class="highlighter-rouge">num_thread_y</code> and <code class="highlighter-rouge">num_thread_x</code>. How to determine the optimal combination of them?
+Well, let’s first do some experiments. Below is the result with Filter = [256, 1, 3, 3] and stride = [1, 1]:</p>
+
+<table>
+ <thead>
+ <tr>
+ <th style="text-align: center">Case</th>
+ <th style="text-align: center">Input</th>
+ <th style="text-align: center">num_thread_y</th>
+ <th style="text-align: center">num_thread_x</th>
+ <th style="text-align: center">TVM SAME pad (us)</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td style="text-align: center">1</td>
+ <td style="text-align: center">[1, 256, 32, 32]</td>
+ <td style="text-align: center">8</td>
+ <td style="text-align: center">32</td>
+ <td style="text-align: center">9.7</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">2</td>
+ <td style="text-align: center">[1, 256, 32, 32]</td>
+ <td style="text-align: center">4</td>
+ <td style="text-align: center">32</td>
+ <td style="text-align: center">8.8</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">3</td>
+ <td style="text-align: center">[1, 256, 32, 32]</td>
+ <td style="text-align: center">1</td>
+ <td style="text-align: center">32</td>
+ <td style="text-align: center">17.7</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">4</td>
+ <td style="text-align: center">[1, 256, 32, 32]</td>
+ <td style="text-align: center">32</td>
+ <td style="text-align: center">1</td>
+ <td style="text-align: center">32.5</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>Many interesting observations from above results:</p>
+
+<ul>
+ <li>
+ <p>Case 2 is faster than case 1. In case 2, each thread computes a 8x1 tile in output, which corresponds to a 10x3 tile in input.
+It has better data reuse than case 1’s 4x1 tile.</p>
+ </li>
+ <li>
+ <p>Case 3 is slower than case 2. It’s because in case 3, the workload per thread is too large and leads to much cost of local memory read.</p>
+ </li>
+ <li>
+ <p>Case 4 is slower than case 3. It’s because <code class="highlighter-rouge">num_thread_x = 32</code> ensures no bank conflicts, while <code class="highlighter-rouge">num_thread_y = 32</code> doesn’t.</p>
+ </li>
+</ul>
+
+<p>To summarize what we learn from above observations:</p>
+
+<ul>
+ <li>Large tile is good for data reuse, but not good for local memory read.</li>
+ <li>The influence of <code class="highlighter-rouge">num_thread_y</code> and <code class="highlighter-rouge">num_thread_x</code> on bank conflicts is asymmetric.</li>
+ <li>To find the optimal combination of <code class="highlighter-rouge">num_thread_y</code> and <code class="highlighter-rouge">num_thread_x</code> is to achieve a balance of efficient shared memory access (avoid bank conflicts), data reuse, and local memory read.</li>
+</ul>
+
+<p>Pretty tricky. So, what exactly should we do to find the optimal combination? The answer is brute force search.
+We can pass <code class="highlighter-rouge">num_thread_y</code> and <code class="highlighter-rouge">num_thread_x</code> as arguments to the schedule function, and try all possible combinations to find the optimal one. This can be done easily in TVM:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="k">def</span> <span class="nf">schedule_depthwise_conv2d</span><span class="p">(</span><span class="o">...</span><span class="p">,</span> <span class="n">num_thread_y</span><span class="o">=</span><span class="mi">8</span><span class="p">,</span> <span class="n">num_thread_x</span><span class="o">=</span><span class="mi">8</span><span class="p">):</span>
+ <span class="n">num_thread_y</span> <span class="o">=</span> <span class="n">num_thread_y</span>
+ <span class="n">num_thread_x</span> <span class="o">=</span> <span class="n">num_thread_x</span>
+ <span class="n">do_schedule_as_usual</span>
+ <span class="k">return</span> <span class="n">schedule</span>
+
+<span class="n">min_time_cost</span> <span class="o">=</span> <span class="n">inf</span>
+<span class="k">for</span> <span class="n">num_thread_y</span><span class="p">,</span> <span class="n">num_thread_x</span> <span class="ow">in</span> <span class="n">all_possible_combinations</span><span class="p">:</span>
+ <span class="n">schedule</span> <span class="o">=</span> <span class="n">schedule_depthwise_conv2d</span><span class="p">(</span><span class="o">...</span><span class="p">,</span> <span class="n">num_thread_y</span><span class="o">=</span><span class="n">num_thread_y</span><span class="p">,</span> <span class="n">num_thread_x</span><span class="o">=</span><span class="n">num_thread_x</span><span class="p">)</span>
+ <span class="n">time_cost</span> <span class="o">=</span> <span class="n">test_depthwise_conv2d</span><span class="p">(</span><span class="o">...</span><span class="p">,</span> <span class="n">schedule</span><span class="p">)</span>
+ <span class="k">if</span> <span class="n">time_cost</span> <span class="o"><</span> <span class="n">min_time_cost</span><span class="p">:</span>
+ <span class="n">min_time_cost</span> <span class="o">=</span> <span class="n">time_cost</span>
+ <span class="n">optimal_combination</span> <span class="o">=</span> <span class="p">[</span><span class="n">num_thread_y</span><span class="p">,</span> <span class="n">num_thread_x</span><span class="p">]</span>
+</code></pre></div></div>
+
+<p>In fact, it can be seen as a simple auto scheduler.</p>
+
+<h3 id="vthread-and-strided-patterns">Vthread and Strided Patterns</h3>
+<p>Vthread (virtual thread) in TVM is introduced to support strided patterns. We can use it this way:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">num_vthread_y</span> <span class="o">=</span> <span class="mi">2</span>
+<span class="n">num_vthread_x</span> <span class="o">=</span> <span class="mi">2</span>
+<span class="n">num_thread_y</span> <span class="o">=</span> <span class="mi">8</span>
+<span class="n">num_thread_x</span> <span class="o">=</span> <span class="mi">8</span>
+<span class="n">thread_vy</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">num_vthread_y</span><span class="p">),</span> <span class="s">"vthread"</span><span class="p">,</span> <span class="n">name</span><span class="o">=</span><span class="s">"vy"</span><span class="p">)</span>
+<span class="n">thread_vx</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">num_vthread_x</span><span class="p">),</span> <span class="s">"vthread"</span><span class="p">,</span> <span class="n">name</span><span class="o">=</span><span class="s">"vx"</span><span class="p">)</span>
+<span class="n">thread_y</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">num_thread_y</span><span class="p">),</span> <span class="s">"threadIdx.y"</span><span class="p">)</span>
+<span class="n">thread_x</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">num_thread_x</span><span class="p">),</span> <span class="s">"threadIdx.x"</span><span class="p">)</span>
+<span class="c1"># split the dimension of height (H in NCHW) twice
+</span><span class="n">tvy</span><span class="p">,</span> <span class="n">vyi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">h_dim</span><span class="p">,</span> <span class="n">nparts</span><span class="o">=</span><span class="n">num_vthread_y</span><span class="p">)</span>
+<span class="n">ty</span><span class="p">,</span> <span class="n">yi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">vyi</span><span class="p">,</span> <span class="n">nparts</span><span class="o">=</span><span class="n">num_thread_y</span><span class="p">)</span>
+<span class="c1"># split the dimension of width (W in NCHW) twice
+</span><span class="n">tvx</span><span class="p">,</span> <span class="n">vxi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">w_dim</span><span class="p">,</span> <span class="n">nparts</span><span class="o">=</span><span class="n">num_vthread_x</span><span class="p">)</span>
+<span class="n">tx</span><span class="p">,</span> <span class="n">xi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">vxi</span><span class="p">,</span> <span class="n">nparts</span><span class="o">=</span><span class="n">num_thread_x</span><span class="p">)</span>
+<span class="c1"># bind thread and vthread respectively
+</span><span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">tvy</span><span class="p">,</span> <span class="n">thread_vy</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">tvx</span><span class="p">,</span> <span class="n">thread_vx</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">ty</span><span class="p">,</span> <span class="n">thread_y</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">tx</span><span class="p">,</span> <span class="n">thread_x</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">]</span><span class="o">.</span><span class="n">reorder</span><span class="p">(</span><span class="n">tvy</span><span class="p">,</span> <span class="n">tvx</span><span class="p">,</span> <span class="n">ty</span><span class="p">,</span> <span class="n">tx</span><span class="p">,</span> <span class="n">yi</span><span class="p">,</span> <span class="n">xi</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>Let’s print the IR to see what vthread does:</p>
+
+<div class="language-c++ highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="cm">/* Input = [1, 1, 32, 32], Filter = [1, 1, 3, 3], stride = [1, 1], padding = 'SAME' */</span>
+<span class="n">produce</span> <span class="n">DepthwiseConv2d</span> <span class="p">{</span>
+ <span class="c1">// attr [iter_var(blockIdx.y, , blockIdx.y)] thread_extent = 1</span>
+ <span class="c1">// attr [iter_var(blockIdx.x, , blockIdx.x)] thread_extent = 1</span>
+ <span class="c1">// attr [iter_var(threadIdx.y, Range(min=0, extent=8), threadIdx.y)] thread_extent = 8</span>
+ <span class="c1">// attr [iter_var(threadIdx.x, Range(min=0, extent=8), threadIdx.x)] thread_extent = 8</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">i</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">2</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">j</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">2</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">DepthwiseConv2d</span><span class="p">[((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">16</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span><spa [...]
+ <span class="n">DepthwiseConv2d</span><span class="p">[(((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">16</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span><sp [...]
+ <span class="n">DepthwiseConv2d</span><span class="p">[(((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">16</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span><sp [...]
+ <span class="n">DepthwiseConv2d</span><span class="p">[(((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">16</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span><sp [...]
+ <span class="k">for</span> <span class="p">(</span><span class="n">di</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">3</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">dj</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">3</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">DepthwiseConv2d</span><span class="p">[((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">16</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span> [...]
+ <span class="n">DepthwiseConv2d</span><span class="p">[(((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">16</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span [...]
+ <span class="n">DepthwiseConv2d</span><span class="p">[(((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">16</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span [...]
+ <span class="n">DepthwiseConv2d</span><span class="p">[(((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">16</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span [...]
+ <span class="p">}</span>
+ <span class="p">}</span>
+ <span class="p">}</span>
+ <span class="p">}</span>
+<span class="p">}</span>
+</code></pre></div></div>
+
+<p>Without vthread (just set to 1), the IR is:</p>
+
+<div class="language-c++ highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="cm">/* Input = [1, 1, 32, 32], Filter = [1, 1, 3, 3], stride = [1, 1], padding = 'SAME' */</span>
+<span class="n">produce</span> <span class="n">DepthwiseConv2d</span> <span class="p">{</span>
+ <span class="c1">// attr [iter_var(blockIdx.y, , blockIdx.y)] thread_extent = 1</span>
+ <span class="c1">// attr [iter_var(blockIdx.x, , blockIdx.x)] thread_extent = 1</span>
+ <span class="c1">// attr [iter_var(threadIdx.y, Range(min=0, extent=8), threadIdx.y)] thread_extent = 8</span>
+ <span class="c1">// attr [iter_var(threadIdx.x, Range(min=0, extent=8), threadIdx.x)] thread_extent = 8</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">i</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">4</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">j</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">4</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">DepthwiseConv2d</span><span class="p">[((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">8</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span><span [...]
+ <span class="k">for</span> <span class="p">(</span><span class="n">di</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">3</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">dj</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">3</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">DepthwiseConv2d</span><span class="p">[((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">8</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span>< [...]
+ <span class="p">}</span>
+ <span class="p">}</span>
+ <span class="p">}</span>
+ <span class="p">}</span>
+<span class="p">}</span>
+</code></pre></div></div>
+
+<p>As we can see, when <code class="highlighter-rouge">num_vthread_y = 2</code> and <code class="highlighter-rouge">num_vthread_x = 2</code>, the 32 x 32 channel is divided into four sub-channels of 16 x 16.
+Each thread computes four output elements at a time, one element in one sub-channel.</p>
+
+<p>Below is the result with Filter = [256, 1, 3, 3], stride = [1, 1], blocking_h = 32, blocking_w = 32:</p>
+
+<style>
+table th:nth-of-type(1) {
+ width: 120px;
+}
+table th:nth-of-type(2) {
+ width: 120px;
+}
+</style>
+
+<table>
+ <thead>
+ <tr>
+ <th style="text-align: center">Case</th>
+ <th style="text-align: center">Input</th>
+ <th style="text-align: center">num_thread_y, num_thread_x</th>
+ <th style="text-align: center">num_vthread_y, num_vthread_x</th>
+ <th style="text-align: center">TVM SAME pad (us)</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td style="text-align: center">1</td>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">8, 8</td>
+ <td style="text-align: center">1, 1</td>
+ <td style="text-align: center">132.5</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">2</td>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">8, 8</td>
+ <td style="text-align: center">1, 4</td>
+ <td style="text-align: center">103.1</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">3</td>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">4, 32</td>
+ <td style="text-align: center">1, 1</td>
+ <td style="text-align: center">95.9</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">4</td>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">8, 16</td>
+ <td style="text-align: center">1, 2</td>
+ <td style="text-align: center">90.9</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>Case 2 is faster than case 1. It’s because in case 2 <code class="highlighter-rouge">num_thread_x=8</code> and <code class="highlighter-rouge">num_vthread_x=4</code> together ensures that consecutive threads access consecutive memory addresses,
+thus avoiding bank conflicts, as illustrated below (each color represents one thread’s workload):</p>
+
+<p style="text-align: center"><img src="/images/depthconv_tutorial/vthread_and_strided_pattern.png" alt="image" width="90%" /></p>
+
+<p>In theory case 3 and 4 should be the same fast, since they have the same workload per thread, and both enjoy efficient shared memory access. Somehow case 4 is just a little faster.</p>
+
+<p>Still remember tensorflow’s speed? It’s 251.6us, and now TVM is 2.8x faster. 387.4 -> 132.5 -> 95.9 -> 90.9, blocking helps the most; tuning thread numbers saves 37us;
+vthread saves additional 5us.</p>
+
+<p>In fact, TVM can be extremely faster than tensorflow with large kernel size or channel_multiplier (because of more filter reuse) :</p>
+
+<table>
+ <thead>
+ <tr>
+ <th style="text-align: center">Input</th>
+ <th style="text-align: center">Filter</th>
+ <th style="text-align: center">stride</th>
+ <th style="text-align: center">tf-1.2 SAME pad (us)</th>
+ <th style="text-align: center">TVM SAME pad (us)</th>
+ <th style="text-align: center">How faster is TVM</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">[256, 1, 3, 3]</td>
+ <td style="text-align: center">[1, 1]</td>
+ <td style="text-align: center">251.6</td>
+ <td style="text-align: center">90.9</td>
+ <td style="text-align: center">2.8x</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">[256, 1, 5, 5]</td>
+ <td style="text-align: center">[1, 1]</td>
+ <td style="text-align: center">597.6</td>
+ <td style="text-align: center">128.9</td>
+ <td style="text-align: center">4.6x</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">[256, 2, 3, 3]</td>
+ <td style="text-align: center">[1, 1]</td>
+ <td style="text-align: center">659.9</td>
+ <td style="text-align: center">143.7</td>
+ <td style="text-align: center">4.6x</td>
+ </tr>
+ <tr>
+ <td style="text-align: center">[1, 256, 96, 96]</td>
+ <td style="text-align: center">[256, 2, 5, 5]</td>
+ <td style="text-align: center">[1, 1]</td>
+ <td style="text-align: center">1203.9</td>
+ <td style="text-align: center">170.5</td>
+ <td style="text-align: center">7.1x</td>
+ </tr>
+ </tbody>
+</table>
+
+<h2 id="operator-fusion">Operator Fusion</h2>
+
+<p>One typical optimization we can do in deep learning is operator fusion, that computes multiple operators together in a single kernel without saving intermediate results back to global memory.
+TVM supports that out of the box.</p>
+
+<p>Consider a common pattern in neural networks: <code class="highlighter-rouge">depthwise_conv2d</code> + <code class="highlighter-rouge">scale_shift</code> + <code class="highlighter-rouge">relu</code>. We can fuse the three operators into one, by slightly modifying the original schedule:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">DepthwiseConv2d</span> <span class="o">=</span> <span class="n">topi</span><span class="o">.</span><span class="n">nn</span><span class="o">.</span><span class="n">depthwise_conv2d</span><span class="p">(</span><span class="n">Input</span><span class="p">,</span> <span class="n">Filter</span><span class="p">,</span> <span class="n">stride</span><span class="p">,</span> <span [...]
+<span class="n">ScaleShift</span> <span class="o">=</span> <span class="n">topi</span><span class="o">.</span><span class="n">nn</span><span class="o">.</span><span class="n">scale_shift</span><span class="p">(</span><span class="n">DepthwiseConv2d</span><span class="p">,</span> <span class="n">Scale</span><span class="p">,</span> <span class="n">Shift</span><span class="p">)</span>
+<span class="n">Relu</span> <span class="o">=</span> <span class="n">topi</span><span class="o">.</span><span class="n">nn</span><span class="o">.</span><span class="n">relu</span><span class="p">(</span><span class="n">ScaleShift</span><span class="p">)</span>
+
+<span class="n">Output</span> <span class="o">=</span> <span class="n">Relu</span> <span class="c1"># is no longer DepthwiseConv2d
+</span><span class="n">s</span><span class="p">[</span><span class="n">ScaleShift</span><span class="p">]</span><span class="o">.</span><span class="n">compute_inline</span><span class="p">()</span> <span class="c1"># this line fuses ScaleShift, explicitly
+</span><span class="n">s</span><span class="p">[</span><span class="n">DepthwiseConv2d</span><span class="p">]</span><span class="o">.</span><span class="n">set_scope</span><span class="p">(</span><span class="s">"local"</span><span class="p">)</span> <span class="c1"># this line fuses DepthwiseConv2d, implicitly
+</span><span class="n">schedule</span><span class="p">(</span><span class="n">Output</span><span class="p">)</span> <span class="c1"># schedule for Output the same way we schedule for DepthwiseConv2d as discussed above
+</span><span class="n">s</span><span class="p">[</span><span class="n">DepthwiseConv2d</span><span class="p">]</span><span class="o">.</span><span class="n">compute_at</span><span class="p">(</span><span class="n">s</span><span class="p">[</span><span class="n">Output</span><span class="p">],</span> <span class="n">tx</span><span class="p">)</span> <span class="c1"># tx is the inner most axis, bound to threadIdx.x
+</span></code></pre></div></div>
+
+<p>It generates IR like this:</p>
+
+<div class="language-c++ highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="cm">/* Input = [1, 1, 32, 32], Filter = [1, 1, 3, 3], stride = [1, 1], padding = 'SAME' */</span>
+<span class="n">produce</span> <span class="n">Relu</span> <span class="p">{</span>
+ <span class="c1">// attr [iter_var(blockIdx.y, , blockIdx.y)] thread_extent = 1</span>
+ <span class="c1">// attr [DepthwiseConv2d] storage_scope = "local"</span>
+ <span class="n">allocate</span> <span class="n">DepthwiseConv2d</span><span class="p">[</span><span class="n">float32</span> <span class="o">*</span> <span class="mi">1</span> <span class="o">*</span> <span class="mi">1</span> <span class="o">*</span> <span class="mi">4</span> <span class="o">*</span> <span class="mi">4</span><span class="p">]</span>
+ <span class="c1">// attr [iter_var(blockIdx.x, , blockIdx.x)] thread_extent = 1</span>
+ <span class="c1">// attr [iter_var(threadIdx.y, Range(min=0, extent=8), threadIdx.y)] thread_extent = 8</span>
+ <span class="c1">// attr [iter_var(threadIdx.x, Range(min=0, extent=8), threadIdx.x)] thread_extent = 8</span>
+ <span class="n">produce</span> <span class="n">DepthwiseConv2d</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">i</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">4</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">j</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">4</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">DepthwiseConv2d</span><span class="p">[((</span><span class="n">i</span><span class="o">*</span><span class="mi">4</span><span class="p">)</span> <span class="o">+</span> <span class="n">j</span><span class="p">)]</span> <span class="o">=</span> <span class="mf">0.000000</span><span class="n">f</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">di</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">3</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">dj</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">3</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">DepthwiseConv2d</span><span class="p">[((</span><span class="n">i</span><span class="o">*</span><span class="mi">4</span><span class="p">)</span> <span class="o">+</span> <span class="n">j</span><span class="p">)]</span> <span class="o">=</span> <span class="p">(</span><span class="n">DepthwiseConv2d</span><span class="p">[((</span><span class="n">i</span><span class="o">*</span><span class="mi">4</span><span class="p">)</span> <span class="o">+</span> <span c [...]
+ <span class="p">}</span>
+ <span class="p">}</span>
+ <span class="p">}</span>
+ <span class="p">}</span>
+ <span class="p">}</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">i2</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">4</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="n">i3</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">.</span><span class="n">inner</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">4</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">Relu</span><span class="p">[((((((((</span><span class="n">blockIdx</span><span class="p">.</span><span class="n">y</span> <span class="o">+</span> <span class="n">blockIdx</span><span class="p">.</span><span class="n">x</span><span class="p">)</span><span class="o">*</span><span class="mi">8</span><span class="p">)</span> <span class="o">+</span> <span class="n">threadIdx</span><span class="p">.</span><span class="n">y</span><span class="p">)</span><span class="o"> [...]
+ <span class="p">}</span>
+ <span class="p">}</span>
+<span class="p">}</span>
+</code></pre></div></div>
+
+<p>As we can see, each thread computes <code class="highlighter-rouge">scale_shift</code> and <code class="highlighter-rouge">relu</code> before writing the result of <code class="highlighter-rouge">depthwise_conv2d</code> to global memory. The fused operator is as fast as single <code class="highlighter-rouge">depthwise_conv2d</code>.
+Below is the result with Input = [1, 256, 96, 96], Filter = [256, 1, 3, 3], stride = [1, 1], padding = ‘SAME’:</p>
+
+<ul>
+ <li>tf-1.2 <code class="highlighter-rouge">depthwise_conv2d</code>: 251.6 us</li>
+ <li>tf-1.2 <code class="highlighter-rouge">depthwise_conv2d</code> + <code class="highlighter-rouge">scale_shift</code> + <code class="highlighter-rouge">relu</code> (separate): 419.9 us</li>
+ <li>TVM <code class="highlighter-rouge">depthwise_conv2d</code>: 90.9 us</li>
+ <li>TVM <code class="highlighter-rouge">depthwise_conv2d + scale_shift + relu</code> (fused): 91.5 us</li>
+</ul>
+
+<p>The advantage of operator fusion is obvious.</p>
+
+<p>This is not the end, TVM can do operator fusion in a smarter way. You may refer to <a href="https://github.com/dmlc/tvm/issues/215">this</a> and read the source code provided below.</p>
+
+<h2 id="show-me-the-code">Show me the code</h2>
+<ul>
+ <li>Declare: <a href="https://github.com/dmlc/tvm/blob/master/topi/python/topi/nn/depthwise_conv2d.py">https://github.com/dmlc/tvm/blob/master/topi/python/topi/nn/depthwise_conv2d.py</a></li>
+ <li>Schedule: <a href="https://github.com/dmlc/tvm/blob/master/topi/python/topi/cuda/depthwise_conv2d.py">https://github.com/dmlc/tvm/blob/master/topi/python/topi/cuda/depthwise_conv2d.py</a></li>
+ <li>Test: <a href="https://github.com/dmlc/tvm/blob/master/topi/recipe/conv/depthwise_conv2d_test.py">https://github.com/dmlc/tvm/blob/master/topi/recipe/conv/depthwise_conv2d_test.py</a></li>
+</ul>
+
+<h2 id="acknowledgements">Acknowledgements</h2>
+<p>The author has many thanks to Tianqi Chen for his helpful advice and inspiring discussion.</p>
+
+<h2 id="bio">Bio</h2>
+<p><a href="https://Huyuwei.github.io">Yuwei Hu</a> is an intern in <a href="http://tusimple.ai/">Tusimple</a>’s HPC group.
+He is experiencing a gap year after obtaining a bachelor’s degree in electrical engineering from Beihang University.</p>
+
+<h2 id="references">References</h2>
+<p>[1] <a href="https://arxiv.org/abs/1610.02357">Xception: Deep Learning with Depthwise Separable Convolutions</a></p>
+
+<p>[2] <a href="https://arxiv.org/abs/1704.04861">MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications</a></p>
+
+<p>[3] <a href="http://norvig.com/21-days.html#answers">Approximate timing for various operations on a typical PC</a></p>
+
+ </div>
+ </div>
+</div>
+</div>
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diff --git a/2017/10/06/nnvm-compiler-announcement.html b/2017/10/06/nnvm-compiler-announcement.html
new file mode 100644
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+++ b/2017/10/06/nnvm-compiler-announcement.html
@@ -0,0 +1,275 @@
+
+<!DOCTYPE html>
+<html lang="en">
+ <head>
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+ <title>NNVM Compiler: Open Compiler for AI Frameworks</title>
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+ <h1>NNVM Compiler: Open Compiler for AI Frameworks </h1>
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+ <time datetime="2017-10-06T08:30:00-07:00" itemprop="datePublished">
+ Oct 6, 2017
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+ <p style="text-align: center">Paul G. Allen School of Computer Science & Engineering, University of Washington</p>
+<p style="text-align: center">Amazon Web Service AI team</p>
+<p style="text-align: center">DMLC open-source community</p>
+
+<p>Deep learning has become ubiquitous and indispensable. We are seeing a rising need for deploying deep learning workloads on many kinds of platforms such as mobile phones, GPU, IoT devices and specialized accelerators. Last month, we announced TVM stack to close the gap between deep learning frameworks, and the performance- or efficiency-oriented hardware backends. TVM stack makes it easy to build an end to end compilation for a deep learning framework. However, we think it would ev [...]
+
+<p>Today, UW Allen school and AWS AI team, together with other contributors, are excited to announce the release of NNVM compiler, an open deep learning compiler to compile front-end framework workloads directly to hardware backends. We build it using the two-level intermediate representation(IR) in the TVM stack.
+The reader is welcome to refer to the <a href="http://www.tvmlang.org/2017/08/17/tvm-release-announcement.html">original TVM announcement</a> for more technical details about TVM stack. With the help of TVM stack, NNVM compiler can:</p>
+
+<ul>
+ <li>Represent and optimize the common deep learning workloads in high level graph IR</li>
+ <li>Transform the computation graph to minimize memory utilization, optimize data layout and fuse computation patterns for different hardware backends.</li>
+ <li>Present an end to end compilation pipeline from front-end deep learning frameworks to bare metal hardwares.</li>
+</ul>
+
+<p style="text-align: center"><img src="/images/nnvm/nnvm_compiler_stack.png" alt="image" width="612px" /></p>
+
+<p>The NNVM compiler can directly take models from deep learning frameworks such as Apache MXNet.
+It also support model exchange formats such as ONNX and CoreML. ONNX support enables NNVM to compile deep learning models from PyTorch, Caffe2 and CNTK.
+The CoreML frontend enables deployment of CoreML models to non-iOS devices.</p>
+
+<p style="text-align: center"><img src="/images/nnvm/nnvm_compiler_code.png" alt="image" width="712px" /></p>
+
+<h2 id="separation-of-optimization-and-deployment">Separation of Optimization and Deployment</h2>
+
+<p style="text-align: center"><img src="/images/nnvm/nnvm_deploy.png" alt="image" width="512px" /></p>
+
+<p>NNVM compiler applies graph level and tensor level optimizations and jointly optimize them to get the best performance. We take a different approach from existing deep learning frameworks, which packages the graph optimization with the deployment runtime. NNVM compiler adopts the conventional wisdom from compiler to separate the optimization from the actual deployment runtime. This approach offers substantial optimization but still keeps the runtime lightweight. The compiled module o [...]
+
+<h2 id="performance">Performance</h2>
+
+<p>NNVM compiler is still under active development, and we can expect more improvements to come, but we have started to see promising results.
+We benchmarked its performance and compared it against Apache MXNet on two typical hardware configurations: ARM CPU on Raspberry PI and Nvidia GPU on AWS. Despite the radical architecture difference between these two chips, we can use the same infrastructure and only need to change the schedule for each type of hardware.</p>
+
+<h3 id="nvidia-gpu">Nvidia GPU</h3>
+
+<p>GPU benchmarks and schedules are contributed by Leyuan Wang (AWS/UCDavis) and Yuwei Hu (TuSimple). We compared the NNVM compiler against Apache MXNet with CUDA8 and cuDNN7 as the backend on Nvidia K80. This is a very strong baseline, as Apache MXNet turns on auto-tuning to select the best kernel from CuDNN. We also used the optimized depthwise kernel in MXNet to optimize MobileNet workload.</p>
+
+<p style="text-align: center"><img src="/images/nnvm/nnvm_k80_result.png" alt="image" width="400px" /></p>
+
+<p>As can be seen, NNVM compiler generate code that outperforms Apache MXNet on K80. These improvements are due to the joint graph level and kernel level optimizations. It is worth noting that NNVM compiler generates all the optimized GPU kernels on its own without relying on external libraries like CuDNN.</p>
+
+<h3 id="raspberry-pi-3b">Raspberry Pi 3b</h3>
+
+<p>The Rasberry Pi compilation stack is contributed by Ziheng Jiang(AWS/FDU).
+We compared NNVM compiler against Apache MXNet with OpenBLAS and NNPack.
+We explored the setups to get the best performance out of MXNet: we turned on Winograd convolution in the NNPACK for 3x3 convolutions, enabled multi-threading and disabled the additional scheduler thread (so all threads are used by NNPack).</p>
+
+<p style="text-align: center"><img src="/images/nnvm/nnvm_rasp_result.png" alt="image" width="400px" /></p>
+
+<p>As can be seen, the code generated by NNVM compiler is two times faster on ResNet18.
+The gap on MobileNet is mainly due to lack of depthwise convolution in existing CPU DNN libraries. NNVM compiler takes benefit of direct generating efficient ARM code directly.</p>
+
+<h2 id="acknowledgement">Acknowledgement</h2>
+<p>This project wouldn’t become possible without our early contributors in the DMLC community.
+We would like to specially thank Yuwei Hu(TuSimple), Leyuan Wang(AWS/UCDavis), Joshua Z. Zhang(AWS)
+and Xingjian Shi(HKUST) for their early contributions to the project. We would also like to thank all the contributors
+to the TVM stack.</p>
+
+<p>We also learnt a lot from the following projects when building NNVM Compiler.</p>
+<ul>
+ <li><a href="https://github.com/Theano/Theano">Theano</a>: possibly the earliest compiler for deep learning</li>
+ <li><a href="https://github.com/halide/Halide">Halide</a>: TVM uses <a href="https://github.com/dmlc/HalideIR">HalideIR</a> as data structure for
+arithematic simplification and low level lowering. HalideIR is derived from Halide.
+We also learns from Halide when implementing the lowering pipeline in TVM.</li>
+ <li><a href="https://github.com/inducer/loopy">Loopy</a>: use of integer set analysis and its loop transformation primitives.</li>
+</ul>
+
+<h2 id="links">Links</h2>
+<ul>
+ <li>Github page of NNVM Compiler: <a href="https://github.com/dmlc/nnvm">https://github.com/dmlc/nnvm</a></li>
+ <li>Github page of TVM: <a href="https://github.com/dmlc/tvm">https://github.com/dmlc/tvm</a></li>
+ <li><a href="https://news.cs.washington.edu/2017/10/06/allen-school-and-aws-team-up-on-new-nnvm-compiler-for-deep-learning-frameworks/">UW Allen school blog about NNVM compiler</a></li>
+ <li><a href="https://aws.amazon.com/blogs/ai/introducing-nnvm-compiler-a-new-open-end-to-end-compiler-for-ai-frameworks/">AWS blogpost about NNVM compiler</a></li>
+</ul>
+
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diff --git a/2017/10/30/Bringing-AMDGPUs-to-TVM-Stack-and-NNVM-Compiler-with-ROCm.html b/2017/10/30/Bringing-AMDGPUs-to-TVM-Stack-and-NNVM-Compiler-with-ROCm.html
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+ <h1>Bringing AMDGPUs to TVM Stack and NNVM Compiler with ROCm </h1>
+ <p class="post-meta">
+ <time datetime="2017-10-30T00:00:00-07:00" itemprop="datePublished">
+ Oct 30, 2017
+ </time>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p style="text-align: center">Aditya Atluri, Advanced Micro Devices, Inc.</p>
+<p style="text-align: center">Masahiro Masuda, Ziosoft, Inc.</p>
+
+<p>We are pleased to announce a new GPU backend for TVM stack - ROCm backend for AMD GPUs. If you are not familiar with TVM, you can refer to <a href="http://tvmlang.org/2017/08/17/tvm-release-announcement.html">the earlier announcement</a> first. In short, TVM stack is an end to end compilation stack to deploy deep learning workloads to all hardware backends. Today’s announcement focuses on the code generator support for AMD GPUs. Specifically, we developed a new GPU code generator for [...]
+
+<p style="text-align: center"><img src="/images/rocm/tvm_rocm_overview.png" alt="image" width="90%" /></p>
+
+<p>TVM stack is developed by an open source community under Apache-2.0 License. ROCm backend support is done with the help from community. Aditya first implemented codegen and runtime. He was later joined by Masahiro. Masahiro’s full time job is not related to TVM or AMD GPUs. Nonetheless, TVM got him excited and he has been involved in fixing bugs, resolving all failing unittests, and adding math function support to codegen.</p>
+
+<h2 id="rocm-stack">ROCm stack</h2>
+
+<p>Radeon Open Compute is open-source initiative by AMD to leverage compute power of current and future generation GPUs. ROCm software stack is a great tool to express and run most commonly used GPU programming models and achieve peak performance. Not only ROCm is an open-source stack, it is an open stack, which means all the ISA and hardware features are well documented and programmable by developers. Developers can experiment with different programming models and try out multiple ways [...]
+
+<p>TVM leverages the open-source feature of ROCm stack by using LLVM AMDGPU backend code generator. TVM translates from its intermediate representation (IR) to LLVM intermediate representation. This is the place where ROCm stack open-source feature takes control. TVM’s LLVM AMDGPU CodeGen pass converts LLVM IR into GPU assembly and object code, which is later called to run the whole network or group of layers or single layer.</p>
+
+<p>On ROCm stack, there is no virtual ISA, you get what you ask for not less not more. Hence, one can schedule operations in a kernel at a granularity of a single instruction, without worrying about instruction reordering and other optimizations you do not ask for.</p>
+
+<h2 id="using-nnvm-compiler-with-rocm-backend">Using NNVM Compiler with ROCm backend</h2>
+
+<p>Thanks to TVM stack, we can directly compile models from popular deep learning frameworks such as MXNet and PyTorch into AMD GPU assembly using NNVM compiler, today. With ROCm backend, the generic workflow becomes as follows.</p>
+
+<p style="text-align: center"><img src="/images/rocm/rocm_workflow.png" alt="image" width="90%" /></p>
+
+<p>We have put together working examples of compiling models from MXNet and PyTorch with NNVM, and running them on AMD GPUs with ROCm backend. More frameworks are supported via the NNVM compiler stack. The repository is available <a href="https://github.com/ROCmSoftwarePlatform/nnvm-rocm">here</a>.</p>
+
+<p>The script <a href="https://github.com/ROCmSoftwarePlatform/nnvm-rocm/blob/master/mxnet_imagenet_inference.py">mxnet_imagenet_inference.py</a> demonstrates Imagenet inference on AMD GPUs with recently introduced MXNet-Gluon model. It does the following:</p>
+
+<ul>
+ <li>Loads Resnet 50 model from <a href="https://mxnet.incubator.apache.org/versions/master/api/python/gluon/model_zoo.html">the Gluon model zoo</a></li>
+ <li>Converts Gluon Resnet 50 model to NNVM graph format, using <code class="highlighter-rouge">nnvm.frontend.from_mxnet (...)</code></li>
+ <li>Compiles and executes the graph with ROCm backend</li>
+</ul>
+
+<p>The example comes with an image of the following cat.</p>
+
+<p style="text-align: center"><img src="/images/rocm/cat.png" alt="image" /></p>
+
+<p>Running our network, it predicts this image as “tigar cat”, among 1000 categories.</p>
+
+<figure class="highlight"><pre><code class="language-plain" data-lang="plain">$ python mxnet_imagenet_inference.py
+Testing model resnet50_v1
+x (1, 3, 224, 224)
+TVM prediction top-1: 282 tiger cat</code></pre></figure>
+
+<p>The script <a href="https://github.com/ROCmSoftwarePlatform/nnvm-rocm/blob/master/advanced_superres_onnx.py">advanced_superres_onnx.py</a> gives an example of loading a model trained with PyTorch. The model is stored in the <a href="https://onnx.ai/">ONNX</a> format. In this example, our network takes an low resolution image as input, and outputs a 4x high resolution image. We refer the details of a problem setup and the network architecture to <a href="https://arxiv.org/abs/1609.0480 [...]
+
+<p>In order to use models in the ONNX format with NNVM, we first use <a href="https://github.com/onnx/onnx">the ONNX library</a> to load the ONNX model into the Protocol buffer object. We can then use <code class="highlighter-rouge">nnvm.frontend.from_onnx(...)</code> to obtain an equivalent NNVM graph. With a NNVM graph in hand, we can follow the generic workflow of compilation and graph execution outlined above.</p>
+
+<p style="text-align: center"><img src="/images/rocm/butterfly.png" alt="image" /></p>
+
+<p>The input to the network is a 64 x 64 image on the left, and it outputs a 256 x 256 image on the right. On the middle is a 256 x 256 image obtained simply by resizing the input image with bicubic interpolation. The network outputs an image of far better quality.</p>
+
+<p>The input images are taken from the original paper, and they are available <a href="https://twitter.app.box.com/s/lcue6vlrd01ljkdtdkhmfvk7vtjhetog">here</a>.</p>
+
+<h2 id="a-note-on-performance">A Note on performance</h2>
+
+<p>The current support on ROCm focuses on the functionality coverage. We have already seen promising performance results by simply adopting existing TVM schedules for CUDA backend. For example, you can try running <a href="https://github.com/dmlc/tvm/blob/master/topi/recipe/gemm/cuda_gemm_square.py">the gemm test script</a> in the TVM repository and see the result. For two types of cards we tested, the current gemm recipe for square matrix multiplication (not yet specifically optimized f [...]
+This is already a promising start, as it is very hard to optimize performance to get to peak and we
+did not yet apply AMD GPU specific optimizations.
+We are starting to look at performance optimization and we expect more improvement to come.</p>
+
+<h2 id="walkthrough-of-rocm-backend">Walkthrough of ROCm backend</h2>
+
+<p>In the following part of this article we focus on explaining how to use ROCm backend when working with TVM directly. All you need to do is to build your TVM function under the target “rocm” and create a runtime context for it. Here, we show an example of ROCm backend usage, following ‘Vector Add Example’ in TVM’s <a href="http://docs.tvmlang.org/tutorials/get_started.html#vector-add-example">getting started tutorial</a>.</p>
+
+<p>We start by setting up a compute operation and a schedule for the vector add kernel. This step is independent of a backend.</p>
+
+<figure class="highlight"><pre><code class="language-python" data-lang="python"><span class="kn">from</span> <span class="nn">__future__</span> <span class="kn">import</span> <span class="n">absolute_import</span><span class="p">,</span> <span class="n">print_function</span>
+<span class="kn">import</span> <span class="nn">tvm</span>
+<span class="kn">import</span> <span class="nn">numpy</span> <span class="k">as</span> <span class="n">np</span>
+
+<span class="n">n</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">var</span><span class="p">(</span><span class="s">"n"</span><span class="p">)</span>
+<span class="n">A</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><span class="n">n</span><span class="p">,),</span> <span class="n">name</span><span class="o">=</span><span class="s">'A'</span><span class="p">)</span>
+<span class="n">B</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><span class="n">n</span><span class="p">,),</span> <span class="n">name</span><span class="o">=</span><span class="s">'B'</span><span class="p">)</span>
+<span class="n">C</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">(</span><span class="n">A</span><span class="o">.</span><span class="n">shape</span><span class="p">,</span> <span class="k">lambda</span> <span class="n">i</span><span class="p">:</span> <span class="n">A</span><span class="p">[</span><span class="n">i</span><span class="p">]</span> <span class="o">+</span> <span class="n">B</span><span class= [...]
+<span class="n">s</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">create_schedule</span><span class="p">(</span><span class="n">C</span><span class="o">.</span><span class="n">op</span><span class="p">)</span>
+<span class="n">bx</span><span class="p">,</span> <span class="n">tx</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">C</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">C</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span><span class="p">[</span><span class="mi">0</span><span class="p">],</span> <span class="n">fact [...]
+<span class="n">s</span><span class="p">[</span><span class="n">C</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">bx</span><span class="p">,</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"blockIdx.x"</span><span class="p">))</span>
+<span class="n">s</span><span class="p">[</span><span class="n">C</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">tx</span><span class="p">,</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"threadIdx.x"</span><span class="p">))</span></code></pre></figure>
+
+<p>Next, to use ROCm backend we build our kernel under “rocm” target. This will cause TVM to use our new code generator. We also need a runtime context for ROCm backend.</p>
+
+<figure class="highlight"><pre><code class="language-python" data-lang="python"><span class="n">target</span> <span class="o">=</span> <span class="s">"rocm"</span>
+<span class="n">fadd_rocm</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">build</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="p">[</span><span class="n">A</span><span class="p">,</span> <span class="n">B</span><span class="p">,</span> <span class="n">C</span><span class="p">],</span> <span class="n">target</span><span class="p">,</span> <span class="n">target_host</span><span class="o">=</span [...]
+<span class="n">ctx</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">rocm</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span></code></pre></figure>
+
+<p>After building the kernel and setting up a runtime context, we can launch our vector add kernel.</p>
+
+<figure class="highlight"><pre><code class="language-python" data-lang="python"><span class="n">n</span> <span class="o">=</span> <span class="mi">1024</span>
+<span class="n">a</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">array</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</span><span class="n">uniform</span><span class="p">(</span><span class="n">size</span><span class="o">=</span><span class="n">n</span><span class="p">)</span><span class="o">.</span><span class= [...]
+<span class="n">b</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">array</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</span><span class="n">uniform</span><span class="p">(</span><span class="n">size</span><span class="o">=</span><span class="n">n</span><span class="p">)</span><span class="o">.</span><span class= [...]
+<span class="n">c</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">array</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">zeros</span><span class="p">(</span><span class="n">n</span><span class="p">,</span> <span class="n">dtype</span><span class="o">=</span><span class="n">C</span><span class="o">.</span><span class="n">dtype</span><span class=" [...]
+
+<span class="n">fadd_rocm</span><span class="p">(</span><span class="n">a</span><span class="p">,</span> <span class="n">b</span><span class="p">,</span> <span class="n">c</span><span class="p">)</span>
+<span class="n">np</span><span class="o">.</span><span class="n">testing</span><span class="o">.</span><span class="n">assert_allclose</span><span class="p">(</span><span class="n">c</span><span class="o">.</span><span class="n">asnumpy</span><span class="p">(),</span> <span class="n">a</span><span class="o">.</span><span class="n">asnumpy</span><span class="p">()</span> <span class="o">+</span> <span class="n">b</span><span class="o">.</span><span class="n">asnumpy</span><span class="p" [...]
+
+<p>We can view LLVM IR that TVM generates in the following way:</p>
+
+<figure class="highlight"><pre><code class="language-python" data-lang="python"><span class="n">dev_module</span> <span class="o">=</span> <span class="n">fadd_rocm</span><span class="o">.</span><span class="n">imported_modules</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
+<span class="k">print</span><span class="p">(</span><span class="n">dev_module</span><span class="o">.</span><span class="n">get_source</span><span class="p">(</span><span class="s">"llvm"</span><span class="p">))</span></code></pre></figure>
+
+<p>You should see something like this:</p>
+
+<figure class="highlight"><pre><code class="language-llvm" data-lang="llvm"><span class="c1">; ModuleID = 'myadd__kernel0'</span>
+<span class="err">source_filename</span> <span class="p">=</span> <span class="s">"myadd__kernel0"</span>
+<span class="k">target</span> <span class="k">datalayout</span> <span class="p">=</span> <span class="s">"e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"</span>
+<span class="k">target</span> <span class="k">triple</span> <span class="p">=</span> <span class="s">"amdgcn-amd-amdhsa-hcc"</span>
+
+
+<span class="c1">; Function Attrs: nounwind</span>
+<span class="k">define</span> <span class="k">dllexport</span> <span class="err">amdgpu_kernel</span> <span class="kt">void</span> <span class="vg">@myadd__kernel0</span><span class="p">(</span><span class="kt">float</span> <span class="k">addrspace</span><span class="p">(</span><span class="m">1</span><span class="p">)*</span> <span class="k">noalias</span> <span class="k">nocapture</span><span class="p">,</span> <span class="kt">float</span> <span class="k">addrspace</span><span class= [...]
+<span class="nl">entry:</span>
+ <span class="nv">%4</span> <span class="p">=</span> <span class="k">tail</span> <span class="k">call</span> <span class="kt">i32</span> <span class="vg">@llvm.amdgcn.workgroup.id.x</span><span class="p">()</span>
+ <span class="nv">%5</span> <span class="p">=</span> <span class="k">tail</span> <span class="k">call</span> <span class="kt">i32</span> <span class="vg">@llvm.amdgcn.workitem.id.x</span><span class="p">()</span>
+ <span class="nv">%6</span> <span class="p">=</span> <span class="k">add</span> <span class="k">nsw</span> <span class="kt">i32</span> <span class="nv">%3</span><span class="p">,</span> <span class="m">-127</span>
+ <span class="nv">%7</span> <span class="p">=</span> <span class="k">ashr</span> <span class="kt">i32</span> <span class="nv">%6</span><span class="p">,</span> <span class="m">6</span>
+ <span class="nv">%8</span> <span class="p">=</span> <span class="k">icmp</span> <span class="k">slt</span> <span class="kt">i32</span> <span class="nv">%4</span><span class="p">,</span> <span class="nv">%7</span>
+ <span class="k">br</span> <span class="kt">i1</span> <span class="nv">%8</span><span class="p">,</span> <span class="kt">label</span> <span class="nv">%if_then</span><span class="p">,</span> <span class="kt">label</span> <span class="nv">%if_else</span>
+
+
+<span class="nl">if_then:</span> <span class="c1">; preds = %entry</span>
+ <span class="nv">%9</span> <span class="p">=</span> <span class="k">shl</span> <span class="k">nsw</span> <span class="kt">i32</span> <span class="nv">%4</span><span class="p">,</span> <span class="m">6</span>
+ <span class="k">br</span> <span class="kt">label</span> <span class="nv">%if_end.sink.split</span>
+
+
+<span class="nl">if_end.sink.split:</span> <span class="c1">; preds = %if_else, %if_then</span>
+ <span class="nv">%.pre-phi</span> <span class="p">=</span> <span class="k">phi</span> <span class="kt">i32</span> <span class="p">[</span> <span class="nv">%21</span><span class="p">,</span> <span class="nv">%if_else</span> <span class="p">],</span> <span class="p">[</span> <span class="nv">%9</span><span class="p">,</span> <span class="nv">%if_then</span> <span class="p">]</span>
+ <span class="nv">%10</span> <span class="p">=</span> <span class="k">add</span> <span class="k">nsw</span> <span class="kt">i32</span> <span class="nv">%.pre-phi</span><span class="p">,</span> <span class="nv">%5</span>
+ <span class="nv">%11</span> <span class="p">=</span> <span class="k">add</span> <span class="k">nsw</span> <span class="kt">i32</span> <span class="nv">%.pre-phi</span><span class="p">,</span> <span class="nv">%5</span>
+ <span class="nv">%12</span> <span class="p">=</span> <span class="k">sext</span> <span class="kt">i32</span> <span class="nv">%11</span> <span class="k">to</span> <span class="kt">i64</span>
+ <span class="nv">%13</span> <span class="p">=</span> <span class="k">getelementptr</span> <span class="k">inbounds</span> <span class="kt">float</span><span class="p">,</span> <span class="kt">float</span> <span class="k">addrspace</span><span class="p">(</span><span class="m">1</span><span class="p">)*</span> <span class="nv">%2</span><span class="p">,</span> <span class="kt">i64</span> <span class="nv">%12</span>
+ <span class="nv">%14</span> <span class="p">=</span> <span class="k">load</span> <span class="kt">float</span><span class="p">,</span> <span class="kt">float</span> <span class="k">addrspace</span><span class="p">(</span><span class="m">1</span><span class="p">)*</span> <span class="nv">%13</span><span class="p">,</span> <span class="k">align</span> <span class="m">4</span><span class="p">,</span> <span class="nv">!tbaa</span> <span class="nv">!2</span>
+ <span class="nv">%15</span> <span class="p">=</span> <span class="k">getelementptr</span> <span class="k">inbounds</span> <span class="kt">float</span><span class="p">,</span> <span class="kt">float</span> <span class="k">addrspace</span><span class="p">(</span><span class="m">1</span><span class="p">)*</span> <span class="nv">%1</span><span class="p">,</span> <span class="kt">i64</span> <span class="nv">%12</span>
+ <span class="nv">%16</span> <span class="p">=</span> <span class="k">load</span> <span class="kt">float</span><span class="p">,</span> <span class="kt">float</span> <span class="k">addrspace</span><span class="p">(</span><span class="m">1</span><span class="p">)*</span> <span class="nv">%15</span><span class="p">,</span> <span class="k">align</span> <span class="m">4</span><span class="p">,</span> <span class="nv">!tbaa</span> <span class="nv">!6</span>
+ <span class="nv">%17</span> <span class="p">=</span> <span class="k">fadd</span> <span class="kt">float</span> <span class="nv">%14</span><span class="p">,</span> <span class="nv">%16</span>
+ <span class="nv">%18</span> <span class="p">=</span> <span class="k">sext</span> <span class="kt">i32</span> <span class="nv">%10</span> <span class="k">to</span> <span class="kt">i64</span>
+ <span class="nv">%19</span> <span class="p">=</span> <span class="k">getelementptr</span> <span class="k">inbounds</span> <span class="kt">float</span><span class="p">,</span> <span class="kt">float</span> <span class="k">addrspace</span><span class="p">(</span><span class="m">1</span><span class="p">)*</span> <span class="nv">%0</span><span class="p">,</span> <span class="kt">i64</span> <span class="nv">%18</span>
+ <span class="k">store</span> <span class="kt">float</span> <span class="nv">%17</span><span class="p">,</span> <span class="kt">float</span> <span class="k">addrspace</span><span class="p">(</span><span class="m">1</span><span class="p">)*</span> <span class="nv">%19</span><span class="p">,</span> <span class="k">align</span> <span class="m">4</span><span class="p">,</span> <span class="nv">!tbaa</span> <span class="nv">!9</span>
+ <span class="k">br</span> <span class="kt">label</span> <span class="nv">%if_end</span>
+
+
+<span class="nl">if_end:</span> <span class="c1">; preds = %if_end.sink.split, %if_else</span>
+ <span class="k">ret</span> <span class="kt">void</span>
+
+
+<span class="nl">if_else:</span> <span class="c1">; preds = %entry</span>
+ <span class="nv">%20</span> <span class="p">=</span> <span class="k">sub</span> <span class="k">nsw</span> <span class="kt">i32</span> <span class="nv">%3</span><span class="p">,</span> <span class="nv">%5</span>
+ <span class="nv">%21</span> <span class="p">=</span> <span class="k">shl</span> <span class="k">nsw</span> <span class="kt">i32</span> <span class="nv">%4</span><span class="p">,</span> <span class="m">6</span>
+ <span class="nv">%22</span> <span class="p">=</span> <span class="k">icmp</span> <span class="k">slt</span> <span class="kt">i32</span> <span class="nv">%21</span><span class="p">,</span> <span class="nv">%20</span>
+ <span class="k">br</span> <span class="kt">i1</span> <span class="nv">%22</span><span class="p">,</span> <span class="kt">label</span> <span class="nv">%if_end.sink.split</span><span class="p">,</span> <span class="kt">label</span> <span class="nv">%if_end</span><span class="p">,</span> <span class="nv">!prof</span> <span class="nv">!12</span>
+<span class="p">}</span></code></pre></figure>
+
+<p>We can also view GPU assembly that ROCm backend generates. This is the real code that runs on your GPU.</p>
+
+<figure class="highlight"><pre><code class="language-python" data-lang="python"><span class="k">print</span><span class="p">(</span><span class="n">dev_module</span><span class="o">.</span><span class="n">get_source</span><span class="p">(</span><span class="s">"asm"</span><span class="p">))</span></code></pre></figure>
+
+<p>The assembly should look something like this, omitting unnecessary details:</p>
+
+<figure class="highlight"><pre><code class="language-plain" data-lang="plain"> s_load_dword s1, s[4:5], 0x18
+ v_mov_b32_e32 v2, -1
+ v_mov_b32_e32 v1, 0
+ s_waitcnt lgkmcnt(0)
+ s_add_i32 s0, s1, 0xffffff81
+ s_ashr_i32 s0, s0, 6
+ s_cmp_ge_i32 s6, s0
+ s_cbranch_scc0 BB0_2
+ v_sub_i32_e32 v1, vcc, s1, v0
+ s_lshl_b32 s0, s6, 6
+ v_cmp_lt_i32_e32 vcc, s0, v1
+ v_mov_b32_e32 v2, 0
+ v_cndmask_b32_e64 v1, 0, -1, vcc
+BB0_2:
+ v_cmp_ne_u32_e32 vcc, 0, v2
+ v_cndmask_b32_e64 v2, 0, 1, vcc
+ v_cmp_ne_u32_e32 vcc, 1, v2
+ s_and_b64 vcc, exec, vcc
+ s_cbranch_vccnz BB0_4
+ s_lshl_b32 s0, s6, 6
+ v_mov_b32_e32 v1, -1
+BB0_4:
+ v_cmp_ne_u32_e32 vcc, 0, v1
+ v_mov_b32_e32 v1, s0
+ s_and_saveexec_b64 s[0:1], vcc
+ s_xor_b64 s[0:1], exec, s[0:1]
+ s_cbranch_execz BB0_6
+BB0_5:
+ s_load_dwordx2 s[2:3], s[4:5], 0x0
+ s_load_dwordx2 s[6:7], s[4:5], 0x8
+ v_add_i32_e32 v0, vcc, v1, v0
+ s_load_dwordx2 s[4:5], s[4:5], 0x10
+ v_ashrrev_i32_e32 v1, 31, v0
+ v_lshlrev_b64 v[0:1], 2, v[0:1]
+ s_waitcnt lgkmcnt(0)
+ v_add_i32_e32 v2, vcc, s4, v0
+ v_mov_b32_e32 v3, s5
+ v_addc_u32_e32 v3, vcc, v3, v1, vcc
+ flat_load_dword v2, v[2:3]
+ v_add_i32_e32 v4, vcc, s6, v0
+ v_mov_b32_e32 v3, s7
+ v_addc_u32_e32 v5, vcc, v3, v1, vcc
+ flat_load_dword v4, v[4:5]
+ v_mov_b32_e32 v3, s3
+ v_add_i32_e32 v0, vcc, s2, v0
+ v_addc_u32_e32 v1, vcc, v3, v1, vcc
+ s_waitcnt vmcnt(0) lgkmcnt(0)
+ v_add_f32_e32 v2, v2, v4
+ flat_store_dword v[0:1], v2
+BB0_6:
+ s_or_b64 exec, exec, s[0:1]
+ s_endpgm</code></pre></figure>
+
+<p>Links</p>
+
+<ul>
+ <li>Github page of NNVM Compiler: <a href="https://github.com/dmlc/nnvm">https://github.com/dmlc/nnvm</a></li>
+ <li>Github page of TVM: <a href="https://github.com/dmlc/tvm">https://github.com/dmlc/tvm</a></li>
+ <li>Examples of ROCm backend with NNVM: <a href="https://github.com/ROCmSoftwarePlatform/nnvm-rocm">https://github.com/ROCmSoftwarePlatform/nnvm-rocm</a></li>
+</ul>
+
+ </div>
+ </div>
+</div>
+</div>
+
+
+
+
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+
+
+
+ <div class="container">
+
+ <footer class="small">
+ Apache TVM is an effort undergoing incubation at The Apache Software Foundation (ASF),
+ sponsored by the <i>Apache Incubator</i>. Incubation is required
+ of all newly accepted projects until a further review indicates that the infrastructure,
+ communications, and decision making process have stabilized in a manner consistent with other
+ successful ASF projects. While incubation status is not necessarily a reflection of the completeness
+ or stability of the code, it does indicate that the project has yet to be fully endorsed by the ASF.
+
+ Copyright © 2020 The Apache Software Foundation. Apache TVM, Apache,
+ the Apache feather, and the Apache TVM project logo are either trademarks or registered trademarks of the Apache Software Foundation.
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diff --git a/2017/11/08/android-rpc-introduction.html b/2017/11/08/android-rpc-introduction.html
new file mode 100644
index 0000000..f4b581f
--- /dev/null
+++ b/2017/11/08/android-rpc-introduction.html
@@ -0,0 +1,424 @@
+
+<!DOCTYPE html>
+<html lang="en">
+ <head>
+ <meta charset="utf-8">
+ <title>Remote Profile and Test Deep Learning Cross Compilation on Mobile Phones with TVM RPC</title>
+
+ <meta name="author" content="">
+
+ <!-- Le HTML5 shim, for IE6-8 support of HTML elements -->
+ <!--[if lt IE 9]>
+ <script src="http://html5shim.googlecode.com/svn/trunk/html5.js"></script>
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+
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+
+ <!-- Le fav and touch icons -->
+ <!-- Update these with your own images
+ <link rel="shortcut icon" href="images/logo/tvm-logo.png">
+ <link rel="shortcut icon" href="images/logo/tvm-logo.png">
+ -->
+ <link href="/images/logo/tvm-logo-square.png" rel="icon" type="image/png"/>
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+ <div class="span14">
+ <h1>Remote Profile and Test Deep Learning Cross Compilation on Mobile Phones with TVM RPC </h1>
+ <p class="post-meta">
+ <time datetime="2017-11-08T00:00:00-08:00" itemprop="datePublished">
+ Nov 8, 2017
+ </time>
+
+ • <span itemprop="author" itemscope itemtype="http://schema.org/Person">
+ <span itemprop="name">Yizhi Liu</span>
+ </span>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p>TVM stack is an end to end compilation stack to deploy deep learning workloads to all hardware backends.
+Thanks to the NNVM compiler support of TVM stack, we can now directly compile descriptions from deep learning frameworks and compile them to bare metal code.
+An impressive feature OF tvm is its ability to deploy computation workloads on different platforms, such as GPUs and mobile phones (will support more hardward backends).</p>
+
+<p>However, when we want to test and profile cross compilation, it is hard to test different computation workloads on a heterogeneous device such as raspberry pi or a mobile phone.
+In order to optimize a computation task, one has to edit the code on the development PC, compile, deploy to the device, test, then modify the codes again to see whether it accelerates. The workflow looks like,</p>
+
+<p style="text-align: center"><img src="/images/android_rpc/flow1.png" alt="image" width="50%" /></p>
+
+<p>Is there any way to speed up this process?</p>
+
+<p>Today we introduce an approach to deploy and test TVM workloads on Android Phones. We develop a TVM runtime for Java and build an Android APP upon it. The Android APP takes shared library as input and runs compiled functions on the mobile phone. Thus our workflow simplifies to,</p>
+
+<p style="text-align: center"><img src="/images/android_rpc/flow2.png" alt="image" width="50%" /></p>
+
+<p>With the help of the TVM RPC, one can build TVM functions and NDArrays on a remote device. The ability to cross-compile to different platforms makes it easy to develop on one platform and test on another.</p>
+
+<p>The process is illustrated as following:</p>
+
+<p style="text-align: center"><img src="/images/android_rpc/arch.png" alt="image" width="70%" /></p>
+
+<h2 id="run-tvm-app-on-android-phone">Run TVM APP on Android Phone</h2>
+
+<p>You can find Android RPC APP in <a href="https://github.com/dmlc/tvm/tree/master/apps/android_rpc">apps/android_rpc</a>. Please follow the instruction to build for your Android device. Once the APK is built, sign it using <code class="highlighter-rouge">apps/android_rpc/dev_tools</code> and install it on the phone. The APP looks like:</p>
+
+<p style="text-align: center"><img src="/images/android_rpc/app.png" alt="image" width="25%" />
+<img src="/images/android_rpc/app_error.png" alt="image" width="25%" /></p>
+
+<p>Usually we cannot start a standalone server on mobile phone, instead we start an proxy server and use our app to connect.</p>
+
+<div class="language-bash highlighter-rouge"><div class="highlight"><pre class="highlight"><code>python <span class="nt">-m</span> tvm.exec.rpc_proxy
+</code></pre></div></div>
+
+<h2 id="create-ndarray-on-the-phone">Create NDArray on the Phone</h2>
+
+<p>Now we can connect to the proxy server from the laptop:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="kn">from</span> <span class="nn">tvm.contrib</span> <span class="kn">import</span> <span class="n">rpc</span>
+<span class="n">remote</span> <span class="o">=</span> <span class="n">rpc</span><span class="o">.</span><span class="n">connect</span><span class="p">(</span><span class="s">"0.0.0.0"</span><span class="p">,</span> <span class="mi">9090</span><span class="p">,</span> <span class="n">key</span><span class="o">=</span><span class="s">"android"</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>This will give us a handler <code class="highlighter-rouge">remote</code> which we can use to communicate with the mobile phone. For instance, the following lines create a 1024x1024 matrix on phone’s GPU:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">A</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">array</span><span class="p">(</span>
+ <span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</span><span class="n">uniform</span><span class="p">(</span><span class="n">size</span><span class="o">=</span><span class="p">(</span><span class="mi">1024</span><span class="p">,</span> <span class="mi">1024</span><span class="p">))</span><span class="o">.</span><span class="n">astype</span><span class="p">(</span><span class="n">dtype</span><span class="p">),</span>
+ <span class="n">ctx</span> <span class="o">=</span> <span class="n">remote</span><span class="o">.</span><span class="n">cl</span><span class="p">(</span><span class="mi">0</span><span class="p">))</span>
+</code></pre></div></div>
+
+<p>When <code class="highlighter-rouge">A.asnumpy()</code> is called from the laptop, the matrix <code class="highlighter-rouge">A </code>will be copied to phone’s RAM and then transfer to the laptop through the proxy server. The TVM RPC interface is transparent to users.</p>
+
+<h2 id="gemm-matrix-multiplication-on-the-phone">GEMM (Matrix Multiplication) on the Phone</h2>
+
+<p>Now we are going to introduce how to test matrix multiplication on an Android phone. First let’s define the very simple GEMM schedule:</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="kn">import</span> <span class="nn">tvm</span>
+<span class="k">def</span> <span class="nf">gemm</span><span class="p">(</span><span class="n">N</span><span class="p">,</span> <span class="n">bn</span><span class="p">):</span>
+ <span class="n">A</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><span class="n">N</span><span class="p">,</span> <span class="n">N</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'A'</span><span class="p">)</span>
+ <span class="n">B</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><span class="n">N</span><span class="p">,</span> <span class="n">N</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'B'</span><span class="p">)</span>
+ <span class="n">k</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">N</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'k'</span><span class="p">)</span>
+
+ <span class="n">C</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">(</span>
+ <span class="p">(</span><span class="n">N</span><span class="p">,</span> <span class="n">N</span><span class="p">),</span>
+ <span class="k">lambda</span> <span class="n">ii</span><span class="p">,</span> <span class="n">jj</span><span class="p">:</span> <span class="n">tvm</span><span class="o">.</span><span class="nb">sum</span><span class="p">(</span><span class="n">A</span><span class="p">[</span><span class="n">ii</span><span class="p">,</span> <span class="n">k</span><span class="p">]</span> <span class="o">*</span> <span class="n">B</span><span class="p">[</span><span class="n">k</span><span cla [...]
+ <span class="n">name</span><span class="o">=</span><span class="s">'C'</span><span class="p">)</span>
+
+ <span class="n">s</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">create_schedule</span><span class="p">(</span><span class="n">C</span><span class="o">.</span><span class="n">op</span><span class="p">)</span>
+
+ <span class="n">block_x</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"blockIdx.x"</span><span class="p">)</span>
+ <span class="n">thread_x</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"threadIdx.x"</span><span class="p">)</span>
+
+ <span class="n">bo</span><span class="p">,</span> <span class="n">bi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">C</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">C</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span><span class="p">[</span><span class="mi">0</span><span class="p">],</span> <span class="n"> [...]
+ <span class="n">to</span><span class="p">,</span> <span class="n">ti</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">C</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">C</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span><span class="p">[</span><span class="mi">1</span><span class="p">],</span> <span class="n"> [...]
+ <span class="n">s</span><span class="p">[</span><span class="n">C</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">bi</span><span class="p">,</span> <span class="n">block_x</span><span class="p">)</span>
+ <span class="n">s</span><span class="p">[</span><span class="n">C</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">ti</span><span class="p">,</span> <span class="n">thread_x</span><span class="p">)</span>
+
+ <span class="k">print</span><span class="p">(</span><span class="n">tvm</span><span class="o">.</span><span class="n">lower</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="p">[</span><span class="n">A</span><span class="p">,</span> <span class="n">B</span><span class="p">,</span> <span class="n">C</span><span class="p">],</span> <span class="n">simple_mode</span><span class="o">=</span><span class="bp">True</span><span class="p">))</span>
+
+ <span class="k">return</span> <span class="n">tvm</span><span class="o">.</span><span class="n">build</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="p">[</span><span class="n">A</span><span class="p">,</span> <span class="n">B</span><span class="p">,</span> <span class="n">C</span><span class="p">],</span>
+ <span class="s">"opencl"</span><span class="p">,</span>
+ <span class="n">target_host</span><span class="o">=</span><span class="s">"llvm -target=arm64-linux-android"</span><span class="p">,</span>
+ <span class="n">name</span><span class="o">=</span><span class="s">"gemm_gpu"</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>There’s nothing special except the last line. Here we set the target to ‘opencl’ since this is the computation language which our Mali GPU supports. Note that we set <code class="highlighter-rouge">target_host</code> to ‘<code class="highlighter-rouge">llvm -target=arm64-linux-android</code>’, it depends on what architecture your Android Phone is. We tested on Samsung Galaxy S6 Edge, which has a Mali-T760 GPU. Here is the CPU info for this phone,</p>
+
+<div class="language-bash highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="nv">$ </span>adb shell
+shell@zenltechn:/ <span class="nv">$ </span><span class="nb">cat</span> /proc/cpuinfo
+Processor : AArch64 Processor rev 2 <span class="o">(</span>aarch64<span class="o">)</span>
+processor : 0
+processor : 1
+processor : 2
+processor : 3
+processor : 4
+processor : 5
+processor : 6
+processor : 7
+Features : fp asimd aes pmull sha1 sha2 crc32
+CPU implementer : 0x41
+CPU architecture: AArch64
+CPU variant : 0x0
+CPU part : 0xd03
+CPU revision : 2
+
+Hardware : SAMSUNG Exynos7420
+</code></pre></div></div>
+
+<p>Please refer to <a href="https://clang.llvm.org/docs/CrossCompilation.html#target-triple">target triple</a> to learn the compile options for LLVM.</p>
+
+<p>We use <code class="highlighter-rouge">tvm.contrib.ndk</code> to build the shared library for the Android system,</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="kn">from</span> <span class="nn">tvm.contrib</span> <span class="kn">import</span> <span class="n">rpc</span><span class="p">,</span> <span class="n">util</span><span class="p">,</span> <span class="n">ndk</span>
+<span class="n">N</span> <span class="o">=</span> <span class="mi">1024</span>
+<span class="n">f</span> <span class="o">=</span> <span class="n">gemm</span><span class="p">(</span><span class="n">N</span><span class="p">,</span> <span class="n">bn</span> <span class="o">=</span> <span class="mi">256</span><span class="p">)</span>
+<span class="n">temp</span> <span class="o">=</span> <span class="n">util</span><span class="o">.</span><span class="n">tempdir</span><span class="p">()</span>
+<span class="n">path_dso</span> <span class="o">=</span> <span class="n">temp</span><span class="o">.</span><span class="n">relpath</span><span class="p">(</span><span class="s">"gemm_gpu.so"</span><span class="p">)</span>
+<span class="n">f</span><span class="o">.</span><span class="n">export_library</span><span class="p">(</span><span class="n">path_dso</span><span class="p">,</span> <span class="n">ndk</span><span class="o">.</span><span class="n">create_shared</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p><code class="highlighter-rouge">ndk.create_shared</code> reads the environment variable <code class="highlighter-rouge">TVM_NDK_CC</code> to find the compiler & linker for the Android device. We can easily use NDK to generate standalone toolchain for our device. For example, the following commands generate standalone compilers and linkers for ARM64 Android devices.</p>
+
+<div class="language-bash highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="nb">cd</span> /opt/android-ndk/build/tools/
+./make-standalone-toolchain.sh <span class="nt">--platform</span><span class="o">=</span>android-24 <span class="nt">--use-llvm</span> <span class="nt">--arch</span><span class="o">=</span>arm64 <span class="nt">--install-dir</span><span class="o">=</span>/opt/android-toolchain-arm64
+</code></pre></div></div>
+
+<p>If everything goes right, we’ve got a shared library ‘gemm_gpu.so’. Now let’s upload it to the mobile phone, make the phone load the module and get a remote handler,</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">remote</span> <span class="o">=</span> <span class="n">rpc</span><span class="o">.</span><span class="n">connect</span><span class="p">(</span><span class="s">"0.0.0.0"</span><span class="p">,</span> <span class="mi">9090</span><span class="p">,</span> <span class="n">key</span><span class="o">=</span><span class="s">"android"</span><span class="p">)</span>
+
+<span class="n">remote</span><span class="o">.</span><span class="n">upload</span><span class="p">(</span><span class="n">path_dso</span><span class="p">)</span>
+<span class="n">f</span> <span class="o">=</span> <span class="n">remote</span><span class="o">.</span><span class="n">load_module</span><span class="p">(</span><span class="s">"gemm_gpu.so"</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>Create the remote arrays and print the running time,</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">ctx</span> <span class="o">=</span> <span class="n">remote</span><span class="o">.</span><span class="n">cl</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span>
+
+<span class="kn">import</span> <span class="nn">numpy</span> <span class="k">as</span> <span class="n">np</span>
+<span class="n">a_np</span> <span class="o">=</span> <span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</span><span class="n">uniform</span><span class="p">(</span><span class="n">size</span><span class="o">=</span><span class="p">(</span><span class="n">N</span><span class="p">,</span> <span class="n">N</span><span class="p">))</span><span class="o">.</span><span class="n">astype</span><span class="p">(</span><span class="s">"float32"</span>< [...]
+<span class="n">b_np</span> <span class="o">=</span> <span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</span><span class="n">uniform</span><span class="p">(</span><span class="n">size</span><span class="o">=</span><span class="p">(</span><span class="n">N</span><span class="p">,</span> <span class="n">N</span><span class="p">))</span><span class="o">.</span><span class="n">astype</span><span class="p">(</span><span class="s">"float32"</span>< [...]
+
+<span class="n">a</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">array</span><span class="p">(</span><span class="n">a_np</span><span class="p">,</span> <span class="n">ctx</span><span class="p">)</span>
+<span class="n">b</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">array</span><span class="p">(</span><span class="n">b_np</span><span class="p">,</span> <span class="n">ctx</span><span class="p">)</span>
+<span class="n">c</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">array</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">zeros</span><span class="p">((</span><span class="n">N</span><span class="p">,</span> <span class="n">N</span><span class="p">),</span> <span class="n">dtype</span><span class="o">=</span><span class="s">"float32"</span><span [...]
+
+<span class="n">time_f</span> <span class="o">=</span> <span class="n">f</span><span class="o">.</span><span class="n">time_evaluator</span><span class="p">(</span><span class="n">f</span><span class="o">.</span><span class="n">entry_name</span><span class="p">,</span> <span class="n">ctx</span><span class="p">,</span> <span class="n">number</span><span class="o">=</span><span class="mi">5</span><span class="p">)</span>
+<span class="n">cost</span> <span class="o">=</span> <span class="n">time_f</span><span class="p">(</span><span class="n">a</span><span class="p">,</span> <span class="n">b</span><span class="p">,</span> <span class="n">c</span><span class="p">)</span><span class="o">.</span><span class="n">mean</span>
+<span class="k">print</span><span class="p">(</span><span class="s">'</span><span class="si">%</span><span class="s">g secs/op, </span><span class="si">%</span><span class="s">g GFLOPS'</span> <span class="o">%</span> <span class="p">(</span><span class="n">cost</span><span class="p">,</span> <span class="n">ngflops</span><span class="p">(</span><span class="n">N</span><span class="p">)</span> <span class="o">/</span> <span class="n">cost</span><span class="p">))</span>
+</code></pre></div></div>
+
+<p>Now we can verify the results on PC,</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">np</span><span class="o">.</span><span class="n">testing</span><span class="o">.</span><span class="n">assert_almost_equal</span><span class="p">(</span>
+ <span class="n">c</span><span class="o">.</span><span class="n">asnumpy</span><span class="p">(),</span>
+ <span class="n">a_np</span><span class="o">.</span><span class="n">dot</span><span class="p">(</span><span class="n">b_np</span><span class="p">),</span>
+ <span class="n">decimal</span><span class="o">=</span><span class="mi">3</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>In the case above, we develop and cross-compile to a binary file for our mobile phone. Through the proxy server, the binary is uploaded to the phone and run in its JVM. This approach makes it easy to develop and test different computation workloads on Android.</p>
+
+<h2 id="java-runtime-for-tvm">Java Runtime for TVM</h2>
+
+<p>The Android APP is built on top of the Java runtime, which provides minimum supports for TVM Function and NDArray. Here’s an example for registering function in tvm4j,</p>
+
+<div class="language-java highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="nc">Function</span> <span class="n">func</span> <span class="o">=</span> <span class="nc">Function</span><span class="o">.</span><span class="na">convertFunc</span><span class="o">(</span><span class="k">new</span> <span class="nc">Function</span><span class="o">.</span><span class="na">Callback</span><span class="o">()</span> <span class="o">{</span>
+ <span class="nd">@Override</span> <span class="kd">public</span> <span class="nc">Object</span> <span class="nf">invoke</span><span class="o">(</span><span class="nc">TVMValue</span><span class="o">...</span> <span class="n">args</span><span class="o">)</span> <span class="o">{</span>
+ <span class="nc">StringBuilder</span> <span class="n">res</span> <span class="o">=</span> <span class="k">new</span> <span class="nc">StringBuilder</span><span class="o">();</span>
+ <span class="k">for</span> <span class="o">(</span><span class="nc">TVMValue</span> <span class="n">arg</span> <span class="o">:</span> <span class="n">args</span><span class="o">)</span> <span class="o">{</span>
+ <span class="n">res</span><span class="o">.</span><span class="na">append</span><span class="o">(</span><span class="n">arg</span><span class="o">.</span><span class="na">asString</span><span class="o">());</span>
+ <span class="o">}</span>
+ <span class="k">return</span> <span class="n">res</span><span class="o">.</span><span class="na">toString</span><span class="o">();</span>
+ <span class="o">}</span>
+ <span class="o">});</span>
+<span class="nc">TVMValue</span> <span class="n">res</span> <span class="o">=</span> <span class="n">func</span><span class="o">.</span><span class="na">pushArg</span><span class="o">(</span><span class="s">"Hello"</span><span class="o">).</span><span class="na">pushArg</span><span class="o">(</span><span class="s">" "</span><span class="o">).</span><span class="na">pushArg</span><span class="o">(</span><span class="s">"World!"</span><span class="o">).</span><span class="na">invoke</span [...]
+<span class="n">assertEquals</span><span class="o">(</span><span class="s">"Hello World!"</span><span class="o">,</span> <span class="n">res</span><span class="o">.</span><span class="na">asString</span><span class="o">());</span>
+<span class="n">res</span><span class="o">.</span><span class="na">release</span><span class="o">();</span>
+<span class="n">func</span><span class="o">.</span><span class="na">release</span><span class="o">();</span>
+</code></pre></div></div>
+
+<p>As we have seen in the GEMM part, one can build shared library by Python and execute it by Java,</p>
+
+<div class="language-java highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="kn">import</span> <span class="nn">ml.dmlc.tvm.Module</span><span class="o">;</span>
+<span class="kn">import</span> <span class="nn">ml.dmlc.tvm.NDArray</span><span class="o">;</span>
+<span class="kn">import</span> <span class="nn">ml.dmlc.tvm.TVMContext</span><span class="o">;</span>
+
+<span class="kn">import</span> <span class="nn">java.io.File</span><span class="o">;</span>
+<span class="kn">import</span> <span class="nn">java.util.Arrays</span><span class="o">;</span>
+
+<span class="kd">public</span> <span class="kd">class</span> <span class="nc">LoadAddFunc</span> <span class="o">{</span>
+ <span class="kd">public</span> <span class="kd">static</span> <span class="kt">void</span> <span class="nf">main</span><span class="o">(</span><span class="nc">String</span><span class="o">[]</span> <span class="n">args</span><span class="o">)</span> <span class="o">{</span>
+ <span class="nc">String</span> <span class="n">loadingDir</span> <span class="o">=</span> <span class="n">args</span><span class="o">[</span><span class="mi">0</span><span class="o">];</span>
+ <span class="nc">Module</span> <span class="n">fadd</span> <span class="o">=</span> <span class="nc">Module</span><span class="o">.</span><span class="na">load</span><span class="o">(</span><span class="n">loadingDir</span> <span class="o">+</span> <span class="nc">File</span><span class="o">.</span><span class="na">separator</span> <span class="o">+</span> <span class="s">"add_cpu.so"</span><span class="o">);</span>
+
+ <span class="nc">TVMContext</span> <span class="n">ctx</span> <span class="o">=</span> <span class="nc">TVMContext</span><span class="o">.</span><span class="na">cpu</span><span class="o">();</span>
+
+ <span class="kt">long</span><span class="o">[]</span> <span class="n">shape</span> <span class="o">=</span> <span class="k">new</span> <span class="kt">long</span><span class="o">[]{</span><span class="mi">2</span><span class="o">};</span>
+ <span class="nc">NDArray</span> <span class="n">arr</span> <span class="o">=</span> <span class="nc">NDArray</span><span class="o">.</span><span class="na">empty</span><span class="o">(</span><span class="n">shape</span><span class="o">,</span> <span class="n">ctx</span><span class="o">);</span>
+ <span class="n">arr</span><span class="o">.</span><span class="na">copyFrom</span><span class="o">(</span><span class="k">new</span> <span class="kt">float</span><span class="o">[]{</span><span class="mi">3</span><span class="n">f</span><span class="o">,</span> <span class="mi">4</span><span class="n">f</span><span class="o">});</span>
+ <span class="nc">NDArray</span> <span class="n">res</span> <span class="o">=</span> <span class="nc">NDArray</span><span class="o">.</span><span class="na">empty</span><span class="o">(</span><span class="n">shape</span><span class="o">,</span> <span class="n">ctx</span><span class="o">);</span>
+
+ <span class="n">fadd</span><span class="o">.</span><span class="na">entryFunc</span><span class="o">().</span><span class="na">pushArg</span><span class="o">(</span><span class="n">arr</span><span class="o">).</span><span class="na">pushArg</span><span class="o">(</span><span class="n">arr</span><span class="o">).</span><span class="na">pushArg</span><span class="o">(</span><span class="n">res</span><span class="o">).</span><span class="na">invoke</span><span class="o">();</span>
+ <span class="nc">System</span><span class="o">.</span><span class="na">out</span><span class="o">.</span><span class="na">println</span><span class="o">(</span><span class="nc">Arrays</span><span class="o">.</span><span class="na">toString</span><span class="o">(</span><span class="n">res</span><span class="o">.</span><span class="na">asFloatArray</span><span class="o">()));</span>
+
+ <span class="n">arr</span><span class="o">.</span><span class="na">release</span><span class="o">();</span>
+ <span class="n">res</span><span class="o">.</span><span class="na">release</span><span class="o">();</span>
+ <span class="n">fadd</span><span class="o">.</span><span class="na">release</span><span class="o">();</span>
+ <span class="o">}</span>
+<span class="o">}</span>
+</code></pre></div></div>
+
+<p>Once you have built TVM library following the <a href="http://docs.tvmlang.org/how_to/install.html">Installation Guide</a>, run</p>
+
+<div class="language-bash highlighter-rouge"><div class="highlight"><pre class="highlight"><code>make jvmpkg
+make jvminstall
+</code></pre></div></div>
+
+<p>This will compile, package and install tvm4j in your local maven repository. Please refer to <a href="https://github.com/dmlc/tvm/tree/master/jvm">tvm4j</a> for more information.</p>
+
+<h2 id="remote-profile-and-test-on-iphoneipad">Remote Profile and Test on iPhone/iPad</h2>
+
+<p>Besides the Android RPC application, we also provide an <a href="https://github.com/dmlc/tvm/tree/master/apps/ios_rpc">iOS RPC app</a>, through which we can easily profile and test TVM computation workloads on iPhone or iPad. It works almost the same as that on Android, while XCode and an iOS device are required.</p>
+
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+ or stability of the code, it does indicate that the project has yet to be fully endorsed by the ASF.
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diff --git a/2018/01/16/opt-mali-gpu.html b/2018/01/16/opt-mali-gpu.html
new file mode 100644
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+ <title>Optimizing Mobile Deep Learning on ARM GPU with TVM</title>
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+ <h1>Optimizing Mobile Deep Learning on ARM GPU with TVM </h1>
+ <p class="post-meta">
+ <time datetime="2018-01-16T00:00:00-08:00" itemprop="datePublished">
+ Jan 16, 2018
+ </time>
+
+ • <span itemprop="author" itemscope itemtype="http://schema.org/Person">
+ <span itemprop="name">Lianmin Zheng</span>
+ </span>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p>With the great success of deep learning, the demand for
+deploying deep neural networks to mobile devices is growing rapidly.
+Similar to what we do in desktop platforms, utilizing GPU in mobile devices
+can benefit both inference speed and energy efficiency. However, most
+existing deep learning frameworks do not support mobile GPU very well.
+The difficulty lies at the difference between mobile GPU architecture and
+desktop GPU architecture. It means special effort is required for optimizing on
+mobile GPU. The non-trivial extra work eventually results in the poor support
+of mobile GPU in most deep learning frameworks.</p>
+
+<p>TVM addresses the difficulty of deploying for different hardwares by
+introducing an unified IR stack, with which the optimization for different
+hardwares can be done easily. In this post, we show how we use
+<a href="http://tvmlang.org/2017/08/17/tvm-release-announcement.html">TVM</a>/<a href="http://tvmlang.org/2017/10/06/nnvm-compiler-announcement.html">NNVM</a> to
+generate efficient kernels for ARM Mali GPU and do end-to-end compilation.
+In our test on Mali-T860 MP4, compared with
+<a href="https://developer.arm.com/technologies/compute-library">Arm Compute Library</a>,
+our method is 1.4x faster on VGG-16 and 2.2x faster on MobileNet.
+Both graph-level and operator-level optimization contribute
+to this speed up.</p>
+
+<p style="text-align: center"><img src="/images/opt-mali/end2end.png" alt="image" width="95%" /></p>
+
+<center> Figure. Inference Speed of Different Backends on ImageNet</center>
+<p></p>
+
+<h1 id="mali-midgrad-gpu">Mali Midgrad GPU</h1>
+<p>We will use Firefly-RK3399 with Mali-T860 MP4 as our test environment,
+so we mainly focus on Mali T8xx below.</p>
+
+<h2 id="architecture">Architecture</h2>
+<p>Figure 1 is an overview of the Mali Architecture on T860 and T880.
+The GPUs are scalable up to 16 coherent shader cores. Inside each
+shader core, there are 2 or 3 arithmetic pipelines, 1 load/store pipeline
+and 1 texture pipeline (so-called TriPipe). The ALU in each arithmetic
+pipeline has four 128-bit vector units and one scalar units.</p>
+
+<p>We use OpenCL for GPU computing. When mapping to OpenCL model, each
+shader core executes one or several work groups. Each shader core supports
+up to 384 concurrently executing threads. Each work item in OpenCL
+typically maps to a single thread on a Mali GPU.
+The Mali GPUs use a VLIW (Very Long Instruction Word) architecture.
+Each instruction word contains multiple operations. The Mali GPUs
+also use SIMD, so that most arithmetic instructions operate on
+multiple data elements simultaneously. <sup>[1]</sup></p>
+
+<center> <img width="50%" src="/images/opt-mali/mali-arch.png" /> </center>
+<center> Figure 1. Mali T860 and T880 (source <sup>[2]</sup>) </center>
+
+<h2 id="difference-with-nvidias-gpus">Difference with NVIDIA’s GPUs</h2>
+<p>Here are some differences that we should concern when writing OpenCL
+code for Mali GPUs, compared with writing for NVIDIA’s GPUs.</p>
+<ul>
+ <li>Mali GPUs use an unified global memory. In NVIDIA’s GPUs, we usually
+copy data to shared memory, because NVIDIA’s GPUs have physically
+separate global memory, shared memory and register. In Mali, this copy
+does not improve performance and can be removed. Besides, Mali GPUs
+usually share the global memory with CPU, so there is no need for copying
+between CPU and GPU.</li>
+ <li>Mali Midgrad GPUs are based on SIMD (Single Instruction Multiple Data)
+and need explicit vectorization. In NVIDIA CUDA, parallelism is
+achieved by SIMT (Single Instruction Multiple Thread), which does
+not require explicit vectorization. But also notice that the newer
+Mali Bitfrost GPUs are based on quad-style vectorization and does not
+require explicit vectorization.</li>
+ <li>All threads in Mali GPUs have individual program counters. It means
+the <code class="highlighter-rouge">warp size</code> is 1, so that branch divergence is not a major problem.</li>
+</ul>
+
+<h1 id="optimization--convolution-as-example">Optimization : Convolution as Example</h1>
+<p>The convolution layer is the core of most deep neural networks and
+takes most of the computation time. So we take the convolution layer
+as example to demonstrate how common optimization techniques like
+packing, tiling, unrolling and vectorization are applied in TVM.</p>
+
+<h2 id="im2col-with-gemm">Im2Col with GEMM</h2>
+<p>A well-known algorithm for convolution layer is <a href="https://petewarden.com/2015/04/20/why-gemm-is-at-the-heart-of-deep-learning/">im2col</a>,
+which converts the little 3D input cubes to columns of a matrix and
+perform a GEMM. The advantage of this method is easy utilization of
+highly optimized BLAS library. However, the memory redundancy
+(9x memory for 3x3 kernel) is awful.</p>
+
+<h2 id="spatial-packing">Spatial Packing</h2>
+<p>Instead, we adopt a method to calculate the convolution, and apply the
+optimization techniques step by step. A convolution layer in VGG-16
+is used as tuning case, whose configuration is listed below.
+We assume the batch size is 1 for inference.</p>
+
+<table>
+ <thead>
+ <tr>
+ <th>Input Shape</th>
+ <th>Output Shape</th>
+ <th>Kernel Size</th>
+ <th>Stride</th>
+ <th>Padding</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td>56x56x256</td>
+ <td>56x56x256</td>
+ <td>3x3</td>
+ <td>(1, 1)</td>
+ <td>(1, 1)</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>As a baseline, we also list the performance of this layer in
+Arm Compute Library.</p>
+
+<table>
+ <thead>
+ <tr>
+ <th>Kernel</th>
+ <th>Cost (second)</th>
+ <th>GFLOPS</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td>GEMM method in ARMComputeLib</td>
+ <td>0.1821</td>
+ <td>20.3111</td>
+ </tr>
+ </tbody>
+</table>
+
+<h3 id="declare-the-computation-tiling-and-packing">Declare the computation: tiling and packing</h3>
+<p>Tiling and packing are two methods intended for better memory access.
+Tiling separates the whole computation into small blocks for better
+datareuse. Packing re-layouts the input matrices according to the
+tiling so that we can access the memory sequentially, which reduces
+cache miss rate.</p>
+
+<p>We do tiling on the width dimension of the input image and CO dimension
+of the filter matrix. This is described by <code class="highlighter-rouge">tvm.compute</code>.</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1"># set tiling factor
+</span><span class="n">VH</span> <span class="o">=</span> <span class="mi">1</span>
+<span class="n">VW</span> <span class="o">=</span> <span class="n">VC</span> <span class="o">=</span> <span class="mi">4</span>
+
+<span class="c1"># get input shape
+</span> <span class="n">_</span><span class="p">,</span> <span class="n">CI</span><span class="p">,</span> <span class="n">IH</span><span class="p">,</span> <span class="n">IW</span> <span class="o">=</span> <span class="n">data</span><span class="o">.</span><span class="n">shape</span>
+<span class="n">CO</span><span class="p">,</span> <span class="n">CI</span><span class="p">,</span> <span class="n">KH</span><span class="p">,</span> <span class="n">KW</span> <span class="o">=</span> <span class="n">kernel</span><span class="o">.</span><span class="n">shape</span>
+<span class="n">TH</span> <span class="o">=</span> <span class="n">IH</span> <span class="o">+</span> <span class="mi">2</span> <span class="o">*</span> <span class="n">H_PAD</span>
+<span class="n">TW</span> <span class="o">=</span> <span class="n">IW</span> <span class="o">+</span> <span class="mi">2</span> <span class="o">*</span> <span class="n">W_PAD</span>
+
+<span class="c1"># calc output shape
+</span><span class="n">OH</span> <span class="o">=</span> <span class="p">(</span><span class="n">IH</span> <span class="o">+</span> <span class="mi">2</span><span class="o">*</span><span class="n">H_PAD</span> <span class="o">-</span> <span class="n">KH</span><span class="p">)</span> <span class="o">//</span> <span class="n">H_STR</span> <span class="o">+</span> <span class="mi">1</span>
+<span class="n">OW</span> <span class="o">=</span> <span class="p">(</span><span class="n">IW</span> <span class="o">+</span> <span class="mi">2</span><span class="o">*</span><span class="n">W_PAD</span> <span class="o">-</span> <span class="n">KW</span><span class="p">)</span> <span class="o">//</span> <span class="n">W_STR</span> <span class="o">+</span> <span class="mi">1</span>
+
+<span class="c1"># data shape after packing
+</span><span class="n">dvshape</span> <span class="o">=</span> <span class="p">(</span><span class="n">N</span><span class="p">,</span> <span class="n">TH</span> <span class="o">//</span> <span class="p">(</span><span class="n">VH</span><span class="o">*</span><span class="n">H_STRIDE</span><span class="p">),</span> <span class="n">TW</span> <span class="o">//</span> <span class="p">(</span><span class="n">VW</span><span class="o">*</span><span class="n">W_STRIDE</span><span class="p">), [...]
+
+<span class="c1"># kernel shape after packing
+</span><span class="n">kvshape</span> <span class="o">=</span> <span class="p">(</span><span class="n">CO</span> <span class="o">//</span> <span class="n">VC</span><span class="p">,</span> <span class="n">CI</span><span class="p">,</span> <span class="n">KH</span><span class="p">,</span> <span class="n">KW</span><span class="p">,</span> <span class="n">VC</span><span class="p">)</span>
+
+<span class="n">ovshape</span> <span class="o">=</span> <span class="p">(</span><span class="n">N</span><span class="p">,</span> <span class="n">CO</span> <span class="o">//</span> <span class="n">VC</span><span class="p">,</span> <span class="n">OH</span> <span class="o">//</span> <span class="n">VH</span><span class="p">,</span> <span class="n">OW</span> <span class="o">//</span> <span class="n">VW</span><span class="p">,</span> <span class="n">VH</span><span class="p">,</span> <span c [...]
+<span class="n">oshape</span> <span class="o">=</span> <span class="p">(</span><span class="n">N</span><span class="p">,</span> <span class="n">CO</span><span class="p">,</span> <span class="n">OH</span><span class="p">,</span> <span class="n">OW</span><span class="p">)</span>
+
+<span class="c1"># define packing
+</span><span class="n">data_vec</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">(</span><span class="n">dvshape</span><span class="p">,</span> <span class="k">lambda</span> <span class="n">n</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">vh</span><span class="p">, [...]
+ <span class="n">data_pad</span><span class="p">[</span><span class="n">n</span><span class="p">][</span><span class="n">ci</span><span class="p">][</span><span class="n">h</span><span class="o">*</span><span class="n">VH</span><span class="o">*</span><span class="n">H_STRIDE</span><span class="o">+</span><span class="n">vh</span><span class="p">][</span><span class="n">w</span><span class="o">*</span><span class="n">VW</span><span class="o">*</span><span class="n">W_STRIDE</span><spa [...]
+
+<span class="n">kernel_vec</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">(</span><span class="n">kvshape</span><span class="p">,</span> <span class="k">lambda</span> <span class="n">co</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span><span class="p">,</span> <span class="n">vc</span><span class="p">:</span>
+ <span class="n">kernel</span><span class="p">[</span><span class="n">co</span><span class="o">*</span><span class="n">VC</span><span class="o">+</span><span class="n">vc</span><span class="p">][</span><span class="n">ci</span><span class="p">][</span><span class="n">kh</span><span class="p">][</span><span class="n">kw</span><span class="p">],</span> <span class="n">name</span><span class="o">=</span><span class="s">'kernel_vec'</span><span class="p">)</span>
+
+<span class="c1"># define convolution
+</span><span class="n">ci</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">CI</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'ci'</span><span class="p">)</span>
+<span class="n">kh</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">KH</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'kh'</span><span class="p">)</span>
+<span class="n">kw</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">KW</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'kw'</span><span class="p">)</span>
+
+<span class="n">conv</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">(</span><span class="n">ovshape</span><span class="p">,</span> <span class="k">lambda</span> <span class="n">n</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <sp [...]
+ <span class="n">tvm</span><span class="o">.</span><span class="nb">sum</span><span class="p">(</span><span class="n">data_vec</span><span class="p">[</span><span class="n">n</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">vh</span><span class="o">*</span><span class="n">H_STRIDE</span><span class="o">+</span><span class="n">kh</span><span [...]
+ <span class="n">kernel_vec</span><span class="p">[</span><span class="n">co</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span><span class="p">,</span> <span class="n">vc</span><span class="p">]</span><span class="o">.</span><span class="n">astype</span><span class="p">(</span><span class="n">out_dtype</span><span class="p">),</span>
+ <span class="n">axis</span><span class="o">=</span><span class="p">[</span><span class="n">ci</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span><span class="p">]),</span> <span class="n">name</span><span class="o">=</span><span class="s">'conv'</span><span class="p">)</span>
+
+<span class="c1"># unpack to correct layout
+</span><span class="n">output</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">(</span><span class="n">oshape</span><span class="p">,</span> <span class="k">lambda</span> <span class="n">n</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">:</span>
+ <span class="n">conv</span><span class="p">[</span><span class="n">n</span><span class="p">][</span><span class="n">co</span><span class="o">//</span><span class="n">VC</span><span class="p">][</span><span class="n">h</span><span class="o">/</span><span class="n">VH</span><span class="p">][</span><span class="n">w</span><span class="o">//</span><span class="n">VW</span><span class="p">][</span><span class="n">h</span><span class="o">%</span><span class="n">VH</span>< [...]
+ <span class="n">name</span><span class="o">=</span><span class="s">'output_unpack'</span><span class="p">,</span> <span class="n">tag</span><span class="o">=</span><span class="s">'direct_conv_output'</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>We can inspect the defined IR by</p>
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="k">print</span><span class="p">(</span><span class="n">tvm</span><span class="o">.</span><span class="n">lower</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="p">[</span><span class="n">data</span><span class="p">,</span> <span class="n">kernel</span><span class="p">,</span> <span class="n">output</span><span class="p">],</span> <span [...]
+</code></pre></div></div>
+<p>I pick the convolution part here.</p>
+<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>produce conv {
+ for (co, 0, 64) {
+ for (h, 0, 56) {
+ for (w, 0, 14) {
+ for (vw.init, 0, 4) {
+ for (vc.init, 0, 4) {
+ conv[((((((((co*56) + h)*14) + w)*4) + vw.init)*4) + vc.init)] = 0.000000f
+ }
+ }
+ for (ci, 0, 256) {
+ for (kh, 0, 3) {
+ for (kw, 0, 3) {
+ for (vw, 0, 4) {
+ for (vc, 0, 4) {
+ conv[((((((((co*56) + h)*14) + w)*4) + vw)*4) + vc)] = (conv[((((((((co*56) + h)*14) + w)*4) + vw)*4) + vc)] + (data_vec[(((((((((h*14) + w)*256) + ci)*3) + kh)*6) + kw) + vw)]*kernel_vec[((((((((co*256) + ci)*3) + kh)*3) + kw)*4) + vc)]))
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+}
+</code></pre></div></div>
+
+<h3 id="kernel-1-bind-thread">Kernel 1: bind thread</h3>
+<p>In TVM, we declare the computation at first and then <em>schedule</em> it.
+This mechanism decouples the algorithm and implementation detail. (This idea
+is from <a href="http://halide-lang.org/">Halide</a>).</p>
+
+<p>The following schedule simply binds axes to GPU threads, so that
+our code can run on Mali GPU.</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1"># helper function for binding thread
+</span><span class="k">def</span> <span class="nf">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">tensor</span><span class="p">,</span> <span class="n">z</span><span class="p">,</span> <span class="n">y</span><span class="p">,</span> <span class="n">x</span><span class="p">,</span> <span class="n">z_factor</span><span class="o">=</span><span class="mi">2</span><span class="p">,</span> <span class="n">y_factor</span><span cla [...]
+ <span class="s">""" tile and bind 3d """</span>
+ <span class="n">y_factor</span> <span class="o">=</span> <span class="n">y_factor</span> <span class="ow">or</span> <span class="n">z_factor</span>
+ <span class="n">x_factor</span> <span class="o">=</span> <span class="n">x_factor</span> <span class="ow">or</span> <span class="n">y_factor</span>
+ <span class="n">zo</span><span class="p">,</span> <span class="n">zi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">z</span><span class="p">,</span> <span class="n">z_factor</span><span class="p">)</span>
+ <span class="n">yo</span><span class="p">,</span> <span class="n">yi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">y</span><span class="p">,</span> <span class="n">y_factor</span><span class="p">)</span>
+ <span class="n">xo</span><span class="p">,</span> <span class="n">xi</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">split</span><span class="p">(</span><span class="n">x</span><span class="p">,</span> <span class="n">x_factor</span><span class="p">)</span>
+ <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">zo</span><span class="p">,</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"blockIdx.z"</span><span class="p">))</span>
+ <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">zi</span><span class="p">,</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"threadIdx.z"</span><span class="p">))</span>
+ <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">yo</span><span class="p">,</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"blockIdx.y"</span><span class="p">))</span>
+ <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">yi</span><span class="p">,</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"threadIdx.y"</span><span class="p">))</span>
+ <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">xo</span><span class="p">,</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"blockIdx.x"</span><span class="p">))</span>
+ <span class="n">s</span><span class="p">[</span><span class="n">tensor</span><span class="p">]</span><span class="o">.</span><span class="n">bind</span><span class="p">(</span><span class="n">xi</span><span class="p">,</span> <span class="n">tvm</span><span class="o">.</span><span class="n">thread_axis</span><span class="p">(</span><span class="s">"threadIdx.x"</span><span class="p">))</span>
+
+<span class="c1"># set tunable parameter
+</span><span class="n">num_thread</span> <span class="o">=</span> <span class="mi">8</span>
+
+<span class="c1"># schedule data packing
+</span><span class="n">_</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">vw</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">data_vec</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class [...]
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">data_vec</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="c1"># schedule kernel packing
+</span><span class="n">co</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span><span class="p">,</span> <span class="n">vc</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span>
+<span class="n">tile_and_bind</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">kernel_vec</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="c1"># schedule conv
+</span><span class="n">_</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">vw</span><span class="p">,</span> <span class="n">vc</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n" [...]
+<span class="n">kc</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">reduce_axis</span>
+
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">reorder</span><span class="p">(</span><span class="n">_</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">kc</span><span class="p">,</span> <span class="n">kh< [...]
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">conv</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">num_thread</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="n">_</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">oh</span><span class="p">,</span> <span class="n">ow</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">output</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span>
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">output</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">oh</span><span class="p">,</span> <span class="n">ow</span><span class="p">,</span> <span class="n">num_thread</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>With this schedule, our code can run now, but the performance is terrible.</p>
+
+<table>
+ <thead>
+ <tr>
+ <th>Kernel</th>
+ <th>Cost (second)</th>
+ <th>GFLOPS</th>
+ <th>speedup</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td>GEMM method in ARMComputeLib</td>
+ <td>0.1821</td>
+ <td>20.3111</td>
+ <td>1x</td>
+ </tr>
+ <tr>
+ <td>Kernel 1: simple bind</td>
+ <td>5.6154</td>
+ <td>0.6588</td>
+ <td>0.03x</td>
+ </tr>
+ </tbody>
+</table>
+
+<h3 id="kernel-2-unrolling">Kernel 2: unrolling</h3>
+<p>Loop unrolling can reduce the instructions for loop control, reduce
+branch penalties and hide latency in reading memory.
+In TVM, this can be done easily by calling <code class="highlighter-rouge">s.unroll(axis)</code></p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1"># set tunable parameter
+</span><span class="n">num_thread</span> <span class="o">=</span> <span class="mi">8</span>
+
+<span class="c1"># schedule data packing
+</span><span class="n">_</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">vw</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">data_vec</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class [...]
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">data_vec</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="s">"""!! ADD UNROLL HERE !!"""</span>
+<span class="n">s</span><span class="p">[</span><span class="n">data_vec</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">vw</span><span class="p">)</span>
+
+<span class="c1"># schedule kernel packing
+</span><span class="n">co</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span><span class="p">,</span> <span class="n">vc</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span>
+<span class="n">tile_and_bind</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">kernel_vec</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="s">"""!! ADD UNROLL HERE !!"""</span>
+<span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">kh</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">kw</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">vc</span><span class="p">)</span>
+
+<span class="c1"># schedule conv
+</span><span class="n">_</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">vw</span><span class="p">,</span> <span class="n">vc</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n" [...]
+<span class="n">kc</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">reduce_axis</span>
+
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">reorder</span><span class="p">(</span><span class="n">_</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">kc</span><span class="p">,</span> <span class="n">kh< [...]
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">conv</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">num_thread</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="s">"""!! ADD UNROLL HERE !!"""</span>
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">kh</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">kw</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">vw</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">vc</span><span class="p">)</span>
+
+<span class="n">_</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">oh</span><span class="p">,</span> <span class="n">ow</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">output</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span>
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">output</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">oh</span><span class="p">,</span> <span class="n">ow</span><span class="p">,</span> <span class="n">num_thread</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+</code></pre></div></div>
+
+<table>
+ <thead>
+ <tr>
+ <th>Kernel</th>
+ <th>Cost (second)</th>
+ <th>GFLOPS</th>
+ <th>speedup</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td>GEMM method in ARMComputeLib</td>
+ <td>0.1821</td>
+ <td>20.3111</td>
+ <td>1x</td>
+ </tr>
+ <tr>
+ <td>Kernel 1: simple bind</td>
+ <td>5.6154</td>
+ <td>0.6588</td>
+ <td>0.03x</td>
+ </tr>
+ <tr>
+ <td>Kernel 2: + unrolling</td>
+ <td>0.3707</td>
+ <td>9.9796</td>
+ <td>0.49x</td>
+ </tr>
+ </tbody>
+</table>
+
+<h3 id="kernel3-vectorization">Kernel3: vectorization</h3>
+<p>As mentioned before, we need to do vectorization explictly
+ in order to achieve the best performance on Mali GPU.</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="c1"># set tunable parameter
+</span><span class="n">num_thread</span> <span class="o">=</span> <span class="mi">8</span>
+
+<span class="c1"># schedule data packing
+</span><span class="n">_</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">vw</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">data_vec</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class [...]
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">data_vec</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="c1"># unroll
+</span><span class="n">s</span><span class="p">[</span><span class="n">data_vec</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">vw</span><span class="p">)</span>
+
+<span class="c1"># schedule kernel packing
+</span><span class="n">co</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span><span class="p">,</span> <span class="n">vc</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span>
+<span class="n">tile_and_bind</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">kernel_vec</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">ci</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="c1"># unroll
+</span><span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">kh</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">kw</span><span class="p">)</span>
+<span class="s">"""!! VECTORIZE HERE !!"""</span>
+<span class="n">s</span><span class="p">[</span><span class="n">kernel_vec</span><span class="p">]</span><span class="o">.</span><span class="n">vectorize</span><span class="p">(</span><span class="n">vc</span><span class="p">)</span>
+
+<span class="c1"># schedule conv
+</span><span class="n">_</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">vw</span><span class="p">,</span> <span class="n">vc</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n" [...]
+<span class="n">kc</span><span class="p">,</span> <span class="n">kh</span><span class="p">,</span> <span class="n">kw</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">reduce_axis</span>
+
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">reorder</span><span class="p">(</span><span class="n">_</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">vh</span><span class="p">,</span> <span class="n">kc</span><span class="p">,</span> <span class="n">kh< [...]
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">conv</span><span class="p">,</span> <span class="n">c</span><span class="p">,</span> <span class="n">h</span><span class="p">,</span> <span class="n">w</span><span class="p">,</span> <span class="n">num_thread</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+
+<span class="c1"># unroll
+</span><span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">kh</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">kw</span><span class="p">)</span>
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">unroll</span><span class="p">(</span><span class="n">vw</span><span class="p">)</span>
+<span class="s">"""!! VECTORIZE HERE !!"""</span>
+<span class="n">s</span><span class="p">[</span><span class="n">conv</span><span class="p">]</span><span class="o">.</span><span class="n">vectorize</span><span class="p">(</span><span class="n">vc</span><span class="p">)</span>
+
+<span class="n">_</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">oh</span><span class="p">,</span> <span class="n">ow</span> <span class="o">=</span> <span class="n">s</span><span class="p">[</span><span class="n">output</span><span class="p">]</span><span class="o">.</span><span class="n">op</span><span class="o">.</span><span class="n">axis</span>
+<span class="n">tile_and_bind3d</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="n">output</span><span class="p">,</span> <span class="n">co</span><span class="p">,</span> <span class="n">oh</span><span class="p">,</span> <span class="n">ow</span><span class="p">,</span> <span class="n">num_thread</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
+</code></pre></div></div>
+
+<table>
+ <thead>
+ <tr>
+ <th>Kernel</th>
+ <th>Cost (second)</th>
+ <th>GFLOPS</th>
+ <th>speedup</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td>GEMM method in ARMComputeLib</td>
+ <td>0.1821</td>
+ <td>20.3111</td>
+ <td>1x</td>
+ </tr>
+ <tr>
+ <td>Kernel 1: simple bind</td>
+ <td>5.6154</td>
+ <td>0.6588</td>
+ <td>0.03x</td>
+ </tr>
+ <tr>
+ <td>Kernel 2: + unrolling</td>
+ <td>0.3707</td>
+ <td>9.9796</td>
+ <td>0.49x</td>
+ </tr>
+ <tr>
+ <td>Kernel 3: + vectorization</td>
+ <td>0.1304</td>
+ <td>28.3679</td>
+ <td>1.40x</td>
+ </tr>
+ </tbody>
+</table>
+
+<h3 id="how-to-set-the-tunable-parameter">How to set the tunable parameter</h3>
+<p>As for the tunable parameters above, some can be calculated.
+For the vectorized dimension <code class="highlighter-rouge">VC</code>, we should fill the 128-bit register,
+so it can be set as 128/32=4 for float32 and 128/16=8 for float16.</p>
+
+<p>But more often we cannot determine the optimal value, due to the
+complicated runtime. We use grid search in TVM. It can be
+done extremely effective since we write python code in TVM’s high-level
+IR rather than direct OpenCL code.</p>
+
+<h3 id="the-generated-opencl-code">The generated OpenCL code</h3>
+<p>We can view the generated OpenCL code by</p>
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="k">print</span><span class="p">(</span><span class="n">func</span><span class="o">.</span><span class="n">imported_modules</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span><span class="o">.</span><span class="n">get_source</span><span class="p">())</span>
+</code></pre></div></div>
+<p>The OpenCL code is too long to be pasted here, and it is hard to read due
+to heavy unrolling. If interested, you can view it
+<a href="https://github.com/merrymercy/tvm-mali/blob/master/data/kernels.cl">here</a>.</p>
+
+<h1 id="end-to-end-benchmarking">End-to-End Benchmarking</h1>
+<p>In this section, we compare the comprehensive performance between
+different backends on some popular deep neural networks.
+Our test environment is</p>
+
+<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>Firefly-RK3399 4G
+CPU: dual-core Cortex-A72 + quad-core Cortex-A53
+GPU: Mali-T860MP4
+
+Arm Compute Library : v17.12
+MXNet: v1.0.1
+Openblas: v0.2.18
+</code></pre></div></div>
+
+<p>We use NNVM and TVM to do end-to-end compilation.</p>
+
+<h2 id="performance">Performance</h2>
+
+<p style="text-align: center"><img src="/images/opt-mali/end2end.png" alt="image" width="95%" /></p>
+
+<center> Figure 2. Inference Speed of Different Backends on ImageNet</center>
+<p></p>
+
+<p>As shown in Figure 2, we test the inference speed on ImageNet.
+On Firefly-RK3399, Mali GPU can be 2x ~ 4x faster than 6-core big.LITTLE CPU.
+Our end-to-end pipeline is 1.4x ~ 2.2x faster than Arm Compute Library.
+We try both GEMM and direct method of convolution layer in
+Arm Compute Library, GEMM method is always faster than direct method
+in these test cases, so we only plot the result of GEMM method.</p>
+
+<p>Some results, like resnet18 on Arm Compute Library, are missing in the Figure 2.
+It is because the graph runtime of Arm Compute Library does not support
+skip connection currently and has a poor neon implementation of
+depthwise convolution. This also reflects the advantage of NNVM
+software stack.</p>
+
+<h2 id="half-precision-performance">Half-Precision Performance</h2>
+<p>Precision in deep neural networks is not very important, especially
+for the inference on mobile devices. Using low-precision arithmetic
+can make the inference much faster. We also test the half-precision
+floating number on Mali GPU.</p>
+
+<table>
+ <thead>
+ <tr>
+ <th>model</th>
+ <th>backend</th>
+ <th>Time Cost per Image (second)</th>
+ <th>speed up to FP32</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td>vgg16</td>
+ <td>ACM-mali</td>
+ <td>0.9694</td>
+ <td>1.69</td>
+ </tr>
+ <tr>
+ <td>vgg16</td>
+ <td>TVM-mali</td>
+ <td>0.6896</td>
+ <td><strong>1.87x</strong></td>
+ </tr>
+ <tr>
+ <td>MobileNet 1.0</td>
+ <td>TVM-mali</td>
+ <td>0.0479</td>
+ <td>1.60x</td>
+ </tr>
+ <tr>
+ <td>ResNet18</td>
+ <td>TVM-mali</td>
+ <td>0.1183</td>
+ <td>1.73x</td>
+ </tr>
+ </tbody>
+</table>
+
+<center> Table 1. Inference Speed of FP16 on ImageNet</center>
+<p></p>
+
+<p>In theory, FP16 can both double peak compute and halve memory consumption,
+so that doubling the speed. But it needs good input shape for
+longer vectorization and fine-tuning some parameters.</p>
+
+<h2 id="further-work-on-mobile-devices">Further Work on Mobile Devices</h2>
+<p>We should admit that there is still some room for improvement,
+mainly at the graph level, such as model compression and weight prelayout.
+Further improvement in NNVM will try to solve these problems.</p>
+
+<h1 id="show-me-the-code">Show me the code</h1>
+
+<ul>
+ <li><a href="https://github.com/merrymercy/tvm-mali">End-to-End benchmark</a></li>
+ <li><a href="https://github.com/dmlc/tvm/tree/master/topi/python/topi/mali">Convolution and Depthwise Convolution Schedule</a></li>
+</ul>
+
+<h1 id="bio--acknowledgement">Bio & Acknowledgement</h1>
+<p><a href="https://lmzheng.net">Lianmin Zheng</a> is an undergraduate
+student at SJTU Apex lab. He is interested in machine learning
+and building computer system.</p>
+
+<p>The author has many thanks to
+<a href="https://homes.cs.washington.edu/~tqchen/">Tianqi Chen</a> for his helpful
+advice and <a href="https://github.com/yzhliu">Yizhi Liu</a> for his earlier work.</p>
+
+<h1 id="reference">Reference</h1>
+<p>[1] <a href="https://developer.arm.com/docs/100614/0302">ARM Mali GPU OpenCL Developer Guide</a>
+[2] <a href="https://developer.arm.com/">ARM Developer</a></p>
+
+ </div>
+ </div>
+</div>
+</div>
+
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+
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+ Apache TVM is an effort undergoing incubation at The Apache Software Foundation (ASF),
+ sponsored by the <i>Apache Incubator</i>. Incubation is required
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+ or stability of the code, it does indicate that the project has yet to be fully endorsed by the ASF.
+
+ Copyright © 2020 The Apache Software Foundation. Apache TVM, Apache,
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+
+
diff --git a/2018/03/12/webgl.html b/2018/03/12/webgl.html
new file mode 100644
index 0000000..988707c
--- /dev/null
+++ b/2018/03/12/webgl.html
@@ -0,0 +1,312 @@
+
+<!DOCTYPE html>
+<html lang="en">
+ <head>
+ <meta charset="utf-8">
+ <title>Compiling Deep Learning Models to WebGL with TVM</title>
+
+ <meta name="author" content="">
+
+ <!-- Le HTML5 shim, for IE6-8 support of HTML elements -->
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+ <script src="http://html5shim.googlecode.com/svn/trunk/html5.js"></script>
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+
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+ <div class="span14">
+ <h1>Compiling Deep Learning Models to WebGL with TVM </h1>
+ <p class="post-meta">
+ <time datetime="2018-03-12T00:00:00-07:00" itemprop="datePublished">
+ Mar 12, 2018
+ </time>
+
+ • <span itemprop="author" itemscope itemtype="http://schema.org/Person">
+ <span itemprop="name">Zhixun Tan</span>
+ </span>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p>Now TVM comes with a brand-new OpenGL/WebGL backend!
+This blog post explains what it is, and what you can achieve with it.</p>
+
+<h1 id="the-openglwebgl-backend">The OpenGL/WebGL Backend</h1>
+
+<p>TVM already targets a lot of backends covering a variety of platforms: CPU, GPU,
+mobile devices, etc… This time we are adding another backend: OpenGL/WebGL.</p>
+
+<p>OpenGL/WebGL enables us to leverage the GPU on an environment which does not
+have CUDA installed. It is, for the time being, the only way of using the GPU
+inside a browser.</p>
+
+<p>This new backend allows us to use OpenGL/WebGL in 3 different ways:</p>
+<ul>
+ <li><strong>Local OpenGL</strong>:
+We can compile a deep learning model into OpenGL and directly
+run it on the local machine, entirely using Python.</li>
+ <li><strong>WebGL with RPC</strong>:
+We can compile a deep learning model into WebGL and export
+it as a shared library via Emscripten, with JavaScript host code and WebGL device code. Then
+we can deploy that library through RPC onto a TVM JavaScript runtime system
+running inside a browser.</li>
+ <li><strong>WebGL with static library</strong>:
+We can compile a deep learning model into WebGL,
+link it with the TVM JavaScript runtime system and export the entire package.
+Then we can run the model in a web page on a browser, with no dependency.
+The detailed flow is described in figure 1.</li>
+</ul>
+
+<p>We rely on Emscripten and its fastcomp LLVM backend to generate the javascript backend.</p>
+
+<p style="text-align: center"><img src="/images/opengl/webgl-flow.png" alt="image" width="65%" /><br />
+Figure 1</p>
+
+<p>See <a href="https://github.com/dmlc/nnvm/blob/master/tutorials/from_mxnet_to_webgl.py">here</a>
+for examples of all three of them.</p>
+
+<h1 id="how-is-this-different-from-x">How is this Different from X?</h1>
+
+<p>Running a neural network on a browser isn’t an entirely new thing.
+Andrej Karpathy’s <a href="https://cs.stanford.edu/people/karpathy/convnetjs/">ConvNetJS</a>
+and Google’s <a href="https://deeplearnjs.org/">DeepLearning.JS</a> are examples of that.</p>
+
+<p>So what’s unique about TVM with WebGL? The big difference is that the op kernels
+in TVM are automatically compiled, not handwritten. As shown in Figure 2, TVM
+utilizes a unified AST to define kernels, and compiles it to code on different
+platforms.</p>
+
+<p style="text-align: center"><img src="/images/opengl/comparison.png" alt="" width="50%" /><br />
+Figure 2</p>
+
+<p>This means that:</p>
+<ul>
+ <li>To deploy your existing model to WebGL, you don’t need to write a lot of
+additional code. The NNVM/TVM model definition is the same for all targets, so
+you just need to compile it to a new target.</li>
+ <li>To add a new op kernel, you only need to define it in TVM once, instead of
+implementing it once for every target. You don’t need to know how to write
+GLSL code to add a new op kernel to WebGL!</li>
+</ul>
+
+<h1 id="benchmark">Benchmark</h1>
+
+<p>Here we perform a benchmark for a typical workload: image classification using
+resnet18.</p>
+
+<p>I’m using my <a href="https://www.asus.com/us/Laptops/N76VZ/">5-year-old laptop</a> which
+has an 8-core Intel® Core™ i7-3610QM, and a GTX650M.</p>
+
+<p>In this benchmark, we download a resnet18 model from the Gluon model zoo, and
+perform end-to-end classification on a cat image. We only measure the model
+execution time (without model/input/parameter loading), and each model is run
+100 times to get an average. The results are shown in figure 3.</p>
+
+<p style="text-align: center"><img src="/images/opengl/opengl-benchmark.png" alt="image" /><br />
+Figure 3</p>
+
+<p>The benchmark is run in 4 different settings:</p>
+<ul>
+ <li><strong>CPU (LLVM)</strong>: The model is compiled into LLVM IR and JIT’ed. Therefore, it is
+run entirely on the CPU.</li>
+ <li><strong>OpenCL</strong>: The model is compiled into OpenCL. There is still some glue code
+compiled to LLVM, which is responsible for setting up and launching OpenCL
+kernels. Then we run it on the local machine.</li>
+ <li><strong>OpenGL</strong>: Same as OpenCL, but compiled to OpenGL.</li>
+ <li><strong>WebGL</strong>: The glue code is compiled to LLVM, and transformed to JavaScript using
+Emscripten’s Fastcomp LLVM backend.
+The device code is compiled to WebGL. We execute the model in Firefox.</li>
+</ul>
+
+<p>From the result above we can observe that, the TVM OpenGL backend has a similar
+performance as OpenCL. More interestingly, the WebGL version inside the browser
+isn’t significantly slower than desktop OpenGL. Considering that the host code
+is JavaScript, this is quite surprising. This might be due to the fact that
+Emscripten generates <a href="http://asmjs.org/">asm.js</a> which enables dramatic
+optimizations in Firefox.</p>
+
+<p>This is a first step toward automatic compilation of deep learning models
+into web browser. We expect more performance improvements as we bring
+optimizations into the TVM stack.</p>
+
+<h2 id="show-me-the-code">Show me the Code</h2>
+<ul>
+ <li>Checkout <a href="https://github.com/dmlc/nnvm/blob/master/tutorials/from_mxnet_to_webgl.py">this complete code example</a>.</li>
+</ul>
+
+<h2 id="acknowledgement">Acknowledgement</h2>
+<p>We thank the developers of Emscripten for providing the fastcomp toolchain and the helps during the development.</p>
+
+ </div>
+ </div>
+</div>
+</div>
+
+
+
+
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+ <h1>Bringing TVM into TensorFlow for Optimizing Neural Machine Translation on GPU </h1>
+ <p class="post-meta">
+ <time datetime="2018-03-23T00:00:00-07:00" itemprop="datePublished">
+ Mar 23, 2018
+ </time>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <h2 id="author">Author</h2>
+
+<p>This is a guest blogpost contributed by Alibaba Group’s Machine Translation Platform team and PAI-Blade team</p>
+
+<h2 id="background">Background</h2>
+
+<p>Neural Machine Translation (NMT) is an end-to-end approach for automating translation, with the potential to overcome the weaknesses in conventional phrase-based translation systems. Recently, Alibaba Group is working on deploying NMT service for global e-commerce.</p>
+
+<p>Currently we are exploiting Transformer [1] as the major backbone in our NMT system since it is more friendly for efficient offline training with on-par (even higher) precison against classical RNN/LSTM-based models. Although Transformer is friendly for the offline training phase as it breaks the dependencies across time steps, it is not quite efficiency for online inference. In our production environment, it has been found that the inference speed of the intial version of Transformer [...]
+One paricular challenge we observed, is that batch matmul is a major performance hot-spot in Transformer and the current implementation in cuBLAS is not well optimized.</p>
+
+<p style="text-align: center"><img src="/images/nmt-transformer/model_arch.png" alt="image" width="40%" /></p>
+
+<p>The results below show that TVM generated kernel (with schdule optimization) brings at least <b><em>13X</em></b> speed-up for batch matmul computation, and a futher speed up with operator fusion enabled.</p>
+
+<p style="text-align: center"><img src="/images/nmt-transformer/batch-matmul-bar-charts.png" alt="image" width="45%" /></p>
+
+<h2 id="batch-matmul">Batch Matmul</h2>
+
+<h3 id="why-batch-matmul">Why batch matmul</h3>
+<p>In Transformer, batch matmul is widely used in the computation of multi-head attention. Using batch matmul, multiple heads in the attention layer can run in parallel, which can help improve the computation efficiency of the hardware.</p>
+
+<p style="text-align: center"><img src="/images/nmt-transformer/batchmatmul.png" alt="image" width="90%" /></p>
+
+<p>We conducted a thorough profiling of the Transformer model in the inference phase, and it is shown that batch matmul computation contribute up to ~ 30% of GPU kernel execution time. Using nvprof[2] to do some first-principle analysis of cuBLAS’s batch matmul kernel，it is clearly indicated that current implementation is quite under-performing and several interesting phenomena are observed.</p>
+
+<h3 id="what-is-batch-matmul">What is batch matmul</h3>
+<p>Typically, a batch matmul computation performs the matrix-matrix multiplication over a batch of matrices. The batch is considered to be “uniform”, i.e. all instances have the same dimensions (M, N, K), leading dimensions (lda, ldb, ldc) and transpositions for their respective A, B and C matrices.</p>
+
+<p>Batch matmul computation can be described more concretely as follows:</p>
+
+<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>void BatchedGemm(input A, input B, output C, M, N, K, batch_dimension) {
+ for (int i = 0; i < batch_dimension; ++i) {
+ DoGemm(A[i],B[i],C[i],M,K,N)
+ }
+}
+</code></pre></div></div>
+
+<h4 id="batch-matmul-shapes">Batch matmul shapes</h4>
+
+<p>In the language translation tasks, shape of the batch matmul is significantly smaller than normal matmul computation in other workloads. The shape in Transformer is relevant to the length of input sentences and that of decoder steps. Normally, it is smaller than 30.</p>
+
+<p>As to the batch dimension, it is a fixed number given a certain inference batch size. For instance, if 16 is used as batch size with beam size being 4, the batch dimension is 16 * 4 * #head (number of heads in multi-head attention, which is usually 8). The shape of the matrix M, K, N are within the range of [1, max decode length] or [1, max encode length].</p>
+
+<h3 id="performance-issue-of-cublas-batch-matmul">Performance issue of cuBLAS’ batch matmul</h3>
+
+<p>Firstly, we make a theoretical FLOPs analysis over the batch matmul kernels. The results are quite interesting: all the batch matmul have limited computation intensity (less than 1 TFLOPs).</p>
+
+<p>Then we profile the cuBLAS performance of batch matmul with multiple shapes through nvprof. The table below shows some of the metrics obtained on a NVIDIA M40 GPU with CUDA8.0.</p>
+
+<table>
+ <thead>
+ <tr>
+ <th>input shape <br /> [batch, M, N, K]</th>
+ <th>kernel</th>
+ <th>theoretical FLOPs</th>
+ <th>nvprof observed FLOPs</th>
+ <th>theoretical FLOPs / <br /> observed FLOPs</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td>[512, 17, 17, 128]</td>
+ <td><strong>maxwell_sgemmBatched_128x128_raggedMn_tn</strong></td>
+ <td>18939904</td>
+ <td>2155872256</td>
+ <td>0.87%</td>
+ </tr>
+ <tr>
+ <td>[512, 1, 17, 128]</td>
+ <td><strong>maxwell_sgemmBatched_128x128_raggedMn_tn</strong></td>
+ <td>1114112</td>
+ <td>2155872256</td>
+ <td>0.052%</td>
+ </tr>
+ <tr>
+ <td>[512, 17, 1, 128]</td>
+ <td><strong>maxwell_sgemmBatched_128x128_raggedMn_tn</strong></td>
+ <td>1114112</td>
+ <td>2155872256</td>
+ <td>0.052%</td>
+ </tr>
+ <tr>
+ <td>[512, 30, 30, 128]</td>
+ <td><strong>maxwell_sgemmBatched_128x128_raggedMn_tn</strong></td>
+ <td>58982400</td>
+ <td>2155872256</td>
+ <td>2.74%</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>Even with different shapes (varing in M, N, K), all the <strong>maxwell_sgemmBatched_128x128_raggedMn_tn</strong> calls execute the same amount of FLOPs, which is much bigger than the theoretical value. It can be inferred that all these different shapes may be padded to a certain shape. Among all these shapes, even in the best case, the theoretical FLOPs is still only 2.74% of the actually executed FLOPs, <em>therefore most of the computation is quite redundant</em>. Similarly, the ca [...]
+
+<p><b>It is obvious that cuBLAS’ batch matmul implementation is far from efficiency. Thus we use TVM to generate efficient batch matmul kernels for our NMT workloads.</b></p>
+
+<h2 id="batch-matmul-computation">Batch matmul computation</h2>
+
+<p>In TVM, a general batch matmul computation can be declared as:</p>
+
+<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code># computation representation
+A = tvm.placeholder((batch, M, K), name='A')
+B = tvm.placeholder((batch, K, N), name='B')
+k = tvm.reduce_axis((0, K), 'k')
+C = tvm.compute((batch, M, N),
+ lambda b, y, x: tvm.sum(A[b, y, k] * B[b, k, x], axis = k),
+ name = 'C')
+</code></pre></div></div>
+
+<h2 id="schedule-optimization">Schedule optimization</h2>
+
+<p>After declaring the computation, we need to devise our own schedule carefully to squeeze performance potential.</p>
+
+<h3 id="tuning-parameters-of-blockthread-numbers">Tuning parameters of block/thread numbers</h3>
+
+<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code> # thread indices
+ block_y = tvm.thread_axis("blockIdx.y")
+ block_x = tvm.thread_axis("blockIdx.x")
+ thread_y = tvm.thread_axis((0, num_thread_y), "threadIdx.y")
+ thread_x = tvm.thread_axis((0, num_thread_x), "threadIdx.x")
+ thread_yz = tvm.thread_axis((0, vthread_y), "vthread", name="vy")
+ thread_xz = tvm.thread_axis((0, vthread_x), "vthread", name="vx")
+
+ # block partitioning
+ BB, FF, MM, PP = s[C].op.axis
+ BBFF = s[C].fuse(BB, FF)
+ MMPP = s[C].fuse(MM, PP)
+ by, ty_block = s[C].split(BBFF, factor = num_thread_y * vthread_y)
+ bx, tx_block = s[C].split(MMPP, factor = num_thread_x * vthread_x)
+ s[C].bind(by, block_y)
+ s[C].bind(bx, block_x)
+ vty, ty = s[C].split(ty_block, nparts = vthread_y)
+ vtx, tx = s[C].split(tx_block, nparts = vthread_x)
+ s[C].reorder(by, bx, vty, vtx, ty, tx)
+ s[C].reorder(by, bx, ty, tx)
+ s[C].bind(ty, thread_y)
+ s[C].bind(tx, thread_x)
+ s[C].bind(vty, thread_yz)
+ s[C].bind(vtx, thread_xz)
+</code></pre></div></div>
+<p>We fuse the outer dimensions of the batch matmul, i.e. the BB and FF of the op’s dimension, normally known as “batch” dimension in batch matmul computation. Then we split the outer and the inner dimensions by a factor of (<code class="highlighter-rouge">number_thread * vthread</code>).</p>
+
+<p>Strided pattern is not needed in batch matmul, thus the virtual thread number (<code class="highlighter-rouge">vthread_y</code> and <code class="highlighter-rouge">vthread_x</code>) are both set to 1.</p>
+
+<h4 id="finding-the-best-combination-of-number_thread">Finding the best combination of number_thread</h4>
+
+<p>The results below are obtained on a NVIDIA M40 GPU device with CUDA8.0.</p>
+
+<table>
+ <thead>
+ <tr>
+ <th>Input Shape [batch,features,M,N,K]</th>
+ <th>num_thread_y, num_thread_x</th>
+ <th>num_vthread_y, num_vthread_x</th>
+ <th>Time(us)</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td>[64,8,1,17,128]</td>
+ <td>8,1</td>
+ <td>32,1</td>
+ <td>37.62</td>
+ </tr>
+ <tr>
+ <td>[64,8,1,17,128]</td>
+ <td>4,1</td>
+ <td>32,1</td>
+ <td>39.30</td>
+ </tr>
+ <tr>
+ <td>[64,8,1,17,128]</td>
+ <td>1,1</td>
+ <td>32,1</td>
+ <td>38.82</td>
+ </tr>
+ <tr>
+ <td>[64,8,1,17,128]</td>
+ <td>1,1</td>
+ <td>256,1</td>
+ <td>41.95</td>
+ </tr>
+ <tr>
+ <td>[64,8,1,17,128]</td>
+ <td>32,1</td>
+ <td>1,1</td>
+ <td>94.61</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>As learned from <a href="http://tvmlang.org/2017/08/22/Optimize-Deep-Learning-GPU-Operators-with-TVM-A-Depthwise-Convolution-Example.html">past experience</a>, the method to find the best combination of <code class="highlighter-rouge">num_thread_y</code> and <code class="highlighter-rouge">num_thread_x</code> is through brute-force search. After a brute-force search, the best combination for current shape can be found, which in current computation is <code class="highlighter-rouge">nu [...]
+
+<h2 id="fuse-batch-matmul-with-other-operations">Fuse batch matmul with other operations</h2>
+
+<p>Normally, the existing “black-box” cuBLAS library calls play the role as the boundary of the normally used “op fusion” optimization tactics. However, with the generated efficient batch matmul kernel, the fusion boundary can be easily broken, more than just element-wise operations can be fused, thus futher performance improvement can be obtained.</p>
+
+<p>It is observed from the the computation graph that a batch matmul is always followed by a <em>broadcast add</em> operation or a <em>transpose</em> operation. By fusing “add” or “transpose” operation with batch matmul, kernel launch overhead and redundant memory access time can be reduced.</p>
+
+<p>Batch matmul and broadcast add fusion computation can be declared as follows:</p>
+
+<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code># computation representation
+A = tvm.placeholder((batch_size, features, M, K), name='A')
+# the shape of B is (N, K) other than (K, N) is because B is transposed is this fusion pattern
+B = tvm.placeholder((batch_size, features, N, K), name='B')
+ENTER = tvm.placeholder((batch_size, 1, M, N), name = 'ENTER')
+k = tvm.reduce_axis((0, K), 'k')
+C = tvm.compute(
+ (batch_size, features, M, N),
+ lambda yb, yf, m, x: tvm.sum(A[yb, yf, m, k] * B[yb, yf, x, k], axis = k),
+ name = 'C')
+D = topi.broadcast_add(C, ENTER)
+</code></pre></div></div>
+
+<p>Batch matmul and transpose fusion computation can be declared as:</p>
+
+<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code># computation representation
+A = tvm.placeholder((batch_size, features, M, K), name='A')
+B = tvm.placeholder((batch_size, features, K, N), name='B')
+k = tvm.reduce_axis((0, K), 'k')
+C = tvm.compute(
+ (batch_size, M, features, N),
+ lambda yb, m, yf, x: tvm.sum(A[yb, yf, m, k] * B[yb, yf, k, x], axis = k),
+ name = 'C')
+</code></pre></div></div>
+<h3 id="fusion-kernel-performance">Fusion Kernel Performance</h3>
+
+<p>The shape of [batch=64, heads=8, M=1, N=17, K=128] is chosen to elaborate the performance of the generated code. 17 is chosen as the sequence length since it is the average input length in our production scenarios.</p>
+
+<ul>
+ <li>tf-r1.4 <code class="highlighter-rouge">BatchMatmul</code>: 513.9 us</li>
+ <li>tf-r1.4 <code class="highlighter-rouge">BatchMatmul</code> + <code class="highlighter-rouge">Transpose</code> (separate): 541.9 us</li>
+ <li>TVM <code class="highlighter-rouge">BatchMatmul</code>: 37.62 us</li>
+ <li>TVM <code class="highlighter-rouge">BatchMatmul</code> + <code class="highlighter-rouge">Transpose</code> (fused): 38.39 us</li>
+</ul>
+
+<p>The kernel fusion optimization brings a further <b><em>1.7X</em></b> speed-up.</p>
+
+<h2 id="integration-with-tensorflow">Integration with Tensorflow</h2>
+
+<p>The input shape of batch matmul in our workload is finite and can be enumerated easily in advance. With those pre-defined shapes, we can generate highly optimized CUDA kernel ahead of time (fixed shape computation could bring the best optimization potential). Meanwhile, a general batch matmul kernel suitable for most of the shapes will also be generated to provide a fall-back machanism for the shapes which does not have a corresponding ahead-of-time generated kernel.</p>
+
+<p>The generated efficient kernels for specific shapes and the fall-back one are integrated into the Tensorflow framework. We develop fused ops, such as BatchMatMulTranspose or BatchMatMulAdd, to launch the specific generated kernel using TVM’s runtime API for certain input shape or invoke the fall-back kernel. A graph optimization pass is conducted to automatically replace the origin batch <em>matmul + add/transpose</em> pattern with the fused ops. Meanwhile, by combining a more aggress [...]
+
+<h2 id="summary">Summary</h2>
+<p>Inside Alibaba, we found that TVM is a very productive tool to develop high performance GPU kernels to meet our in-house requirements. In this blog, NMT Transformer model is taken as an example to illustrate our optimization strategy with TVM. Firstly, we locate the hot-spot of Transformer model through first-principle analysis. Then we use TVM to generate highly optimized CUDA kernel to replace cuBLAS version (<b><em>13X</em></b> speed-up is observed). Next, we leverage TVM’s kernel [...]
+
+<h2 id="resources">Resources</h2>
+<ul>
+ <li><a href="https://github.com/Orion34C/tvm-batch-matmul-example/blob/master/tvm_batch_matmul_transpose_m1_kX.py">TVM implementation of fused batch matmul + transpose computation</a></li>
+</ul>
+
+<h2 id="references">References</h2>
+<p>[1] <a href="https://arxiv.org/pdf/1706.03762.pdf">Attention is All You Need</a></p>
+
+<p>[2] <a href="https://devblogs.nvidia.com/cuda-pro-tip-nvprof-your-handy-universal-gpu-profiler/">nvprof is Your Handy Universal GPU Profiler</a></p>
+
+<p>[3] <a href="https://github.com/tensorflow/tensorflow/pull/16306">Add Loop Invariant Node Motion Optimization in GraphOptimizer</a></p>
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diff --git a/2018/07/12/vta-release-announcement.html b/2018/07/12/vta-release-announcement.html
new file mode 100644
index 0000000..08c2b6e
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+ <h1>VTA: An Open, Customizable Deep Learning Acceleration Stack </h1>
+ <p class="post-meta">
+ <time datetime="2018-07-12T00:00:00-07:00" itemprop="datePublished">
+ Jul 12, 2018
+ </time>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p style="text-align: center">Thierry Moreau(VTA architect), Tianqi Chen(TVM stack), Ziheng Jiang†(graph compilation), Luis Vega(cloud deployment)</p>
+<p style="text-align: center">Advisors: Luis Ceze, Carlos Guestrin, Arvind Krishnamurthy</p>
+<p style="text-align: center">Paul G. Allen School of Computer Science & Engineering, University of Washington</p>
+
+<p>Hardware acceleration is an enabler for ubiquitous and efficient deep learning. With hardware accelerators appearing in the datacenter and edge devices, hardware specialization has taken on a prominent role in the deep learning system stack.</p>
+
+<p>We are excited to announce the launch of the Versatile Tensor Accelerator (VTA, pronounced <em>vita</em>), an open, generic, and customizable deep learning accelerator design. VTA is a programmable accelerator that exposes a RISC-like programming abstraction to describe tensor-level operations. We designed VTA to expose the most salient and common characteristics of mainstream deep learning accelerators, such as tensor operations, DMA load/stores, and explicit compute/memory arbitration.</p>
+
+<p>VTA is more than a standalone accelerator design: it’s an end-to-end solution that includes drivers, a JIT runtime, and an optimizing compiler stack based on TVM. The current release includes a behavioral hardware simulator, as well as the infrastructure to deploy VTA on low-cost FPGA hardware for fast prototyping. By extending the TVM stack with a customizable, and open source deep learning hardware accelerator design, we are exposing a transparent end-to-end deep learning stack from [...]
+
+<p style="text-align: center"><img src="https://raw.githubusercontent.com/uwsaml/web-data/master/vta/blogpost/vta_stack.png" alt="image" width="50%" /></p>
+
+<p>The VTA and TVM stack together constitute a blueprint for end-to-end, accelerator-centric deep learning system that can:</p>
+
+<ul>
+ <li>Provide an open deep learning system stack for hardware, compilers, and systems researchers alike to incorporate optimizations and co-design techniques.</li>
+ <li>Lower the barrier of entry for machine learning practitioners to experiment with novel network architectures, operators and data representations that require specialized hardware support.</li>
+</ul>
+
+<h2 id="use-case-scenarios-for-researchers">Use-Case Scenarios for Researchers</h2>
+
+<p>We highlight ways in which the VTA design together with a complete TVM software stack can enable novel opportunities across hardware, compilers, and deep learning research.</p>
+
+<h3 id="hardware-designers-and-computer-architects">Hardware Designers and Computer Architects</h3>
+
+<p>With new ASIC designs being regularly announced, providing a complete and usable software stack on top of novel hardware is essential to gain a competitive edge both in research circles, and commercially.
+Our VTA release provides a reference TVM software stack built for hardware accelerators.
+We hope to empower hardware designers to quickly build and deploy optimized deep learning libraries ready to be utilized by high-level frameworks of the likes of TensorFlow or PyTorch.
+Software support is essential for performing full-system evaluation to understand the limits and performance bottlenecks in hardware-accelerated systems.
+With the use of FPGAs as hardware deployment backends, we provide a complete solution for rapid and iterative hardware design prototyping.
+Finally, our vision is to see VTA grow into an collection of hardware designs, eventually leading to an open ecosystem of custom hardware accelerators.</p>
+
+<p style="text-align: center"><img src="https://www.acm.org/binaries/content/gallery/acm/ctas/publications/artifact-badges.jpg/artifact-badges.jpg/acm%3Adesktopcta" alt="image" width="20%" /></p>
+
+<p>In addition, VTA is one of the first hardware-software reproducible <a href="http://ctuning.org/ae/">ACM artifacts</a>, which can serve as a template for reproducible deep learning architecture research.
+The VTA artifact deployable using <a href="http://cknowledge.org/">CK</a>, was presented at ReQuEST 2018, co-located with <a href="http://cknowledge.org/request-cfp-asplos2018.html">ASPLOS</a>.</p>
+
+<h3 id="optimizing-compilers-researchers">Optimizing Compilers Researchers</h3>
+
+<p>Novel intermediate representations and optimizing compilers of the likes of TVM have been proposed to better take advantage of deep learning workloads characteristics.
+VTA complements TVM to provide accelerator-centric optimization passes, and low-level code generation. Our open-source deep learning compiler stack also aims to emulate the success of LLVM, by allowing the community to improve accelerator-centric compiler support over time, particularly as more hardware variants of VTA emerge.
+The extendability of the compiler stack, combined with the ability to modify the architecture and the programming interface of the hardware back-end should lead to exciting opportunities in hardware-software co-design for deep learning.</p>
+
+<h3 id="deep-learning-researchers">Deep Learning Researchers</h3>
+
+<p>A transparent and customizable software and hardware stack empowers deep learning researchers to come up with novel neural network operators, and data representations, all the while enabling the complete evaluation of those optimizations on end-to-end systems. Techniques like binarization are currently limited to CPU and GPU evaluations, unless significant engineering resources are dedicated to produce an FPGA or ASIC design that can evaluate the technique’s full energy savings potent [...]
+
+<h2 id="technical-details">Technical Details</h2>
+
+<h3 id="stack-overview">Stack Overview</h3>
+
+<p>The VTA deep learning accelerator and TVM stack can bridge the gap between productivity-oriented deep learning frameworks, and performance-focused hardware substrates, such as FPGAs.</p>
+<ul>
+ <li>NNVM, the graph-level optimizer, provides a graph-level Intermediate Representation (IR) used as a common language between different deep learning frameworks to take advantage of graph-level optimizations, such as operator fusion. The NNVM IR is also used to specify data layout and data format constraints: e.g. tiling for tensorization, and bit-packing for ultra-low precision computing.</li>
+ <li>TVM, the tensor-level optimizer, builds upon the Halide DSL and schedule primitives to provide an optimizing compiler capable of bringing performance portability for deep learning across hardware back-ends. TVM brings novel scheduling primitives that target specialized hardware accelerators, such as tensorization, which lowers computation onto specialized tensor-tensor hardware instructions. In addition, it provides schedule primitives and lowering rules that allow for explicit mem [...]
+ <li>The VTA runtime performs JIT compilation of VTA binaries (instruction streams and micro-kernel code), manages shared memory, and performs synchronization to hand off execution to VTA. The VTA runtime presents an API that looks generic to TVM, to hide complexities of platform-specific bookkeeping tasks. It exposes a C++ API that a TVM module can call into - this simplifies the future inclusion of other hardware accelerator designs, without having to drastically modify the upper TVM [...]
+ <li>VTA’s two-level ISA provides both (1) a high-level CISC ISA that describes variable latency operations such as DMA loads, or deep learning operators and (2) a low-level, and fixed latency RISC ISA that describe low-level matrix-matrix operations. This two-level ISA allows both code compactness, and expressiveness.</li>
+ <li>Finally, VTA’s micro-architecture provides a flexible deep learning hardware design specification, that can be conveniently compiled onto other FPGA platforms, and eventually in the long term down to ASICs.</li>
+</ul>
+
+<h3 id="vta-hardware-design-overview">VTA Hardware Design Overview</h3>
+
+<p>The Vanilla Tensor Accelerator (VTA) is a generic deep learning accelerator built around a GEMM core, which performs dense matrix multiplication at a high computational throughput.
+The design is inspired by mainstream deep learning accelerators, of the likes of Google’s TPU accelerator. The design adopts decoupled access-execute to hide memory access latency and maximize utilization of compute resources. To a broader extent, VTA can serve as a template deep learning accelerator design, exposing a clean tensor computation abstraction to the compiler stack.</p>
+
+<p style="text-align: center"><img src="https://raw.githubusercontent.com/uwsaml/web-data/master/vta/blogpost/vta_overview.png" alt="image" width="60%" /></p>
+
+<p>The figure above presents a high-level overview of the VTA hardware organization. VTA is composed of four modules that communicate between each other via FIFO queues and single-writer/single-reader SRAM memory blocks, to allow for task-level pipeline parallelism.
+The compute module performs both dense linear algebra computation with its GEMM core, and general computation with its tensor ALU.
+It operates on a register file which instead of storing scalar values, stores tensors of rank 1 or 2.
+The micro-op cache stores low-level code that dictates a sequence of operations to mutate the register file.</p>
+
+<p>The VTA hardware design template offers modularity to the user, with the option to modify hardware datatypes, memory architecture, the GEMM core dimensions, hardware operators, and pipelining stages.
+Exposing multiple variants of VTA to the compiler stack facilitates the developments of compilers, since we can test TVM’s ability to target an multitude of hardware accelerators, rather than a single design.</p>
+
+<h3 id="vta-prototyping-with-vta-simulator-and-pynq-fpga-board">VTA Prototyping with VTA Simulator and Pynq FPGA Board</h3>
+
+<p>The VTA release allows users to experiment with hardware acceleration, and accelerator-centric compiler optimizations in two ways.
+The first approach, which doesn’t require special hardware is to run deep learning workloads on a behavioral simulator of the VTA design.
+This simulator back-end is readily available for developers to experiment with.
+The second approach relies on an off-the-shelf and low-cost FPGA development board – the <a href="http://www.pynq.io/">Pynq board</a>, which exposes a reconfigurable FPGA fabric and an ARM SoC.</p>
+
+<p style="text-align: center"><img src="https://raw.githubusercontent.com/uwsaml/web-data/master/vta/blogpost/vta_system.png" alt="image" width="70%" /></p>
+
+<p>The VTA release offers a simple compilation and deployment flow of the VTA hardware design and TVM workloads on the Pynq platform, with the help of an RPC server interface.
+The RPC server handles FPGA reconfiguration tasks and TVM module invocation offloading onto the VTA runtime.
+The VTA runtime system runs on the ARM CPU of the Pynq embedded system, and generates VTA binaries on the fly to offload to the FPGA hardware.
+This complete solution allows for out-of-the-box prototyping on low-cost FPGAs, with an interactive and familiar Python environment, hiding much of the complexity and headaches of FPGA design away from the user.</p>
+
+<p>For programmers familiar with hardware and FPGAs, we expose the VTA design expressed in HLS C, and provide scripts built on top of the Xilinx toolchains to compile the design into an FPGA bitstream.
+We are currently building a repository of VTA variants, so that users can explore different design variants for their deep learning workloads without having to go through the time consuming FPGA compilation process.</p>
+
+<h2 id="performance-assessment">Performance Assessment</h2>
+
+<p><em>VTA is at its early stages of development and we expect more performance improvements and optimizations to come.
+As of now we offer end-to-end performance evaluations on the low-cost Pynq board which incorporates a dated 28nm FPGA fabric.
+While this platform is meant for prototyping (the 2012 FPGA cannot compete with modern ASICs), we are porting VTA to newer high-performance FPGA platforms that will offer more competitive performance.</em></p>
+
+<p><em>We are working on more experiments and will release new results as they are obtained.</em></p>
+
+<h3 id="resource-utilization-on-resnet-18">Resource Utilization on ResNet-18</h3>
+
+<p>A popular method used to assess the efficient use of hardware are roofline diagrams: given a hardware design, how efficiently are different workloads utilizing the hardware compute and memory resources. The roofline plot below shows the throughput achieved on different convolution layers of the ResNet-18 inference benchmark. Each layer has a different arithmetic intensity, i.e. compute to data movement ratio.
+In the left half, convolution layers are bandwidth limited, whereas on the right half, they are compute limited.</p>
+
+<p style="text-align: center"><img src="https://raw.githubusercontent.com/uwsaml/web-data/master/vta/blogpost/vta_roofline.png" alt="image" width="60%" /></p>
+
+<p>The goal behind designing a hardware architecture, and a compiler stack is to bring each workload as close as possible to the roofline of the target hardware.
+The roofline plot shows the effects of having the hardware and compiler work together to maximize utilization of the available hardware resources.
+The technique showcased is latency hiding, which requires explicit dependence tracking at the hardware level, compiler support to partition work, explicit dependence insertion in the instruction stream during code-generation.
+The result is an overall higher utilization of the available compute and memory resources.</p>
+
+<h3 id="end-to-end-resnet-18-evaluation">End to end ResNet-18 evaluation</h3>
+
+<p style="text-align: center"><img src="https://raw.githubusercontent.com/uwsaml/web-data/master/vta/blogpost/vta_e2e.png" alt="image" width="60%" /></p>
+
+<p>A benefit of having a complete compiler stack built for VTA is the ability to run end-to-end workloads. This is compelling in the context of hardware acceleration because we need to understand what performance bottlenecks, and Amdahl limitations stand in the way to obtaining faster performance.
+The bar plot above shows inference performance with and without offloading the ResNet convolutional layers to the FPGA-based VTA design, on the Pynq board’s ARM Cortex A9 SoC.
+At a glance, it iss clear that VTA accomplishing its goal, reducing the time it takes to perform convolutions on the CPU (dark blue).
+However, it becomes apparent that other operators need offloading, as they now constitute a new bottleneck.
+This kind of high-level visibility is essential to system designers who want to understand how systems affect end-to-end performance.</p>
+
+<h2 id="open-source-effort">Open Source Effort</h2>
+<p>VTA is research effort at the Paul G. Allen School Computer Science and Engineering at University of Washington, and is now integrated into the TVM stack. The TVM project follows the Apache open-source model, to create a community maintained project. You are more than welcome to join us and lead the effort.</p>
+
+<h2 id="acknowledgements">Acknowledgements</h2>
+<p>VTA is a research project that came out of the SAML group, which is generously supported by grants from DARPA and the National Science Foundation and gifts from Huawei, Oracle, Intel and anonymous donors.</p>
+
+<h2 id="get-started">Get Started!</h2>
+<ul>
+ <li>TVM and VTA Github page can be found here: <a href="https://github.com/dmlc/tvm">https://github.com/dmlc/tvm</a>.</li>
+ <li>You can get started with easy to follow <a href="https://tvm.apache.org/docs//vta/tutorials/index.html">tutorials on programming VTA with TVM</a>.</li>
+ <li>For more technical details on VTA, read our <a href="https://arxiv.org/abs/1807.04188">VTA technical report</a> on ArXiv.</li>
+</ul>
+
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+ successful ASF projects. While incubation status is not necessarily a reflection of the completeness
+ or stability of the code, it does indicate that the project has yet to be fully endorsed by the ASF.
+
+ Copyright © 2020 The Apache Software Foundation. Apache TVM, Apache,
+ the Apache feather, and the Apache TVM project logo are either trademarks or registered trademarks of the Apache Software Foundation.
+
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diff --git a/2018/08/10/DLPack-Bridge.html b/2018/08/10/DLPack-Bridge.html
new file mode 100644
index 0000000..9849d29
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+
+<!DOCTYPE html>
+<html lang="en">
+ <head>
+ <meta charset="utf-8">
+ <title>Building a Cross-Framework Deep Learning Compiler via DLPack</title>
+
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+ <h1>Building a Cross-Framework Deep Learning Compiler via DLPack </h1>
+ <p class="post-meta">
+ <time datetime="2018-08-10T00:00:00-07:00" itemprop="datePublished">
+ Aug 10, 2018
+ </time>
+
+ • <span itemprop="author" itemscope itemtype="http://schema.org/Person">
+ <span itemprop="name">Eddie Yan</span>
+ </span>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p>Deep learning frameworks such as Tensorflow, PyTorch, and ApacheMxNet provide a
+powerful toolbox for quickly prototyping and deploying deep learning models.
+Unfortunately, their ease-of-use has often come at the cost of fragmentation: it
+is only easy to use each framework in isolation. Vertical integration has made
+development streamlined for common use cases, but venturing off of the beaten
+path can be tricky.</p>
+
+<p>One scenario that is poorly supported is passing tensors
+<em>directly</em> from one framework to another in memory, without any data duplication
+or copies. Supporting such a use case would enable users to string together
+pipelines where certain operators are better supported in one framework (or
+faster) than another efficiently. A shared data representation between
+frameworks would also bridge this gap, and allow compiler stacks to target a
+single format when generating code for operators.</p>
+
+<p><a href="https://github.com/dmlc/dlpack">DLPack</a> is an intermediate in-memory
+representation standard for tensor data structures. With DLPack as a common
+representation, we can leverage TVM in scripts written for frameworks that
+traditionally could only rely on vendor-provided libraries. TVM packed functions
+can operate on DLPack tensors, providing wrappers bridging tensor data
+structures from frameworks such as PyTorch and MxNet <em>with zero-data-copy</em>.</p>
+
+<p>DLPack presents a simple, portable in-memory data structure:</p>
+<div class="language-c highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="cm">/*!
+ * \brief Plain C Tensor object, does not manage memory.
+ */</span>
+<span class="k">typedef</span> <span class="k">struct</span> <span class="p">{</span>
+ <span class="cm">/*!
+ * \brief The opaque data pointer points to the allocated data.
+ * This will be CUDA device pointer or cl_mem handle in OpenCL.
+ * This pointer is always aligns to 256 bytes as in CUDA.
+ */</span>
+ <span class="kt">void</span><span class="o">*</span> <span class="n">data</span><span class="p">;</span>
+ <span class="cm">/*! \brief The device context of the tensor */</span>
+ <span class="n">DLContext</span> <span class="n">ctx</span><span class="p">;</span>
+ <span class="cm">/*! \brief Number of dimensions */</span>
+ <span class="kt">int</span> <span class="n">ndim</span><span class="p">;</span>
+ <span class="cm">/*! \brief The data type of the pointer*/</span>
+ <span class="n">DLDataType</span> <span class="n">dtype</span><span class="p">;</span>
+ <span class="cm">/*! \brief The shape of the tensor */</span>
+ <span class="kt">int64_t</span><span class="o">*</span> <span class="n">shape</span><span class="p">;</span>
+ <span class="cm">/*!
+ * \brief strides of the tensor,
+ * can be NULL, indicating tensor is compact.
+ */</span>
+ <span class="kt">int64_t</span><span class="o">*</span> <span class="n">strides</span><span class="p">;</span>
+ <span class="cm">/*! \brief The offset in bytes to the beginning pointer to data */</span>
+ <span class="kt">uint64_t</span> <span class="n">byte_offset</span><span class="p">;</span>
+<span class="p">}</span> <span class="n">DLTensor</span><span class="p">;</span>
+</code></pre></div></div>
+
+<p>As an example, we declare and compile a matrix multiplication operator in TVM,
+and build a wrapper that uses the DLPack representation to allow this operator
+to support PyTorch tensors. We also repeat this demonstration with MxNet. This
+extension allows machine learning developers to quickly port research code to
+relatively unsupported hardware platforms without sacrificing performance.</p>
+
+<p>Illustration of how DLPack provides an intermediate wrapper that is shared
+between frameworks and TVM:</p>
+<p style="text-align: center"><img src="/images/pytorch-dlpack/dlpack.png" alt="image" width="65%" /><br />
+Figure 1</p>
+
+<p>First, we compute a reference output in PyTorch:</p>
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code> <span class="kn">import</span> <span class="nn">torch</span>
+ <span class="n">x</span> <span class="o">=</span> <span class="n">torch</span><span class="o">.</span><span class="n">rand</span><span class="p">(</span><span class="mi">56</span><span class="p">,</span><span class="mi">56</span><span class="p">)</span>
+ <span class="n">y</span> <span class="o">=</span> <span class="n">torch</span><span class="o">.</span><span class="n">rand</span><span class="p">(</span><span class="mi">56</span><span class="p">,</span><span class="mi">56</span><span class="p">)</span>
+ <span class="n">z</span> <span class="o">=</span> <span class="n">x</span><span class="o">.</span><span class="n">mm</span><span class="p">(</span><span class="n">y</span><span class="p">)</span>
+</code></pre></div></div>
+
+<p>We then define and build a TVM matrix multiplication operator, using the default
+schedule:</p>
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code> <span class="n">n</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">convert</span><span class="p">(</span><span class="mi">56</span><span class="p">)</span>
+ <span class="n">X</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><span class="n">n</span><span class="p">,</span><span class="n">n</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'X'</span><span class="p">)</span>
+ <span class="n">Y</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><span class="n">n</span><span class="p">,</span><span class="n">n</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'Y'</span><span class="p">)</span>
+
+ <span class="n">k</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">n</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'k'</span><span class="p">)</span>
+ <span class="n">Z</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">((</span><span class="n">n</span><span class="p">,</span><span class="n">n</span><span class="p">),</span> <span class="k">lambda</span> <span class="n">i</span><span class="p">,</span><span class="n">j</span> <span class="p">:</span> <span class="n">tvm</span><span class="o">.</span><span class="nb">sum</span><span class="p">(</span><span [...]
+ <span class="n">s</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">create_schedule</span><span class="p">(</span><span class="n">Z</span><span class="o">.</span><span class="n">op</span><span class="p">)</span>
+ <span class="n">fmm</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">build</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="p">[</span><span class="n">X</span><span class="p">,</span> <span class="n">Y</span><span class="p">,</span> <span class="n">Z</span><span class="p">],</span> <span class="n">target_host</span><span class="o">=</span><span class="s">'llvm'</span><span class="p">,</span> < [...]
+</code></pre></div></div>
+<p>For brevity, we do not cover TVM’s large collection of scheduling primitives
+that we can use to optimize matrix multiplication. If you wish to make a custom
+GEMM operator run <em>fast</em> on your hardware device, a detailed tutorial can be
+found <a href="https://tvm.apache.org/docs//tutorials/optimize/opt_gemm.html">here</a>.</p>
+
+<p>We then convert the TVM function into one that supports PyTorch tensors:</p>
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code> <span class="kn">from</span> <span class="nn">tvm.contrib.dlpack</span> <span class="kn">import</span> <span class="n">to_pytorch_func</span>
+ <span class="c1"># fmm is the previously built TVM function (Python function)
+</span> <span class="c1"># fmm is the wrapped TVM function (Python function)
+</span> <span class="n">fmm_pytorch</span> <span class="o">=</span> <span class="n">to_pytorch_func</span><span class="p">(</span><span class="n">fmm</span><span class="p">)</span>
+ <span class="n">z2</span> <span class="o">=</span> <span class="n">torch</span><span class="o">.</span><span class="n">empty</span><span class="p">(</span><span class="mi">56</span><span class="p">,</span><span class="mi">56</span><span class="p">)</span>
+ <span class="n">fmm_pytorch</span><span class="p">(</span><span class="n">x</span><span class="p">,</span> <span class="n">y</span><span class="p">,</span> <span class="n">z2</span><span class="p">)</span>
+ <span class="n">np</span><span class="o">.</span><span class="n">testing</span><span class="o">.</span><span class="n">assert_allclose</span><span class="p">(</span><span class="n">z</span><span class="o">.</span><span class="n">numpy</span><span class="p">(),</span> <span class="n">z2</span><span class="o">.</span><span class="n">numpy</span><span class="p">())</span>
+</code></pre></div></div>
+<p>and verify that the results match.</p>
+
+<p>We can repeat the same example, but using MxNet instead:</p>
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code> <span class="kn">import</span> <span class="nn">mxnet</span>
+ <span class="kn">from</span> <span class="nn">tvm.contrib.mxnet</span> <span class="kn">import</span> <span class="n">to_mxnet_func</span>
+ <span class="n">ctx</span> <span class="o">=</span> <span class="n">mxnet</span><span class="o">.</span><span class="n">cpu</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span>
+ <span class="n">x</span> <span class="o">=</span> <span class="n">mxnet</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">uniform</span><span class="p">(</span><span class="n">shape</span><span class="o">=</span><span class="p">(</span><span class="mi">56</span><span class="p">,</span><span class="mi">56</span><span class="p">),</span> <span class="n">ctx</span><span class="o">=</span><span class="n">ctx</span><span class="p">)</span>
+ <span class="n">y</span> <span class="o">=</span> <span class="n">mxnet</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">uniform</span><span class="p">(</span><span class="n">shape</span><span class="o">=</span><span class="p">(</span><span class="mi">56</span><span class="p">,</span><span class="mi">56</span><span class="p">),</span> <span class="n">ctx</span><span class="o">=</span><span class="n">ctx</span><span class="p">)</span>
+ <span class="n">z</span> <span class="o">=</span> <span class="n">mxnet</span><span class="o">.</span><span class="n">nd</span><span class="o">.</span><span class="n">empty</span><span class="p">(</span><span class="n">shape</span><span class="o">=</span><span class="p">(</span><span class="mi">56</span><span class="p">,</span><span class="mi">56</span><span class="p">),</span> <span class="n">ctx</span><span class="o">=</span><span class="n">ctx</span><span class="p">)</span>
+ <span class="n">f</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">build</span><span class="p">(</span><span class="n">s</span><span class="p">,</span> <span class="p">[</span><span class="n">X</span><span class="p">,</span> <span class="n">Y</span><span class="p">,</span> <span class="n">Z</span><span class="p">],</span> <span class="n">target_host</span><span class="o">=</span><span class="s">'llvm'</span><span class="p">,</span> <sp [...]
+ <span class="n">f_mxnet</span> <span class="o">=</span> <span class="n">to_mxnet_func</span><span class="p">(</span><span class="n">f</span><span class="p">)</span>
+ <span class="n">f_mxnet</span><span class="p">(</span><span class="n">x</span><span class="p">,</span> <span class="n">y</span><span class="p">,</span> <span class="n">z</span><span class="p">)</span>
+ <span class="n">np</span><span class="o">.</span><span class="n">testing</span><span class="o">.</span><span class="n">assert_allclose</span><span class="p">(</span><span class="n">z</span><span class="o">.</span><span class="n">asnumpy</span><span class="p">(),</span> <span class="n">x</span><span class="o">.</span><span class="n">asnumpy</span><span class="p">()</span><span class="o">.</span><span class="n">dot</span><span class="p">(</span><span class="n">y</span><span class="o">. [...]
+</code></pre></div></div>
+
+<h2 id="under-the-hood-of-the-pytorch-example">Under the hood of the PyTorch Example</h2>
+<p>As TVM provides <a href="https://github.com/dmlc/tvm/blob/master/include/tvm/runtime/c_runtime_api.h#L455">functions</a> to convert dlpack tensors to tvm <code class="highlighter-rouge">NDArray</code>s and
+vice-versa, so all that is needed is some syntactic sugar by wrapping functions.
+<code class="highlighter-rouge">convert_func</code> is a generic converter for frameworks using tensors with dlpack
+support, and can be used to implement convenient converters, such as
+<code class="highlighter-rouge">to_pytorch_func</code>.</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="k">def</span> <span class="nf">convert_func</span><span class="p">(</span><span class="n">tvm_func</span><span class="p">,</span> <span class="n">tensor_type</span><span class="p">,</span> <span class="n">to_dlpack_func</span><span class="p">):</span>
+ <span class="k">assert</span> <span class="nb">callable</span><span class="p">(</span><span class="n">tvm_func</span><span class="p">)</span>
+
+ <span class="k">def</span> <span class="nf">_wrapper</span><span class="p">(</span><span class="o">*</span><span class="n">args</span><span class="p">):</span>
+ <span class="n">args</span> <span class="o">=</span> <span class="nb">tuple</span><span class="p">(</span><span class="n">ndarray</span><span class="o">.</span><span class="n">from_dlpack</span><span class="p">(</span><span class="n">to_dlpack_func</span><span class="p">(</span><span class="n">arg</span><span class="p">))</span>\
+ <span class="k">if</span> <span class="nb">isinstance</span><span class="p">(</span><span class="n">arg</span><span class="p">,</span> <span class="n">tensor_type</span><span class="p">)</span> <span class="k">else</span> <span class="n">arg</span> <span class="k">for</span> <span class="n">arg</span> <span class="ow">in</span> <span class="n">args</span><span class="p">)</span>
+ <span class="k">return</span> <span class="n">tvm_func</span><span class="p">(</span><span class="o">*</span><span class="n">args</span><span class="p">)</span>
+
+ <span class="k">return</span> <span class="n">_wrapper</span>
+
+<span class="k">def</span> <span class="nf">to_pytorch_func</span><span class="p">(</span><span class="n">tvm_func</span><span class="p">):</span>
+ <span class="kn">import</span> <span class="nn">torch</span>
+ <span class="kn">import</span> <span class="nn">torch.utils.dlpack</span>
+ <span class="k">return</span> <span class="n">convert_func</span><span class="p">(</span><span class="n">tvm_func</span><span class="p">,</span> <span class="n">torch</span><span class="o">.</span><span class="n">Tensor</span><span class="p">,</span> <span class="n">torch</span><span class="o">.</span><span class="n">utils</span><span class="o">.</span><span class="n">dlpack</span><span class="o">.</span><span class="n">to_dlpack</span><span class="p">)</span>
+</code></pre></div></div>
+
+ </div>
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+</div>
+</div>
+
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diff --git a/2018/10/03/auto-opt-all.html b/2018/10/03/auto-opt-all.html
new file mode 100644
index 0000000..87f8122
--- /dev/null
+++ b/2018/10/03/auto-opt-all.html
@@ -0,0 +1,590 @@
+
+<!DOCTYPE html>
+<html lang="en">
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+ <title>Automatic Kernel Optimization for Deep Learning on All Hardware Platforms</title>
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+ <div class="span14">
+ <h1>Automatic Kernel Optimization for Deep Learning on All Hardware Platforms </h1>
+ <p class="post-meta">
+ <time datetime="2018-10-03T00:00:00-07:00" itemprop="datePublished">
+ Oct 3, 2018
+ </time>
+
+ • <span itemprop="author" itemscope itemtype="http://schema.org/Person">
+ <span itemprop="name">Lianmin Zheng, Eddie Yan, Tianqi Chen</span>
+ </span>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p>Optimizing the performance of deep neural network on a diverse range of hardware platforms is still a hard
+problem for AI developers. In terms of system support, we are facing a many-to-many problem here:
+deploying trained models from multiple frontends (e.g. Tensorflow, ONNX, MXNet) to multiple
+hardware platforms (e.g. CPU, GPU, Accelerators). The most performance critical part of
+this problem is obtaining high performance kernel implementations for growing model
+architectures and hardware platforms.</p>
+
+<p>To address this challenge, TVM takes a full stack compiler approach.
+TVM combines code generation and automatic program optimization to generate kernels
+that are comparable to heavily hand-optimized libraries,
+obtaining state-of-the-art inference performance on hardware platforms including
+ARM CPUs, Intel CPUs, Mali GPUs, NVIIDA GPUs and AMD GPUs.</p>
+
+<p>In this blog post, we show the workflow of automatic kernel optimization in TVM compiler stack and
+benchmark results on several hardware platforms.</p>
+
+<h1 id="system-overview">System Overview</h1>
+
+<p style="text-align: center"><img src="/images/autotune-all/overview.png" alt="image" width="35%" /></p>
+<center> Figure 1. System Overview </center>
+<p></p>
+
+<p>Kernel optimization in TVM is done in an iterative loop fashion.
+As shown in Figure 1, the automatic kernel optimization takes a neural network (typically in computational graph representation)
+from frontend frameworks as input, and generates kernels for all operators in this network.</p>
+
+<p>The inner loop uses a scalable RPC runtime, machine learning based tuners and a tensor compiler.
+In each round of the loop, the tuner picks a batch of promising candidate kernel implementations from a large search space,
+and profile them on real hardware. Then the tuner gets the profiling results. These profiling results are used as training
+data to fit a prediction model. After fitting the prediction model, the tuner picks the next promising candidates according to the predictions,
+and the loop continues. This way, we search for fast kernels iteratively.</p>
+
+<p>The below figure compares traditional auto-tuning and AutoTVM.
+The major difference is that AutoTVM is</p>
+<ul>
+ <li><strong>Scalable</strong> to heterogenous cluster of devices</li>
+ <li><strong>Learning</strong> to optimize tensor programs with a transferable machine learning cost model</li>
+</ul>
+
+<p>You can refer to our paper[1] for more details.</p>
+
+<p style="text-align: center"><img src="/images/autotune-all/autotvm.png" alt="image" width="50%" /></p>
+<center> Figure 2. Comparison of Traditional Auto-tuning and AutoTVM </center>
+<p></p>
+
+<h2 id="begin-tuning">Begin Tuning</h2>
+<p>For demonstration, we run our optimization for resnet-18 on RK3399, an ARM development board.
+The detailed instructions are omitted due to the space limit of a blog post.
+Links to tutorials for ARM CPU, Mali GPU, NVIDIA GPU, AMD GPU are all available at the end of this blog.</p>
+
+<p>First we get a pre-trained model from MXNet model zoo, and extract tuning tasks from it.</p>
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="kn">from</span> <span class="nn">mxnet.gluon.model_zoo.vision</span> <span class="kn">import</span> <span class="n">get_model</span>
+
+<span class="n">block</span> <span class="o">=</span> <span class="n">get_model</span><span class="p">(</span><span class="s">'resnet18_v1'</span><span class="p">,</span> <span class="n">pretrained</span><span class="o">=</span><span class="bp">True</span><span class="p">)</span>
+<span class="n">net</span><span class="p">,</span> <span class="n">params</span> <span class="o">=</span> <span class="n">nnvm</span><span class="o">.</span><span class="n">frontend</span><span class="o">.</span><span class="n">from_mxnet</span><span class="p">(</span><span class="n">block</span><span class="p">)</span>
+
+<span class="n">tasks</span> <span class="o">=</span> <span class="n">autotvm</span><span class="o">.</span><span class="n">extract_from_graph</span><span class="p">(</span><span class="n">net</span><span class="p">)</span>
+<span class="n">tune_tasks</span><span class="p">(</span><span class="n">tasks</span><span class="p">,</span> <span class="o">**</span><span class="n">tuning_option</span><span class="p">)</span>
+</code></pre></div></div>
+<p>There are 12 different conv2d layers in resnet-18, so we launch 12 tuning tasks.
+For each of them, the tuner makes several hundreds of trials and picks the best one.
+After finishing all tuning tasks, we compile the whole network and generate a single deployable minimal library.
+One sample output is</p>
+
+<div class="highlighter-rouge"><div class="highlight"><pre class="highlight"><code>Extract tasks...
+Tuning...
+[Task 1/12] Current/Best: 22.37/ 52.19 GFLOPS | Progress: (544/1000) | 406.59 s Done.
+[Task 2/12] Current/Best: 6.51/ 18.77 GFLOPS | Progress: (608/1000) | 325.05 s Done.
+[Task 3/12] Current/Best: 4.67/ 24.87 GFLOPS | Progress: (480/1000) | 372.31 s Done.
+[Task 4/12] Current/Best: 11.35/ 46.83 GFLOPS | Progress: (736/1000) | 602.39 s Done.
+[Task 5/12] Current/Best: 1.01/ 19.80 GFLOPS | Progress: (448/1000) | 262.16 s Done.
+[Task 6/12] Current/Best: 2.47/ 23.76 GFLOPS | Progress: (672/1000) | 563.85 s Done.
+[Task 7/12] Current/Best: 14.57/ 33.97 GFLOPS | Progress: (544/1000) | 465.15 s Done.
+[Task 8/12] Current/Best: 1.13/ 17.65 GFLOPS | Progress: (576/1000) | 365.08 s Done.
+[Task 9/12] Current/Best: 14.45/ 22.66 GFLOPS | Progress: (928/1000) | 724.25 s Done.
+[Task 10/12] Current/Best: 3.22/ 15.36 GFLOPS | Progress: (864/1000) | 564.27 s Done.
+[Task 11/12] Current/Best: 11.03/ 32.23 GFLOPS | Progress: (736/1000) | 635.15 s Done.
+[Task 12/12] Current/Best: 8.00/ 21.65 GFLOPS | Progress: (1000/1000) | 1111.81 s Done.
+Compile...
+Upload...
+Evaluate inference time cost...
+Mean inference time (std dev): 162.59 ms (0.06 ms)
+</code></pre></div></div>
+
+<p>The tuning is especially helpful and worth a try if your model has some strange shapes or
+your hardware is customized, as hand-optimized static libraries cannot consider all situations.</p>
+
+<h1 id="benchmark-results">Benchmark Results</h1>
+<p>We pre-tuned some popular networks on our device cluster and released the following benchmark.
+Instructions for reproduction are at the end of this blog.</p>
+
+<p>Comprehensively benchmarking TVM is easy since we have a unified runtime interface.
+However maintaining complete, up-to-date, and correct comparisons against all other platforms is not feasible
+without expert assistance from the developers of many other projects.
+So we put all our numbers in a table, and then provide an incomplete comparison with some other libraries.</p>
+
+<h2 id="comparison">Comparison</h2>
+<p>We validate the effectiveness of our automatic optimization stack by
+comparing with heavily optimized traditional libraries on each platform.</p>
+
+<p>We tested popular image classification networks on ImageNet (3x224x224) dataset with batch size = 1 and data type = float32.
+The reported numbers are time costs per image in milliseconds.</p>
+
+<h3 id="arm-cpu">ARM CPU</h3>
+
+<p>We choose <a href="https://github.com/Tencent/ncnn">NCNN</a>, a widely used, hand-optimized kernel library as baseline.
+It makes extensive use of NEON assembly instructions. For example, the code base contains
+<a href="https://github.com/Tencent/ncnn/blob/master/src/layer/arm/convolution_3x3.h">13k lines of code</a> for only 3x3 convolution layers.
+We reference the benchmark numbers in their project repository.
+As shown in the figure below, TVM outperforms it for all networks on Rasbperry Pi 3B.</p>
+
+<p><img src="/images/autotune-all/arm.png" alt="image" width="90%" /></p>
+
+<h3 id="mali-gpu">Mali GPU</h3>
+
+<p><a href="https://github.com/ARM-software/ComputeLibrary">ARM Compute Library</a> is a vendor provided library that supports Mali GPU (OpenCL) well.
+According to the results, TVM provides stronger performance in ResNet and MobileNet due to advantages in convolutional layers.
+TVM lags behind a bit on vgg-16 because vgg-16 is an old and huge network and has several large dense layers.</p>
+
+<p><img src="/images/autotune-all/mali.png" alt="image" width="90%" /></p>
+
+<h3 id="nvidia-gpu">NVIDIA GPU</h3>
+
+<p>On NVIDIA GPU, <a href="https://developer.nvidia.com/cudnn">CuDNN</a> and <a href="https://developer.nvidia.com/tensorrt">TensorRT</a> are two vendor-provided libraries for training and inference respectively. Since we focus on inference,
+we run our benchmark in the unbatched setting. Another tensor compiler <a href="https://github.com/plaidml/plaidml">PlaidML</a> is also reported as baseline
+as there is a previous benchmark of it compared against a pre-AutoTVM version of TVM.
+We reference its benchmark results from <a href="https://github.com/plaidml/plaidbench">PlaidBench</a>.
+According to the results below, TVM achieves parity with TensorRT performance.</p>
+
+<p><img src="/images/autotune-all/nvidia.png" alt="image" width="90%" /></p>
+
+<h3 id="amd-gpu">AMD GPU</h3>
+
+<p>We also take a quick look at a AMD GPU. TVM supports OpenCL and <a href="https://rocm.github.io/">ROCm</a> backend. We found ROCm is better since
+it is more specialized for AMD GPUs.
+<a href="https://github.com/ROCmSoftwarePlatform/MIOpen">MIOpen</a> is a vendor provided
+kernel library. TVM’s graph runtime can call MIOpen’s kernel implementations directly, so we report
+the baseline performance by using this integration.</p>
+
+<p>We didn’t do any specific optimization for AMD GPU. All computation definition and schedule code for NVIDIA GPU is directly reused.
+As a result, TVM is a little bit slower then MIOpen in most cases.
+We believe there is still room for improvement.</p>
+
+<p><img src="/images/autotune-all/amd.png" alt="image" width="90%" /></p>
+
+<h2 id="all-our-results">All Our Results</h2>
+<p>We tested the following networks on ImageNet (3x224x224) dataset with batch size = 1 and data type = float32.
+The reported numbers are time costs per image in milliseconds.</p>
+
+<table>
+ <thead>
+ <tr>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ <th> </th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td> </td>
+ <td><strong>densenet121</strong></td>
+ <td><strong>inception v3</strong></td>
+ <td><strong>mobilenet</strong></td>
+ <td><strong>mobilenet v2</strong></td>
+ <td><strong>resnet18</strong></td>
+ <td><strong>resnet50</strong></td>
+ <td><strong>squeezenet v1.0</strong></td>
+ <td><strong>squeezenet v1.1</strong></td>
+ <td><strong>vgg16</strong></td>
+ <td><strong>vgg19</strong></td>
+ </tr>
+ <tr>
+ <td><strong>ARM CPU</strong></td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ </tr>
+ <tr>
+ <td>Huawei P20 Pro</td>
+ <td>181.4</td>
+ <td>439.9</td>
+ <td>41.1</td>
+ <td>34.5</td>
+ <td>76.5</td>
+ <td>208.2</td>
+ <td>51.8</td>
+ <td>25.7</td>
+ <td>480.6</td>
+ <td>627.0</td>
+ </tr>
+ <tr>
+ <td>Google Pixel2</td>
+ <td>162.2</td>
+ <td>433.5</td>
+ <td>39.5</td>
+ <td>30.1</td>
+ <td>61.1</td>
+ <td>181.3</td>
+ <td>47.3</td>
+ <td>23.2</td>
+ <td>391.1</td>
+ <td>487.7</td>
+ </tr>
+ <tr>
+ <td>Firefly RK3399</td>
+ <td>335.9</td>
+ <td>1285.9</td>
+ <td>78.6</td>
+ <td>66.7</td>
+ <td>161.2</td>
+ <td>403.8</td>
+ <td>94.6</td>
+ <td>48.5</td>
+ <td>902.9</td>
+ <td>1090.1</td>
+ </tr>
+ <tr>
+ <td>Raspberry Pi 3B</td>
+ <td>609.5</td>
+ <td>2070.4</td>
+ <td>122.2</td>
+ <td>103.7</td>
+ <td>322.5</td>
+ <td>725.8</td>
+ <td>185.1</td>
+ <td>94.1</td>
+ <td>1759.6</td>
+ <td>2118.6</td>
+ </tr>
+ <tr>
+ <td>Xilinx PYNQ</td>
+ <td>2888.3</td>
+ <td>9709.1</td>
+ <td>723.5</td>
+ <td>514.3</td>
+ <td>1234.6</td>
+ <td>3580.5</td>
+ <td>909.9</td>
+ <td>477.3</td>
+ <td><sup>-(Note 1)</sup></td>
+ <td>-</td>
+ </tr>
+ <tr>
+ <td><strong>Mali GPU</strong></td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ </tr>
+ <tr>
+ <td>Mali-T860</td>
+ <td>410.9</td>
+ <td>783.1</td>
+ <td>75.4</td>
+ <td>70.8</td>
+ <td>128.6</td>
+ <td>352.9</td>
+ <td>106.2</td>
+ <td>58.0</td>
+ <td>679.5</td>
+ <td>805.3</td>
+ </tr>
+ <tr>
+ <td><strong>NVIDIA GPU</strong></td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ </tr>
+ <tr>
+ <td>GTX 1080 Ti</td>
+ <td>3.6</td>
+ <td>5.8</td>
+ <td>0.6</td>
+ <td>- <sup>(Note 2) </sup></td>
+ <td>-</td>
+ <td>2.7</td>
+ <td>-</td>
+ <td>-</td>
+ <td>4.0</td>
+ <td>4.6</td>
+ </tr>
+ <tr>
+ <td>GTX TITAN X</td>
+ <td>5.8</td>
+ <td>9.7</td>
+ <td>1.0</td>
+ <td>-</td>
+ <td>-</td>
+ <td>4.3</td>
+ <td>-</td>
+ <td>-</td>
+ <td>6.4</td>
+ <td>7.5</td>
+ </tr>
+ <tr>
+ <td><strong>AMD GPU</strong></td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ </tr>
+ <tr>
+ <td>AMD Vega FE</td>
+ <td>5.7</td>
+ <td>8.8</td>
+ <td>1.0</td>
+ <td>-</td>
+ <td>-</td>
+ <td>4.5</td>
+ <td>-</td>
+ <td>-</td>
+ <td>5.9</td>
+ <td>7.0</td>
+ </tr>
+ <tr>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ <td> </td>
+ </tr>
+ </tbody>
+</table>
+
+<ul>
+ <li>Note 1: Out of memory on this board.</li>
+ <li>Note 2: We didn’t tune some small networks on GPU due to time constraints.
+When profiling data is not available, TVM can use fallback code generation.
+But competitive performance is not guaranteed in this scenario.</li>
+</ul>
+
+<h1 id="conclusion">Conclusion</h1>
+<p>With an expressive code generator and an efficient search algorithm, we are able to
+generate kernels that are comparable to heavily hand-optimized ones.
+Since programmer time is expensive and machine time is getting cheaper,
+we believe automatic optimization with real hardware and data in the loop will be the standard workflow
+for inference deployment. TVM just provides such a solution.</p>
+
+<h2 id="links">Links</h2>
+<p>[1] benchmark: <a href="https://github.com/dmlc/tvm/tree/master/apps/benchmark">https://github.com/dmlc/tvm/tree/master/apps/benchmark</a><br />
+[2] Tutorial on tuning for ARM CPU: <a href="https://tvm.apache.org/docs//tutorials/autotvm/tune_nnvm_arm.html">https://tvm.apache.org/docs//tutorials/autotvm/tune_nnvm_arm.html</a><br />
+[3] Tutorial on tuning for Mobile GPU: <a href="https://tvm.apache.org/docs//tutorials/autotvm/tune_nnvm_mobile_gpu.html">https://tvm.apache.org/docs//tutorials/autotvm/tune_nnvm_mobile_gpu.html</a><br />
+[4] Tutorial on tuning for NVIDIA/AMD GPU: <a href="https://tvm.apache.org/docs//tutorials/autotvm/tune_nnvm_cuda.html">https://tvm.apache.org/docs//tutorials/autotvm/tune_nnvm_cuda.html</a><br />
+[5] Paper about AutoTVM: <a href="https://arxiv.org/abs/1805.08166">Learning to Optimize Tensor Program</a><br />
+[6] Paper about Intel CPU (by AWS contributors) : <a href="https://arxiv.org/abs/1809.02697">Optimizing CNN Model Inference on CPUs</a></p>
+
+
+ </div>
+ </div>
+</div>
+</div>
+
+
+
+
+
+
+
+
+ <div class="container">
+
+ <footer class="small">
+ Apache TVM is an effort undergoing incubation at The Apache Software Foundation (ASF),
+ sponsored by the <i>Apache Incubator</i>. Incubation is required
+ of all newly accepted projects until a further review indicates that the infrastructure,
+ communications, and decision making process have stabilized in a manner consistent with other
+ successful ASF projects. While incubation status is not necessarily a reflection of the completeness
+ or stability of the code, it does indicate that the project has yet to be fully endorsed by the ASF.
+
+ Copyright © 2020 The Apache Software Foundation. Apache TVM, Apache,
+ the Apache feather, and the Apache TVM project logo are either trademarks or registered trademarks of the Apache Software Foundation.
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+
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+ </div>
+ </body>
+</html>
+
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diff --git a/2018/10/09/ml-in-tees.html b/2018/10/09/ml-in-tees.html
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+ <h1>Efficient Privacy-Preserving ML Using TVM </h1>
+ <p class="post-meta">
+ <time datetime="2018-10-09T00:00:00-07:00" itemprop="datePublished">
+ Oct 9, 2018
+ </time>
+
+ • <span itemprop="author" itemscope itemtype="http://schema.org/Person">
+ <span itemprop="name">Nick Hynes</span>
+ </span>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p>This post describes Myelin, a framework for privacy-preserving machine learning in trusted hardware enclaves, and how TVM makes Myelin fast.
+The key idea is that TVM, unlike other popular ML frameworks, compiles models into lightweight, optimized, and dependency-free libraries which can fit into resource constrained enclaves.</p>
+
+<p style="text-align: center"><img src="/images/sgx/tvmfits.png" alt="TVM fits in enclaves" style="width: 80vw; max-width: 600px" /></p>
+
+<p>Give creating a privacy-preserving ML model a try! Check out the <a href="https://github.com/dmlc/tvm/tree/master/apps/sgx">example code</a> available in the TVM repo.</p>
+
+<h1 id="motivation-privacy-preserving-ml">Motivation: Privacy-Preserving ML</h1>
+
+<p>Machine learning models benefit from large and diverse datasets.
+Unfortunately, using such datasets often requires trusting a centralized data aggregator or computation provider.
+For sensitive applications like healthcare and finance this is undesirable as it could compromise patient privacy or divulge trade secrets.
+Recent advances in secure and privacy-preserving computation, including <em>trusted execution environments</em> and <em>differential privacy</em>, offer a way for mutually distrusting parties to efficiently train a machine learning model without compromising the training data.
+We use TVM to make privacy-preserving ML framework fast.</p>
+
+<p style="text-align: center"><img src="/images/sgx/sgx.png" alt="Myelin workflow" style="width: 80vw; max-width: 600px" /></p>
+
+<h2 id="use-cases">Use Cases</h2>
+
+<ul>
+ <li><strong>private MLaaS</strong>: a cloud provider runs their architecture on your data. You get the model outputs, your data stays private, and the cloud provider knows that you can’t steal model.</li>
+ <li><strong>trustworthy ML competitions</strong>: you train a model on contest data. The contest organizer sends private test data to your model and gets verifiable report of accuracy. Your model stays safe until the organizer decides to purchase it. Other participants can‘t cheat by training on test data.</li>
+ <li><strong>training on shared private data</strong>: you (a researcher) want to train a model on several hospitals’ data. Directly sharing is too complicated. Instead, have a “trusted third party” train a privacy-preserving model.</li>
+ <li><a href="http://www.vldb.org/pvldb/vol11/p2086-hynes.pdf"><strong>ML on the Blockchain</strong></a></li>
+</ul>
+
+<h1 id="background">Background</h1>
+
+<p style="text-align: center"><img src="/images/sgx/dpnn.png" alt="sketch of DP deep learning in a TEE" style="width: 80vw; max-width: 400px" /></p>
+
+<h2 id="trusted-execution-environments">Trusted Execution Environments</h2>
+
+<p>A <a href="https://en.wikipedia.org/wiki/Trusted_Computing#Remote_attestation">trusted execution environment</a> (TEE) essentially allows a remote user to provably run code on another person’s machine without revealing the computation to the hardware provider.</p>
+
+<p>More technically, the TEE provides a secure <em>enclave</em> of isolated/encrypted memory and CPU registers; also a trusted source of randomness.
+The TEE can also send a signed attestation of the code that’s loaded so that the remote user can verify that the enclave has been correctly loaded.
+This process, known as remote attestation, can be used to establish a secure communication channel into the enclave .
+The remote user can then provision it with secrets like private keys, model parameters, and training data.</p>
+
+<p>Compared to pure crypto methods like <a href="https://en.wikipedia.org/wiki/Garbled_circuit">secure multi-parity computation (MPC)</a> and <a href="https://en.wikipedia.org/wiki/Homomorphic_encryption#Fully_homomorphic_encryption">fully-homomorphic encryption (FHE)</a>, TEEs are several orders of magnitude faster and support general-purpose computation (i.e. not just arithmetic operations).
+Perhaps the only drawbacks are the additional trust assumptions in the hardware root of trust (a key burned into the processor) and loaded software.</p>
+
+<p>Trust assumptions notwithstanding, TEE technology is becoming increasingly widespread and is playing a major role in practical privacy-preservation.
+In fact, general-purpose TEEs already exist in commodity hardware like <a href="https://software.intel.com/en-us/sgx">Intel SGX</a> and <a href="https://genode.org/documentation/articles/trustzone">ARM TrustZone</a>.
+Additionally, the fully-open source <a href="https://keystone-enclave.org">Keystone enclave</a> is on the way.</p>
+
+<h2 id="differential-privacy">Differential Privacy</h2>
+
+<p style="text-align: center"><img src="/images/sgx/dp.png" alt="DP as false positive/negative" style="width: 80vw; max-width: 500px" /></p>
+
+<p><a href="https://en.wikipedia.org/wiki/Differential_Privacy#Randomized_Response">Differential privacy (DP)</a> provides a formal guarantee that models trained on similar datasets are indistinguishable
+Informally, a user’s privacy is not compromised by choosing to contribute data to a model.</p>
+
+<p>In other words, given the output of an algorithm on two datasets which differ in only a single record, differential privacy upper bounds the probability that an adversary can determine which dataset.
+An algorithm may be made DP using a mechanism which adds noise to the algorithm’s output.
+The amount of noise is calibrated on how much the output depends on any particular inputs.
+If you’re familiar with hypothesis testing, if outcomes A and B each have probability 0.5, applying a DP mechanism is like convolving with a probability distribution: the privacy is in the false positive and false negative rates.
+Since deep learning models tend to generalize well, the amount of noise is often less than might be expected.</p>
+
+<p>Running a DP training algorithm in a TEE ensures that the DP mechanism is faithfully applied.</p>
+
+<h1 id="efficient-privacy-preserving-ml-using-tvm">Efficient Privacy-Preserving ML Using TVM</h1>
+
+<p>One of the primary challenges of working with a TEE is that the code running within does not have access to the untrusted OS.
+This means that the trusted software cannot create threads or perform I.O
+Practically speaking, the result is that numerical libraries like OpenBLAS–much less frameworks like PyTorch and TensorFlow–cannot run directly in enclaves.</p>
+
+<p>TEEs actually have a similar programming model to resource-constrained hardware accelerators.
+This is exactly what TVM is made for!
+In the privacy workflow, a user first defines an entire training graph in the high-level graph specification language.
+TVM them compiles the model and outputs a static library containing optimized numerical kernels which can easily be loaded into a TEE.
+Since the kernels are automatically generated and have strict bounds checking, they expose a low surface area of attack.
+They are supported by a lightweight memory-safe Rust runtime which also may easily be reviewed for safety and correctness.</p>
+
+<p>Of course, safety is most useful when practically applicable.
+Fortunately, TVM modules in enclaves have comparable performance to native CPU-based training.
+By coordinating threads using the untrusted runtime, a single TVM enclave can fully utilize the resources of its host machine.
+Moreover, it’s not difficult to imagine a secure parameter server which orchestrates entire datacenters of enclave-enabled machines.</p>
+
+<p>TVM also provides opportunities for more subtle optimization of privacy-preserving algorithms.
+Indeed, its fine-grained scheduling features allow speedups when using differential privacy.
+For instance, the tightest DP bounds may be obtained from clipping the gradients of each training example and adding noise to each [1].
+In autograd frameworks, this requires forwarding the model for each example in the minibatch (though only one backward pass is needed) [2].
+Using TVM, however, per-example gradient clipping is straightforward: instead of scheduling each weight update as a single reduction over both batch and feature dimensions, the reduction is split into two.
+The reduction over features is followed by clipping and noising, and then the final result is finally summed over examples to obtain the weight update.
+Thus, TVM allows applying differential privacy without introducing overhead greater than what is required by the technique.
+Also, if one really wants to get really fancy, it’s possible to fuse the clipping and noising operations and apply them in-place to further trim down latency and memory usage.</p>
+
+<p>For benchmarks on realistic workloads, please refer to the tech report <a href="https://arxiv.org/abs/1807.06689"><em>Efficient Deep Learning on Multi-Source Private Data</em></a>.
+And, of course, feel free go give the framework a spin in the <a href="https://github.com/dmlc/tvm/tree/master/apps/sgx">TVM SGX example</a>.</p>
+
+<h1 id="conclusion">Conclusion</h1>
+
+<p>The next generation of learning systems will be ushered in by privacy.
+As TEE technology becomes better understood and more widely available, it makes sense to leverage it as a resource for privacy-preserving machine learning and analytics.
+TVM is well poised to facilitate development of this use case in both research and deployment.</p>
+
+<h1 id="bio--acknowledgement">Bio & Acknowledgement</h1>
+
+<p><a href="https://github.com/nhynes">Nick</a> is a PhD student in Prof. Dawn Song’s lab at UC Berkeley.
+His research interest is in the general domain of ML on shared private data, but this is really just an excuse to mess with Rust, security monitors, hardware enclaves, and compilers like TVM.</p>
+
+<p>Thanks to Tianqi Chen for the code reviews!</p>
+
+<h1 id="references">References</h1>
+
+<p>[1] <a href="https://arxiv.org/abs/1607.00133">Deep Learning with Differential Privacy</a><br />
+[2] <a href="https://arxiv.org/pdf/1510.01799v2.pdf">Efficient Per-Example Gradient Computations</a></p>
+
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diff --git a/2018/12/18/lowprecision-conv.html b/2018/12/18/lowprecision-conv.html
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+ <h1>Automating Generation of Low Precision Deep Learning Operators </h1>
+ <p class="post-meta">
+ <time datetime="2018-12-18T00:00:00-08:00" itemprop="datePublished">
+ Dec 18, 2018
+ </time>
+
+ • <span itemprop="author" itemscope itemtype="http://schema.org/Person">
+ <span itemprop="name">Meghan Cowan</span>
+ </span>
+
+ </p>
+ <p class="post-meta">
+ </p>
+ </br>
+ <p>As deep learning models grow larger and more complex, deploying them on low powered phone and IoT
+devices becomes challenging because of their limited compute and energy budgets. A recent trend
+ in deep learning is the use of extremely quantized models that operate on inputs and
+ weights of a few bits, with networks like XNOR-Net, DoReFa-Net, and HWGQ-Net making steady
+progress improving accuracy.</p>
+
+<p>An example of a low precision graph snippet is below. The low precision convolution takes in
+quantized data and bitpacks into the proper data layout for an efficient bitserial convolution.
+The output is in a higher precision and traditional deep learning layers such as batch normalization and ReLu are applied to it, before being re-quantized and sent through another low precision operator.</p>
+
+<p style="text-align: center"><img src="/images/low-precision/workflow.png" alt="image" width="50%" /></p>
+<center> Low precision convolution pipeline.</center>
+<p></p>
+
+<p>Theoretically, low precision operators use less operations than
+floating point operators, leading many to believe they can achieve up tremendous speedups.
+However, deep learning frameworks leverage decades of engineering work through low level
+BLAS and LAPACK libraries that are incredibly well optimized, and CPUs include intrinsic
+instructions to accelerate these tasks. In practice, it is not simple to develop low-level
+operators such as convolutions that are competitive with 8-bit quantized or even floating
+point operators.
+In this post we introduce our approach to automatically generating optimized
+low precision convolutions for CPUs. We declare our low precision operators so that they compute
+on efficiently stored low precision inputs, and describe a schedule that describes a search space
+of implementation parameters. We rely on AutoTVM to quickly search the space and find optimized
+parameters for the particular convolution, precision, and backend.</p>
+
+<h2 id="bitserial-computation-background">Bitserial Computation Background</h2>
+
+<p>The core of low precision models is the bitserial dot product that enables convolution and
+dense operators to be computed using only bitwise operations and popcount.
+ Typically, a dot product is computed by element wise multiplication of two vectors followed by
+ summing all the elements, like the simple example below. If all the data is binary, the input
+ vectors can be packed into single integer, and the dot product can be computed by bitwise-anding
+ the packed inputs and counting the number of 1’s in the result using popcount.
+Note: Depending how the input data is quantized, bitwise-xnor may be used instead of bitwise-and.</p>
+
+<p style="text-align: center"><img src="/images/low-precision/binary-dotproduct.png" alt="image" width="50%" /></p>
+<center> Binary dot product.</center>
+<p></p>
+
+<p>Arbitrary precision dot products can be computed in this fashion by first separating input data
+into bitplanes. Once in this representation we can compute dotproduct by summing weighted binary
+dot products between the bitplanes of A and B. The number of binary dotproducts grows with the
+product of A and B’s precision, so this method is only practical for very low precision data.</p>
+
+<p style="text-align: center"><img src="/images/low-precision/bitserial-dotproduct.png" alt="image" width="50%" /></p>
+<center> Bitserial dot product.</center>
+<p></p>
+
+<h2 id="defining-operators-in-tvm">Defining Operators in TVM</h2>
+<p>Before the computation, input data needs to be bitpacked so that the bitplanes of the input data
+can be accessed and are packed into a supported datatype such as a uint8 or uint32. We provide
+a flexible bitpacking operator that takes arbitrary size input tensors and returns a bitpacked
+tensor where the user specifies which axis the bitplanes should be.</p>
+
+<p style="text-align: center"><img src="/images/low-precision/bitpack.png" alt="image" width="50%" /></p>
+<center> Different bitpacked layouts.</center>
+<p></p>
+
+<p>Once in this bitpacked format the low precision convolution can be computed bitserially.
+For this demo, that data is packed along the input channel and the bitplanes are added to the
+innermost axis, and the data is packed into 32-bit integers. The bitserial convolution is computed
+similar to a normal convolution, but the bitwise-and (&) replaces multiplication, and we use
+popcount to accumulate values in the packed data. The bitplane axes become additional reduction axes
+and compute the binary dot products between different bitplanes of the input and kernel.
+Finally, the output is computed in an unpacked format and in higher precision.</p>
+
+<div class="language-python highlighter-rouge"><div class="highlight"><pre class="highlight"><code><span class="n">Input_bitpacked</span> <span class="o">=</span> <span class="n">bitpack</span><span class="p">(</span><span class="n">Input</span><span class="p">,</span> <span class="n">activation_bits</span><span class="p">,</span> <span class="n">pack_axis</span><span class="o">=</span><span class="mi">3</span><span class="p">,</span> <span class="n">bit_axis</span><span class="o">=</spa [...]
+<span class="n">Weights_bitpacked</span> <span class="o">=</span> <span class="n">bitpack</span><span class="p">(</span><span class="n">Filter</span><span class="p">,</span> <span class="n">weight_bits</span><span class="p">,</span> <span class="n">pack_axis</span><span class="o">=</span><span class="mi">2</span><span class="p">,</span> <span class="n">bit_axis</span><span class="o">=</span><span class="mi">4</span><span class="p">,</span> <span class="n">pack_type</span><span class="o"> [...]
+<span class="n">batch</span><span class="p">,</span> <span class="n">in_height</span><span class="p">,</span> <span class="n">in_width</span><span class="p">,</span> <span class="n">in_channel_q</span><span class="p">,</span> <span class="n">_</span> <span class="o">=</span> <span class="n">Input_bitpacked</span><span class="o">.</span><span class="n">shape</span>
+<span class="n">kernel_h</span><span class="p">,</span> <span class="n">kernel_w</span><span class="p">,</span> <span class="n">_</span><span class="p">,</span> <span class="n">num_filter</span><span class="p">,</span> <span class="n">_</span> <span class="o">=</span> <span class="n">Filter_bitpakced</span><span class="o">.</span><span class="n">shape</span>
+
+<span class="n">stride_h</span><span class="p">,</span> <span class="n">stride_w</span> <span class="o">=</span> <span class="n">stride</span>
+<span class="n">pad_top</span><span class="p">,</span> <span class="n">pad_left</span><span class="p">,</span> <span class="n">pad_down</span><span class="p">,</span> <span class="n">pad_right</span> <span class="o">=</span> <span class="n">get_pad_tuple</span><span class="p">(</span><span class="n">padding</span><span class="p">,</span> <span class="p">(</span><span class="n">kernel_h</span><span class="p">,</span> <span class="n">kernel_w</span><span class="p">))</span>
+
+<span class="c1"># Computing the output shape
+</span><span class="n">out_channel</span> <span class="o">=</span> <span class="n">num_filter</span>
+<span class="n">out_height</span> <span class="o">=</span> <span class="n">simplify</span><span class="p">((</span><span class="n">in_height</span> <span class="o">-</span> <span class="n">kernel_h</span> <span class="o">+</span> <span class="n">pad_top</span> <span class="o">+</span> <span class="n">pad_down</span><span class="p">)</span> <span class="o">//</span> <span class="n">stride_h</span> <span class="o">+</span> <span class="mi">1</span><span class="p">)</span>
+<span class="n">out_width</span> <span class="o">=</span> <span class="n">simplify</span><span class="p">((</span><span class="n">in_width</span> <span class="o">-</span> <span class="n">kernel_w</span> <span class="o">+</span> <span class="n">pad_left</span> <span class="o">+</span> <span class="n">pad_right</span><span class="p">)</span> <span class="o">//</span> <span class="n">stride_w</span> <span class="o">+</span> <span class="mi">1</span><span class="p">)</span>
+<span class="n">pad_before</span> <span class="o">=</span> <span class="p">[</span><span class="mi">0</span><span class="p">,</span> <span class="n">pad_top</span><span class="p">,</span> <span class="n">pad_left</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">0</span><span class="p">]</span>
+<span class="n">pad_after</span> <span class="o">=</span> <span class="p">[</span><span class="mi">0</span><span class="p">,</span> <span class="n">pad_down</span><span class="p">,</span> <span class="n">pad_right</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">0</span><span class="p">]</span>
+<span class="n">Input_padded</span> <span class="o">=</span> <span class="n">pad</span><span class="p">(</span><span class="n">Input_bitpacked</span><span class="p">,</span> <span class="n">pad_before</span><span class="p">,</span> <span class="n">pad_after</span><span class="p">,</span> <span class="n">name</span><span class="o">=</span><span class="s">"PaddedInput"</span><span class="p">)</span>
+
+<span class="c1"># Treat the bitplane axes like additional reduction axes
+</span><span class="n">rc</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">in_channel_q</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'rc'</span><span class="p">)</span>
+<span class="n">ry</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">kernel_h</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'ry'</span><span class="p">)</span>
+<span class="n">rx</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">kernel_w</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'rx'</span><span class="p">)</span>
+<span class="n">ib</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">input_bits</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'ib'</span><span class="p">)</span>
+<span class="n">wb</span> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">reduce_axis</span><span class="p">((</span><span class="mi">0</span><span class="p">,</span> <span class="n">weight_bits</span><span class="p">),</span> <span class="n">name</span><span class="o">=</span><span class="s">'wb'</span><span class="p">)</span>
+
+
+<span class="n">tvm</span><span class="o">.</span><span class="n">compute</span><span class="p">((</span><span class="n">batch</span><span class="p">,</span> <span class="n">out_height</span><span class="p">,</span> <span class="n">out_width</span><span class="p">,</span> <span class="n">out_channel</span><span class="p">),</span> <span class="k">lambda</span> <span class="n">nn</span><span class="p">,</span> <span class="n">yy</span><span class="p">,</span> <span class="n">xx</span><spa [...]
+ <span class="n">tvm</span><span class="o">.</span><span class="nb">sum</span><span class="p">(</span><span class="n">tvm</span><span class="o">.</span><span class="n">popcount</span><span class="p">(</span>
+ <span class="n">Input_padded</span><span class="p">[</span><span class="n">nn</span><span class="p">,</span> <span class="n">yy</span> <span class="o">*</span> <span class="n">stride_h</span> <span class="o">+</span> <span class="n">ry</span><span class="p">,</span> <span class="n">xx</span> <span class="o">*</span> <span class="n">stride_w</span> <span class="o">+</span> <span class="n">rx</span><span class="p">,</span> <span class="n">rc</span><span class="p">,</span> <s [...]
+ <span class="n">Weights_bitpacked</span><span class="p">[</span><span class="n">ry</span><span class="p">,</span> <span class="n">rx</span><span class="p">,</span> <span class="n">rc</span><span class="p">,</span> <span class="n">ff</span><span class="p">,</span> <span class="n">wb</span><span class="p">]))</span> <span class="o"><<</span> <span class="p">(</span><span class="n">ib</span><span class="o">+</span><span class="n">wb</span><span class="p">)))</span><span [...]
+ <span class="n">axis</span><span class="o">=</span><span class="p">[</span><span class="n">rc</span><span class="p">,</span> <span class="n">ry</span><span class="p">,</span> <span class="n">rx</span><span class="p">,</span> <span class="n">wb</span><span class="p">,</span> <span class="n">ib</span><span class="p">]))</span>
+
+</code></pre></div></div>
+
+<p>In our schedule we apply common optimizations like vectorization and memory tiling to provide better
+memory locality and take advantage of SIMD units. Some of these optimizations such as tiling,
+require parameters that need to be tuned to for the specific microarchitecture. We expose these
+parameters as knobs to TVM and use AutoTVM to automatically tune all the parameters simultaneously.</p>
+
+<p>Finally, we can craft small microkernels to replace the innermost loop(s) of computation and schedule
+ them using TVM’s tensorize primitive. Since, compilers often produce suboptimal code, people can
+ often write short assembly sequences that are more efficient. These microkernels often take advantage
+ of new intrinsics that are being introduced to help accelerate deep learning workloads and use
+ them clever ways to improve memory accesses or reduce the number instructions required.</p>
+
+<h2 id="results">Results</h2>
+
+<h3 id="raspberry-pi">Raspberry Pi</h3>
+<p>Convolution speedups on Raspberry Pi 3B compared to 16-bit integer TVM implementation.
+Workload are convolution layers from ResNet18.</p>
+
+<p style="text-align: center"><img src="/images/low-precision/rasp-conv.png" alt="image" width="50%" /></p>
+<center> Speedup of low precision convolutions on a Raspberry Pi compared to 16-bit TVM implementation.</center>
+<p></p>
+
+<p>2-bit activation, 1-bit weight convolution speedups on Raspberry Pi 3B compared to hand optimized implementation from <a href="https://arxiv.org/pdf/1712.02427.pdf">High performance ultra-low-precision convolutions
+on mobile devices.</a>.
+Workload are convolution layers from ResNet18.</p>
+
+<p style="text-align: center"><img src="/images/low-precision/rasp-conv-2.png" alt="image" width="50%" /></p>
+<center> Speedup of 2-bit weight 1-bit activation Raspberry Pi convolutions against a hand optimized implementation.</center>
+<p></p>
+
+<h3 id="x86">x86</h3>
+
+<p>Convolution speedups on x86 compared to a 32-bit floating point TVM implementation.
+Note: x86 doesn’t support a vectorized popcount for this microarchitecture, so speedups are lower.</p>
+<p style="text-align: center"><img src="/images/low-precision/x86-conv.png" alt="image" width="50%" /></p>
+<center> Speedup of x86 low precision convolutions compared to a 32-bit floating point TVM implementation.</center>
+<p></p>
+
+<h2 id="show-me-the-code">Show me the code</h2>
+
+<ul>
+ <li><a href="https://github.com/dmlc/tvm/blob/master/topi/python/topi/nn/bitserial_conv2d.py">TOPI bitserial convolution</a></li>
+ <li><a href="https://github.com/dmlc/tvm/blob/master/topi/python/topi/arm_cpu/bitserial_conv2d.py">TOPI ARM cpu bitserial convolution</a></li>
+</ul>
+
+<h2 id="references">References</h2>
+
+<ul>
+ <li>[1] <a href="https://arxiv.org/abs/1810.11066">Automating Generation of Low Precision Deep Learning Operators</a></li>
+ <li>[2] <a href="https://arxiv.org/abs/1603.05279">XNOR-Net</a></li>
+ <li>[3] <a href="https://arxiv.org/abs/1702.00953">HWGQ</a></li>
+ <li>[4] <a href="https://arxiv.org/abs/1606.06160">DoReFa</a></li>
+</ul>
+
+
+ </div>
+ </div>
+</div>
+</div>
+
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+ Apache TVM is an effort undergoing incubation at The Apache Software Foundation (ASF),
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