You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by "raiden00pl (via GitHub)" <gi...@apache.org> on 2023/08/21 11:11:31 UTC
[GitHub] [nuttx] raiden00pl commented on a diff in pull request #10328: arch/stm32h7: add CM4 core support
raiden00pl commented on code in PR #10328:
URL: https://github.com/apache/nuttx/pull/10328#discussion_r1299967567
##########
arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h:
##########
@@ -60,10 +60,18 @@
#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */
#define STM32_AXISRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System AXI SRAM */
-#define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x3001ffff: System SRAM1 */
-#define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */
-#define STM32_SRAM3_BASE 0x3004c000 /* 0x30040000-0x30047fff: System SRAM3 */
-#define STM32_SRAM123_BASE 0x30000000 /* 0x30000000-0x30047fff: System SRAM123 */
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
Review Comment:
From RM0399 -> 2.4 Embedded SRAM:
```
The AHB SRAMs of the D2 domain are also aliased to an address range below
0x2000 0000 to maintain the Cortex®-M4 Harvard architecture:
•AHB SRAM1 also mapped at address 0x1000 0000 and accessible by all system
masters through D2 domain AHB matrix
•AHB SRAM2 also mapped at address 0x1002 0000 and accessible by all system
masters through D2 domain AHB matrix
•AHB SRAM3 also mapped at address 0x1004 0000 and accessible by all system
masters through D2 domain AHB matrix
```
##########
arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h:
##########
@@ -60,10 +60,18 @@
#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */
#define STM32_AXISRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System AXI SRAM */
-#define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x3001ffff: System SRAM1 */
-#define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */
-#define STM32_SRAM3_BASE 0x3004c000 /* 0x30040000-0x30047fff: System SRAM3 */
-#define STM32_SRAM123_BASE 0x30000000 /* 0x30000000-0x30047fff: System SRAM123 */
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
Review Comment:
From RM0399 -> 2.4 Embedded SRAM:
```
The AHB SRAMs of the D2 domain are also aliased to an address range below
0x2000 0000 to maintain the Cortex®-M4 Harvard architecture:
•AHB SRAM1 also mapped at address 0x1000 0000 and accessible by all system
masters through D2 domain AHB matrix
•AHB SRAM2 also mapped at address 0x1002 0000 and accessible by all system
masters through D2 domain AHB matrix
•AHB SRAM3 also mapped at address 0x1004 0000 and accessible by all system
masters through D2 domain AHB matrix
```
--
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org
For queries about this service, please contact Infrastructure at:
users@infra.apache.org