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Posted to dev@mahout.apache.org by Andrew Musselman <an...@gmail.com> on 2017/04/10 16:03:15 UTC
RC
Finally settled down to where I can cut another RC; before I do, Andy are
you okay with the inequalities in all the tests?
I'll also be changing this typoed filename:
commit 3d0c271df2713f125a435f30f399a6865f87636b
Author: Andrew Palumbo <ap...@apache.org>
Date: Sat Apr 1 19:54:51 2017 -0700
[noJira] flip signs in SparseSparseDrmTimere.mscala example
Re: RC
Posted by Andrew Musselman <an...@gmail.com>.
Oh, not worth it, no problem.
On Mon, Apr 10, 2017 at 9:16 AM, Andrew Palumbo <ap...@outlook.com> wrote:
> Well its just in the commit log that it is incorrect. Could just push an
> empty cosmetic commit so it's not the first thing that everybody sees.
>
>
>
> Sent from my Verizon Wireless 4G LTE smartphone
>
>
> -------- Original message --------
> From: Andrew Musselman <an...@gmail.com>
> Date: 04/10/2017 09:03 (GMT-08:00)
> To: dev@mahout.apache.org
> Subject: RC
>
> Finally settled down to where I can cut another RC; before I do, Andy are
> you okay with the inequalities in all the tests?
>
> I'll also be changing this typoed filename:
>
> commit 3d0c271df2713f125a435f30f399a6865f87636b
> Author: Andrew Palumbo <ap...@apache.org>
> Date: Sat Apr 1 19:54:51 2017 -0700
>
> [noJira] flip signs in SparseSparseDrmTimere.mscala example
>
RE: RC
Posted by Andrew Palumbo <ap...@outlook.com>.
Well its just in the commit log that it is incorrect. Could just push an empty cosmetic commit so it's not the first thing that everybody sees.
Sent from my Verizon Wireless 4G LTE smartphone
-------- Original message --------
From: Andrew Musselman <an...@gmail.com>
Date: 04/10/2017 09:03 (GMT-08:00)
To: dev@mahout.apache.org
Subject: RC
Finally settled down to where I can cut another RC; before I do, Andy are
you okay with the inequalities in all the tests?
I'll also be changing this typoed filename:
commit 3d0c271df2713f125a435f30f399a6865f87636b
Author: Andrew Palumbo <ap...@apache.org>
Date: Sat Apr 1 19:54:51 2017 -0700
[noJira] flip signs in SparseSparseDrmTimere.mscala example