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Posted to discuss-archive@tvm.apache.org by Eamicheal via Apache TVM Discuss <no...@discuss.tvm.ai> on 2021/11/22 19:35:51 UTC

[Apache TVM Discuss] [Questions] [VTA] Question about VTA HLS design


Hi Jake and KJK,

I am currently looking at tracing the time it takes for the data to reach the fetch, load, and compute module, Can you please support with the best approach for this?





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[Apache TVM Discuss] [Questions] [VTA] Question about VTA HLS design

Posted by JAEWOOK LEE via Apache TVM Discuss <no...@discuss.tvm.ai>.


Hi there. 

It's been quite a while I have worked on it, I will tell you based on what I remember.

Since VTA  is made using HLS, I have looked at how HLS translates the VTA and makes those Verilog files.

Using that information, I have put debug flags on that Verilog file synthesized by HLS.

Since the Pynq-Z1 had so limited resources, I have ported into ZCU104 to do so.





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