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Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2018/03/01 17:45:38 UTC
[GitHub] jacobrosenthal closed pull request #861: bsp: allow override of i2c, spis and spim pins
jacobrosenthal closed pull request #861: bsp: allow override of i2c, spis and spim pins
URL: https://github.com/apache/mynewt-core/pull/861
This is a PR merged from a forked repository.
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diff --git a/hw/bsp/ada_feather_nrf52/src/hal_bsp.c b/hw/bsp/ada_feather_nrf52/src/hal_bsp.c
index 78e2dc754..d623adb96 100644
--- a/hw/bsp/ada_feather_nrf52/src/hal_bsp.c
+++ b/hw/bsp/ada_feather_nrf52/src/hal_bsp.c
@@ -79,18 +79,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 12,
- .mosi_pin = 13,
- .miso_pin = 14,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 12,
- .mosi_pin = 13,
- .miso_pin = 14,
- .ss_pin = 15,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -121,9 +121,9 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 26,
- .sda_pin = 25,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/ada_feather_nrf52/syscfg.yml b/hw/bsp/ada_feather_nrf52/syscfg.yml
index 678a1167c..377f56aa8 100644
--- a/hw/bsp/ada_feather_nrf52/syscfg.yml
+++ b/hw/bsp/ada_feather_nrf52/syscfg.yml
@@ -49,6 +49,39 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 12
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 13
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 14
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 12
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 13
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 14
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 15
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 26
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 25
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/apollo2_evb/src/hal_bsp.c b/hw/bsp/apollo2_evb/src/hal_bsp.c
index c23edbd15..bca4cbcf6 100644
--- a/hw/bsp/apollo2_evb/src/hal_bsp.c
+++ b/hw/bsp/apollo2_evb/src/hal_bsp.c
@@ -57,49 +57,49 @@ static const struct hal_bsp_mem_dump dump_cfg[] = {
#if MYNEWT_VAL(SPI_0_MASTER)
static const struct apollo2_spi_cfg hal_bsp_spi0m_cfg = {
- .sck_pin = 5,
- .mosi_pin = 7,
- .miso_pin = 6,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_1_MASTER)
static const struct apollo2_spi_cfg hal_bsp_spi1m_cfg = {
- .sck_pin = 8,
- .mosi_pin = 10,
- .miso_pin = 9,
+ .sck_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_2_MASTER)
static const struct apollo2_spi_cfg hal_bsp_spi2m_cfg = {
- .sck_pin = 0,
- .mosi_pin = 1,
- .miso_pin = 2,
+ .sck_pin = MYNEWT_VAL(SPI_2_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_2_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_2_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_3_MASTER)
static const struct apollo2_spi_cfg hal_bsp_spi3m_cfg = {
- .sck_pin = 42,
- .mosi_pin = 38,
- .miso_pin = 43,
+ .sck_pin = MYNEWT_VAL(SPI_3_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_3_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_3_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_4_MASTER)
static const struct apollo2_spi_cfg hal_bsp_spi4m_cfg = {
- .sck_pin = 39,
- .mosi_pin = 44,
- .miso_pin = 40,
+ .sck_pin = MYNEWT_VAL(SPI_4_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_4_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_4_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_5_MASTER)
static const struct apollo2_spi_cfg hal_bsp_spi5m_cfg = {
- .sck_pin = 48,
- .mosi_pin = 47,
- .miso_pin = 49,
+ .sck_pin = MYNEWT_VAL(SPI_5_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_5_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_5_MASTER_PIN_MISO),
};
#endif
diff --git a/hw/bsp/apollo2_evb/syscfg.yml b/hw/bsp/apollo2_evb/syscfg.yml
index 47c5f1b7a..3ee074253 100644
--- a/hw/bsp/apollo2_evb/syscfg.yml
+++ b/hw/bsp/apollo2_evb/syscfg.yml
@@ -39,6 +39,66 @@ syscfg.defs:
description: 'CTS pin for UART0'
value: 38
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 5
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 7
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 6
+
+ SPI_1_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_1_MASTER'
+ value: 8
+ SPI_1_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_MASTER'
+ value: 10
+ SPI_1_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_1_MASTER'
+ value: 9
+
+ SPI_2_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_2_MASTER'
+ value: 0
+ SPI_2_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_2_MASTER'
+ value: 1
+ SPI_2_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_2_MASTER'
+ value: 2
+
+ SPI_3_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_3_MASTER'
+ value: 42
+ SPI_3_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_3_MASTER'
+ value: 38
+ SPI_3_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_3_MASTER'
+ value: 43
+
+ SPI_4_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_4_MASTER'
+ value: 39
+ SPI_4_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_4_MASTER'
+ value: 44
+ SPI_4_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_4_MASTER'
+ value: 40
+
+ SPI_5_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_5_MASTER'
+ value: 48
+ SPI_5_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_5_MASTER'
+ value: 47
+ SPI_5_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_5_MASTER'
+ value: 49
+
syscfg.vals:
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
diff --git a/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c b/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c
index b6020560a..cd0447436 100644
--- a/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c
+++ b/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c
@@ -78,18 +78,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 24,
- .mosi_pin = 23,
- .miso_pin = 22,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 24,
- .mosi_pin = 23,
- .miso_pin = 22,
- .ss_pin = 19,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -120,9 +120,9 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 27,
- .sda_pin = 26,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/arduino_primo_nrf52/syscfg.yml b/hw/bsp/arduino_primo_nrf52/syscfg.yml
index a879c064c..ef6f9d953 100644
--- a/hw/bsp/arduino_primo_nrf52/syscfg.yml
+++ b/hw/bsp/arduino_primo_nrf52/syscfg.yml
@@ -54,6 +54,39 @@ syscfg.defs:
description: 'RX pin for UART1'
value: 5
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 24
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 23
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 22
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 24
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 23
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 22
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 19
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 27
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 26
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/bbc_microbit/src/hal_bsp.c b/hw/bsp/bbc_microbit/src/hal_bsp.c
index 4eb35ed61..7cba8f363 100644
--- a/hw/bsp/bbc_microbit/src/hal_bsp.c
+++ b/hw/bsp/bbc_microbit/src/hal_bsp.c
@@ -56,18 +56,18 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf51_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_1_SLAVE)
static const struct nrf51_hal_spi_cfg os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = 24
+ .sck_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
};
#endif
diff --git a/hw/bsp/bbc_microbit/syscfg.yml b/hw/bsp/bbc_microbit/syscfg.yml
index abac22e51..631571602 100644
--- a/hw/bsp/bbc_microbit/syscfg.yml
+++ b/hw/bsp/bbc_microbit/syscfg.yml
@@ -50,6 +50,29 @@ syscfg.defs:
description: 'reference mV in VDD if used'
value: 0
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 29
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 25
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 28
+
+ SPI_1_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_1_SLAVE'
+ value: 29
+ SPI_1_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_SLAVE'
+ value: 25
+ SPI_1_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_1_SLAVE'
+ value: 28
+ SPI_1_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_1_SLAVE'
+ value: 24
+
TIMER_0:
description: 'NRF51 Timer 0'
value: 1
diff --git a/hw/bsp/ble400/src/hal_bsp.c b/hw/bsp/ble400/src/hal_bsp.c
index 98126e9a2..dbea6bc44 100644
--- a/hw/bsp/ble400/src/hal_bsp.c
+++ b/hw/bsp/ble400/src/hal_bsp.c
@@ -55,26 +55,26 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf51_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 25,
- .mosi_pin = 24,
- .miso_pin = 23
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_1_SLAVE)
static const struct nrf51_hal_spi_cfg os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = 24
+ .sck_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
};
#endif
#if MYNEWT_VAL(I2C_0)
static const struct nrf51_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 1,
- .sda_pin = 0,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/ble400/syscfg.yml b/hw/bsp/ble400/syscfg.yml
index 2f151d553..9840f7fdd 100644
--- a/hw/bsp/ble400/syscfg.yml
+++ b/hw/bsp/ble400/syscfg.yml
@@ -50,6 +50,39 @@ syscfg.defs:
description: 'reference mV in VDD if used'
value: 0
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 25
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 24
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 23
+
+ SPI_1_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_1_SLAVE'
+ value: 29
+ SPI_1_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_SLAVE'
+ value: 25
+ SPI_1_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_1_SLAVE'
+ value: 28
+ SPI_1_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_1_SLAVE'
+ value: 24
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 1
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 0
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF51 Timer 0'
value: 1
diff --git a/hw/bsp/bmd200/src/hal_bsp.c b/hw/bsp/bmd200/src/hal_bsp.c
index 500967561..dbea6bc44 100644
--- a/hw/bsp/bmd200/src/hal_bsp.c
+++ b/hw/bsp/bmd200/src/hal_bsp.c
@@ -55,26 +55,26 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf51_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_1_SLAVE)
static const struct nrf51_hal_spi_cfg os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = 24
+ .sck_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
};
#endif
#if MYNEWT_VAL(I2C_0)
static const struct nrf51_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 7,
- .sda_pin = 30,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/bmd200/syscfg.yml b/hw/bsp/bmd200/syscfg.yml
index 409187d98..16ece2a4a 100644
--- a/hw/bsp/bmd200/syscfg.yml
+++ b/hw/bsp/bmd200/syscfg.yml
@@ -50,6 +50,39 @@ syscfg.defs:
description: 'reference mV in VDD if used'
value: 0
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 29
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 25
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 28
+
+ SPI_1_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_1_SLAVE'
+ value: 29
+ SPI_1_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_SLAVE'
+ value: 25
+ SPI_1_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_1_SLAVE'
+ value: 28
+ SPI_1_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_1_SLAVE'
+ value: 24
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 7
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 30
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF51 Timer 0'
value: 1
diff --git a/hw/bsp/bmd300eval/src/hal_bsp.c b/hw/bsp/bmd300eval/src/hal_bsp.c
index 4b1d54142..7ffbfaf67 100644
--- a/hw/bsp/bmd300eval/src/hal_bsp.c
+++ b/hw/bsp/bmd300eval/src/hal_bsp.c
@@ -76,18 +76,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .ssn_pin = 22,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
diff --git a/hw/bsp/bmd300eval/syscfg.yml b/hw/bsp/bmd300eval/syscfg.yml
index 9c4de8894..ba2435dbc 100644
--- a/hw/bsp/bmd300eval/syscfg.yml
+++ b/hw/bsp/bmd300eval/syscfg.yml
@@ -50,6 +50,29 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 23
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 24
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 25
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 23
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 24
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 25
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 22
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/nina-b1/src/hal_bsp.c b/hw/bsp/nina-b1/src/hal_bsp.c
index b29adecf0..e86d5236e 100644
--- a/hw/bsp/nina-b1/src/hal_bsp.c
+++ b/hw/bsp/nina-b1/src/hal_bsp.c
@@ -79,18 +79,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .ss_pin = 22,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -121,9 +121,9 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 27,
- .sda_pin = 26,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/nina-b1/syscfg.yml b/hw/bsp/nina-b1/syscfg.yml
index ba028dfb1..5beffc68f 100644
--- a/hw/bsp/nina-b1/syscfg.yml
+++ b/hw/bsp/nina-b1/syscfg.yml
@@ -49,6 +49,39 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 23
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 24
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 25
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 23
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 24
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 25
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 22
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 27
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 26
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/nrf51-arduino_101/src/hal_bsp.c b/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
index 1f0ca2d8f..55b646c81 100644
--- a/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
+++ b/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
@@ -57,18 +57,18 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf51_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_1_SLAVE)
static const struct nrf51_hal_spi_cfg os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = 24
+ .sck_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
};
#endif
diff --git a/hw/bsp/nrf51-arduino_101/syscfg.yml b/hw/bsp/nrf51-arduino_101/syscfg.yml
index a9debfe77..352f2bb0a 100644
--- a/hw/bsp/nrf51-arduino_101/syscfg.yml
+++ b/hw/bsp/nrf51-arduino_101/syscfg.yml
@@ -50,6 +50,29 @@ syscfg.defs:
description: 'reference mV in VDD if used'
value: 0
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 29
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 25
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 28
+
+ SPI_1_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_1_SLAVE'
+ value: 29
+ SPI_1_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_SLAVE'
+ value: 25
+ SPI_1_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_1_SLAVE'
+ value: 28
+ SPI_1_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_1_SLAVE'
+ value: 24
+
TIMER_0:
description: 'NRF51 Timer 0'
value: 1
diff --git a/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c b/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c
index 0d28e71ac..e286f6a7e 100644
--- a/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c
+++ b/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c
@@ -54,27 +54,27 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
* NOTE: Our HAL expects that the SS pin, if used, is treated as a gpio line
* and is handled outside the SPI routines.
*/
-static const struct nrf51_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28
+static const struct nrf51_hal_spi_cfg os_bsp_spi0m_cfg = {
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_1_SLAVE)
static const struct nrf51_hal_spi_cfg os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = 24
+ .sck_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
};
#endif
#if MYNEWT_VAL(I2C_0)
static const struct nrf51_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 7,
- .sda_pin = 30,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/nrf51dk-16kbram/syscfg.yml b/hw/bsp/nrf51dk-16kbram/syscfg.yml
index 68d8ca73e..22f965e28 100644
--- a/hw/bsp/nrf51dk-16kbram/syscfg.yml
+++ b/hw/bsp/nrf51dk-16kbram/syscfg.yml
@@ -50,6 +50,40 @@ syscfg.defs:
description: 'reference mV in VDD if used'
value: 0
+
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 29
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 25
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 28
+
+ SPI_1_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_1_SLAVE'
+ value: 29
+ SPI_1_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_SLAVE'
+ value: 25
+ SPI_1_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_1_SLAVE'
+ value: 28
+ SPI_1_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_1_SLAVE'
+ value: 24
+
+ I2C_0_SDA_PIN:
+ description: 'Data pin for I2C0'
+ value: 30
+ I2C_0_SCL_PIN:
+ description: 'Clock pin for I2C0'
+ value: 7
+ I2C_0_FREQUENCY:
+ description: 'Bus frequency in KHz for I2C0'
+ value: 100
+
TIMER_0:
description: 'NRF51 Timer 0'
value: 1
diff --git a/hw/bsp/nrf51dk/src/hal_bsp.c b/hw/bsp/nrf51dk/src/hal_bsp.c
index 76c0bf38e..42f7de050 100644
--- a/hw/bsp/nrf51dk/src/hal_bsp.c
+++ b/hw/bsp/nrf51dk/src/hal_bsp.c
@@ -60,26 +60,26 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf51_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_1_SLAVE)
static const struct nrf51_hal_spi_cfg os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = 24
+ .sck_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
};
#endif
#if MYNEWT_VAL(I2C_0)
static const struct nrf51_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 7,
- .sda_pin = 30,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/nrf51dk/syscfg.yml b/hw/bsp/nrf51dk/syscfg.yml
index a87bfb009..c3d5a6386 100644
--- a/hw/bsp/nrf51dk/syscfg.yml
+++ b/hw/bsp/nrf51dk/syscfg.yml
@@ -49,6 +49,38 @@ syscfg.defs:
ADC_0_REFMV_VDD:
description: 'reference mV in VDD if used'
value: 0
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 29
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 25
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 28
+
+ SPI_1_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_1_SLAVE'
+ value: 29
+ SPI_1_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_SLAVE'
+ value: 25
+ SPI_1_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_1_SLAVE'
+ value: 28
+ SPI_1_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_1_SLAVE'
+ value: 24
+
+ I2C_0_SDA_PIN:
+ description: 'Data pin for I2C0'
+ value: 30
+ I2C_0_SCL_PIN:
+ description: 'Clock pin for I2C0'
+ value: 7
+ I2C_0_FREQUENCY:
+ description: 'Bus frequency in KHz for I2C0'
+ value: 100
TIMER_0:
description: 'NRF51 Timer 0'
diff --git a/hw/bsp/nrf52-thingy/src/hal_bsp.c b/hw/bsp/nrf52-thingy/src/hal_bsp.c
index f96773e7a..ef912b3d3 100644
--- a/hw/bsp/nrf52-thingy/src/hal_bsp.c
+++ b/hw/bsp/nrf52-thingy/src/hal_bsp.c
@@ -85,18 +85,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .ss_pin = 22,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -118,9 +118,9 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 15,
- .sda_pin = 14,
- .i2c_frequency = 400 /* 400 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#if MYNEWT_VAL(LIS2DH12_ONB)
diff --git a/hw/bsp/nrf52-thingy/syscfg.yml b/hw/bsp/nrf52-thingy/syscfg.yml
index f2094e1e4..641bf93b7 100644
--- a/hw/bsp/nrf52-thingy/syscfg.yml
+++ b/hw/bsp/nrf52-thingy/syscfg.yml
@@ -49,6 +49,39 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 23
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 24
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 25
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 23
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 24
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 25
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 22
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 15
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 14
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 400
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/nrf52840pdk/src/hal_bsp.c b/hw/bsp/nrf52840pdk/src/hal_bsp.c
index fecb1db32..29fdb42b7 100644
--- a/hw/bsp/nrf52840pdk/src/hal_bsp.c
+++ b/hw/bsp/nrf52840pdk/src/hal_bsp.c
@@ -75,18 +75,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 45,
- .mosi_pin = 46,
- .miso_pin = 47,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 45,
- .mosi_pin = 46,
- .miso_pin = 47,
- .ss_pin = 44,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -121,9 +121,9 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c0_cfg = {
- .scl_pin = 27,
- .sda_pin = 26,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/nrf52840pdk/syscfg.yml b/hw/bsp/nrf52840pdk/syscfg.yml
index dc38dd5d6..221a0dbd4 100644
--- a/hw/bsp/nrf52840pdk/syscfg.yml
+++ b/hw/bsp/nrf52840pdk/syscfg.yml
@@ -49,6 +49,39 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 45
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 46
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 47
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 45
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 46
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 47
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 44
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 27
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 26
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF52840 Timer 0'
value: 1
diff --git a/hw/bsp/nrf52dk/src/hal_bsp.c b/hw/bsp/nrf52dk/src/hal_bsp.c
index 3d341c1da..11d117796 100644
--- a/hw/bsp/nrf52dk/src/hal_bsp.c
+++ b/hw/bsp/nrf52dk/src/hal_bsp.c
@@ -79,18 +79,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .ss_pin = 22,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -121,9 +121,9 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 27,
- .sda_pin = 26,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/nrf52dk/syscfg.yml b/hw/bsp/nrf52dk/syscfg.yml
index 44b5a9a1a..aa59f37c0 100644
--- a/hw/bsp/nrf52dk/syscfg.yml
+++ b/hw/bsp/nrf52dk/syscfg.yml
@@ -49,6 +49,39 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 23
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 24
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 25
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 23
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 24
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 25
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 22
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 27
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 26
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/rb-blend2/src/hal_bsp.c b/hw/bsp/rb-blend2/src/hal_bsp.c
index c79f7c840..ee5b1f0cc 100644
--- a/hw/bsp/rb-blend2/src/hal_bsp.c
+++ b/hw/bsp/rb-blend2/src/hal_bsp.c
@@ -79,18 +79,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 20,
- .mosi_pin = 23,
- .miso_pin = 24,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 20,
- .mosi_pin = 23,
- .miso_pin = 24,
- .ss_pin = 22,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -121,9 +121,9 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 27,
- .sda_pin = 26,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/rb-blend2/syscfg.yml b/hw/bsp/rb-blend2/syscfg.yml
index f45ff6a72..6d3de0930 100644
--- a/hw/bsp/rb-blend2/syscfg.yml
+++ b/hw/bsp/rb-blend2/syscfg.yml
@@ -50,6 +50,39 @@ syscfg.defs:
description: 'RX pin for UART1'
value: 11
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 20
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 23
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 24
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 20
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 23
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 24
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 22
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 27
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 26
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/rb-nano2/src/hal_bsp.c b/hw/bsp/rb-nano2/src/hal_bsp.c
index 82273c56b..046c92306 100644
--- a/hw/bsp/rb-nano2/src/hal_bsp.c
+++ b/hw/bsp/rb-nano2/src/hal_bsp.c
@@ -78,18 +78,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .ss_pin = 22,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
diff --git a/hw/bsp/rb-nano2/syscfg.yml b/hw/bsp/rb-nano2/syscfg.yml
index 26ea8fa45..c0362b853 100644
--- a/hw/bsp/rb-nano2/syscfg.yml
+++ b/hw/bsp/rb-nano2/syscfg.yml
@@ -50,6 +50,29 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 23
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 24
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 25
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 23
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 24
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 25
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 22
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/ruuvi_tag_revb2/src/hal_bsp.c b/hw/bsp/ruuvi_tag_revb2/src/hal_bsp.c
index 128d6ff20..d78244a44 100644
--- a/hw/bsp/ruuvi_tag_revb2/src/hal_bsp.c
+++ b/hw/bsp/ruuvi_tag_revb2/src/hal_bsp.c
@@ -92,9 +92,9 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#if MYNEWT_VAL(BME280_ONB)
@@ -118,10 +118,10 @@ static const struct sensor_itf spi_0_itf_lis = {
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = 22,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -152,9 +152,9 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
- .scl_pin = 27,
- .sda_pin = 26,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/ruuvi_tag_revb2/syscfg.yml b/hw/bsp/ruuvi_tag_revb2/syscfg.yml
index a0809c112..12bfc8608 100644
--- a/hw/bsp/ruuvi_tag_revb2/syscfg.yml
+++ b/hw/bsp/ruuvi_tag_revb2/syscfg.yml
@@ -49,6 +49,39 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 29
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 25
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 28
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 29
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 25
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 28
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 22
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 27
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 26
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/telee02/src/hal_bsp.c b/hw/bsp/telee02/src/hal_bsp.c
index 3983bb648..cf4da0f02 100644
--- a/hw/bsp/telee02/src/hal_bsp.c
+++ b/hw/bsp/telee02/src/hal_bsp.c
@@ -80,9 +80,9 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 25,
- .mosi_pin = 23,
- .miso_pin = 24,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
diff --git a/hw/bsp/telee02/syscfg.yml b/hw/bsp/telee02/syscfg.yml
index e0404d6fa..5f437b0c1 100644
--- a/hw/bsp/telee02/syscfg.yml
+++ b/hw/bsp/telee02/syscfg.yml
@@ -49,6 +49,16 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 25
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 23
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 24
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
diff --git a/hw/bsp/vbluno51/src/hal_bsp.c b/hw/bsp/vbluno51/src/hal_bsp.c
index 252d7f199..b44de78ad 100644
--- a/hw/bsp/vbluno51/src/hal_bsp.c
+++ b/hw/bsp/vbluno51/src/hal_bsp.c
@@ -55,34 +55,34 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf51_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 28,
- .mosi_pin = 24,
- .miso_pin = 25
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_1_SLAVE)
static const struct nrf51_hal_spi_cfg os_bsp_spi1s_cfg = {
- .sck_pin = 28,
- .mosi_pin = 24,
- .miso_pin = 25,
- .ss_pin = 23
+ .sck_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
};
#endif
#if MYNEWT_VAL(I2C_0)
static const struct nrf51_hal_i2c_cfg hal_i2c0_cfg = {
- .scl_pin = 30,
- .sda_pin = 29,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
#if MYNEWT_VAL(I2C_1)
static const struct nrf51_hal_i2c_cfg hal_i2c1_cfg = {
- .scl_pin = 6,
- .sda_pin = 5,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_1_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/vbluno51/syscfg.yml b/hw/bsp/vbluno51/syscfg.yml
index c326806ab..ed3009c3a 100644
--- a/hw/bsp/vbluno51/syscfg.yml
+++ b/hw/bsp/vbluno51/syscfg.yml
@@ -50,6 +50,49 @@ syscfg.defs:
description: 'reference mV in VDD if used'
value: 0
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 28
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 24
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 25
+
+ SPI_1_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_1_SLAVE'
+ value: 28
+ SPI_1_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_SLAVE'
+ value: 24
+ SPI_1_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_1_SLAVE'
+ value: 25
+ SPI_1_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_1_SLAVE'
+ value: 23
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 30
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 29
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
+ I2C_1_PIN_SCL:
+ description: 'SCL pin for I2C_1'
+ value: 6
+ I2C_1_PIN_SDA:
+ description: 'SDA pin for I2C_1'
+ value: 5
+ I2C_1_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_1 bus'
+ value: 100
+
TIMER_0:
description: 'NRF51 Timer 0'
value: 1
diff --git a/hw/bsp/vbluno52/src/hal_bsp.c b/hw/bsp/vbluno52/src/hal_bsp.c
index 9c3a379c8..472798075 100644
--- a/hw/bsp/vbluno52/src/hal_bsp.c
+++ b/hw/bsp/vbluno52/src/hal_bsp.c
@@ -79,18 +79,18 @@ static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
* and is handled outside the SPI routines.
*/
static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
- .sck_pin = 15,
- .mosi_pin = 13,
- .miso_pin = 14,
+ .sck_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
};
#endif
#if MYNEWT_VAL(SPI_0_SLAVE)
static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
- .sck_pin = 15,
- .mosi_pin = 13,
- .miso_pin = 14,
- .ss_pin = 11,
+ .sck_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .mosi_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .miso_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .ss_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
};
#endif
@@ -121,17 +121,17 @@ static struct pwm_dev os_bsp_spwm;
#if MYNEWT_VAL(I2C_0)
static const struct nrf52_hal_i2c_cfg hal_i2c0_cfg = {
- .scl_pin = 27,
- .sda_pin = 26,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ),
};
#endif
#if MYNEWT_VAL(I2C_1)
static const struct nrf52_hal_i2c_cfg hal_i2c1_cfg = {
- .scl_pin = 31,
- .sda_pin = 30,
- .i2c_frequency = 100 /* 100 kHz */
+ .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .i2c_frequency = MYNEWT_VAL(I2C_1_FREQ_KHZ),
};
#endif
diff --git a/hw/bsp/vbluno52/syscfg.yml b/hw/bsp/vbluno52/syscfg.yml
index 73700a2e4..278296485 100644
--- a/hw/bsp/vbluno52/syscfg.yml
+++ b/hw/bsp/vbluno52/syscfg.yml
@@ -49,6 +49,49 @@ syscfg.defs:
description: 'RX pin for UART1'
value: -1
+ SPI_0_MASTER_PIN_SCK:
+ description: 'SCK pin for SPI_0_MASTER'
+ value: 15
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 13
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MISO pin for SPI_0_MASTER'
+ value: 14
+
+ SPI_0_SLAVE_PIN_SCK:
+ description: 'SCK pin for SPI_0_SLAVE'
+ value: 15
+ SPI_0_SLAVE_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_SLAVE'
+ value: 13
+ SPI_0_SLAVE_PIN_MISO:
+ description: 'MISO pin for SPI_0_SLAVE'
+ value: 14
+ SPI_0_SLAVE_PIN_SS:
+ description: 'SS pin for SPI_0_SLAVE'
+ value: 11
+
+ I2C_0_PIN_SCL:
+ description: 'SCL pin for I2C_0'
+ value: 27
+ I2C_0_PIN_SDA:
+ description: 'SDA pin for I2C_0'
+ value: 26
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
+ I2C_1_PIN_SCL:
+ description: 'SCL pin for I2C_1'
+ value: 31
+ I2C_1_PIN_SDA:
+ description: 'SDA pin for I2C_1'
+ value: 30
+ I2C_1_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_1 bus'
+ value: 100
+
TIMER_0:
description: 'NRF52 Timer 0'
value: 1
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