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Posted to commits@nuttx.apache.org by pk...@apache.org on 2022/03/09 08:16:02 UTC
[incubator-nuttx] 01/02: arch/risc-v: Correct handling of QPFPU and DPFPU
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 8dedf1d9afe90214dc521c92eddd7403d827bdff
Author: Huang Qi <hu...@xiaomi.com>
AuthorDate: Wed Mar 9 09:10:44 2022 +0800
arch/risc-v: Correct handling of QPFPU and DPFPU
If QPFPU enabled we will never enter the expected QPFPU branch since
option QPFPU depend on DPFPU.
Signed-off-by: Huang Qi <hu...@xiaomi.com>
---
arch/risc-v/include/irq.h | 6 +++---
arch/risc-v/src/common/riscv_fpu.S | 8 ++++----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h
index d3e50c0..89e172f 100644
--- a/arch/risc-v/include/irq.h
+++ b/arch/risc-v/include/irq.h
@@ -183,10 +183,10 @@
#define INT_XCPT_SIZE (INT_REG_SIZE * INT_XCPT_REGS)
#ifdef CONFIG_ARCH_RV32
-# if defined(CONFIG_ARCH_DPFPU)
-# define FPU_REG_SIZE 2
-# elif defined(CONFIG_ARCH_QPFPU)
+# if defined(CONFIG_ARCH_QPFPU)
# define FPU_REG_SIZE 4
+# elif defined(CONFIG_ARCH_DPFPU)
+# define FPU_REG_SIZE 2
# elif defined(CONFIG_ARCH_FPU)
# define FPU_REG_SIZE 1
# endif
diff --git a/arch/risc-v/src/common/riscv_fpu.S b/arch/risc-v/src/common/riscv_fpu.S
index d11cf01..ba35db2 100644
--- a/arch/risc-v/src/common/riscv_fpu.S
+++ b/arch/risc-v/src/common/riscv_fpu.S
@@ -48,12 +48,12 @@
#define FS_CLEAN 0x4000
#define FS_DIRTY 0x6000
-#if defined(CONFIG_ARCH_DPFPU)
-# define FLOAD fld
-# define FSTORE fsd
-#elif defined(CONFIG_ARCH_QPFPU)
+#if defined(CONFIG_ARCH_QPFPU)
# define FLOAD flq
# define FSTORE fsq
+#elif defined(CONFIG_ARCH_DPFPU)
+# define FLOAD fld
+# define FSTORE fsd
#else
# define FLOAD flw
# define FSTORE fsw