[GitHub] [incubator-nuttx] acassis commented on a change in pull request #2721: xtensa/esp32: Add efuse driver

[GitBox <gi...@apache.org>]

acassis commented on a change in pull request #2721:
URL: https://github.com/apache/incubator-nuttx/pull/2721#discussion_r561272506



##########
File path: arch/xtensa/src/esp32/esp32_efuse.c
##########
@@ -0,0 +1,486 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_efuse_utils.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <debug.h>
+#include <errno.h>
+#include <assert.h>
+#include <string.h>
+#include <nuttx/efuse/efuse.h>
+
+#include "xtensa.h"
+#include "esp32_efuse.h"
+#include "esp32_clockconfig.h"
+#include "hardware/efuse_reg.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define EFUSE_CONF_WRITE   0x5a5a /* eFuse_pgm_op_ena, force no rd/wr dis. */
+#define EFUSE_CONF_READ    0x5aa5 /* eFuse_read_op_ena, release force. */
+#define EFUSE_CMD_PGM      0x02   /* Command to program. */
+#define EFUSE_CMD_READ     0x01   /* Command to read. */
+
+#define MIN(a, b)          ((a) < (b) ? (a) : (b))
+
+uint32_t g_start_efuse_rdreg[4] =
+{
+  EFUSE_BLK0_RDATA0_REG,
+  EFUSE_BLK1_RDATA0_REG,
+  EFUSE_BLK2_RDATA0_REG,
+  EFUSE_BLK3_RDATA0_REG
+};
+
+uint32_t g_start_efuse_wrreg[4] =
+{
+  EFUSE_BLK0_WDATA0_REG,
+  EFUSE_BLK1_WDATA0_REG,
+  EFUSE_BLK2_WDATA0_REG,
+  EFUSE_BLK3_WDATA0_REG
+};
+
+void esp_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int esp_efuse_set_timing(void)
+{
+  uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000;
+  uint32_t clk_sel0;
+  uint32_t clk_sel1;
+  uint32_t dac_clk_div;
+
+  if (apb_freq_mhz <= 26)
+    {
+      clk_sel0 = 250;
+      clk_sel1 = 255;
+      dac_clk_div = 52;
+    }
+  else
+    {
+      if (apb_freq_mhz <= 40)
+        {
+          clk_sel0 = 160;
+          clk_sel1 = 255;
+          dac_clk_div = 80;
+        }
+      else
+        {
+          clk_sel0 = 80;
+          clk_sel1 = 128;
+          dac_clk_div = 100;
+        }
+    }
+
+  REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div);
+  REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0);
+  REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1);
+  return OK;
+}
+
+/* efuse read operation: copies data from physical efuses to efuse read
+ * registers.
+ */
+
+void esp_efuse_clear_program_regs(void)
+{
+  putreg32(EFUSE_CONF_READ, EFUSE_CONF_REG);
+}
+
+/* Burn values written to the efuse write registers */
+
+void esp_efuse_burn_efuses(void)

Review comment:
       this one is used by the efuse_lowerhalf, cannot be static




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