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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/04/14 19:02:24 UTC
[incubator-nuttx] branch master updated (88971a1 -> 11705ff)
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 88971a1 arch/arm/src/stm32f7/stm32_flash.c: Fix return value of stm32_flash_lock
new bf21c1b Risc-v: Fix the not supported options in the latest 'RISCV_TOOLCHAIN' in rv32im's Toolchain.defs.
new 7262af2 rv32im/Toolchain.defs: when 'CONFIG_ARCH_FPU' enabled, add 'f' to match and mabi.
new 38b4933 Change --start-group and '--end-group' as args.
new 957c14d Add initialization for idle task.
new 0d3691a Add fpu support.
new 11705ff Fix nxstyle issue
The 6 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/risc-v/include/rv32im/irq.h | 137 ++++++++++++++++++-
arch/risc-v/src/Makefile | 5 +-
arch/risc-v/src/common/up_initialize.c | 13 +-
arch/risc-v/src/common/up_internal.h | 35 +++--
arch/risc-v/src/rv32im/Toolchain.defs | 30 +++--
arch/risc-v/src/rv32im/up_fpu.S | 236 +++++++++++++++++++++++++++++++++
6 files changed, 431 insertions(+), 25 deletions(-)
create mode 100644 arch/risc-v/src/rv32im/up_fpu.S
[incubator-nuttx] 05/06: Add fpu support.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 0d3691a4604cddc15cb4a886a6c915e7fc5c1e9d
Author: zhongan <zh...@xiaomi.com>
AuthorDate: Thu Apr 2 11:20:20 2020 +0800
Add fpu support.
---
arch/risc-v/include/rv32im/irq.h | 129 ++++++++++++++++++-
arch/risc-v/src/common/up_internal.h | 8 ++
arch/risc-v/src/rv32im/up_fpu.S | 236 +++++++++++++++++++++++++++++++++++
3 files changed, 371 insertions(+), 2 deletions(-)
diff --git a/arch/risc-v/include/rv32im/irq.h b/arch/risc-v/include/rv32im/irq.h
index 3944d9d..567a75c 100644
--- a/arch/risc-v/include/rv32im/irq.h
+++ b/arch/risc-v/include/rv32im/irq.h
@@ -132,11 +132,63 @@
#ifdef CONFIG_ARCH_CHIP_GAP8
/* 31 registers, ePC, plus 6 loop registers */
-# define XCPTCONTEXT_REGS (32 + 6)
+# define INT_XCPT_REGS (32 + 6)
#else
-# define XCPTCONTEXT_REGS 33
+# define INT_XCPT_REGS 33
#endif
+#define INT_XCPT_SIZE (4 * INT_XCPT_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+#if defined(CONFIG_ARCH_DPFPU)
+# define FPU_REG_SIZE 2
+#elif defined(CONFIG_ARCH_QPFPU)
+# define FPU_REG_SIZE 4
+#else
+# define FPU_REG_SIZE 1
+#endif
+
+# define REG_F0_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 0)
+# define REG_F1_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 1)
+# define REG_F2_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 2)
+# define REG_F3_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 3)
+# define REG_F4_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 4)
+# define REG_F5_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 5)
+# define REG_F6_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 6)
+# define REG_F7_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 7)
+# define REG_F8_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 8)
+# define REG_F9_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 9)
+# define REG_F10_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 10)
+# define REG_F11_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 11)
+# define REG_F12_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 12)
+# define REG_F13_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 13)
+# define REG_F14_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 14)
+# define REG_F15_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 15)
+# define REG_F16_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 16)
+# define REG_F17_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 17)
+# define REG_F18_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 18)
+# define REG_F19_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 19)
+# define REG_F20_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 20)
+# define REG_F21_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 21)
+# define REG_F22_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 22)
+# define REG_F23_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 23)
+# define REG_F24_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 24)
+# define REG_F25_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 25)
+# define REG_F26_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 26)
+# define REG_F27_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 27)
+# define REG_F28_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 28)
+# define REG_F29_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 29)
+# define REG_F30_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 30)
+# define REG_F31_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 31)
+# define REG_FCSR_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 32)
+
+# define FPU_XCPT_REGS (FPU_REG_SIZE * 33)
+#else
+# define FPU_XCPT_REGS 0
+#endif
+
+#define XCPTCONTEXT_REGS (INT_XCPT_REGS + FPU_XCPT_REGS)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/* In assembly language, values have to be referenced as byte address
@@ -178,6 +230,42 @@
# define REG_X30 (4*REG_X30_NDX)
# define REG_X31 (4*REG_X31_NDX)
# define REG_INT_CTX (4*REG_INT_CTX_NDX)
+#ifdef CONFIG_ARCH_FPU
+# define REG_F0 (4*REG_F0_NDX)
+# define REG_F1 (4*REG_F1_NDX)
+# define REG_F2 (4*REG_F2_NDX)
+# define REG_F3 (4*REG_F3_NDX)
+# define REG_F4 (4*REG_F4_NDX)
+# define REG_F5 (4*REG_F5_NDX)
+# define REG_F6 (4*REG_F6_NDX)
+# define REG_F7 (4*REG_F7_NDX)
+# define REG_F8 (4*REG_F8_NDX)
+# define REG_F9 (4*REG_F9_NDX)
+# define REG_F10 (4*REG_F10_NDX)
+# define REG_F11 (4*REG_F11_NDX)
+# define REG_F12 (4*REG_F12_NDX)
+# define REG_F13 (4*REG_F13_NDX)
+# define REG_F14 (4*REG_F14_NDX)
+# define REG_F15 (4*REG_F15_NDX)
+# define REG_F16 (4*REG_F16_NDX)
+# define REG_F17 (4*REG_F17_NDX)
+# define REG_F18 (4*REG_F18_NDX)
+# define REG_F19 (4*REG_F19_NDX)
+# define REG_F20 (4*REG_F20_NDX)
+# define REG_F21 (4*REG_F21_NDX)
+# define REG_F22 (4*REG_F22_NDX)
+# define REG_F23 (4*REG_F23_NDX)
+# define REG_F24 (4*REG_F24_NDX)
+# define REG_F25 (4*REG_F25_NDX)
+# define REG_F26 (4*REG_F26_NDX)
+# define REG_F27 (4*REG_F27_NDX)
+# define REG_F28 (4*REG_F28_NDX)
+# define REG_F29 (4*REG_F29_NDX)
+# define REG_F30 (4*REG_F30_NDX)
+# define REG_F31 (4*REG_F31_NDX)
+# define REG_FCSR (4*REG_FCSR_NDX)
+#endif
+
#else
# define REG_EPC REG_EPC_NDX
# define REG_X1 REG_X1_NDX
@@ -212,6 +300,43 @@
# define REG_X30 REG_X30_NDX
# define REG_X31 REG_X31_NDX
# define REG_INT_CTX REG_INT_CTX_NDX
+
+#ifdef CONFIG_ARCH_FPU
+# define REG_F0 REG_F0_NDX
+# define REG_F1 REG_F1_NDX
+# define REG_F2 REG_F2_NDX
+# define REG_F3 REG_F3_NDX
+# define REG_F4 REG_F4_NDX
+# define REG_F5 REG_F5_NDX
+# define REG_F6 REG_F6_NDX
+# define REG_F7 REG_F7_NDX
+# define REG_F8 REG_F8_NDX
+# define REG_F9 REG_F9_NDX
+# define REG_F10 REG_F10_NDX
+# define REG_F11 REG_F11_NDX
+# define REG_F12 REG_F12_NDX
+# define REG_F13 REG_F13_NDX
+# define REG_F14 REG_F14_NDX
+# define REG_F15 REG_F15_NDX
+# define REG_F16 REG_F16_NDX
+# define REG_F17 REG_F17_NDX
+# define REG_F18 REG_F18_NDX
+# define REG_F19 REG_F19_NDX
+# define REG_F20 REG_F20_NDX
+# define REG_F21 REG_F21_NDX
+# define REG_F22 REG_F22_NDX
+# define REG_F23 REG_F23_NDX
+# define REG_F24 REG_F24_NDX
+# define REG_F25 REG_F25_NDX
+# define REG_F26 REG_F26_NDX
+# define REG_F27 REG_F27_NDX
+# define REG_F28 REG_F28_NDX
+# define REG_F29 REG_F29_NDX
+# define REG_F30 REG_F30_NDX
+# define REG_F31 REG_F31_NDX
+# define REG_FCSR REG_FCSR_NDX
+#endif
+
#endif
/* Now define more user friendly alternative name that can be used either
diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/up_internal.h
index ef9a9b2..068d05f 100644
--- a/arch/risc-v/src/common/up_internal.h
+++ b/arch/risc-v/src/common/up_internal.h
@@ -193,6 +193,14 @@ void up_sigdeliver(void);
int up_swint(int irq, FAR void *context, FAR void *arg);
uint32_t up_get_newintctx(void);
+#ifdef CONFIG_ARCH_FPU
+void up_savefpu(uint32_t *regs);
+void up_restorefpu(const uint32_t *regs);
+#else
+# define up_savefpu(regs)
+# define up_restorefpu(regs)
+#endif
+
/* Low level serial output **************************************************/
void up_lowputc(char ch);
diff --git a/arch/risc-v/src/rv32im/up_fpu.S b/arch/risc-v/src/rv32im/up_fpu.S
new file mode 100644
index 0000000..f2a9766
--- /dev/null
+++ b/arch/risc-v/src/rv32im/up_fpu.S
@@ -0,0 +1,236 @@
+/************************************************************************************
+ * arch/risc-v/src/rv32im/up_fpu.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/rv32im/irq.h>
+
+#ifdef CONFIG_ARCH_FPU
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Symbols
+ ************************************************************************************/
+
+ .globl up_fpuconfig
+ .globl up_savefpu
+ .globl up_restorefpu
+
+ .file "up_fpu.S"
+
+#define FS_MASK 0x6000
+#define FS_OFF 0x0000
+#define FS_INITIAL 0x2000
+#define FS_CLEAN 0x4000
+#define FS_DIRTY 0x6000
+
+#if defined(CONFIG_ARCH_DPFPU)
+# define FLOAD fld
+# define FSTORE fsd
+#elif defined(CONFIG_ARCH_QPFPU)
+# define FLOAD flq
+# define FSTORE fsq
+#else
+# define FLOAD flw
+# define FSTORE fsw
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: up_fpuconfig
+ *
+ * Description:
+ * init fpu
+ *
+ * C Function Prototype:
+ * void up_fpuconfig(void);
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * This function does not return anything explicitly.
+ *
+ ************************************************************************************/
+
+ .type up_fpuconfig, function
+
+up_fpuconfig:
+ li a0, FS_INITIAL
+ csrs mstatus, a0
+ csrwi fcsr, 0
+ ret
+
+/************************************************************************************
+ * Name: up_savefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), save the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void up_savefpu(uint32_t *regs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area in which to save the floating point
+ * registers
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+ .type up_savefpu, function
+
+up_savefpu:
+ lw t0, REG_INT_CTX(a0)
+ li t1, FS_MASK
+ and t2, t0, t1
+ li t1, FS_DIRTY
+ bne t2, t1, 1f
+ li t1, ~FS_MASK
+ and t0, t0, t1
+ li t1, FS_CLEAN
+ or t0, t0, t1
+ sw t0, REG_INT_CTX(a0)
+
+ /* Store all floating point registers */
+
+ FSTORE f0, REG_F0(a0)
+ FSTORE f1, REG_F1(a0)
+ FSTORE f2, REG_F2(a0)
+ FSTORE f3, REG_F3(a0)
+ FSTORE f4, REG_F4(a0)
+ FSTORE f5, REG_F5(a0)
+ FSTORE f6, REG_F6(a0)
+ FSTORE f7, REG_F7(a0)
+ FSTORE f8, REG_F8(a0)
+ FSTORE f9, REG_F9(a0)
+ FSTORE f10, REG_F10(a0)
+ FSTORE f11, REG_F11(a0)
+ FSTORE f12, REG_F12(a0)
+ FSTORE f13, REG_F13(a0)
+ FSTORE f14, REG_F14(a0)
+ FSTORE f15, REG_F15(a0)
+ FSTORE f16, REG_F16(a0)
+ FSTORE f17, REG_F17(a0)
+ FSTORE f18, REG_F18(a0)
+ FSTORE f19, REG_F19(a0)
+ FSTORE f20, REG_F20(a0)
+ FSTORE f21, REG_F21(a0)
+ FSTORE f22, REG_F22(a0)
+ FSTORE f23, REG_F23(a0)
+ FSTORE f24, REG_F24(a0)
+ FSTORE f25, REG_F25(a0)
+ FSTORE f26, REG_F26(a0)
+ FSTORE f27, REG_F27(a0)
+ FSTORE f28, REG_F28(a0)
+ FSTORE f29, REG_F29(a0)
+ FSTORE f30, REG_F30(a0)
+ FSTORE f31, REG_F31(a0)
+
+ frcsr t0
+ sw t0, REG_FCSR(a0)
+
+1:
+ ret
+
+/************************************************************************************
+ * Name: up_restorefpu
+ *
+ * Description:
+ * Given the pointer to a register save area (in A0), restore the state of the
+ * floating point registers.
+ *
+ * C Function Prototype:
+ * void up_restorefpu(const uint32_t *regs);
+ *
+ * Input Parameters:
+ * regs - A pointer to the register save area containing the floating point
+ * registers.
+ *
+ * Returned Value:
+ * This function does not return anything explicitly. However, it is called from
+ * interrupt level assembly logic that assumes that r0 is preserved.
+ *
+ ************************************************************************************/
+
+ .type up_restorefpu, function
+
+up_restorefpu:
+ lw t0, REG_INT_CTX(a0)
+ li t1, FS_MASK
+ and t2, t0, t1
+ li t1, FS_INITIAL
+ ble t2, t1, 1f
+
+ /* Load all floating point registers */
+
+ FLOAD f0, REG_F0(a0)
+ FLOAD f1, REG_F1(a0)
+ FLOAD f2, REG_F2(a0)
+ FLOAD f3, REG_F3(a0)
+ FLOAD f4, REG_F4(a0)
+ FLOAD f5, REG_F5(a0)
+ FLOAD f6, REG_F6(a0)
+ FLOAD f7, REG_F7(a0)
+ FLOAD f8, REG_F8(a0)
+ FLOAD f9, REG_F9(a0)
+ FLOAD f10, REG_F10(a0)
+ FLOAD f11, REG_F11(a0)
+ FLOAD f12, REG_F12(a0)
+ FLOAD f13, REG_F13(a0)
+ FLOAD f14, REG_F14(a0)
+ FLOAD f15, REG_F15(a0)
+ FLOAD f16, REG_F16(a0)
+ FLOAD f17, REG_F17(a0)
+ FLOAD f18, REG_F18(a0)
+ FLOAD f19, REG_F19(a0)
+ FLOAD f20, REG_F20(a0)
+ FLOAD f21, REG_F21(a0)
+ FLOAD f22, REG_F22(a0)
+ FLOAD f23, REG_F23(a0)
+ FLOAD f24, REG_F24(a0)
+ FLOAD f25, REG_F25(a0)
+ FLOAD f26, REG_F26(a0)
+ FLOAD f27, REG_F27(a0)
+ FLOAD f28, REG_F28(a0)
+ FLOAD f29, REG_F29(a0)
+ FLOAD f30, REG_F30(a0)
+ FLOAD f31, REG_F31(a0)
+
+ /* Store the floating point control and status register */
+
+ lw t0, REG_FCSR(a0)
+ fscsr t0
+
+1:
+ ret
+
+#endif /* CONFIG_ARCH_FPU */
[incubator-nuttx] 03/06: Change --start-group and '--end-group' as
args.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 38b4933e88228b767eb78268bdc52ee509b9ccb1
Author: zhongan <zh...@xiaomi.com>
AuthorDate: Tue Mar 31 19:43:31 2020 +0800
Change --start-group and '--end-group' as args.
---
arch/risc-v/src/Makefile | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/risc-v/src/Makefile b/arch/risc-v/src/Makefile
index 495f5d7..e707898 100644
--- a/arch/risc-v/src/Makefile
+++ b/arch/risc-v/src/Makefile
@@ -109,6 +109,9 @@ BIN = libarch$(LIBEXT)
LDFLAGS += $(ARCHSCRIPT)
+LDSTARTGROUP ?= --start-group
+LDENDGROUP ?= --end-group
+
EXTRA_LIBS ?=
EXTRA_LIBPATHS ?=
LINKLIBS ?=
@@ -176,7 +179,7 @@ nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
$(Q) echo "LD: nuttx"
$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \
-o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \
- --start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
+ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP)
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
$(Q) $(NM) $(NUTTX) | \
grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
[incubator-nuttx] 04/06: Add initialization for idle task.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 957c14d95ec35b8536a939a585d7891dd6862a5a
Author: zhongan <zh...@xiaomi.com>
AuthorDate: Thu Apr 2 11:21:53 2020 +0800
Add initialization for idle task.
---
arch/risc-v/src/common/up_initialize.c | 10 ++++++++++
arch/risc-v/src/common/up_internal.h | 11 +++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/risc-v/src/common/up_initialize.c b/arch/risc-v/src/common/up_initialize.c
index 142115a..21b848f 100644
--- a/arch/risc-v/src/common/up_initialize.c
+++ b/arch/risc-v/src/common/up_initialize.c
@@ -49,6 +49,7 @@
#include <arch/board/board.h>
+#include "sched/sched.h"
#include "up_arch.h"
#include "up_internal.h"
@@ -105,6 +106,8 @@ static inline void up_color_intstack(void)
void up_initialize(void)
{
+ FAR struct tcb_s *idle;
+
/* Colorize the interrupt stack */
up_color_intstack();
@@ -113,6 +116,13 @@ void up_initialize(void)
up_addregion();
+ /* Initialize the idle task stack info */
+
+ idle = this_task(); /* It should be idle task */
+ idle->stack_alloc_ptr = _END_BSS;
+ idle->adj_stack_ptr = (FAR void *)g_idle_topstack;
+ idle->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
+
/* Register devices */
#if defined(CONFIG_DEV_NULL)
diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/up_internal.h
index b28264c..ef9a9b2 100644
--- a/arch/risc-v/src/common/up_internal.h
+++ b/arch/risc-v/src/common/up_internal.h
@@ -77,6 +77,14 @@
#define up_restorestate(regs) (g_current_regs = regs)
#endif
+#define _START_TEXT &_stext
+#define _END_TEXT &_etext
+#define _START_BSS &_sbss
+#define _END_BSS &_ebss
+#define _DATA_INIT &_eronly
+#define _START_DATA &_sdata
+#define _END_DATA &_edata
+
/* Determine which (if any) console driver to use. If a console is enabled
* and no other console device is specified, then a serial console is
* assumed.
@@ -112,6 +120,7 @@ extern "C"
#define EXTERN extern
#endif
+#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_RV64GC
#ifdef CONFIG_SMP
EXTERN volatile uint64_t *g_current_regs[CONFIG_SMP_NCPUS];
@@ -153,6 +162,8 @@ EXTERN uint32_t _edata; /* End+1 of .data */
EXTERN uint32_t _sbss; /* Start of .bss */
EXTERN uint32_t _ebss; /* End+1 of .bss */
+#endif /* __ASSEMBLY__ */
+
/****************************************************************************
* Public Functions
****************************************************************************/
[incubator-nuttx] 02/06: rv32im/Toolchain.defs: when
'CONFIG_ARCH_FPU' enabled, add 'f' to match and mabi.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 7262af219f481e973e6fec592e8c546ebc6bfefd
Author: zhongan <zh...@xiaomi.com>
AuthorDate: Wed Mar 18 17:27:22 2020 +0800
rv32im/Toolchain.defs: when 'CONFIG_ARCH_FPU' enabled, add 'f' to match and mabi.
---
arch/risc-v/src/rv32im/Toolchain.defs | 30 ++++++++++++++++++++----------
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/arch/risc-v/src/rv32im/Toolchain.defs b/arch/risc-v/src/rv32im/Toolchain.defs
index c41ffe8..612959a 100644
--- a/arch/risc-v/src/rv32im/Toolchain.defs
+++ b/arch/risc-v/src/rv32im/Toolchain.defs
@@ -79,11 +79,16 @@ endif
ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGL)
CROSSDEV ?= riscv64-unknown-elf-
ARCROSSDEV ?= riscv64-unknown-elf-
-ifeq ($(CONFIG_RV32IM_HW_MULDIV),y)
- ARCHCPUFLAGS = -march=rv32im -mabi=ilp32f -mdiv
-else
- ARCHCPUFLAGS = -march=rv32im -mabi=ilp32f -mno-div
-endif
+ ifeq ($(CONFIG_ARCH_FPU),y)
+ ARCHCPUFLAGS = -march=rv32imf -mabi=ilp32f
+ else
+ ARCHCPUFLAGS = -march=rv32im -mabi=ilp32
+ endif
+ ifeq ($(CONFIG_RV32IM_HW_MULDIV),y)
+ ARCHCPUFLAGS += -mdiv
+ else
+ ARCHCPUFLAGS += -mno-div
+ endif
endif
ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGW)
@@ -92,11 +97,16 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGW)
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
WINTOOL = y
endif
-ifeq ($(CONFIG_RV32IM_HW_MULDIV),y)
- ARCHCPUFLAGS = -march=rv32im -mabi=ilp32f -mdiv
-else
- ARCHCPUFLAGS = -march=rv32im -mabi=ilp32f -mno-div
-endif
+ ifeq ($(CONFIG_ARCH_FPU),y)
+ ARCHCPUFLAGS = -march=rv32imf -mabi=ilp32f
+ else
+ ARCHCPUFLAGS = -march=rv32im -mabi=ilp32
+ endif
+ ifeq ($(CONFIG_RV32IM_HW_MULDIV),y)
+ ARCHCPUFLAGS += -mdiv
+ else
+ ARCHCPUFLAGS += -mno-div
+ endif
endif
ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RISCY)
[incubator-nuttx] 06/06: Fix nxstyle issue
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 11705ffc71f1606d0b7d7febef1f77d18762ea57
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Wed Apr 15 01:42:46 2020 +0800
Fix nxstyle issue
---
arch/risc-v/include/rv32im/irq.h | 8 +++++---
arch/risc-v/src/common/up_initialize.c | 3 ++-
arch/risc-v/src/common/up_internal.h | 16 ++++++++--------
3 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/arch/risc-v/include/rv32im/irq.h b/arch/risc-v/include/rv32im/irq.h
index 567a75c..888d160 100644
--- a/arch/risc-v/include/rv32im/irq.h
+++ b/arch/risc-v/include/rv32im/irq.h
@@ -55,7 +55,7 @@
/* Configuration ************************************************************/
-/* If this is a kernel build, how many nested system calls should we support? */
+/* How many nested system calls should we support? */
#ifndef CONFIG_SYS_NNEST
# define CONFIG_SYS_NNEST 2
@@ -66,8 +66,10 @@
#define REG_EPC_NDX 0
/* General pupose registers */
-/* $0: Zero register does not need to be saved */
-/* $1: ra (return address) */
+
+/* $0: Zero register does not need to be saved
+ * $1: ra (return address)
+ */
#define REG_X1_NDX 1
diff --git a/arch/risc-v/src/common/up_initialize.c b/arch/risc-v/src/common/up_initialize.c
index 21b848f..c6c0066 100644
--- a/arch/risc-v/src/common/up_initialize.c
+++ b/arch/risc-v/src/common/up_initialize.c
@@ -1,7 +1,8 @@
/****************************************************************************
* arch/risc-v/src/common/up_initialize.c
*
- * Copyright (C) 2007-2010, 2012-2015, 2017 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2010, 2012-2015, 2017 Gregory Nutt. All rights
+ * reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/up_internal.h
index 068d05f..4a19946 100644
--- a/arch/risc-v/src/common/up_internal.h
+++ b/arch/risc-v/src/common/up_internal.h
@@ -142,14 +142,14 @@ EXTERN uint32_t g_intstackalloc; /* Allocated stack base */
EXTERN uint32_t g_intstackbase; /* Initial top of interrupt stack */
#endif
-/* These 'addresses' of these values are setup by the linker script. They are
- * not actual uint32_t storage locations! They are only used meaningfully in the
- * following way:
+/* These 'addresses' of these values are setup by the linker script. They
+ * are not actual uint32_t storage locations! They are only used meaningfully
+ * in the following way:
*
* - The linker script defines, for example, the symbol_sdata.
* - The declareion extern uint32_t _sdata; makes C happy. C will believe
- * that the value _sdata is the address of a uint32_t variable _data (it is
- * not!).
+ * that the value _sdata is the address of a uint32_t variable _data (it
+ * is not!).
* - We can recoved the linker value then by simply taking the address of
* of _data. like: uint32_t *pdata = &_sdata;
*/
@@ -165,12 +165,12 @@ EXTERN uint32_t _ebss; /* End+1 of .bss */
#endif /* __ASSEMBLY__ */
/****************************************************************************
- * Public Functions
- ****************************************************************************/
+* Public Function Prototypes
+ ***************************************************************************/
#ifndef __ASSEMBLY__
-/* Low level initialization provided by board-level logic ******************/
+/* Low level initialization provided by board-level logic *******************/
void up_boot(void);
[incubator-nuttx] 01/06: Risc-v: Fix the not supported options in
the latest 'RISCV_TOOLCHAIN' in rv32im's Toolchain.defs.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit bf21c1b9478a9f2287ea8880a93e77f4d60889eb
Author: zhongan <zh...@xiaomi.com>
AuthorDate: Fri Mar 6 11:38:05 2020 +0800
Risc-v: Fix the not supported options in the latest 'RISCV_TOOLCHAIN' in rv32im's Toolchain.defs.
---
arch/risc-v/src/rv32im/Toolchain.defs | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/risc-v/src/rv32im/Toolchain.defs b/arch/risc-v/src/rv32im/Toolchain.defs
index 6fab514..c41ffe8 100644
--- a/arch/risc-v/src/rv32im/Toolchain.defs
+++ b/arch/risc-v/src/rv32im/Toolchain.defs
@@ -80,9 +80,9 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGL)
CROSSDEV ?= riscv64-unknown-elf-
ARCROSSDEV ?= riscv64-unknown-elf-
ifeq ($(CONFIG_RV32IM_HW_MULDIV),y)
- ARCHCPUFLAGS = -march=RV32IMXcustom -m32
+ ARCHCPUFLAGS = -march=rv32im -mabi=ilp32f -mdiv
else
- ARCHCPUFLAGS = -march=RV32IXcustom -m32
+ ARCHCPUFLAGS = -march=rv32im -mabi=ilp32f -mno-div
endif
endif
@@ -93,9 +93,9 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGW)
WINTOOL = y
endif
ifeq ($(CONFIG_RV32IM_HW_MULDIV),y)
- ARCHCPUFLAGS = -march=RV32IMXcustom -m32
+ ARCHCPUFLAGS = -march=rv32im -mabi=ilp32f -mdiv
else
- ARCHCPUFLAGS = -march=RV32IXcustom -m32
+ ARCHCPUFLAGS = -march=rv32im -mabi=ilp32f -mno-div
endif
endif