[GitHub] [tvm] multiverstack commented on a diff in pull request #12766: [TIR][Schedule] Relax cache read/write's restriction and fix unexpected behavior

[GitBox <gi...@apache.org>]

multiverstack commented on code in PR #12766:
URL: https://github.com/apache/tvm/pull/12766#discussion_r970491091


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tests/python/unittest/test_tir_schedule_cache_read_write.py:
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@@ -414,15 +432,15 @@ def cache_read_multi_consumer_target() -> None:
             with T.block("A"):
                 vi = T.axis.S(128, i * 16 + j)
                 A[vi] = 1.0
-        for j in T.grid(16):
-            with T.block("A"):
-                vi = T.axis.S(128, i * 16 + j)
-                A_global[vi] = A[vi]
         for j in T.grid(16):
             with T.block("B"):
                 vi = T.axis.S(128, i * 16 + j)
                 B[vi] = A[vi] + 1.0
 
+    for i in T.grid(128):

Review Comment:
   Thanks, indeed. but if considering a case that R-W-R a same buffer, and we want to _**cache_read**_ the second R, the 1st R should be ignored. This PR's solution is to specify the 2nd R in _**consumer_blocks**_ and ignore R if it is not in _**consumer_blocks**_. So for this test case, block("B") is ignored. Since the purpose of this case is to cache_read block("C"), the cache block seems to be more reasonable if next to block("C"). Any better solutions is welcomed.



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