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Posted to commits@mynewt.apache.org by ut...@apache.org on 2018/03/19 16:37:31 UTC
[mynewt-core] 02/04: Added support for PLL based system clock
driven by HSI for stm32f3 and stm32f7.
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 5d535a3c03a7ed8ebb685f329c24752a49d8ae6d
Author: Markus Lampert <ma...@bibi.ca>
AuthorDate: Tue Mar 13 14:47:50 2018 -0700
Added support for PLL based system clock driven by HSI for stm32f3 and stm32f7.
---
hw/bsp/nucleo-f303k8/src/hal_bsp.c | 2 +
hw/bsp/nucleo-f303k8/syscfg.yml | 1 +
hw/bsp/nucleo-f303re/src/hal_bsp.c | 2 +
hw/bsp/nucleo-f303re/syscfg.yml | 1 +
hw/bsp/stm32f3discovery/src/hal_bsp.c | 2 +
hw/bsp/stm32f767-nucleo/src/hal_bsp.c | 3 ++
hw/bsp/stm32f767-nucleo/syscfg.yml | 1 +
hw/bsp/stm32f7discovery/src/hal_bsp.c | 5 ++-
hw/mcu/stm/stm32f3xx/src/hal_system_clock.c | 50 +++++++++++++++++++++++++
hw/mcu/stm/stm32f3xx/syscfg.yml | 5 +++
hw/mcu/stm/stm32f7xx/src/hal_system_clock.c | 58 +++++++++++++++++++++++++++++
hw/mcu/stm/stm32f7xx/syscfg.yml | 5 +++
12 files changed, 134 insertions(+), 1 deletion(-)
diff --git a/hw/bsp/nucleo-f303k8/src/hal_bsp.c b/hw/bsp/nucleo-f303k8/src/hal_bsp.c
index c2447be..9213e99 100644
--- a/hw/bsp/nucleo-f303k8/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f303k8/src/hal_bsp.c
@@ -137,6 +137,8 @@ hal_bsp_init(void)
int rc;
(void)rc; /* in case there are no devices declared */
+ hal_system_clock_start();
+
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *)&hal_uart[UART_0_DEV_ID],
UART_DEV_NAME(UART_0_DEV_ID),
diff --git a/hw/bsp/nucleo-f303k8/syscfg.yml b/hw/bsp/nucleo-f303k8/syscfg.yml
index 1dbf558..2c75a58 100644
--- a/hw/bsp/nucleo-f303k8/syscfg.yml
+++ b/hw/bsp/nucleo-f303k8/syscfg.yml
@@ -35,3 +35,4 @@ syscfg.vals:
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
+ MCU_SYSCLK_PLL_HSI: 0
diff --git a/hw/bsp/nucleo-f303re/src/hal_bsp.c b/hw/bsp/nucleo-f303re/src/hal_bsp.c
index 9278163..7a4d1c5 100644
--- a/hw/bsp/nucleo-f303re/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f303re/src/hal_bsp.c
@@ -137,6 +137,8 @@ hal_bsp_init(void)
int rc;
(void)rc; /* in case there are no devices declared */
+ hal_system_clock_start();
+
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *)&hal_uart[UART_0_DEV_ID],
UART_DEV_NAME(UART_0_DEV_ID),
diff --git a/hw/bsp/nucleo-f303re/syscfg.yml b/hw/bsp/nucleo-f303re/syscfg.yml
index 1dbf558..2c75a58 100644
--- a/hw/bsp/nucleo-f303re/syscfg.yml
+++ b/hw/bsp/nucleo-f303re/syscfg.yml
@@ -35,3 +35,4 @@ syscfg.vals:
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
+ MCU_SYSCLK_PLL_HSI: 0
diff --git a/hw/bsp/stm32f3discovery/src/hal_bsp.c b/hw/bsp/stm32f3discovery/src/hal_bsp.c
index 11ad4d8..bfa4fe0 100644
--- a/hw/bsp/stm32f3discovery/src/hal_bsp.c
+++ b/hw/bsp/stm32f3discovery/src/hal_bsp.c
@@ -122,6 +122,8 @@ hal_bsp_init(void)
int rc;
(void)rc; /* in case there are no devices declared */
+ hal_system_clock_start();
+
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *)&hal_uart[0], UART_DEV_NAME,
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
diff --git a/hw/bsp/stm32f767-nucleo/src/hal_bsp.c b/hw/bsp/stm32f767-nucleo/src/hal_bsp.c
index 7630340..1435572 100644
--- a/hw/bsp/stm32f767-nucleo/src/hal_bsp.c
+++ b/hw/bsp/stm32f767-nucleo/src/hal_bsp.c
@@ -30,6 +30,7 @@
#include <hal/hal_bsp.h>
#include <hal/hal_gpio.h>
#include <hal/hal_flash_int.h>
+#include <hal/hal_system.h>
#include <hal/hal_timer.h>
#include <stm32f767xx.h>
@@ -138,6 +139,8 @@ hal_bsp_init(void)
(void)rc;
+ hal_system_clock_start();
+
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *) &hal_uart0, "uart0",
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
diff --git a/hw/bsp/stm32f767-nucleo/syscfg.yml b/hw/bsp/stm32f767-nucleo/syscfg.yml
index fb083ed..706c33e 100644
--- a/hw/bsp/stm32f767-nucleo/syscfg.yml
+++ b/hw/bsp/stm32f767-nucleo/syscfg.yml
@@ -40,3 +40,4 @@ syscfg.vals:
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
+ MCU_SYSCLK_PLL_HSI: 0
diff --git a/hw/bsp/stm32f7discovery/src/hal_bsp.c b/hw/bsp/stm32f7discovery/src/hal_bsp.c
index 5d17063..0da7f5d 100644
--- a/hw/bsp/stm32f7discovery/src/hal_bsp.c
+++ b/hw/bsp/stm32f7discovery/src/hal_bsp.c
@@ -28,8 +28,9 @@
#endif
#include <hal/hal_bsp.h>
-#include <hal/hal_gpio.h>
#include <hal/hal_flash_int.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_system.h>
#include <hal/hal_timer.h>
#include <stm32f746xx.h>
@@ -133,6 +134,8 @@ hal_bsp_init(void)
(void)rc;
+ hal_system_clock_start();
+
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *) &hal_uart0, "uart0",
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
diff --git a/hw/mcu/stm/stm32f3xx/src/hal_system_clock.c b/hw/mcu/stm/stm32f3xx/src/hal_system_clock.c
new file mode 100644
index 0000000..c339923
--- /dev/null
+++ b/hw/mcu/stm/stm32f3xx/src/hal_system_clock.c
@@ -0,0 +1,50 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <hal/hal_system.h>
+#include <mcu/cortex_m4.h>
+#include "stm32f3xx_hal.h"
+#include "stm32f3xx_hal_rcc.h"
+
+void
+hal_system_clock_start(void)
+{
+#if MYNEWT_VAL(MCU_SYSCLK_PLL_HSI)
+ RCC_OscInitTypeDef osc;
+ RCC_ClkInitTypeDef clk;
+
+ osc.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+ osc.PLL.PLLState = RCC_PLL_ON;
+ osc.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ osc.PLL.PREDIV = RCC_PREDIV_DIV2;
+#endif
+ osc.PLL.PLLMUL = RCC_PLL_MUL16;
+ osc.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ assert(HAL_OK == HAL_RCC_OscConfig(&osc));
+
+ clk.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ clk.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ clk.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ clk.APB1CLKDivider = RCC_HCLK_DIV2;
+ clk.APB2CLKDivider = RCC_HCLK_DIV1;
+ assert(HAL_OK == HAL_RCC_ClockConfig(&clk, FLASH_LATENCY_2));
+#endif
+}
diff --git a/hw/mcu/stm/stm32f3xx/syscfg.yml b/hw/mcu/stm/stm32f3xx/syscfg.yml
index f455638..8e0607b 100644
--- a/hw/mcu/stm/stm32f3xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f3xx/syscfg.yml
@@ -26,3 +26,8 @@ syscfg.defs:
MCU_STM32F3:
description: MCUs are of STM32F3xx family
value: 1
+
+ MCU_SYSCLK_PLL_HSI:
+ description: Configure PLL as sysclock driven by HSI.
+ value: 0
+
diff --git a/hw/mcu/stm/stm32f7xx/src/hal_system_clock.c b/hw/mcu/stm/stm32f7xx/src/hal_system_clock.c
new file mode 100644
index 0000000..f782a86
--- /dev/null
+++ b/hw/mcu/stm/stm32f7xx/src/hal_system_clock.c
@@ -0,0 +1,58 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "stm32f7xx_hal.h"
+#include "stm32f7xx_hal_rcc.h"
+#include <assert.h>
+#include <hal/hal_system.h>
+#include <mcu/cortex_m7.h>
+
+void
+hal_system_clock_start(void)
+{
+#if MYNEWT_VAL(MCU_SYSCLK_PLL_HSI)
+ RCC_OscInitTypeDef osc;
+ RCC_ClkInitTypeDef clk;
+
+ /*
+ * CLK_IN = HSI ... 16MHz
+ * PLL_CLK_OUT = CLK_IN / PLLM * PLLN ... 436MHz
+ * PLLCLK = PLL_CLK_OUT / PLLP ... SYSCLK
+ * PLL48CLK = PLL_CLK_OUT / PLLQ ... USB clock
+ * PLLDSICLK = PLL_CLK_OUT / PLLR ... DSI host
+ */
+ osc.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+ osc.PLL.PLLState = RCC_PLL_ON;
+ osc.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ osc.PLL.PLLM = 16;
+ osc.PLL.PLLN = 432;
+ osc.PLL.PLLP = RCC_PLLP_DIV2;
+ osc.PLL.PLLQ = 9;
+ osc.PLL.PLLR = 7;
+ osc.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ assert(HAL_OK == HAL_RCC_OscConfig(&osc));
+
+ clk.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ clk.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ clk.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ clk.APB1CLKDivider = RCC_HCLK_DIV4;
+ clk.APB2CLKDivider = RCC_HCLK_DIV2;
+ assert(HAL_OK == HAL_RCC_ClockConfig(&clk, FLASH_LATENCY_7));
+#endif
+}
diff --git a/hw/mcu/stm/stm32f7xx/syscfg.yml b/hw/mcu/stm/stm32f7xx/syscfg.yml
index cf82e27..39dc6a9 100644
--- a/hw/mcu/stm/stm32f7xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f7xx/syscfg.yml
@@ -26,3 +26,8 @@ syscfg.defs:
MCU_STM32F7:
description: MCUs are of STM32F7xx family
value: 1
+
+ MCU_SYSCLK_PLL_HSI:
+ description: Configure PLL as sysclock driven by HSI.
+ value: 0
+
--
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